1/* 2 * dts file for Xilinx ZynqMP 3 * 4 * (C) Copyright 2014 - 2015, Xilinx, Inc. 5 * 6 * Michal Simek <michal.simek@xilinx.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11/ { 12 compatible = "xlnx,zynqmp"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu@0 { 21 compatible = "arm,cortex-a53", "arm,armv8"; 22 device_type = "cpu"; 23 enable-method = "psci"; 24 reg = <0x0>; 25 cpu-idle-states = <&CPU_SLEEP_0>; 26 }; 27 28 cpu@1 { 29 compatible = "arm,cortex-a53", "arm,armv8"; 30 device_type = "cpu"; 31 enable-method = "psci"; 32 reg = <0x1>; 33 cpu-idle-states = <&CPU_SLEEP_0>; 34 }; 35 36 cpu@2 { 37 compatible = "arm,cortex-a53", "arm,armv8"; 38 device_type = "cpu"; 39 enable-method = "psci"; 40 reg = <0x2>; 41 cpu-idle-states = <&CPU_SLEEP_0>; 42 }; 43 44 cpu@3 { 45 compatible = "arm,cortex-a53", "arm,armv8"; 46 device_type = "cpu"; 47 enable-method = "psci"; 48 reg = <0x3>; 49 cpu-idle-states = <&CPU_SLEEP_0>; 50 }; 51 52 idle-states { 53 entry-mehod = "arm,psci"; 54 55 CPU_SLEEP_0: cpu-sleep-0 { 56 compatible = "arm,idle-state"; 57 arm,psci-suspend-param = <0x40000000>; 58 local-timer-stop; 59 entry-latency-us = <300>; 60 exit-latency-us = <600>; 61 min-residency-us = <800000>; 62 }; 63 }; 64 }; 65 66 dcc: dcc { 67 compatible = "arm,dcc"; 68 status = "disabled"; 69 u-boot,dm-pre-reloc; 70 }; 71 72 power-domains { 73 compatible = "xlnx,zynqmp-genpd"; 74 75 pd_usb0: pd-usb0 { 76 #power-domain-cells = <0x0>; 77 pd-id = <0x16>; 78 }; 79 80 pd_usb1: pd-usb1 { 81 #power-domain-cells = <0x0>; 82 pd-id = <0x17>; 83 }; 84 85 pd_sata: pd-sata { 86 #power-domain-cells = <0x0>; 87 pd-id = <0x1c>; 88 }; 89 90 pd_spi0: pd-spi0 { 91 #power-domain-cells = <0x0>; 92 pd-id = <0x23>; 93 }; 94 95 pd_spi1: pd-spi1 { 96 #power-domain-cells = <0x0>; 97 pd-id = <0x24>; 98 }; 99 100 pd_uart0: pd-uart0 { 101 #power-domain-cells = <0x0>; 102 pd-id = <0x21>; 103 }; 104 105 pd_uart1: pd-uart1 { 106 #power-domain-cells = <0x0>; 107 pd-id = <0x22>; 108 }; 109 110 pd_eth0: pd-eth0 { 111 #power-domain-cells = <0x0>; 112 pd-id = <0x1d>; 113 }; 114 115 pd_eth1: pd-eth1 { 116 #power-domain-cells = <0x0>; 117 pd-id = <0x1e>; 118 }; 119 120 pd_eth2: pd-eth2 { 121 #power-domain-cells = <0x0>; 122 pd-id = <0x1f>; 123 }; 124 125 pd_eth3: pd-eth3 { 126 #power-domain-cells = <0x0>; 127 pd-id = <0x20>; 128 }; 129 130 pd_i2c0: pd-i2c0 { 131 #power-domain-cells = <0x0>; 132 pd-id = <0x25>; 133 }; 134 135 pd_i2c1: pd-i2c1 { 136 #power-domain-cells = <0x0>; 137 pd-id = <0x26>; 138 }; 139 140 pd_dp: pd-dp { 141 /* fixme: what to attach to */ 142 #power-domain-cells = <0x0>; 143 pd-id = <0x29>; 144 }; 145 146 pd_gdma: pd-gdma { 147 #power-domain-cells = <0x0>; 148 pd-id = <0x2a>; 149 }; 150 151 pd_adma: pd-adma { 152 #power-domain-cells = <0x0>; 153 pd-id = <0x2b>; 154 }; 155 156 pd_ttc0: pd-ttc0 { 157 #power-domain-cells = <0x0>; 158 pd-id = <0x18>; 159 }; 160 161 pd_ttc1: pd-ttc1 { 162 #power-domain-cells = <0x0>; 163 pd-id = <0x19>; 164 }; 165 166 pd_ttc2: pd-ttc2 { 167 #power-domain-cells = <0x0>; 168 pd-id = <0x1a>; 169 }; 170 171 pd_ttc3: pd-ttc3 { 172 #power-domain-cells = <0x0>; 173 pd-id = <0x1b>; 174 }; 175 176 pd_sd0: pd-sd0 { 177 #power-domain-cells = <0x0>; 178 pd-id = <0x27>; 179 }; 180 181 pd_sd1: pd-sd1 { 182 #power-domain-cells = <0x0>; 183 pd-id = <0x28>; 184 }; 185 186 pd_nand: pd-nand { 187 #power-domain-cells = <0x0>; 188 pd-id = <0x2c>; 189 }; 190 191 pd_qspi: pd-qspi { 192 #power-domain-cells = <0x0>; 193 pd-id = <0x2d>; 194 }; 195 196 pd_gpio: pd-gpio { 197 #power-domain-cells = <0x0>; 198 pd-id = <0x2e>; 199 }; 200 201 pd_can0: pd-can0 { 202 #power-domain-cells = <0x0>; 203 pd-id = <0x2f>; 204 }; 205 206 pd_can1: pd-can1 { 207 #power-domain-cells = <0x0>; 208 pd-id = <0x30>; 209 }; 210 211 pd_pcie: pd-pcie { 212 #power-domain-cells = <0x0>; 213 pd-id = <0x3b>; 214 }; 215 216 pd_gpu: pd-gpu { 217 #power-domain-cells = <0x0>; 218 pd-id = <0x3a 0x14 0x15>; 219 }; 220 }; 221 222 pmu { 223 compatible = "arm,armv8-pmuv3"; 224 interrupt-parent = <&gic>; 225 interrupts = <0 143 4>, 226 <0 144 4>, 227 <0 145 4>, 228 <0 146 4>; 229 }; 230 231 psci { 232 compatible = "arm,psci-0.2"; 233 method = "smc"; 234 }; 235 236 firmware { 237 compatible = "xlnx,zynqmp-pm"; 238 method = "smc"; 239 }; 240 241 timer { 242 compatible = "arm,armv8-timer"; 243 interrupt-parent = <&gic>; 244 interrupts = <1 13 0xf01>, 245 <1 14 0xf01>, 246 <1 11 0xf01>, 247 <1 10 0xf01>; 248 }; 249 250 edac { 251 compatible = "arm,cortex-a53-edac"; 252 }; 253 254 pcap { 255 compatible = "xlnx,zynqmp-pcap-fpga"; 256 }; 257 258 amba_apu: amba_apu@0 { 259 compatible = "simple-bus"; 260 #address-cells = <2>; 261 #size-cells = <1>; 262 ranges = <0 0 0 0 0xffffffff>; 263 264 gic: interrupt-controller@f9010000 { 265 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 266 #interrupt-cells = <3>; 267 reg = <0x0 0xf9010000 0x10000>, 268 <0x0 0xf9020000 0x20000>, 269 <0x0 0xf9040000 0x20000>, 270 <0x0 0xf9060000 0x20000>; 271 interrupt-controller; 272 interrupt-parent = <&gic>; 273 interrupts = <1 9 0xf04>; 274 }; 275 }; 276 277 amba: amba { 278 compatible = "simple-bus"; 279 u-boot,dm-pre-reloc; 280 #address-cells = <2>; 281 #size-cells = <2>; 282 ranges; 283 284 can0: can@ff060000 { 285 compatible = "xlnx,zynq-can-1.0"; 286 status = "disabled"; 287 clock-names = "can_clk", "pclk"; 288 reg = <0x0 0xff060000 0x0 0x1000>; 289 interrupts = <0 23 4>; 290 interrupt-parent = <&gic>; 291 tx-fifo-depth = <0x40>; 292 rx-fifo-depth = <0x40>; 293 power-domains = <&pd_can0>; 294 }; 295 296 can1: can@ff070000 { 297 compatible = "xlnx,zynq-can-1.0"; 298 status = "disabled"; 299 clock-names = "can_clk", "pclk"; 300 reg = <0x0 0xff070000 0x0 0x1000>; 301 interrupts = <0 24 4>; 302 interrupt-parent = <&gic>; 303 tx-fifo-depth = <0x40>; 304 rx-fifo-depth = <0x40>; 305 power-domains = <&pd_can1>; 306 }; 307 308 cci: cci@fd6e0000 { 309 compatible = "arm,cci-400"; 310 reg = <0x0 0xfd6e0000 0x0 0x9000>; 311 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 312 #address-cells = <1>; 313 #size-cells = <1>; 314 315 pmu@9000 { 316 compatible = "arm,cci-400-pmu,r1"; 317 reg = <0x9000 0x5000>; 318 interrupt-parent = <&gic>; 319 interrupts = <0 123 4>, 320 <0 123 4>, 321 <0 123 4>, 322 <0 123 4>, 323 <0 123 4>; 324 }; 325 }; 326 327 /* GDMA */ 328 fpd_dma_chan1: dma@fd500000 { 329 status = "disabled"; 330 compatible = "xlnx,zynqmp-dma-1.0"; 331 reg = <0x0 0xfd500000 0x0 0x1000>; 332 interrupt-parent = <&gic>; 333 interrupts = <0 124 4>; 334 clock-names = "clk_main", "clk_apb"; 335 xlnx,bus-width = <128>; 336 #stream-id-cells = <1>; 337 iommus = <&smmu 0x14e8>; 338 power-domains = <&pd_gdma>; 339 }; 340 341 fpd_dma_chan2: dma@fd510000 { 342 status = "disabled"; 343 compatible = "xlnx,zynqmp-dma-1.0"; 344 reg = <0x0 0xfd510000 0x0 0x1000>; 345 interrupt-parent = <&gic>; 346 interrupts = <0 125 4>; 347 clock-names = "clk_main", "clk_apb"; 348 xlnx,bus-width = <128>; 349 #stream-id-cells = <1>; 350 iommus = <&smmu 0x14e9>; 351 power-domains = <&pd_gdma>; 352 }; 353 354 fpd_dma_chan3: dma@fd520000 { 355 status = "disabled"; 356 compatible = "xlnx,zynqmp-dma-1.0"; 357 reg = <0x0 0xfd520000 0x0 0x1000>; 358 interrupt-parent = <&gic>; 359 interrupts = <0 126 4>; 360 clock-names = "clk_main", "clk_apb"; 361 xlnx,bus-width = <128>; 362 #stream-id-cells = <1>; 363 iommus = <&smmu 0x14ea>; 364 power-domains = <&pd_gdma>; 365 }; 366 367 fpd_dma_chan4: dma@fd530000 { 368 status = "disabled"; 369 compatible = "xlnx,zynqmp-dma-1.0"; 370 reg = <0x0 0xfd530000 0x0 0x1000>; 371 interrupt-parent = <&gic>; 372 interrupts = <0 127 4>; 373 clock-names = "clk_main", "clk_apb"; 374 xlnx,bus-width = <128>; 375 #stream-id-cells = <1>; 376 iommus = <&smmu 0x14eb>; 377 power-domains = <&pd_gdma>; 378 }; 379 380 fpd_dma_chan5: dma@fd540000 { 381 status = "disabled"; 382 compatible = "xlnx,zynqmp-dma-1.0"; 383 reg = <0x0 0xfd540000 0x0 0x1000>; 384 interrupt-parent = <&gic>; 385 interrupts = <0 128 4>; 386 clock-names = "clk_main", "clk_apb"; 387 xlnx,bus-width = <128>; 388 #stream-id-cells = <1>; 389 iommus = <&smmu 0x14ec>; 390 power-domains = <&pd_gdma>; 391 }; 392 393 fpd_dma_chan6: dma@fd550000 { 394 status = "disabled"; 395 compatible = "xlnx,zynqmp-dma-1.0"; 396 reg = <0x0 0xfd550000 0x0 0x1000>; 397 interrupt-parent = <&gic>; 398 interrupts = <0 129 4>; 399 clock-names = "clk_main", "clk_apb"; 400 xlnx,bus-width = <128>; 401 #stream-id-cells = <1>; 402 iommus = <&smmu 0x14ed>; 403 power-domains = <&pd_gdma>; 404 }; 405 406 fpd_dma_chan7: dma@fd560000 { 407 status = "disabled"; 408 compatible = "xlnx,zynqmp-dma-1.0"; 409 reg = <0x0 0xfd560000 0x0 0x1000>; 410 interrupt-parent = <&gic>; 411 interrupts = <0 130 4>; 412 clock-names = "clk_main", "clk_apb"; 413 xlnx,bus-width = <128>; 414 #stream-id-cells = <1>; 415 iommus = <&smmu 0x14ee>; 416 power-domains = <&pd_gdma>; 417 }; 418 419 fpd_dma_chan8: dma@fd570000 { 420 status = "disabled"; 421 compatible = "xlnx,zynqmp-dma-1.0"; 422 reg = <0x0 0xfd570000 0x0 0x1000>; 423 interrupt-parent = <&gic>; 424 interrupts = <0 131 4>; 425 clock-names = "clk_main", "clk_apb"; 426 xlnx,bus-width = <128>; 427 #stream-id-cells = <1>; 428 iommus = <&smmu 0x14ef>; 429 power-domains = <&pd_gdma>; 430 }; 431 432 gpu: gpu@fd4b0000 { 433 status = "disabled"; 434 compatible = "arm,mali-400", "arm,mali-utgard"; 435 reg = <0x0 0xfd4b0000 0x0 0x30000>; 436 interrupt-parent = <&gic>; 437 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; 438 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; 439 power-domains = <&pd_gpu>; 440 }; 441 442 /* LPDDMA default allows only secured access. inorder to enable 443 * These dma channels, Users should ensure that these dma 444 * Channels are allowed for non secure access. 445 */ 446 lpd_dma_chan1: dma@ffa80000 { 447 status = "disabled"; 448 compatible = "xlnx,zynqmp-dma-1.0"; 449 clock-names = "clk_main", "clk_apb"; 450 reg = <0x0 0xffa80000 0x0 0x1000>; 451 interrupt-parent = <&gic>; 452 interrupts = <0 77 4>; 453 xlnx,bus-width = <64>; 454 #stream-id-cells = <1>; 455 iommus = <&smmu 0x868>; 456 power-domains = <&pd_adma>; 457 }; 458 459 lpd_dma_chan2: dma@ffa90000 { 460 status = "disabled"; 461 compatible = "xlnx,zynqmp-dma-1.0"; 462 clock-names = "clk_main", "clk_apb"; 463 reg = <0x0 0xffa90000 0x0 0x1000>; 464 interrupt-parent = <&gic>; 465 interrupts = <0 78 4>; 466 xlnx,bus-width = <64>; 467 #stream-id-cells = <1>; 468 iommus = <&smmu 0x869>; 469 power-domains = <&pd_adma>; 470 }; 471 472 lpd_dma_chan3: dma@ffaa0000 { 473 status = "disabled"; 474 compatible = "xlnx,zynqmp-dma-1.0"; 475 clock-names = "clk_main", "clk_apb"; 476 reg = <0x0 0xffaa0000 0x0 0x1000>; 477 interrupt-parent = <&gic>; 478 interrupts = <0 79 4>; 479 xlnx,bus-width = <64>; 480 #stream-id-cells = <1>; 481 iommus = <&smmu 0x86a>; 482 power-domains = <&pd_adma>; 483 }; 484 485 lpd_dma_chan4: dma@ffab0000 { 486 status = "disabled"; 487 compatible = "xlnx,zynqmp-dma-1.0"; 488 clock-names = "clk_main", "clk_apb"; 489 reg = <0x0 0xffab0000 0x0 0x1000>; 490 interrupt-parent = <&gic>; 491 interrupts = <0 80 4>; 492 xlnx,bus-width = <64>; 493 #stream-id-cells = <1>; 494 iommus = <&smmu 0x86b>; 495 power-domains = <&pd_adma>; 496 }; 497 498 lpd_dma_chan5: dma@ffac0000 { 499 status = "disabled"; 500 compatible = "xlnx,zynqmp-dma-1.0"; 501 clock-names = "clk_main", "clk_apb"; 502 reg = <0x0 0xffac0000 0x0 0x1000>; 503 interrupt-parent = <&gic>; 504 interrupts = <0 81 4>; 505 xlnx,bus-width = <64>; 506 #stream-id-cells = <1>; 507 iommus = <&smmu 0x86c>; 508 power-domains = <&pd_adma>; 509 }; 510 511 lpd_dma_chan6: dma@ffad0000 { 512 status = "disabled"; 513 compatible = "xlnx,zynqmp-dma-1.0"; 514 clock-names = "clk_main", "clk_apb"; 515 reg = <0x0 0xffad0000 0x0 0x1000>; 516 interrupt-parent = <&gic>; 517 interrupts = <0 82 4>; 518 xlnx,bus-width = <64>; 519 #stream-id-cells = <1>; 520 iommus = <&smmu 0x86d>; 521 power-domains = <&pd_adma>; 522 }; 523 524 lpd_dma_chan7: dma@ffae0000 { 525 status = "disabled"; 526 compatible = "xlnx,zynqmp-dma-1.0"; 527 clock-names = "clk_main", "clk_apb"; 528 reg = <0x0 0xffae0000 0x0 0x1000>; 529 interrupt-parent = <&gic>; 530 interrupts = <0 83 4>; 531 xlnx,bus-width = <64>; 532 #stream-id-cells = <1>; 533 iommus = <&smmu 0x86e>; 534 power-domains = <&pd_adma>; 535 }; 536 537 lpd_dma_chan8: dma@ffaf0000 { 538 status = "disabled"; 539 compatible = "xlnx,zynqmp-dma-1.0"; 540 clock-names = "clk_main", "clk_apb"; 541 reg = <0x0 0xffaf0000 0x0 0x1000>; 542 interrupt-parent = <&gic>; 543 interrupts = <0 84 4>; 544 xlnx,bus-width = <64>; 545 #stream-id-cells = <1>; 546 iommus = <&smmu 0x86f>; 547 power-domains = <&pd_adma>; 548 }; 549 550 mc: memory-controller@fd070000 { 551 compatible = "xlnx,zynqmp-ddrc-2.40a"; 552 reg = <0x0 0xfd070000 0x0 0x30000>; 553 interrupt-parent = <&gic>; 554 interrupts = <0 112 4>; 555 }; 556 557 nand0: nand@ff100000 { 558 compatible = "arasan,nfc-v3p10"; 559 status = "disabled"; 560 reg = <0x0 0xff100000 0x0 0x1000>; 561 clock-names = "clk_sys", "clk_flash"; 562 interrupt-parent = <&gic>; 563 interrupts = <0 14 4>; 564 #address-cells = <2>; 565 #size-cells = <1>; 566 #stream-id-cells = <1>; 567 iommus = <&smmu 0x872>; 568 power-domains = <&pd_nand>; 569 }; 570 571 gem0: ethernet@ff0b0000 { 572 compatible = "cdns,zynqmp-gem"; 573 status = "disabled"; 574 interrupt-parent = <&gic>; 575 interrupts = <0 57 4>, <0 57 4>; 576 reg = <0x0 0xff0b0000 0x0 0x1000>; 577 clock-names = "pclk", "hclk", "tx_clk"; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 #stream-id-cells = <1>; 581 iommus = <&smmu 0x874>; 582 power-domains = <&pd_eth0>; 583 }; 584 585 gem1: ethernet@ff0c0000 { 586 compatible = "cdns,zynqmp-gem"; 587 status = "disabled"; 588 interrupt-parent = <&gic>; 589 interrupts = <0 59 4>, <0 59 4>; 590 reg = <0x0 0xff0c0000 0x0 0x1000>; 591 clock-names = "pclk", "hclk", "tx_clk"; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 #stream-id-cells = <1>; 595 iommus = <&smmu 0x875>; 596 power-domains = <&pd_eth1>; 597 }; 598 599 gem2: ethernet@ff0d0000 { 600 compatible = "cdns,zynqmp-gem"; 601 status = "disabled"; 602 interrupt-parent = <&gic>; 603 interrupts = <0 61 4>, <0 61 4>; 604 reg = <0x0 0xff0d0000 0x0 0x1000>; 605 clock-names = "pclk", "hclk", "tx_clk"; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 #stream-id-cells = <1>; 609 iommus = <&smmu 0x876>; 610 power-domains = <&pd_eth2>; 611 }; 612 613 gem3: ethernet@ff0e0000 { 614 compatible = "cdns,zynqmp-gem"; 615 status = "disabled"; 616 interrupt-parent = <&gic>; 617 interrupts = <0 63 4>, <0 63 4>; 618 reg = <0x0 0xff0e0000 0x0 0x1000>; 619 clock-names = "pclk", "hclk", "tx_clk"; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 #stream-id-cells = <1>; 623 iommus = <&smmu 0x877>; 624 power-domains = <&pd_eth3>; 625 }; 626 627 gpio: gpio@ff0a0000 { 628 compatible = "xlnx,zynqmp-gpio-1.0"; 629 status = "disabled"; 630 #gpio-cells = <0x2>; 631 interrupt-parent = <&gic>; 632 interrupts = <0 16 4>; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 reg = <0x0 0xff0a0000 0x0 0x1000>; 636 power-domains = <&pd_gpio>; 637 }; 638 639 i2c0: i2c@ff020000 { 640 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 641 status = "disabled"; 642 interrupt-parent = <&gic>; 643 interrupts = <0 17 4>; 644 reg = <0x0 0xff020000 0x0 0x1000>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 power-domains = <&pd_i2c0>; 648 }; 649 650 i2c1: i2c@ff030000 { 651 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 652 status = "disabled"; 653 interrupt-parent = <&gic>; 654 interrupts = <0 18 4>; 655 reg = <0x0 0xff030000 0x0 0x1000>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 power-domains = <&pd_i2c1>; 659 }; 660 661 ocm: memory-controller@ff960000 { 662 compatible = "xlnx,zynqmp-ocmc-1.0"; 663 reg = <0x0 0xff960000 0x0 0x1000>; 664 interrupt-parent = <&gic>; 665 interrupts = <0 10 4>; 666 }; 667 668 pcie: pcie@fd0e0000 { 669 compatible = "xlnx,nwl-pcie-2.11"; 670 status = "disabled"; 671 #address-cells = <3>; 672 #size-cells = <2>; 673 #interrupt-cells = <1>; 674 msi-controller; 675 device_type = "pci"; 676 interrupt-parent = <&gic>; 677 interrupts = <0 118 4>, 678 <0 117 4>, 679 <0 116 4>, 680 <0 115 4>, /* MSI_1 [63...32] */ 681 <0 114 4>; /* MSI_0 [31...0] */ 682 interrupt-names = "misc","dummy","intx", "msi1", "msi0"; 683 msi-parent = <&pcie>; 684 reg = <0x0 0xfd0e0000 0x0 0x1000>, 685 <0x0 0xfd480000 0x0 0x1000>, 686 <0x80 0x00000000 0x0 0x1000000>; 687 reg-names = "breg", "pcireg", "cfg"; 688 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 689 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 690 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 691 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 692 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 693 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 694 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 695 power-domains = <&pd_pcie>; 696 pcie_intc: legacy-interrupt-controller { 697 interrupt-controller; 698 #address-cells = <0>; 699 #interrupt-cells = <1>; 700 }; 701 }; 702 703 qspi: spi@ff0f0000 { 704 compatible = "xlnx,zynqmp-qspi-1.0"; 705 status = "disabled"; 706 clock-names = "ref_clk", "pclk"; 707 interrupts = <0 15 4>; 708 interrupt-parent = <&gic>; 709 num-cs = <1>; 710 reg = <0x0 0xff0f0000 0x0 0x1000>, 711 <0x0 0xc0000000 0x0 0x8000000>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 #stream-id-cells = <1>; 715 iommus = <&smmu 0x873>; 716 power-domains = <&pd_qspi>; 717 }; 718 719 rtc: rtc@ffa60000 { 720 compatible = "xlnx,zynqmp-rtc"; 721 status = "disabled"; 722 reg = <0x0 0xffa60000 0x0 0x100>; 723 interrupt-parent = <&gic>; 724 interrupts = <0 26 4>, <0 27 4>; 725 interrupt-names = "alarm", "sec"; 726 }; 727 728 serdes: zynqmp_phy@fd400000 { 729 compatible = "xlnx,zynqmp-psgtr"; 730 status = "disabled"; 731 reg = <0x0 0xfd400000 0x0 0x40000>, 732 <0x0 0xfd3d0000 0x0 0x1000>, 733 <0x0 0xfd1a0000 0x0 0x1000>, 734 <0x0 0xff5e0000 0x0 0x1000>; 735 reg-names = "serdes", "siou", "fpd", "lpd"; 736 xlnx,tx_termination_fix; 737 lane0: lane0 { 738 #phy-cells = <4>; 739 }; 740 lane1: lane1 { 741 #phy-cells = <4>; 742 }; 743 lane2: lane2 { 744 #phy-cells = <4>; 745 }; 746 lane3: lane3 { 747 #phy-cells = <4>; 748 }; 749 }; 750 751 sata: ahci@fd0c0000 { 752 compatible = "ceva,ahci-1v84"; 753 status = "disabled"; 754 reg = <0x0 0xfd0c0000 0x0 0x2000>; 755 interrupt-parent = <&gic>; 756 interrupts = <0 133 4>; 757 power-domains = <&pd_sata>; 758 }; 759 760 sdhci0: sdhci@ff160000 { 761 u-boot,dm-pre-reloc; 762 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 763 status = "disabled"; 764 interrupt-parent = <&gic>; 765 interrupts = <0 48 4>; 766 reg = <0x0 0xff160000 0x0 0x1000>; 767 clock-names = "clk_xin", "clk_ahb"; 768 xlnx,device_id = <0>; 769 #stream-id-cells = <1>; 770 iommus = <&smmu 0x870>; 771 power-domains = <&pd_sd0>; 772 }; 773 774 sdhci1: sdhci@ff170000 { 775 u-boot,dm-pre-reloc; 776 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 777 status = "disabled"; 778 interrupt-parent = <&gic>; 779 interrupts = <0 49 4>; 780 reg = <0x0 0xff170000 0x0 0x1000>; 781 clock-names = "clk_xin", "clk_ahb"; 782 xlnx,device_id = <1>; 783 #stream-id-cells = <1>; 784 iommus = <&smmu 0x871>; 785 power-domains = <&pd_sd1>; 786 }; 787 788 smmu: smmu@fd800000 { 789 compatible = "arm,mmu-500"; 790 reg = <0x0 0xfd800000 0x0 0x20000>; 791 #iommu-cells = <1>; 792 #global-interrupts = <1>; 793 interrupt-parent = <&gic>; 794 interrupts = <0 155 4>, 795 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 796 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 797 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 798 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 799 mmu-masters = < &gem0 0x874 800 &gem1 0x875 801 &gem2 0x876 802 &gem3 0x877 803 &usb0 0x860 804 &usb1 0x861 805 &qspi 0x873 806 &lpd_dma_chan1 0x868 807 &lpd_dma_chan2 0x869 808 &lpd_dma_chan3 0x86a 809 &lpd_dma_chan4 0x86b 810 &lpd_dma_chan5 0x86c 811 &lpd_dma_chan6 0x86d 812 &lpd_dma_chan7 0x86e 813 &lpd_dma_chan8 0x86f 814 &fpd_dma_chan1 0x14e8 815 &fpd_dma_chan2 0x14e9 816 &fpd_dma_chan3 0x14ea 817 &fpd_dma_chan4 0x14eb 818 &fpd_dma_chan5 0x14ec 819 &fpd_dma_chan6 0x14ed 820 &fpd_dma_chan7 0x14ee 821 &fpd_dma_chan8 0x14ef 822 &sdhci0 0x870 823 &sdhci1 0x871 824 &nand0 0x872>; 825 }; 826 827 spi0: spi@ff040000 { 828 compatible = "cdns,spi-r1p6"; 829 status = "disabled"; 830 interrupt-parent = <&gic>; 831 interrupts = <0 19 4>; 832 reg = <0x0 0xff040000 0x0 0x1000>; 833 clock-names = "ref_clk", "pclk"; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 power-domains = <&pd_spi0>; 837 }; 838 839 spi1: spi@ff050000 { 840 compatible = "cdns,spi-r1p6"; 841 status = "disabled"; 842 interrupt-parent = <&gic>; 843 interrupts = <0 20 4>; 844 reg = <0x0 0xff050000 0x0 0x1000>; 845 clock-names = "ref_clk", "pclk"; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 power-domains = <&pd_spi1>; 849 }; 850 851 ttc0: timer@ff110000 { 852 compatible = "cdns,ttc"; 853 status = "disabled"; 854 interrupt-parent = <&gic>; 855 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 856 reg = <0x0 0xff110000 0x0 0x1000>; 857 timer-width = <32>; 858 power-domains = <&pd_ttc0>; 859 }; 860 861 ttc1: timer@ff120000 { 862 compatible = "cdns,ttc"; 863 status = "disabled"; 864 interrupt-parent = <&gic>; 865 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 866 reg = <0x0 0xff120000 0x0 0x1000>; 867 timer-width = <32>; 868 power-domains = <&pd_ttc1>; 869 }; 870 871 ttc2: timer@ff130000 { 872 compatible = "cdns,ttc"; 873 status = "disabled"; 874 interrupt-parent = <&gic>; 875 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 876 reg = <0x0 0xff130000 0x0 0x1000>; 877 timer-width = <32>; 878 power-domains = <&pd_ttc2>; 879 }; 880 881 ttc3: timer@ff140000 { 882 compatible = "cdns,ttc"; 883 status = "disabled"; 884 interrupt-parent = <&gic>; 885 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 886 reg = <0x0 0xff140000 0x0 0x1000>; 887 timer-width = <32>; 888 power-domains = <&pd_ttc3>; 889 }; 890 891 uart0: serial@ff000000 { 892 u-boot,dm-pre-reloc; 893 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 894 status = "disabled"; 895 interrupt-parent = <&gic>; 896 interrupts = <0 21 4>; 897 reg = <0x0 0xff000000 0x0 0x1000>; 898 clock-names = "uart_clk", "pclk"; 899 power-domains = <&pd_uart0>; 900 }; 901 902 uart1: serial@ff010000 { 903 u-boot,dm-pre-reloc; 904 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 905 status = "disabled"; 906 interrupt-parent = <&gic>; 907 interrupts = <0 22 4>; 908 reg = <0x0 0xff010000 0x0 0x1000>; 909 clock-names = "uart_clk", "pclk"; 910 power-domains = <&pd_uart1>; 911 }; 912 913 usb0: usb0 { 914 #address-cells = <2>; 915 #size-cells = <2>; 916 status = "disabled"; 917 compatible = "xlnx,zynqmp-dwc3"; 918 clock-names = "bus_clk", "ref_clk"; 919 clocks = <&clk125>, <&clk125>; 920 #stream-id-cells = <1>; 921 iommus = <&smmu 0x860>; 922 power-domains = <&pd_usb0>; 923 ranges; 924 925 dwc3_0: dwc3@fe200000 { 926 compatible = "snps,dwc3"; 927 status = "disabled"; 928 reg = <0x0 0xfe200000 0x0 0x40000>; 929 interrupt-parent = <&gic>; 930 interrupts = <0 65 4>; 931 /* snps,quirk-frame-length-adjustment = <0x20>; */ 932 snps,refclk_fladj; 933 }; 934 }; 935 936 usb1: usb1 { 937 #address-cells = <2>; 938 #size-cells = <2>; 939 status = "disabled"; 940 compatible = "xlnx,zynqmp-dwc3"; 941 clock-names = "bus_clk", "ref_clk"; 942 clocks = <&clk125>, <&clk125>; 943 #stream-id-cells = <1>; 944 iommus = <&smmu 0x861>; 945 power-domains = <&pd_usb1>; 946 ranges; 947 948 dwc3_1: dwc3@fe300000 { 949 compatible = "snps,dwc3"; 950 status = "disabled"; 951 reg = <0x0 0xfe300000 0x0 0x40000>; 952 interrupt-parent = <&gic>; 953 interrupts = <0 70 4>; 954 /* snps,quirk-frame-length-adjustment = <0x20>; */ 955 snps,refclk_fladj; 956 }; 957 }; 958 959 watchdog0: watchdog@fd4d0000 { 960 compatible = "cdns,wdt-r1p2"; 961 status = "disabled"; 962 interrupt-parent = <&gic>; 963 interrupts = <0 113 1>; 964 reg = <0x0 0xfd4d0000 0x0 0x1000>; 965 timeout-sec = <10>; 966 }; 967 968 xilinx_drm: xilinx_drm { 969 compatible = "xlnx,drm"; 970 status = "disabled"; 971 xlnx,encoder-slave = <&xlnx_dp>; 972 xlnx,connector-type = "DisplayPort"; 973 xlnx,dp-sub = <&xlnx_dp_sub>; 974 planes { 975 xlnx,pixel-format = "rgb565"; 976 plane0 { 977 dmas = <&xlnx_dpdma 3>; 978 dma-names = "dma0"; 979 }; 980 plane1 { 981 dmas = <&xlnx_dpdma 0>, 982 <&xlnx_dpdma 1>, 983 <&xlnx_dpdma 2>; 984 dma-names = "dma0", "dma1", "dma2"; 985 }; 986 }; 987 }; 988 989 xlnx_dp: dp@fd4a0000 { 990 compatible = "xlnx,v-dp"; 991 status = "disabled"; 992 reg = <0x0 0xfd4a0000 0x0 0x1000>; 993 interrupts = <0 119 4>; 994 interrupt-parent = <&gic>; 995 clock-names = "aclk", "aud_clk"; 996 xlnx,dp-version = "v1.2"; 997 xlnx,max-lanes = <2>; 998 xlnx,max-link-rate = <540000>; 999 xlnx,max-bpc = <16>; 1000 xlnx,enable-ycrcb; 1001 xlnx,colormetry = "rgb"; 1002 xlnx,bpc = <8>; 1003 xlnx,audio-chan = <2>; 1004 xlnx,dp-sub = <&xlnx_dp_sub>; 1005 xlnx,max-pclock-frequency = <300000>; 1006 }; 1007 1008 xlnx_dp_snd_card: dp_snd_card { 1009 compatible = "xlnx,dp-snd-card"; 1010 status = "disabled"; 1011 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; 1012 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; 1013 }; 1014 1015 xlnx_dp_snd_codec0: dp_snd_codec0 { 1016 compatible = "xlnx,dp-snd-codec"; 1017 status = "disabled"; 1018 clock-names = "aud_clk"; 1019 }; 1020 1021 xlnx_dp_snd_pcm0: dp_snd_pcm0 { 1022 compatible = "xlnx,dp-snd-pcm"; 1023 status = "disabled"; 1024 dmas = <&xlnx_dpdma 4>; 1025 dma-names = "tx"; 1026 }; 1027 1028 xlnx_dp_snd_pcm1: dp_snd_pcm1 { 1029 compatible = "xlnx,dp-snd-pcm"; 1030 status = "disabled"; 1031 dmas = <&xlnx_dpdma 5>; 1032 dma-names = "tx"; 1033 }; 1034 1035 xlnx_dp_sub: dp_sub@fd4aa000 { 1036 compatible = "xlnx,dp-sub"; 1037 status = "disabled"; 1038 reg = <0x0 0xfd4aa000 0x0 0x1000>, 1039 <0x0 0xfd4ab000 0x0 0x1000>, 1040 <0x0 0xfd4ac000 0x0 0x1000>; 1041 reg-names = "blend", "av_buf", "aud"; 1042 xlnx,output-fmt = "rgb"; 1043 xlnx,vid-fmt = "yuyv"; 1044 xlnx,gfx-fmt = "rgb565"; 1045 }; 1046 1047 xlnx_dpdma: dma@fd4c0000 { 1048 compatible = "xlnx,dpdma"; 1049 status = "disabled"; 1050 reg = <0x0 0xfd4c0000 0x0 0x1000>; 1051 interrupts = <0 122 4>; 1052 interrupt-parent = <&gic>; 1053 clock-names = "axi_clk"; 1054 dma-channels = <6>; 1055 #dma-cells = <1>; 1056 dma-video0channel { 1057 compatible = "xlnx,video0"; 1058 }; 1059 dma-video1channel { 1060 compatible = "xlnx,video1"; 1061 }; 1062 dma-video2channel { 1063 compatible = "xlnx,video2"; 1064 }; 1065 dma-graphicschannel { 1066 compatible = "xlnx,graphics"; 1067 }; 1068 dma-audio0channel { 1069 compatible = "xlnx,audio0"; 1070 }; 1071 dma-audio1channel { 1072 compatible = "xlnx,audio1"; 1073 }; 1074 }; 1075 }; 1076}; 1077