1/* 2 * dts file for Xilinx ZynqMP 3 * 4 * (C) Copyright 2014 - 2015, Xilinx, Inc. 5 * 6 * Michal Simek <michal.simek@xilinx.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11/ { 12 compatible = "xlnx,zynqmp"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu@0 { 21 compatible = "arm,cortex-a53", "arm,armv8"; 22 device_type = "cpu"; 23 enable-method = "psci"; 24 reg = <0x0>; 25 }; 26 27 cpu@1 { 28 compatible = "arm,cortex-a53", "arm,armv8"; 29 device_type = "cpu"; 30 enable-method = "psci"; 31 reg = <0x1>; 32 }; 33 34 cpu@2 { 35 compatible = "arm,cortex-a53", "arm,armv8"; 36 device_type = "cpu"; 37 enable-method = "psci"; 38 reg = <0x2>; 39 }; 40 41 cpu@3 { 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 reg = <0x3>; 46 }; 47 }; 48 49 dcc: dcc { 50 compatible = "arm,dcc"; 51 status = "disabled"; 52 u-boot,dm-pre-reloc; 53 }; 54 55 power-domains { 56 compatible = "xlnx,zynqmp-genpd"; 57 58 pd_usb0: pd-usb0 { 59 #power-domain-cells = <0x0>; 60 pd-id = <0x16>; 61 }; 62 63 pd_usb1: pd-usb1 { 64 #power-domain-cells = <0x0>; 65 pd-id = <0x17>; 66 }; 67 68 pd_sata: pd-sata { 69 #power-domain-cells = <0x0>; 70 pd-id = <0x1c>; 71 }; 72 73 pd_spi0: pd-spi0 { 74 #power-domain-cells = <0x0>; 75 pd-id = <0x23>; 76 }; 77 78 pd_spi1: pd-spi1 { 79 #power-domain-cells = <0x0>; 80 pd-id = <0x24>; 81 }; 82 83 pd_uart0: pd-uart0 { 84 #power-domain-cells = <0x0>; 85 pd-id = <0x21>; 86 }; 87 88 pd_uart1: pd-uart1 { 89 #power-domain-cells = <0x0>; 90 pd-id = <0x22>; 91 }; 92 93 pd_eth0: pd-eth0 { 94 #power-domain-cells = <0x0>; 95 pd-id = <0x1d>; 96 }; 97 98 pd_eth1: pd-eth1 { 99 #power-domain-cells = <0x0>; 100 pd-id = <0x1e>; 101 }; 102 103 pd_eth2: pd-eth2 { 104 #power-domain-cells = <0x0>; 105 pd-id = <0x1f>; 106 }; 107 108 pd_eth3: pd-eth3 { 109 #power-domain-cells = <0x0>; 110 pd-id = <0x20>; 111 }; 112 113 pd_i2c0: pd-i2c0 { 114 #power-domain-cells = <0x0>; 115 pd-id = <0x25>; 116 }; 117 118 pd_i2c1: pd-i2c1 { 119 #power-domain-cells = <0x0>; 120 pd-id = <0x26>; 121 }; 122 123 pd_dp: pd-dp { 124 /* fixme: what to attach to */ 125 #power-domain-cells = <0x0>; 126 pd-id = <0x29>; 127 }; 128 129 pd_gdma: pd-gdma { 130 #power-domain-cells = <0x0>; 131 pd-id = <0x2a>; 132 }; 133 134 pd_adma: pd-adma { 135 #power-domain-cells = <0x0>; 136 pd-id = <0x2b>; 137 }; 138 139 pd_ttc0: pd-ttc0 { 140 #power-domain-cells = <0x0>; 141 pd-id = <0x18>; 142 }; 143 144 pd_ttc1: pd-ttc1 { 145 #power-domain-cells = <0x0>; 146 pd-id = <0x19>; 147 }; 148 149 pd_ttc2: pd-ttc2 { 150 #power-domain-cells = <0x0>; 151 pd-id = <0x1a>; 152 }; 153 154 pd_ttc3: pd-ttc3 { 155 #power-domain-cells = <0x0>; 156 pd-id = <0x1b>; 157 }; 158 159 pd_sd0: pd-sd0 { 160 #power-domain-cells = <0x0>; 161 pd-id = <0x27>; 162 }; 163 164 pd_sd1: pd-sd1 { 165 #power-domain-cells = <0x0>; 166 pd-id = <0x28>; 167 }; 168 169 pd_nand: pd-nand { 170 #power-domain-cells = <0x0>; 171 pd-id = <0x2c>; 172 }; 173 174 pd_qspi: pd-qspi { 175 #power-domain-cells = <0x0>; 176 pd-id = <0x2d>; 177 }; 178 179 pd_gpio: pd-gpio { 180 #power-domain-cells = <0x0>; 181 pd-id = <0x2e>; 182 }; 183 184 pd_can0: pd-can0 { 185 #power-domain-cells = <0x0>; 186 pd-id = <0x2f>; 187 }; 188 189 pd_can1: pd-can1 { 190 #power-domain-cells = <0x0>; 191 pd-id = <0x30>; 192 }; 193 194 pd_pcie: pd-pcie { 195 #power-domain-cells = <0x0>; 196 pd-id = <0x3b>; 197 }; 198 199 pd_gpu: pd-gpu { 200 #power-domain-cells = <0x0>; 201 pd-id = <0x3a 0x14 0x15>; 202 }; 203 }; 204 205 pmu { 206 compatible = "arm,armv8-pmuv3"; 207 interrupt-parent = <&gic>; 208 interrupts = <0 143 4>, 209 <0 144 4>, 210 <0 145 4>, 211 <0 146 4>; 212 }; 213 214 psci { 215 compatible = "arm,psci-0.2"; 216 method = "smc"; 217 }; 218 219 firmware { 220 compatible = "xlnx,zynqmp-pm"; 221 method = "smc"; 222 }; 223 224 timer { 225 compatible = "arm,armv8-timer"; 226 interrupt-parent = <&gic>; 227 interrupts = <1 13 0xf01>, 228 <1 14 0xf01>, 229 <1 11 0xf01>, 230 <1 10 0xf01>; 231 }; 232 233 edac { 234 compatible = "arm,cortex-a53-edac"; 235 }; 236 237 pcap { 238 compatible = "xlnx,zynqmp-pcap-fpga"; 239 }; 240 241 amba_apu: amba_apu@0 { 242 compatible = "simple-bus"; 243 #address-cells = <2>; 244 #size-cells = <1>; 245 ranges = <0 0 0 0 0xffffffff>; 246 247 gic: interrupt-controller@f9010000 { 248 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 249 #interrupt-cells = <3>; 250 reg = <0x0 0xf9010000 0x10000>, 251 <0x0 0xf9020000 0x20000>, 252 <0x0 0xf9040000 0x20000>, 253 <0x0 0xf9060000 0x20000>; 254 interrupt-controller; 255 interrupt-parent = <&gic>; 256 interrupts = <1 9 0xf04>; 257 }; 258 }; 259 260 amba: amba { 261 compatible = "simple-bus"; 262 u-boot,dm-pre-reloc; 263 #address-cells = <2>; 264 #size-cells = <2>; 265 ranges; 266 267 can0: can@ff060000 { 268 compatible = "xlnx,zynq-can-1.0"; 269 status = "disabled"; 270 clock-names = "can_clk", "pclk"; 271 reg = <0x0 0xff060000 0x0 0x1000>; 272 interrupts = <0 23 4>; 273 interrupt-parent = <&gic>; 274 tx-fifo-depth = <0x40>; 275 rx-fifo-depth = <0x40>; 276 power-domains = <&pd_can0>; 277 }; 278 279 can1: can@ff070000 { 280 compatible = "xlnx,zynq-can-1.0"; 281 status = "disabled"; 282 clock-names = "can_clk", "pclk"; 283 reg = <0x0 0xff070000 0x0 0x1000>; 284 interrupts = <0 24 4>; 285 interrupt-parent = <&gic>; 286 tx-fifo-depth = <0x40>; 287 rx-fifo-depth = <0x40>; 288 power-domains = <&pd_can1>; 289 }; 290 291 cci: cci@fd6e0000 { 292 compatible = "arm,cci-400"; 293 reg = <0x0 0xfd6e0000 0x0 0x9000>; 294 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 295 #address-cells = <1>; 296 #size-cells = <1>; 297 298 pmu@9000 { 299 compatible = "arm,cci-400-pmu,r1"; 300 reg = <0x9000 0x5000>; 301 interrupt-parent = <&gic>; 302 interrupts = <0 123 4>, 303 <0 123 4>, 304 <0 123 4>, 305 <0 123 4>, 306 <0 123 4>; 307 }; 308 }; 309 310 /* GDMA */ 311 fpd_dma_chan1: dma@fd500000 { 312 status = "disabled"; 313 compatible = "xlnx,zynqmp-dma-1.0"; 314 reg = <0x0 0xfd500000 0x0 0x1000>; 315 interrupt-parent = <&gic>; 316 interrupts = <0 124 4>; 317 clock-names = "clk_main", "clk_apb"; 318 xlnx,bus-width = <128>; 319 #stream-id-cells = <1>; 320 iommus = <&smmu 0x14e8>; 321 power-domains = <&pd_gdma>; 322 }; 323 324 fpd_dma_chan2: dma@fd510000 { 325 status = "disabled"; 326 compatible = "xlnx,zynqmp-dma-1.0"; 327 reg = <0x0 0xfd510000 0x0 0x1000>; 328 interrupt-parent = <&gic>; 329 interrupts = <0 125 4>; 330 clock-names = "clk_main", "clk_apb"; 331 xlnx,bus-width = <128>; 332 #stream-id-cells = <1>; 333 iommus = <&smmu 0x14e9>; 334 power-domains = <&pd_gdma>; 335 }; 336 337 fpd_dma_chan3: dma@fd520000 { 338 status = "disabled"; 339 compatible = "xlnx,zynqmp-dma-1.0"; 340 reg = <0x0 0xfd520000 0x0 0x1000>; 341 interrupt-parent = <&gic>; 342 interrupts = <0 126 4>; 343 clock-names = "clk_main", "clk_apb"; 344 xlnx,bus-width = <128>; 345 #stream-id-cells = <1>; 346 iommus = <&smmu 0x14ea>; 347 power-domains = <&pd_gdma>; 348 }; 349 350 fpd_dma_chan4: dma@fd530000 { 351 status = "disabled"; 352 compatible = "xlnx,zynqmp-dma-1.0"; 353 reg = <0x0 0xfd530000 0x0 0x1000>; 354 interrupt-parent = <&gic>; 355 interrupts = <0 127 4>; 356 clock-names = "clk_main", "clk_apb"; 357 xlnx,bus-width = <128>; 358 #stream-id-cells = <1>; 359 iommus = <&smmu 0x14eb>; 360 power-domains = <&pd_gdma>; 361 }; 362 363 fpd_dma_chan5: dma@fd540000 { 364 status = "disabled"; 365 compatible = "xlnx,zynqmp-dma-1.0"; 366 reg = <0x0 0xfd540000 0x0 0x1000>; 367 interrupt-parent = <&gic>; 368 interrupts = <0 128 4>; 369 clock-names = "clk_main", "clk_apb"; 370 xlnx,bus-width = <128>; 371 #stream-id-cells = <1>; 372 iommus = <&smmu 0x14ec>; 373 power-domains = <&pd_gdma>; 374 }; 375 376 fpd_dma_chan6: dma@fd550000 { 377 status = "disabled"; 378 compatible = "xlnx,zynqmp-dma-1.0"; 379 reg = <0x0 0xfd550000 0x0 0x1000>; 380 interrupt-parent = <&gic>; 381 interrupts = <0 129 4>; 382 clock-names = "clk_main", "clk_apb"; 383 xlnx,bus-width = <128>; 384 #stream-id-cells = <1>; 385 iommus = <&smmu 0x14ed>; 386 power-domains = <&pd_gdma>; 387 }; 388 389 fpd_dma_chan7: dma@fd560000 { 390 status = "disabled"; 391 compatible = "xlnx,zynqmp-dma-1.0"; 392 reg = <0x0 0xfd560000 0x0 0x1000>; 393 interrupt-parent = <&gic>; 394 interrupts = <0 130 4>; 395 clock-names = "clk_main", "clk_apb"; 396 xlnx,bus-width = <128>; 397 #stream-id-cells = <1>; 398 iommus = <&smmu 0x14ee>; 399 power-domains = <&pd_gdma>; 400 }; 401 402 fpd_dma_chan8: dma@fd570000 { 403 status = "disabled"; 404 compatible = "xlnx,zynqmp-dma-1.0"; 405 reg = <0x0 0xfd570000 0x0 0x1000>; 406 interrupt-parent = <&gic>; 407 interrupts = <0 131 4>; 408 clock-names = "clk_main", "clk_apb"; 409 xlnx,bus-width = <128>; 410 #stream-id-cells = <1>; 411 iommus = <&smmu 0x14ef>; 412 power-domains = <&pd_gdma>; 413 }; 414 415 gpu: gpu@fd4b0000 { 416 status = "disabled"; 417 compatible = "arm,mali-400", "arm,mali-utgard"; 418 reg = <0x0 0xfd4b0000 0x0 0x30000>; 419 interrupt-parent = <&gic>; 420 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; 421 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; 422 power-domains = <&pd_gpu>; 423 }; 424 425 /* LPDDMA default allows only secured access. inorder to enable 426 * These dma channels, Users should ensure that these dma 427 * Channels are allowed for non secure access. 428 */ 429 lpd_dma_chan1: dma@ffa80000 { 430 status = "disabled"; 431 compatible = "xlnx,zynqmp-dma-1.0"; 432 clock-names = "clk_main", "clk_apb"; 433 reg = <0x0 0xffa80000 0x0 0x1000>; 434 interrupt-parent = <&gic>; 435 interrupts = <0 77 4>; 436 xlnx,bus-width = <64>; 437 #stream-id-cells = <1>; 438 iommus = <&smmu 0x868>; 439 power-domains = <&pd_adma>; 440 }; 441 442 lpd_dma_chan2: dma@ffa90000 { 443 status = "disabled"; 444 compatible = "xlnx,zynqmp-dma-1.0"; 445 clock-names = "clk_main", "clk_apb"; 446 reg = <0x0 0xffa90000 0x0 0x1000>; 447 interrupt-parent = <&gic>; 448 interrupts = <0 78 4>; 449 xlnx,bus-width = <64>; 450 #stream-id-cells = <1>; 451 iommus = <&smmu 0x869>; 452 power-domains = <&pd_adma>; 453 }; 454 455 lpd_dma_chan3: dma@ffaa0000 { 456 status = "disabled"; 457 compatible = "xlnx,zynqmp-dma-1.0"; 458 clock-names = "clk_main", "clk_apb"; 459 reg = <0x0 0xffaa0000 0x0 0x1000>; 460 interrupt-parent = <&gic>; 461 interrupts = <0 79 4>; 462 xlnx,bus-width = <64>; 463 #stream-id-cells = <1>; 464 iommus = <&smmu 0x86a>; 465 power-domains = <&pd_adma>; 466 }; 467 468 lpd_dma_chan4: dma@ffab0000 { 469 status = "disabled"; 470 compatible = "xlnx,zynqmp-dma-1.0"; 471 clock-names = "clk_main", "clk_apb"; 472 reg = <0x0 0xffab0000 0x0 0x1000>; 473 interrupt-parent = <&gic>; 474 interrupts = <0 80 4>; 475 xlnx,bus-width = <64>; 476 #stream-id-cells = <1>; 477 iommus = <&smmu 0x86b>; 478 power-domains = <&pd_adma>; 479 }; 480 481 lpd_dma_chan5: dma@ffac0000 { 482 status = "disabled"; 483 compatible = "xlnx,zynqmp-dma-1.0"; 484 clock-names = "clk_main", "clk_apb"; 485 reg = <0x0 0xffac0000 0x0 0x1000>; 486 interrupt-parent = <&gic>; 487 interrupts = <0 81 4>; 488 xlnx,bus-width = <64>; 489 #stream-id-cells = <1>; 490 iommus = <&smmu 0x86c>; 491 power-domains = <&pd_adma>; 492 }; 493 494 lpd_dma_chan6: dma@ffad0000 { 495 status = "disabled"; 496 compatible = "xlnx,zynqmp-dma-1.0"; 497 clock-names = "clk_main", "clk_apb"; 498 reg = <0x0 0xffad0000 0x0 0x1000>; 499 interrupt-parent = <&gic>; 500 interrupts = <0 82 4>; 501 xlnx,bus-width = <64>; 502 #stream-id-cells = <1>; 503 iommus = <&smmu 0x86d>; 504 power-domains = <&pd_adma>; 505 }; 506 507 lpd_dma_chan7: dma@ffae0000 { 508 status = "disabled"; 509 compatible = "xlnx,zynqmp-dma-1.0"; 510 clock-names = "clk_main", "clk_apb"; 511 reg = <0x0 0xffae0000 0x0 0x1000>; 512 interrupt-parent = <&gic>; 513 interrupts = <0 83 4>; 514 xlnx,bus-width = <64>; 515 #stream-id-cells = <1>; 516 iommus = <&smmu 0x86e>; 517 power-domains = <&pd_adma>; 518 }; 519 520 lpd_dma_chan8: dma@ffaf0000 { 521 status = "disabled"; 522 compatible = "xlnx,zynqmp-dma-1.0"; 523 clock-names = "clk_main", "clk_apb"; 524 reg = <0x0 0xffaf0000 0x0 0x1000>; 525 interrupt-parent = <&gic>; 526 interrupts = <0 84 4>; 527 xlnx,bus-width = <64>; 528 #stream-id-cells = <1>; 529 iommus = <&smmu 0x86f>; 530 power-domains = <&pd_adma>; 531 }; 532 533 mc: memory-controller@fd070000 { 534 compatible = "xlnx,zynqmp-ddrc-2.40a"; 535 reg = <0x0 0xfd070000 0x0 0x30000>; 536 interrupt-parent = <&gic>; 537 interrupts = <0 112 4>; 538 }; 539 540 nand0: nand@ff100000 { 541 compatible = "arasan,nfc-v3p10"; 542 status = "disabled"; 543 reg = <0x0 0xff100000 0x0 0x1000>; 544 clock-names = "clk_sys", "clk_flash"; 545 interrupt-parent = <&gic>; 546 interrupts = <0 14 4>; 547 #address-cells = <2>; 548 #size-cells = <1>; 549 #stream-id-cells = <1>; 550 iommus = <&smmu 0x872>; 551 power-domains = <&pd_nand>; 552 }; 553 554 gem0: ethernet@ff0b0000 { 555 compatible = "cdns,zynqmp-gem"; 556 status = "disabled"; 557 interrupt-parent = <&gic>; 558 interrupts = <0 57 4>, <0 57 4>; 559 reg = <0x0 0xff0b0000 0x0 0x1000>; 560 clock-names = "pclk", "hclk", "tx_clk"; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 #stream-id-cells = <1>; 564 iommus = <&smmu 0x874>; 565 power-domains = <&pd_eth0>; 566 }; 567 568 gem1: ethernet@ff0c0000 { 569 compatible = "cdns,zynqmp-gem"; 570 status = "disabled"; 571 interrupt-parent = <&gic>; 572 interrupts = <0 59 4>, <0 59 4>; 573 reg = <0x0 0xff0c0000 0x0 0x1000>; 574 clock-names = "pclk", "hclk", "tx_clk"; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 #stream-id-cells = <1>; 578 iommus = <&smmu 0x875>; 579 power-domains = <&pd_eth1>; 580 }; 581 582 gem2: ethernet@ff0d0000 { 583 compatible = "cdns,zynqmp-gem"; 584 status = "disabled"; 585 interrupt-parent = <&gic>; 586 interrupts = <0 61 4>, <0 61 4>; 587 reg = <0x0 0xff0d0000 0x0 0x1000>; 588 clock-names = "pclk", "hclk", "tx_clk"; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 #stream-id-cells = <1>; 592 iommus = <&smmu 0x876>; 593 power-domains = <&pd_eth2>; 594 }; 595 596 gem3: ethernet@ff0e0000 { 597 compatible = "cdns,zynqmp-gem"; 598 status = "disabled"; 599 interrupt-parent = <&gic>; 600 interrupts = <0 63 4>, <0 63 4>; 601 reg = <0x0 0xff0e0000 0x0 0x1000>; 602 clock-names = "pclk", "hclk", "tx_clk"; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 #stream-id-cells = <1>; 606 iommus = <&smmu 0x877>; 607 power-domains = <&pd_eth3>; 608 }; 609 610 gpio: gpio@ff0a0000 { 611 compatible = "xlnx,zynqmp-gpio-1.0"; 612 status = "disabled"; 613 #gpio-cells = <0x2>; 614 interrupt-parent = <&gic>; 615 interrupts = <0 16 4>; 616 interrupt-controller; 617 #interrupt-cells = <2>; 618 reg = <0x0 0xff0a0000 0x0 0x1000>; 619 power-domains = <&pd_gpio>; 620 }; 621 622 i2c0: i2c@ff020000 { 623 compatible = "cdns,i2c-r1p10"; 624 status = "disabled"; 625 interrupt-parent = <&gic>; 626 interrupts = <0 17 4>; 627 reg = <0x0 0xff020000 0x0 0x1000>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 power-domains = <&pd_i2c0>; 631 }; 632 633 i2c1: i2c@ff030000 { 634 compatible = "cdns,i2c-r1p10"; 635 status = "disabled"; 636 interrupt-parent = <&gic>; 637 interrupts = <0 18 4>; 638 reg = <0x0 0xff030000 0x0 0x1000>; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 power-domains = <&pd_i2c1>; 642 }; 643 644 ocm: memory-controller@ff960000 { 645 compatible = "xlnx,zynqmp-ocmc-1.0"; 646 reg = <0x0 0xff960000 0x0 0x1000>; 647 interrupt-parent = <&gic>; 648 interrupts = <0 10 4>; 649 }; 650 651 pcie: pcie@fd0e0000 { 652 compatible = "xlnx,nwl-pcie-2.11"; 653 status = "disabled"; 654 #address-cells = <3>; 655 #size-cells = <2>; 656 #interrupt-cells = <1>; 657 msi-controller; 658 device_type = "pci"; 659 interrupt-parent = <&gic>; 660 interrupts = <0 118 4>, 661 <0 117 4>, 662 <0 116 4>, 663 <0 115 4>, /* MSI_1 [63...32] */ 664 <0 114 4>; /* MSI_0 [31...0] */ 665 interrupt-names = "misc","dummy","intx", "msi1", "msi0"; 666 msi-parent = <&pcie>; 667 reg = <0x0 0xfd0e0000 0x0 0x1000>, 668 <0x0 0xfd480000 0x0 0x1000>, 669 <0x80 0x00000000 0x0 0x1000000>; 670 reg-names = "breg", "pcireg", "cfg"; 671 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 672 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 673 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 674 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 675 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 676 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 677 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 678 power-domains = <&pd_pcie>; 679 pcie_intc: legacy-interrupt-controller { 680 interrupt-controller; 681 #address-cells = <0>; 682 #interrupt-cells = <1>; 683 }; 684 }; 685 686 qspi: spi@ff0f0000 { 687 compatible = "xlnx,zynqmp-qspi-1.0"; 688 status = "disabled"; 689 clock-names = "ref_clk", "pclk"; 690 interrupts = <0 15 4>; 691 interrupt-parent = <&gic>; 692 num-cs = <1>; 693 reg = <0x0 0xff0f0000 0x0 0x1000>, 694 <0x0 0xc0000000 0x0 0x8000000>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 #stream-id-cells = <1>; 698 iommus = <&smmu 0x873>; 699 power-domains = <&pd_qspi>; 700 }; 701 702 rtc: rtc@ffa60000 { 703 compatible = "xlnx,zynqmp-rtc"; 704 status = "disabled"; 705 reg = <0x0 0xffa60000 0x0 0x100>; 706 interrupt-parent = <&gic>; 707 interrupts = <0 26 4>, <0 27 4>; 708 interrupt-names = "alarm", "sec"; 709 }; 710 711 serdes: zynqmp_phy@fd400000 { 712 compatible = "xlnx,zynqmp-psgtr"; 713 status = "disabled"; 714 reg = <0x0 0xfd400000 0x0 0x40000>, 715 <0x0 0xfd3d0000 0x0 0x1000>, 716 <0x0 0xfd1a0000 0x0 0x1000>, 717 <0x0 0xff5e0000 0x0 0x1000>; 718 reg-names = "serdes", "siou", "fpd", "lpd"; 719 xlnx,tx_termination_fix; 720 lane0: lane0 { 721 #phy-cells = <4>; 722 }; 723 lane1: lane1 { 724 #phy-cells = <4>; 725 }; 726 lane2: lane2 { 727 #phy-cells = <4>; 728 }; 729 lane3: lane3 { 730 #phy-cells = <4>; 731 }; 732 }; 733 734 sata: ahci@fd0c0000 { 735 compatible = "ceva,ahci-1v84"; 736 status = "disabled"; 737 reg = <0x0 0xfd0c0000 0x0 0x2000>; 738 interrupt-parent = <&gic>; 739 interrupts = <0 133 4>; 740 power-domains = <&pd_sata>; 741 }; 742 743 sdhci0: sdhci@ff160000 { 744 u-boot,dm-pre-reloc; 745 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 746 status = "disabled"; 747 interrupt-parent = <&gic>; 748 interrupts = <0 48 4>; 749 reg = <0x0 0xff160000 0x0 0x1000>; 750 clock-names = "clk_xin", "clk_ahb"; 751 xlnx,device_id = <0>; 752 #stream-id-cells = <1>; 753 iommus = <&smmu 0x870>; 754 power-domains = <&pd_sd0>; 755 }; 756 757 sdhci1: sdhci@ff170000 { 758 u-boot,dm-pre-reloc; 759 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 760 status = "disabled"; 761 interrupt-parent = <&gic>; 762 interrupts = <0 49 4>; 763 reg = <0x0 0xff170000 0x0 0x1000>; 764 clock-names = "clk_xin", "clk_ahb"; 765 xlnx,device_id = <1>; 766 #stream-id-cells = <1>; 767 iommus = <&smmu 0x871>; 768 power-domains = <&pd_sd1>; 769 }; 770 771 smmu: smmu@fd800000 { 772 compatible = "arm,mmu-500"; 773 reg = <0x0 0xfd800000 0x0 0x20000>; 774 #iommu-cells = <1>; 775 #global-interrupts = <1>; 776 interrupt-parent = <&gic>; 777 interrupts = <0 155 4>, 778 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 779 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 780 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 781 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 782 mmu-masters = < &gem0 0x874 783 &gem1 0x875 784 &gem2 0x876 785 &gem3 0x877 786 &usb0 0x860 787 &usb1 0x861 788 &qspi 0x873 789 &lpd_dma_chan1 0x868 790 &lpd_dma_chan2 0x869 791 &lpd_dma_chan3 0x86a 792 &lpd_dma_chan4 0x86b 793 &lpd_dma_chan5 0x86c 794 &lpd_dma_chan6 0x86d 795 &lpd_dma_chan7 0x86e 796 &lpd_dma_chan8 0x86f 797 &fpd_dma_chan1 0x14e8 798 &fpd_dma_chan2 0x14e9 799 &fpd_dma_chan3 0x14ea 800 &fpd_dma_chan4 0x14eb 801 &fpd_dma_chan5 0x14ec 802 &fpd_dma_chan6 0x14ed 803 &fpd_dma_chan7 0x14ee 804 &fpd_dma_chan8 0x14ef 805 &sdhci0 0x870 806 &sdhci1 0x871 807 &nand0 0x872>; 808 }; 809 810 spi0: spi@ff040000 { 811 compatible = "cdns,spi-r1p6"; 812 status = "disabled"; 813 interrupt-parent = <&gic>; 814 interrupts = <0 19 4>; 815 reg = <0x0 0xff040000 0x0 0x1000>; 816 clock-names = "ref_clk", "pclk"; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 power-domains = <&pd_spi0>; 820 }; 821 822 spi1: spi@ff050000 { 823 compatible = "cdns,spi-r1p6"; 824 status = "disabled"; 825 interrupt-parent = <&gic>; 826 interrupts = <0 20 4>; 827 reg = <0x0 0xff050000 0x0 0x1000>; 828 clock-names = "ref_clk", "pclk"; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 power-domains = <&pd_spi1>; 832 }; 833 834 ttc0: timer@ff110000 { 835 compatible = "cdns,ttc"; 836 status = "disabled"; 837 interrupt-parent = <&gic>; 838 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 839 reg = <0x0 0xff110000 0x0 0x1000>; 840 timer-width = <32>; 841 power-domains = <&pd_ttc0>; 842 }; 843 844 ttc1: timer@ff120000 { 845 compatible = "cdns,ttc"; 846 status = "disabled"; 847 interrupt-parent = <&gic>; 848 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 849 reg = <0x0 0xff120000 0x0 0x1000>; 850 timer-width = <32>; 851 power-domains = <&pd_ttc1>; 852 }; 853 854 ttc2: timer@ff130000 { 855 compatible = "cdns,ttc"; 856 status = "disabled"; 857 interrupt-parent = <&gic>; 858 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 859 reg = <0x0 0xff130000 0x0 0x1000>; 860 timer-width = <32>; 861 power-domains = <&pd_ttc2>; 862 }; 863 864 ttc3: timer@ff140000 { 865 compatible = "cdns,ttc"; 866 status = "disabled"; 867 interrupt-parent = <&gic>; 868 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 869 reg = <0x0 0xff140000 0x0 0x1000>; 870 timer-width = <32>; 871 power-domains = <&pd_ttc3>; 872 }; 873 874 uart0: serial@ff000000 { 875 u-boot,dm-pre-reloc; 876 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 877 status = "disabled"; 878 interrupt-parent = <&gic>; 879 interrupts = <0 21 4>; 880 reg = <0x0 0xff000000 0x0 0x1000>; 881 clock-names = "uart_clk", "pclk"; 882 power-domains = <&pd_uart0>; 883 }; 884 885 uart1: serial@ff010000 { 886 u-boot,dm-pre-reloc; 887 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 888 status = "disabled"; 889 interrupt-parent = <&gic>; 890 interrupts = <0 22 4>; 891 reg = <0x0 0xff010000 0x0 0x1000>; 892 clock-names = "uart_clk", "pclk"; 893 power-domains = <&pd_uart1>; 894 }; 895 896 usb0: usb0 { 897 #address-cells = <2>; 898 #size-cells = <2>; 899 status = "disabled"; 900 compatible = "xlnx,zynqmp-dwc3"; 901 clock-names = "bus_clk", "ref_clk"; 902 clocks = <&clk125>, <&clk125>; 903 #stream-id-cells = <1>; 904 iommus = <&smmu 0x860>; 905 power-domains = <&pd_usb0>; 906 ranges; 907 908 dwc3_0: dwc3@fe200000 { 909 compatible = "snps,dwc3"; 910 status = "disabled"; 911 reg = <0x0 0xfe200000 0x0 0x40000>; 912 interrupt-parent = <&gic>; 913 interrupts = <0 65 4>; 914 /* snps,quirk-frame-length-adjustment = <0x20>; */ 915 snps,refclk_fladj; 916 }; 917 }; 918 919 usb1: usb1 { 920 #address-cells = <2>; 921 #size-cells = <2>; 922 status = "disabled"; 923 compatible = "xlnx,zynqmp-dwc3"; 924 clock-names = "bus_clk", "ref_clk"; 925 clocks = <&clk125>, <&clk125>; 926 #stream-id-cells = <1>; 927 iommus = <&smmu 0x861>; 928 power-domains = <&pd_usb1>; 929 ranges; 930 931 dwc3_1: dwc3@fe300000 { 932 compatible = "snps,dwc3"; 933 status = "disabled"; 934 reg = <0x0 0xfe300000 0x0 0x40000>; 935 interrupt-parent = <&gic>; 936 interrupts = <0 70 4>; 937 /* snps,quirk-frame-length-adjustment = <0x20>; */ 938 snps,refclk_fladj; 939 }; 940 }; 941 942 watchdog0: watchdog@fd4d0000 { 943 compatible = "cdns,wdt-r1p2"; 944 status = "disabled"; 945 interrupt-parent = <&gic>; 946 interrupts = <0 113 1>; 947 reg = <0x0 0xfd4d0000 0x0 0x1000>; 948 timeout-sec = <10>; 949 }; 950 951 xilinx_drm: xilinx_drm { 952 compatible = "xlnx,drm"; 953 status = "disabled"; 954 xlnx,encoder-slave = <&xlnx_dp>; 955 xlnx,connector-type = "DisplayPort"; 956 xlnx,dp-sub = <&xlnx_dp_sub>; 957 planes { 958 xlnx,pixel-format = "rgb565"; 959 plane0 { 960 dmas = <&xlnx_dpdma 3>; 961 dma-names = "dma0"; 962 }; 963 plane1 { 964 dmas = <&xlnx_dpdma 0>, 965 <&xlnx_dpdma 1>, 966 <&xlnx_dpdma 2>; 967 dma-names = "dma0", "dma1", "dma2"; 968 }; 969 }; 970 }; 971 972 xlnx_dp: dp@fd4a0000 { 973 compatible = "xlnx,v-dp"; 974 status = "disabled"; 975 reg = <0x0 0xfd4a0000 0x0 0x1000>; 976 interrupts = <0 119 4>; 977 interrupt-parent = <&gic>; 978 clock-names = "aclk", "aud_clk"; 979 xlnx,dp-version = "v1.2"; 980 xlnx,max-lanes = <2>; 981 xlnx,max-link-rate = <540000>; 982 xlnx,max-bpc = <16>; 983 xlnx,enable-ycrcb; 984 xlnx,colormetry = "rgb"; 985 xlnx,bpc = <8>; 986 xlnx,audio-chan = <2>; 987 xlnx,dp-sub = <&xlnx_dp_sub>; 988 xlnx,max-pclock-frequency = <300000>; 989 }; 990 991 xlnx_dp_snd_card: dp_snd_card { 992 compatible = "xlnx,dp-snd-card"; 993 status = "disabled"; 994 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; 995 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; 996 }; 997 998 xlnx_dp_snd_codec0: dp_snd_codec0 { 999 compatible = "xlnx,dp-snd-codec"; 1000 status = "disabled"; 1001 clock-names = "aud_clk"; 1002 }; 1003 1004 xlnx_dp_snd_pcm0: dp_snd_pcm0 { 1005 compatible = "xlnx,dp-snd-pcm"; 1006 status = "disabled"; 1007 dmas = <&xlnx_dpdma 4>; 1008 dma-names = "tx"; 1009 }; 1010 1011 xlnx_dp_snd_pcm1: dp_snd_pcm1 { 1012 compatible = "xlnx,dp-snd-pcm"; 1013 status = "disabled"; 1014 dmas = <&xlnx_dpdma 5>; 1015 dma-names = "tx"; 1016 }; 1017 1018 xlnx_dp_sub: dp_sub@fd4aa000 { 1019 compatible = "xlnx,dp-sub"; 1020 status = "disabled"; 1021 reg = <0x0 0xfd4aa000 0x0 0x1000>, 1022 <0x0 0xfd4ab000 0x0 0x1000>, 1023 <0x0 0xfd4ac000 0x0 0x1000>; 1024 reg-names = "blend", "av_buf", "aud"; 1025 xlnx,output-fmt = "rgb"; 1026 xlnx,vid-fmt = "yuyv"; 1027 xlnx,gfx-fmt = "rgb565"; 1028 }; 1029 1030 xlnx_dpdma: dma@fd4c0000 { 1031 compatible = "xlnx,dpdma"; 1032 status = "disabled"; 1033 reg = <0x0 0xfd4c0000 0x0 0x1000>; 1034 interrupts = <0 122 4>; 1035 interrupt-parent = <&gic>; 1036 clock-names = "axi_clk"; 1037 dma-channels = <6>; 1038 #dma-cells = <1>; 1039 dma-video0channel { 1040 compatible = "xlnx,video0"; 1041 }; 1042 dma-video1channel { 1043 compatible = "xlnx,video1"; 1044 }; 1045 dma-video2channel { 1046 compatible = "xlnx,video2"; 1047 }; 1048 dma-graphicschannel { 1049 compatible = "xlnx,graphics"; 1050 }; 1051 dma-audio0channel { 1052 compatible = "xlnx,audio0"; 1053 }; 1054 dma-audio1channel { 1055 compatible = "xlnx,audio1"; 1056 }; 1057 }; 1058 }; 1059}; 1060