1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include "skeleton.dtsi" 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2600"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c6 = &i2c6; 19 i2c7 = &i2c7; 20 i2c8 = &i2c8; 21 i2c9 = &i2c9; 22 i2c10 = &i2c10; 23 i2c11 = &i2c11; 24 i2c12 = &i2c12; 25 i2c13 = &i2c13; 26 i2c14 = &i2c14; 27 i2c15 = &i2c15; 28 serial0 = &uart1; 29 serial1 = &uart2; 30 serial2 = &uart3; 31 serial3 = &uart4; 32 serial4 = &uart5; 33 serial5 = &uart6; 34 serial6 = &uart7; 35 serial7 = &uart8; 36 serial8 = &uart9; 37 serial9 = &uart10; 38 serial10 = &uart11; 39 serial11 = &uart12; 40 serial12 = &uart13; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 enable-method = "aspeed,ast2600-smp"; 47 48 cpu@0 { 49 compatible = "arm,cortex-a7"; 50 device_type = "cpu"; 51 reg = <0>; 52 clock-frequency = <48000000>; 53 }; 54 55 cpu@1 { 56 compatible = "arm,cortex-a7"; 57 device_type = "cpu"; 58 reg = <1>; 59 clock-frequency = <48000000>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 71 clock-frequency = <25000000>; 72 }; 73 74 memory@80000000 { 75 device_type = "memory"; 76 reg = <0x80000000 0>; 77 }; 78 79 reserved-memory { 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges; 83 84 gfx_memory: framebuffer { 85 size = <0x01000000>; 86 alignment = <0x01000000>; 87 compatible = "shared-dma-pool"; 88 reusable; 89 }; 90 91 video_memory: video { 92 size = <0x04000000>; 93 alignment = <0x01000000>; 94 compatible = "shared-dma-pool"; 95 no-map; 96 }; 97 }; 98 99 ahb { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 device_type = "soc"; 104 ranges; 105 106 gic: interrupt-controller@40461000 { 107 compatible = "arm,cortex-a7-gic"; 108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 109 #interrupt-cells = <3>; 110 interrupt-controller; 111 interrupt-parent = <&gic>; 112 reg = <0x40461000 0x1000>, 113 <0x40462000 0x1000>, 114 <0x40464000 0x2000>, 115 <0x40466000 0x2000>; 116 }; 117 118 fmc: flash-controller@1e620000 { 119 reg = < 0x1e620000 0xc4 120 0x20000000 0x10000000 >; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 compatible = "aspeed,ast2500-fmc"; 124 status = "disabled"; 125 interrupts = <19>; 126 flash@0 { 127 reg = < 0 >; 128 compatible = "jedec,spi-nor"; 129 status = "disabled"; 130 }; 131 flash@1 { 132 reg = < 1 >; 133 compatible = "jedec,spi-nor"; 134 status = "disabled"; 135 }; 136 flash@2 { 137 reg = < 2 >; 138 compatible = "jedec,spi-nor"; 139 status = "disabled"; 140 }; 141 }; 142 143 spi1: flash-controller@1e630000 { 144 reg = < 0x1e630000 0xc4 145 0x30000000 0x08000000 >; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 compatible = "aspeed,ast2500-spi"; 149 status = "disabled"; 150 flash@0 { 151 reg = < 0 >; 152 compatible = "jedec,spi-nor"; 153 status = "disabled"; 154 }; 155 flash@1 { 156 reg = < 1 >; 157 compatible = "jedec,spi-nor"; 158 status = "disabled"; 159 }; 160 }; 161 162 spi2: flash-controller@1e631000 { 163 reg = < 0x1e631000 0xc4 164 0x38000000 0x08000000 >; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 compatible = "aspeed,ast2500-spi"; 168 status = "disabled"; 169 flash@0 { 170 reg = < 0 >; 171 compatible = "jedec,spi-nor"; 172 status = "disabled"; 173 }; 174 flash@1 { 175 reg = < 1 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 }; 180 181 edac: sdram@1e6e0000 { 182 compatible = "aspeed,ast2600-sdram-edac"; 183 reg = <0x1e6e0000 0x174>; 184 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 185 }; 186 187 mac0: ethernet@1e660000 { 188 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 189 reg = <0x1e660000 0x180>; 190 interrupts = <2>; 191 status = "disabled"; 192 }; 193 194 mac2: ftgmac@1e670000 { 195 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 196 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 200#if 0 201 phy-handle = <&phy0>; 202#endif 203 status = "disabled"; 204 }; 205 206 mac1: ftgmac@1e680000 { 207 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 208 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 212#if 0 213 phy-handle = <&phy0>; 214#endif 215 status = "disabled"; 216 }; 217 218 mac3: ftgmac@1e690000 { 219 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 220 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 224#if 0 225 phy-handle = <&phy0>; 226#endif 227 status = "disabled"; 228 }; 229 230 231 apb { 232 compatible = "simple-bus"; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 ranges; 236 237 syscon: syscon@1e6e2000 { 238 compatible = "aspeed,aspeed-scu", "aspeed,ast2600-scu", "syscon", "simple-mfd"; 239 reg = <0x1e6e2000 0x1000>; 240 #address-cells = <1>; 241 #size-cells = <1>; 242 #clock-cells = <1>; 243 #reset-cells = <1>; 244 ranges = <0 0x1e6e2000 0x1000>; 245 246 vga_scratch: scratch { 247 compatible = "aspeed,bmc-misc"; 248 }; 249 250 scu_ic0: interrupt-controller@0 { 251 #interrupt-cells = <1>; 252 compatible = "aspeed,ast2600-scu-ic"; 253 reg = <0x560 0x10>; 254 interrupt-parent = <&gic>; 255 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 256 interrupt-controller; 257 }; 258 259 scu_ic1: interrupt-controller@1 { 260 #interrupt-cells = <1>; 261 compatible = "aspeed,ast2600-scu-ic"; 262 reg = <0x570 0x10>; 263 interrupt-parent = <&gic>; 264 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-controller; 266 }; 267 268 }; 269 270 smp-memram@0 { 271 compatible = "aspeed,ast2600-smpmem", "syscon"; 272 reg = <0x1e6e2180 0x40>; 273 }; 274 275 276 uart1: serial@1e783000 { 277 compatible = "ns16550a"; 278 reg = <0x1e783000 0x20>; 279 reg-shift = <2>; 280 no-loopback-test; 281 status = "disabled"; 282 }; 283 284 uart5: serial@1e784000 { 285 compatible = "ns16550a"; 286 reg = <0x1e784000 0x1000>; 287 reg-shift = <2>; 288 clock-frequency = <1846154>; 289 no-loopback-test; 290 }; 291 292 wdt1: watchdog@1e785000 { 293 compatible = "aspeed,ast2600-wdt"; 294 reg = <0x1e785000 0x40>; 295 }; 296 297 wdt2: watchdog@1e785040 { 298 compatible = "aspeed,ast2600-wdt"; 299 reg = <0x1e785040 0x40>; 300 }; 301 302 wdt3: watchdog@1e785080 { 303 compatible = "aspeed,ast2600-wdt"; 304 reg = <0x1e785080 0x40>; 305 }; 306 307 wdt4: watchdog@1e7850C0 { 308 compatible = "aspeed,ast2600-wdt"; 309 reg = <0x1e7850C0 0x40>; 310 }; 311 312 lpc: lpc@1e789000 { 313 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 314 reg = <0x1e789000 0x200>; 315 316 #address-cells = <1>; 317 #size-cells = <1>; 318 ranges = <0x0 0x1e789000 0x1000>; 319 320 lpc_bmc: lpc-bmc@0 { 321 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 322 reg = <0x0 0x80>; 323 reg-io-width = <4>; 324 #address-cells = <1>; 325 #size-cells = <1>; 326 ranges = <0x0 0x0 0x80>; 327 328 kcs1: kcs1@0 { 329 compatible = "aspeed,ast2600-kcs-bmc"; 330 reg = <0x0 0x80>; 331 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 332 kcs_chan = <1>; 333 kcs_addr = <0xCA0>; 334 status = "disabled"; 335 }; 336 337 kcs2: kcs2@0 { 338 compatible = "aspeed,ast2600-kcs-bmc"; 339 reg = <0x0 0x80>; 340 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 341 kcs_chan = <2>; 342 kcs_addr = <0xCA8>; 343 status = "disabled"; 344 }; 345 346 kcs3: kcs3@0 { 347 compatible = "aspeed,ast2600-kcs-bmc"; 348 reg = <0x0 0x80>; 349 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 350 kcs_chan = <3>; 351 kcs_addr = <0xCA2>; 352 }; 353 354 kcs4: kcs4@0 { 355 compatible = "aspeed,ast2600-kcs-bmc"; 356 reg = <0x0 0x120>; 357 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 358 kcs_chan = <4>; 359 kcs_addr = <0xCA4>; 360 status = "disabled"; 361 }; 362 363 }; 364 365 lpc_host: lpc-host@80 { 366 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 367 reg = <0x80 0x1e0>; 368 reg-io-width = <4>; 369 370 #address-cells = <1>; 371 #size-cells = <1>; 372 ranges = <0x0 0x80 0x1e0>; 373 374 lpc_ctrl: lpc-ctrl@0 { 375 compatible = "aspeed,ast2600-lpc-ctrl"; 376 reg = <0x0 0x80>; 377 status = "disabled"; 378 }; 379 380 lpc_snoop: lpc-snoop@0 { 381 compatible = "aspeed,ast2600-lpc-snoop"; 382 reg = <0x0 0x80>; 383 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 384 snoop-ports = <0x80>; 385 status = "disabled"; 386 }; 387 388 lhc: lhc@20 { 389 compatible = "aspeed,ast2600-lhc"; 390 reg = <0x20 0x24 0x48 0x8>; 391 }; 392 393 lpc_reset: reset-controller@18 { 394 compatible = "aspeed,ast2600-lpc-reset"; 395 reg = <0x18 0x4>; 396 #reset-cells = <1>; 397 status = "disabled"; 398 }; 399 400 ibt: ibt@c0 { 401 compatible = "aspeed,ast2600-ibt-bmc"; 402 reg = <0xc0 0x18>; 403 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 404 status = "disabled"; 405 }; 406 407 sio_regs: regs { 408 compatible = "aspeed,bmc-misc"; 409 }; 410 411 mbox: mbox@180 { 412 compatible = "aspeed,ast2600-mbox"; 413 reg = <0x180 0x5c>; 414 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 415 #mbox-cells = <1>; 416 status = "disabled"; 417 }; 418 }; 419 }; 420 421 uart2: serial@1e78d000 { 422 compatible = "ns16550a"; 423 reg = <0x1e78d000 0x20>; 424 reg-shift = <2>; 425 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 426 no-loopback-test; 427 status = "disabled"; 428 }; 429 430 uart3: serial@1e78e000 { 431 compatible = "ns16550a"; 432 reg = <0x1e78e000 0x20>; 433 reg-shift = <2>; 434 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 435 no-loopback-test; 436 status = "disabled"; 437 }; 438 439 uart4: serial@1e78f000 { 440 compatible = "ns16550a"; 441 reg = <0x1e78f000 0x20>; 442 reg-shift = <2>; 443 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 444 no-loopback-test; 445 status = "disabled"; 446 }; 447 448 i2c: bus@1e78a000 { 449 compatible = "simple-bus"; 450 #address-cells = <1>; 451 #size-cells = <1>; 452 ranges = <0 0x1e78a000 0x1000>; 453 }; 454 455 uart6: serial@1e790000 { 456 compatible = "ns16550a"; 457 reg = <0x1e790000 0x20>; 458 reg-shift = <2>; 459 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 460 no-loopback-test; 461 status = "disabled"; 462 }; 463 464 uart7: serial@1e790100 { 465 compatible = "ns16550a"; 466 reg = <0x1e790100 0x20>; 467 reg-shift = <2>; 468 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 469 no-loopback-test; 470 status = "disabled"; 471 }; 472 473 uart8: serial@1e790200 { 474 compatible = "ns16550a"; 475 reg = <0x1e790200 0x20>; 476 reg-shift = <2>; 477 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 478 no-loopback-test; 479 status = "disabled"; 480 }; 481 482 uart9: serial@1e790300 { 483 compatible = "ns16550a"; 484 reg = <0x1e790300 0x20>; 485 reg-shift = <2>; 486 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 487 no-loopback-test; 488 status = "disabled"; 489 }; 490 491 uart10: serial@1e790400 { 492 compatible = "ns16550a"; 493 reg = <0x1e790400 0x20>; 494 reg-shift = <2>; 495 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 496 no-loopback-test; 497 status = "disabled"; 498 }; 499 500 uart11: serial@1e790500 { 501 compatible = "ns16550a"; 502 reg = <0x1e790400 0x20>; 503 reg-shift = <2>; 504 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 505 no-loopback-test; 506 status = "disabled"; 507 }; 508 509 uart12: serial@1e790600 { 510 compatible = "ns16550a"; 511 reg = <0x1e790600 0x20>; 512 reg-shift = <2>; 513 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 514 no-loopback-test; 515 status = "disabled"; 516 }; 517 518 uart13: serial@1e790700 { 519 compatible = "ns16550a"; 520 reg = <0x1e790700 0x20>; 521 reg-shift = <2>; 522 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 523 no-loopback-test; 524 status = "disabled"; 525 }; 526 527 528 529 }; 530 531 }; 532 533}; 534 535&i2c { 536 i2cglobal: i2cg@00 { 537 compatible = "aspeed,ast2600-i2c-global", "syscon", "simple-mfd"; 538 reg = <0x0 0x40>; 539 540#if 0 541 new-mode; 542#endif 543 }; 544 545 i2c0: i2c@80 { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 #interrupt-cells = <1>; 549 550 reg = <0x80 0x80 0xC00 0x20>; 551 compatible = "aspeed,ast2600-i2c-bus"; 552#if 0 553 compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 554 #compatible = "aspeed,ast2500-i2c-bus"; 555 #compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 556#endif 557 bus-frequency = <100000>; 558 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 559 }; 560 561 i2c1: i2c@100 { 562 #address-cells = <1>; 563 #size-cells = <0>; 564 #interrupt-cells = <1>; 565 566 reg = <0x100 0x80 0xC20 0x20>; 567 compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 568#if 0 569 #compatible = "aspeed,ast2500-i2c-bus"; 570 #compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 571#endif 572 bus-frequency = <100000>; 573 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 574 }; 575 576 i2c2: i2c@180 { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 #interrupt-cells = <1>; 580 581 reg = <0x180 0x80 0xC40 0x20>; 582 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 583 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 584 bus-frequency = <100000>; 585 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 586 }; 587 588 i2c3: i2c@200 { 589 #address-cells = <1>; 590 #size-cells = <0>; 591 #interrupt-cells = <1>; 592 593 reg = <0x200 0x40 0xC60 0x20>; 594 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 595 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 596 bus-frequency = <100000>; 597 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 598 }; 599 600 i2c4: i2c@280 { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 #interrupt-cells = <1>; 604 605 reg = <0x280 0x80 0xC80 0x20>; 606 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 607 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 608 bus-frequency = <100000>; 609 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 610 }; 611 612 i2c5: i2c@300 { 613 #address-cells = <1>; 614 #size-cells = <0>; 615 #interrupt-cells = <1>; 616 617 reg = <0x300 0x40 0xCA0 0x20>; 618 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 619 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 620 bus-frequency = <100000>; 621 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 622 }; 623 624 i2c6: i2c@380 { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 #interrupt-cells = <1>; 628 629 reg = <0x380 0x80 0xCC0 0x20>; 630 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 631 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 632 bus-frequency = <100000>; 633 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 634 }; 635 636 i2c7: i2c@400 { 637 #address-cells = <1>; 638 #size-cells = <0>; 639 #interrupt-cells = <1>; 640 641 reg = <0x400 0x80 0xCE0 0x20>; 642 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 643 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 644 bus-frequency = <100000>; 645 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 646 }; 647 648 i2c8: i2c@480 { 649 #address-cells = <1>; 650 #size-cells = <0>; 651 #interrupt-cells = <1>; 652 653 reg = <0x480 0x80 0xD00 0x20>; 654 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 655 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 656 bus-frequency = <100000>; 657 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 658 }; 659 660 i2c9: i2c@500 { 661 #address-cells = <1>; 662 #size-cells = <0>; 663 #interrupt-cells = <1>; 664 665 reg = <0x500 0x80 0xD20 0x20>; 666 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 667 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 668 bus-frequency = <100000>; 669 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 670 status = "disabled"; 671 }; 672 673 i2c10: i2c@580 { 674 #address-cells = <1>; 675 #size-cells = <0>; 676 #interrupt-cells = <1>; 677 678 reg = <0x580 0x80 0xD40 0x20>; 679 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 680 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 681 bus-frequency = <100000>; 682 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 683 status = "disabled"; 684 }; 685 686 i2c11: i2c@600 { 687 #address-cells = <1>; 688 #size-cells = <0>; 689 #interrupt-cells = <1>; 690 691 reg = <0x600 0x80 0xD60 0x20>; 692 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 693 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 694 bus-frequency = <100000>; 695 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 696 status = "disabled"; 697 }; 698 699 i2c12: i2c@680 { 700 #address-cells = <1>; 701 #size-cells = <0>; 702 #interrupt-cells = <1>; 703 704 reg = <0x680 0x80 0xD80 0x20>; 705 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 706 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 707 bus-frequency = <100000>; 708 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 709 status = "disabled"; 710 }; 711 712 i2c13: i2c@700 { 713 #address-cells = <1>; 714 #size-cells = <0>; 715 #interrupt-cells = <1>; 716 717 reg = <0x700 0x80 0xDA0 0x20>; 718 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 719 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 720 bus-frequency = <100000>; 721 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 722 status = "disabled"; 723 }; 724 725 i2c14: i2c@780 { 726 #address-cells = <1>; 727 #size-cells = <0>; 728 #interrupt-cells = <1>; 729 730 reg = <0x780 0x80 0xDC0 0x20>; 731 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 732 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 733 bus-frequency = <100000>; 734 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 735 status = "disabled"; 736 }; 737 738 i2c15: i2c@800 { 739 #address-cells = <1>; 740 #size-cells = <0>; 741 #interrupt-cells = <1>; 742 743 reg = <0x800 0x80 0xDE0 0x20>; 744 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 745 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 746 bus-frequency = <100000>; 747 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 748 status = "disabled"; 749 }; 750 751}; 752 753