1#include <dt-bindings/clock/ast2600-clock.h>
2#include <dt-bindings/reset/ast2600-reset.h>
3
4#include "ast2600.dtsi"
5
6/ {
7	scu: clock-controller@1e6e2000 {
8		compatible = "aspeed,ast2600-scu";
9		reg = <0x1e6e2000 0x1000>;
10		u-boot,dm-pre-reloc;
11		#clock-cells = <1>;
12		#reset-cells = <1>;
13	};
14
15	rst: reset-controller {
16		u-boot,dm-pre-reloc;
17		compatible = "aspeed,ast2600-reset";
18		aspeed,wdt = <&wdt1>;
19		#reset-cells = <1>;
20	};
21
22	sdrammc: sdrammc@1e6e0000 {
23		u-boot,dm-pre-reloc;
24		compatible = "aspeed,ast2600-sdrammc";
25		reg = <0x1e6e0000 0x100
26			0x1e6e0100 0x300
27			0x1e6e0400 0x200 >;
28		#reset-cells = <1>;
29		clocks = <&scu ASPEED_CLK_MPLL>;
30		resets = <&rst ASPEED_RESET_SDRAM>;
31	};
32
33	ahb {
34		u-boot,dm-pre-reloc;
35
36		apb {
37			u-boot,dm-pre-reloc;
38		};
39
40	};
41};
42
43&uart1 {
44	clock-frequency = <1846154>;
45};
46
47&uart2 {
48	clock-frequency = <1846154>;
49};
50
51&uart3 {
52	clock-frequency = <1846154>;
53};
54
55&uart4 {
56	clock-frequency = <1846154>;
57};
58
59&uart5 {
60#if 0
61	clock-frequency = <1846154>;
62#endif
63	clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
64};
65
66&mdio {
67	resets = <&rst ASPEED_RESET_MII>;
68};
69
70&mac0 {
71	clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
72};
73
74#if 0
75&mac1 {
76	clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
77};
78#endif
79&fmc {
80	clocks = <&scu ASPEED_CLK_AHB>;
81};
82
83&spi1 {
84	clocks = <&scu ASPEED_CLK_AHB>;
85};
86
87&spi2 {
88	clocks = <&scu ASPEED_CLK_AHB>;
89};
90