1config ARCH_LS1021A 2 bool 3 select SYS_FSL_ERRATUM_A010315 4 select SYS_FSL_SRDS_1 5 select SYS_HAS_SERDES 6 select SYS_FSL_DDR_BE if SYS_FSL_DDR 7 select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR 8 select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR 9 select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR 10 select SYS_FSL_HAS_SEC 11 select SYS_FSL_SEC_COMPAT_5 12 select SYS_FSL_SEC_LE 13 14menu "LS102xA architecture" 15 depends on ARCH_LS1021A 16 17config LS1_DEEP_SLEEP 18 bool "Deep sleep" 19 depends on ARCH_LS1021A 20 21config MAX_CPUS 22 int "Maximum number of CPUs permitted for LS102xA" 23 depends on ARCH_LS1021A 24 default 2 25 help 26 Set this number to the maximum number of possible CPUs in the SoC. 27 SoCs may have multiple clusters with each cluster may have multiple 28 ports. If some ports are reserved but higher ports are used for 29 cores, count the reserved ports. This will allocate enough memory 30 in spin table to properly handle all cores. 31 32config NUM_DDR_CONTROLLERS 33 int "Maximum DDR controllers" 34 default 1 35 36config SECURE_BOOT 37 bool "Secure Boot" 38 help 39 Enable Freescale Secure Boot feature. Normally selected 40 by defconfig. If unsure, do not change. 41 42config SYS_FSL_ERRATUM_A010315 43 bool "Workaround for PCIe erratum A010315" 44 45config SYS_FSL_SRDS_1 46 bool 47 48config SYS_FSL_SRDS_2 49 bool 50 51config SYS_HAS_SERDES 52 bool 53 54config SYS_FSL_IFC_BANK_COUNT 55 int "Maximum banks of Integrated flash controller" 56 depends on ARCH_LS1021A 57 default 8 58 59endmenu 60