1config ARCH_LS1021A 2 bool 3 select SYS_FSL_DDR_BE if SYS_FSL_DDR 4 select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR 5 select SYS_FSL_ERRATUM_A008378 6 select SYS_FSL_ERRATUM_A008407 7 select SYS_FSL_ERRATUM_A008850 8 select SYS_FSL_ERRATUM_A008997 9 select SYS_FSL_ERRATUM_A009007 10 select SYS_FSL_ERRATUM_A009008 11 select SYS_FSL_ERRATUM_A009663 12 select SYS_FSL_ERRATUM_A009798 13 select SYS_FSL_ERRATUM_A009942 14 select SYS_FSL_ERRATUM_A010315 15 select SYS_FSL_HAS_CCI400 16 select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR 17 select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR 18 select SYS_FSL_HAS_SEC 19 select SYS_FSL_SEC_COMPAT_5 20 select SYS_FSL_SEC_LE 21 select SYS_FSL_SRDS_1 22 select SYS_HAS_SERDES 23 imply CMD_PCI 24 imply SCSI 25 imply SCSI_AHCI 26 27menu "LS102xA architecture" 28 depends on ARCH_LS1021A 29 30config FSL_PCIE_COMPAT 31 string "PCIe compatible of Kernel DT" 32 depends on PCIE_LAYERSCAPE 33 default "fsl,ls1021a-pcie" if ARCH_LS1021A 34 help 35 This compatible is used to find pci controller node in Kernel DT 36 to complete fixup. 37 38config LS1_DEEP_SLEEP 39 bool "Deep sleep" 40 depends on ARCH_LS1021A 41 42config MAX_CPUS 43 int "Maximum number of CPUs permitted for LS102xA" 44 depends on ARCH_LS1021A 45 default 2 46 help 47 Set this number to the maximum number of possible CPUs in the SoC. 48 SoCs may have multiple clusters with each cluster may have multiple 49 ports. If some ports are reserved but higher ports are used for 50 cores, count the reserved ports. This will allocate enough memory 51 in spin table to properly handle all cores. 52 53config SECURE_BOOT 54 bool "Secure Boot" 55 help 56 Enable Freescale Secure Boot feature. Normally selected 57 by defconfig. If unsure, do not change. 58 59config SYS_CCI400_OFFSET 60 hex "Offset for CCI400 base" 61 depends on SYS_FSL_HAS_CCI400 62 default 0x180000 63 help 64 Offset for CCI400 base. 65 CCI400 base addr = CCSRBAR + CCI400_OFFSET 66 67config SYS_FSL_ERRATUM_A008850 68 bool 69 help 70 Workaround for DDR erratum A008850 71 72config SYS_FSL_ERRATUM_A008997 73 bool 74 help 75 Workaround for USB PHY erratum A008997 76 77config SYS_FSL_ERRATUM_A009007 78 bool 79 help 80 Workaround for USB PHY erratum A009007 81 82config SYS_FSL_ERRATUM_A009008 83 bool 84 help 85 Workaround for USB PHY erratum A009008 86 87config SYS_FSL_ERRATUM_A009798 88 bool 89 help 90 Workaround for USB PHY erratum A009798 91 92config SYS_FSL_ERRATUM_A010315 93 bool "Workaround for PCIe erratum A010315" 94 95config SYS_FSL_HAS_CCI400 96 bool 97 98config SYS_FSL_SRDS_1 99 bool 100 101config SYS_FSL_SRDS_2 102 bool 103 104config SYS_HAS_SERDES 105 bool 106 107config SYS_FSL_IFC_BANK_COUNT 108 int "Maximum banks of Integrated flash controller" 109 depends on ARCH_LS1021A 110 default 8 111 112config SYS_FSL_ERRATUM_A008407 113 bool 114 115endmenu 116