1config ARCH_LS1021A 2 bool 3 select SYS_FSL_ERRATUM_A010315 4 select SYS_FSL_SRDS_1 5 select SYS_HAS_SERDES 6 select SYS_FSL_DDR_BE 7 select SYS_FSL_DDR_VER_50 8 9menu "LS102xA architecture" 10 depends on ARCH_LS1021A 11 12config LS1_DEEP_SLEEP 13 bool "Deep sleep" 14 depends on ARCH_LS1021A 15 16config MAX_CPUS 17 int "Maximum number of CPUs permitted for LS102xA" 18 depends on ARCH_LS1021A 19 default 2 20 help 21 Set this number to the maximum number of possible CPUs in the SoC. 22 SoCs may have multiple clusters with each cluster may have multiple 23 ports. If some ports are reserved but higher ports are used for 24 cores, count the reserved ports. This will allocate enough memory 25 in spin table to properly handle all cores. 26 27config NUM_DDR_CONTROLLERS 28 int "Maximum DDR controllers" 29 default 1 30 31config SYS_FSL_ERRATUM_A010315 32 bool "Workaround for PCIe erratum A010315" 33 34config SYS_FSL_SRDS_1 35 bool 36 37config SYS_FSL_SRDS_2 38 bool 39 40config SYS_HAS_SERDES 41 bool 42 43config SYS_FSL_DDR 44 bool "Freescale DDR driver" 45 help 46 Select Freescale General DDR driver, shared between most Freescale 47 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- 48 based Layerscape SoCs (such as ls2080a). 49 50config SYS_FSL_DDR_BE 51 bool 52 default y 53 help 54 Access DDR registers in big-endian. 55 56config SYS_FSL_DDR_VER 57 int 58 default 50 if SYS_FSL_DDR_VER_50 59 60config SYS_FSL_DDR_VER_50 61 bool 62 63config SYS_FSL_DDRC_ARM_GEN3 64 bool 65 66config SYS_FSL_DDRC_GEN4 67 bool 68 69config SYS_FSL_DDR3 70 bool "Freescale DDR3 controller" 71 depends on !SYS_FSL_DDR4 72 select SYS_FSL_DDR 73 select SYS_FSL_DDRC_ARM_GEN3 74 help 75 Enable Freescale DDR3 controller on ARM-based SoCs. 76 77config SYS_FSL_DDR4 78 bool "Freescale DDR4 controller" 79 select SYS_FSL_DDR 80 select SYS_FSL_DDRC_GEN4 81 help 82 Enable Freescale DDR4 controller. 83 84config SYS_FSL_IFC_BANK_COUNT 85 int "Maximum banks of Integrated flash controller" 86 depends on ARCH_LS1021A 87 default 8 88 89endmenu 90