1config ARCH_LS1021A 2 bool 3 select SYS_FSL_ERRATUM_A010315 4 select SYS_FSL_SRDS_1 5 select SYS_HAS_SERDES 6 select SYS_FSL_DDR_BE 7 select SYS_FSL_DDR_VER_50 8 9menu "LS102xA architecture" 10 depends on ARCH_LS1021A 11 12config LS1_DEEP_SLEEP 13 bool "Deep sleep" 14 depends on ARCH_LS1021A 15 16config MAX_CPUS 17 int "Maximum number of CPUs permitted for LS102xA" 18 depends on ARCH_LS1021A 19 default 2 20 help 21 Set this number to the maximum number of possible CPUs in the SoC. 22 SoCs may have multiple clusters with each cluster may have multiple 23 ports. If some ports are reserved but higher ports are used for 24 cores, count the reserved ports. This will allocate enough memory 25 in spin table to properly handle all cores. 26 27config NUM_DDR_CONTROLLERS 28 int "Maximum DDR controllers" 29 default 1 30 31config SECURE_BOOT 32 bool "Secure Boot" 33 help 34 Enable Freescale Secure Boot feature. Normally selected 35 by defconfig. If unsure, do not change. 36 37config SYS_FSL_ERRATUM_A010315 38 bool "Workaround for PCIe erratum A010315" 39 40config SYS_FSL_SRDS_1 41 bool 42 43config SYS_FSL_SRDS_2 44 bool 45 46config SYS_HAS_SERDES 47 bool 48 49config SYS_FSL_DDR 50 bool "Freescale DDR driver" 51 help 52 Select Freescale General DDR driver, shared between most Freescale 53 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- 54 based Layerscape SoCs (such as ls2080a). 55 56config SYS_FSL_DDR_BE 57 bool 58 default y 59 help 60 Access DDR registers in big-endian. 61 62config SYS_FSL_DDR_VER 63 int 64 default 50 if SYS_FSL_DDR_VER_50 65 66config SYS_FSL_DDR_VER_50 67 bool 68 69config SYS_FSL_DDRC_ARM_GEN3 70 bool 71 72config SYS_FSL_DDRC_GEN4 73 bool 74 75config SYS_FSL_DDR3 76 bool "Freescale DDR3 controller" 77 depends on !SYS_FSL_DDR4 78 select SYS_FSL_DDR 79 select SYS_FSL_DDRC_ARM_GEN3 80 help 81 Enable Freescale DDR3 controller on ARM-based SoCs. 82 83config SYS_FSL_DDR4 84 bool "Freescale DDR4 controller" 85 select SYS_FSL_DDR 86 select SYS_FSL_DDRC_GEN4 87 help 88 Enable Freescale DDR4 controller. 89 90config SYS_FSL_IFC_BANK_COUNT 91 int "Maximum banks of Integrated flash controller" 92 depends on ARCH_LS1021A 93 default 8 94 95endmenu 96