1config ARCH_LS1021A 2 bool 3 select SYS_FSL_ERRATUM_A008378 4 select SYS_FSL_ERRATUM_A008407 5 select SYS_FSL_ERRATUM_A009663 6 select SYS_FSL_ERRATUM_A009942 7 select SYS_FSL_ERRATUM_A010315 8 select SYS_FSL_SRDS_1 9 select SYS_HAS_SERDES 10 select SYS_FSL_DDR_BE if SYS_FSL_DDR 11 select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR 12 select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR 13 select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR 14 select SYS_FSL_HAS_SEC 15 select SYS_FSL_SEC_COMPAT_5 16 select SYS_FSL_SEC_LE 17 imply SCSI 18 19menu "LS102xA architecture" 20 depends on ARCH_LS1021A 21 22config FSL_PCIE_COMPAT 23 string "PCIe compatible of Kernel DT" 24 depends on PCIE_LAYERSCAPE 25 default "fsl,ls1021a-pcie" if ARCH_LS1021A 26 help 27 This compatible is used to find pci controller node in Kernel DT 28 to complete fixup. 29 30config LS1_DEEP_SLEEP 31 bool "Deep sleep" 32 depends on ARCH_LS1021A 33 34config MAX_CPUS 35 int "Maximum number of CPUs permitted for LS102xA" 36 depends on ARCH_LS1021A 37 default 2 38 help 39 Set this number to the maximum number of possible CPUs in the SoC. 40 SoCs may have multiple clusters with each cluster may have multiple 41 ports. If some ports are reserved but higher ports are used for 42 cores, count the reserved ports. This will allocate enough memory 43 in spin table to properly handle all cores. 44 45config SECURE_BOOT 46 bool "Secure Boot" 47 help 48 Enable Freescale Secure Boot feature. Normally selected 49 by defconfig. If unsure, do not change. 50 51config SYS_FSL_ERRATUM_A010315 52 bool "Workaround for PCIe erratum A010315" 53 54config SYS_FSL_SRDS_1 55 bool 56 57config SYS_FSL_SRDS_2 58 bool 59 60config SYS_HAS_SERDES 61 bool 62 63config SYS_FSL_IFC_BANK_COUNT 64 int "Maximum banks of Integrated flash controller" 65 depends on ARCH_LS1021A 66 default 8 67 68config SYS_FSL_ERRATUM_A008407 69 bool 70 71endmenu 72