1 /* 2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <linux/compiler.h> 10 #include <linux/kernel.h> 11 #include <linux/log2.h> 12 #include <asm/arcregs.h> 13 #include <asm/arc-bcr.h> 14 #include <asm/cache.h> 15 16 /* 17 * [ NOTE 1 ]: 18 * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable 19 * operation may result in unexpected behavior and data loss even if we flush 20 * data cache right before invalidation. That may happens if we store any context 21 * on stack (like we store BLINK register on stack before function call). 22 * BLINK register is the register where return address is automatically saved 23 * when we do function call with instructions like 'bl'. 24 * 25 * There is the real example: 26 * We may hang in the next code as we store any BLINK register on stack in 27 * invalidate_dcache_all() function. 28 * 29 * void flush_dcache_all() { 30 * __dc_entire_op(OP_FLUSH); 31 * // Other code // 32 * } 33 * 34 * void invalidate_dcache_all() { 35 * __dc_entire_op(OP_INV); 36 * // Other code // 37 * } 38 * 39 * void foo(void) { 40 * flush_dcache_all(); 41 * invalidate_dcache_all(); 42 * } 43 * 44 * Now let's see what really happens during that code execution: 45 * 46 * foo() 47 * |->> call flush_dcache_all 48 * [return address is saved to BLINK register] 49 * [push BLINK] (save to stack) ![point 1] 50 * |->> call __dc_entire_op(OP_FLUSH) 51 * [return address is saved to BLINK register] 52 * [flush L1 D$] 53 * return [jump to BLINK] 54 * <<------ 55 * [other flush_dcache_all code] 56 * [pop BLINK] (get from stack) 57 * return [jump to BLINK] 58 * <<------ 59 * |->> call invalidate_dcache_all 60 * [return address is saved to BLINK register] 61 * [push BLINK] (save to stack) ![point 2] 62 * |->> call __dc_entire_op(OP_FLUSH) 63 * [return address is saved to BLINK register] 64 * [invalidate L1 D$] ![point 3] 65 * // Oops!!! 66 * // We lose return address from invalidate_dcache_all function: 67 * // we save it to stack and invalidate L1 D$ after that! 68 * return [jump to BLINK] 69 * <<------ 70 * [other invalidate_dcache_all code] 71 * [pop BLINK] (get from stack) 72 * // we don't have this data in L1 dcache as we invalidated it in [point 3] 73 * // so we get it from next memory level (for example DDR memory) 74 * // but in the memory we have value which we save in [point 1], which 75 * // is return address from flush_dcache_all function (instead of 76 * // address from current invalidate_dcache_all function which we 77 * // saved in [point 2] !) 78 * return [jump to BLINK] 79 * <<------ 80 * // As BLINK points to invalidate_dcache_all, we call it again and 81 * // loop forever. 82 * 83 * Fortunately we may fix that by using flush & invalidation of D$ with a single 84 * one instruction (instead of flush and invalidation instructions pair) and 85 * enabling force function inline with '__attribute__((always_inline))' gcc 86 * attribute to avoid any function call (and BLINK store) between cache flush 87 * and disable. 88 */ 89 90 DECLARE_GLOBAL_DATA_PTR; 91 92 /* Bit values in IC_CTRL */ 93 #define IC_CTRL_CACHE_DISABLE BIT(0) 94 95 /* Bit values in DC_CTRL */ 96 #define DC_CTRL_CACHE_DISABLE BIT(0) 97 #define DC_CTRL_INV_MODE_FLUSH BIT(6) 98 #define DC_CTRL_FLUSH_STATUS BIT(8) 99 100 #define OP_INV BIT(0) 101 #define OP_FLUSH BIT(1) 102 #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV) 103 104 /* Bit val in SLC_CONTROL */ 105 #define SLC_CTRL_DIS 0x001 106 #define SLC_CTRL_IM 0x040 107 #define SLC_CTRL_BUSY 0x100 108 #define SLC_CTRL_RGN_OP_INV 0x200 109 110 #define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1)) 111 112 static inline bool pae_exists(void) 113 { 114 /* TODO: should we compare mmu version from BCR and from CONFIG? */ 115 #if (CONFIG_ARC_MMU_VER >= 4) 116 union bcr_mmu_4 mmu4; 117 118 mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR); 119 120 if (mmu4.fields.pae) 121 return true; 122 #endif /* (CONFIG_ARC_MMU_VER >= 4) */ 123 124 return false; 125 } 126 127 static inline bool icache_exists(void) 128 { 129 union bcr_di_cache ibcr; 130 131 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 132 return !!ibcr.fields.ver; 133 } 134 135 static inline bool icache_enabled(void) 136 { 137 if (!icache_exists()) 138 return false; 139 140 return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE); 141 } 142 143 static inline bool dcache_exists(void) 144 { 145 union bcr_di_cache dbcr; 146 147 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 148 return !!dbcr.fields.ver; 149 } 150 151 static inline bool dcache_enabled(void) 152 { 153 if (!dcache_exists()) 154 return false; 155 156 return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE); 157 } 158 159 static inline bool slc_exists(void) 160 { 161 if (is_isa_arcv2()) { 162 union bcr_generic sbcr; 163 164 sbcr.word = read_aux_reg(ARC_BCR_SLC); 165 return !!sbcr.fields.ver; 166 } 167 168 return false; 169 } 170 171 static inline bool ioc_exists(void) 172 { 173 if (is_isa_arcv2()) { 174 union bcr_clust_cfg cbcr; 175 176 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); 177 return cbcr.fields.c; 178 } 179 180 return false; 181 } 182 183 static inline bool ioc_enabled(void) 184 { 185 /* 186 * We check only CONFIG option instead of IOC HW state check as IOC 187 * must be disabled by default. 188 */ 189 if (is_ioc_enabled()) 190 return ioc_exists(); 191 192 return false; 193 } 194 195 static void __slc_entire_op(const int op) 196 { 197 unsigned int ctrl; 198 199 if (!slc_exists()) 200 return; 201 202 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 203 204 if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 205 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 206 else 207 ctrl |= SLC_CTRL_IM; 208 209 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 210 211 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 212 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); 213 else 214 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); 215 216 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 217 read_aux_reg(ARC_AUX_SLC_CTRL); 218 219 /* Important to wait for flush to complete */ 220 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 221 } 222 223 static void slc_upper_region_init(void) 224 { 225 /* 226 * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist 227 * only if PAE exists in current HW. So we had to check pae_exist 228 * before using them. 229 */ 230 if (!pae_exists()) 231 return; 232 233 /* 234 * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 235 * as we don't use PAE40. 236 */ 237 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); 238 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); 239 } 240 241 static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) 242 { 243 #ifdef CONFIG_ISA_ARCV2 244 245 unsigned int ctrl; 246 unsigned long end; 247 248 if (!slc_exists()) 249 return; 250 251 /* 252 * The Region Flush operation is specified by CTRL.RGN_OP[11..9] 253 * - b'000 (default) is Flush, 254 * - b'001 is Invalidate if CTRL.IM == 0 255 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 256 */ 257 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 258 259 /* Don't rely on default value of IM bit */ 260 if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 261 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 262 else 263 ctrl |= SLC_CTRL_IM; 264 265 if (op & OP_INV) 266 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ 267 else 268 ctrl &= ~SLC_CTRL_RGN_OP_INV; 269 270 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 271 272 /* 273 * Lower bits are ignored, no need to clip 274 * END needs to be setup before START (latter triggers the operation) 275 * END can't be same as START, so add (l2_line_sz - 1) to sz 276 */ 277 end = paddr + sz + gd->arch.slc_line_sz - 1; 278 279 /* 280 * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) 281 * are always == 0 as we don't use PAE40, so we only setup lower ones 282 * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START) 283 */ 284 write_aux_reg(ARC_AUX_SLC_RGN_END, end); 285 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); 286 287 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 288 read_aux_reg(ARC_AUX_SLC_CTRL); 289 290 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 291 292 #endif /* CONFIG_ISA_ARCV2 */ 293 } 294 295 static void arc_ioc_setup(void) 296 { 297 /* IOC Aperture start is equal to DDR start */ 298 unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; 299 /* IOC Aperture size is equal to DDR size */ 300 long ap_size = CONFIG_SYS_SDRAM_SIZE; 301 302 flush_n_invalidate_dcache_all(); 303 304 if (!is_power_of_2(ap_size) || ap_size < 4096) 305 panic("IOC Aperture size must be power of 2 and bigger 4Kib"); 306 307 /* 308 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, 309 * so setting 0x11 implies 512M, 0x12 implies 1G... 310 */ 311 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 312 order_base_2(ap_size / 1024) - 2); 313 314 /* IOC Aperture start must be aligned to the size of the aperture */ 315 if (ap_base % ap_size != 0) 316 panic("IOC Aperture start must be aligned to the size of the aperture"); 317 318 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); 319 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); 320 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); 321 } 322 323 static void read_decode_cache_bcr_arcv2(void) 324 { 325 #ifdef CONFIG_ISA_ARCV2 326 327 union bcr_slc_cfg slc_cfg; 328 329 if (slc_exists()) { 330 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); 331 gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; 332 } 333 334 #endif /* CONFIG_ISA_ARCV2 */ 335 } 336 337 void read_decode_cache_bcr(void) 338 { 339 int dc_line_sz = 0, ic_line_sz = 0; 340 union bcr_di_cache ibcr, dbcr; 341 342 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 343 if (ibcr.fields.ver) { 344 gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; 345 if (!ic_line_sz) 346 panic("Instruction exists but line length is 0\n"); 347 } 348 349 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 350 if (dbcr.fields.ver) { 351 gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; 352 if (!dc_line_sz) 353 panic("Data cache exists but line length is 0\n"); 354 } 355 356 if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz)) 357 panic("Instruction and data cache line lengths differ\n"); 358 } 359 360 void cache_init(void) 361 { 362 read_decode_cache_bcr(); 363 364 if (is_isa_arcv2()) 365 read_decode_cache_bcr_arcv2(); 366 367 if (is_isa_arcv2() && ioc_enabled()) 368 arc_ioc_setup(); 369 370 if (is_isa_arcv2() && slc_exists()) 371 slc_upper_region_init(); 372 } 373 374 int icache_status(void) 375 { 376 return icache_enabled(); 377 } 378 379 void icache_enable(void) 380 { 381 if (icache_exists()) 382 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & 383 ~IC_CTRL_CACHE_DISABLE); 384 } 385 386 void icache_disable(void) 387 { 388 if (icache_exists()) 389 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | 390 IC_CTRL_CACHE_DISABLE); 391 } 392 393 /* IC supports only invalidation */ 394 static inline void __ic_entire_invalidate(void) 395 { 396 if (!icache_enabled()) 397 return; 398 399 /* Any write to IC_IVIC register triggers invalidation of entire I$ */ 400 write_aux_reg(ARC_AUX_IC_IVIC, 1); 401 /* 402 * As per ARC HS databook (see chapter 5.3.3.2) 403 * it is required to add 3 NOPs after each write to IC_IVIC. 404 */ 405 __builtin_arc_nop(); 406 __builtin_arc_nop(); 407 __builtin_arc_nop(); 408 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ 409 } 410 411 void invalidate_icache_all(void) 412 { 413 __ic_entire_invalidate(); 414 415 if (is_isa_arcv2()) 416 __slc_entire_op(OP_INV); 417 } 418 419 int dcache_status(void) 420 { 421 return dcache_enabled(); 422 } 423 424 void dcache_enable(void) 425 { 426 if (!dcache_exists()) 427 return; 428 429 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & 430 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); 431 } 432 433 void dcache_disable(void) 434 { 435 if (!dcache_exists()) 436 return; 437 438 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | 439 DC_CTRL_CACHE_DISABLE); 440 } 441 442 /* Common Helper for Line Operations on D-cache */ 443 static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, 444 const int cacheop) 445 { 446 unsigned int aux_cmd; 447 int num_lines; 448 449 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 450 aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; 451 452 sz += paddr & ~CACHE_LINE_MASK; 453 paddr &= CACHE_LINE_MASK; 454 455 num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz); 456 457 while (num_lines-- > 0) { 458 #if (CONFIG_ARC_MMU_VER == 3) 459 write_aux_reg(ARC_AUX_DC_PTAG, paddr); 460 #endif 461 write_aux_reg(aux_cmd, paddr); 462 paddr += gd->arch.l1_line_sz; 463 } 464 } 465 466 static void __before_dc_op(const int op) 467 { 468 unsigned int ctrl; 469 470 ctrl = read_aux_reg(ARC_AUX_DC_CTRL); 471 472 /* IM bit implies flush-n-inv, instead of vanilla inv */ 473 if (op == OP_INV) 474 ctrl &= ~DC_CTRL_INV_MODE_FLUSH; 475 else 476 ctrl |= DC_CTRL_INV_MODE_FLUSH; 477 478 write_aux_reg(ARC_AUX_DC_CTRL, ctrl); 479 } 480 481 static void __after_dc_op(const int op) 482 { 483 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ 484 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); 485 } 486 487 static inline void __dc_entire_op(const int cacheop) 488 { 489 int aux; 490 491 if (!dcache_enabled()) 492 return; 493 494 __before_dc_op(cacheop); 495 496 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 497 aux = ARC_AUX_DC_IVDC; 498 else 499 aux = ARC_AUX_DC_FLSH; 500 501 write_aux_reg(aux, 0x1); 502 503 __after_dc_op(cacheop); 504 } 505 506 static inline void __dc_line_op(unsigned long paddr, unsigned long sz, 507 const int cacheop) 508 { 509 if (!dcache_enabled()) 510 return; 511 512 __before_dc_op(cacheop); 513 __dcache_line_loop(paddr, sz, cacheop); 514 __after_dc_op(cacheop); 515 } 516 517 void invalidate_dcache_range(unsigned long start, unsigned long end) 518 { 519 if (start >= end) 520 return; 521 522 /* 523 * ARCv1 -> call __dc_line_op 524 * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 525 * ARCv2 && IOC enabled -> nothing 526 */ 527 if (!is_isa_arcv2() || !ioc_enabled()) 528 __dc_line_op(start, end - start, OP_INV); 529 530 if (is_isa_arcv2() && !ioc_enabled()) 531 __slc_rgn_op(start, end - start, OP_INV); 532 } 533 534 void flush_dcache_range(unsigned long start, unsigned long end) 535 { 536 if (start >= end) 537 return; 538 539 /* 540 * ARCv1 -> call __dc_line_op 541 * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 542 * ARCv2 && IOC enabled -> nothing 543 */ 544 if (!is_isa_arcv2() || !ioc_enabled()) 545 __dc_line_op(start, end - start, OP_FLUSH); 546 547 if (is_isa_arcv2() && !ioc_enabled()) 548 __slc_rgn_op(start, end - start, OP_FLUSH); 549 } 550 551 void flush_cache(unsigned long start, unsigned long size) 552 { 553 flush_dcache_range(start, start + size); 554 } 555 556 /* 557 * As invalidate_dcache_all() is not used in generic U-Boot code and as we 558 * don't need it in arch/arc code alone (invalidate without flush) we implement 559 * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because 560 * it's much safer. See [ NOTE 1 ] for more details. 561 */ 562 void flush_n_invalidate_dcache_all(void) 563 { 564 __dc_entire_op(OP_FLUSH_N_INV); 565 566 if (is_isa_arcv2()) 567 __slc_entire_op(OP_FLUSH_N_INV); 568 } 569 570 void flush_dcache_all(void) 571 { 572 __dc_entire_op(OP_FLUSH); 573 574 if (is_isa_arcv2()) 575 __slc_entire_op(OP_FLUSH); 576 } 577