1 /* 2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <linux/compiler.h> 10 #include <linux/kernel.h> 11 #include <linux/log2.h> 12 #include <asm/arcregs.h> 13 #include <asm/arc-bcr.h> 14 #include <asm/cache.h> 15 16 /* 17 * [ NOTE 1 ]: 18 * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable 19 * operation may result in unexpected behavior and data loss even if we flush 20 * data cache right before invalidation. That may happens if we store any context 21 * on stack (like we store BLINK register on stack before function call). 22 * BLINK register is the register where return address is automatically saved 23 * when we do function call with instructions like 'bl'. 24 * 25 * There is the real example: 26 * We may hang in the next code as we store any BLINK register on stack in 27 * invalidate_dcache_all() function. 28 * 29 * void flush_dcache_all() { 30 * __dc_entire_op(OP_FLUSH); 31 * // Other code // 32 * } 33 * 34 * void invalidate_dcache_all() { 35 * __dc_entire_op(OP_INV); 36 * // Other code // 37 * } 38 * 39 * void foo(void) { 40 * flush_dcache_all(); 41 * invalidate_dcache_all(); 42 * } 43 * 44 * Now let's see what really happens during that code execution: 45 * 46 * foo() 47 * |->> call flush_dcache_all 48 * [return address is saved to BLINK register] 49 * [push BLINK] (save to stack) ![point 1] 50 * |->> call __dc_entire_op(OP_FLUSH) 51 * [return address is saved to BLINK register] 52 * [flush L1 D$] 53 * return [jump to BLINK] 54 * <<------ 55 * [other flush_dcache_all code] 56 * [pop BLINK] (get from stack) 57 * return [jump to BLINK] 58 * <<------ 59 * |->> call invalidate_dcache_all 60 * [return address is saved to BLINK register] 61 * [push BLINK] (save to stack) ![point 2] 62 * |->> call __dc_entire_op(OP_FLUSH) 63 * [return address is saved to BLINK register] 64 * [invalidate L1 D$] ![point 3] 65 * // Oops!!! 66 * // We lose return address from invalidate_dcache_all function: 67 * // we save it to stack and invalidate L1 D$ after that! 68 * return [jump to BLINK] 69 * <<------ 70 * [other invalidate_dcache_all code] 71 * [pop BLINK] (get from stack) 72 * // we don't have this data in L1 dcache as we invalidated it in [point 3] 73 * // so we get it from next memory level (for example DDR memory) 74 * // but in the memory we have value which we save in [point 1], which 75 * // is return address from flush_dcache_all function (instead of 76 * // address from current invalidate_dcache_all function which we 77 * // saved in [point 2] !) 78 * return [jump to BLINK] 79 * <<------ 80 * // As BLINK points to invalidate_dcache_all, we call it again and 81 * // loop forever. 82 * 83 * Fortunately we may fix that by using flush & invalidation of D$ with a single 84 * one instruction (instead of flush and invalidation instructions pair) and 85 * enabling force function inline with '__attribute__((always_inline))' gcc 86 * attribute to avoid any function call (and BLINK store) between cache flush 87 * and disable. 88 */ 89 90 /* Bit values in IC_CTRL */ 91 #define IC_CTRL_CACHE_DISABLE BIT(0) 92 93 /* Bit values in DC_CTRL */ 94 #define DC_CTRL_CACHE_DISABLE BIT(0) 95 #define DC_CTRL_INV_MODE_FLUSH BIT(6) 96 #define DC_CTRL_FLUSH_STATUS BIT(8) 97 #define CACHE_VER_NUM_MASK 0xF 98 99 #define OP_INV BIT(0) 100 #define OP_FLUSH BIT(1) 101 #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV) 102 103 /* Bit val in SLC_CONTROL */ 104 #define SLC_CTRL_DIS 0x001 105 #define SLC_CTRL_IM 0x040 106 #define SLC_CTRL_BUSY 0x100 107 #define SLC_CTRL_RGN_OP_INV 0x200 108 109 /* 110 * By default that variable will fall into .bss section. 111 * But .bss section is not relocated and so it will be initilized before 112 * relocation but will be used after being zeroed. 113 */ 114 int l1_line_sz __section(".data"); 115 bool dcache_exists __section(".data") = false; 116 bool icache_exists __section(".data") = false; 117 118 #define CACHE_LINE_MASK (~(l1_line_sz - 1)) 119 120 #ifdef CONFIG_ISA_ARCV2 121 int slc_line_sz __section(".data"); 122 bool slc_exists __section(".data") = false; 123 bool ioc_exists __section(".data") = false; 124 bool pae_exists __section(".data") = false; 125 126 /* To force enable IOC set ioc_enable to 'true' */ 127 bool ioc_enable __section(".data") = false; 128 129 void read_decode_mmu_bcr(void) 130 { 131 /* TODO: should we compare mmu version from BCR and from CONFIG? */ 132 #if (CONFIG_ARC_MMU_VER >= 4) 133 union bcr_mmu_4 mmu4; 134 135 mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR); 136 137 pae_exists = !!mmu4.fields.pae; 138 #endif /* (CONFIG_ARC_MMU_VER >= 4) */ 139 } 140 141 static void __slc_entire_op(const int op) 142 { 143 unsigned int ctrl; 144 145 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 146 147 if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 148 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 149 else 150 ctrl |= SLC_CTRL_IM; 151 152 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 153 154 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 155 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); 156 else 157 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); 158 159 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 160 read_aux_reg(ARC_AUX_SLC_CTRL); 161 162 /* Important to wait for flush to complete */ 163 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 164 } 165 166 static void slc_upper_region_init(void) 167 { 168 /* 169 * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 170 * as we don't use PAE40. 171 */ 172 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); 173 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); 174 } 175 176 static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) 177 { 178 unsigned int ctrl; 179 unsigned long end; 180 181 /* 182 * The Region Flush operation is specified by CTRL.RGN_OP[11..9] 183 * - b'000 (default) is Flush, 184 * - b'001 is Invalidate if CTRL.IM == 0 185 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 186 */ 187 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 188 189 /* Don't rely on default value of IM bit */ 190 if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 191 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 192 else 193 ctrl |= SLC_CTRL_IM; 194 195 if (op & OP_INV) 196 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ 197 else 198 ctrl &= ~SLC_CTRL_RGN_OP_INV; 199 200 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 201 202 /* 203 * Lower bits are ignored, no need to clip 204 * END needs to be setup before START (latter triggers the operation) 205 * END can't be same as START, so add (l2_line_sz - 1) to sz 206 */ 207 end = paddr + sz + slc_line_sz - 1; 208 209 /* 210 * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) 211 * are always == 0 as we don't use PAE40, so we only setup lower ones 212 * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START) 213 */ 214 write_aux_reg(ARC_AUX_SLC_RGN_END, end); 215 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); 216 217 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 218 read_aux_reg(ARC_AUX_SLC_CTRL); 219 220 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 221 } 222 223 static void arc_ioc_setup(void) 224 { 225 /* IOC Aperture start is equal to DDR start */ 226 unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; 227 /* IOC Aperture size is equal to DDR size */ 228 long ap_size = CONFIG_SYS_SDRAM_SIZE; 229 230 flush_n_invalidate_dcache_all(); 231 232 if (!is_power_of_2(ap_size) || ap_size < 4096) 233 panic("IOC Aperture size must be power of 2 and bigger 4Kib"); 234 235 /* 236 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, 237 * so setting 0x11 implies 512M, 0x12 implies 1G... 238 */ 239 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 240 order_base_2(ap_size / 1024) - 2); 241 242 /* IOC Aperture start must be aligned to the size of the aperture */ 243 if (ap_base % ap_size != 0) 244 panic("IOC Aperture start must be aligned to the size of the aperture"); 245 246 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); 247 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); 248 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); 249 } 250 #endif /* CONFIG_ISA_ARCV2 */ 251 252 #ifdef CONFIG_ISA_ARCV2 253 static void read_decode_cache_bcr_arcv2(void) 254 { 255 union bcr_slc_cfg slc_cfg; 256 union bcr_clust_cfg cbcr; 257 union bcr_generic sbcr; 258 259 sbcr.word = read_aux_reg(ARC_BCR_SLC); 260 if (sbcr.fields.ver) { 261 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); 262 slc_exists = true; 263 slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; 264 } 265 266 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); 267 if (cbcr.fields.c && ioc_enable) 268 ioc_exists = true; 269 } 270 #endif 271 272 void read_decode_cache_bcr(void) 273 { 274 int dc_line_sz = 0, ic_line_sz = 0; 275 union bcr_di_cache ibcr, dbcr; 276 277 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 278 if (ibcr.fields.ver) { 279 icache_exists = true; 280 l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; 281 if (!ic_line_sz) 282 panic("Instruction exists but line length is 0\n"); 283 } 284 285 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 286 if (dbcr.fields.ver) { 287 dcache_exists = true; 288 l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; 289 if (!dc_line_sz) 290 panic("Data cache exists but line length is 0\n"); 291 } 292 293 if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz)) 294 panic("Instruction and data cache line lengths differ\n"); 295 } 296 297 void cache_init(void) 298 { 299 read_decode_cache_bcr(); 300 301 #ifdef CONFIG_ISA_ARCV2 302 read_decode_cache_bcr_arcv2(); 303 304 if (ioc_exists) 305 arc_ioc_setup(); 306 307 read_decode_mmu_bcr(); 308 309 /* 310 * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist 311 * only if PAE exists in current HW. So we had to check pae_exist 312 * before using them. 313 */ 314 if (slc_exists && pae_exists) 315 slc_upper_region_init(); 316 #endif /* CONFIG_ISA_ARCV2 */ 317 } 318 319 int icache_status(void) 320 { 321 if (!icache_exists) 322 return 0; 323 324 if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) 325 return 0; 326 else 327 return 1; 328 } 329 330 void icache_enable(void) 331 { 332 if (icache_exists) 333 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & 334 ~IC_CTRL_CACHE_DISABLE); 335 } 336 337 void icache_disable(void) 338 { 339 if (icache_exists) 340 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | 341 IC_CTRL_CACHE_DISABLE); 342 } 343 344 /* IC supports only invalidation */ 345 static inline void __ic_entire_invalidate(void) 346 { 347 if (!icache_status()) 348 return; 349 350 /* Any write to IC_IVIC register triggers invalidation of entire I$ */ 351 write_aux_reg(ARC_AUX_IC_IVIC, 1); 352 /* 353 * As per ARC HS databook (see chapter 5.3.3.2) 354 * it is required to add 3 NOPs after each write to IC_IVIC. 355 */ 356 __builtin_arc_nop(); 357 __builtin_arc_nop(); 358 __builtin_arc_nop(); 359 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ 360 } 361 362 void invalidate_icache_all(void) 363 { 364 __ic_entire_invalidate(); 365 366 #ifdef CONFIG_ISA_ARCV2 367 if (slc_exists) 368 __slc_entire_op(OP_INV); 369 #endif 370 } 371 372 int dcache_status(void) 373 { 374 if (!dcache_exists) 375 return 0; 376 377 if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) 378 return 0; 379 else 380 return 1; 381 } 382 383 void dcache_enable(void) 384 { 385 if (!dcache_exists) 386 return; 387 388 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & 389 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); 390 } 391 392 void dcache_disable(void) 393 { 394 if (!dcache_exists) 395 return; 396 397 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | 398 DC_CTRL_CACHE_DISABLE); 399 } 400 401 #ifndef CONFIG_SYS_DCACHE_OFF 402 /* Common Helper for Line Operations on D-cache */ 403 static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, 404 const int cacheop) 405 { 406 unsigned int aux_cmd; 407 int num_lines; 408 409 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 410 aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; 411 412 sz += paddr & ~CACHE_LINE_MASK; 413 paddr &= CACHE_LINE_MASK; 414 415 num_lines = DIV_ROUND_UP(sz, l1_line_sz); 416 417 while (num_lines-- > 0) { 418 #if (CONFIG_ARC_MMU_VER == 3) 419 write_aux_reg(ARC_AUX_DC_PTAG, paddr); 420 #endif 421 write_aux_reg(aux_cmd, paddr); 422 paddr += l1_line_sz; 423 } 424 } 425 426 static void __before_dc_op(const int op) 427 { 428 unsigned int ctrl; 429 430 ctrl = read_aux_reg(ARC_AUX_DC_CTRL); 431 432 /* IM bit implies flush-n-inv, instead of vanilla inv */ 433 if (op == OP_INV) 434 ctrl &= ~DC_CTRL_INV_MODE_FLUSH; 435 else 436 ctrl |= DC_CTRL_INV_MODE_FLUSH; 437 438 write_aux_reg(ARC_AUX_DC_CTRL, ctrl); 439 } 440 441 static void __after_dc_op(const int op) 442 { 443 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ 444 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); 445 } 446 447 static inline void __dc_entire_op(const int cacheop) 448 { 449 int aux; 450 451 __before_dc_op(cacheop); 452 453 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 454 aux = ARC_AUX_DC_IVDC; 455 else 456 aux = ARC_AUX_DC_FLSH; 457 458 write_aux_reg(aux, 0x1); 459 460 __after_dc_op(cacheop); 461 } 462 463 static inline void __dc_line_op(unsigned long paddr, unsigned long sz, 464 const int cacheop) 465 { 466 __before_dc_op(cacheop); 467 __dcache_line_loop(paddr, sz, cacheop); 468 __after_dc_op(cacheop); 469 } 470 #else 471 #define __dc_entire_op(cacheop) 472 #define __dc_line_op(paddr, sz, cacheop) 473 #endif /* !CONFIG_SYS_DCACHE_OFF */ 474 475 void invalidate_dcache_range(unsigned long start, unsigned long end) 476 { 477 if (start >= end) 478 return; 479 480 #ifdef CONFIG_ISA_ARCV2 481 if (!ioc_exists) 482 #endif 483 __dc_line_op(start, end - start, OP_INV); 484 485 #ifdef CONFIG_ISA_ARCV2 486 if (slc_exists && !ioc_exists) 487 __slc_rgn_op(start, end - start, OP_INV); 488 #endif 489 } 490 491 void flush_dcache_range(unsigned long start, unsigned long end) 492 { 493 if (start >= end) 494 return; 495 496 #ifdef CONFIG_ISA_ARCV2 497 if (!ioc_exists) 498 #endif 499 __dc_line_op(start, end - start, OP_FLUSH); 500 501 #ifdef CONFIG_ISA_ARCV2 502 if (slc_exists && !ioc_exists) 503 __slc_rgn_op(start, end - start, OP_FLUSH); 504 #endif 505 } 506 507 void flush_cache(unsigned long start, unsigned long size) 508 { 509 flush_dcache_range(start, start + size); 510 } 511 512 /* 513 * As invalidate_dcache_all() is not used in generic U-Boot code and as we 514 * don't need it in arch/arc code alone (invalidate without flush) we implement 515 * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because 516 * it's much safer. See [ NOTE 1 ] for more details. 517 */ 518 void flush_n_invalidate_dcache_all(void) 519 { 520 __dc_entire_op(OP_FLUSH_N_INV); 521 522 #ifdef CONFIG_ISA_ARCV2 523 if (slc_exists) 524 __slc_entire_op(OP_FLUSH_N_INV); 525 #endif 526 } 527 528 void flush_dcache_all(void) 529 { 530 __dc_entire_op(OP_FLUSH); 531 532 #ifdef CONFIG_ISA_ARCV2 533 if (slc_exists) 534 __slc_entire_op(OP_FLUSH); 535 #endif 536 } 537