1 /* 2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <linux/compiler.h> 10 #include <linux/kernel.h> 11 #include <linux/log2.h> 12 #include <asm/arcregs.h> 13 #include <asm/arc-bcr.h> 14 #include <asm/cache.h> 15 16 /* 17 * [ NOTE 1 ]: 18 * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable 19 * operation may result in unexpected behavior and data loss even if we flush 20 * data cache right before invalidation. That may happens if we store any context 21 * on stack (like we store BLINK register on stack before function call). 22 * BLINK register is the register where return address is automatically saved 23 * when we do function call with instructions like 'bl'. 24 * 25 * There is the real example: 26 * We may hang in the next code as we store any BLINK register on stack in 27 * invalidate_dcache_all() function. 28 * 29 * void flush_dcache_all() { 30 * __dc_entire_op(OP_FLUSH); 31 * // Other code // 32 * } 33 * 34 * void invalidate_dcache_all() { 35 * __dc_entire_op(OP_INV); 36 * // Other code // 37 * } 38 * 39 * void foo(void) { 40 * flush_dcache_all(); 41 * invalidate_dcache_all(); 42 * } 43 * 44 * Now let's see what really happens during that code execution: 45 * 46 * foo() 47 * |->> call flush_dcache_all 48 * [return address is saved to BLINK register] 49 * [push BLINK] (save to stack) ![point 1] 50 * |->> call __dc_entire_op(OP_FLUSH) 51 * [return address is saved to BLINK register] 52 * [flush L1 D$] 53 * return [jump to BLINK] 54 * <<------ 55 * [other flush_dcache_all code] 56 * [pop BLINK] (get from stack) 57 * return [jump to BLINK] 58 * <<------ 59 * |->> call invalidate_dcache_all 60 * [return address is saved to BLINK register] 61 * [push BLINK] (save to stack) ![point 2] 62 * |->> call __dc_entire_op(OP_FLUSH) 63 * [return address is saved to BLINK register] 64 * [invalidate L1 D$] ![point 3] 65 * // Oops!!! 66 * // We lose return address from invalidate_dcache_all function: 67 * // we save it to stack and invalidate L1 D$ after that! 68 * return [jump to BLINK] 69 * <<------ 70 * [other invalidate_dcache_all code] 71 * [pop BLINK] (get from stack) 72 * // we don't have this data in L1 dcache as we invalidated it in [point 3] 73 * // so we get it from next memory level (for example DDR memory) 74 * // but in the memory we have value which we save in [point 1], which 75 * // is return address from flush_dcache_all function (instead of 76 * // address from current invalidate_dcache_all function which we 77 * // saved in [point 2] !) 78 * return [jump to BLINK] 79 * <<------ 80 * // As BLINK points to invalidate_dcache_all, we call it again and 81 * // loop forever. 82 * 83 * Fortunately we may fix that by using flush & invalidation of D$ with a single 84 * one instruction (instead of flush and invalidation instructions pair) and 85 * enabling force function inline with '__attribute__((always_inline))' gcc 86 * attribute to avoid any function call (and BLINK store) between cache flush 87 * and disable. 88 */ 89 90 DECLARE_GLOBAL_DATA_PTR; 91 92 /* Bit values in IC_CTRL */ 93 #define IC_CTRL_CACHE_DISABLE BIT(0) 94 95 /* Bit values in DC_CTRL */ 96 #define DC_CTRL_CACHE_DISABLE BIT(0) 97 #define DC_CTRL_INV_MODE_FLUSH BIT(6) 98 #define DC_CTRL_FLUSH_STATUS BIT(8) 99 100 #define OP_INV BIT(0) 101 #define OP_FLUSH BIT(1) 102 #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV) 103 104 /* Bit val in SLC_CONTROL */ 105 #define SLC_CTRL_DIS 0x001 106 #define SLC_CTRL_IM 0x040 107 #define SLC_CTRL_BUSY 0x100 108 #define SLC_CTRL_RGN_OP_INV 0x200 109 110 /* 111 * By default that variable will fall into .bss section. 112 * But .bss section is not relocated and so it will be initilized before 113 * relocation but will be used after being zeroed. 114 */ 115 #define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1)) 116 117 bool ioc_exists __section(".data") = false; 118 119 /* To force enable IOC set ioc_enable to 'true' */ 120 bool ioc_enable __section(".data") = false; 121 122 static inline bool pae_exists(void) 123 { 124 /* TODO: should we compare mmu version from BCR and from CONFIG? */ 125 #if (CONFIG_ARC_MMU_VER >= 4) 126 union bcr_mmu_4 mmu4; 127 128 mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR); 129 130 if (mmu4.fields.pae) 131 return true; 132 #endif /* (CONFIG_ARC_MMU_VER >= 4) */ 133 134 return false; 135 } 136 137 static inline bool icache_exists(void) 138 { 139 union bcr_di_cache ibcr; 140 141 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 142 return !!ibcr.fields.ver; 143 } 144 145 static inline bool dcache_exists(void) 146 { 147 union bcr_di_cache dbcr; 148 149 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 150 return !!dbcr.fields.ver; 151 } 152 153 static inline bool slc_exists(void) 154 { 155 if (is_isa_arcv2()) { 156 union bcr_generic sbcr; 157 158 sbcr.word = read_aux_reg(ARC_BCR_SLC); 159 return !!sbcr.fields.ver; 160 } 161 162 return false; 163 } 164 165 static void __slc_entire_op(const int op) 166 { 167 unsigned int ctrl; 168 169 if (!slc_exists()) 170 return; 171 172 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 173 174 if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 175 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 176 else 177 ctrl |= SLC_CTRL_IM; 178 179 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 180 181 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 182 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); 183 else 184 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); 185 186 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 187 read_aux_reg(ARC_AUX_SLC_CTRL); 188 189 /* Important to wait for flush to complete */ 190 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 191 } 192 193 static void slc_upper_region_init(void) 194 { 195 /* 196 * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist 197 * only if PAE exists in current HW. So we had to check pae_exist 198 * before using them. 199 */ 200 if (!pae_exists()) 201 return; 202 203 /* 204 * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 205 * as we don't use PAE40. 206 */ 207 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); 208 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); 209 } 210 211 static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) 212 { 213 #ifdef CONFIG_ISA_ARCV2 214 215 unsigned int ctrl; 216 unsigned long end; 217 218 if (!slc_exists()) 219 return; 220 221 /* 222 * The Region Flush operation is specified by CTRL.RGN_OP[11..9] 223 * - b'000 (default) is Flush, 224 * - b'001 is Invalidate if CTRL.IM == 0 225 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 226 */ 227 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 228 229 /* Don't rely on default value of IM bit */ 230 if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 231 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 232 else 233 ctrl |= SLC_CTRL_IM; 234 235 if (op & OP_INV) 236 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ 237 else 238 ctrl &= ~SLC_CTRL_RGN_OP_INV; 239 240 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 241 242 /* 243 * Lower bits are ignored, no need to clip 244 * END needs to be setup before START (latter triggers the operation) 245 * END can't be same as START, so add (l2_line_sz - 1) to sz 246 */ 247 end = paddr + sz + gd->arch.slc_line_sz - 1; 248 249 /* 250 * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) 251 * are always == 0 as we don't use PAE40, so we only setup lower ones 252 * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START) 253 */ 254 write_aux_reg(ARC_AUX_SLC_RGN_END, end); 255 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); 256 257 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 258 read_aux_reg(ARC_AUX_SLC_CTRL); 259 260 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 261 262 #endif /* CONFIG_ISA_ARCV2 */ 263 } 264 265 static void arc_ioc_setup(void) 266 { 267 /* IOC Aperture start is equal to DDR start */ 268 unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; 269 /* IOC Aperture size is equal to DDR size */ 270 long ap_size = CONFIG_SYS_SDRAM_SIZE; 271 272 flush_n_invalidate_dcache_all(); 273 274 if (!is_power_of_2(ap_size) || ap_size < 4096) 275 panic("IOC Aperture size must be power of 2 and bigger 4Kib"); 276 277 /* 278 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, 279 * so setting 0x11 implies 512M, 0x12 implies 1G... 280 */ 281 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 282 order_base_2(ap_size / 1024) - 2); 283 284 /* IOC Aperture start must be aligned to the size of the aperture */ 285 if (ap_base % ap_size != 0) 286 panic("IOC Aperture start must be aligned to the size of the aperture"); 287 288 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); 289 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); 290 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); 291 } 292 293 static void read_decode_cache_bcr_arcv2(void) 294 { 295 #ifdef CONFIG_ISA_ARCV2 296 297 union bcr_slc_cfg slc_cfg; 298 union bcr_clust_cfg cbcr; 299 300 if (slc_exists()) { 301 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); 302 gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; 303 } 304 305 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); 306 if (cbcr.fields.c && ioc_enable) 307 ioc_exists = true; 308 309 #endif /* CONFIG_ISA_ARCV2 */ 310 } 311 312 void read_decode_cache_bcr(void) 313 { 314 int dc_line_sz = 0, ic_line_sz = 0; 315 union bcr_di_cache ibcr, dbcr; 316 317 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 318 if (ibcr.fields.ver) { 319 gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; 320 if (!ic_line_sz) 321 panic("Instruction exists but line length is 0\n"); 322 } 323 324 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 325 if (dbcr.fields.ver) { 326 gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; 327 if (!dc_line_sz) 328 panic("Data cache exists but line length is 0\n"); 329 } 330 331 if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz)) 332 panic("Instruction and data cache line lengths differ\n"); 333 } 334 335 void cache_init(void) 336 { 337 read_decode_cache_bcr(); 338 339 if (is_isa_arcv2()) 340 read_decode_cache_bcr_arcv2(); 341 342 if (is_isa_arcv2() && ioc_exists) 343 arc_ioc_setup(); 344 345 if (is_isa_arcv2() && slc_exists()) 346 slc_upper_region_init(); 347 } 348 349 int icache_status(void) 350 { 351 if (!icache_exists()) 352 return 0; 353 354 if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) 355 return 0; 356 else 357 return 1; 358 } 359 360 void icache_enable(void) 361 { 362 if (icache_exists()) 363 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & 364 ~IC_CTRL_CACHE_DISABLE); 365 } 366 367 void icache_disable(void) 368 { 369 if (icache_exists()) 370 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | 371 IC_CTRL_CACHE_DISABLE); 372 } 373 374 /* IC supports only invalidation */ 375 static inline void __ic_entire_invalidate(void) 376 { 377 if (!icache_status()) 378 return; 379 380 /* Any write to IC_IVIC register triggers invalidation of entire I$ */ 381 write_aux_reg(ARC_AUX_IC_IVIC, 1); 382 /* 383 * As per ARC HS databook (see chapter 5.3.3.2) 384 * it is required to add 3 NOPs after each write to IC_IVIC. 385 */ 386 __builtin_arc_nop(); 387 __builtin_arc_nop(); 388 __builtin_arc_nop(); 389 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ 390 } 391 392 void invalidate_icache_all(void) 393 { 394 __ic_entire_invalidate(); 395 396 if (is_isa_arcv2()) 397 __slc_entire_op(OP_INV); 398 } 399 400 int dcache_status(void) 401 { 402 if (!dcache_exists()) 403 return 0; 404 405 if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) 406 return 0; 407 else 408 return 1; 409 } 410 411 void dcache_enable(void) 412 { 413 if (!dcache_exists()) 414 return; 415 416 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & 417 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); 418 } 419 420 void dcache_disable(void) 421 { 422 if (!dcache_exists()) 423 return; 424 425 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | 426 DC_CTRL_CACHE_DISABLE); 427 } 428 429 /* Common Helper for Line Operations on D-cache */ 430 static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, 431 const int cacheop) 432 { 433 unsigned int aux_cmd; 434 int num_lines; 435 436 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 437 aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; 438 439 sz += paddr & ~CACHE_LINE_MASK; 440 paddr &= CACHE_LINE_MASK; 441 442 num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz); 443 444 while (num_lines-- > 0) { 445 #if (CONFIG_ARC_MMU_VER == 3) 446 write_aux_reg(ARC_AUX_DC_PTAG, paddr); 447 #endif 448 write_aux_reg(aux_cmd, paddr); 449 paddr += gd->arch.l1_line_sz; 450 } 451 } 452 453 static void __before_dc_op(const int op) 454 { 455 unsigned int ctrl; 456 457 ctrl = read_aux_reg(ARC_AUX_DC_CTRL); 458 459 /* IM bit implies flush-n-inv, instead of vanilla inv */ 460 if (op == OP_INV) 461 ctrl &= ~DC_CTRL_INV_MODE_FLUSH; 462 else 463 ctrl |= DC_CTRL_INV_MODE_FLUSH; 464 465 write_aux_reg(ARC_AUX_DC_CTRL, ctrl); 466 } 467 468 static void __after_dc_op(const int op) 469 { 470 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ 471 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); 472 } 473 474 static inline void __dc_entire_op(const int cacheop) 475 { 476 int aux; 477 478 if (!dcache_status()) 479 return; 480 481 __before_dc_op(cacheop); 482 483 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 484 aux = ARC_AUX_DC_IVDC; 485 else 486 aux = ARC_AUX_DC_FLSH; 487 488 write_aux_reg(aux, 0x1); 489 490 __after_dc_op(cacheop); 491 } 492 493 static inline void __dc_line_op(unsigned long paddr, unsigned long sz, 494 const int cacheop) 495 { 496 if (!dcache_status()) 497 return; 498 499 __before_dc_op(cacheop); 500 __dcache_line_loop(paddr, sz, cacheop); 501 __after_dc_op(cacheop); 502 } 503 504 void invalidate_dcache_range(unsigned long start, unsigned long end) 505 { 506 if (start >= end) 507 return; 508 509 /* 510 * ARCv1 -> call __dc_line_op 511 * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 512 * ARCv2 && IOC enabled -> nothing 513 */ 514 if (!is_isa_arcv2() || !ioc_exists) 515 __dc_line_op(start, end - start, OP_INV); 516 517 if (is_isa_arcv2() && !ioc_exists) 518 __slc_rgn_op(start, end - start, OP_INV); 519 } 520 521 void flush_dcache_range(unsigned long start, unsigned long end) 522 { 523 if (start >= end) 524 return; 525 526 /* 527 * ARCv1 -> call __dc_line_op 528 * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 529 * ARCv2 && IOC enabled -> nothing 530 */ 531 if (!is_isa_arcv2() || !ioc_exists) 532 __dc_line_op(start, end - start, OP_FLUSH); 533 534 if (is_isa_arcv2() && !ioc_exists) 535 __slc_rgn_op(start, end - start, OP_FLUSH); 536 } 537 538 void flush_cache(unsigned long start, unsigned long size) 539 { 540 flush_dcache_range(start, start + size); 541 } 542 543 /* 544 * As invalidate_dcache_all() is not used in generic U-Boot code and as we 545 * don't need it in arch/arc code alone (invalidate without flush) we implement 546 * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because 547 * it's much safer. See [ NOTE 1 ] for more details. 548 */ 549 void flush_n_invalidate_dcache_all(void) 550 { 551 __dc_entire_op(OP_FLUSH_N_INV); 552 553 if (is_isa_arcv2()) 554 __slc_entire_op(OP_FLUSH_N_INV); 555 } 556 557 void flush_dcache_all(void) 558 { 559 __dc_entire_op(OP_FLUSH); 560 561 if (is_isa_arcv2()) 562 __slc_entire_op(OP_FLUSH); 563 } 564