1660d5f0dSAlexey Brodkin /* 2660d5f0dSAlexey Brodkin * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3660d5f0dSAlexey Brodkin * 4660d5f0dSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5660d5f0dSAlexey Brodkin */ 6660d5f0dSAlexey Brodkin 7660d5f0dSAlexey Brodkin #include <config.h> 8379b3280SAlexey Brodkin #include <common.h> 9ef639e6fSAlexey Brodkin #include <linux/compiler.h> 10ef639e6fSAlexey Brodkin #include <linux/kernel.h> 1197a63144SAlexey Brodkin #include <linux/log2.h> 12660d5f0dSAlexey Brodkin #include <asm/arcregs.h> 1388ae27edSEugeniy Paltsev #include <asm/arc-bcr.h> 14205e7a7bSAlexey Brodkin #include <asm/cache.h> 15660d5f0dSAlexey Brodkin 16c27814beSEugeniy Paltsev /* 17c27814beSEugeniy Paltsev * [ NOTE 1 ]: 18c27814beSEugeniy Paltsev * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable 19c27814beSEugeniy Paltsev * operation may result in unexpected behavior and data loss even if we flush 20c27814beSEugeniy Paltsev * data cache right before invalidation. That may happens if we store any context 21c27814beSEugeniy Paltsev * on stack (like we store BLINK register on stack before function call). 22c27814beSEugeniy Paltsev * BLINK register is the register where return address is automatically saved 23c27814beSEugeniy Paltsev * when we do function call with instructions like 'bl'. 24c27814beSEugeniy Paltsev * 25c27814beSEugeniy Paltsev * There is the real example: 26c27814beSEugeniy Paltsev * We may hang in the next code as we store any BLINK register on stack in 27c27814beSEugeniy Paltsev * invalidate_dcache_all() function. 28c27814beSEugeniy Paltsev * 29c27814beSEugeniy Paltsev * void flush_dcache_all() { 30c27814beSEugeniy Paltsev * __dc_entire_op(OP_FLUSH); 31c27814beSEugeniy Paltsev * // Other code // 32c27814beSEugeniy Paltsev * } 33c27814beSEugeniy Paltsev * 34c27814beSEugeniy Paltsev * void invalidate_dcache_all() { 35c27814beSEugeniy Paltsev * __dc_entire_op(OP_INV); 36c27814beSEugeniy Paltsev * // Other code // 37c27814beSEugeniy Paltsev * } 38c27814beSEugeniy Paltsev * 39c27814beSEugeniy Paltsev * void foo(void) { 40c27814beSEugeniy Paltsev * flush_dcache_all(); 41c27814beSEugeniy Paltsev * invalidate_dcache_all(); 42c27814beSEugeniy Paltsev * } 43c27814beSEugeniy Paltsev * 44c27814beSEugeniy Paltsev * Now let's see what really happens during that code execution: 45c27814beSEugeniy Paltsev * 46c27814beSEugeniy Paltsev * foo() 47c27814beSEugeniy Paltsev * |->> call flush_dcache_all 48c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 49c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 1] 50c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 51c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 52c27814beSEugeniy Paltsev * [flush L1 D$] 53c27814beSEugeniy Paltsev * return [jump to BLINK] 54c27814beSEugeniy Paltsev * <<------ 55c27814beSEugeniy Paltsev * [other flush_dcache_all code] 56c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 57c27814beSEugeniy Paltsev * return [jump to BLINK] 58c27814beSEugeniy Paltsev * <<------ 59c27814beSEugeniy Paltsev * |->> call invalidate_dcache_all 60c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 61c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 2] 62c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 63c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 64c27814beSEugeniy Paltsev * [invalidate L1 D$] ![point 3] 65c27814beSEugeniy Paltsev * // Oops!!! 66c27814beSEugeniy Paltsev * // We lose return address from invalidate_dcache_all function: 67c27814beSEugeniy Paltsev * // we save it to stack and invalidate L1 D$ after that! 68c27814beSEugeniy Paltsev * return [jump to BLINK] 69c27814beSEugeniy Paltsev * <<------ 70c27814beSEugeniy Paltsev * [other invalidate_dcache_all code] 71c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 72c27814beSEugeniy Paltsev * // we don't have this data in L1 dcache as we invalidated it in [point 3] 73c27814beSEugeniy Paltsev * // so we get it from next memory level (for example DDR memory) 74c27814beSEugeniy Paltsev * // but in the memory we have value which we save in [point 1], which 75c27814beSEugeniy Paltsev * // is return address from flush_dcache_all function (instead of 76c27814beSEugeniy Paltsev * // address from current invalidate_dcache_all function which we 77c27814beSEugeniy Paltsev * // saved in [point 2] !) 78c27814beSEugeniy Paltsev * return [jump to BLINK] 79c27814beSEugeniy Paltsev * <<------ 80c27814beSEugeniy Paltsev * // As BLINK points to invalidate_dcache_all, we call it again and 81c27814beSEugeniy Paltsev * // loop forever. 82c27814beSEugeniy Paltsev * 83c27814beSEugeniy Paltsev * Fortunately we may fix that by using flush & invalidation of D$ with a single 84c27814beSEugeniy Paltsev * one instruction (instead of flush and invalidation instructions pair) and 85c27814beSEugeniy Paltsev * enabling force function inline with '__attribute__((always_inline))' gcc 86c27814beSEugeniy Paltsev * attribute to avoid any function call (and BLINK store) between cache flush 87c27814beSEugeniy Paltsev * and disable. 88c27814beSEugeniy Paltsev */ 89c27814beSEugeniy Paltsev 90bf8974edSEugeniy Paltsev DECLARE_GLOBAL_DATA_PTR; 91bf8974edSEugeniy Paltsev 92660d5f0dSAlexey Brodkin /* Bit values in IC_CTRL */ 9319b10a42SEugeniy Paltsev #define IC_CTRL_CACHE_DISABLE BIT(0) 94660d5f0dSAlexey Brodkin 95660d5f0dSAlexey Brodkin /* Bit values in DC_CTRL */ 9619b10a42SEugeniy Paltsev #define DC_CTRL_CACHE_DISABLE BIT(0) 9719b10a42SEugeniy Paltsev #define DC_CTRL_INV_MODE_FLUSH BIT(6) 9819b10a42SEugeniy Paltsev #define DC_CTRL_FLUSH_STATUS BIT(8) 99660d5f0dSAlexey Brodkin 1005d7a24d6SEugeniy Paltsev #define OP_INV BIT(0) 1015d7a24d6SEugeniy Paltsev #define OP_FLUSH BIT(1) 1025d7a24d6SEugeniy Paltsev #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV) 103ef639e6fSAlexey Brodkin 10441cada4dSEugeniy Paltsev /* Bit val in SLC_CONTROL */ 10541cada4dSEugeniy Paltsev #define SLC_CTRL_DIS 0x001 10641cada4dSEugeniy Paltsev #define SLC_CTRL_IM 0x040 10741cada4dSEugeniy Paltsev #define SLC_CTRL_BUSY 0x100 10841cada4dSEugeniy Paltsev #define SLC_CTRL_RGN_OP_INV 0x200 10941cada4dSEugeniy Paltsev 110bf8974edSEugeniy Paltsev #define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1)) 111379b3280SAlexey Brodkin 11275790873SEugeniy Paltsev static inline bool pae_exists(void) 113ef639e6fSAlexey Brodkin { 11441cada4dSEugeniy Paltsev /* TODO: should we compare mmu version from BCR and from CONFIG? */ 11541cada4dSEugeniy Paltsev #if (CONFIG_ARC_MMU_VER >= 4) 11688ae27edSEugeniy Paltsev union bcr_mmu_4 mmu4; 117ef639e6fSAlexey Brodkin 11888ae27edSEugeniy Paltsev mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR); 119ef639e6fSAlexey Brodkin 12075790873SEugeniy Paltsev if (mmu4.fields.pae) 12175790873SEugeniy Paltsev return true; 12241cada4dSEugeniy Paltsev #endif /* (CONFIG_ARC_MMU_VER >= 4) */ 12375790873SEugeniy Paltsev 12475790873SEugeniy Paltsev return false; 12575790873SEugeniy Paltsev } 12675790873SEugeniy Paltsev 12775790873SEugeniy Paltsev static inline bool icache_exists(void) 12875790873SEugeniy Paltsev { 12975790873SEugeniy Paltsev union bcr_di_cache ibcr; 13075790873SEugeniy Paltsev 13175790873SEugeniy Paltsev ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 13275790873SEugeniy Paltsev return !!ibcr.fields.ver; 13375790873SEugeniy Paltsev } 13475790873SEugeniy Paltsev 135*c75eeb0bSEugeniy Paltsev static inline bool icache_enabled(void) 136*c75eeb0bSEugeniy Paltsev { 137*c75eeb0bSEugeniy Paltsev if (!icache_exists()) 138*c75eeb0bSEugeniy Paltsev return false; 139*c75eeb0bSEugeniy Paltsev 140*c75eeb0bSEugeniy Paltsev return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE); 141*c75eeb0bSEugeniy Paltsev } 142*c75eeb0bSEugeniy Paltsev 14375790873SEugeniy Paltsev static inline bool dcache_exists(void) 14475790873SEugeniy Paltsev { 14575790873SEugeniy Paltsev union bcr_di_cache dbcr; 14675790873SEugeniy Paltsev 14775790873SEugeniy Paltsev dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 14875790873SEugeniy Paltsev return !!dbcr.fields.ver; 14975790873SEugeniy Paltsev } 15075790873SEugeniy Paltsev 151*c75eeb0bSEugeniy Paltsev static inline bool dcache_enabled(void) 152*c75eeb0bSEugeniy Paltsev { 153*c75eeb0bSEugeniy Paltsev if (!dcache_exists()) 154*c75eeb0bSEugeniy Paltsev return false; 155*c75eeb0bSEugeniy Paltsev 156*c75eeb0bSEugeniy Paltsev return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE); 157*c75eeb0bSEugeniy Paltsev } 158*c75eeb0bSEugeniy Paltsev 15975790873SEugeniy Paltsev static inline bool slc_exists(void) 16075790873SEugeniy Paltsev { 16175790873SEugeniy Paltsev if (is_isa_arcv2()) { 16275790873SEugeniy Paltsev union bcr_generic sbcr; 16375790873SEugeniy Paltsev 16475790873SEugeniy Paltsev sbcr.word = read_aux_reg(ARC_BCR_SLC); 16575790873SEugeniy Paltsev return !!sbcr.fields.ver; 16675790873SEugeniy Paltsev } 16775790873SEugeniy Paltsev 16875790873SEugeniy Paltsev return false; 16941cada4dSEugeniy Paltsev } 17041cada4dSEugeniy Paltsev 17148b04832SEugeniy Paltsev static inline bool ioc_exists(void) 17248b04832SEugeniy Paltsev { 17348b04832SEugeniy Paltsev if (is_isa_arcv2()) { 17448b04832SEugeniy Paltsev union bcr_clust_cfg cbcr; 17548b04832SEugeniy Paltsev 17648b04832SEugeniy Paltsev cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); 17748b04832SEugeniy Paltsev return cbcr.fields.c; 17848b04832SEugeniy Paltsev } 17948b04832SEugeniy Paltsev 18048b04832SEugeniy Paltsev return false; 18148b04832SEugeniy Paltsev } 18248b04832SEugeniy Paltsev 18348b04832SEugeniy Paltsev static inline bool ioc_enabled(void) 18448b04832SEugeniy Paltsev { 18548b04832SEugeniy Paltsev /* 18648b04832SEugeniy Paltsev * We check only CONFIG option instead of IOC HW state check as IOC 18748b04832SEugeniy Paltsev * must be disabled by default. 18848b04832SEugeniy Paltsev */ 18948b04832SEugeniy Paltsev if (is_ioc_enabled()) 19048b04832SEugeniy Paltsev return ioc_exists(); 19148b04832SEugeniy Paltsev 19248b04832SEugeniy Paltsev return false; 19348b04832SEugeniy Paltsev } 19448b04832SEugeniy Paltsev 19541cada4dSEugeniy Paltsev static void __slc_entire_op(const int op) 19641cada4dSEugeniy Paltsev { 19741cada4dSEugeniy Paltsev unsigned int ctrl; 19841cada4dSEugeniy Paltsev 19975790873SEugeniy Paltsev if (!slc_exists()) 200ea9f6f1eSEugeniy Paltsev return; 201ea9f6f1eSEugeniy Paltsev 20241cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 20341cada4dSEugeniy Paltsev 20441cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 20541cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 20641cada4dSEugeniy Paltsev else 20741cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 20841cada4dSEugeniy Paltsev 20941cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 21041cada4dSEugeniy Paltsev 21141cada4dSEugeniy Paltsev if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 21241cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); 21341cada4dSEugeniy Paltsev else 21441cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); 21541cada4dSEugeniy Paltsev 21641cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 21741cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 21841cada4dSEugeniy Paltsev 21941cada4dSEugeniy Paltsev /* Important to wait for flush to complete */ 22041cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 22141cada4dSEugeniy Paltsev } 22241cada4dSEugeniy Paltsev 22341cada4dSEugeniy Paltsev static void slc_upper_region_init(void) 22441cada4dSEugeniy Paltsev { 22541cada4dSEugeniy Paltsev /* 226246ba284SEugeniy Paltsev * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist 227246ba284SEugeniy Paltsev * only if PAE exists in current HW. So we had to check pae_exist 228246ba284SEugeniy Paltsev * before using them. 229246ba284SEugeniy Paltsev */ 230246ba284SEugeniy Paltsev if (!pae_exists()) 231246ba284SEugeniy Paltsev return; 232246ba284SEugeniy Paltsev 233246ba284SEugeniy Paltsev /* 23441cada4dSEugeniy Paltsev * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 23541cada4dSEugeniy Paltsev * as we don't use PAE40. 23641cada4dSEugeniy Paltsev */ 23741cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); 23841cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); 23941cada4dSEugeniy Paltsev } 24041cada4dSEugeniy Paltsev 24141cada4dSEugeniy Paltsev static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) 24241cada4dSEugeniy Paltsev { 24305c6a26aSEugeniy Paltsev #ifdef CONFIG_ISA_ARCV2 24405c6a26aSEugeniy Paltsev 24541cada4dSEugeniy Paltsev unsigned int ctrl; 24641cada4dSEugeniy Paltsev unsigned long end; 24741cada4dSEugeniy Paltsev 24875790873SEugeniy Paltsev if (!slc_exists()) 249ea9f6f1eSEugeniy Paltsev return; 250ea9f6f1eSEugeniy Paltsev 25141cada4dSEugeniy Paltsev /* 25241cada4dSEugeniy Paltsev * The Region Flush operation is specified by CTRL.RGN_OP[11..9] 25341cada4dSEugeniy Paltsev * - b'000 (default) is Flush, 25441cada4dSEugeniy Paltsev * - b'001 is Invalidate if CTRL.IM == 0 25541cada4dSEugeniy Paltsev * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 25641cada4dSEugeniy Paltsev */ 25741cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 25841cada4dSEugeniy Paltsev 25941cada4dSEugeniy Paltsev /* Don't rely on default value of IM bit */ 26041cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 26141cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 26241cada4dSEugeniy Paltsev else 26341cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 26441cada4dSEugeniy Paltsev 26541cada4dSEugeniy Paltsev if (op & OP_INV) 26641cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ 26741cada4dSEugeniy Paltsev else 26841cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_RGN_OP_INV; 26941cada4dSEugeniy Paltsev 27041cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 27141cada4dSEugeniy Paltsev 27241cada4dSEugeniy Paltsev /* 27341cada4dSEugeniy Paltsev * Lower bits are ignored, no need to clip 27441cada4dSEugeniy Paltsev * END needs to be setup before START (latter triggers the operation) 27541cada4dSEugeniy Paltsev * END can't be same as START, so add (l2_line_sz - 1) to sz 27641cada4dSEugeniy Paltsev */ 277bf8974edSEugeniy Paltsev end = paddr + sz + gd->arch.slc_line_sz - 1; 27841cada4dSEugeniy Paltsev 27941cada4dSEugeniy Paltsev /* 28041cada4dSEugeniy Paltsev * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) 28141cada4dSEugeniy Paltsev * are always == 0 as we don't use PAE40, so we only setup lower ones 28241cada4dSEugeniy Paltsev * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START) 28341cada4dSEugeniy Paltsev */ 28441cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END, end); 28541cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); 28641cada4dSEugeniy Paltsev 28741cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 28841cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 28941cada4dSEugeniy Paltsev 29041cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 29105c6a26aSEugeniy Paltsev 29205c6a26aSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 29341cada4dSEugeniy Paltsev } 294a6f557c4SEugeniy Paltsev 295a6f557c4SEugeniy Paltsev static void arc_ioc_setup(void) 296a6f557c4SEugeniy Paltsev { 297a6f557c4SEugeniy Paltsev /* IOC Aperture start is equal to DDR start */ 298a6f557c4SEugeniy Paltsev unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; 299a6f557c4SEugeniy Paltsev /* IOC Aperture size is equal to DDR size */ 300a6f557c4SEugeniy Paltsev long ap_size = CONFIG_SYS_SDRAM_SIZE; 301a6f557c4SEugeniy Paltsev 302a6f557c4SEugeniy Paltsev flush_n_invalidate_dcache_all(); 303a6f557c4SEugeniy Paltsev 304a6f557c4SEugeniy Paltsev if (!is_power_of_2(ap_size) || ap_size < 4096) 305a6f557c4SEugeniy Paltsev panic("IOC Aperture size must be power of 2 and bigger 4Kib"); 306a6f557c4SEugeniy Paltsev 307a6f557c4SEugeniy Paltsev /* 308a6f557c4SEugeniy Paltsev * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, 309a6f557c4SEugeniy Paltsev * so setting 0x11 implies 512M, 0x12 implies 1G... 310a6f557c4SEugeniy Paltsev */ 311a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 312a6f557c4SEugeniy Paltsev order_base_2(ap_size / 1024) - 2); 313a6f557c4SEugeniy Paltsev 314a6f557c4SEugeniy Paltsev /* IOC Aperture start must be aligned to the size of the aperture */ 315a6f557c4SEugeniy Paltsev if (ap_base % ap_size != 0) 316a6f557c4SEugeniy Paltsev panic("IOC Aperture start must be aligned to the size of the aperture"); 317a6f557c4SEugeniy Paltsev 318a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); 319a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); 320a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); 321a6f557c4SEugeniy Paltsev } 322ef639e6fSAlexey Brodkin 323379b3280SAlexey Brodkin static void read_decode_cache_bcr_arcv2(void) 324ef639e6fSAlexey Brodkin { 32505c6a26aSEugeniy Paltsev #ifdef CONFIG_ISA_ARCV2 32605c6a26aSEugeniy Paltsev 32788ae27edSEugeniy Paltsev union bcr_slc_cfg slc_cfg; 328379b3280SAlexey Brodkin 32975790873SEugeniy Paltsev if (slc_exists()) { 330379b3280SAlexey Brodkin slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); 331bf8974edSEugeniy Paltsev gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; 332379b3280SAlexey Brodkin } 333db6ce231SAlexey Brodkin 33405c6a26aSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 335379b3280SAlexey Brodkin } 336379b3280SAlexey Brodkin 337379b3280SAlexey Brodkin void read_decode_cache_bcr(void) 338379b3280SAlexey Brodkin { 339379b3280SAlexey Brodkin int dc_line_sz = 0, ic_line_sz = 0; 34088ae27edSEugeniy Paltsev union bcr_di_cache ibcr, dbcr; 341379b3280SAlexey Brodkin 342379b3280SAlexey Brodkin ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 343379b3280SAlexey Brodkin if (ibcr.fields.ver) { 344bf8974edSEugeniy Paltsev gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; 345379b3280SAlexey Brodkin if (!ic_line_sz) 346379b3280SAlexey Brodkin panic("Instruction exists but line length is 0\n"); 347ef639e6fSAlexey Brodkin } 348ef639e6fSAlexey Brodkin 349379b3280SAlexey Brodkin dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 350379b3280SAlexey Brodkin if (dbcr.fields.ver) { 351bf8974edSEugeniy Paltsev gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; 352379b3280SAlexey Brodkin if (!dc_line_sz) 353379b3280SAlexey Brodkin panic("Data cache exists but line length is 0\n"); 354379b3280SAlexey Brodkin } 355379b3280SAlexey Brodkin 356379b3280SAlexey Brodkin if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz)) 357379b3280SAlexey Brodkin panic("Instruction and data cache line lengths differ\n"); 358ef639e6fSAlexey Brodkin } 359ef639e6fSAlexey Brodkin 360ef639e6fSAlexey Brodkin void cache_init(void) 361ef639e6fSAlexey Brodkin { 362379b3280SAlexey Brodkin read_decode_cache_bcr(); 363379b3280SAlexey Brodkin 36405c6a26aSEugeniy Paltsev if (is_isa_arcv2()) 365379b3280SAlexey Brodkin read_decode_cache_bcr_arcv2(); 366db6ce231SAlexey Brodkin 36748b04832SEugeniy Paltsev if (is_isa_arcv2() && ioc_enabled()) 368a6f557c4SEugeniy Paltsev arc_ioc_setup(); 36941cada4dSEugeniy Paltsev 370246ba284SEugeniy Paltsev if (is_isa_arcv2() && slc_exists()) 37141cada4dSEugeniy Paltsev slc_upper_region_init(); 372ef639e6fSAlexey Brodkin } 373ef639e6fSAlexey Brodkin 374660d5f0dSAlexey Brodkin int icache_status(void) 375660d5f0dSAlexey Brodkin { 376*c75eeb0bSEugeniy Paltsev return icache_enabled(); 377660d5f0dSAlexey Brodkin } 378660d5f0dSAlexey Brodkin 379660d5f0dSAlexey Brodkin void icache_enable(void) 380660d5f0dSAlexey Brodkin { 38175790873SEugeniy Paltsev if (icache_exists()) 382660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & 383660d5f0dSAlexey Brodkin ~IC_CTRL_CACHE_DISABLE); 384660d5f0dSAlexey Brodkin } 385660d5f0dSAlexey Brodkin 386660d5f0dSAlexey Brodkin void icache_disable(void) 387660d5f0dSAlexey Brodkin { 38875790873SEugeniy Paltsev if (icache_exists()) 389660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | 390660d5f0dSAlexey Brodkin IC_CTRL_CACHE_DISABLE); 391660d5f0dSAlexey Brodkin } 392660d5f0dSAlexey Brodkin 39316aeee81SEugeniy Paltsev /* IC supports only invalidation */ 39416aeee81SEugeniy Paltsev static inline void __ic_entire_invalidate(void) 395660d5f0dSAlexey Brodkin { 396*c75eeb0bSEugeniy Paltsev if (!icache_enabled()) 39716aeee81SEugeniy Paltsev return; 39816aeee81SEugeniy Paltsev 399660d5f0dSAlexey Brodkin /* Any write to IC_IVIC register triggers invalidation of entire I$ */ 400660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_IVIC, 1); 401f2a22678SAlexey Brodkin /* 402f2a22678SAlexey Brodkin * As per ARC HS databook (see chapter 5.3.3.2) 403f2a22678SAlexey Brodkin * it is required to add 3 NOPs after each write to IC_IVIC. 404f2a22678SAlexey Brodkin */ 405f2a22678SAlexey Brodkin __builtin_arc_nop(); 406f2a22678SAlexey Brodkin __builtin_arc_nop(); 407f2a22678SAlexey Brodkin __builtin_arc_nop(); 408ef639e6fSAlexey Brodkin read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ 409660d5f0dSAlexey Brodkin } 41041cada4dSEugeniy Paltsev 41116aeee81SEugeniy Paltsev void invalidate_icache_all(void) 41216aeee81SEugeniy Paltsev { 41316aeee81SEugeniy Paltsev __ic_entire_invalidate(); 41416aeee81SEugeniy Paltsev 415ea9f6f1eSEugeniy Paltsev if (is_isa_arcv2()) 41641cada4dSEugeniy Paltsev __slc_entire_op(OP_INV); 41741cada4dSEugeniy Paltsev } 418660d5f0dSAlexey Brodkin 419660d5f0dSAlexey Brodkin int dcache_status(void) 420660d5f0dSAlexey Brodkin { 421*c75eeb0bSEugeniy Paltsev return dcache_enabled(); 422660d5f0dSAlexey Brodkin } 423660d5f0dSAlexey Brodkin 424660d5f0dSAlexey Brodkin void dcache_enable(void) 425660d5f0dSAlexey Brodkin { 42675790873SEugeniy Paltsev if (!dcache_exists()) 427660d5f0dSAlexey Brodkin return; 428660d5f0dSAlexey Brodkin 429660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & 430660d5f0dSAlexey Brodkin ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); 431660d5f0dSAlexey Brodkin } 432660d5f0dSAlexey Brodkin 433660d5f0dSAlexey Brodkin void dcache_disable(void) 434660d5f0dSAlexey Brodkin { 43575790873SEugeniy Paltsev if (!dcache_exists()) 436660d5f0dSAlexey Brodkin return; 437660d5f0dSAlexey Brodkin 438660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | 439660d5f0dSAlexey Brodkin DC_CTRL_CACHE_DISABLE); 440660d5f0dSAlexey Brodkin } 441660d5f0dSAlexey Brodkin 442c4ef14d2SEugeniy Paltsev /* Common Helper for Line Operations on D-cache */ 443c4ef14d2SEugeniy Paltsev static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, 444ef639e6fSAlexey Brodkin const int cacheop) 445660d5f0dSAlexey Brodkin { 446ef639e6fSAlexey Brodkin unsigned int aux_cmd; 447ef639e6fSAlexey Brodkin int num_lines; 448660d5f0dSAlexey Brodkin 449ef639e6fSAlexey Brodkin /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 450ef639e6fSAlexey Brodkin aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; 451660d5f0dSAlexey Brodkin 452ef639e6fSAlexey Brodkin sz += paddr & ~CACHE_LINE_MASK; 453ef639e6fSAlexey Brodkin paddr &= CACHE_LINE_MASK; 454ef639e6fSAlexey Brodkin 455bf8974edSEugeniy Paltsev num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz); 456ef639e6fSAlexey Brodkin 457ef639e6fSAlexey Brodkin while (num_lines-- > 0) { 458ef639e6fSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 459c4ef14d2SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_PTAG, paddr); 460ef639e6fSAlexey Brodkin #endif 461ef639e6fSAlexey Brodkin write_aux_reg(aux_cmd, paddr); 462bf8974edSEugeniy Paltsev paddr += gd->arch.l1_line_sz; 463ef639e6fSAlexey Brodkin } 464ef639e6fSAlexey Brodkin } 465ef639e6fSAlexey Brodkin 4665d7a24d6SEugeniy Paltsev static void __before_dc_op(const int op) 467ef639e6fSAlexey Brodkin { 4685d7a24d6SEugeniy Paltsev unsigned int ctrl; 469ef639e6fSAlexey Brodkin 4705d7a24d6SEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_DC_CTRL); 4715d7a24d6SEugeniy Paltsev 4725d7a24d6SEugeniy Paltsev /* IM bit implies flush-n-inv, instead of vanilla inv */ 4735d7a24d6SEugeniy Paltsev if (op == OP_INV) 4745d7a24d6SEugeniy Paltsev ctrl &= ~DC_CTRL_INV_MODE_FLUSH; 4755d7a24d6SEugeniy Paltsev else 4765d7a24d6SEugeniy Paltsev ctrl |= DC_CTRL_INV_MODE_FLUSH; 4775d7a24d6SEugeniy Paltsev 4785d7a24d6SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_CTRL, ctrl); 479ef639e6fSAlexey Brodkin } 480ef639e6fSAlexey Brodkin 4815d7a24d6SEugeniy Paltsev static void __after_dc_op(const int op) 482ef639e6fSAlexey Brodkin { 483ef639e6fSAlexey Brodkin if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ 48419b10a42SEugeniy Paltsev while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); 485ef639e6fSAlexey Brodkin } 486ef639e6fSAlexey Brodkin 487ef639e6fSAlexey Brodkin static inline void __dc_entire_op(const int cacheop) 488ef639e6fSAlexey Brodkin { 489ef639e6fSAlexey Brodkin int aux; 4905d7a24d6SEugeniy Paltsev 491*c75eeb0bSEugeniy Paltsev if (!dcache_enabled()) 492c877a891SEugeniy Paltsev return; 493c877a891SEugeniy Paltsev 4945d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 495ef639e6fSAlexey Brodkin 496ef639e6fSAlexey Brodkin if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 497ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_IVDC; 498ef639e6fSAlexey Brodkin else 499ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_FLSH; 500ef639e6fSAlexey Brodkin 501ef639e6fSAlexey Brodkin write_aux_reg(aux, 0x1); 502ef639e6fSAlexey Brodkin 5035d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 504ef639e6fSAlexey Brodkin } 505ef639e6fSAlexey Brodkin 506ef639e6fSAlexey Brodkin static inline void __dc_line_op(unsigned long paddr, unsigned long sz, 507ef639e6fSAlexey Brodkin const int cacheop) 508ef639e6fSAlexey Brodkin { 509*c75eeb0bSEugeniy Paltsev if (!dcache_enabled()) 510c877a891SEugeniy Paltsev return; 511c877a891SEugeniy Paltsev 5125d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 513c4ef14d2SEugeniy Paltsev __dcache_line_loop(paddr, sz, cacheop); 5145d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 515ef639e6fSAlexey Brodkin } 516ef639e6fSAlexey Brodkin 517660d5f0dSAlexey Brodkin void invalidate_dcache_range(unsigned long start, unsigned long end) 518660d5f0dSAlexey Brodkin { 51941cada4dSEugeniy Paltsev if (start >= end) 52041cada4dSEugeniy Paltsev return; 52141cada4dSEugeniy Paltsev 52205c6a26aSEugeniy Paltsev /* 52305c6a26aSEugeniy Paltsev * ARCv1 -> call __dc_line_op 52405c6a26aSEugeniy Paltsev * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 52505c6a26aSEugeniy Paltsev * ARCv2 && IOC enabled -> nothing 52605c6a26aSEugeniy Paltsev */ 52748b04832SEugeniy Paltsev if (!is_isa_arcv2() || !ioc_enabled()) 528db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_INV); 529db6ce231SAlexey Brodkin 53048b04832SEugeniy Paltsev if (is_isa_arcv2() && !ioc_enabled()) 53141cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_INV); 532660d5f0dSAlexey Brodkin } 533660d5f0dSAlexey Brodkin 534ef639e6fSAlexey Brodkin void flush_dcache_range(unsigned long start, unsigned long end) 535660d5f0dSAlexey Brodkin { 53641cada4dSEugeniy Paltsev if (start >= end) 53741cada4dSEugeniy Paltsev return; 53841cada4dSEugeniy Paltsev 53905c6a26aSEugeniy Paltsev /* 54005c6a26aSEugeniy Paltsev * ARCv1 -> call __dc_line_op 54105c6a26aSEugeniy Paltsev * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 54205c6a26aSEugeniy Paltsev * ARCv2 && IOC enabled -> nothing 54305c6a26aSEugeniy Paltsev */ 54448b04832SEugeniy Paltsev if (!is_isa_arcv2() || !ioc_enabled()) 545db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_FLUSH); 546db6ce231SAlexey Brodkin 54748b04832SEugeniy Paltsev if (is_isa_arcv2() && !ioc_enabled()) 54841cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_FLUSH); 549660d5f0dSAlexey Brodkin } 550660d5f0dSAlexey Brodkin 551660d5f0dSAlexey Brodkin void flush_cache(unsigned long start, unsigned long size) 552660d5f0dSAlexey Brodkin { 553660d5f0dSAlexey Brodkin flush_dcache_range(start, start + size); 554660d5f0dSAlexey Brodkin } 5556eb15e50SAlexey Brodkin 556c27814beSEugeniy Paltsev /* 557c27814beSEugeniy Paltsev * As invalidate_dcache_all() is not used in generic U-Boot code and as we 558c27814beSEugeniy Paltsev * don't need it in arch/arc code alone (invalidate without flush) we implement 559c27814beSEugeniy Paltsev * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because 560c27814beSEugeniy Paltsev * it's much safer. See [ NOTE 1 ] for more details. 561c27814beSEugeniy Paltsev */ 562c27814beSEugeniy Paltsev void flush_n_invalidate_dcache_all(void) 563ef639e6fSAlexey Brodkin { 564c27814beSEugeniy Paltsev __dc_entire_op(OP_FLUSH_N_INV); 565db6ce231SAlexey Brodkin 566ea9f6f1eSEugeniy Paltsev if (is_isa_arcv2()) 567c27814beSEugeniy Paltsev __slc_entire_op(OP_FLUSH_N_INV); 5686eb15e50SAlexey Brodkin } 5696eb15e50SAlexey Brodkin 570ef639e6fSAlexey Brodkin void flush_dcache_all(void) 5716eb15e50SAlexey Brodkin { 572db6ce231SAlexey Brodkin __dc_entire_op(OP_FLUSH); 573db6ce231SAlexey Brodkin 574ea9f6f1eSEugeniy Paltsev if (is_isa_arcv2()) 575ef639e6fSAlexey Brodkin __slc_entire_op(OP_FLUSH); 5766eb15e50SAlexey Brodkin } 577