1660d5f0dSAlexey Brodkin /* 2660d5f0dSAlexey Brodkin * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3660d5f0dSAlexey Brodkin * 4660d5f0dSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5660d5f0dSAlexey Brodkin */ 6660d5f0dSAlexey Brodkin 7660d5f0dSAlexey Brodkin #include <config.h> 8379b3280SAlexey Brodkin #include <common.h> 9ef639e6fSAlexey Brodkin #include <linux/compiler.h> 10ef639e6fSAlexey Brodkin #include <linux/kernel.h> 1197a63144SAlexey Brodkin #include <linux/log2.h> 12660d5f0dSAlexey Brodkin #include <asm/arcregs.h> 1388ae27edSEugeniy Paltsev #include <asm/arc-bcr.h> 14205e7a7bSAlexey Brodkin #include <asm/cache.h> 15660d5f0dSAlexey Brodkin 16c27814beSEugeniy Paltsev /* 17c27814beSEugeniy Paltsev * [ NOTE 1 ]: 18c27814beSEugeniy Paltsev * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable 19c27814beSEugeniy Paltsev * operation may result in unexpected behavior and data loss even if we flush 20c27814beSEugeniy Paltsev * data cache right before invalidation. That may happens if we store any context 21c27814beSEugeniy Paltsev * on stack (like we store BLINK register on stack before function call). 22c27814beSEugeniy Paltsev * BLINK register is the register where return address is automatically saved 23c27814beSEugeniy Paltsev * when we do function call with instructions like 'bl'. 24c27814beSEugeniy Paltsev * 25c27814beSEugeniy Paltsev * There is the real example: 26c27814beSEugeniy Paltsev * We may hang in the next code as we store any BLINK register on stack in 27c27814beSEugeniy Paltsev * invalidate_dcache_all() function. 28c27814beSEugeniy Paltsev * 29c27814beSEugeniy Paltsev * void flush_dcache_all() { 30c27814beSEugeniy Paltsev * __dc_entire_op(OP_FLUSH); 31c27814beSEugeniy Paltsev * // Other code // 32c27814beSEugeniy Paltsev * } 33c27814beSEugeniy Paltsev * 34c27814beSEugeniy Paltsev * void invalidate_dcache_all() { 35c27814beSEugeniy Paltsev * __dc_entire_op(OP_INV); 36c27814beSEugeniy Paltsev * // Other code // 37c27814beSEugeniy Paltsev * } 38c27814beSEugeniy Paltsev * 39c27814beSEugeniy Paltsev * void foo(void) { 40c27814beSEugeniy Paltsev * flush_dcache_all(); 41c27814beSEugeniy Paltsev * invalidate_dcache_all(); 42c27814beSEugeniy Paltsev * } 43c27814beSEugeniy Paltsev * 44c27814beSEugeniy Paltsev * Now let's see what really happens during that code execution: 45c27814beSEugeniy Paltsev * 46c27814beSEugeniy Paltsev * foo() 47c27814beSEugeniy Paltsev * |->> call flush_dcache_all 48c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 49c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 1] 50c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 51c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 52c27814beSEugeniy Paltsev * [flush L1 D$] 53c27814beSEugeniy Paltsev * return [jump to BLINK] 54c27814beSEugeniy Paltsev * <<------ 55c27814beSEugeniy Paltsev * [other flush_dcache_all code] 56c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 57c27814beSEugeniy Paltsev * return [jump to BLINK] 58c27814beSEugeniy Paltsev * <<------ 59c27814beSEugeniy Paltsev * |->> call invalidate_dcache_all 60c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 61c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 2] 62c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 63c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 64c27814beSEugeniy Paltsev * [invalidate L1 D$] ![point 3] 65c27814beSEugeniy Paltsev * // Oops!!! 66c27814beSEugeniy Paltsev * // We lose return address from invalidate_dcache_all function: 67c27814beSEugeniy Paltsev * // we save it to stack and invalidate L1 D$ after that! 68c27814beSEugeniy Paltsev * return [jump to BLINK] 69c27814beSEugeniy Paltsev * <<------ 70c27814beSEugeniy Paltsev * [other invalidate_dcache_all code] 71c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 72c27814beSEugeniy Paltsev * // we don't have this data in L1 dcache as we invalidated it in [point 3] 73c27814beSEugeniy Paltsev * // so we get it from next memory level (for example DDR memory) 74c27814beSEugeniy Paltsev * // but in the memory we have value which we save in [point 1], which 75c27814beSEugeniy Paltsev * // is return address from flush_dcache_all function (instead of 76c27814beSEugeniy Paltsev * // address from current invalidate_dcache_all function which we 77c27814beSEugeniy Paltsev * // saved in [point 2] !) 78c27814beSEugeniy Paltsev * return [jump to BLINK] 79c27814beSEugeniy Paltsev * <<------ 80c27814beSEugeniy Paltsev * // As BLINK points to invalidate_dcache_all, we call it again and 81c27814beSEugeniy Paltsev * // loop forever. 82c27814beSEugeniy Paltsev * 83c27814beSEugeniy Paltsev * Fortunately we may fix that by using flush & invalidation of D$ with a single 84c27814beSEugeniy Paltsev * one instruction (instead of flush and invalidation instructions pair) and 85c27814beSEugeniy Paltsev * enabling force function inline with '__attribute__((always_inline))' gcc 86c27814beSEugeniy Paltsev * attribute to avoid any function call (and BLINK store) between cache flush 87c27814beSEugeniy Paltsev * and disable. 88c27814beSEugeniy Paltsev */ 89c27814beSEugeniy Paltsev 90*bf8974edSEugeniy Paltsev DECLARE_GLOBAL_DATA_PTR; 91*bf8974edSEugeniy Paltsev 92660d5f0dSAlexey Brodkin /* Bit values in IC_CTRL */ 9319b10a42SEugeniy Paltsev #define IC_CTRL_CACHE_DISABLE BIT(0) 94660d5f0dSAlexey Brodkin 95660d5f0dSAlexey Brodkin /* Bit values in DC_CTRL */ 9619b10a42SEugeniy Paltsev #define DC_CTRL_CACHE_DISABLE BIT(0) 9719b10a42SEugeniy Paltsev #define DC_CTRL_INV_MODE_FLUSH BIT(6) 9819b10a42SEugeniy Paltsev #define DC_CTRL_FLUSH_STATUS BIT(8) 99660d5f0dSAlexey Brodkin 1005d7a24d6SEugeniy Paltsev #define OP_INV BIT(0) 1015d7a24d6SEugeniy Paltsev #define OP_FLUSH BIT(1) 1025d7a24d6SEugeniy Paltsev #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV) 103ef639e6fSAlexey Brodkin 10441cada4dSEugeniy Paltsev /* Bit val in SLC_CONTROL */ 10541cada4dSEugeniy Paltsev #define SLC_CTRL_DIS 0x001 10641cada4dSEugeniy Paltsev #define SLC_CTRL_IM 0x040 10741cada4dSEugeniy Paltsev #define SLC_CTRL_BUSY 0x100 10841cada4dSEugeniy Paltsev #define SLC_CTRL_RGN_OP_INV 0x200 10941cada4dSEugeniy Paltsev 110ef639e6fSAlexey Brodkin /* 111ef639e6fSAlexey Brodkin * By default that variable will fall into .bss section. 112ef639e6fSAlexey Brodkin * But .bss section is not relocated and so it will be initilized before 113ef639e6fSAlexey Brodkin * relocation but will be used after being zeroed. 114ef639e6fSAlexey Brodkin */ 115*bf8974edSEugeniy Paltsev #define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1)) 116379b3280SAlexey Brodkin 1173cf23939SEugeniy Paltsev bool ioc_exists __section(".data") = false; 118ef639e6fSAlexey Brodkin 119b0146f9eSEugeniy Paltsev /* To force enable IOC set ioc_enable to 'true' */ 120b0146f9eSEugeniy Paltsev bool ioc_enable __section(".data") = false; 121b0146f9eSEugeniy Paltsev 12275790873SEugeniy Paltsev static inline bool pae_exists(void) 123ef639e6fSAlexey Brodkin { 12441cada4dSEugeniy Paltsev /* TODO: should we compare mmu version from BCR and from CONFIG? */ 12541cada4dSEugeniy Paltsev #if (CONFIG_ARC_MMU_VER >= 4) 12688ae27edSEugeniy Paltsev union bcr_mmu_4 mmu4; 127ef639e6fSAlexey Brodkin 12888ae27edSEugeniy Paltsev mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR); 129ef639e6fSAlexey Brodkin 13075790873SEugeniy Paltsev if (mmu4.fields.pae) 13175790873SEugeniy Paltsev return true; 13241cada4dSEugeniy Paltsev #endif /* (CONFIG_ARC_MMU_VER >= 4) */ 13375790873SEugeniy Paltsev 13475790873SEugeniy Paltsev return false; 13575790873SEugeniy Paltsev } 13675790873SEugeniy Paltsev 13775790873SEugeniy Paltsev static inline bool icache_exists(void) 13875790873SEugeniy Paltsev { 13975790873SEugeniy Paltsev union bcr_di_cache ibcr; 14075790873SEugeniy Paltsev 14175790873SEugeniy Paltsev ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 14275790873SEugeniy Paltsev return !!ibcr.fields.ver; 14375790873SEugeniy Paltsev } 14475790873SEugeniy Paltsev 14575790873SEugeniy Paltsev static inline bool dcache_exists(void) 14675790873SEugeniy Paltsev { 14775790873SEugeniy Paltsev union bcr_di_cache dbcr; 14875790873SEugeniy Paltsev 14975790873SEugeniy Paltsev dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 15075790873SEugeniy Paltsev return !!dbcr.fields.ver; 15175790873SEugeniy Paltsev } 15275790873SEugeniy Paltsev 15375790873SEugeniy Paltsev static inline bool slc_exists(void) 15475790873SEugeniy Paltsev { 15575790873SEugeniy Paltsev if (is_isa_arcv2()) { 15675790873SEugeniy Paltsev union bcr_generic sbcr; 15775790873SEugeniy Paltsev 15875790873SEugeniy Paltsev sbcr.word = read_aux_reg(ARC_BCR_SLC); 15975790873SEugeniy Paltsev return !!sbcr.fields.ver; 16075790873SEugeniy Paltsev } 16175790873SEugeniy Paltsev 16275790873SEugeniy Paltsev return false; 16341cada4dSEugeniy Paltsev } 16441cada4dSEugeniy Paltsev 16541cada4dSEugeniy Paltsev static void __slc_entire_op(const int op) 16641cada4dSEugeniy Paltsev { 16741cada4dSEugeniy Paltsev unsigned int ctrl; 16841cada4dSEugeniy Paltsev 16975790873SEugeniy Paltsev if (!slc_exists()) 170ea9f6f1eSEugeniy Paltsev return; 171ea9f6f1eSEugeniy Paltsev 17241cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 17341cada4dSEugeniy Paltsev 17441cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 17541cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 17641cada4dSEugeniy Paltsev else 17741cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 17841cada4dSEugeniy Paltsev 17941cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 18041cada4dSEugeniy Paltsev 18141cada4dSEugeniy Paltsev if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 18241cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); 18341cada4dSEugeniy Paltsev else 18441cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); 18541cada4dSEugeniy Paltsev 18641cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 18741cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 18841cada4dSEugeniy Paltsev 18941cada4dSEugeniy Paltsev /* Important to wait for flush to complete */ 19041cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 19141cada4dSEugeniy Paltsev } 19241cada4dSEugeniy Paltsev 19341cada4dSEugeniy Paltsev static void slc_upper_region_init(void) 19441cada4dSEugeniy Paltsev { 19541cada4dSEugeniy Paltsev /* 19641cada4dSEugeniy Paltsev * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 19741cada4dSEugeniy Paltsev * as we don't use PAE40. 19841cada4dSEugeniy Paltsev */ 19941cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); 20041cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); 20141cada4dSEugeniy Paltsev } 20241cada4dSEugeniy Paltsev 20341cada4dSEugeniy Paltsev static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) 20441cada4dSEugeniy Paltsev { 20505c6a26aSEugeniy Paltsev #ifdef CONFIG_ISA_ARCV2 20605c6a26aSEugeniy Paltsev 20741cada4dSEugeniy Paltsev unsigned int ctrl; 20841cada4dSEugeniy Paltsev unsigned long end; 20941cada4dSEugeniy Paltsev 21075790873SEugeniy Paltsev if (!slc_exists()) 211ea9f6f1eSEugeniy Paltsev return; 212ea9f6f1eSEugeniy Paltsev 21341cada4dSEugeniy Paltsev /* 21441cada4dSEugeniy Paltsev * The Region Flush operation is specified by CTRL.RGN_OP[11..9] 21541cada4dSEugeniy Paltsev * - b'000 (default) is Flush, 21641cada4dSEugeniy Paltsev * - b'001 is Invalidate if CTRL.IM == 0 21741cada4dSEugeniy Paltsev * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 21841cada4dSEugeniy Paltsev */ 21941cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 22041cada4dSEugeniy Paltsev 22141cada4dSEugeniy Paltsev /* Don't rely on default value of IM bit */ 22241cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 22341cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 22441cada4dSEugeniy Paltsev else 22541cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 22641cada4dSEugeniy Paltsev 22741cada4dSEugeniy Paltsev if (op & OP_INV) 22841cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ 22941cada4dSEugeniy Paltsev else 23041cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_RGN_OP_INV; 23141cada4dSEugeniy Paltsev 23241cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 23341cada4dSEugeniy Paltsev 23441cada4dSEugeniy Paltsev /* 23541cada4dSEugeniy Paltsev * Lower bits are ignored, no need to clip 23641cada4dSEugeniy Paltsev * END needs to be setup before START (latter triggers the operation) 23741cada4dSEugeniy Paltsev * END can't be same as START, so add (l2_line_sz - 1) to sz 23841cada4dSEugeniy Paltsev */ 239*bf8974edSEugeniy Paltsev end = paddr + sz + gd->arch.slc_line_sz - 1; 24041cada4dSEugeniy Paltsev 24141cada4dSEugeniy Paltsev /* 24241cada4dSEugeniy Paltsev * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) 24341cada4dSEugeniy Paltsev * are always == 0 as we don't use PAE40, so we only setup lower ones 24441cada4dSEugeniy Paltsev * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START) 24541cada4dSEugeniy Paltsev */ 24641cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END, end); 24741cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); 24841cada4dSEugeniy Paltsev 24941cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 25041cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 25141cada4dSEugeniy Paltsev 25241cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 25305c6a26aSEugeniy Paltsev 25405c6a26aSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 25541cada4dSEugeniy Paltsev } 256a6f557c4SEugeniy Paltsev 257a6f557c4SEugeniy Paltsev static void arc_ioc_setup(void) 258a6f557c4SEugeniy Paltsev { 259a6f557c4SEugeniy Paltsev /* IOC Aperture start is equal to DDR start */ 260a6f557c4SEugeniy Paltsev unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; 261a6f557c4SEugeniy Paltsev /* IOC Aperture size is equal to DDR size */ 262a6f557c4SEugeniy Paltsev long ap_size = CONFIG_SYS_SDRAM_SIZE; 263a6f557c4SEugeniy Paltsev 264a6f557c4SEugeniy Paltsev flush_n_invalidate_dcache_all(); 265a6f557c4SEugeniy Paltsev 266a6f557c4SEugeniy Paltsev if (!is_power_of_2(ap_size) || ap_size < 4096) 267a6f557c4SEugeniy Paltsev panic("IOC Aperture size must be power of 2 and bigger 4Kib"); 268a6f557c4SEugeniy Paltsev 269a6f557c4SEugeniy Paltsev /* 270a6f557c4SEugeniy Paltsev * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, 271a6f557c4SEugeniy Paltsev * so setting 0x11 implies 512M, 0x12 implies 1G... 272a6f557c4SEugeniy Paltsev */ 273a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 274a6f557c4SEugeniy Paltsev order_base_2(ap_size / 1024) - 2); 275a6f557c4SEugeniy Paltsev 276a6f557c4SEugeniy Paltsev /* IOC Aperture start must be aligned to the size of the aperture */ 277a6f557c4SEugeniy Paltsev if (ap_base % ap_size != 0) 278a6f557c4SEugeniy Paltsev panic("IOC Aperture start must be aligned to the size of the aperture"); 279a6f557c4SEugeniy Paltsev 280a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); 281a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); 282a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); 283a6f557c4SEugeniy Paltsev } 284ef639e6fSAlexey Brodkin 285379b3280SAlexey Brodkin static void read_decode_cache_bcr_arcv2(void) 286ef639e6fSAlexey Brodkin { 28705c6a26aSEugeniy Paltsev #ifdef CONFIG_ISA_ARCV2 28805c6a26aSEugeniy Paltsev 28988ae27edSEugeniy Paltsev union bcr_slc_cfg slc_cfg; 29088ae27edSEugeniy Paltsev union bcr_clust_cfg cbcr; 291379b3280SAlexey Brodkin 29275790873SEugeniy Paltsev if (slc_exists()) { 293379b3280SAlexey Brodkin slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); 294*bf8974edSEugeniy Paltsev gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; 295379b3280SAlexey Brodkin } 296db6ce231SAlexey Brodkin 297db6ce231SAlexey Brodkin cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); 298b0146f9eSEugeniy Paltsev if (cbcr.fields.c && ioc_enable) 2993cf23939SEugeniy Paltsev ioc_exists = true; 30005c6a26aSEugeniy Paltsev 30105c6a26aSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 302379b3280SAlexey Brodkin } 303379b3280SAlexey Brodkin 304379b3280SAlexey Brodkin void read_decode_cache_bcr(void) 305379b3280SAlexey Brodkin { 306379b3280SAlexey Brodkin int dc_line_sz = 0, ic_line_sz = 0; 30788ae27edSEugeniy Paltsev union bcr_di_cache ibcr, dbcr; 308379b3280SAlexey Brodkin 309379b3280SAlexey Brodkin ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 310379b3280SAlexey Brodkin if (ibcr.fields.ver) { 311*bf8974edSEugeniy Paltsev gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; 312379b3280SAlexey Brodkin if (!ic_line_sz) 313379b3280SAlexey Brodkin panic("Instruction exists but line length is 0\n"); 314ef639e6fSAlexey Brodkin } 315ef639e6fSAlexey Brodkin 316379b3280SAlexey Brodkin dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 317379b3280SAlexey Brodkin if (dbcr.fields.ver) { 318*bf8974edSEugeniy Paltsev gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; 319379b3280SAlexey Brodkin if (!dc_line_sz) 320379b3280SAlexey Brodkin panic("Data cache exists but line length is 0\n"); 321379b3280SAlexey Brodkin } 322379b3280SAlexey Brodkin 323379b3280SAlexey Brodkin if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz)) 324379b3280SAlexey Brodkin panic("Instruction and data cache line lengths differ\n"); 325ef639e6fSAlexey Brodkin } 326ef639e6fSAlexey Brodkin 327ef639e6fSAlexey Brodkin void cache_init(void) 328ef639e6fSAlexey Brodkin { 329379b3280SAlexey Brodkin read_decode_cache_bcr(); 330379b3280SAlexey Brodkin 33105c6a26aSEugeniy Paltsev if (is_isa_arcv2()) 332379b3280SAlexey Brodkin read_decode_cache_bcr_arcv2(); 333db6ce231SAlexey Brodkin 33405c6a26aSEugeniy Paltsev if (is_isa_arcv2() && ioc_exists) 335a6f557c4SEugeniy Paltsev arc_ioc_setup(); 33641cada4dSEugeniy Paltsev 33741cada4dSEugeniy Paltsev /* 33841cada4dSEugeniy Paltsev * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist 33941cada4dSEugeniy Paltsev * only if PAE exists in current HW. So we had to check pae_exist 34041cada4dSEugeniy Paltsev * before using them. 34141cada4dSEugeniy Paltsev */ 34275790873SEugeniy Paltsev if (is_isa_arcv2() && slc_exists() && pae_exists()) 34341cada4dSEugeniy Paltsev slc_upper_region_init(); 344ef639e6fSAlexey Brodkin } 345ef639e6fSAlexey Brodkin 346660d5f0dSAlexey Brodkin int icache_status(void) 347660d5f0dSAlexey Brodkin { 34875790873SEugeniy Paltsev if (!icache_exists()) 349660d5f0dSAlexey Brodkin return 0; 350660d5f0dSAlexey Brodkin 351ef639e6fSAlexey Brodkin if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) 352ef639e6fSAlexey Brodkin return 0; 353ef639e6fSAlexey Brodkin else 354ef639e6fSAlexey Brodkin return 1; 355660d5f0dSAlexey Brodkin } 356660d5f0dSAlexey Brodkin 357660d5f0dSAlexey Brodkin void icache_enable(void) 358660d5f0dSAlexey Brodkin { 35975790873SEugeniy Paltsev if (icache_exists()) 360660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & 361660d5f0dSAlexey Brodkin ~IC_CTRL_CACHE_DISABLE); 362660d5f0dSAlexey Brodkin } 363660d5f0dSAlexey Brodkin 364660d5f0dSAlexey Brodkin void icache_disable(void) 365660d5f0dSAlexey Brodkin { 36675790873SEugeniy Paltsev if (icache_exists()) 367660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | 368660d5f0dSAlexey Brodkin IC_CTRL_CACHE_DISABLE); 369660d5f0dSAlexey Brodkin } 370660d5f0dSAlexey Brodkin 37116aeee81SEugeniy Paltsev /* IC supports only invalidation */ 37216aeee81SEugeniy Paltsev static inline void __ic_entire_invalidate(void) 373660d5f0dSAlexey Brodkin { 37416aeee81SEugeniy Paltsev if (!icache_status()) 37516aeee81SEugeniy Paltsev return; 37616aeee81SEugeniy Paltsev 377660d5f0dSAlexey Brodkin /* Any write to IC_IVIC register triggers invalidation of entire I$ */ 378660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_IVIC, 1); 379f2a22678SAlexey Brodkin /* 380f2a22678SAlexey Brodkin * As per ARC HS databook (see chapter 5.3.3.2) 381f2a22678SAlexey Brodkin * it is required to add 3 NOPs after each write to IC_IVIC. 382f2a22678SAlexey Brodkin */ 383f2a22678SAlexey Brodkin __builtin_arc_nop(); 384f2a22678SAlexey Brodkin __builtin_arc_nop(); 385f2a22678SAlexey Brodkin __builtin_arc_nop(); 386ef639e6fSAlexey Brodkin read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ 387660d5f0dSAlexey Brodkin } 38841cada4dSEugeniy Paltsev 38916aeee81SEugeniy Paltsev void invalidate_icache_all(void) 39016aeee81SEugeniy Paltsev { 39116aeee81SEugeniy Paltsev __ic_entire_invalidate(); 39216aeee81SEugeniy Paltsev 393ea9f6f1eSEugeniy Paltsev if (is_isa_arcv2()) 39441cada4dSEugeniy Paltsev __slc_entire_op(OP_INV); 39541cada4dSEugeniy Paltsev } 396660d5f0dSAlexey Brodkin 397660d5f0dSAlexey Brodkin int dcache_status(void) 398660d5f0dSAlexey Brodkin { 39975790873SEugeniy Paltsev if (!dcache_exists()) 400660d5f0dSAlexey Brodkin return 0; 401660d5f0dSAlexey Brodkin 402ef639e6fSAlexey Brodkin if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) 403ef639e6fSAlexey Brodkin return 0; 404ef639e6fSAlexey Brodkin else 405ef639e6fSAlexey Brodkin return 1; 406660d5f0dSAlexey Brodkin } 407660d5f0dSAlexey Brodkin 408660d5f0dSAlexey Brodkin void dcache_enable(void) 409660d5f0dSAlexey Brodkin { 41075790873SEugeniy Paltsev if (!dcache_exists()) 411660d5f0dSAlexey Brodkin return; 412660d5f0dSAlexey Brodkin 413660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & 414660d5f0dSAlexey Brodkin ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); 415660d5f0dSAlexey Brodkin } 416660d5f0dSAlexey Brodkin 417660d5f0dSAlexey Brodkin void dcache_disable(void) 418660d5f0dSAlexey Brodkin { 41975790873SEugeniy Paltsev if (!dcache_exists()) 420660d5f0dSAlexey Brodkin return; 421660d5f0dSAlexey Brodkin 422660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | 423660d5f0dSAlexey Brodkin DC_CTRL_CACHE_DISABLE); 424660d5f0dSAlexey Brodkin } 425660d5f0dSAlexey Brodkin 426c4ef14d2SEugeniy Paltsev /* Common Helper for Line Operations on D-cache */ 427c4ef14d2SEugeniy Paltsev static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, 428ef639e6fSAlexey Brodkin const int cacheop) 429660d5f0dSAlexey Brodkin { 430ef639e6fSAlexey Brodkin unsigned int aux_cmd; 431ef639e6fSAlexey Brodkin int num_lines; 432660d5f0dSAlexey Brodkin 433ef639e6fSAlexey Brodkin /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 434ef639e6fSAlexey Brodkin aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; 435660d5f0dSAlexey Brodkin 436ef639e6fSAlexey Brodkin sz += paddr & ~CACHE_LINE_MASK; 437ef639e6fSAlexey Brodkin paddr &= CACHE_LINE_MASK; 438ef639e6fSAlexey Brodkin 439*bf8974edSEugeniy Paltsev num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz); 440ef639e6fSAlexey Brodkin 441ef639e6fSAlexey Brodkin while (num_lines-- > 0) { 442ef639e6fSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 443c4ef14d2SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_PTAG, paddr); 444ef639e6fSAlexey Brodkin #endif 445ef639e6fSAlexey Brodkin write_aux_reg(aux_cmd, paddr); 446*bf8974edSEugeniy Paltsev paddr += gd->arch.l1_line_sz; 447ef639e6fSAlexey Brodkin } 448ef639e6fSAlexey Brodkin } 449ef639e6fSAlexey Brodkin 4505d7a24d6SEugeniy Paltsev static void __before_dc_op(const int op) 451ef639e6fSAlexey Brodkin { 4525d7a24d6SEugeniy Paltsev unsigned int ctrl; 453ef639e6fSAlexey Brodkin 4545d7a24d6SEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_DC_CTRL); 4555d7a24d6SEugeniy Paltsev 4565d7a24d6SEugeniy Paltsev /* IM bit implies flush-n-inv, instead of vanilla inv */ 4575d7a24d6SEugeniy Paltsev if (op == OP_INV) 4585d7a24d6SEugeniy Paltsev ctrl &= ~DC_CTRL_INV_MODE_FLUSH; 4595d7a24d6SEugeniy Paltsev else 4605d7a24d6SEugeniy Paltsev ctrl |= DC_CTRL_INV_MODE_FLUSH; 4615d7a24d6SEugeniy Paltsev 4625d7a24d6SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_CTRL, ctrl); 463ef639e6fSAlexey Brodkin } 464ef639e6fSAlexey Brodkin 4655d7a24d6SEugeniy Paltsev static void __after_dc_op(const int op) 466ef639e6fSAlexey Brodkin { 467ef639e6fSAlexey Brodkin if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ 46819b10a42SEugeniy Paltsev while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); 469ef639e6fSAlexey Brodkin } 470ef639e6fSAlexey Brodkin 471ef639e6fSAlexey Brodkin static inline void __dc_entire_op(const int cacheop) 472ef639e6fSAlexey Brodkin { 473ef639e6fSAlexey Brodkin int aux; 4745d7a24d6SEugeniy Paltsev 475c877a891SEugeniy Paltsev if (!dcache_status()) 476c877a891SEugeniy Paltsev return; 477c877a891SEugeniy Paltsev 4785d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 479ef639e6fSAlexey Brodkin 480ef639e6fSAlexey Brodkin if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 481ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_IVDC; 482ef639e6fSAlexey Brodkin else 483ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_FLSH; 484ef639e6fSAlexey Brodkin 485ef639e6fSAlexey Brodkin write_aux_reg(aux, 0x1); 486ef639e6fSAlexey Brodkin 4875d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 488ef639e6fSAlexey Brodkin } 489ef639e6fSAlexey Brodkin 490ef639e6fSAlexey Brodkin static inline void __dc_line_op(unsigned long paddr, unsigned long sz, 491ef639e6fSAlexey Brodkin const int cacheop) 492ef639e6fSAlexey Brodkin { 493c877a891SEugeniy Paltsev if (!dcache_status()) 494c877a891SEugeniy Paltsev return; 495c877a891SEugeniy Paltsev 4965d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 497c4ef14d2SEugeniy Paltsev __dcache_line_loop(paddr, sz, cacheop); 4985d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 499ef639e6fSAlexey Brodkin } 500ef639e6fSAlexey Brodkin 501660d5f0dSAlexey Brodkin void invalidate_dcache_range(unsigned long start, unsigned long end) 502660d5f0dSAlexey Brodkin { 50341cada4dSEugeniy Paltsev if (start >= end) 50441cada4dSEugeniy Paltsev return; 50541cada4dSEugeniy Paltsev 50605c6a26aSEugeniy Paltsev /* 50705c6a26aSEugeniy Paltsev * ARCv1 -> call __dc_line_op 50805c6a26aSEugeniy Paltsev * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 50905c6a26aSEugeniy Paltsev * ARCv2 && IOC enabled -> nothing 51005c6a26aSEugeniy Paltsev */ 51105c6a26aSEugeniy Paltsev if (!is_isa_arcv2() || !ioc_exists) 512db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_INV); 513db6ce231SAlexey Brodkin 514ea9f6f1eSEugeniy Paltsev if (is_isa_arcv2() && !ioc_exists) 51541cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_INV); 516660d5f0dSAlexey Brodkin } 517660d5f0dSAlexey Brodkin 518ef639e6fSAlexey Brodkin void flush_dcache_range(unsigned long start, unsigned long end) 519660d5f0dSAlexey Brodkin { 52041cada4dSEugeniy Paltsev if (start >= end) 52141cada4dSEugeniy Paltsev return; 52241cada4dSEugeniy Paltsev 52305c6a26aSEugeniy Paltsev /* 52405c6a26aSEugeniy Paltsev * ARCv1 -> call __dc_line_op 52505c6a26aSEugeniy Paltsev * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 52605c6a26aSEugeniy Paltsev * ARCv2 && IOC enabled -> nothing 52705c6a26aSEugeniy Paltsev */ 52805c6a26aSEugeniy Paltsev if (!is_isa_arcv2() || !ioc_exists) 529db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_FLUSH); 530db6ce231SAlexey Brodkin 531ea9f6f1eSEugeniy Paltsev if (is_isa_arcv2() && !ioc_exists) 53241cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_FLUSH); 533660d5f0dSAlexey Brodkin } 534660d5f0dSAlexey Brodkin 535660d5f0dSAlexey Brodkin void flush_cache(unsigned long start, unsigned long size) 536660d5f0dSAlexey Brodkin { 537660d5f0dSAlexey Brodkin flush_dcache_range(start, start + size); 538660d5f0dSAlexey Brodkin } 5396eb15e50SAlexey Brodkin 540c27814beSEugeniy Paltsev /* 541c27814beSEugeniy Paltsev * As invalidate_dcache_all() is not used in generic U-Boot code and as we 542c27814beSEugeniy Paltsev * don't need it in arch/arc code alone (invalidate without flush) we implement 543c27814beSEugeniy Paltsev * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because 544c27814beSEugeniy Paltsev * it's much safer. See [ NOTE 1 ] for more details. 545c27814beSEugeniy Paltsev */ 546c27814beSEugeniy Paltsev void flush_n_invalidate_dcache_all(void) 547ef639e6fSAlexey Brodkin { 548c27814beSEugeniy Paltsev __dc_entire_op(OP_FLUSH_N_INV); 549db6ce231SAlexey Brodkin 550ea9f6f1eSEugeniy Paltsev if (is_isa_arcv2()) 551c27814beSEugeniy Paltsev __slc_entire_op(OP_FLUSH_N_INV); 5526eb15e50SAlexey Brodkin } 5536eb15e50SAlexey Brodkin 554ef639e6fSAlexey Brodkin void flush_dcache_all(void) 5556eb15e50SAlexey Brodkin { 556db6ce231SAlexey Brodkin __dc_entire_op(OP_FLUSH); 557db6ce231SAlexey Brodkin 558ea9f6f1eSEugeniy Paltsev if (is_isa_arcv2()) 559ef639e6fSAlexey Brodkin __slc_entire_op(OP_FLUSH); 5606eb15e50SAlexey Brodkin } 561