1660d5f0dSAlexey Brodkin /* 2660d5f0dSAlexey Brodkin * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3660d5f0dSAlexey Brodkin * 4660d5f0dSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5660d5f0dSAlexey Brodkin */ 6660d5f0dSAlexey Brodkin 7660d5f0dSAlexey Brodkin #include <config.h> 8379b3280SAlexey Brodkin #include <common.h> 9ef639e6fSAlexey Brodkin #include <linux/compiler.h> 10ef639e6fSAlexey Brodkin #include <linux/kernel.h> 1197a63144SAlexey Brodkin #include <linux/log2.h> 12660d5f0dSAlexey Brodkin #include <asm/arcregs.h> 13205e7a7bSAlexey Brodkin #include <asm/cache.h> 14660d5f0dSAlexey Brodkin 15c27814beSEugeniy Paltsev /* 16c27814beSEugeniy Paltsev * [ NOTE 1 ]: 17c27814beSEugeniy Paltsev * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable 18c27814beSEugeniy Paltsev * operation may result in unexpected behavior and data loss even if we flush 19c27814beSEugeniy Paltsev * data cache right before invalidation. That may happens if we store any context 20c27814beSEugeniy Paltsev * on stack (like we store BLINK register on stack before function call). 21c27814beSEugeniy Paltsev * BLINK register is the register where return address is automatically saved 22c27814beSEugeniy Paltsev * when we do function call with instructions like 'bl'. 23c27814beSEugeniy Paltsev * 24c27814beSEugeniy Paltsev * There is the real example: 25c27814beSEugeniy Paltsev * We may hang in the next code as we store any BLINK register on stack in 26c27814beSEugeniy Paltsev * invalidate_dcache_all() function. 27c27814beSEugeniy Paltsev * 28c27814beSEugeniy Paltsev * void flush_dcache_all() { 29c27814beSEugeniy Paltsev * __dc_entire_op(OP_FLUSH); 30c27814beSEugeniy Paltsev * // Other code // 31c27814beSEugeniy Paltsev * } 32c27814beSEugeniy Paltsev * 33c27814beSEugeniy Paltsev * void invalidate_dcache_all() { 34c27814beSEugeniy Paltsev * __dc_entire_op(OP_INV); 35c27814beSEugeniy Paltsev * // Other code // 36c27814beSEugeniy Paltsev * } 37c27814beSEugeniy Paltsev * 38c27814beSEugeniy Paltsev * void foo(void) { 39c27814beSEugeniy Paltsev * flush_dcache_all(); 40c27814beSEugeniy Paltsev * invalidate_dcache_all(); 41c27814beSEugeniy Paltsev * } 42c27814beSEugeniy Paltsev * 43c27814beSEugeniy Paltsev * Now let's see what really happens during that code execution: 44c27814beSEugeniy Paltsev * 45c27814beSEugeniy Paltsev * foo() 46c27814beSEugeniy Paltsev * |->> call flush_dcache_all 47c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 48c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 1] 49c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 50c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 51c27814beSEugeniy Paltsev * [flush L1 D$] 52c27814beSEugeniy Paltsev * return [jump to BLINK] 53c27814beSEugeniy Paltsev * <<------ 54c27814beSEugeniy Paltsev * [other flush_dcache_all code] 55c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 56c27814beSEugeniy Paltsev * return [jump to BLINK] 57c27814beSEugeniy Paltsev * <<------ 58c27814beSEugeniy Paltsev * |->> call invalidate_dcache_all 59c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 60c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 2] 61c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 62c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 63c27814beSEugeniy Paltsev * [invalidate L1 D$] ![point 3] 64c27814beSEugeniy Paltsev * // Oops!!! 65c27814beSEugeniy Paltsev * // We lose return address from invalidate_dcache_all function: 66c27814beSEugeniy Paltsev * // we save it to stack and invalidate L1 D$ after that! 67c27814beSEugeniy Paltsev * return [jump to BLINK] 68c27814beSEugeniy Paltsev * <<------ 69c27814beSEugeniy Paltsev * [other invalidate_dcache_all code] 70c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 71c27814beSEugeniy Paltsev * // we don't have this data in L1 dcache as we invalidated it in [point 3] 72c27814beSEugeniy Paltsev * // so we get it from next memory level (for example DDR memory) 73c27814beSEugeniy Paltsev * // but in the memory we have value which we save in [point 1], which 74c27814beSEugeniy Paltsev * // is return address from flush_dcache_all function (instead of 75c27814beSEugeniy Paltsev * // address from current invalidate_dcache_all function which we 76c27814beSEugeniy Paltsev * // saved in [point 2] !) 77c27814beSEugeniy Paltsev * return [jump to BLINK] 78c27814beSEugeniy Paltsev * <<------ 79c27814beSEugeniy Paltsev * // As BLINK points to invalidate_dcache_all, we call it again and 80c27814beSEugeniy Paltsev * // loop forever. 81c27814beSEugeniy Paltsev * 82c27814beSEugeniy Paltsev * Fortunately we may fix that by using flush & invalidation of D$ with a single 83c27814beSEugeniy Paltsev * one instruction (instead of flush and invalidation instructions pair) and 84c27814beSEugeniy Paltsev * enabling force function inline with '__attribute__((always_inline))' gcc 85c27814beSEugeniy Paltsev * attribute to avoid any function call (and BLINK store) between cache flush 86c27814beSEugeniy Paltsev * and disable. 87c27814beSEugeniy Paltsev */ 88c27814beSEugeniy Paltsev 89660d5f0dSAlexey Brodkin /* Bit values in IC_CTRL */ 9019b10a42SEugeniy Paltsev #define IC_CTRL_CACHE_DISABLE BIT(0) 91660d5f0dSAlexey Brodkin 92660d5f0dSAlexey Brodkin /* Bit values in DC_CTRL */ 9319b10a42SEugeniy Paltsev #define DC_CTRL_CACHE_DISABLE BIT(0) 9419b10a42SEugeniy Paltsev #define DC_CTRL_INV_MODE_FLUSH BIT(6) 9519b10a42SEugeniy Paltsev #define DC_CTRL_FLUSH_STATUS BIT(8) 96660d5f0dSAlexey Brodkin #define CACHE_VER_NUM_MASK 0xF 97660d5f0dSAlexey Brodkin 985d7a24d6SEugeniy Paltsev #define OP_INV BIT(0) 995d7a24d6SEugeniy Paltsev #define OP_FLUSH BIT(1) 1005d7a24d6SEugeniy Paltsev #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV) 101ef639e6fSAlexey Brodkin 10241cada4dSEugeniy Paltsev /* Bit val in SLC_CONTROL */ 10341cada4dSEugeniy Paltsev #define SLC_CTRL_DIS 0x001 10441cada4dSEugeniy Paltsev #define SLC_CTRL_IM 0x040 10541cada4dSEugeniy Paltsev #define SLC_CTRL_BUSY 0x100 10641cada4dSEugeniy Paltsev #define SLC_CTRL_RGN_OP_INV 0x200 10741cada4dSEugeniy Paltsev 108ef639e6fSAlexey Brodkin /* 109ef639e6fSAlexey Brodkin * By default that variable will fall into .bss section. 110ef639e6fSAlexey Brodkin * But .bss section is not relocated and so it will be initilized before 111ef639e6fSAlexey Brodkin * relocation but will be used after being zeroed. 112ef639e6fSAlexey Brodkin */ 113379b3280SAlexey Brodkin int l1_line_sz __section(".data"); 1143cf23939SEugeniy Paltsev bool dcache_exists __section(".data") = false; 1153cf23939SEugeniy Paltsev bool icache_exists __section(".data") = false; 116379b3280SAlexey Brodkin 117379b3280SAlexey Brodkin #define CACHE_LINE_MASK (~(l1_line_sz - 1)) 118379b3280SAlexey Brodkin 119379b3280SAlexey Brodkin #ifdef CONFIG_ISA_ARCV2 120ef639e6fSAlexey Brodkin int slc_line_sz __section(".data"); 1213cf23939SEugeniy Paltsev bool slc_exists __section(".data") = false; 1223cf23939SEugeniy Paltsev bool ioc_exists __section(".data") = false; 12341cada4dSEugeniy Paltsev bool pae_exists __section(".data") = false; 124ef639e6fSAlexey Brodkin 125b0146f9eSEugeniy Paltsev /* To force enable IOC set ioc_enable to 'true' */ 126b0146f9eSEugeniy Paltsev bool ioc_enable __section(".data") = false; 127b0146f9eSEugeniy Paltsev 12841cada4dSEugeniy Paltsev void read_decode_mmu_bcr(void) 129ef639e6fSAlexey Brodkin { 13041cada4dSEugeniy Paltsev /* TODO: should we compare mmu version from BCR and from CONFIG? */ 13141cada4dSEugeniy Paltsev #if (CONFIG_ARC_MMU_VER >= 4) 13241cada4dSEugeniy Paltsev u32 tmp; 133ef639e6fSAlexey Brodkin 13441cada4dSEugeniy Paltsev tmp = read_aux_reg(ARC_AUX_MMU_BCR); 135ef639e6fSAlexey Brodkin 13641cada4dSEugeniy Paltsev struct bcr_mmu_4 { 13741cada4dSEugeniy Paltsev #ifdef CONFIG_CPU_BIG_ENDIAN 13841cada4dSEugeniy Paltsev unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, 13941cada4dSEugeniy Paltsev n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; 140ef639e6fSAlexey Brodkin #else 14141cada4dSEugeniy Paltsev /* DTLB ITLB JES JE JA */ 14241cada4dSEugeniy Paltsev unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, 14341cada4dSEugeniy Paltsev pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; 14441cada4dSEugeniy Paltsev #endif /* CONFIG_CPU_BIG_ENDIAN */ 14541cada4dSEugeniy Paltsev } *mmu4; 14641cada4dSEugeniy Paltsev 14741cada4dSEugeniy Paltsev mmu4 = (struct bcr_mmu_4 *)&tmp; 14841cada4dSEugeniy Paltsev 14941cada4dSEugeniy Paltsev pae_exists = !!mmu4->pae; 15041cada4dSEugeniy Paltsev #endif /* (CONFIG_ARC_MMU_VER >= 4) */ 15141cada4dSEugeniy Paltsev } 15241cada4dSEugeniy Paltsev 15341cada4dSEugeniy Paltsev static void __slc_entire_op(const int op) 15441cada4dSEugeniy Paltsev { 15541cada4dSEugeniy Paltsev unsigned int ctrl; 15641cada4dSEugeniy Paltsev 15741cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 15841cada4dSEugeniy Paltsev 15941cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 16041cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 16141cada4dSEugeniy Paltsev else 16241cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 16341cada4dSEugeniy Paltsev 16441cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 16541cada4dSEugeniy Paltsev 16641cada4dSEugeniy Paltsev if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 16741cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); 16841cada4dSEugeniy Paltsev else 16941cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); 17041cada4dSEugeniy Paltsev 17141cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 17241cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 17341cada4dSEugeniy Paltsev 17441cada4dSEugeniy Paltsev /* Important to wait for flush to complete */ 17541cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 17641cada4dSEugeniy Paltsev } 17741cada4dSEugeniy Paltsev 17841cada4dSEugeniy Paltsev static void slc_upper_region_init(void) 17941cada4dSEugeniy Paltsev { 18041cada4dSEugeniy Paltsev /* 18141cada4dSEugeniy Paltsev * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 18241cada4dSEugeniy Paltsev * as we don't use PAE40. 18341cada4dSEugeniy Paltsev */ 18441cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); 18541cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); 18641cada4dSEugeniy Paltsev } 18741cada4dSEugeniy Paltsev 18841cada4dSEugeniy Paltsev static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) 18941cada4dSEugeniy Paltsev { 19041cada4dSEugeniy Paltsev unsigned int ctrl; 19141cada4dSEugeniy Paltsev unsigned long end; 19241cada4dSEugeniy Paltsev 19341cada4dSEugeniy Paltsev /* 19441cada4dSEugeniy Paltsev * The Region Flush operation is specified by CTRL.RGN_OP[11..9] 19541cada4dSEugeniy Paltsev * - b'000 (default) is Flush, 19641cada4dSEugeniy Paltsev * - b'001 is Invalidate if CTRL.IM == 0 19741cada4dSEugeniy Paltsev * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 19841cada4dSEugeniy Paltsev */ 19941cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 20041cada4dSEugeniy Paltsev 20141cada4dSEugeniy Paltsev /* Don't rely on default value of IM bit */ 20241cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 20341cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 20441cada4dSEugeniy Paltsev else 20541cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 20641cada4dSEugeniy Paltsev 20741cada4dSEugeniy Paltsev if (op & OP_INV) 20841cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ 20941cada4dSEugeniy Paltsev else 21041cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_RGN_OP_INV; 21141cada4dSEugeniy Paltsev 21241cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 21341cada4dSEugeniy Paltsev 21441cada4dSEugeniy Paltsev /* 21541cada4dSEugeniy Paltsev * Lower bits are ignored, no need to clip 21641cada4dSEugeniy Paltsev * END needs to be setup before START (latter triggers the operation) 21741cada4dSEugeniy Paltsev * END can't be same as START, so add (l2_line_sz - 1) to sz 21841cada4dSEugeniy Paltsev */ 21941cada4dSEugeniy Paltsev end = paddr + sz + slc_line_sz - 1; 22041cada4dSEugeniy Paltsev 22141cada4dSEugeniy Paltsev /* 22241cada4dSEugeniy Paltsev * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) 22341cada4dSEugeniy Paltsev * are always == 0 as we don't use PAE40, so we only setup lower ones 22441cada4dSEugeniy Paltsev * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START) 22541cada4dSEugeniy Paltsev */ 22641cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END, end); 22741cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); 22841cada4dSEugeniy Paltsev 22941cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 23041cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 23141cada4dSEugeniy Paltsev 23241cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 23341cada4dSEugeniy Paltsev } 234*a6f557c4SEugeniy Paltsev 235*a6f557c4SEugeniy Paltsev static void arc_ioc_setup(void) 236*a6f557c4SEugeniy Paltsev { 237*a6f557c4SEugeniy Paltsev /* IOC Aperture start is equal to DDR start */ 238*a6f557c4SEugeniy Paltsev unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; 239*a6f557c4SEugeniy Paltsev /* IOC Aperture size is equal to DDR size */ 240*a6f557c4SEugeniy Paltsev long ap_size = CONFIG_SYS_SDRAM_SIZE; 241*a6f557c4SEugeniy Paltsev 242*a6f557c4SEugeniy Paltsev flush_n_invalidate_dcache_all(); 243*a6f557c4SEugeniy Paltsev 244*a6f557c4SEugeniy Paltsev if (!is_power_of_2(ap_size) || ap_size < 4096) 245*a6f557c4SEugeniy Paltsev panic("IOC Aperture size must be power of 2 and bigger 4Kib"); 246*a6f557c4SEugeniy Paltsev 247*a6f557c4SEugeniy Paltsev /* 248*a6f557c4SEugeniy Paltsev * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, 249*a6f557c4SEugeniy Paltsev * so setting 0x11 implies 512M, 0x12 implies 1G... 250*a6f557c4SEugeniy Paltsev */ 251*a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 252*a6f557c4SEugeniy Paltsev order_base_2(ap_size / 1024) - 2); 253*a6f557c4SEugeniy Paltsev 254*a6f557c4SEugeniy Paltsev /* IOC Aperture start must be aligned to the size of the aperture */ 255*a6f557c4SEugeniy Paltsev if (ap_base % ap_size != 0) 256*a6f557c4SEugeniy Paltsev panic("IOC Aperture start must be aligned to the size of the aperture"); 257*a6f557c4SEugeniy Paltsev 258*a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); 259*a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); 260*a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); 261*a6f557c4SEugeniy Paltsev } 26241cada4dSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 263ef639e6fSAlexey Brodkin 264379b3280SAlexey Brodkin #ifdef CONFIG_ISA_ARCV2 265379b3280SAlexey Brodkin static void read_decode_cache_bcr_arcv2(void) 266ef639e6fSAlexey Brodkin { 267379b3280SAlexey Brodkin union { 268379b3280SAlexey Brodkin struct { 269379b3280SAlexey Brodkin #ifdef CONFIG_CPU_BIG_ENDIAN 270379b3280SAlexey Brodkin unsigned int pad:24, way:2, lsz:2, sz:4; 271379b3280SAlexey Brodkin #else 272379b3280SAlexey Brodkin unsigned int sz:4, lsz:2, way:2, pad:24; 273379b3280SAlexey Brodkin #endif 274379b3280SAlexey Brodkin } fields; 275379b3280SAlexey Brodkin unsigned int word; 276379b3280SAlexey Brodkin } slc_cfg; 277379b3280SAlexey Brodkin 278379b3280SAlexey Brodkin union { 279379b3280SAlexey Brodkin struct { 280379b3280SAlexey Brodkin #ifdef CONFIG_CPU_BIG_ENDIAN 281379b3280SAlexey Brodkin unsigned int pad:24, ver:8; 282379b3280SAlexey Brodkin #else 283379b3280SAlexey Brodkin unsigned int ver:8, pad:24; 284379b3280SAlexey Brodkin #endif 285379b3280SAlexey Brodkin } fields; 286379b3280SAlexey Brodkin unsigned int word; 287379b3280SAlexey Brodkin } sbcr; 288379b3280SAlexey Brodkin 289379b3280SAlexey Brodkin sbcr.word = read_aux_reg(ARC_BCR_SLC); 290379b3280SAlexey Brodkin if (sbcr.fields.ver) { 291379b3280SAlexey Brodkin slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); 2923cf23939SEugeniy Paltsev slc_exists = true; 293379b3280SAlexey Brodkin slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; 294379b3280SAlexey Brodkin } 295db6ce231SAlexey Brodkin 296db6ce231SAlexey Brodkin union { 297db6ce231SAlexey Brodkin struct bcr_clust_cfg { 298db6ce231SAlexey Brodkin #ifdef CONFIG_CPU_BIG_ENDIAN 299db6ce231SAlexey Brodkin unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; 300db6ce231SAlexey Brodkin #else 301db6ce231SAlexey Brodkin unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; 302db6ce231SAlexey Brodkin #endif 303db6ce231SAlexey Brodkin } fields; 304db6ce231SAlexey Brodkin unsigned int word; 305db6ce231SAlexey Brodkin } cbcr; 306db6ce231SAlexey Brodkin 307db6ce231SAlexey Brodkin cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); 308b0146f9eSEugeniy Paltsev if (cbcr.fields.c && ioc_enable) 3093cf23939SEugeniy Paltsev ioc_exists = true; 310379b3280SAlexey Brodkin } 311379b3280SAlexey Brodkin #endif 312379b3280SAlexey Brodkin 313379b3280SAlexey Brodkin void read_decode_cache_bcr(void) 314379b3280SAlexey Brodkin { 315379b3280SAlexey Brodkin int dc_line_sz = 0, ic_line_sz = 0; 316379b3280SAlexey Brodkin 317379b3280SAlexey Brodkin union { 318379b3280SAlexey Brodkin struct { 319379b3280SAlexey Brodkin #ifdef CONFIG_CPU_BIG_ENDIAN 320379b3280SAlexey Brodkin unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; 321379b3280SAlexey Brodkin #else 322379b3280SAlexey Brodkin unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; 323379b3280SAlexey Brodkin #endif 324379b3280SAlexey Brodkin } fields; 325379b3280SAlexey Brodkin unsigned int word; 326379b3280SAlexey Brodkin } ibcr, dbcr; 327379b3280SAlexey Brodkin 328379b3280SAlexey Brodkin ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 329379b3280SAlexey Brodkin if (ibcr.fields.ver) { 3303cf23939SEugeniy Paltsev icache_exists = true; 331379b3280SAlexey Brodkin l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; 332379b3280SAlexey Brodkin if (!ic_line_sz) 333379b3280SAlexey Brodkin panic("Instruction exists but line length is 0\n"); 334ef639e6fSAlexey Brodkin } 335ef639e6fSAlexey Brodkin 336379b3280SAlexey Brodkin dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 337379b3280SAlexey Brodkin if (dbcr.fields.ver) { 3383cf23939SEugeniy Paltsev dcache_exists = true; 339379b3280SAlexey Brodkin l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; 340379b3280SAlexey Brodkin if (!dc_line_sz) 341379b3280SAlexey Brodkin panic("Data cache exists but line length is 0\n"); 342379b3280SAlexey Brodkin } 343379b3280SAlexey Brodkin 344379b3280SAlexey Brodkin if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz)) 345379b3280SAlexey Brodkin panic("Instruction and data cache line lengths differ\n"); 346ef639e6fSAlexey Brodkin } 347ef639e6fSAlexey Brodkin 348ef639e6fSAlexey Brodkin void cache_init(void) 349ef639e6fSAlexey Brodkin { 350379b3280SAlexey Brodkin read_decode_cache_bcr(); 351379b3280SAlexey Brodkin 352ef639e6fSAlexey Brodkin #ifdef CONFIG_ISA_ARCV2 353379b3280SAlexey Brodkin read_decode_cache_bcr_arcv2(); 354db6ce231SAlexey Brodkin 355*a6f557c4SEugeniy Paltsev if (ioc_exists) 356*a6f557c4SEugeniy Paltsev arc_ioc_setup(); 35741cada4dSEugeniy Paltsev 35841cada4dSEugeniy Paltsev read_decode_mmu_bcr(); 35941cada4dSEugeniy Paltsev 36041cada4dSEugeniy Paltsev /* 36141cada4dSEugeniy Paltsev * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist 36241cada4dSEugeniy Paltsev * only if PAE exists in current HW. So we had to check pae_exist 36341cada4dSEugeniy Paltsev * before using them. 36441cada4dSEugeniy Paltsev */ 36541cada4dSEugeniy Paltsev if (slc_exists && pae_exists) 36641cada4dSEugeniy Paltsev slc_upper_region_init(); 36741cada4dSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 368ef639e6fSAlexey Brodkin } 369ef639e6fSAlexey Brodkin 370660d5f0dSAlexey Brodkin int icache_status(void) 371660d5f0dSAlexey Brodkin { 372379b3280SAlexey Brodkin if (!icache_exists) 373660d5f0dSAlexey Brodkin return 0; 374660d5f0dSAlexey Brodkin 375ef639e6fSAlexey Brodkin if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) 376ef639e6fSAlexey Brodkin return 0; 377ef639e6fSAlexey Brodkin else 378ef639e6fSAlexey Brodkin return 1; 379660d5f0dSAlexey Brodkin } 380660d5f0dSAlexey Brodkin 381660d5f0dSAlexey Brodkin void icache_enable(void) 382660d5f0dSAlexey Brodkin { 383379b3280SAlexey Brodkin if (icache_exists) 384660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & 385660d5f0dSAlexey Brodkin ~IC_CTRL_CACHE_DISABLE); 386660d5f0dSAlexey Brodkin } 387660d5f0dSAlexey Brodkin 388660d5f0dSAlexey Brodkin void icache_disable(void) 389660d5f0dSAlexey Brodkin { 390379b3280SAlexey Brodkin if (icache_exists) 391660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | 392660d5f0dSAlexey Brodkin IC_CTRL_CACHE_DISABLE); 393660d5f0dSAlexey Brodkin } 394660d5f0dSAlexey Brodkin 39516aeee81SEugeniy Paltsev /* IC supports only invalidation */ 39616aeee81SEugeniy Paltsev static inline void __ic_entire_invalidate(void) 397660d5f0dSAlexey Brodkin { 39816aeee81SEugeniy Paltsev if (!icache_status()) 39916aeee81SEugeniy Paltsev return; 40016aeee81SEugeniy Paltsev 401660d5f0dSAlexey Brodkin /* Any write to IC_IVIC register triggers invalidation of entire I$ */ 402660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_IVIC, 1); 403f2a22678SAlexey Brodkin /* 404f2a22678SAlexey Brodkin * As per ARC HS databook (see chapter 5.3.3.2) 405f2a22678SAlexey Brodkin * it is required to add 3 NOPs after each write to IC_IVIC. 406f2a22678SAlexey Brodkin */ 407f2a22678SAlexey Brodkin __builtin_arc_nop(); 408f2a22678SAlexey Brodkin __builtin_arc_nop(); 409f2a22678SAlexey Brodkin __builtin_arc_nop(); 410ef639e6fSAlexey Brodkin read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ 411660d5f0dSAlexey Brodkin } 41241cada4dSEugeniy Paltsev 41316aeee81SEugeniy Paltsev void invalidate_icache_all(void) 41416aeee81SEugeniy Paltsev { 41516aeee81SEugeniy Paltsev __ic_entire_invalidate(); 41616aeee81SEugeniy Paltsev 41741cada4dSEugeniy Paltsev #ifdef CONFIG_ISA_ARCV2 41841cada4dSEugeniy Paltsev if (slc_exists) 41941cada4dSEugeniy Paltsev __slc_entire_op(OP_INV); 420ef639e6fSAlexey Brodkin #endif 42141cada4dSEugeniy Paltsev } 422660d5f0dSAlexey Brodkin 423660d5f0dSAlexey Brodkin int dcache_status(void) 424660d5f0dSAlexey Brodkin { 425379b3280SAlexey Brodkin if (!dcache_exists) 426660d5f0dSAlexey Brodkin return 0; 427660d5f0dSAlexey Brodkin 428ef639e6fSAlexey Brodkin if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) 429ef639e6fSAlexey Brodkin return 0; 430ef639e6fSAlexey Brodkin else 431ef639e6fSAlexey Brodkin return 1; 432660d5f0dSAlexey Brodkin } 433660d5f0dSAlexey Brodkin 434660d5f0dSAlexey Brodkin void dcache_enable(void) 435660d5f0dSAlexey Brodkin { 436379b3280SAlexey Brodkin if (!dcache_exists) 437660d5f0dSAlexey Brodkin return; 438660d5f0dSAlexey Brodkin 439660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & 440660d5f0dSAlexey Brodkin ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); 441660d5f0dSAlexey Brodkin } 442660d5f0dSAlexey Brodkin 443660d5f0dSAlexey Brodkin void dcache_disable(void) 444660d5f0dSAlexey Brodkin { 445379b3280SAlexey Brodkin if (!dcache_exists) 446660d5f0dSAlexey Brodkin return; 447660d5f0dSAlexey Brodkin 448660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | 449660d5f0dSAlexey Brodkin DC_CTRL_CACHE_DISABLE); 450660d5f0dSAlexey Brodkin } 451660d5f0dSAlexey Brodkin 452660d5f0dSAlexey Brodkin #ifndef CONFIG_SYS_DCACHE_OFF 453c4ef14d2SEugeniy Paltsev /* Common Helper for Line Operations on D-cache */ 454c4ef14d2SEugeniy Paltsev static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, 455ef639e6fSAlexey Brodkin const int cacheop) 456660d5f0dSAlexey Brodkin { 457ef639e6fSAlexey Brodkin unsigned int aux_cmd; 458ef639e6fSAlexey Brodkin int num_lines; 459660d5f0dSAlexey Brodkin 460ef639e6fSAlexey Brodkin /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 461ef639e6fSAlexey Brodkin aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; 462660d5f0dSAlexey Brodkin 463ef639e6fSAlexey Brodkin sz += paddr & ~CACHE_LINE_MASK; 464ef639e6fSAlexey Brodkin paddr &= CACHE_LINE_MASK; 465ef639e6fSAlexey Brodkin 466379b3280SAlexey Brodkin num_lines = DIV_ROUND_UP(sz, l1_line_sz); 467ef639e6fSAlexey Brodkin 468ef639e6fSAlexey Brodkin while (num_lines-- > 0) { 469ef639e6fSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 470c4ef14d2SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_PTAG, paddr); 471ef639e6fSAlexey Brodkin #endif 472ef639e6fSAlexey Brodkin write_aux_reg(aux_cmd, paddr); 473379b3280SAlexey Brodkin paddr += l1_line_sz; 474ef639e6fSAlexey Brodkin } 475ef639e6fSAlexey Brodkin } 476ef639e6fSAlexey Brodkin 4775d7a24d6SEugeniy Paltsev static void __before_dc_op(const int op) 478ef639e6fSAlexey Brodkin { 4795d7a24d6SEugeniy Paltsev unsigned int ctrl; 480ef639e6fSAlexey Brodkin 4815d7a24d6SEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_DC_CTRL); 4825d7a24d6SEugeniy Paltsev 4835d7a24d6SEugeniy Paltsev /* IM bit implies flush-n-inv, instead of vanilla inv */ 4845d7a24d6SEugeniy Paltsev if (op == OP_INV) 4855d7a24d6SEugeniy Paltsev ctrl &= ~DC_CTRL_INV_MODE_FLUSH; 4865d7a24d6SEugeniy Paltsev else 4875d7a24d6SEugeniy Paltsev ctrl |= DC_CTRL_INV_MODE_FLUSH; 4885d7a24d6SEugeniy Paltsev 4895d7a24d6SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_CTRL, ctrl); 490ef639e6fSAlexey Brodkin } 491ef639e6fSAlexey Brodkin 4925d7a24d6SEugeniy Paltsev static void __after_dc_op(const int op) 493ef639e6fSAlexey Brodkin { 494ef639e6fSAlexey Brodkin if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ 49519b10a42SEugeniy Paltsev while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); 496ef639e6fSAlexey Brodkin } 497ef639e6fSAlexey Brodkin 498ef639e6fSAlexey Brodkin static inline void __dc_entire_op(const int cacheop) 499ef639e6fSAlexey Brodkin { 500ef639e6fSAlexey Brodkin int aux; 5015d7a24d6SEugeniy Paltsev 5025d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 503ef639e6fSAlexey Brodkin 504ef639e6fSAlexey Brodkin if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 505ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_IVDC; 506ef639e6fSAlexey Brodkin else 507ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_FLSH; 508ef639e6fSAlexey Brodkin 509ef639e6fSAlexey Brodkin write_aux_reg(aux, 0x1); 510ef639e6fSAlexey Brodkin 5115d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 512ef639e6fSAlexey Brodkin } 513ef639e6fSAlexey Brodkin 514ef639e6fSAlexey Brodkin static inline void __dc_line_op(unsigned long paddr, unsigned long sz, 515ef639e6fSAlexey Brodkin const int cacheop) 516ef639e6fSAlexey Brodkin { 5175d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 518c4ef14d2SEugeniy Paltsev __dcache_line_loop(paddr, sz, cacheop); 5195d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 520ef639e6fSAlexey Brodkin } 521ef639e6fSAlexey Brodkin #else 522ef639e6fSAlexey Brodkin #define __dc_entire_op(cacheop) 523ef639e6fSAlexey Brodkin #define __dc_line_op(paddr, sz, cacheop) 524ef639e6fSAlexey Brodkin #endif /* !CONFIG_SYS_DCACHE_OFF */ 525ef639e6fSAlexey Brodkin 526660d5f0dSAlexey Brodkin void invalidate_dcache_range(unsigned long start, unsigned long end) 527660d5f0dSAlexey Brodkin { 52841cada4dSEugeniy Paltsev if (start >= end) 52941cada4dSEugeniy Paltsev return; 53041cada4dSEugeniy Paltsev 531ef639e6fSAlexey Brodkin #ifdef CONFIG_ISA_ARCV2 532db6ce231SAlexey Brodkin if (!ioc_exists) 533db6ce231SAlexey Brodkin #endif 534db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_INV); 535db6ce231SAlexey Brodkin 536db6ce231SAlexey Brodkin #ifdef CONFIG_ISA_ARCV2 537db6ce231SAlexey Brodkin if (slc_exists && !ioc_exists) 53841cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_INV); 539660d5f0dSAlexey Brodkin #endif 540660d5f0dSAlexey Brodkin } 541660d5f0dSAlexey Brodkin 542ef639e6fSAlexey Brodkin void flush_dcache_range(unsigned long start, unsigned long end) 543660d5f0dSAlexey Brodkin { 54441cada4dSEugeniy Paltsev if (start >= end) 54541cada4dSEugeniy Paltsev return; 54641cada4dSEugeniy Paltsev 547ef639e6fSAlexey Brodkin #ifdef CONFIG_ISA_ARCV2 548db6ce231SAlexey Brodkin if (!ioc_exists) 549db6ce231SAlexey Brodkin #endif 550db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_FLUSH); 551db6ce231SAlexey Brodkin 552db6ce231SAlexey Brodkin #ifdef CONFIG_ISA_ARCV2 553db6ce231SAlexey Brodkin if (slc_exists && !ioc_exists) 55441cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_FLUSH); 555ef639e6fSAlexey Brodkin #endif 556660d5f0dSAlexey Brodkin } 557660d5f0dSAlexey Brodkin 558660d5f0dSAlexey Brodkin void flush_cache(unsigned long start, unsigned long size) 559660d5f0dSAlexey Brodkin { 560660d5f0dSAlexey Brodkin flush_dcache_range(start, start + size); 561660d5f0dSAlexey Brodkin } 5626eb15e50SAlexey Brodkin 563c27814beSEugeniy Paltsev /* 564c27814beSEugeniy Paltsev * As invalidate_dcache_all() is not used in generic U-Boot code and as we 565c27814beSEugeniy Paltsev * don't need it in arch/arc code alone (invalidate without flush) we implement 566c27814beSEugeniy Paltsev * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because 567c27814beSEugeniy Paltsev * it's much safer. See [ NOTE 1 ] for more details. 568c27814beSEugeniy Paltsev */ 569c27814beSEugeniy Paltsev void flush_n_invalidate_dcache_all(void) 570ef639e6fSAlexey Brodkin { 571c27814beSEugeniy Paltsev __dc_entire_op(OP_FLUSH_N_INV); 572db6ce231SAlexey Brodkin 573db6ce231SAlexey Brodkin #ifdef CONFIG_ISA_ARCV2 574bd91508bSAlexey Brodkin if (slc_exists) 575c27814beSEugeniy Paltsev __slc_entire_op(OP_FLUSH_N_INV); 576ef639e6fSAlexey Brodkin #endif 5776eb15e50SAlexey Brodkin } 5786eb15e50SAlexey Brodkin 579ef639e6fSAlexey Brodkin void flush_dcache_all(void) 5806eb15e50SAlexey Brodkin { 581db6ce231SAlexey Brodkin __dc_entire_op(OP_FLUSH); 582db6ce231SAlexey Brodkin 583db6ce231SAlexey Brodkin #ifdef CONFIG_ISA_ARCV2 5842a8382c6SAlexey Brodkin if (slc_exists) 585ef639e6fSAlexey Brodkin __slc_entire_op(OP_FLUSH); 586ef639e6fSAlexey Brodkin #endif 5876eb15e50SAlexey Brodkin } 588