1660d5f0dSAlexey Brodkin /* 2660d5f0dSAlexey Brodkin * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3660d5f0dSAlexey Brodkin * 4660d5f0dSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5660d5f0dSAlexey Brodkin */ 6660d5f0dSAlexey Brodkin 7660d5f0dSAlexey Brodkin #include <config.h> 8379b3280SAlexey Brodkin #include <common.h> 9ef639e6fSAlexey Brodkin #include <linux/compiler.h> 10ef639e6fSAlexey Brodkin #include <linux/kernel.h> 1197a63144SAlexey Brodkin #include <linux/log2.h> 12660d5f0dSAlexey Brodkin #include <asm/arcregs.h> 1388ae27edSEugeniy Paltsev #include <asm/arc-bcr.h> 14205e7a7bSAlexey Brodkin #include <asm/cache.h> 15660d5f0dSAlexey Brodkin 16c27814beSEugeniy Paltsev /* 17c27814beSEugeniy Paltsev * [ NOTE 1 ]: 18c27814beSEugeniy Paltsev * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable 19c27814beSEugeniy Paltsev * operation may result in unexpected behavior and data loss even if we flush 20c27814beSEugeniy Paltsev * data cache right before invalidation. That may happens if we store any context 21c27814beSEugeniy Paltsev * on stack (like we store BLINK register on stack before function call). 22c27814beSEugeniy Paltsev * BLINK register is the register where return address is automatically saved 23c27814beSEugeniy Paltsev * when we do function call with instructions like 'bl'. 24c27814beSEugeniy Paltsev * 25c27814beSEugeniy Paltsev * There is the real example: 26c27814beSEugeniy Paltsev * We may hang in the next code as we store any BLINK register on stack in 27c27814beSEugeniy Paltsev * invalidate_dcache_all() function. 28c27814beSEugeniy Paltsev * 29c27814beSEugeniy Paltsev * void flush_dcache_all() { 30c27814beSEugeniy Paltsev * __dc_entire_op(OP_FLUSH); 31c27814beSEugeniy Paltsev * // Other code // 32c27814beSEugeniy Paltsev * } 33c27814beSEugeniy Paltsev * 34c27814beSEugeniy Paltsev * void invalidate_dcache_all() { 35c27814beSEugeniy Paltsev * __dc_entire_op(OP_INV); 36c27814beSEugeniy Paltsev * // Other code // 37c27814beSEugeniy Paltsev * } 38c27814beSEugeniy Paltsev * 39c27814beSEugeniy Paltsev * void foo(void) { 40c27814beSEugeniy Paltsev * flush_dcache_all(); 41c27814beSEugeniy Paltsev * invalidate_dcache_all(); 42c27814beSEugeniy Paltsev * } 43c27814beSEugeniy Paltsev * 44c27814beSEugeniy Paltsev * Now let's see what really happens during that code execution: 45c27814beSEugeniy Paltsev * 46c27814beSEugeniy Paltsev * foo() 47c27814beSEugeniy Paltsev * |->> call flush_dcache_all 48c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 49c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 1] 50c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 51c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 52c27814beSEugeniy Paltsev * [flush L1 D$] 53c27814beSEugeniy Paltsev * return [jump to BLINK] 54c27814beSEugeniy Paltsev * <<------ 55c27814beSEugeniy Paltsev * [other flush_dcache_all code] 56c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 57c27814beSEugeniy Paltsev * return [jump to BLINK] 58c27814beSEugeniy Paltsev * <<------ 59c27814beSEugeniy Paltsev * |->> call invalidate_dcache_all 60c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 61c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 2] 62c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 63c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 64c27814beSEugeniy Paltsev * [invalidate L1 D$] ![point 3] 65c27814beSEugeniy Paltsev * // Oops!!! 66c27814beSEugeniy Paltsev * // We lose return address from invalidate_dcache_all function: 67c27814beSEugeniy Paltsev * // we save it to stack and invalidate L1 D$ after that! 68c27814beSEugeniy Paltsev * return [jump to BLINK] 69c27814beSEugeniy Paltsev * <<------ 70c27814beSEugeniy Paltsev * [other invalidate_dcache_all code] 71c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 72c27814beSEugeniy Paltsev * // we don't have this data in L1 dcache as we invalidated it in [point 3] 73c27814beSEugeniy Paltsev * // so we get it from next memory level (for example DDR memory) 74c27814beSEugeniy Paltsev * // but in the memory we have value which we save in [point 1], which 75c27814beSEugeniy Paltsev * // is return address from flush_dcache_all function (instead of 76c27814beSEugeniy Paltsev * // address from current invalidate_dcache_all function which we 77c27814beSEugeniy Paltsev * // saved in [point 2] !) 78c27814beSEugeniy Paltsev * return [jump to BLINK] 79c27814beSEugeniy Paltsev * <<------ 80c27814beSEugeniy Paltsev * // As BLINK points to invalidate_dcache_all, we call it again and 81c27814beSEugeniy Paltsev * // loop forever. 82c27814beSEugeniy Paltsev * 83c27814beSEugeniy Paltsev * Fortunately we may fix that by using flush & invalidation of D$ with a single 84c27814beSEugeniy Paltsev * one instruction (instead of flush and invalidation instructions pair) and 85c27814beSEugeniy Paltsev * enabling force function inline with '__attribute__((always_inline))' gcc 86c27814beSEugeniy Paltsev * attribute to avoid any function call (and BLINK store) between cache flush 87c27814beSEugeniy Paltsev * and disable. 88c27814beSEugeniy Paltsev */ 89c27814beSEugeniy Paltsev 90bf8974edSEugeniy Paltsev DECLARE_GLOBAL_DATA_PTR; 91bf8974edSEugeniy Paltsev 92660d5f0dSAlexey Brodkin /* Bit values in IC_CTRL */ 9319b10a42SEugeniy Paltsev #define IC_CTRL_CACHE_DISABLE BIT(0) 94660d5f0dSAlexey Brodkin 95660d5f0dSAlexey Brodkin /* Bit values in DC_CTRL */ 9619b10a42SEugeniy Paltsev #define DC_CTRL_CACHE_DISABLE BIT(0) 9719b10a42SEugeniy Paltsev #define DC_CTRL_INV_MODE_FLUSH BIT(6) 9819b10a42SEugeniy Paltsev #define DC_CTRL_FLUSH_STATUS BIT(8) 99660d5f0dSAlexey Brodkin 1005d7a24d6SEugeniy Paltsev #define OP_INV BIT(0) 1015d7a24d6SEugeniy Paltsev #define OP_FLUSH BIT(1) 1025d7a24d6SEugeniy Paltsev #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV) 103ef639e6fSAlexey Brodkin 10441cada4dSEugeniy Paltsev /* Bit val in SLC_CONTROL */ 10541cada4dSEugeniy Paltsev #define SLC_CTRL_DIS 0x001 10641cada4dSEugeniy Paltsev #define SLC_CTRL_IM 0x040 10741cada4dSEugeniy Paltsev #define SLC_CTRL_BUSY 0x100 10841cada4dSEugeniy Paltsev #define SLC_CTRL_RGN_OP_INV 0x200 10941cada4dSEugeniy Paltsev 110bf8974edSEugeniy Paltsev #define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1)) 111379b3280SAlexey Brodkin 11275790873SEugeniy Paltsev static inline bool pae_exists(void) 113ef639e6fSAlexey Brodkin { 11441cada4dSEugeniy Paltsev /* TODO: should we compare mmu version from BCR and from CONFIG? */ 11541cada4dSEugeniy Paltsev #if (CONFIG_ARC_MMU_VER >= 4) 11688ae27edSEugeniy Paltsev union bcr_mmu_4 mmu4; 117ef639e6fSAlexey Brodkin 11888ae27edSEugeniy Paltsev mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR); 119ef639e6fSAlexey Brodkin 12075790873SEugeniy Paltsev if (mmu4.fields.pae) 12175790873SEugeniy Paltsev return true; 12241cada4dSEugeniy Paltsev #endif /* (CONFIG_ARC_MMU_VER >= 4) */ 12375790873SEugeniy Paltsev 12475790873SEugeniy Paltsev return false; 12575790873SEugeniy Paltsev } 12675790873SEugeniy Paltsev 12775790873SEugeniy Paltsev static inline bool icache_exists(void) 12875790873SEugeniy Paltsev { 12975790873SEugeniy Paltsev union bcr_di_cache ibcr; 13075790873SEugeniy Paltsev 13175790873SEugeniy Paltsev ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 13275790873SEugeniy Paltsev return !!ibcr.fields.ver; 13375790873SEugeniy Paltsev } 13475790873SEugeniy Paltsev 135c75eeb0bSEugeniy Paltsev static inline bool icache_enabled(void) 136c75eeb0bSEugeniy Paltsev { 137c75eeb0bSEugeniy Paltsev if (!icache_exists()) 138c75eeb0bSEugeniy Paltsev return false; 139c75eeb0bSEugeniy Paltsev 140c75eeb0bSEugeniy Paltsev return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE); 141c75eeb0bSEugeniy Paltsev } 142c75eeb0bSEugeniy Paltsev 14375790873SEugeniy Paltsev static inline bool dcache_exists(void) 14475790873SEugeniy Paltsev { 14575790873SEugeniy Paltsev union bcr_di_cache dbcr; 14675790873SEugeniy Paltsev 14775790873SEugeniy Paltsev dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 14875790873SEugeniy Paltsev return !!dbcr.fields.ver; 14975790873SEugeniy Paltsev } 15075790873SEugeniy Paltsev 151c75eeb0bSEugeniy Paltsev static inline bool dcache_enabled(void) 152c75eeb0bSEugeniy Paltsev { 153c75eeb0bSEugeniy Paltsev if (!dcache_exists()) 154c75eeb0bSEugeniy Paltsev return false; 155c75eeb0bSEugeniy Paltsev 156c75eeb0bSEugeniy Paltsev return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE); 157c75eeb0bSEugeniy Paltsev } 158c75eeb0bSEugeniy Paltsev 15975790873SEugeniy Paltsev static inline bool slc_exists(void) 16075790873SEugeniy Paltsev { 16175790873SEugeniy Paltsev if (is_isa_arcv2()) { 16275790873SEugeniy Paltsev union bcr_generic sbcr; 16375790873SEugeniy Paltsev 16475790873SEugeniy Paltsev sbcr.word = read_aux_reg(ARC_BCR_SLC); 16575790873SEugeniy Paltsev return !!sbcr.fields.ver; 16675790873SEugeniy Paltsev } 16775790873SEugeniy Paltsev 16875790873SEugeniy Paltsev return false; 16941cada4dSEugeniy Paltsev } 17041cada4dSEugeniy Paltsev 171*95336738SEugeniy Paltsev static inline bool slc_data_bypass(void) 172*95336738SEugeniy Paltsev { 173*95336738SEugeniy Paltsev /* 174*95336738SEugeniy Paltsev * If L1 data cache is disabled SL$ is bypassed and all load/store 175*95336738SEugeniy Paltsev * requests are sent directly to main memory. 176*95336738SEugeniy Paltsev */ 177*95336738SEugeniy Paltsev return !dcache_enabled(); 178*95336738SEugeniy Paltsev } 179*95336738SEugeniy Paltsev 18048b04832SEugeniy Paltsev static inline bool ioc_exists(void) 18148b04832SEugeniy Paltsev { 18248b04832SEugeniy Paltsev if (is_isa_arcv2()) { 18348b04832SEugeniy Paltsev union bcr_clust_cfg cbcr; 18448b04832SEugeniy Paltsev 18548b04832SEugeniy Paltsev cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); 18648b04832SEugeniy Paltsev return cbcr.fields.c; 18748b04832SEugeniy Paltsev } 18848b04832SEugeniy Paltsev 18948b04832SEugeniy Paltsev return false; 19048b04832SEugeniy Paltsev } 19148b04832SEugeniy Paltsev 19248b04832SEugeniy Paltsev static inline bool ioc_enabled(void) 19348b04832SEugeniy Paltsev { 19448b04832SEugeniy Paltsev /* 19548b04832SEugeniy Paltsev * We check only CONFIG option instead of IOC HW state check as IOC 19648b04832SEugeniy Paltsev * must be disabled by default. 19748b04832SEugeniy Paltsev */ 19848b04832SEugeniy Paltsev if (is_ioc_enabled()) 19948b04832SEugeniy Paltsev return ioc_exists(); 20048b04832SEugeniy Paltsev 20148b04832SEugeniy Paltsev return false; 20248b04832SEugeniy Paltsev } 20348b04832SEugeniy Paltsev 20441cada4dSEugeniy Paltsev static void __slc_entire_op(const int op) 20541cada4dSEugeniy Paltsev { 20641cada4dSEugeniy Paltsev unsigned int ctrl; 20741cada4dSEugeniy Paltsev 20875790873SEugeniy Paltsev if (!slc_exists()) 209ea9f6f1eSEugeniy Paltsev return; 210ea9f6f1eSEugeniy Paltsev 21141cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 21241cada4dSEugeniy Paltsev 21341cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 21441cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 21541cada4dSEugeniy Paltsev else 21641cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 21741cada4dSEugeniy Paltsev 21841cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 21941cada4dSEugeniy Paltsev 22041cada4dSEugeniy Paltsev if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 22141cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); 22241cada4dSEugeniy Paltsev else 22341cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); 22441cada4dSEugeniy Paltsev 22541cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 22641cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 22741cada4dSEugeniy Paltsev 22841cada4dSEugeniy Paltsev /* Important to wait for flush to complete */ 22941cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 23041cada4dSEugeniy Paltsev } 23141cada4dSEugeniy Paltsev 23241cada4dSEugeniy Paltsev static void slc_upper_region_init(void) 23341cada4dSEugeniy Paltsev { 23441cada4dSEugeniy Paltsev /* 235246ba284SEugeniy Paltsev * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist 236246ba284SEugeniy Paltsev * only if PAE exists in current HW. So we had to check pae_exist 237246ba284SEugeniy Paltsev * before using them. 238246ba284SEugeniy Paltsev */ 239246ba284SEugeniy Paltsev if (!pae_exists()) 240246ba284SEugeniy Paltsev return; 241246ba284SEugeniy Paltsev 242246ba284SEugeniy Paltsev /* 24341cada4dSEugeniy Paltsev * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 24441cada4dSEugeniy Paltsev * as we don't use PAE40. 24541cada4dSEugeniy Paltsev */ 24641cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); 24741cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); 24841cada4dSEugeniy Paltsev } 24941cada4dSEugeniy Paltsev 25041cada4dSEugeniy Paltsev static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) 25141cada4dSEugeniy Paltsev { 25205c6a26aSEugeniy Paltsev #ifdef CONFIG_ISA_ARCV2 25305c6a26aSEugeniy Paltsev 25441cada4dSEugeniy Paltsev unsigned int ctrl; 25541cada4dSEugeniy Paltsev unsigned long end; 25641cada4dSEugeniy Paltsev 25775790873SEugeniy Paltsev if (!slc_exists()) 258ea9f6f1eSEugeniy Paltsev return; 259ea9f6f1eSEugeniy Paltsev 26041cada4dSEugeniy Paltsev /* 26141cada4dSEugeniy Paltsev * The Region Flush operation is specified by CTRL.RGN_OP[11..9] 26241cada4dSEugeniy Paltsev * - b'000 (default) is Flush, 26341cada4dSEugeniy Paltsev * - b'001 is Invalidate if CTRL.IM == 0 26441cada4dSEugeniy Paltsev * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 26541cada4dSEugeniy Paltsev */ 26641cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 26741cada4dSEugeniy Paltsev 26841cada4dSEugeniy Paltsev /* Don't rely on default value of IM bit */ 26941cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 27041cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 27141cada4dSEugeniy Paltsev else 27241cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 27341cada4dSEugeniy Paltsev 27441cada4dSEugeniy Paltsev if (op & OP_INV) 27541cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ 27641cada4dSEugeniy Paltsev else 27741cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_RGN_OP_INV; 27841cada4dSEugeniy Paltsev 27941cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 28041cada4dSEugeniy Paltsev 28141cada4dSEugeniy Paltsev /* 28241cada4dSEugeniy Paltsev * Lower bits are ignored, no need to clip 28341cada4dSEugeniy Paltsev * END needs to be setup before START (latter triggers the operation) 28441cada4dSEugeniy Paltsev * END can't be same as START, so add (l2_line_sz - 1) to sz 28541cada4dSEugeniy Paltsev */ 286bf8974edSEugeniy Paltsev end = paddr + sz + gd->arch.slc_line_sz - 1; 28741cada4dSEugeniy Paltsev 28841cada4dSEugeniy Paltsev /* 28941cada4dSEugeniy Paltsev * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) 29041cada4dSEugeniy Paltsev * are always == 0 as we don't use PAE40, so we only setup lower ones 29141cada4dSEugeniy Paltsev * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START) 29241cada4dSEugeniy Paltsev */ 29341cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END, end); 29441cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); 29541cada4dSEugeniy Paltsev 29641cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 29741cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 29841cada4dSEugeniy Paltsev 29941cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 30005c6a26aSEugeniy Paltsev 30105c6a26aSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 30241cada4dSEugeniy Paltsev } 303a6f557c4SEugeniy Paltsev 304a6f557c4SEugeniy Paltsev static void arc_ioc_setup(void) 305a6f557c4SEugeniy Paltsev { 306a6f557c4SEugeniy Paltsev /* IOC Aperture start is equal to DDR start */ 307a6f557c4SEugeniy Paltsev unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; 308a6f557c4SEugeniy Paltsev /* IOC Aperture size is equal to DDR size */ 309a6f557c4SEugeniy Paltsev long ap_size = CONFIG_SYS_SDRAM_SIZE; 310a6f557c4SEugeniy Paltsev 311a6f557c4SEugeniy Paltsev flush_n_invalidate_dcache_all(); 312a6f557c4SEugeniy Paltsev 313a6f557c4SEugeniy Paltsev if (!is_power_of_2(ap_size) || ap_size < 4096) 314a6f557c4SEugeniy Paltsev panic("IOC Aperture size must be power of 2 and bigger 4Kib"); 315a6f557c4SEugeniy Paltsev 316a6f557c4SEugeniy Paltsev /* 317a6f557c4SEugeniy Paltsev * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, 318a6f557c4SEugeniy Paltsev * so setting 0x11 implies 512M, 0x12 implies 1G... 319a6f557c4SEugeniy Paltsev */ 320a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 321a6f557c4SEugeniy Paltsev order_base_2(ap_size / 1024) - 2); 322a6f557c4SEugeniy Paltsev 323a6f557c4SEugeniy Paltsev /* IOC Aperture start must be aligned to the size of the aperture */ 324a6f557c4SEugeniy Paltsev if (ap_base % ap_size != 0) 325a6f557c4SEugeniy Paltsev panic("IOC Aperture start must be aligned to the size of the aperture"); 326a6f557c4SEugeniy Paltsev 327a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); 328a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); 329a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); 330a6f557c4SEugeniy Paltsev } 331ef639e6fSAlexey Brodkin 332379b3280SAlexey Brodkin static void read_decode_cache_bcr_arcv2(void) 333ef639e6fSAlexey Brodkin { 33405c6a26aSEugeniy Paltsev #ifdef CONFIG_ISA_ARCV2 33505c6a26aSEugeniy Paltsev 33688ae27edSEugeniy Paltsev union bcr_slc_cfg slc_cfg; 337379b3280SAlexey Brodkin 33875790873SEugeniy Paltsev if (slc_exists()) { 339379b3280SAlexey Brodkin slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); 340bf8974edSEugeniy Paltsev gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; 341379b3280SAlexey Brodkin } 342db6ce231SAlexey Brodkin 34305c6a26aSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 344379b3280SAlexey Brodkin } 345379b3280SAlexey Brodkin 346379b3280SAlexey Brodkin void read_decode_cache_bcr(void) 347379b3280SAlexey Brodkin { 348379b3280SAlexey Brodkin int dc_line_sz = 0, ic_line_sz = 0; 34988ae27edSEugeniy Paltsev union bcr_di_cache ibcr, dbcr; 350379b3280SAlexey Brodkin 351379b3280SAlexey Brodkin ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 352379b3280SAlexey Brodkin if (ibcr.fields.ver) { 353bf8974edSEugeniy Paltsev gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; 354379b3280SAlexey Brodkin if (!ic_line_sz) 355379b3280SAlexey Brodkin panic("Instruction exists but line length is 0\n"); 356ef639e6fSAlexey Brodkin } 357ef639e6fSAlexey Brodkin 358379b3280SAlexey Brodkin dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 359379b3280SAlexey Brodkin if (dbcr.fields.ver) { 360bf8974edSEugeniy Paltsev gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; 361379b3280SAlexey Brodkin if (!dc_line_sz) 362379b3280SAlexey Brodkin panic("Data cache exists but line length is 0\n"); 363379b3280SAlexey Brodkin } 364379b3280SAlexey Brodkin 365379b3280SAlexey Brodkin if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz)) 366379b3280SAlexey Brodkin panic("Instruction and data cache line lengths differ\n"); 367ef639e6fSAlexey Brodkin } 368ef639e6fSAlexey Brodkin 369ef639e6fSAlexey Brodkin void cache_init(void) 370ef639e6fSAlexey Brodkin { 371379b3280SAlexey Brodkin read_decode_cache_bcr(); 372379b3280SAlexey Brodkin 37305c6a26aSEugeniy Paltsev if (is_isa_arcv2()) 374379b3280SAlexey Brodkin read_decode_cache_bcr_arcv2(); 375db6ce231SAlexey Brodkin 37648b04832SEugeniy Paltsev if (is_isa_arcv2() && ioc_enabled()) 377a6f557c4SEugeniy Paltsev arc_ioc_setup(); 37841cada4dSEugeniy Paltsev 379246ba284SEugeniy Paltsev if (is_isa_arcv2() && slc_exists()) 38041cada4dSEugeniy Paltsev slc_upper_region_init(); 381ef639e6fSAlexey Brodkin } 382ef639e6fSAlexey Brodkin 383660d5f0dSAlexey Brodkin int icache_status(void) 384660d5f0dSAlexey Brodkin { 385c75eeb0bSEugeniy Paltsev return icache_enabled(); 386660d5f0dSAlexey Brodkin } 387660d5f0dSAlexey Brodkin 388660d5f0dSAlexey Brodkin void icache_enable(void) 389660d5f0dSAlexey Brodkin { 39075790873SEugeniy Paltsev if (icache_exists()) 391660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & 392660d5f0dSAlexey Brodkin ~IC_CTRL_CACHE_DISABLE); 393660d5f0dSAlexey Brodkin } 394660d5f0dSAlexey Brodkin 395660d5f0dSAlexey Brodkin void icache_disable(void) 396660d5f0dSAlexey Brodkin { 39775790873SEugeniy Paltsev if (icache_exists()) 398660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | 399660d5f0dSAlexey Brodkin IC_CTRL_CACHE_DISABLE); 400660d5f0dSAlexey Brodkin } 401660d5f0dSAlexey Brodkin 40216aeee81SEugeniy Paltsev /* IC supports only invalidation */ 40316aeee81SEugeniy Paltsev static inline void __ic_entire_invalidate(void) 404660d5f0dSAlexey Brodkin { 405c75eeb0bSEugeniy Paltsev if (!icache_enabled()) 40616aeee81SEugeniy Paltsev return; 40716aeee81SEugeniy Paltsev 408660d5f0dSAlexey Brodkin /* Any write to IC_IVIC register triggers invalidation of entire I$ */ 409660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_IVIC, 1); 410f2a22678SAlexey Brodkin /* 411f2a22678SAlexey Brodkin * As per ARC HS databook (see chapter 5.3.3.2) 412f2a22678SAlexey Brodkin * it is required to add 3 NOPs after each write to IC_IVIC. 413f2a22678SAlexey Brodkin */ 414f2a22678SAlexey Brodkin __builtin_arc_nop(); 415f2a22678SAlexey Brodkin __builtin_arc_nop(); 416f2a22678SAlexey Brodkin __builtin_arc_nop(); 417ef639e6fSAlexey Brodkin read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ 418660d5f0dSAlexey Brodkin } 41941cada4dSEugeniy Paltsev 42016aeee81SEugeniy Paltsev void invalidate_icache_all(void) 42116aeee81SEugeniy Paltsev { 42216aeee81SEugeniy Paltsev __ic_entire_invalidate(); 42316aeee81SEugeniy Paltsev 424*95336738SEugeniy Paltsev /* 425*95336738SEugeniy Paltsev * If SL$ is bypassed for data it is used only for instructions, 426*95336738SEugeniy Paltsev * so we need to invalidate it too. 427*95336738SEugeniy Paltsev * TODO: HS 3.0 supports SLC disable so we need to check slc 428*95336738SEugeniy Paltsev * enable/disable status here. 429*95336738SEugeniy Paltsev */ 430*95336738SEugeniy Paltsev if (is_isa_arcv2() && slc_data_bypass()) 43141cada4dSEugeniy Paltsev __slc_entire_op(OP_INV); 43241cada4dSEugeniy Paltsev } 433660d5f0dSAlexey Brodkin 434660d5f0dSAlexey Brodkin int dcache_status(void) 435660d5f0dSAlexey Brodkin { 436c75eeb0bSEugeniy Paltsev return dcache_enabled(); 437660d5f0dSAlexey Brodkin } 438660d5f0dSAlexey Brodkin 439660d5f0dSAlexey Brodkin void dcache_enable(void) 440660d5f0dSAlexey Brodkin { 44175790873SEugeniy Paltsev if (!dcache_exists()) 442660d5f0dSAlexey Brodkin return; 443660d5f0dSAlexey Brodkin 444660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & 445660d5f0dSAlexey Brodkin ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); 446660d5f0dSAlexey Brodkin } 447660d5f0dSAlexey Brodkin 448660d5f0dSAlexey Brodkin void dcache_disable(void) 449660d5f0dSAlexey Brodkin { 45075790873SEugeniy Paltsev if (!dcache_exists()) 451660d5f0dSAlexey Brodkin return; 452660d5f0dSAlexey Brodkin 453660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | 454660d5f0dSAlexey Brodkin DC_CTRL_CACHE_DISABLE); 455660d5f0dSAlexey Brodkin } 456660d5f0dSAlexey Brodkin 457c4ef14d2SEugeniy Paltsev /* Common Helper for Line Operations on D-cache */ 458c4ef14d2SEugeniy Paltsev static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, 459ef639e6fSAlexey Brodkin const int cacheop) 460660d5f0dSAlexey Brodkin { 461ef639e6fSAlexey Brodkin unsigned int aux_cmd; 462ef639e6fSAlexey Brodkin int num_lines; 463660d5f0dSAlexey Brodkin 464ef639e6fSAlexey Brodkin /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 465ef639e6fSAlexey Brodkin aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; 466660d5f0dSAlexey Brodkin 467ef639e6fSAlexey Brodkin sz += paddr & ~CACHE_LINE_MASK; 468ef639e6fSAlexey Brodkin paddr &= CACHE_LINE_MASK; 469ef639e6fSAlexey Brodkin 470bf8974edSEugeniy Paltsev num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz); 471ef639e6fSAlexey Brodkin 472ef639e6fSAlexey Brodkin while (num_lines-- > 0) { 473ef639e6fSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 474c4ef14d2SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_PTAG, paddr); 475ef639e6fSAlexey Brodkin #endif 476ef639e6fSAlexey Brodkin write_aux_reg(aux_cmd, paddr); 477bf8974edSEugeniy Paltsev paddr += gd->arch.l1_line_sz; 478ef639e6fSAlexey Brodkin } 479ef639e6fSAlexey Brodkin } 480ef639e6fSAlexey Brodkin 4815d7a24d6SEugeniy Paltsev static void __before_dc_op(const int op) 482ef639e6fSAlexey Brodkin { 4835d7a24d6SEugeniy Paltsev unsigned int ctrl; 484ef639e6fSAlexey Brodkin 4855d7a24d6SEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_DC_CTRL); 4865d7a24d6SEugeniy Paltsev 4875d7a24d6SEugeniy Paltsev /* IM bit implies flush-n-inv, instead of vanilla inv */ 4885d7a24d6SEugeniy Paltsev if (op == OP_INV) 4895d7a24d6SEugeniy Paltsev ctrl &= ~DC_CTRL_INV_MODE_FLUSH; 4905d7a24d6SEugeniy Paltsev else 4915d7a24d6SEugeniy Paltsev ctrl |= DC_CTRL_INV_MODE_FLUSH; 4925d7a24d6SEugeniy Paltsev 4935d7a24d6SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_CTRL, ctrl); 494ef639e6fSAlexey Brodkin } 495ef639e6fSAlexey Brodkin 4965d7a24d6SEugeniy Paltsev static void __after_dc_op(const int op) 497ef639e6fSAlexey Brodkin { 498ef639e6fSAlexey Brodkin if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ 49919b10a42SEugeniy Paltsev while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); 500ef639e6fSAlexey Brodkin } 501ef639e6fSAlexey Brodkin 502ef639e6fSAlexey Brodkin static inline void __dc_entire_op(const int cacheop) 503ef639e6fSAlexey Brodkin { 504ef639e6fSAlexey Brodkin int aux; 5055d7a24d6SEugeniy Paltsev 506c75eeb0bSEugeniy Paltsev if (!dcache_enabled()) 507c877a891SEugeniy Paltsev return; 508c877a891SEugeniy Paltsev 5095d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 510ef639e6fSAlexey Brodkin 511ef639e6fSAlexey Brodkin if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 512ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_IVDC; 513ef639e6fSAlexey Brodkin else 514ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_FLSH; 515ef639e6fSAlexey Brodkin 516ef639e6fSAlexey Brodkin write_aux_reg(aux, 0x1); 517ef639e6fSAlexey Brodkin 5185d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 519ef639e6fSAlexey Brodkin } 520ef639e6fSAlexey Brodkin 521ef639e6fSAlexey Brodkin static inline void __dc_line_op(unsigned long paddr, unsigned long sz, 522ef639e6fSAlexey Brodkin const int cacheop) 523ef639e6fSAlexey Brodkin { 524c75eeb0bSEugeniy Paltsev if (!dcache_enabled()) 525c877a891SEugeniy Paltsev return; 526c877a891SEugeniy Paltsev 5275d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 528c4ef14d2SEugeniy Paltsev __dcache_line_loop(paddr, sz, cacheop); 5295d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 530ef639e6fSAlexey Brodkin } 531ef639e6fSAlexey Brodkin 532660d5f0dSAlexey Brodkin void invalidate_dcache_range(unsigned long start, unsigned long end) 533660d5f0dSAlexey Brodkin { 53441cada4dSEugeniy Paltsev if (start >= end) 53541cada4dSEugeniy Paltsev return; 53641cada4dSEugeniy Paltsev 53705c6a26aSEugeniy Paltsev /* 53805c6a26aSEugeniy Paltsev * ARCv1 -> call __dc_line_op 539*95336738SEugeniy Paltsev * ARCv2 && L1 D$ disabled -> nothing 540*95336738SEugeniy Paltsev * ARCv2 && L1 D$ enabled && IOC enabled -> nothing 541*95336738SEugeniy Paltsev * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op 54205c6a26aSEugeniy Paltsev */ 54348b04832SEugeniy Paltsev if (!is_isa_arcv2() || !ioc_enabled()) 544db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_INV); 545db6ce231SAlexey Brodkin 546*95336738SEugeniy Paltsev if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass()) 54741cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_INV); 548660d5f0dSAlexey Brodkin } 549660d5f0dSAlexey Brodkin 550ef639e6fSAlexey Brodkin void flush_dcache_range(unsigned long start, unsigned long end) 551660d5f0dSAlexey Brodkin { 55241cada4dSEugeniy Paltsev if (start >= end) 55341cada4dSEugeniy Paltsev return; 55441cada4dSEugeniy Paltsev 55505c6a26aSEugeniy Paltsev /* 55605c6a26aSEugeniy Paltsev * ARCv1 -> call __dc_line_op 557*95336738SEugeniy Paltsev * ARCv2 && L1 D$ disabled -> nothing 558*95336738SEugeniy Paltsev * ARCv2 && L1 D$ enabled && IOC enabled -> nothing 559*95336738SEugeniy Paltsev * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op 56005c6a26aSEugeniy Paltsev */ 56148b04832SEugeniy Paltsev if (!is_isa_arcv2() || !ioc_enabled()) 562db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_FLUSH); 563db6ce231SAlexey Brodkin 564*95336738SEugeniy Paltsev if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass()) 56541cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_FLUSH); 566660d5f0dSAlexey Brodkin } 567660d5f0dSAlexey Brodkin 568660d5f0dSAlexey Brodkin void flush_cache(unsigned long start, unsigned long size) 569660d5f0dSAlexey Brodkin { 570660d5f0dSAlexey Brodkin flush_dcache_range(start, start + size); 571660d5f0dSAlexey Brodkin } 5726eb15e50SAlexey Brodkin 573c27814beSEugeniy Paltsev /* 574c27814beSEugeniy Paltsev * As invalidate_dcache_all() is not used in generic U-Boot code and as we 575c27814beSEugeniy Paltsev * don't need it in arch/arc code alone (invalidate without flush) we implement 576c27814beSEugeniy Paltsev * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because 577c27814beSEugeniy Paltsev * it's much safer. See [ NOTE 1 ] for more details. 578c27814beSEugeniy Paltsev */ 579c27814beSEugeniy Paltsev void flush_n_invalidate_dcache_all(void) 580ef639e6fSAlexey Brodkin { 581c27814beSEugeniy Paltsev __dc_entire_op(OP_FLUSH_N_INV); 582db6ce231SAlexey Brodkin 583*95336738SEugeniy Paltsev if (is_isa_arcv2() && !slc_data_bypass()) 584c27814beSEugeniy Paltsev __slc_entire_op(OP_FLUSH_N_INV); 5856eb15e50SAlexey Brodkin } 5866eb15e50SAlexey Brodkin 587ef639e6fSAlexey Brodkin void flush_dcache_all(void) 5886eb15e50SAlexey Brodkin { 589db6ce231SAlexey Brodkin __dc_entire_op(OP_FLUSH); 590db6ce231SAlexey Brodkin 591*95336738SEugeniy Paltsev if (is_isa_arcv2() && !slc_data_bypass()) 592ef639e6fSAlexey Brodkin __slc_entire_op(OP_FLUSH); 5936eb15e50SAlexey Brodkin } 594