1660d5f0dSAlexey Brodkin /* 2660d5f0dSAlexey Brodkin * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3660d5f0dSAlexey Brodkin * 4660d5f0dSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5660d5f0dSAlexey Brodkin */ 6660d5f0dSAlexey Brodkin 7660d5f0dSAlexey Brodkin #include <config.h> 8379b3280SAlexey Brodkin #include <common.h> 9ef639e6fSAlexey Brodkin #include <linux/compiler.h> 10ef639e6fSAlexey Brodkin #include <linux/kernel.h> 1197a63144SAlexey Brodkin #include <linux/log2.h> 12660d5f0dSAlexey Brodkin #include <asm/arcregs.h> 1388ae27edSEugeniy Paltsev #include <asm/arc-bcr.h> 14205e7a7bSAlexey Brodkin #include <asm/cache.h> 15660d5f0dSAlexey Brodkin 16c27814beSEugeniy Paltsev /* 17c27814beSEugeniy Paltsev * [ NOTE 1 ]: 18c27814beSEugeniy Paltsev * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable 19c27814beSEugeniy Paltsev * operation may result in unexpected behavior and data loss even if we flush 20c27814beSEugeniy Paltsev * data cache right before invalidation. That may happens if we store any context 21c27814beSEugeniy Paltsev * on stack (like we store BLINK register on stack before function call). 22c27814beSEugeniy Paltsev * BLINK register is the register where return address is automatically saved 23c27814beSEugeniy Paltsev * when we do function call with instructions like 'bl'. 24c27814beSEugeniy Paltsev * 25c27814beSEugeniy Paltsev * There is the real example: 26c27814beSEugeniy Paltsev * We may hang in the next code as we store any BLINK register on stack in 27c27814beSEugeniy Paltsev * invalidate_dcache_all() function. 28c27814beSEugeniy Paltsev * 29c27814beSEugeniy Paltsev * void flush_dcache_all() { 30c27814beSEugeniy Paltsev * __dc_entire_op(OP_FLUSH); 31c27814beSEugeniy Paltsev * // Other code // 32c27814beSEugeniy Paltsev * } 33c27814beSEugeniy Paltsev * 34c27814beSEugeniy Paltsev * void invalidate_dcache_all() { 35c27814beSEugeniy Paltsev * __dc_entire_op(OP_INV); 36c27814beSEugeniy Paltsev * // Other code // 37c27814beSEugeniy Paltsev * } 38c27814beSEugeniy Paltsev * 39c27814beSEugeniy Paltsev * void foo(void) { 40c27814beSEugeniy Paltsev * flush_dcache_all(); 41c27814beSEugeniy Paltsev * invalidate_dcache_all(); 42c27814beSEugeniy Paltsev * } 43c27814beSEugeniy Paltsev * 44c27814beSEugeniy Paltsev * Now let's see what really happens during that code execution: 45c27814beSEugeniy Paltsev * 46c27814beSEugeniy Paltsev * foo() 47c27814beSEugeniy Paltsev * |->> call flush_dcache_all 48c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 49c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 1] 50c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 51c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 52c27814beSEugeniy Paltsev * [flush L1 D$] 53c27814beSEugeniy Paltsev * return [jump to BLINK] 54c27814beSEugeniy Paltsev * <<------ 55c27814beSEugeniy Paltsev * [other flush_dcache_all code] 56c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 57c27814beSEugeniy Paltsev * return [jump to BLINK] 58c27814beSEugeniy Paltsev * <<------ 59c27814beSEugeniy Paltsev * |->> call invalidate_dcache_all 60c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 61c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 2] 62c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 63c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 64c27814beSEugeniy Paltsev * [invalidate L1 D$] ![point 3] 65c27814beSEugeniy Paltsev * // Oops!!! 66c27814beSEugeniy Paltsev * // We lose return address from invalidate_dcache_all function: 67c27814beSEugeniy Paltsev * // we save it to stack and invalidate L1 D$ after that! 68c27814beSEugeniy Paltsev * return [jump to BLINK] 69c27814beSEugeniy Paltsev * <<------ 70c27814beSEugeniy Paltsev * [other invalidate_dcache_all code] 71c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 72c27814beSEugeniy Paltsev * // we don't have this data in L1 dcache as we invalidated it in [point 3] 73c27814beSEugeniy Paltsev * // so we get it from next memory level (for example DDR memory) 74c27814beSEugeniy Paltsev * // but in the memory we have value which we save in [point 1], which 75c27814beSEugeniy Paltsev * // is return address from flush_dcache_all function (instead of 76c27814beSEugeniy Paltsev * // address from current invalidate_dcache_all function which we 77c27814beSEugeniy Paltsev * // saved in [point 2] !) 78c27814beSEugeniy Paltsev * return [jump to BLINK] 79c27814beSEugeniy Paltsev * <<------ 80c27814beSEugeniy Paltsev * // As BLINK points to invalidate_dcache_all, we call it again and 81c27814beSEugeniy Paltsev * // loop forever. 82c27814beSEugeniy Paltsev * 83c27814beSEugeniy Paltsev * Fortunately we may fix that by using flush & invalidation of D$ with a single 84c27814beSEugeniy Paltsev * one instruction (instead of flush and invalidation instructions pair) and 85c27814beSEugeniy Paltsev * enabling force function inline with '__attribute__((always_inline))' gcc 86c27814beSEugeniy Paltsev * attribute to avoid any function call (and BLINK store) between cache flush 87c27814beSEugeniy Paltsev * and disable. 88c27814beSEugeniy Paltsev */ 89c27814beSEugeniy Paltsev 90bf8974edSEugeniy Paltsev DECLARE_GLOBAL_DATA_PTR; 91bf8974edSEugeniy Paltsev 92660d5f0dSAlexey Brodkin /* Bit values in IC_CTRL */ 9319b10a42SEugeniy Paltsev #define IC_CTRL_CACHE_DISABLE BIT(0) 94660d5f0dSAlexey Brodkin 95660d5f0dSAlexey Brodkin /* Bit values in DC_CTRL */ 9619b10a42SEugeniy Paltsev #define DC_CTRL_CACHE_DISABLE BIT(0) 9719b10a42SEugeniy Paltsev #define DC_CTRL_INV_MODE_FLUSH BIT(6) 9819b10a42SEugeniy Paltsev #define DC_CTRL_FLUSH_STATUS BIT(8) 99660d5f0dSAlexey Brodkin 1005d7a24d6SEugeniy Paltsev #define OP_INV BIT(0) 1015d7a24d6SEugeniy Paltsev #define OP_FLUSH BIT(1) 1025d7a24d6SEugeniy Paltsev #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV) 103ef639e6fSAlexey Brodkin 10441cada4dSEugeniy Paltsev /* Bit val in SLC_CONTROL */ 10541cada4dSEugeniy Paltsev #define SLC_CTRL_DIS 0x001 10641cada4dSEugeniy Paltsev #define SLC_CTRL_IM 0x040 10741cada4dSEugeniy Paltsev #define SLC_CTRL_BUSY 0x100 10841cada4dSEugeniy Paltsev #define SLC_CTRL_RGN_OP_INV 0x200 10941cada4dSEugeniy Paltsev 110bf8974edSEugeniy Paltsev #define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1)) 111379b3280SAlexey Brodkin 11275790873SEugeniy Paltsev static inline bool pae_exists(void) 113ef639e6fSAlexey Brodkin { 11441cada4dSEugeniy Paltsev /* TODO: should we compare mmu version from BCR and from CONFIG? */ 11541cada4dSEugeniy Paltsev #if (CONFIG_ARC_MMU_VER >= 4) 11688ae27edSEugeniy Paltsev union bcr_mmu_4 mmu4; 117ef639e6fSAlexey Brodkin 11888ae27edSEugeniy Paltsev mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR); 119ef639e6fSAlexey Brodkin 12075790873SEugeniy Paltsev if (mmu4.fields.pae) 12175790873SEugeniy Paltsev return true; 12241cada4dSEugeniy Paltsev #endif /* (CONFIG_ARC_MMU_VER >= 4) */ 12375790873SEugeniy Paltsev 12475790873SEugeniy Paltsev return false; 12575790873SEugeniy Paltsev } 12675790873SEugeniy Paltsev 12775790873SEugeniy Paltsev static inline bool icache_exists(void) 12875790873SEugeniy Paltsev { 12975790873SEugeniy Paltsev union bcr_di_cache ibcr; 13075790873SEugeniy Paltsev 13175790873SEugeniy Paltsev ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 13275790873SEugeniy Paltsev return !!ibcr.fields.ver; 13375790873SEugeniy Paltsev } 13475790873SEugeniy Paltsev 13575790873SEugeniy Paltsev static inline bool dcache_exists(void) 13675790873SEugeniy Paltsev { 13775790873SEugeniy Paltsev union bcr_di_cache dbcr; 13875790873SEugeniy Paltsev 13975790873SEugeniy Paltsev dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 14075790873SEugeniy Paltsev return !!dbcr.fields.ver; 14175790873SEugeniy Paltsev } 14275790873SEugeniy Paltsev 14375790873SEugeniy Paltsev static inline bool slc_exists(void) 14475790873SEugeniy Paltsev { 14575790873SEugeniy Paltsev if (is_isa_arcv2()) { 14675790873SEugeniy Paltsev union bcr_generic sbcr; 14775790873SEugeniy Paltsev 14875790873SEugeniy Paltsev sbcr.word = read_aux_reg(ARC_BCR_SLC); 14975790873SEugeniy Paltsev return !!sbcr.fields.ver; 15075790873SEugeniy Paltsev } 15175790873SEugeniy Paltsev 15275790873SEugeniy Paltsev return false; 15341cada4dSEugeniy Paltsev } 15441cada4dSEugeniy Paltsev 155*48b04832SEugeniy Paltsev static inline bool ioc_exists(void) 156*48b04832SEugeniy Paltsev { 157*48b04832SEugeniy Paltsev if (is_isa_arcv2()) { 158*48b04832SEugeniy Paltsev union bcr_clust_cfg cbcr; 159*48b04832SEugeniy Paltsev 160*48b04832SEugeniy Paltsev cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); 161*48b04832SEugeniy Paltsev return cbcr.fields.c; 162*48b04832SEugeniy Paltsev } 163*48b04832SEugeniy Paltsev 164*48b04832SEugeniy Paltsev return false; 165*48b04832SEugeniy Paltsev } 166*48b04832SEugeniy Paltsev 167*48b04832SEugeniy Paltsev static inline bool ioc_enabled(void) 168*48b04832SEugeniy Paltsev { 169*48b04832SEugeniy Paltsev /* 170*48b04832SEugeniy Paltsev * We check only CONFIG option instead of IOC HW state check as IOC 171*48b04832SEugeniy Paltsev * must be disabled by default. 172*48b04832SEugeniy Paltsev */ 173*48b04832SEugeniy Paltsev if (is_ioc_enabled()) 174*48b04832SEugeniy Paltsev return ioc_exists(); 175*48b04832SEugeniy Paltsev 176*48b04832SEugeniy Paltsev return false; 177*48b04832SEugeniy Paltsev } 178*48b04832SEugeniy Paltsev 17941cada4dSEugeniy Paltsev static void __slc_entire_op(const int op) 18041cada4dSEugeniy Paltsev { 18141cada4dSEugeniy Paltsev unsigned int ctrl; 18241cada4dSEugeniy Paltsev 18375790873SEugeniy Paltsev if (!slc_exists()) 184ea9f6f1eSEugeniy Paltsev return; 185ea9f6f1eSEugeniy Paltsev 18641cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 18741cada4dSEugeniy Paltsev 18841cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 18941cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 19041cada4dSEugeniy Paltsev else 19141cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 19241cada4dSEugeniy Paltsev 19341cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 19441cada4dSEugeniy Paltsev 19541cada4dSEugeniy Paltsev if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 19641cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); 19741cada4dSEugeniy Paltsev else 19841cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); 19941cada4dSEugeniy Paltsev 20041cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 20141cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 20241cada4dSEugeniy Paltsev 20341cada4dSEugeniy Paltsev /* Important to wait for flush to complete */ 20441cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 20541cada4dSEugeniy Paltsev } 20641cada4dSEugeniy Paltsev 20741cada4dSEugeniy Paltsev static void slc_upper_region_init(void) 20841cada4dSEugeniy Paltsev { 20941cada4dSEugeniy Paltsev /* 210246ba284SEugeniy Paltsev * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist 211246ba284SEugeniy Paltsev * only if PAE exists in current HW. So we had to check pae_exist 212246ba284SEugeniy Paltsev * before using them. 213246ba284SEugeniy Paltsev */ 214246ba284SEugeniy Paltsev if (!pae_exists()) 215246ba284SEugeniy Paltsev return; 216246ba284SEugeniy Paltsev 217246ba284SEugeniy Paltsev /* 21841cada4dSEugeniy Paltsev * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 21941cada4dSEugeniy Paltsev * as we don't use PAE40. 22041cada4dSEugeniy Paltsev */ 22141cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); 22241cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); 22341cada4dSEugeniy Paltsev } 22441cada4dSEugeniy Paltsev 22541cada4dSEugeniy Paltsev static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) 22641cada4dSEugeniy Paltsev { 22705c6a26aSEugeniy Paltsev #ifdef CONFIG_ISA_ARCV2 22805c6a26aSEugeniy Paltsev 22941cada4dSEugeniy Paltsev unsigned int ctrl; 23041cada4dSEugeniy Paltsev unsigned long end; 23141cada4dSEugeniy Paltsev 23275790873SEugeniy Paltsev if (!slc_exists()) 233ea9f6f1eSEugeniy Paltsev return; 234ea9f6f1eSEugeniy Paltsev 23541cada4dSEugeniy Paltsev /* 23641cada4dSEugeniy Paltsev * The Region Flush operation is specified by CTRL.RGN_OP[11..9] 23741cada4dSEugeniy Paltsev * - b'000 (default) is Flush, 23841cada4dSEugeniy Paltsev * - b'001 is Invalidate if CTRL.IM == 0 23941cada4dSEugeniy Paltsev * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 24041cada4dSEugeniy Paltsev */ 24141cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 24241cada4dSEugeniy Paltsev 24341cada4dSEugeniy Paltsev /* Don't rely on default value of IM bit */ 24441cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 24541cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 24641cada4dSEugeniy Paltsev else 24741cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 24841cada4dSEugeniy Paltsev 24941cada4dSEugeniy Paltsev if (op & OP_INV) 25041cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ 25141cada4dSEugeniy Paltsev else 25241cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_RGN_OP_INV; 25341cada4dSEugeniy Paltsev 25441cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 25541cada4dSEugeniy Paltsev 25641cada4dSEugeniy Paltsev /* 25741cada4dSEugeniy Paltsev * Lower bits are ignored, no need to clip 25841cada4dSEugeniy Paltsev * END needs to be setup before START (latter triggers the operation) 25941cada4dSEugeniy Paltsev * END can't be same as START, so add (l2_line_sz - 1) to sz 26041cada4dSEugeniy Paltsev */ 261bf8974edSEugeniy Paltsev end = paddr + sz + gd->arch.slc_line_sz - 1; 26241cada4dSEugeniy Paltsev 26341cada4dSEugeniy Paltsev /* 26441cada4dSEugeniy Paltsev * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) 26541cada4dSEugeniy Paltsev * are always == 0 as we don't use PAE40, so we only setup lower ones 26641cada4dSEugeniy Paltsev * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START) 26741cada4dSEugeniy Paltsev */ 26841cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END, end); 26941cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); 27041cada4dSEugeniy Paltsev 27141cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 27241cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 27341cada4dSEugeniy Paltsev 27441cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 27505c6a26aSEugeniy Paltsev 27605c6a26aSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 27741cada4dSEugeniy Paltsev } 278a6f557c4SEugeniy Paltsev 279a6f557c4SEugeniy Paltsev static void arc_ioc_setup(void) 280a6f557c4SEugeniy Paltsev { 281a6f557c4SEugeniy Paltsev /* IOC Aperture start is equal to DDR start */ 282a6f557c4SEugeniy Paltsev unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; 283a6f557c4SEugeniy Paltsev /* IOC Aperture size is equal to DDR size */ 284a6f557c4SEugeniy Paltsev long ap_size = CONFIG_SYS_SDRAM_SIZE; 285a6f557c4SEugeniy Paltsev 286a6f557c4SEugeniy Paltsev flush_n_invalidate_dcache_all(); 287a6f557c4SEugeniy Paltsev 288a6f557c4SEugeniy Paltsev if (!is_power_of_2(ap_size) || ap_size < 4096) 289a6f557c4SEugeniy Paltsev panic("IOC Aperture size must be power of 2 and bigger 4Kib"); 290a6f557c4SEugeniy Paltsev 291a6f557c4SEugeniy Paltsev /* 292a6f557c4SEugeniy Paltsev * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, 293a6f557c4SEugeniy Paltsev * so setting 0x11 implies 512M, 0x12 implies 1G... 294a6f557c4SEugeniy Paltsev */ 295a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 296a6f557c4SEugeniy Paltsev order_base_2(ap_size / 1024) - 2); 297a6f557c4SEugeniy Paltsev 298a6f557c4SEugeniy Paltsev /* IOC Aperture start must be aligned to the size of the aperture */ 299a6f557c4SEugeniy Paltsev if (ap_base % ap_size != 0) 300a6f557c4SEugeniy Paltsev panic("IOC Aperture start must be aligned to the size of the aperture"); 301a6f557c4SEugeniy Paltsev 302a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); 303a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); 304a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); 305a6f557c4SEugeniy Paltsev } 306ef639e6fSAlexey Brodkin 307379b3280SAlexey Brodkin static void read_decode_cache_bcr_arcv2(void) 308ef639e6fSAlexey Brodkin { 30905c6a26aSEugeniy Paltsev #ifdef CONFIG_ISA_ARCV2 31005c6a26aSEugeniy Paltsev 31188ae27edSEugeniy Paltsev union bcr_slc_cfg slc_cfg; 312379b3280SAlexey Brodkin 31375790873SEugeniy Paltsev if (slc_exists()) { 314379b3280SAlexey Brodkin slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); 315bf8974edSEugeniy Paltsev gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; 316379b3280SAlexey Brodkin } 317db6ce231SAlexey Brodkin 31805c6a26aSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 319379b3280SAlexey Brodkin } 320379b3280SAlexey Brodkin 321379b3280SAlexey Brodkin void read_decode_cache_bcr(void) 322379b3280SAlexey Brodkin { 323379b3280SAlexey Brodkin int dc_line_sz = 0, ic_line_sz = 0; 32488ae27edSEugeniy Paltsev union bcr_di_cache ibcr, dbcr; 325379b3280SAlexey Brodkin 326379b3280SAlexey Brodkin ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 327379b3280SAlexey Brodkin if (ibcr.fields.ver) { 328bf8974edSEugeniy Paltsev gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; 329379b3280SAlexey Brodkin if (!ic_line_sz) 330379b3280SAlexey Brodkin panic("Instruction exists but line length is 0\n"); 331ef639e6fSAlexey Brodkin } 332ef639e6fSAlexey Brodkin 333379b3280SAlexey Brodkin dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 334379b3280SAlexey Brodkin if (dbcr.fields.ver) { 335bf8974edSEugeniy Paltsev gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; 336379b3280SAlexey Brodkin if (!dc_line_sz) 337379b3280SAlexey Brodkin panic("Data cache exists but line length is 0\n"); 338379b3280SAlexey Brodkin } 339379b3280SAlexey Brodkin 340379b3280SAlexey Brodkin if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz)) 341379b3280SAlexey Brodkin panic("Instruction and data cache line lengths differ\n"); 342ef639e6fSAlexey Brodkin } 343ef639e6fSAlexey Brodkin 344ef639e6fSAlexey Brodkin void cache_init(void) 345ef639e6fSAlexey Brodkin { 346379b3280SAlexey Brodkin read_decode_cache_bcr(); 347379b3280SAlexey Brodkin 34805c6a26aSEugeniy Paltsev if (is_isa_arcv2()) 349379b3280SAlexey Brodkin read_decode_cache_bcr_arcv2(); 350db6ce231SAlexey Brodkin 351*48b04832SEugeniy Paltsev if (is_isa_arcv2() && ioc_enabled()) 352a6f557c4SEugeniy Paltsev arc_ioc_setup(); 35341cada4dSEugeniy Paltsev 354246ba284SEugeniy Paltsev if (is_isa_arcv2() && slc_exists()) 35541cada4dSEugeniy Paltsev slc_upper_region_init(); 356ef639e6fSAlexey Brodkin } 357ef639e6fSAlexey Brodkin 358660d5f0dSAlexey Brodkin int icache_status(void) 359660d5f0dSAlexey Brodkin { 36075790873SEugeniy Paltsev if (!icache_exists()) 361660d5f0dSAlexey Brodkin return 0; 362660d5f0dSAlexey Brodkin 363ef639e6fSAlexey Brodkin if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) 364ef639e6fSAlexey Brodkin return 0; 365ef639e6fSAlexey Brodkin else 366ef639e6fSAlexey Brodkin return 1; 367660d5f0dSAlexey Brodkin } 368660d5f0dSAlexey Brodkin 369660d5f0dSAlexey Brodkin void icache_enable(void) 370660d5f0dSAlexey Brodkin { 37175790873SEugeniy Paltsev if (icache_exists()) 372660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & 373660d5f0dSAlexey Brodkin ~IC_CTRL_CACHE_DISABLE); 374660d5f0dSAlexey Brodkin } 375660d5f0dSAlexey Brodkin 376660d5f0dSAlexey Brodkin void icache_disable(void) 377660d5f0dSAlexey Brodkin { 37875790873SEugeniy Paltsev if (icache_exists()) 379660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | 380660d5f0dSAlexey Brodkin IC_CTRL_CACHE_DISABLE); 381660d5f0dSAlexey Brodkin } 382660d5f0dSAlexey Brodkin 38316aeee81SEugeniy Paltsev /* IC supports only invalidation */ 38416aeee81SEugeniy Paltsev static inline void __ic_entire_invalidate(void) 385660d5f0dSAlexey Brodkin { 38616aeee81SEugeniy Paltsev if (!icache_status()) 38716aeee81SEugeniy Paltsev return; 38816aeee81SEugeniy Paltsev 389660d5f0dSAlexey Brodkin /* Any write to IC_IVIC register triggers invalidation of entire I$ */ 390660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_IVIC, 1); 391f2a22678SAlexey Brodkin /* 392f2a22678SAlexey Brodkin * As per ARC HS databook (see chapter 5.3.3.2) 393f2a22678SAlexey Brodkin * it is required to add 3 NOPs after each write to IC_IVIC. 394f2a22678SAlexey Brodkin */ 395f2a22678SAlexey Brodkin __builtin_arc_nop(); 396f2a22678SAlexey Brodkin __builtin_arc_nop(); 397f2a22678SAlexey Brodkin __builtin_arc_nop(); 398ef639e6fSAlexey Brodkin read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ 399660d5f0dSAlexey Brodkin } 40041cada4dSEugeniy Paltsev 40116aeee81SEugeniy Paltsev void invalidate_icache_all(void) 40216aeee81SEugeniy Paltsev { 40316aeee81SEugeniy Paltsev __ic_entire_invalidate(); 40416aeee81SEugeniy Paltsev 405ea9f6f1eSEugeniy Paltsev if (is_isa_arcv2()) 40641cada4dSEugeniy Paltsev __slc_entire_op(OP_INV); 40741cada4dSEugeniy Paltsev } 408660d5f0dSAlexey Brodkin 409660d5f0dSAlexey Brodkin int dcache_status(void) 410660d5f0dSAlexey Brodkin { 41175790873SEugeniy Paltsev if (!dcache_exists()) 412660d5f0dSAlexey Brodkin return 0; 413660d5f0dSAlexey Brodkin 414ef639e6fSAlexey Brodkin if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) 415ef639e6fSAlexey Brodkin return 0; 416ef639e6fSAlexey Brodkin else 417ef639e6fSAlexey Brodkin return 1; 418660d5f0dSAlexey Brodkin } 419660d5f0dSAlexey Brodkin 420660d5f0dSAlexey Brodkin void dcache_enable(void) 421660d5f0dSAlexey Brodkin { 42275790873SEugeniy Paltsev if (!dcache_exists()) 423660d5f0dSAlexey Brodkin return; 424660d5f0dSAlexey Brodkin 425660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & 426660d5f0dSAlexey Brodkin ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); 427660d5f0dSAlexey Brodkin } 428660d5f0dSAlexey Brodkin 429660d5f0dSAlexey Brodkin void dcache_disable(void) 430660d5f0dSAlexey Brodkin { 43175790873SEugeniy Paltsev if (!dcache_exists()) 432660d5f0dSAlexey Brodkin return; 433660d5f0dSAlexey Brodkin 434660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | 435660d5f0dSAlexey Brodkin DC_CTRL_CACHE_DISABLE); 436660d5f0dSAlexey Brodkin } 437660d5f0dSAlexey Brodkin 438c4ef14d2SEugeniy Paltsev /* Common Helper for Line Operations on D-cache */ 439c4ef14d2SEugeniy Paltsev static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, 440ef639e6fSAlexey Brodkin const int cacheop) 441660d5f0dSAlexey Brodkin { 442ef639e6fSAlexey Brodkin unsigned int aux_cmd; 443ef639e6fSAlexey Brodkin int num_lines; 444660d5f0dSAlexey Brodkin 445ef639e6fSAlexey Brodkin /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 446ef639e6fSAlexey Brodkin aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; 447660d5f0dSAlexey Brodkin 448ef639e6fSAlexey Brodkin sz += paddr & ~CACHE_LINE_MASK; 449ef639e6fSAlexey Brodkin paddr &= CACHE_LINE_MASK; 450ef639e6fSAlexey Brodkin 451bf8974edSEugeniy Paltsev num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz); 452ef639e6fSAlexey Brodkin 453ef639e6fSAlexey Brodkin while (num_lines-- > 0) { 454ef639e6fSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 455c4ef14d2SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_PTAG, paddr); 456ef639e6fSAlexey Brodkin #endif 457ef639e6fSAlexey Brodkin write_aux_reg(aux_cmd, paddr); 458bf8974edSEugeniy Paltsev paddr += gd->arch.l1_line_sz; 459ef639e6fSAlexey Brodkin } 460ef639e6fSAlexey Brodkin } 461ef639e6fSAlexey Brodkin 4625d7a24d6SEugeniy Paltsev static void __before_dc_op(const int op) 463ef639e6fSAlexey Brodkin { 4645d7a24d6SEugeniy Paltsev unsigned int ctrl; 465ef639e6fSAlexey Brodkin 4665d7a24d6SEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_DC_CTRL); 4675d7a24d6SEugeniy Paltsev 4685d7a24d6SEugeniy Paltsev /* IM bit implies flush-n-inv, instead of vanilla inv */ 4695d7a24d6SEugeniy Paltsev if (op == OP_INV) 4705d7a24d6SEugeniy Paltsev ctrl &= ~DC_CTRL_INV_MODE_FLUSH; 4715d7a24d6SEugeniy Paltsev else 4725d7a24d6SEugeniy Paltsev ctrl |= DC_CTRL_INV_MODE_FLUSH; 4735d7a24d6SEugeniy Paltsev 4745d7a24d6SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_CTRL, ctrl); 475ef639e6fSAlexey Brodkin } 476ef639e6fSAlexey Brodkin 4775d7a24d6SEugeniy Paltsev static void __after_dc_op(const int op) 478ef639e6fSAlexey Brodkin { 479ef639e6fSAlexey Brodkin if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ 48019b10a42SEugeniy Paltsev while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); 481ef639e6fSAlexey Brodkin } 482ef639e6fSAlexey Brodkin 483ef639e6fSAlexey Brodkin static inline void __dc_entire_op(const int cacheop) 484ef639e6fSAlexey Brodkin { 485ef639e6fSAlexey Brodkin int aux; 4865d7a24d6SEugeniy Paltsev 487c877a891SEugeniy Paltsev if (!dcache_status()) 488c877a891SEugeniy Paltsev return; 489c877a891SEugeniy Paltsev 4905d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 491ef639e6fSAlexey Brodkin 492ef639e6fSAlexey Brodkin if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 493ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_IVDC; 494ef639e6fSAlexey Brodkin else 495ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_FLSH; 496ef639e6fSAlexey Brodkin 497ef639e6fSAlexey Brodkin write_aux_reg(aux, 0x1); 498ef639e6fSAlexey Brodkin 4995d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 500ef639e6fSAlexey Brodkin } 501ef639e6fSAlexey Brodkin 502ef639e6fSAlexey Brodkin static inline void __dc_line_op(unsigned long paddr, unsigned long sz, 503ef639e6fSAlexey Brodkin const int cacheop) 504ef639e6fSAlexey Brodkin { 505c877a891SEugeniy Paltsev if (!dcache_status()) 506c877a891SEugeniy Paltsev return; 507c877a891SEugeniy Paltsev 5085d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 509c4ef14d2SEugeniy Paltsev __dcache_line_loop(paddr, sz, cacheop); 5105d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 511ef639e6fSAlexey Brodkin } 512ef639e6fSAlexey Brodkin 513660d5f0dSAlexey Brodkin void invalidate_dcache_range(unsigned long start, unsigned long end) 514660d5f0dSAlexey Brodkin { 51541cada4dSEugeniy Paltsev if (start >= end) 51641cada4dSEugeniy Paltsev return; 51741cada4dSEugeniy Paltsev 51805c6a26aSEugeniy Paltsev /* 51905c6a26aSEugeniy Paltsev * ARCv1 -> call __dc_line_op 52005c6a26aSEugeniy Paltsev * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 52105c6a26aSEugeniy Paltsev * ARCv2 && IOC enabled -> nothing 52205c6a26aSEugeniy Paltsev */ 523*48b04832SEugeniy Paltsev if (!is_isa_arcv2() || !ioc_enabled()) 524db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_INV); 525db6ce231SAlexey Brodkin 526*48b04832SEugeniy Paltsev if (is_isa_arcv2() && !ioc_enabled()) 52741cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_INV); 528660d5f0dSAlexey Brodkin } 529660d5f0dSAlexey Brodkin 530ef639e6fSAlexey Brodkin void flush_dcache_range(unsigned long start, unsigned long end) 531660d5f0dSAlexey Brodkin { 53241cada4dSEugeniy Paltsev if (start >= end) 53341cada4dSEugeniy Paltsev return; 53441cada4dSEugeniy Paltsev 53505c6a26aSEugeniy Paltsev /* 53605c6a26aSEugeniy Paltsev * ARCv1 -> call __dc_line_op 53705c6a26aSEugeniy Paltsev * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 53805c6a26aSEugeniy Paltsev * ARCv2 && IOC enabled -> nothing 53905c6a26aSEugeniy Paltsev */ 540*48b04832SEugeniy Paltsev if (!is_isa_arcv2() || !ioc_enabled()) 541db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_FLUSH); 542db6ce231SAlexey Brodkin 543*48b04832SEugeniy Paltsev if (is_isa_arcv2() && !ioc_enabled()) 54441cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_FLUSH); 545660d5f0dSAlexey Brodkin } 546660d5f0dSAlexey Brodkin 547660d5f0dSAlexey Brodkin void flush_cache(unsigned long start, unsigned long size) 548660d5f0dSAlexey Brodkin { 549660d5f0dSAlexey Brodkin flush_dcache_range(start, start + size); 550660d5f0dSAlexey Brodkin } 5516eb15e50SAlexey Brodkin 552c27814beSEugeniy Paltsev /* 553c27814beSEugeniy Paltsev * As invalidate_dcache_all() is not used in generic U-Boot code and as we 554c27814beSEugeniy Paltsev * don't need it in arch/arc code alone (invalidate without flush) we implement 555c27814beSEugeniy Paltsev * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because 556c27814beSEugeniy Paltsev * it's much safer. See [ NOTE 1 ] for more details. 557c27814beSEugeniy Paltsev */ 558c27814beSEugeniy Paltsev void flush_n_invalidate_dcache_all(void) 559ef639e6fSAlexey Brodkin { 560c27814beSEugeniy Paltsev __dc_entire_op(OP_FLUSH_N_INV); 561db6ce231SAlexey Brodkin 562ea9f6f1eSEugeniy Paltsev if (is_isa_arcv2()) 563c27814beSEugeniy Paltsev __slc_entire_op(OP_FLUSH_N_INV); 5646eb15e50SAlexey Brodkin } 5656eb15e50SAlexey Brodkin 566ef639e6fSAlexey Brodkin void flush_dcache_all(void) 5676eb15e50SAlexey Brodkin { 568db6ce231SAlexey Brodkin __dc_entire_op(OP_FLUSH); 569db6ce231SAlexey Brodkin 570ea9f6f1eSEugeniy Paltsev if (is_isa_arcv2()) 571ef639e6fSAlexey Brodkin __slc_entire_op(OP_FLUSH); 5726eb15e50SAlexey Brodkin } 573