1660d5f0dSAlexey Brodkin /* 2660d5f0dSAlexey Brodkin * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3660d5f0dSAlexey Brodkin * 4660d5f0dSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5660d5f0dSAlexey Brodkin */ 6660d5f0dSAlexey Brodkin 7660d5f0dSAlexey Brodkin #include <config.h> 8379b3280SAlexey Brodkin #include <common.h> 9ef639e6fSAlexey Brodkin #include <linux/compiler.h> 10ef639e6fSAlexey Brodkin #include <linux/kernel.h> 1197a63144SAlexey Brodkin #include <linux/log2.h> 12660d5f0dSAlexey Brodkin #include <asm/arcregs.h> 1388ae27edSEugeniy Paltsev #include <asm/arc-bcr.h> 14205e7a7bSAlexey Brodkin #include <asm/cache.h> 15660d5f0dSAlexey Brodkin 16c27814beSEugeniy Paltsev /* 17c27814beSEugeniy Paltsev * [ NOTE 1 ]: 18c27814beSEugeniy Paltsev * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable 19c27814beSEugeniy Paltsev * operation may result in unexpected behavior and data loss even if we flush 20c27814beSEugeniy Paltsev * data cache right before invalidation. That may happens if we store any context 21c27814beSEugeniy Paltsev * on stack (like we store BLINK register on stack before function call). 22c27814beSEugeniy Paltsev * BLINK register is the register where return address is automatically saved 23c27814beSEugeniy Paltsev * when we do function call with instructions like 'bl'. 24c27814beSEugeniy Paltsev * 25c27814beSEugeniy Paltsev * There is the real example: 26c27814beSEugeniy Paltsev * We may hang in the next code as we store any BLINK register on stack in 27c27814beSEugeniy Paltsev * invalidate_dcache_all() function. 28c27814beSEugeniy Paltsev * 29c27814beSEugeniy Paltsev * void flush_dcache_all() { 30c27814beSEugeniy Paltsev * __dc_entire_op(OP_FLUSH); 31c27814beSEugeniy Paltsev * // Other code // 32c27814beSEugeniy Paltsev * } 33c27814beSEugeniy Paltsev * 34c27814beSEugeniy Paltsev * void invalidate_dcache_all() { 35c27814beSEugeniy Paltsev * __dc_entire_op(OP_INV); 36c27814beSEugeniy Paltsev * // Other code // 37c27814beSEugeniy Paltsev * } 38c27814beSEugeniy Paltsev * 39c27814beSEugeniy Paltsev * void foo(void) { 40c27814beSEugeniy Paltsev * flush_dcache_all(); 41c27814beSEugeniy Paltsev * invalidate_dcache_all(); 42c27814beSEugeniy Paltsev * } 43c27814beSEugeniy Paltsev * 44c27814beSEugeniy Paltsev * Now let's see what really happens during that code execution: 45c27814beSEugeniy Paltsev * 46c27814beSEugeniy Paltsev * foo() 47c27814beSEugeniy Paltsev * |->> call flush_dcache_all 48c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 49c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 1] 50c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 51c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 52c27814beSEugeniy Paltsev * [flush L1 D$] 53c27814beSEugeniy Paltsev * return [jump to BLINK] 54c27814beSEugeniy Paltsev * <<------ 55c27814beSEugeniy Paltsev * [other flush_dcache_all code] 56c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 57c27814beSEugeniy Paltsev * return [jump to BLINK] 58c27814beSEugeniy Paltsev * <<------ 59c27814beSEugeniy Paltsev * |->> call invalidate_dcache_all 60c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 61c27814beSEugeniy Paltsev * [push BLINK] (save to stack) ![point 2] 62c27814beSEugeniy Paltsev * |->> call __dc_entire_op(OP_FLUSH) 63c27814beSEugeniy Paltsev * [return address is saved to BLINK register] 64c27814beSEugeniy Paltsev * [invalidate L1 D$] ![point 3] 65c27814beSEugeniy Paltsev * // Oops!!! 66c27814beSEugeniy Paltsev * // We lose return address from invalidate_dcache_all function: 67c27814beSEugeniy Paltsev * // we save it to stack and invalidate L1 D$ after that! 68c27814beSEugeniy Paltsev * return [jump to BLINK] 69c27814beSEugeniy Paltsev * <<------ 70c27814beSEugeniy Paltsev * [other invalidate_dcache_all code] 71c27814beSEugeniy Paltsev * [pop BLINK] (get from stack) 72c27814beSEugeniy Paltsev * // we don't have this data in L1 dcache as we invalidated it in [point 3] 73c27814beSEugeniy Paltsev * // so we get it from next memory level (for example DDR memory) 74c27814beSEugeniy Paltsev * // but in the memory we have value which we save in [point 1], which 75c27814beSEugeniy Paltsev * // is return address from flush_dcache_all function (instead of 76c27814beSEugeniy Paltsev * // address from current invalidate_dcache_all function which we 77c27814beSEugeniy Paltsev * // saved in [point 2] !) 78c27814beSEugeniy Paltsev * return [jump to BLINK] 79c27814beSEugeniy Paltsev * <<------ 80c27814beSEugeniy Paltsev * // As BLINK points to invalidate_dcache_all, we call it again and 81c27814beSEugeniy Paltsev * // loop forever. 82c27814beSEugeniy Paltsev * 83c27814beSEugeniy Paltsev * Fortunately we may fix that by using flush & invalidation of D$ with a single 84c27814beSEugeniy Paltsev * one instruction (instead of flush and invalidation instructions pair) and 85c27814beSEugeniy Paltsev * enabling force function inline with '__attribute__((always_inline))' gcc 86c27814beSEugeniy Paltsev * attribute to avoid any function call (and BLINK store) between cache flush 87c27814beSEugeniy Paltsev * and disable. 88c27814beSEugeniy Paltsev */ 89c27814beSEugeniy Paltsev 90660d5f0dSAlexey Brodkin /* Bit values in IC_CTRL */ 9119b10a42SEugeniy Paltsev #define IC_CTRL_CACHE_DISABLE BIT(0) 92660d5f0dSAlexey Brodkin 93660d5f0dSAlexey Brodkin /* Bit values in DC_CTRL */ 9419b10a42SEugeniy Paltsev #define DC_CTRL_CACHE_DISABLE BIT(0) 9519b10a42SEugeniy Paltsev #define DC_CTRL_INV_MODE_FLUSH BIT(6) 9619b10a42SEugeniy Paltsev #define DC_CTRL_FLUSH_STATUS BIT(8) 97660d5f0dSAlexey Brodkin #define CACHE_VER_NUM_MASK 0xF 98660d5f0dSAlexey Brodkin 995d7a24d6SEugeniy Paltsev #define OP_INV BIT(0) 1005d7a24d6SEugeniy Paltsev #define OP_FLUSH BIT(1) 1015d7a24d6SEugeniy Paltsev #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV) 102ef639e6fSAlexey Brodkin 10341cada4dSEugeniy Paltsev /* Bit val in SLC_CONTROL */ 10441cada4dSEugeniy Paltsev #define SLC_CTRL_DIS 0x001 10541cada4dSEugeniy Paltsev #define SLC_CTRL_IM 0x040 10641cada4dSEugeniy Paltsev #define SLC_CTRL_BUSY 0x100 10741cada4dSEugeniy Paltsev #define SLC_CTRL_RGN_OP_INV 0x200 10841cada4dSEugeniy Paltsev 109ef639e6fSAlexey Brodkin /* 110ef639e6fSAlexey Brodkin * By default that variable will fall into .bss section. 111ef639e6fSAlexey Brodkin * But .bss section is not relocated and so it will be initilized before 112ef639e6fSAlexey Brodkin * relocation but will be used after being zeroed. 113ef639e6fSAlexey Brodkin */ 114379b3280SAlexey Brodkin int l1_line_sz __section(".data"); 1153cf23939SEugeniy Paltsev bool dcache_exists __section(".data") = false; 1163cf23939SEugeniy Paltsev bool icache_exists __section(".data") = false; 117379b3280SAlexey Brodkin 118379b3280SAlexey Brodkin #define CACHE_LINE_MASK (~(l1_line_sz - 1)) 119379b3280SAlexey Brodkin 120ef639e6fSAlexey Brodkin int slc_line_sz __section(".data"); 1213cf23939SEugeniy Paltsev bool slc_exists __section(".data") = false; 1223cf23939SEugeniy Paltsev bool ioc_exists __section(".data") = false; 12341cada4dSEugeniy Paltsev bool pae_exists __section(".data") = false; 124ef639e6fSAlexey Brodkin 125b0146f9eSEugeniy Paltsev /* To force enable IOC set ioc_enable to 'true' */ 126b0146f9eSEugeniy Paltsev bool ioc_enable __section(".data") = false; 127b0146f9eSEugeniy Paltsev 12841cada4dSEugeniy Paltsev void read_decode_mmu_bcr(void) 129ef639e6fSAlexey Brodkin { 13041cada4dSEugeniy Paltsev /* TODO: should we compare mmu version from BCR and from CONFIG? */ 13141cada4dSEugeniy Paltsev #if (CONFIG_ARC_MMU_VER >= 4) 13288ae27edSEugeniy Paltsev union bcr_mmu_4 mmu4; 133ef639e6fSAlexey Brodkin 13488ae27edSEugeniy Paltsev mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR); 135ef639e6fSAlexey Brodkin 13688ae27edSEugeniy Paltsev pae_exists = !!mmu4.fields.pae; 13741cada4dSEugeniy Paltsev #endif /* (CONFIG_ARC_MMU_VER >= 4) */ 13841cada4dSEugeniy Paltsev } 13941cada4dSEugeniy Paltsev 14041cada4dSEugeniy Paltsev static void __slc_entire_op(const int op) 14141cada4dSEugeniy Paltsev { 14241cada4dSEugeniy Paltsev unsigned int ctrl; 14341cada4dSEugeniy Paltsev 14441cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 14541cada4dSEugeniy Paltsev 14641cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 14741cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 14841cada4dSEugeniy Paltsev else 14941cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 15041cada4dSEugeniy Paltsev 15141cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 15241cada4dSEugeniy Paltsev 15341cada4dSEugeniy Paltsev if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 15441cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); 15541cada4dSEugeniy Paltsev else 15641cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); 15741cada4dSEugeniy Paltsev 15841cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 15941cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 16041cada4dSEugeniy Paltsev 16141cada4dSEugeniy Paltsev /* Important to wait for flush to complete */ 16241cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 16341cada4dSEugeniy Paltsev } 16441cada4dSEugeniy Paltsev 16541cada4dSEugeniy Paltsev static void slc_upper_region_init(void) 16641cada4dSEugeniy Paltsev { 16741cada4dSEugeniy Paltsev /* 16841cada4dSEugeniy Paltsev * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 16941cada4dSEugeniy Paltsev * as we don't use PAE40. 17041cada4dSEugeniy Paltsev */ 17141cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); 17241cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); 17341cada4dSEugeniy Paltsev } 17441cada4dSEugeniy Paltsev 17541cada4dSEugeniy Paltsev static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) 17641cada4dSEugeniy Paltsev { 177*05c6a26aSEugeniy Paltsev #ifdef CONFIG_ISA_ARCV2 178*05c6a26aSEugeniy Paltsev 17941cada4dSEugeniy Paltsev unsigned int ctrl; 18041cada4dSEugeniy Paltsev unsigned long end; 18141cada4dSEugeniy Paltsev 18241cada4dSEugeniy Paltsev /* 18341cada4dSEugeniy Paltsev * The Region Flush operation is specified by CTRL.RGN_OP[11..9] 18441cada4dSEugeniy Paltsev * - b'000 (default) is Flush, 18541cada4dSEugeniy Paltsev * - b'001 is Invalidate if CTRL.IM == 0 18641cada4dSEugeniy Paltsev * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 18741cada4dSEugeniy Paltsev */ 18841cada4dSEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); 18941cada4dSEugeniy Paltsev 19041cada4dSEugeniy Paltsev /* Don't rely on default value of IM bit */ 19141cada4dSEugeniy Paltsev if (!(op & OP_FLUSH)) /* i.e. OP_INV */ 19241cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ 19341cada4dSEugeniy Paltsev else 19441cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_IM; 19541cada4dSEugeniy Paltsev 19641cada4dSEugeniy Paltsev if (op & OP_INV) 19741cada4dSEugeniy Paltsev ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ 19841cada4dSEugeniy Paltsev else 19941cada4dSEugeniy Paltsev ctrl &= ~SLC_CTRL_RGN_OP_INV; 20041cada4dSEugeniy Paltsev 20141cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); 20241cada4dSEugeniy Paltsev 20341cada4dSEugeniy Paltsev /* 20441cada4dSEugeniy Paltsev * Lower bits are ignored, no need to clip 20541cada4dSEugeniy Paltsev * END needs to be setup before START (latter triggers the operation) 20641cada4dSEugeniy Paltsev * END can't be same as START, so add (l2_line_sz - 1) to sz 20741cada4dSEugeniy Paltsev */ 20841cada4dSEugeniy Paltsev end = paddr + sz + slc_line_sz - 1; 20941cada4dSEugeniy Paltsev 21041cada4dSEugeniy Paltsev /* 21141cada4dSEugeniy Paltsev * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) 21241cada4dSEugeniy Paltsev * are always == 0 as we don't use PAE40, so we only setup lower ones 21341cada4dSEugeniy Paltsev * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START) 21441cada4dSEugeniy Paltsev */ 21541cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_END, end); 21641cada4dSEugeniy Paltsev write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); 21741cada4dSEugeniy Paltsev 21841cada4dSEugeniy Paltsev /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ 21941cada4dSEugeniy Paltsev read_aux_reg(ARC_AUX_SLC_CTRL); 22041cada4dSEugeniy Paltsev 22141cada4dSEugeniy Paltsev while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); 222*05c6a26aSEugeniy Paltsev 223*05c6a26aSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 22441cada4dSEugeniy Paltsev } 225a6f557c4SEugeniy Paltsev 226a6f557c4SEugeniy Paltsev static void arc_ioc_setup(void) 227a6f557c4SEugeniy Paltsev { 228a6f557c4SEugeniy Paltsev /* IOC Aperture start is equal to DDR start */ 229a6f557c4SEugeniy Paltsev unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; 230a6f557c4SEugeniy Paltsev /* IOC Aperture size is equal to DDR size */ 231a6f557c4SEugeniy Paltsev long ap_size = CONFIG_SYS_SDRAM_SIZE; 232a6f557c4SEugeniy Paltsev 233a6f557c4SEugeniy Paltsev flush_n_invalidate_dcache_all(); 234a6f557c4SEugeniy Paltsev 235a6f557c4SEugeniy Paltsev if (!is_power_of_2(ap_size) || ap_size < 4096) 236a6f557c4SEugeniy Paltsev panic("IOC Aperture size must be power of 2 and bigger 4Kib"); 237a6f557c4SEugeniy Paltsev 238a6f557c4SEugeniy Paltsev /* 239a6f557c4SEugeniy Paltsev * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, 240a6f557c4SEugeniy Paltsev * so setting 0x11 implies 512M, 0x12 implies 1G... 241a6f557c4SEugeniy Paltsev */ 242a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 243a6f557c4SEugeniy Paltsev order_base_2(ap_size / 1024) - 2); 244a6f557c4SEugeniy Paltsev 245a6f557c4SEugeniy Paltsev /* IOC Aperture start must be aligned to the size of the aperture */ 246a6f557c4SEugeniy Paltsev if (ap_base % ap_size != 0) 247a6f557c4SEugeniy Paltsev panic("IOC Aperture start must be aligned to the size of the aperture"); 248a6f557c4SEugeniy Paltsev 249a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); 250a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); 251a6f557c4SEugeniy Paltsev write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); 252a6f557c4SEugeniy Paltsev } 253ef639e6fSAlexey Brodkin 254379b3280SAlexey Brodkin static void read_decode_cache_bcr_arcv2(void) 255ef639e6fSAlexey Brodkin { 256*05c6a26aSEugeniy Paltsev #ifdef CONFIG_ISA_ARCV2 257*05c6a26aSEugeniy Paltsev 25888ae27edSEugeniy Paltsev union bcr_slc_cfg slc_cfg; 25988ae27edSEugeniy Paltsev union bcr_clust_cfg cbcr; 26088ae27edSEugeniy Paltsev union bcr_generic sbcr; 261379b3280SAlexey Brodkin 262379b3280SAlexey Brodkin sbcr.word = read_aux_reg(ARC_BCR_SLC); 263379b3280SAlexey Brodkin if (sbcr.fields.ver) { 264379b3280SAlexey Brodkin slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); 2653cf23939SEugeniy Paltsev slc_exists = true; 266379b3280SAlexey Brodkin slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; 267379b3280SAlexey Brodkin } 268db6ce231SAlexey Brodkin 269db6ce231SAlexey Brodkin cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); 270b0146f9eSEugeniy Paltsev if (cbcr.fields.c && ioc_enable) 2713cf23939SEugeniy Paltsev ioc_exists = true; 272*05c6a26aSEugeniy Paltsev 273*05c6a26aSEugeniy Paltsev #endif /* CONFIG_ISA_ARCV2 */ 274379b3280SAlexey Brodkin } 275379b3280SAlexey Brodkin 276379b3280SAlexey Brodkin void read_decode_cache_bcr(void) 277379b3280SAlexey Brodkin { 278379b3280SAlexey Brodkin int dc_line_sz = 0, ic_line_sz = 0; 27988ae27edSEugeniy Paltsev union bcr_di_cache ibcr, dbcr; 280379b3280SAlexey Brodkin 281379b3280SAlexey Brodkin ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); 282379b3280SAlexey Brodkin if (ibcr.fields.ver) { 2833cf23939SEugeniy Paltsev icache_exists = true; 284379b3280SAlexey Brodkin l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; 285379b3280SAlexey Brodkin if (!ic_line_sz) 286379b3280SAlexey Brodkin panic("Instruction exists but line length is 0\n"); 287ef639e6fSAlexey Brodkin } 288ef639e6fSAlexey Brodkin 289379b3280SAlexey Brodkin dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); 290379b3280SAlexey Brodkin if (dbcr.fields.ver) { 2913cf23939SEugeniy Paltsev dcache_exists = true; 292379b3280SAlexey Brodkin l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; 293379b3280SAlexey Brodkin if (!dc_line_sz) 294379b3280SAlexey Brodkin panic("Data cache exists but line length is 0\n"); 295379b3280SAlexey Brodkin } 296379b3280SAlexey Brodkin 297379b3280SAlexey Brodkin if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz)) 298379b3280SAlexey Brodkin panic("Instruction and data cache line lengths differ\n"); 299ef639e6fSAlexey Brodkin } 300ef639e6fSAlexey Brodkin 301ef639e6fSAlexey Brodkin void cache_init(void) 302ef639e6fSAlexey Brodkin { 303379b3280SAlexey Brodkin read_decode_cache_bcr(); 304379b3280SAlexey Brodkin 305*05c6a26aSEugeniy Paltsev if (is_isa_arcv2()) 306379b3280SAlexey Brodkin read_decode_cache_bcr_arcv2(); 307db6ce231SAlexey Brodkin 308*05c6a26aSEugeniy Paltsev if (is_isa_arcv2() && ioc_exists) 309a6f557c4SEugeniy Paltsev arc_ioc_setup(); 31041cada4dSEugeniy Paltsev 31141cada4dSEugeniy Paltsev read_decode_mmu_bcr(); 31241cada4dSEugeniy Paltsev 31341cada4dSEugeniy Paltsev /* 31441cada4dSEugeniy Paltsev * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist 31541cada4dSEugeniy Paltsev * only if PAE exists in current HW. So we had to check pae_exist 31641cada4dSEugeniy Paltsev * before using them. 31741cada4dSEugeniy Paltsev */ 318*05c6a26aSEugeniy Paltsev if (is_isa_arcv2() && slc_exists && pae_exists) 31941cada4dSEugeniy Paltsev slc_upper_region_init(); 320ef639e6fSAlexey Brodkin } 321ef639e6fSAlexey Brodkin 322660d5f0dSAlexey Brodkin int icache_status(void) 323660d5f0dSAlexey Brodkin { 324379b3280SAlexey Brodkin if (!icache_exists) 325660d5f0dSAlexey Brodkin return 0; 326660d5f0dSAlexey Brodkin 327ef639e6fSAlexey Brodkin if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) 328ef639e6fSAlexey Brodkin return 0; 329ef639e6fSAlexey Brodkin else 330ef639e6fSAlexey Brodkin return 1; 331660d5f0dSAlexey Brodkin } 332660d5f0dSAlexey Brodkin 333660d5f0dSAlexey Brodkin void icache_enable(void) 334660d5f0dSAlexey Brodkin { 335379b3280SAlexey Brodkin if (icache_exists) 336660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & 337660d5f0dSAlexey Brodkin ~IC_CTRL_CACHE_DISABLE); 338660d5f0dSAlexey Brodkin } 339660d5f0dSAlexey Brodkin 340660d5f0dSAlexey Brodkin void icache_disable(void) 341660d5f0dSAlexey Brodkin { 342379b3280SAlexey Brodkin if (icache_exists) 343660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | 344660d5f0dSAlexey Brodkin IC_CTRL_CACHE_DISABLE); 345660d5f0dSAlexey Brodkin } 346660d5f0dSAlexey Brodkin 34716aeee81SEugeniy Paltsev /* IC supports only invalidation */ 34816aeee81SEugeniy Paltsev static inline void __ic_entire_invalidate(void) 349660d5f0dSAlexey Brodkin { 35016aeee81SEugeniy Paltsev if (!icache_status()) 35116aeee81SEugeniy Paltsev return; 35216aeee81SEugeniy Paltsev 353660d5f0dSAlexey Brodkin /* Any write to IC_IVIC register triggers invalidation of entire I$ */ 354660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_IC_IVIC, 1); 355f2a22678SAlexey Brodkin /* 356f2a22678SAlexey Brodkin * As per ARC HS databook (see chapter 5.3.3.2) 357f2a22678SAlexey Brodkin * it is required to add 3 NOPs after each write to IC_IVIC. 358f2a22678SAlexey Brodkin */ 359f2a22678SAlexey Brodkin __builtin_arc_nop(); 360f2a22678SAlexey Brodkin __builtin_arc_nop(); 361f2a22678SAlexey Brodkin __builtin_arc_nop(); 362ef639e6fSAlexey Brodkin read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ 363660d5f0dSAlexey Brodkin } 36441cada4dSEugeniy Paltsev 36516aeee81SEugeniy Paltsev void invalidate_icache_all(void) 36616aeee81SEugeniy Paltsev { 36716aeee81SEugeniy Paltsev __ic_entire_invalidate(); 36816aeee81SEugeniy Paltsev 369*05c6a26aSEugeniy Paltsev if (is_isa_arcv2() && slc_exists) 37041cada4dSEugeniy Paltsev __slc_entire_op(OP_INV); 37141cada4dSEugeniy Paltsev } 372660d5f0dSAlexey Brodkin 373660d5f0dSAlexey Brodkin int dcache_status(void) 374660d5f0dSAlexey Brodkin { 375379b3280SAlexey Brodkin if (!dcache_exists) 376660d5f0dSAlexey Brodkin return 0; 377660d5f0dSAlexey Brodkin 378ef639e6fSAlexey Brodkin if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) 379ef639e6fSAlexey Brodkin return 0; 380ef639e6fSAlexey Brodkin else 381ef639e6fSAlexey Brodkin return 1; 382660d5f0dSAlexey Brodkin } 383660d5f0dSAlexey Brodkin 384660d5f0dSAlexey Brodkin void dcache_enable(void) 385660d5f0dSAlexey Brodkin { 386379b3280SAlexey Brodkin if (!dcache_exists) 387660d5f0dSAlexey Brodkin return; 388660d5f0dSAlexey Brodkin 389660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & 390660d5f0dSAlexey Brodkin ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); 391660d5f0dSAlexey Brodkin } 392660d5f0dSAlexey Brodkin 393660d5f0dSAlexey Brodkin void dcache_disable(void) 394660d5f0dSAlexey Brodkin { 395379b3280SAlexey Brodkin if (!dcache_exists) 396660d5f0dSAlexey Brodkin return; 397660d5f0dSAlexey Brodkin 398660d5f0dSAlexey Brodkin write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | 399660d5f0dSAlexey Brodkin DC_CTRL_CACHE_DISABLE); 400660d5f0dSAlexey Brodkin } 401660d5f0dSAlexey Brodkin 402c4ef14d2SEugeniy Paltsev /* Common Helper for Line Operations on D-cache */ 403c4ef14d2SEugeniy Paltsev static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, 404ef639e6fSAlexey Brodkin const int cacheop) 405660d5f0dSAlexey Brodkin { 406ef639e6fSAlexey Brodkin unsigned int aux_cmd; 407ef639e6fSAlexey Brodkin int num_lines; 408660d5f0dSAlexey Brodkin 409ef639e6fSAlexey Brodkin /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ 410ef639e6fSAlexey Brodkin aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; 411660d5f0dSAlexey Brodkin 412ef639e6fSAlexey Brodkin sz += paddr & ~CACHE_LINE_MASK; 413ef639e6fSAlexey Brodkin paddr &= CACHE_LINE_MASK; 414ef639e6fSAlexey Brodkin 415379b3280SAlexey Brodkin num_lines = DIV_ROUND_UP(sz, l1_line_sz); 416ef639e6fSAlexey Brodkin 417ef639e6fSAlexey Brodkin while (num_lines-- > 0) { 418ef639e6fSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 419c4ef14d2SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_PTAG, paddr); 420ef639e6fSAlexey Brodkin #endif 421ef639e6fSAlexey Brodkin write_aux_reg(aux_cmd, paddr); 422379b3280SAlexey Brodkin paddr += l1_line_sz; 423ef639e6fSAlexey Brodkin } 424ef639e6fSAlexey Brodkin } 425ef639e6fSAlexey Brodkin 4265d7a24d6SEugeniy Paltsev static void __before_dc_op(const int op) 427ef639e6fSAlexey Brodkin { 4285d7a24d6SEugeniy Paltsev unsigned int ctrl; 429ef639e6fSAlexey Brodkin 4305d7a24d6SEugeniy Paltsev ctrl = read_aux_reg(ARC_AUX_DC_CTRL); 4315d7a24d6SEugeniy Paltsev 4325d7a24d6SEugeniy Paltsev /* IM bit implies flush-n-inv, instead of vanilla inv */ 4335d7a24d6SEugeniy Paltsev if (op == OP_INV) 4345d7a24d6SEugeniy Paltsev ctrl &= ~DC_CTRL_INV_MODE_FLUSH; 4355d7a24d6SEugeniy Paltsev else 4365d7a24d6SEugeniy Paltsev ctrl |= DC_CTRL_INV_MODE_FLUSH; 4375d7a24d6SEugeniy Paltsev 4385d7a24d6SEugeniy Paltsev write_aux_reg(ARC_AUX_DC_CTRL, ctrl); 439ef639e6fSAlexey Brodkin } 440ef639e6fSAlexey Brodkin 4415d7a24d6SEugeniy Paltsev static void __after_dc_op(const int op) 442ef639e6fSAlexey Brodkin { 443ef639e6fSAlexey Brodkin if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ 44419b10a42SEugeniy Paltsev while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); 445ef639e6fSAlexey Brodkin } 446ef639e6fSAlexey Brodkin 447ef639e6fSAlexey Brodkin static inline void __dc_entire_op(const int cacheop) 448ef639e6fSAlexey Brodkin { 449ef639e6fSAlexey Brodkin int aux; 4505d7a24d6SEugeniy Paltsev 451c877a891SEugeniy Paltsev if (!dcache_status()) 452c877a891SEugeniy Paltsev return; 453c877a891SEugeniy Paltsev 4545d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 455ef639e6fSAlexey Brodkin 456ef639e6fSAlexey Brodkin if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ 457ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_IVDC; 458ef639e6fSAlexey Brodkin else 459ef639e6fSAlexey Brodkin aux = ARC_AUX_DC_FLSH; 460ef639e6fSAlexey Brodkin 461ef639e6fSAlexey Brodkin write_aux_reg(aux, 0x1); 462ef639e6fSAlexey Brodkin 4635d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 464ef639e6fSAlexey Brodkin } 465ef639e6fSAlexey Brodkin 466ef639e6fSAlexey Brodkin static inline void __dc_line_op(unsigned long paddr, unsigned long sz, 467ef639e6fSAlexey Brodkin const int cacheop) 468ef639e6fSAlexey Brodkin { 469c877a891SEugeniy Paltsev if (!dcache_status()) 470c877a891SEugeniy Paltsev return; 471c877a891SEugeniy Paltsev 4725d7a24d6SEugeniy Paltsev __before_dc_op(cacheop); 473c4ef14d2SEugeniy Paltsev __dcache_line_loop(paddr, sz, cacheop); 4745d7a24d6SEugeniy Paltsev __after_dc_op(cacheop); 475ef639e6fSAlexey Brodkin } 476ef639e6fSAlexey Brodkin 477660d5f0dSAlexey Brodkin void invalidate_dcache_range(unsigned long start, unsigned long end) 478660d5f0dSAlexey Brodkin { 47941cada4dSEugeniy Paltsev if (start >= end) 48041cada4dSEugeniy Paltsev return; 48141cada4dSEugeniy Paltsev 482*05c6a26aSEugeniy Paltsev /* 483*05c6a26aSEugeniy Paltsev * ARCv1 -> call __dc_line_op 484*05c6a26aSEugeniy Paltsev * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 485*05c6a26aSEugeniy Paltsev * ARCv2 && IOC enabled -> nothing 486*05c6a26aSEugeniy Paltsev */ 487*05c6a26aSEugeniy Paltsev if (!is_isa_arcv2() || !ioc_exists) 488db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_INV); 489db6ce231SAlexey Brodkin 490*05c6a26aSEugeniy Paltsev if (is_isa_arcv2() && slc_exists && !ioc_exists) 49141cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_INV); 492660d5f0dSAlexey Brodkin } 493660d5f0dSAlexey Brodkin 494ef639e6fSAlexey Brodkin void flush_dcache_range(unsigned long start, unsigned long end) 495660d5f0dSAlexey Brodkin { 49641cada4dSEugeniy Paltsev if (start >= end) 49741cada4dSEugeniy Paltsev return; 49841cada4dSEugeniy Paltsev 499*05c6a26aSEugeniy Paltsev /* 500*05c6a26aSEugeniy Paltsev * ARCv1 -> call __dc_line_op 501*05c6a26aSEugeniy Paltsev * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op 502*05c6a26aSEugeniy Paltsev * ARCv2 && IOC enabled -> nothing 503*05c6a26aSEugeniy Paltsev */ 504*05c6a26aSEugeniy Paltsev if (!is_isa_arcv2() || !ioc_exists) 505db6ce231SAlexey Brodkin __dc_line_op(start, end - start, OP_FLUSH); 506db6ce231SAlexey Brodkin 507*05c6a26aSEugeniy Paltsev if (is_isa_arcv2() && slc_exists && !ioc_exists) 50841cada4dSEugeniy Paltsev __slc_rgn_op(start, end - start, OP_FLUSH); 509660d5f0dSAlexey Brodkin } 510660d5f0dSAlexey Brodkin 511660d5f0dSAlexey Brodkin void flush_cache(unsigned long start, unsigned long size) 512660d5f0dSAlexey Brodkin { 513660d5f0dSAlexey Brodkin flush_dcache_range(start, start + size); 514660d5f0dSAlexey Brodkin } 5156eb15e50SAlexey Brodkin 516c27814beSEugeniy Paltsev /* 517c27814beSEugeniy Paltsev * As invalidate_dcache_all() is not used in generic U-Boot code and as we 518c27814beSEugeniy Paltsev * don't need it in arch/arc code alone (invalidate without flush) we implement 519c27814beSEugeniy Paltsev * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because 520c27814beSEugeniy Paltsev * it's much safer. See [ NOTE 1 ] for more details. 521c27814beSEugeniy Paltsev */ 522c27814beSEugeniy Paltsev void flush_n_invalidate_dcache_all(void) 523ef639e6fSAlexey Brodkin { 524c27814beSEugeniy Paltsev __dc_entire_op(OP_FLUSH_N_INV); 525db6ce231SAlexey Brodkin 526*05c6a26aSEugeniy Paltsev if (is_isa_arcv2() && slc_exists) 527c27814beSEugeniy Paltsev __slc_entire_op(OP_FLUSH_N_INV); 5286eb15e50SAlexey Brodkin } 5296eb15e50SAlexey Brodkin 530ef639e6fSAlexey Brodkin void flush_dcache_all(void) 5316eb15e50SAlexey Brodkin { 532db6ce231SAlexey Brodkin __dc_entire_op(OP_FLUSH); 533db6ce231SAlexey Brodkin 534*05c6a26aSEugeniy Paltsev if (is_isa_arcv2() && slc_exists) 535ef639e6fSAlexey Brodkin __slc_entire_op(OP_FLUSH); 5366eb15e50SAlexey Brodkin } 537