1menu "ARC architecture" 2 depends on ARC 3 4config SYS_ARCH 5 default "arc" 6 7config SYS_CPU 8 default "arcv1" if ISA_ARCOMPACT 9 default "arcv2" if ISA_ARCV2 10 11choice 12 prompt "ARC Instruction Set" 13 default ISA_ARCOMPACT 14 15config ISA_ARCOMPACT 16 bool "ARCompact ISA" 17 help 18 The original ARC ISA of ARC600/700 cores 19 20config ISA_ARCV2 21 bool "ARC ISA v2" 22 help 23 ISA for the Next Generation ARC-HS cores 24 25endchoice 26 27choice 28 prompt "CPU selection" 29 default CPU_ARC770D if ISA_ARCOMPACT 30 default CPU_ARCHS38 if ISA_ARCV2 31 32config CPU_ARC750D 33 bool "ARC 750D" 34 select ARC_MMU_V2 35 depends on ISA_ARCOMPACT 36 help 37 Choose this option to build an U-Boot for ARC750D CPU. 38 39config CPU_ARC770D 40 bool "ARC 770D" 41 select ARC_MMU_V3 42 depends on ISA_ARCOMPACT 43 help 44 Choose this option to build an U-Boot for ARC770D CPU. 45 46config CPU_ARCEM6 47 bool "ARC EM6" 48 select ARC_MMU_ABSENT 49 depends on ISA_ARCV2 50 help 51 Next Generation ARC Core based on ISA-v2 ISA without MMU. 52 53config CPU_ARCHS36 54 bool "ARC HS36" 55 select ARC_MMU_ABSENT 56 depends on ISA_ARCV2 57 help 58 Next Generation ARC Core based on ISA-v2 ISA without MMU. 59 60config CPU_ARCHS38 61 bool "ARC HS38" 62 select ARC_MMU_V4 63 depends on ISA_ARCV2 64 help 65 Next Generation ARC Core based on ISA-v2 ISA with MMU. 66 67endchoice 68 69choice 70 prompt "MMU Version" 71 default ARC_MMU_V3 if CPU_ARC770D 72 default ARC_MMU_V2 if CPU_ARC750D 73 default ARC_MMU_ABSENT if CPU_ARCEM6 74 default ARC_MMU_ABSENT if CPU_ARCHS36 75 default ARC_MMU_V4 if CPU_ARCHS38 76 77config ARC_MMU_ABSENT 78 bool "No MMU" 79 help 80 No MMU 81 82config ARC_MMU_V2 83 bool "MMU v2" 84 depends on CPU_ARC750D 85 help 86 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio 87 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 88 89config ARC_MMU_V3 90 bool "MMU v3" 91 depends on CPU_ARC770D 92 help 93 Introduced with ARC700 4.10: New Features 94 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 95 Shared Address Spaces (SASID) 96 97config ARC_MMU_V4 98 bool "MMU v4" 99 depends on CPU_ARCHS38 100 help 101 Introduced as a part of ARC HS38 release. 102 103endchoice 104 105config CPU_BIG_ENDIAN 106 bool "Enable Big Endian Mode" 107 default n 108 help 109 Build kernel for Big Endian Mode of ARC CPU 110 111config SYS_ICACHE_OFF 112 bool "Do not use Instruction Cache" 113 default n 114 115config SYS_DCACHE_OFF 116 bool "Do not use Data Cache" 117 default n 118 119config ARC_CACHE_LINE_SHIFT 120 int "Cache Line Length (as power of 2)" 121 range 5 7 122 default "6" 123 depends on !SYS_DCACHE_OFF || !SYS_ICACHE_OFF 124 help 125 Starting with ARC700 4.9, Cache line length is configurable, 126 This option specifies "N", with Line-len = 2 power N 127 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 128 Linux only supports same line lengths for I and D caches. 129 130choice 131 prompt "Target select" 132 default TARGET_AXS101 133 134config TARGET_TB100 135 bool "Support tb100" 136 137config TARGET_ARCANGEL4 138 bool "Support arcangel4" 139 140config TARGET_AXS101 141 bool "Support axs101" 142 143endchoice 144 145source "board/abilis/tb100/Kconfig" 146source "board/synopsys/Kconfig" 147source "board/synopsys/axs101/Kconfig" 148 149endmenu 150