1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 */ 7 8 #ifndef TCG_TARGET_HAS_H 9 #define TCG_TARGET_HAS_H 10 11 /* MOVN/MOVZ instructions detection */ 12 #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ 13 defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \ 14 defined(_MIPS_ARCH_MIPS4) 15 #define use_movnz_instructions 1 16 #else 17 extern bool use_movnz_instructions; 18 #endif 19 20 /* MIPS32 instruction set detection */ 21 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 1) 22 #define use_mips32_instructions 1 23 #else 24 extern bool use_mips32_instructions; 25 #endif 26 27 /* MIPS32R2 instruction set detection */ 28 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) 29 #define use_mips32r2_instructions 1 30 #else 31 extern bool use_mips32r2_instructions; 32 #endif 33 34 /* MIPS32R6 instruction set detection */ 35 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 6) 36 #define use_mips32r6_instructions 1 37 #else 38 #define use_mips32r6_instructions 0 39 #endif 40 41 /* optional instructions */ 42 #define TCG_TARGET_HAS_bswap16_i32 1 43 #define TCG_TARGET_HAS_bswap32_i32 1 44 #define TCG_TARGET_HAS_negsetcond_i32 0 45 46 #if TCG_TARGET_REG_BITS == 64 47 #define TCG_TARGET_HAS_add2_i32 0 48 #define TCG_TARGET_HAS_sub2_i32 0 49 #define TCG_TARGET_HAS_extr_i64_i32 1 50 #define TCG_TARGET_HAS_add2_i64 0 51 #define TCG_TARGET_HAS_sub2_i64 0 52 #define TCG_TARGET_HAS_ext32s_i64 1 53 #define TCG_TARGET_HAS_ext32u_i64 1 54 #define TCG_TARGET_HAS_negsetcond_i64 0 55 #endif 56 57 /* optional instructions detected at runtime */ 58 #define TCG_TARGET_HAS_extract2_i32 0 59 #define TCG_TARGET_HAS_qemu_st8_i32 0 60 61 #if TCG_TARGET_REG_BITS == 64 62 #define TCG_TARGET_HAS_bswap16_i64 1 63 #define TCG_TARGET_HAS_bswap32_i64 1 64 #define TCG_TARGET_HAS_bswap64_i64 1 65 #define TCG_TARGET_HAS_extract2_i64 0 66 #endif 67 68 #define TCG_TARGET_HAS_qemu_ldst_i128 0 69 #define TCG_TARGET_HAS_tst 0 70 71 #define TCG_TARGET_extract_valid(type, ofs, len) use_mips32r2_instructions 72 #define TCG_TARGET_deposit_valid(type, ofs, len) use_mips32r2_instructions 73 74 static inline bool 75 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 76 { 77 if (ofs == 0) { 78 switch (len) { 79 case 8: 80 case 16: 81 return use_mips32r2_instructions; 82 case 32: 83 return type == TCG_TYPE_I64; 84 } 85 } 86 return false; 87 } 88 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 89 90 #endif 91