1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define target-specific opcode support
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 */
7
8 #ifndef TCG_TARGET_HAS_H
9 #define TCG_TARGET_HAS_H
10
11 /* MOVN/MOVZ instructions detection */
12 #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
13 defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
14 defined(_MIPS_ARCH_MIPS4)
15 #define use_movnz_instructions 1
16 #else
17 extern bool use_movnz_instructions;
18 #endif
19
20 /* MIPS32 instruction set detection */
21 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
22 #define use_mips32_instructions 1
23 #else
24 extern bool use_mips32_instructions;
25 #endif
26
27 /* MIPS32R2 instruction set detection */
28 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
29 #define use_mips32r2_instructions 1
30 #else
31 extern bool use_mips32r2_instructions;
32 #endif
33
34 /* MIPS32R6 instruction set detection */
35 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
36 #define use_mips32r6_instructions 1
37 #else
38 #define use_mips32r6_instructions 0
39 #endif
40
41 /* optional instructions */
42 #define TCG_TARGET_HAS_div_i32 1
43 #define TCG_TARGET_HAS_rem_i32 1
44 #define TCG_TARGET_HAS_not_i32 1
45 #define TCG_TARGET_HAS_nor_i32 1
46 #define TCG_TARGET_HAS_andc_i32 0
47 #define TCG_TARGET_HAS_orc_i32 0
48 #define TCG_TARGET_HAS_eqv_i32 0
49 #define TCG_TARGET_HAS_nand_i32 0
50 #define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions)
51 #define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
52 #define TCG_TARGET_HAS_muluh_i32 1
53 #define TCG_TARGET_HAS_mulsh_i32 1
54 #define TCG_TARGET_HAS_bswap16_i32 1
55 #define TCG_TARGET_HAS_bswap32_i32 1
56 #define TCG_TARGET_HAS_negsetcond_i32 0
57
58 #if TCG_TARGET_REG_BITS == 64
59 #define TCG_TARGET_HAS_add2_i32 0
60 #define TCG_TARGET_HAS_sub2_i32 0
61 #define TCG_TARGET_HAS_extr_i64_i32 1
62 #define TCG_TARGET_HAS_div_i64 1
63 #define TCG_TARGET_HAS_rem_i64 1
64 #define TCG_TARGET_HAS_not_i64 1
65 #define TCG_TARGET_HAS_nor_i64 1
66 #define TCG_TARGET_HAS_andc_i64 0
67 #define TCG_TARGET_HAS_orc_i64 0
68 #define TCG_TARGET_HAS_eqv_i64 0
69 #define TCG_TARGET_HAS_nand_i64 0
70 #define TCG_TARGET_HAS_add2_i64 0
71 #define TCG_TARGET_HAS_sub2_i64 0
72 #define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)
73 #define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions)
74 #define TCG_TARGET_HAS_muluh_i64 1
75 #define TCG_TARGET_HAS_mulsh_i64 1
76 #define TCG_TARGET_HAS_ext32s_i64 1
77 #define TCG_TARGET_HAS_ext32u_i64 1
78 #define TCG_TARGET_HAS_negsetcond_i64 0
79 #endif
80
81 /* optional instructions detected at runtime */
82 #define TCG_TARGET_HAS_extract2_i32 0
83 #define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
84 #define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
85 #define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
86 #define TCG_TARGET_HAS_clz_i32 use_mips32r2_instructions
87 #define TCG_TARGET_HAS_ctz_i32 0
88 #define TCG_TARGET_HAS_ctpop_i32 0
89 #define TCG_TARGET_HAS_qemu_st8_i32 0
90
91 #if TCG_TARGET_REG_BITS == 64
92 #define TCG_TARGET_HAS_bswap16_i64 1
93 #define TCG_TARGET_HAS_bswap32_i64 1
94 #define TCG_TARGET_HAS_bswap64_i64 1
95 #define TCG_TARGET_HAS_extract2_i64 0
96 #define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
97 #define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
98 #define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
99 #define TCG_TARGET_HAS_clz_i64 use_mips32r2_instructions
100 #define TCG_TARGET_HAS_ctz_i64 0
101 #define TCG_TARGET_HAS_ctpop_i64 0
102 #endif
103
104 /* optional instructions automatically implemented */
105 #define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
106 #define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
107
108 #if TCG_TARGET_REG_BITS == 64
109 #define TCG_TARGET_HAS_ext8u_i64 0 /* andi rt, rs, 0xff */
110 #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */
111 #endif
112
113 #define TCG_TARGET_HAS_qemu_ldst_i128 0
114 #define TCG_TARGET_HAS_tst 0
115
116 #define TCG_TARGET_extract_valid(type, ofs, len) use_mips32r2_instructions
117 #define TCG_TARGET_deposit_valid(type, ofs, len) use_mips32r2_instructions
118
119 static inline bool
tcg_target_sextract_valid(TCGType type,unsigned ofs,unsigned len)120 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
121 {
122 if (ofs == 0) {
123 switch (len) {
124 case 8:
125 case 16:
126 return use_mips32r2_instructions;
127 case 32:
128 return type == TCG_TYPE_I64;
129 }
130 }
131 return false;
132 }
133 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid
134
135 #endif
136