xref: /openbmc/qemu/tcg/mips/tcg-target-has.h (revision a363e1e179445102d7940e92d394d6c00c126f13)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Define target-specific opcode support
4  * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5  * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6  */
7 
8 #ifndef TCG_TARGET_HAS_H
9 #define TCG_TARGET_HAS_H
10 
11 /* MOVN/MOVZ instructions detection */
12 #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
13     defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
14     defined(_MIPS_ARCH_MIPS4)
15 #define use_movnz_instructions  1
16 #else
17 extern bool use_movnz_instructions;
18 #endif
19 
20 /* MIPS32 instruction set detection */
21 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
22 #define use_mips32_instructions  1
23 #else
24 extern bool use_mips32_instructions;
25 #endif
26 
27 /* MIPS32R2 instruction set detection */
28 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
29 #define use_mips32r2_instructions  1
30 #else
31 extern bool use_mips32r2_instructions;
32 #endif
33 
34 /* MIPS32R6 instruction set detection */
35 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
36 #define use_mips32r6_instructions  1
37 #else
38 #define use_mips32r6_instructions  0
39 #endif
40 
41 /* optional instructions */
42 #define TCG_TARGET_HAS_bswap16_i32      1
43 #define TCG_TARGET_HAS_bswap32_i32      1
44 
45 #if TCG_TARGET_REG_BITS == 64
46 #define TCG_TARGET_HAS_add2_i32         0
47 #define TCG_TARGET_HAS_sub2_i32         0
48 #define TCG_TARGET_HAS_extr_i64_i32     1
49 #define TCG_TARGET_HAS_add2_i64         0
50 #define TCG_TARGET_HAS_sub2_i64         0
51 #define TCG_TARGET_HAS_ext32s_i64       1
52 #define TCG_TARGET_HAS_ext32u_i64       1
53 #endif
54 
55 /* optional instructions detected at runtime */
56 #define TCG_TARGET_HAS_extract2_i32     0
57 #define TCG_TARGET_HAS_qemu_st8_i32     0
58 
59 #if TCG_TARGET_REG_BITS == 64
60 #define TCG_TARGET_HAS_bswap16_i64      1
61 #define TCG_TARGET_HAS_bswap32_i64      1
62 #define TCG_TARGET_HAS_bswap64_i64      1
63 #define TCG_TARGET_HAS_extract2_i64     0
64 #endif
65 
66 #define TCG_TARGET_HAS_qemu_ldst_i128   0
67 #define TCG_TARGET_HAS_tst              0
68 
69 #define TCG_TARGET_extract_valid(type, ofs, len)  use_mips32r2_instructions
70 #define TCG_TARGET_deposit_valid(type, ofs, len)  use_mips32r2_instructions
71 
72 static inline bool
73 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
74 {
75     if (ofs == 0) {
76         switch (len) {
77         case 8:
78         case 16:
79             return use_mips32r2_instructions;
80         case 32:
81             return type == TCG_TYPE_I64;
82         }
83     }
84     return false;
85 }
86 #define TCG_TARGET_sextract_valid  tcg_target_sextract_valid
87 
88 #endif
89