xref: /openbmc/qemu/tcg/i386/tcg-target-has.h (revision bfe964809bf6ce951b2e674929d7b730c754e298)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Define target-specific opcode support
4  * Copyright (c) 2008 Fabrice Bellard
5  */
6 
7 #ifndef TCG_TARGET_HAS_H
8 #define TCG_TARGET_HAS_H
9 
10 #include "host/cpuinfo.h"
11 
12 #define have_bmi1         (cpuinfo & CPUINFO_BMI1)
13 #define have_popcnt       (cpuinfo & CPUINFO_POPCNT)
14 #define have_avx1         (cpuinfo & CPUINFO_AVX1)
15 #define have_avx2         (cpuinfo & CPUINFO_AVX2)
16 #define have_movbe        (cpuinfo & CPUINFO_MOVBE)
17 
18 /*
19  * There are interesting instructions in AVX512, so long as we have AVX512VL,
20  * which indicates support for EVEX on sizes smaller than 512 bits.
21  */
22 #define have_avx512vl     ((cpuinfo & CPUINFO_AVX512VL) && \
23                            (cpuinfo & CPUINFO_AVX512F))
24 #define have_avx512bw     ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl)
25 #define have_avx512dq     ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl)
26 #define have_avx512vbmi2  ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl)
27 
28 /* optional instructions */
29 #define TCG_TARGET_HAS_bswap16_i32      1
30 #define TCG_TARGET_HAS_bswap32_i32      1
31 #define TCG_TARGET_HAS_extract2_i32     1
32 #define TCG_TARGET_HAS_negsetcond_i32   1
33 #define TCG_TARGET_HAS_add2_i32         1
34 #define TCG_TARGET_HAS_sub2_i32         1
35 #define TCG_TARGET_HAS_mulu2_i32        1
36 
37 #if TCG_TARGET_REG_BITS == 64
38 /* Keep 32-bit values zero-extended in a register.  */
39 #define TCG_TARGET_HAS_extr_i64_i32     1
40 #define TCG_TARGET_HAS_bswap16_i64      1
41 #define TCG_TARGET_HAS_bswap32_i64      1
42 #define TCG_TARGET_HAS_bswap64_i64      1
43 #define TCG_TARGET_HAS_extract2_i64     1
44 #define TCG_TARGET_HAS_negsetcond_i64   1
45 #define TCG_TARGET_HAS_add2_i64         1
46 #define TCG_TARGET_HAS_sub2_i64         1
47 #define TCG_TARGET_HAS_mulu2_i64        1
48 #define TCG_TARGET_HAS_qemu_st8_i32     0
49 #else
50 #define TCG_TARGET_HAS_qemu_st8_i32     1
51 #endif
52 
53 #define TCG_TARGET_HAS_qemu_ldst_i128 \
54     (TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA))
55 
56 #define TCG_TARGET_HAS_tst              1
57 
58 /* We do not support older SSE systems, only beginning with AVX1.  */
59 #define TCG_TARGET_HAS_v64              have_avx1
60 #define TCG_TARGET_HAS_v128             have_avx1
61 #define TCG_TARGET_HAS_v256             have_avx2
62 
63 #define TCG_TARGET_HAS_andc_vec         1
64 #define TCG_TARGET_HAS_orc_vec          have_avx512vl
65 #define TCG_TARGET_HAS_nand_vec         have_avx512vl
66 #define TCG_TARGET_HAS_nor_vec          have_avx512vl
67 #define TCG_TARGET_HAS_eqv_vec          have_avx512vl
68 #define TCG_TARGET_HAS_not_vec          have_avx512vl
69 #define TCG_TARGET_HAS_neg_vec          0
70 #define TCG_TARGET_HAS_abs_vec          1
71 #define TCG_TARGET_HAS_roti_vec         have_avx512vl
72 #define TCG_TARGET_HAS_rots_vec         0
73 #define TCG_TARGET_HAS_rotv_vec         have_avx512vl
74 #define TCG_TARGET_HAS_shi_vec          1
75 #define TCG_TARGET_HAS_shs_vec          1
76 #define TCG_TARGET_HAS_shv_vec          have_avx2
77 #define TCG_TARGET_HAS_mul_vec          1
78 #define TCG_TARGET_HAS_sat_vec          1
79 #define TCG_TARGET_HAS_minmax_vec       1
80 #define TCG_TARGET_HAS_bitsel_vec       have_avx512vl
81 #define TCG_TARGET_HAS_cmpsel_vec       1
82 #define TCG_TARGET_HAS_tst_vec          have_avx512bw
83 
84 #define TCG_TARGET_deposit_valid(type, ofs, len) \
85     (((ofs) == 0 && ((len) == 8 || (len) == 16)) || \
86      (TCG_TARGET_REG_BITS == 32 && (ofs) == 8 && (len) == 8))
87 
88 /*
89  * Check for the possibility of low byte/word extraction, high-byte extraction
90  * and zero-extending 32-bit right-shift.
91  *
92  * We cannot sign-extend from high byte to 64-bits without using the
93  * REX prefix that explicitly excludes access to the high-byte registers.
94  */
95 static inline bool
96 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
97 {
98     switch (ofs) {
99     case 0:
100         switch (len) {
101         case 8:
102         case 16:
103             return true;
104         case 32:
105             return type == TCG_TYPE_I64;
106         }
107         return false;
108     case 8:
109         return len == 8 && type == TCG_TYPE_I32;
110     }
111     return false;
112 }
113 #define TCG_TARGET_sextract_valid  tcg_target_sextract_valid
114 
115 static inline bool
116 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
117 {
118     if (type == TCG_TYPE_I64 && ofs + len == 32) {
119         return true;
120     }
121     switch (ofs) {
122     case 0:
123         return len == 8 || len == 16;
124     case 8:
125         return len == 8;
126     }
127     return false;
128 }
129 #define TCG_TARGET_extract_valid  tcg_target_extract_valid
130 
131 #endif
132