1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define target-specific opcode support
4 * Copyright (c) 2008 Fabrice Bellard
5 */
6
7 #ifndef TCG_TARGET_HAS_H
8 #define TCG_TARGET_HAS_H
9
10 #include "host/cpuinfo.h"
11
12 #define have_bmi1 (cpuinfo & CPUINFO_BMI1)
13 #define have_popcnt (cpuinfo & CPUINFO_POPCNT)
14 #define have_avx1 (cpuinfo & CPUINFO_AVX1)
15 #define have_avx2 (cpuinfo & CPUINFO_AVX2)
16 #define have_movbe (cpuinfo & CPUINFO_MOVBE)
17
18 /*
19 * There are interesting instructions in AVX512, so long as we have AVX512VL,
20 * which indicates support for EVEX on sizes smaller than 512 bits.
21 */
22 #define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \
23 (cpuinfo & CPUINFO_AVX512F))
24 #define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl)
25 #define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl)
26 #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl)
27
28 /* optional instructions */
29 #define TCG_TARGET_HAS_div2_i32 1
30 #define TCG_TARGET_HAS_rot_i32 1
31 #define TCG_TARGET_HAS_ext8s_i32 1
32 #define TCG_TARGET_HAS_ext16s_i32 1
33 #define TCG_TARGET_HAS_ext8u_i32 1
34 #define TCG_TARGET_HAS_ext16u_i32 1
35 #define TCG_TARGET_HAS_bswap16_i32 1
36 #define TCG_TARGET_HAS_bswap32_i32 1
37 #define TCG_TARGET_HAS_not_i32 1
38 #define TCG_TARGET_HAS_andc_i32 have_bmi1
39 #define TCG_TARGET_HAS_orc_i32 0
40 #define TCG_TARGET_HAS_eqv_i32 0
41 #define TCG_TARGET_HAS_nand_i32 0
42 #define TCG_TARGET_HAS_nor_i32 0
43 #define TCG_TARGET_HAS_clz_i32 1
44 #define TCG_TARGET_HAS_ctz_i32 1
45 #define TCG_TARGET_HAS_ctpop_i32 have_popcnt
46 #define TCG_TARGET_HAS_extract2_i32 1
47 #define TCG_TARGET_HAS_negsetcond_i32 1
48 #define TCG_TARGET_HAS_add2_i32 1
49 #define TCG_TARGET_HAS_sub2_i32 1
50 #define TCG_TARGET_HAS_mulu2_i32 1
51 #define TCG_TARGET_HAS_muls2_i32 1
52 #define TCG_TARGET_HAS_muluh_i32 0
53 #define TCG_TARGET_HAS_mulsh_i32 0
54
55 #if TCG_TARGET_REG_BITS == 64
56 /* Keep 32-bit values zero-extended in a register. */
57 #define TCG_TARGET_HAS_extr_i64_i32 1
58 #define TCG_TARGET_HAS_div2_i64 1
59 #define TCG_TARGET_HAS_rot_i64 1
60 #define TCG_TARGET_HAS_ext8s_i64 1
61 #define TCG_TARGET_HAS_ext16s_i64 1
62 #define TCG_TARGET_HAS_ext32s_i64 1
63 #define TCG_TARGET_HAS_ext8u_i64 1
64 #define TCG_TARGET_HAS_ext16u_i64 1
65 #define TCG_TARGET_HAS_ext32u_i64 1
66 #define TCG_TARGET_HAS_bswap16_i64 1
67 #define TCG_TARGET_HAS_bswap32_i64 1
68 #define TCG_TARGET_HAS_bswap64_i64 1
69 #define TCG_TARGET_HAS_not_i64 1
70 #define TCG_TARGET_HAS_andc_i64 have_bmi1
71 #define TCG_TARGET_HAS_orc_i64 0
72 #define TCG_TARGET_HAS_eqv_i64 0
73 #define TCG_TARGET_HAS_nand_i64 0
74 #define TCG_TARGET_HAS_nor_i64 0
75 #define TCG_TARGET_HAS_clz_i64 1
76 #define TCG_TARGET_HAS_ctz_i64 1
77 #define TCG_TARGET_HAS_ctpop_i64 have_popcnt
78 #define TCG_TARGET_HAS_extract2_i64 1
79 #define TCG_TARGET_HAS_negsetcond_i64 1
80 #define TCG_TARGET_HAS_add2_i64 1
81 #define TCG_TARGET_HAS_sub2_i64 1
82 #define TCG_TARGET_HAS_mulu2_i64 1
83 #define TCG_TARGET_HAS_muls2_i64 1
84 #define TCG_TARGET_HAS_muluh_i64 0
85 #define TCG_TARGET_HAS_mulsh_i64 0
86 #define TCG_TARGET_HAS_qemu_st8_i32 0
87 #else
88 #define TCG_TARGET_HAS_qemu_st8_i32 1
89 #endif
90
91 #define TCG_TARGET_HAS_qemu_ldst_i128 \
92 (TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA))
93
94 #define TCG_TARGET_HAS_tst 1
95
96 /* We do not support older SSE systems, only beginning with AVX1. */
97 #define TCG_TARGET_HAS_v64 have_avx1
98 #define TCG_TARGET_HAS_v128 have_avx1
99 #define TCG_TARGET_HAS_v256 have_avx2
100
101 #define TCG_TARGET_HAS_andc_vec 1
102 #define TCG_TARGET_HAS_orc_vec have_avx512vl
103 #define TCG_TARGET_HAS_nand_vec have_avx512vl
104 #define TCG_TARGET_HAS_nor_vec have_avx512vl
105 #define TCG_TARGET_HAS_eqv_vec have_avx512vl
106 #define TCG_TARGET_HAS_not_vec have_avx512vl
107 #define TCG_TARGET_HAS_neg_vec 0
108 #define TCG_TARGET_HAS_abs_vec 1
109 #define TCG_TARGET_HAS_roti_vec have_avx512vl
110 #define TCG_TARGET_HAS_rots_vec 0
111 #define TCG_TARGET_HAS_rotv_vec have_avx512vl
112 #define TCG_TARGET_HAS_shi_vec 1
113 #define TCG_TARGET_HAS_shs_vec 1
114 #define TCG_TARGET_HAS_shv_vec have_avx2
115 #define TCG_TARGET_HAS_mul_vec 1
116 #define TCG_TARGET_HAS_sat_vec 1
117 #define TCG_TARGET_HAS_minmax_vec 1
118 #define TCG_TARGET_HAS_bitsel_vec have_avx512vl
119 #define TCG_TARGET_HAS_cmpsel_vec 1
120 #define TCG_TARGET_HAS_tst_vec have_avx512bw
121
122 #define TCG_TARGET_deposit_valid(type, ofs, len) \
123 (((ofs) == 0 && ((len) == 8 || (len) == 16)) || \
124 (TCG_TARGET_REG_BITS == 32 && (ofs) == 8 && (len) == 8))
125
126 /*
127 * Check for the possibility of low byte/word extraction, high-byte extraction
128 * and zero-extending 32-bit right-shift.
129 *
130 * We cannot sign-extend from high byte to 64-bits without using the
131 * REX prefix that explicitly excludes access to the high-byte registers.
132 */
133 static inline bool
tcg_target_sextract_valid(TCGType type,unsigned ofs,unsigned len)134 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
135 {
136 switch (ofs) {
137 case 0:
138 switch (len) {
139 case 8:
140 case 16:
141 return true;
142 case 32:
143 return type == TCG_TYPE_I64;
144 }
145 return false;
146 case 8:
147 return len == 8 && type == TCG_TYPE_I32;
148 }
149 return false;
150 }
151 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid
152
153 static inline bool
tcg_target_extract_valid(TCGType type,unsigned ofs,unsigned len)154 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
155 {
156 if (type == TCG_TYPE_I64 && ofs + len == 32) {
157 return true;
158 }
159 switch (ofs) {
160 case 0:
161 return len == 8 || len == 16;
162 case 8:
163 return len == 8;
164 }
165 return false;
166 }
167 #define TCG_TARGET_extract_valid tcg_target_extract_valid
168
169 #endif
170