1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2008 Fabrice Bellard 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 #define have_bmi1 (cpuinfo & CPUINFO_BMI1) 13 #define have_popcnt (cpuinfo & CPUINFO_POPCNT) 14 #define have_avx1 (cpuinfo & CPUINFO_AVX1) 15 #define have_avx2 (cpuinfo & CPUINFO_AVX2) 16 #define have_movbe (cpuinfo & CPUINFO_MOVBE) 17 18 /* 19 * There are interesting instructions in AVX512, so long as we have AVX512VL, 20 * which indicates support for EVEX on sizes smaller than 512 bits. 21 */ 22 #define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \ 23 (cpuinfo & CPUINFO_AVX512F)) 24 #define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl) 25 #define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl) 26 #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl) 27 28 /* optional instructions */ 29 #define TCG_TARGET_HAS_bswap16_i32 1 30 #define TCG_TARGET_HAS_bswap32_i32 1 31 #define TCG_TARGET_HAS_extract2_i32 1 32 #define TCG_TARGET_HAS_add2_i32 1 33 #define TCG_TARGET_HAS_sub2_i32 1 34 35 #if TCG_TARGET_REG_BITS == 64 36 /* Keep 32-bit values zero-extended in a register. */ 37 #define TCG_TARGET_HAS_extr_i64_i32 1 38 #define TCG_TARGET_HAS_bswap16_i64 1 39 #define TCG_TARGET_HAS_bswap32_i64 1 40 #define TCG_TARGET_HAS_bswap64_i64 1 41 #define TCG_TARGET_HAS_extract2_i64 1 42 #define TCG_TARGET_HAS_add2_i64 1 43 #define TCG_TARGET_HAS_sub2_i64 1 44 #define TCG_TARGET_HAS_qemu_st8_i32 0 45 #else 46 #define TCG_TARGET_HAS_qemu_st8_i32 1 47 #endif 48 49 #define TCG_TARGET_HAS_qemu_ldst_i128 \ 50 (TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA)) 51 52 #define TCG_TARGET_HAS_tst 1 53 54 /* We do not support older SSE systems, only beginning with AVX1. */ 55 #define TCG_TARGET_HAS_v64 have_avx1 56 #define TCG_TARGET_HAS_v128 have_avx1 57 #define TCG_TARGET_HAS_v256 have_avx2 58 59 #define TCG_TARGET_HAS_andc_vec 1 60 #define TCG_TARGET_HAS_orc_vec have_avx512vl 61 #define TCG_TARGET_HAS_nand_vec have_avx512vl 62 #define TCG_TARGET_HAS_nor_vec have_avx512vl 63 #define TCG_TARGET_HAS_eqv_vec have_avx512vl 64 #define TCG_TARGET_HAS_not_vec have_avx512vl 65 #define TCG_TARGET_HAS_neg_vec 0 66 #define TCG_TARGET_HAS_abs_vec 1 67 #define TCG_TARGET_HAS_roti_vec have_avx512vl 68 #define TCG_TARGET_HAS_rots_vec 0 69 #define TCG_TARGET_HAS_rotv_vec have_avx512vl 70 #define TCG_TARGET_HAS_shi_vec 1 71 #define TCG_TARGET_HAS_shs_vec 1 72 #define TCG_TARGET_HAS_shv_vec have_avx2 73 #define TCG_TARGET_HAS_mul_vec 1 74 #define TCG_TARGET_HAS_sat_vec 1 75 #define TCG_TARGET_HAS_minmax_vec 1 76 #define TCG_TARGET_HAS_bitsel_vec have_avx512vl 77 #define TCG_TARGET_HAS_cmpsel_vec 1 78 #define TCG_TARGET_HAS_tst_vec have_avx512bw 79 80 #define TCG_TARGET_deposit_valid(type, ofs, len) \ 81 (((ofs) == 0 && ((len) == 8 || (len) == 16)) || \ 82 (TCG_TARGET_REG_BITS == 32 && (ofs) == 8 && (len) == 8)) 83 84 /* 85 * Check for the possibility of low byte/word extraction, high-byte extraction 86 * and zero-extending 32-bit right-shift. 87 * 88 * We cannot sign-extend from high byte to 64-bits without using the 89 * REX prefix that explicitly excludes access to the high-byte registers. 90 */ 91 static inline bool 92 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 93 { 94 switch (ofs) { 95 case 0: 96 switch (len) { 97 case 8: 98 case 16: 99 return true; 100 case 32: 101 return type == TCG_TYPE_I64; 102 } 103 return false; 104 case 8: 105 return len == 8 && type == TCG_TYPE_I32; 106 } 107 return false; 108 } 109 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 110 111 static inline bool 112 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) 113 { 114 if (type == TCG_TYPE_I64 && ofs + len == 32) { 115 return true; 116 } 117 switch (ofs) { 118 case 0: 119 return len == 8 || len == 16; 120 case 8: 121 return len == 8; 122 } 123 return false; 124 } 125 #define TCG_TARGET_extract_valid tcg_target_extract_valid 126 127 #endif 128