1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2008 Fabrice Bellard 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 #define have_bmi1 (cpuinfo & CPUINFO_BMI1) 13 #define have_popcnt (cpuinfo & CPUINFO_POPCNT) 14 #define have_avx1 (cpuinfo & CPUINFO_AVX1) 15 #define have_avx2 (cpuinfo & CPUINFO_AVX2) 16 #define have_movbe (cpuinfo & CPUINFO_MOVBE) 17 18 /* 19 * There are interesting instructions in AVX512, so long as we have AVX512VL, 20 * which indicates support for EVEX on sizes smaller than 512 bits. 21 */ 22 #define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \ 23 (cpuinfo & CPUINFO_AVX512F)) 24 #define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl) 25 #define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl) 26 #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl) 27 28 /* optional instructions */ 29 #define TCG_TARGET_HAS_add2_i32 1 30 #define TCG_TARGET_HAS_sub2_i32 1 31 32 #if TCG_TARGET_REG_BITS == 64 33 /* Keep 32-bit values zero-extended in a register. */ 34 #define TCG_TARGET_HAS_extr_i64_i32 1 35 #define TCG_TARGET_HAS_add2_i64 1 36 #define TCG_TARGET_HAS_sub2_i64 1 37 #define TCG_TARGET_HAS_qemu_st8_i32 0 38 #else 39 #define TCG_TARGET_HAS_qemu_st8_i32 1 40 #endif 41 42 #define TCG_TARGET_HAS_qemu_ldst_i128 \ 43 (TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA)) 44 45 #define TCG_TARGET_HAS_tst 1 46 47 /* We do not support older SSE systems, only beginning with AVX1. */ 48 #define TCG_TARGET_HAS_v64 have_avx1 49 #define TCG_TARGET_HAS_v128 have_avx1 50 #define TCG_TARGET_HAS_v256 have_avx2 51 52 #define TCG_TARGET_HAS_andc_vec 1 53 #define TCG_TARGET_HAS_orc_vec have_avx512vl 54 #define TCG_TARGET_HAS_nand_vec have_avx512vl 55 #define TCG_TARGET_HAS_nor_vec have_avx512vl 56 #define TCG_TARGET_HAS_eqv_vec have_avx512vl 57 #define TCG_TARGET_HAS_not_vec have_avx512vl 58 #define TCG_TARGET_HAS_neg_vec 0 59 #define TCG_TARGET_HAS_abs_vec 1 60 #define TCG_TARGET_HAS_roti_vec have_avx512vl 61 #define TCG_TARGET_HAS_rots_vec 0 62 #define TCG_TARGET_HAS_rotv_vec have_avx512vl 63 #define TCG_TARGET_HAS_shi_vec 1 64 #define TCG_TARGET_HAS_shs_vec 1 65 #define TCG_TARGET_HAS_shv_vec have_avx2 66 #define TCG_TARGET_HAS_mul_vec 1 67 #define TCG_TARGET_HAS_sat_vec 1 68 #define TCG_TARGET_HAS_minmax_vec 1 69 #define TCG_TARGET_HAS_bitsel_vec have_avx512vl 70 #define TCG_TARGET_HAS_cmpsel_vec 1 71 #define TCG_TARGET_HAS_tst_vec have_avx512bw 72 73 #define TCG_TARGET_deposit_valid(type, ofs, len) \ 74 (((ofs) == 0 && ((len) == 8 || (len) == 16)) || \ 75 (TCG_TARGET_REG_BITS == 32 && (ofs) == 8 && (len) == 8)) 76 77 /* 78 * Check for the possibility of low byte/word extraction, high-byte extraction 79 * and zero-extending 32-bit right-shift. 80 * 81 * We cannot sign-extend from high byte to 64-bits without using the 82 * REX prefix that explicitly excludes access to the high-byte registers. 83 */ 84 static inline bool 85 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 86 { 87 switch (ofs) { 88 case 0: 89 switch (len) { 90 case 8: 91 case 16: 92 return true; 93 case 32: 94 return type == TCG_TYPE_I64; 95 } 96 return false; 97 case 8: 98 return len == 8 && type == TCG_TYPE_I32; 99 } 100 return false; 101 } 102 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 103 104 static inline bool 105 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) 106 { 107 if (type == TCG_TYPE_I64 && ofs + len == 32) { 108 return true; 109 } 110 switch (ofs) { 111 case 0: 112 return len == 8 || len == 16; 113 case 8: 114 return len == 8; 115 } 116 return false; 117 } 118 #define TCG_TARGET_extract_valid tcg_target_extract_valid 119 120 #endif 121