1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #define XTREG(idx, ofs, bi, sz, al, no, fl, cp, typ, grp, name, \ 29 a1, a2, a3, a4, a5, a6) { \ 30 .targno = (no), \ 31 .flags = (fl), \ 32 .type = (typ), \ 33 .group = (grp), \ 34 .size = (sz), \ 35 }, 36 #define XTREG_END { .targno = -1 }, 37 38 #ifndef XCHAL_HAVE_DEPBITS 39 #define XCHAL_HAVE_DEPBITS 0 40 #endif 41 42 #ifndef XCHAL_HAVE_DIV32 43 #define XCHAL_HAVE_DIV32 0 44 #endif 45 46 #ifndef XCHAL_UNALIGNED_LOAD_HW 47 #define XCHAL_UNALIGNED_LOAD_HW 0 48 #endif 49 50 #ifndef XCHAL_HAVE_VECBASE 51 #define XCHAL_HAVE_VECBASE 0 52 #define XCHAL_VECBASE_RESET_VADDR 0 53 #endif 54 55 #ifndef XCHAL_RESET_VECTOR0_VADDR 56 #define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR 57 #endif 58 59 #ifndef XCHAL_RESET_VECTOR1_VADDR 60 #define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR 61 #endif 62 63 #ifndef XCHAL_HW_MIN_VERSION 64 #define XCHAL_HW_MIN_VERSION 0 65 #endif 66 67 #ifndef XCHAL_LOOP_BUFFER_SIZE 68 #define XCHAL_LOOP_BUFFER_SIZE 0 69 #endif 70 71 #ifndef XCHAL_HAVE_EXTERN_REGS 72 #define XCHAL_HAVE_EXTERN_REGS 0 73 #endif 74 75 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0) 76 77 #define XTENSA_OPTIONS ( \ 78 XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \ 79 XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \ 80 XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \ 81 XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \ 82 XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \ 83 XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \ 84 XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \ 85 XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \ 86 XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \ 87 XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \ 88 XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \ 89 XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \ 90 XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \ 91 XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \ 92 XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \ 93 XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \ 94 XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \ 95 XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \ 96 XTENSA_OPTION_ATOMCTL) | \ 97 XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \ 98 /* Interrupts and exceptions */ \ 99 XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \ 100 XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \ 101 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \ 102 XTENSA_OPTION_UNALIGNED_EXCEPTION) | \ 103 XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \ 104 XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \ 105 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \ 106 XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \ 107 /* Local memory, TODO */ \ 108 XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \ 109 XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \ 110 XTENSA_OPTION_ICACHE_INDEX_LOCK) | \ 111 XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) | \ 112 XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \ 113 XTENSA_OPTION_DCACHE_INDEX_LOCK) | \ 114 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \ 115 /* Memory protection and translation */ \ 116 XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \ 117 XTENSA_OPTION_REGION_PROTECTION) | \ 118 XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \ 119 XTENSA_OPTION_REGION_TRANSLATION) | \ 120 XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \ 121 XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \ 122 /* Other, TODO */ \ 123 XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \ 124 XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\ 125 XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \ 126 XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \ 127 XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) | \ 128 XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS)) 129 130 #ifndef XCHAL_WINDOW_OF4_VECOFS 131 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 132 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 133 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 134 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 135 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 136 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 137 #endif 138 139 #if XCHAL_HAVE_WINDOWED 140 #define WINDOW_VECTORS \ 141 [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \ 142 XCHAL_WINDOW_VECTORS_VADDR, \ 143 [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \ 144 XCHAL_WINDOW_VECTORS_VADDR, \ 145 [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \ 146 XCHAL_WINDOW_VECTORS_VADDR, \ 147 [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \ 148 XCHAL_WINDOW_VECTORS_VADDR, \ 149 [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \ 150 XCHAL_WINDOW_VECTORS_VADDR, \ 151 [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \ 152 XCHAL_WINDOW_VECTORS_VADDR, 153 #else 154 #define WINDOW_VECTORS 155 #endif 156 157 #define EXCEPTION_VECTORS { \ 158 [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \ 159 [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \ 160 WINDOW_VECTORS \ 161 [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \ 162 [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \ 163 [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \ 164 [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \ 165 } 166 167 #define INTERRUPT_VECTORS { \ 168 0, \ 169 0, \ 170 XCHAL_INTLEVEL2_VECTOR_VADDR, \ 171 XCHAL_INTLEVEL3_VECTOR_VADDR, \ 172 XCHAL_INTLEVEL4_VECTOR_VADDR, \ 173 XCHAL_INTLEVEL5_VECTOR_VADDR, \ 174 XCHAL_INTLEVEL6_VECTOR_VADDR, \ 175 XCHAL_INTLEVEL7_VECTOR_VADDR, \ 176 } 177 178 #define LEVEL_MASKS { \ 179 [1] = XCHAL_INTLEVEL1_MASK, \ 180 [2] = XCHAL_INTLEVEL2_MASK, \ 181 [3] = XCHAL_INTLEVEL3_MASK, \ 182 [4] = XCHAL_INTLEVEL4_MASK, \ 183 [5] = XCHAL_INTLEVEL5_MASK, \ 184 [6] = XCHAL_INTLEVEL6_MASK, \ 185 [7] = XCHAL_INTLEVEL7_MASK, \ 186 } 187 188 #define INTTYPE_MASKS { \ 189 [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \ 190 [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \ 191 [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \ 192 } 193 194 #define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL 195 #define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE 196 #define XTHAL_INTTYPE_NMI INTTYPE_NMI 197 #define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE 198 #define XTHAL_INTTYPE_TIMER INTTYPE_TIMER 199 #define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG 200 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR 201 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR 202 #define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING 203 204 205 #define INTERRUPT(i) { \ 206 .level = XCHAL_INT ## i ## _LEVEL, \ 207 .inttype = XCHAL_INT ## i ## _TYPE, \ 208 } 209 210 #define INTERRUPTS { \ 211 [0] = INTERRUPT(0), \ 212 [1] = INTERRUPT(1), \ 213 [2] = INTERRUPT(2), \ 214 [3] = INTERRUPT(3), \ 215 [4] = INTERRUPT(4), \ 216 [5] = INTERRUPT(5), \ 217 [6] = INTERRUPT(6), \ 218 [7] = INTERRUPT(7), \ 219 [8] = INTERRUPT(8), \ 220 [9] = INTERRUPT(9), \ 221 [10] = INTERRUPT(10), \ 222 [11] = INTERRUPT(11), \ 223 [12] = INTERRUPT(12), \ 224 [13] = INTERRUPT(13), \ 225 [14] = INTERRUPT(14), \ 226 [15] = INTERRUPT(15), \ 227 [16] = INTERRUPT(16), \ 228 [17] = INTERRUPT(17), \ 229 [18] = INTERRUPT(18), \ 230 [19] = INTERRUPT(19), \ 231 [20] = INTERRUPT(20), \ 232 [21] = INTERRUPT(21), \ 233 [22] = INTERRUPT(22), \ 234 [23] = INTERRUPT(23), \ 235 [24] = INTERRUPT(24), \ 236 [25] = INTERRUPT(25), \ 237 [26] = INTERRUPT(26), \ 238 [27] = INTERRUPT(27), \ 239 [28] = INTERRUPT(28), \ 240 [29] = INTERRUPT(29), \ 241 [30] = INTERRUPT(30), \ 242 [31] = INTERRUPT(31), \ 243 } 244 245 #define TIMERINTS { \ 246 [0] = XCHAL_TIMER0_INTERRUPT, \ 247 [1] = XCHAL_TIMER1_INTERRUPT, \ 248 [2] = XCHAL_TIMER2_INTERRUPT, \ 249 } 250 251 #define EXTINTS { \ 252 [0] = XCHAL_EXTINT0_NUM, \ 253 [1] = XCHAL_EXTINT1_NUM, \ 254 [2] = XCHAL_EXTINT2_NUM, \ 255 [3] = XCHAL_EXTINT3_NUM, \ 256 [4] = XCHAL_EXTINT4_NUM, \ 257 [5] = XCHAL_EXTINT5_NUM, \ 258 [6] = XCHAL_EXTINT6_NUM, \ 259 [7] = XCHAL_EXTINT7_NUM, \ 260 [8] = XCHAL_EXTINT8_NUM, \ 261 [9] = XCHAL_EXTINT9_NUM, \ 262 [10] = XCHAL_EXTINT10_NUM, \ 263 [11] = XCHAL_EXTINT11_NUM, \ 264 [12] = XCHAL_EXTINT12_NUM, \ 265 [13] = XCHAL_EXTINT13_NUM, \ 266 [14] = XCHAL_EXTINT14_NUM, \ 267 [15] = XCHAL_EXTINT15_NUM, \ 268 [16] = XCHAL_EXTINT16_NUM, \ 269 [17] = XCHAL_EXTINT17_NUM, \ 270 [18] = XCHAL_EXTINT18_NUM, \ 271 [19] = XCHAL_EXTINT19_NUM, \ 272 [20] = XCHAL_EXTINT20_NUM, \ 273 [21] = XCHAL_EXTINT21_NUM, \ 274 [22] = XCHAL_EXTINT22_NUM, \ 275 [23] = XCHAL_EXTINT23_NUM, \ 276 [24] = XCHAL_EXTINT24_NUM, \ 277 [25] = XCHAL_EXTINT25_NUM, \ 278 [26] = XCHAL_EXTINT26_NUM, \ 279 [27] = XCHAL_EXTINT27_NUM, \ 280 [28] = XCHAL_EXTINT28_NUM, \ 281 [29] = XCHAL_EXTINT29_NUM, \ 282 [30] = XCHAL_EXTINT30_NUM, \ 283 [31] = XCHAL_EXTINT31_NUM, \ 284 } 285 286 #define EXCEPTIONS_SECTION \ 287 .excm_level = XCHAL_EXCM_LEVEL, \ 288 .vecbase = XCHAL_VECBASE_RESET_VADDR, \ 289 .exception_vector = EXCEPTION_VECTORS 290 291 #define INTERRUPTS_SECTION \ 292 .ninterrupt = XCHAL_NUM_INTERRUPTS, \ 293 .nlevel = XCHAL_NUM_INTLEVELS, \ 294 .interrupt_vector = INTERRUPT_VECTORS, \ 295 .level_mask = LEVEL_MASKS, \ 296 .inttype_mask = INTTYPE_MASKS, \ 297 .interrupt = INTERRUPTS, \ 298 .nccompare = XCHAL_NUM_TIMERS, \ 299 .timerint = TIMERINTS, \ 300 .nextint = XCHAL_NUM_EXTINTERRUPTS, \ 301 .extint = EXTINTS 302 303 #if XCHAL_HAVE_PTP_MMU 304 305 #define TLB_TEMPLATE(ways, refill_way_size, way56) { \ 306 .nways = ways, \ 307 .way_size = { \ 308 (refill_way_size), (refill_way_size), \ 309 (refill_way_size), (refill_way_size), \ 310 4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \ 311 }, \ 312 .varway56 = (way56), \ 313 .nrefillentries = (refill_way_size) * 4, \ 314 } 315 316 #define ITLB(varway56) \ 317 TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56) 318 319 #define DTLB(varway56) \ 320 TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56) 321 322 #define TLB_SECTION \ 323 .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \ 324 .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY) 325 326 #ifndef XCHAL_SYSROM0_PADDR 327 #define XCHAL_SYSROM0_PADDR 0xfe000000 328 #define XCHAL_SYSROM0_SIZE 0x02000000 329 #endif 330 331 #ifndef XCHAL_SYSRAM0_PADDR 332 #define XCHAL_SYSRAM0_PADDR 0x00000000 333 #define XCHAL_SYSRAM0_SIZE 0x08000000 334 #endif 335 336 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR 337 338 #define TLB_TEMPLATE { \ 339 .nways = 1, \ 340 .way_size = { \ 341 8, \ 342 } \ 343 } 344 345 #define TLB_SECTION \ 346 .itlb = TLB_TEMPLATE, \ 347 .dtlb = TLB_TEMPLATE 348 349 #ifndef XCHAL_SYSROM0_PADDR 350 #define XCHAL_SYSROM0_PADDR 0x50000000 351 #define XCHAL_SYSROM0_SIZE 0x04000000 352 #endif 353 354 #ifndef XCHAL_SYSRAM0_PADDR 355 #define XCHAL_SYSRAM0_PADDR 0x60000000 356 #define XCHAL_SYSRAM0_SIZE 0x04000000 357 #endif 358 359 #else 360 361 #ifndef XCHAL_SYSROM0_PADDR 362 #define XCHAL_SYSROM0_PADDR 0x50000000 363 #define XCHAL_SYSROM0_SIZE 0x04000000 364 #endif 365 366 #ifndef XCHAL_SYSRAM0_PADDR 367 #define XCHAL_SYSRAM0_PADDR 0x60000000 368 #define XCHAL_SYSRAM0_SIZE 0x04000000 369 #endif 370 371 #endif 372 373 #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0) 374 #define REGISTER_CORE(core) \ 375 static void __attribute__((constructor)) register_core(void) \ 376 { \ 377 static XtensaConfigList node = { \ 378 .config = &core, \ 379 }; \ 380 xtensa_register_core(&node); \ 381 } 382 #else 383 #define REGISTER_CORE(core) 384 #endif 385 386 #define DEBUG_SECTION \ 387 .debug_level = XCHAL_DEBUGLEVEL, \ 388 .nibreak = XCHAL_NUM_IBREAK, \ 389 .ndbreak = XCHAL_NUM_DBREAK 390 391 #define CACHE_SECTION \ 392 .icache_ways = XCHAL_ICACHE_WAYS, \ 393 .dcache_ways = XCHAL_DCACHE_WAYS, \ 394 .memctl_mask = \ 395 (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \ 396 (XCHAL_DCACHE_SIZE ? \ 397 MEMCTL_DALLOCWAYS_MASK | MEMCTL_DUSEWAYS_MASK : 0) | \ 398 MEMCTL_ISNP | MEMCTL_DSNP | \ 399 (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0) 400 401 #define MEM_LOCATION(name, n) \ 402 { \ 403 .addr = XCHAL_ ## name ## n ## _PADDR, \ 404 .size = XCHAL_ ## name ## n ## _SIZE, \ 405 } 406 407 #define MEM_SECTIONS(name) \ 408 MEM_LOCATION(name, 0), \ 409 MEM_LOCATION(name, 1), \ 410 MEM_LOCATION(name, 2), \ 411 MEM_LOCATION(name, 3) 412 413 #define MEM_SECTION(name) \ 414 .num = XCHAL_NUM_ ## name, \ 415 .location = { \ 416 MEM_SECTIONS(name) \ 417 } 418 419 #define SYSMEM_SECTION(name) \ 420 .num = 1, \ 421 .location = { \ 422 { \ 423 .addr = XCHAL_ ## name ## 0_PADDR, \ 424 .size = XCHAL_ ## name ## 0_SIZE, \ 425 } \ 426 } 427 428 #define LOCAL_MEMORIES_SECTION \ 429 .instrom = { \ 430 MEM_SECTION(INSTROM) \ 431 }, \ 432 .instram = { \ 433 MEM_SECTION(INSTRAM) \ 434 }, \ 435 .datarom = { \ 436 MEM_SECTION(DATAROM) \ 437 }, \ 438 .dataram = { \ 439 MEM_SECTION(DATARAM) \ 440 }, \ 441 .sysrom = { \ 442 SYSMEM_SECTION(SYSROM) \ 443 }, \ 444 .sysram = { \ 445 SYSMEM_SECTION(SYSRAM) \ 446 } 447 448 #define CONFIG_SECTION \ 449 .configid = { \ 450 XCHAL_HW_CONFIGID0, \ 451 XCHAL_HW_CONFIGID1, \ 452 } 453 454 #define DEFAULT_SECTIONS \ 455 .options = XTENSA_OPTIONS, \ 456 .nareg = XCHAL_NUM_AREGS, \ 457 .ndepc = (XCHAL_XEA_VERSION >= 2), \ 458 .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \ 459 .max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \ 460 EXCEPTIONS_SECTION, \ 461 INTERRUPTS_SECTION, \ 462 TLB_SECTION, \ 463 DEBUG_SECTION, \ 464 CACHE_SECTION, \ 465 LOCAL_MEMORIES_SECTION, \ 466 CONFIG_SECTION 467 468 469 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2 470 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0 471 #endif 472 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3 473 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0 474 #endif 475 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4 476 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0 477 #endif 478 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5 479 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0 480 #endif 481 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6 482 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0 483 #endif 484 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7 485 #define XCHAL_INTLEVEL7_VECTOR_VADDR 0 486 #endif 487 488 489 #if XCHAL_NUM_INTERRUPTS <= 0 490 #define XCHAL_INT0_LEVEL 0 491 #define XCHAL_INT0_TYPE 0 492 #endif 493 #if XCHAL_NUM_INTERRUPTS <= 1 494 #define XCHAL_INT1_LEVEL 0 495 #define XCHAL_INT1_TYPE 0 496 #endif 497 #if XCHAL_NUM_INTERRUPTS <= 2 498 #define XCHAL_INT2_LEVEL 0 499 #define XCHAL_INT2_TYPE 0 500 #endif 501 #if XCHAL_NUM_INTERRUPTS <= 3 502 #define XCHAL_INT3_LEVEL 0 503 #define XCHAL_INT3_TYPE 0 504 #endif 505 #if XCHAL_NUM_INTERRUPTS <= 4 506 #define XCHAL_INT4_LEVEL 0 507 #define XCHAL_INT4_TYPE 0 508 #endif 509 #if XCHAL_NUM_INTERRUPTS <= 5 510 #define XCHAL_INT5_LEVEL 0 511 #define XCHAL_INT5_TYPE 0 512 #endif 513 #if XCHAL_NUM_INTERRUPTS <= 6 514 #define XCHAL_INT6_LEVEL 0 515 #define XCHAL_INT6_TYPE 0 516 #endif 517 #if XCHAL_NUM_INTERRUPTS <= 7 518 #define XCHAL_INT7_LEVEL 0 519 #define XCHAL_INT7_TYPE 0 520 #endif 521 #if XCHAL_NUM_INTERRUPTS <= 8 522 #define XCHAL_INT8_LEVEL 0 523 #define XCHAL_INT8_TYPE 0 524 #endif 525 #if XCHAL_NUM_INTERRUPTS <= 9 526 #define XCHAL_INT9_LEVEL 0 527 #define XCHAL_INT9_TYPE 0 528 #endif 529 #if XCHAL_NUM_INTERRUPTS <= 10 530 #define XCHAL_INT10_LEVEL 0 531 #define XCHAL_INT10_TYPE 0 532 #endif 533 #if XCHAL_NUM_INTERRUPTS <= 11 534 #define XCHAL_INT11_LEVEL 0 535 #define XCHAL_INT11_TYPE 0 536 #endif 537 #if XCHAL_NUM_INTERRUPTS <= 12 538 #define XCHAL_INT12_LEVEL 0 539 #define XCHAL_INT12_TYPE 0 540 #endif 541 #if XCHAL_NUM_INTERRUPTS <= 13 542 #define XCHAL_INT13_LEVEL 0 543 #define XCHAL_INT13_TYPE 0 544 #endif 545 #if XCHAL_NUM_INTERRUPTS <= 14 546 #define XCHAL_INT14_LEVEL 0 547 #define XCHAL_INT14_TYPE 0 548 #endif 549 #if XCHAL_NUM_INTERRUPTS <= 15 550 #define XCHAL_INT15_LEVEL 0 551 #define XCHAL_INT15_TYPE 0 552 #endif 553 #if XCHAL_NUM_INTERRUPTS <= 16 554 #define XCHAL_INT16_LEVEL 0 555 #define XCHAL_INT16_TYPE 0 556 #endif 557 #if XCHAL_NUM_INTERRUPTS <= 17 558 #define XCHAL_INT17_LEVEL 0 559 #define XCHAL_INT17_TYPE 0 560 #endif 561 #if XCHAL_NUM_INTERRUPTS <= 18 562 #define XCHAL_INT18_LEVEL 0 563 #define XCHAL_INT18_TYPE 0 564 #endif 565 #if XCHAL_NUM_INTERRUPTS <= 19 566 #define XCHAL_INT19_LEVEL 0 567 #define XCHAL_INT19_TYPE 0 568 #endif 569 #if XCHAL_NUM_INTERRUPTS <= 20 570 #define XCHAL_INT20_LEVEL 0 571 #define XCHAL_INT20_TYPE 0 572 #endif 573 #if XCHAL_NUM_INTERRUPTS <= 21 574 #define XCHAL_INT21_LEVEL 0 575 #define XCHAL_INT21_TYPE 0 576 #endif 577 #if XCHAL_NUM_INTERRUPTS <= 22 578 #define XCHAL_INT22_LEVEL 0 579 #define XCHAL_INT22_TYPE 0 580 #endif 581 #if XCHAL_NUM_INTERRUPTS <= 23 582 #define XCHAL_INT23_LEVEL 0 583 #define XCHAL_INT23_TYPE 0 584 #endif 585 #if XCHAL_NUM_INTERRUPTS <= 24 586 #define XCHAL_INT24_LEVEL 0 587 #define XCHAL_INT24_TYPE 0 588 #endif 589 #if XCHAL_NUM_INTERRUPTS <= 25 590 #define XCHAL_INT25_LEVEL 0 591 #define XCHAL_INT25_TYPE 0 592 #endif 593 #if XCHAL_NUM_INTERRUPTS <= 26 594 #define XCHAL_INT26_LEVEL 0 595 #define XCHAL_INT26_TYPE 0 596 #endif 597 #if XCHAL_NUM_INTERRUPTS <= 27 598 #define XCHAL_INT27_LEVEL 0 599 #define XCHAL_INT27_TYPE 0 600 #endif 601 #if XCHAL_NUM_INTERRUPTS <= 28 602 #define XCHAL_INT28_LEVEL 0 603 #define XCHAL_INT28_TYPE 0 604 #endif 605 #if XCHAL_NUM_INTERRUPTS <= 29 606 #define XCHAL_INT29_LEVEL 0 607 #define XCHAL_INT29_TYPE 0 608 #endif 609 #if XCHAL_NUM_INTERRUPTS <= 30 610 #define XCHAL_INT30_LEVEL 0 611 #define XCHAL_INT30_TYPE 0 612 #endif 613 #if XCHAL_NUM_INTERRUPTS <= 31 614 #define XCHAL_INT31_LEVEL 0 615 #define XCHAL_INT31_TYPE 0 616 #endif 617 618 619 #if XCHAL_NUM_EXTINTERRUPTS <= 0 620 #define XCHAL_EXTINT0_NUM 0 621 #endif 622 #if XCHAL_NUM_EXTINTERRUPTS <= 1 623 #define XCHAL_EXTINT1_NUM 0 624 #endif 625 #if XCHAL_NUM_EXTINTERRUPTS <= 2 626 #define XCHAL_EXTINT2_NUM 0 627 #endif 628 #if XCHAL_NUM_EXTINTERRUPTS <= 3 629 #define XCHAL_EXTINT3_NUM 0 630 #endif 631 #if XCHAL_NUM_EXTINTERRUPTS <= 4 632 #define XCHAL_EXTINT4_NUM 0 633 #endif 634 #if XCHAL_NUM_EXTINTERRUPTS <= 5 635 #define XCHAL_EXTINT5_NUM 0 636 #endif 637 #if XCHAL_NUM_EXTINTERRUPTS <= 6 638 #define XCHAL_EXTINT6_NUM 0 639 #endif 640 #if XCHAL_NUM_EXTINTERRUPTS <= 7 641 #define XCHAL_EXTINT7_NUM 0 642 #endif 643 #if XCHAL_NUM_EXTINTERRUPTS <= 8 644 #define XCHAL_EXTINT8_NUM 0 645 #endif 646 #if XCHAL_NUM_EXTINTERRUPTS <= 9 647 #define XCHAL_EXTINT9_NUM 0 648 #endif 649 #if XCHAL_NUM_EXTINTERRUPTS <= 10 650 #define XCHAL_EXTINT10_NUM 0 651 #endif 652 #if XCHAL_NUM_EXTINTERRUPTS <= 11 653 #define XCHAL_EXTINT11_NUM 0 654 #endif 655 #if XCHAL_NUM_EXTINTERRUPTS <= 12 656 #define XCHAL_EXTINT12_NUM 0 657 #endif 658 #if XCHAL_NUM_EXTINTERRUPTS <= 13 659 #define XCHAL_EXTINT13_NUM 0 660 #endif 661 #if XCHAL_NUM_EXTINTERRUPTS <= 14 662 #define XCHAL_EXTINT14_NUM 0 663 #endif 664 #if XCHAL_NUM_EXTINTERRUPTS <= 15 665 #define XCHAL_EXTINT15_NUM 0 666 #endif 667 #if XCHAL_NUM_EXTINTERRUPTS <= 16 668 #define XCHAL_EXTINT16_NUM 0 669 #endif 670 #if XCHAL_NUM_EXTINTERRUPTS <= 17 671 #define XCHAL_EXTINT17_NUM 0 672 #endif 673 #if XCHAL_NUM_EXTINTERRUPTS <= 18 674 #define XCHAL_EXTINT18_NUM 0 675 #endif 676 #if XCHAL_NUM_EXTINTERRUPTS <= 19 677 #define XCHAL_EXTINT19_NUM 0 678 #endif 679 #if XCHAL_NUM_EXTINTERRUPTS <= 20 680 #define XCHAL_EXTINT20_NUM 0 681 #endif 682 #if XCHAL_NUM_EXTINTERRUPTS <= 21 683 #define XCHAL_EXTINT21_NUM 0 684 #endif 685 #if XCHAL_NUM_EXTINTERRUPTS <= 22 686 #define XCHAL_EXTINT22_NUM 0 687 #endif 688 #if XCHAL_NUM_EXTINTERRUPTS <= 23 689 #define XCHAL_EXTINT23_NUM 0 690 #endif 691 #if XCHAL_NUM_EXTINTERRUPTS <= 24 692 #define XCHAL_EXTINT24_NUM 0 693 #endif 694 #if XCHAL_NUM_EXTINTERRUPTS <= 25 695 #define XCHAL_EXTINT25_NUM 0 696 #endif 697 #if XCHAL_NUM_EXTINTERRUPTS <= 26 698 #define XCHAL_EXTINT26_NUM 0 699 #endif 700 #if XCHAL_NUM_EXTINTERRUPTS <= 27 701 #define XCHAL_EXTINT27_NUM 0 702 #endif 703 #if XCHAL_NUM_EXTINTERRUPTS <= 28 704 #define XCHAL_EXTINT28_NUM 0 705 #endif 706 #if XCHAL_NUM_EXTINTERRUPTS <= 29 707 #define XCHAL_EXTINT29_NUM 0 708 #endif 709 #if XCHAL_NUM_EXTINTERRUPTS <= 30 710 #define XCHAL_EXTINT30_NUM 0 711 #endif 712 #if XCHAL_NUM_EXTINTERRUPTS <= 31 713 #define XCHAL_EXTINT31_NUM 0 714 #endif 715 716 717 #define XTHAL_TIMER_UNCONFIGURED 0 718 719 #if XCHAL_NUM_INSTROM < 1 720 #define XCHAL_INSTROM0_PADDR 0 721 #define XCHAL_INSTROM0_SIZE 0 722 #endif 723 #if XCHAL_NUM_INSTROM < 2 724 #define XCHAL_INSTROM1_PADDR 0 725 #define XCHAL_INSTROM1_SIZE 0 726 #endif 727 #if XCHAL_NUM_INSTROM < 3 728 #define XCHAL_INSTROM2_PADDR 0 729 #define XCHAL_INSTROM2_SIZE 0 730 #endif 731 #if XCHAL_NUM_INSTROM < 4 732 #define XCHAL_INSTROM3_PADDR 0 733 #define XCHAL_INSTROM3_SIZE 0 734 #endif 735 #if XCHAL_NUM_INSTROM > MAX_NMEMORY 736 #error XCHAL_NUM_INSTROM > MAX_NMEMORY 737 #endif 738 739 #if XCHAL_NUM_INSTRAM < 1 740 #define XCHAL_INSTRAM0_PADDR 0 741 #define XCHAL_INSTRAM0_SIZE 0 742 #endif 743 #if XCHAL_NUM_INSTRAM < 2 744 #define XCHAL_INSTRAM1_PADDR 0 745 #define XCHAL_INSTRAM1_SIZE 0 746 #endif 747 #if XCHAL_NUM_INSTRAM < 3 748 #define XCHAL_INSTRAM2_PADDR 0 749 #define XCHAL_INSTRAM2_SIZE 0 750 #endif 751 #if XCHAL_NUM_INSTRAM < 4 752 #define XCHAL_INSTRAM3_PADDR 0 753 #define XCHAL_INSTRAM3_SIZE 0 754 #endif 755 #if XCHAL_NUM_INSTRAM > MAX_NMEMORY 756 #error XCHAL_NUM_INSTRAM > MAX_NMEMORY 757 #endif 758 759 #if XCHAL_NUM_DATAROM < 1 760 #define XCHAL_DATAROM0_PADDR 0 761 #define XCHAL_DATAROM0_SIZE 0 762 #endif 763 #if XCHAL_NUM_DATAROM < 2 764 #define XCHAL_DATAROM1_PADDR 0 765 #define XCHAL_DATAROM1_SIZE 0 766 #endif 767 #if XCHAL_NUM_DATAROM < 3 768 #define XCHAL_DATAROM2_PADDR 0 769 #define XCHAL_DATAROM2_SIZE 0 770 #endif 771 #if XCHAL_NUM_DATAROM < 4 772 #define XCHAL_DATAROM3_PADDR 0 773 #define XCHAL_DATAROM3_SIZE 0 774 #endif 775 #if XCHAL_NUM_DATAROM > MAX_NMEMORY 776 #error XCHAL_NUM_DATAROM > MAX_NMEMORY 777 #endif 778 779 #if XCHAL_NUM_DATARAM < 1 780 #define XCHAL_DATARAM0_PADDR 0 781 #define XCHAL_DATARAM0_SIZE 0 782 #endif 783 #if XCHAL_NUM_DATARAM < 2 784 #define XCHAL_DATARAM1_PADDR 0 785 #define XCHAL_DATARAM1_SIZE 0 786 #endif 787 #if XCHAL_NUM_DATARAM < 3 788 #define XCHAL_DATARAM2_PADDR 0 789 #define XCHAL_DATARAM2_SIZE 0 790 #endif 791 #if XCHAL_NUM_DATARAM < 4 792 #define XCHAL_DATARAM3_PADDR 0 793 #define XCHAL_DATARAM3_SIZE 0 794 #endif 795 #if XCHAL_NUM_DATARAM > MAX_NMEMORY 796 #error XCHAL_NUM_DATARAM > MAX_NMEMORY 797 #endif 798