1 /* 2 * RX translation 3 * 4 * Copyright (c) 2019 Yoshinori Sato 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/bswap.h" 21 #include "qemu/qemu-print.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "tcg/tcg-op.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 #include "exec/translator.h" 29 #include "exec/log.h" 30 31 typedef struct DisasContext { 32 DisasContextBase base; 33 CPURXState *env; 34 uint32_t pc; 35 uint32_t tb_flags; 36 } DisasContext; 37 38 typedef struct DisasCompare { 39 TCGv value; 40 TCGv temp; 41 TCGCond cond; 42 } DisasCompare; 43 44 const char *rx_crname(uint8_t cr) 45 { 46 static const char *cr_names[] = { 47 "psw", "pc", "usp", "fpsw", "", "", "", "", 48 "bpsw", "bpc", "isp", "fintv", "intb", "", "", "" 49 }; 50 if (cr >= ARRAY_SIZE(cr_names)) { 51 return "illegal"; 52 } 53 return cr_names[cr]; 54 } 55 56 /* Target-specific values for dc->base.is_jmp. */ 57 #define DISAS_JUMP DISAS_TARGET_0 58 #define DISAS_UPDATE DISAS_TARGET_1 59 #define DISAS_EXIT DISAS_TARGET_2 60 61 /* global register indexes */ 62 static TCGv cpu_regs[16]; 63 static TCGv cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c; 64 static TCGv cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl; 65 static TCGv cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp; 66 static TCGv cpu_fintv, cpu_intb, cpu_pc; 67 static TCGv_i64 cpu_acc; 68 69 #define cpu_sp cpu_regs[0] 70 71 #include "exec/gen-icount.h" 72 73 /* decoder helper */ 74 static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, 75 int i, int n) 76 { 77 while (++i <= n) { 78 uint8_t b = cpu_ldub_code(ctx->env, ctx->base.pc_next++); 79 insn |= b << (32 - i * 8); 80 } 81 return insn; 82 } 83 84 static uint32_t li(DisasContext *ctx, int sz) 85 { 86 int32_t tmp, addr; 87 CPURXState *env = ctx->env; 88 addr = ctx->base.pc_next; 89 90 tcg_debug_assert(sz < 4); 91 switch (sz) { 92 case 1: 93 ctx->base.pc_next += 1; 94 return cpu_ldsb_code(env, addr); 95 case 2: 96 ctx->base.pc_next += 2; 97 return cpu_ldsw_code(env, addr); 98 case 3: 99 ctx->base.pc_next += 3; 100 tmp = cpu_ldsb_code(env, addr + 2) << 16; 101 tmp |= cpu_lduw_code(env, addr) & 0xffff; 102 return tmp; 103 case 0: 104 ctx->base.pc_next += 4; 105 return cpu_ldl_code(env, addr); 106 } 107 return 0; 108 } 109 110 static int bdsp_s(DisasContext *ctx, int d) 111 { 112 /* 113 * 0 -> 8 114 * 1 -> 9 115 * 2 -> 10 116 * 3 -> 3 117 * : 118 * 7 -> 7 119 */ 120 if (d < 3) { 121 d += 8; 122 } 123 return d; 124 } 125 126 /* Include the auto-generated decoder. */ 127 #include "decode-insns.c.inc" 128 129 void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) 130 { 131 RXCPU *cpu = RX_CPU(cs); 132 CPURXState *env = &cpu->env; 133 int i; 134 uint32_t psw; 135 136 psw = rx_cpu_pack_psw(env); 137 qemu_fprintf(f, "pc=0x%08x psw=0x%08x\n", 138 env->pc, psw); 139 for (i = 0; i < 16; i += 4) { 140 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", 141 i, env->regs[i], i + 1, env->regs[i + 1], 142 i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]); 143 } 144 } 145 146 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) 147 { 148 if (translator_use_goto_tb(&dc->base, dest)) { 149 tcg_gen_goto_tb(n); 150 tcg_gen_movi_i32(cpu_pc, dest); 151 tcg_gen_exit_tb(dc->base.tb, n); 152 } else { 153 tcg_gen_movi_i32(cpu_pc, dest); 154 tcg_gen_lookup_and_goto_ptr(); 155 } 156 dc->base.is_jmp = DISAS_NORETURN; 157 } 158 159 /* generic load wrapper */ 160 static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem) 161 { 162 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); 163 } 164 165 /* unsigned load wrapper */ 166 static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem) 167 { 168 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); 169 } 170 171 /* generic store wrapper */ 172 static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem) 173 { 174 tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); 175 } 176 177 /* [ri, rb] */ 178 static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem, 179 int size, int ri, int rb) 180 { 181 tcg_gen_shli_i32(mem, cpu_regs[ri], size); 182 tcg_gen_add_i32(mem, mem, cpu_regs[rb]); 183 } 184 185 /* dsp[reg] */ 186 static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem, 187 int ld, int size, int reg) 188 { 189 uint32_t dsp; 190 191 tcg_debug_assert(ld < 3); 192 switch (ld) { 193 case 0: 194 return cpu_regs[reg]; 195 case 1: 196 dsp = cpu_ldub_code(ctx->env, ctx->base.pc_next) << size; 197 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 198 ctx->base.pc_next += 1; 199 return mem; 200 case 2: 201 dsp = cpu_lduw_code(ctx->env, ctx->base.pc_next) << size; 202 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 203 ctx->base.pc_next += 2; 204 return mem; 205 } 206 return NULL; 207 } 208 209 static inline MemOp mi_to_mop(unsigned mi) 210 { 211 static const MemOp mop[5] = { MO_SB, MO_SW, MO_UL, MO_UW, MO_UB }; 212 tcg_debug_assert(mi < 5); 213 return mop[mi]; 214 } 215 216 /* load source operand */ 217 static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem, 218 int ld, int mi, int rs) 219 { 220 TCGv addr; 221 MemOp mop; 222 if (ld < 3) { 223 mop = mi_to_mop(mi); 224 addr = rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs); 225 tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE); 226 return mem; 227 } else { 228 return cpu_regs[rs]; 229 } 230 } 231 232 /* Processor mode check */ 233 static int is_privileged(DisasContext *ctx, int is_exception) 234 { 235 if (FIELD_EX32(ctx->tb_flags, PSW, PM)) { 236 if (is_exception) { 237 gen_helper_raise_privilege_violation(cpu_env); 238 } 239 return 0; 240 } else { 241 return 1; 242 } 243 } 244 245 /* generate QEMU condition */ 246 static void psw_cond(DisasCompare *dc, uint32_t cond) 247 { 248 tcg_debug_assert(cond < 16); 249 switch (cond) { 250 case 0: /* z */ 251 dc->cond = TCG_COND_EQ; 252 dc->value = cpu_psw_z; 253 break; 254 case 1: /* nz */ 255 dc->cond = TCG_COND_NE; 256 dc->value = cpu_psw_z; 257 break; 258 case 2: /* c */ 259 dc->cond = TCG_COND_NE; 260 dc->value = cpu_psw_c; 261 break; 262 case 3: /* nc */ 263 dc->cond = TCG_COND_EQ; 264 dc->value = cpu_psw_c; 265 break; 266 case 4: /* gtu (C& ~Z) == 1 */ 267 case 5: /* leu (C& ~Z) == 0 */ 268 tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0); 269 tcg_gen_and_i32(dc->temp, dc->temp, cpu_psw_c); 270 dc->cond = (cond == 4) ? TCG_COND_NE : TCG_COND_EQ; 271 dc->value = dc->temp; 272 break; 273 case 6: /* pz (S == 0) */ 274 dc->cond = TCG_COND_GE; 275 dc->value = cpu_psw_s; 276 break; 277 case 7: /* n (S == 1) */ 278 dc->cond = TCG_COND_LT; 279 dc->value = cpu_psw_s; 280 break; 281 case 8: /* ge (S^O)==0 */ 282 case 9: /* lt (S^O)==1 */ 283 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 284 dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT; 285 dc->value = dc->temp; 286 break; 287 case 10: /* gt ((S^O)|Z)==0 */ 288 case 11: /* le ((S^O)|Z)==1 */ 289 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 290 tcg_gen_sari_i32(dc->temp, dc->temp, 31); 291 tcg_gen_andc_i32(dc->temp, cpu_psw_z, dc->temp); 292 dc->cond = (cond == 10) ? TCG_COND_NE : TCG_COND_EQ; 293 dc->value = dc->temp; 294 break; 295 case 12: /* o */ 296 dc->cond = TCG_COND_LT; 297 dc->value = cpu_psw_o; 298 break; 299 case 13: /* no */ 300 dc->cond = TCG_COND_GE; 301 dc->value = cpu_psw_o; 302 break; 303 case 14: /* always true */ 304 dc->cond = TCG_COND_ALWAYS; 305 dc->value = dc->temp; 306 break; 307 case 15: /* always false */ 308 dc->cond = TCG_COND_NEVER; 309 dc->value = dc->temp; 310 break; 311 } 312 } 313 314 static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc) 315 { 316 switch (cr) { 317 case 0: /* PSW */ 318 gen_helper_pack_psw(ret, cpu_env); 319 break; 320 case 1: /* PC */ 321 tcg_gen_movi_i32(ret, pc); 322 break; 323 case 2: /* USP */ 324 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 325 tcg_gen_mov_i32(ret, cpu_sp); 326 } else { 327 tcg_gen_mov_i32(ret, cpu_usp); 328 } 329 break; 330 case 3: /* FPSW */ 331 tcg_gen_mov_i32(ret, cpu_fpsw); 332 break; 333 case 8: /* BPSW */ 334 tcg_gen_mov_i32(ret, cpu_bpsw); 335 break; 336 case 9: /* BPC */ 337 tcg_gen_mov_i32(ret, cpu_bpc); 338 break; 339 case 10: /* ISP */ 340 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 341 tcg_gen_mov_i32(ret, cpu_isp); 342 } else { 343 tcg_gen_mov_i32(ret, cpu_sp); 344 } 345 break; 346 case 11: /* FINTV */ 347 tcg_gen_mov_i32(ret, cpu_fintv); 348 break; 349 case 12: /* INTB */ 350 tcg_gen_mov_i32(ret, cpu_intb); 351 break; 352 default: 353 qemu_log_mask(LOG_GUEST_ERROR, "Unimplement control register %d", cr); 354 /* Unimplement registers return 0 */ 355 tcg_gen_movi_i32(ret, 0); 356 break; 357 } 358 } 359 360 static void move_to_cr(DisasContext *ctx, TCGv val, int cr) 361 { 362 if (cr >= 8 && !is_privileged(ctx, 0)) { 363 /* Some control registers can only be written in privileged mode. */ 364 qemu_log_mask(LOG_GUEST_ERROR, 365 "disallow control register write %s", rx_crname(cr)); 366 return; 367 } 368 switch (cr) { 369 case 0: /* PSW */ 370 gen_helper_set_psw(cpu_env, val); 371 if (is_privileged(ctx, 0)) { 372 /* PSW.{I,U} may be updated here. exit TB. */ 373 ctx->base.is_jmp = DISAS_UPDATE; 374 } 375 break; 376 /* case 1: to PC not supported */ 377 case 2: /* USP */ 378 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 379 tcg_gen_mov_i32(cpu_sp, val); 380 } else { 381 tcg_gen_mov_i32(cpu_usp, val); 382 } 383 break; 384 case 3: /* FPSW */ 385 gen_helper_set_fpsw(cpu_env, val); 386 break; 387 case 8: /* BPSW */ 388 tcg_gen_mov_i32(cpu_bpsw, val); 389 break; 390 case 9: /* BPC */ 391 tcg_gen_mov_i32(cpu_bpc, val); 392 break; 393 case 10: /* ISP */ 394 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 395 tcg_gen_mov_i32(cpu_isp, val); 396 } else { 397 tcg_gen_mov_i32(cpu_sp, val); 398 } 399 break; 400 case 11: /* FINTV */ 401 tcg_gen_mov_i32(cpu_fintv, val); 402 break; 403 case 12: /* INTB */ 404 tcg_gen_mov_i32(cpu_intb, val); 405 break; 406 default: 407 qemu_log_mask(LOG_GUEST_ERROR, 408 "Unimplement control register %d", cr); 409 break; 410 } 411 } 412 413 static void push(TCGv val) 414 { 415 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 416 rx_gen_st(MO_32, val, cpu_sp); 417 } 418 419 static void pop(TCGv ret) 420 { 421 rx_gen_ld(MO_32, ret, cpu_sp); 422 tcg_gen_addi_i32(cpu_sp, cpu_sp, 4); 423 } 424 425 /* mov.<bwl> rs,dsp5[rd] */ 426 static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) 427 { 428 TCGv mem; 429 mem = tcg_temp_new(); 430 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 431 rx_gen_st(a->sz, cpu_regs[a->rs], mem); 432 return true; 433 } 434 435 /* mov.<bwl> dsp5[rs],rd */ 436 static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) 437 { 438 TCGv mem; 439 mem = tcg_temp_new(); 440 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 441 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 442 return true; 443 } 444 445 /* mov.l #uimm4,rd */ 446 /* mov.l #uimm8,rd */ 447 /* mov.l #imm,rd */ 448 static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) 449 { 450 tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); 451 return true; 452 } 453 454 /* mov.<bwl> #uimm8,dsp[rd] */ 455 /* mov.<bwl> #imm, dsp[rd] */ 456 static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) 457 { 458 TCGv imm, mem; 459 imm = tcg_const_i32(a->imm); 460 mem = tcg_temp_new(); 461 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 462 rx_gen_st(a->sz, imm, mem); 463 return true; 464 } 465 466 /* mov.<bwl> [ri,rb],rd */ 467 static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a) 468 { 469 TCGv mem; 470 mem = tcg_temp_new(); 471 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 472 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 473 return true; 474 } 475 476 /* mov.<bwl> rd,[ri,rb] */ 477 static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) 478 { 479 TCGv mem; 480 mem = tcg_temp_new(); 481 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 482 rx_gen_st(a->sz, cpu_regs[a->rs], mem); 483 return true; 484 } 485 486 /* mov.<bwl> dsp[rs],dsp[rd] */ 487 /* mov.<bwl> rs,dsp[rd] */ 488 /* mov.<bwl> dsp[rs],rd */ 489 /* mov.<bwl> rs,rd */ 490 static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) 491 { 492 static void (* const mov[])(TCGv ret, TCGv arg) = { 493 tcg_gen_ext8s_i32, tcg_gen_ext16s_i32, tcg_gen_mov_i32, 494 }; 495 TCGv tmp, mem, addr; 496 if (a->lds == 3 && a->ldd == 3) { 497 /* mov.<bwl> rs,rd */ 498 mov[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]); 499 return true; 500 } 501 502 mem = tcg_temp_new(); 503 if (a->lds == 3) { 504 /* mov.<bwl> rs,dsp[rd] */ 505 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs); 506 rx_gen_st(a->sz, cpu_regs[a->rd], addr); 507 } else if (a->ldd == 3) { 508 /* mov.<bwl> dsp[rs],rd */ 509 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 510 rx_gen_ld(a->sz, cpu_regs[a->rd], addr); 511 } else { 512 /* mov.<bwl> dsp[rs],dsp[rd] */ 513 tmp = tcg_temp_new(); 514 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 515 rx_gen_ld(a->sz, tmp, addr); 516 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); 517 rx_gen_st(a->sz, tmp, addr); 518 } 519 return true; 520 } 521 522 /* mov.<bwl> rs,[rd+] */ 523 /* mov.<bwl> rs,[-rd] */ 524 static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) 525 { 526 TCGv val; 527 val = tcg_temp_new(); 528 tcg_gen_mov_i32(val, cpu_regs[a->rs]); 529 if (a->ad == 1) { 530 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 531 } 532 rx_gen_st(a->sz, val, cpu_regs[a->rd]); 533 if (a->ad == 0) { 534 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 535 } 536 return true; 537 } 538 539 /* mov.<bwl> [rd+],rs */ 540 /* mov.<bwl> [-rd],rs */ 541 static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) 542 { 543 TCGv val; 544 val = tcg_temp_new(); 545 if (a->ad == 1) { 546 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 547 } 548 rx_gen_ld(a->sz, val, cpu_regs[a->rd]); 549 if (a->ad == 0) { 550 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 551 } 552 tcg_gen_mov_i32(cpu_regs[a->rs], val); 553 return true; 554 } 555 556 /* movu.<bw> dsp5[rs],rd */ 557 /* movu.<bw> dsp[rs],rd */ 558 static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a) 559 { 560 TCGv mem; 561 mem = tcg_temp_new(); 562 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 563 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 564 return true; 565 } 566 567 /* movu.<bw> rs,rd */ 568 static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a) 569 { 570 static void (* const ext[])(TCGv ret, TCGv arg) = { 571 tcg_gen_ext8u_i32, tcg_gen_ext16u_i32, 572 }; 573 ext[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]); 574 return true; 575 } 576 577 /* movu.<bw> [ri,rb],rd */ 578 static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a) 579 { 580 TCGv mem; 581 mem = tcg_temp_new(); 582 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 583 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 584 return true; 585 } 586 587 /* movu.<bw> [rd+],rs */ 588 /* mov.<bw> [-rd],rs */ 589 static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) 590 { 591 TCGv val; 592 val = tcg_temp_new(); 593 if (a->ad == 1) { 594 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 595 } 596 rx_gen_ldu(a->sz, val, cpu_regs[a->rd]); 597 if (a->ad == 0) { 598 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 599 } 600 tcg_gen_mov_i32(cpu_regs[a->rs], val); 601 return true; 602 } 603 604 605 /* pop rd */ 606 static bool trans_POP(DisasContext *ctx, arg_POP *a) 607 { 608 /* mov.l [r0+], rd */ 609 arg_MOV_rp mov_a; 610 mov_a.rd = 0; 611 mov_a.rs = a->rd; 612 mov_a.ad = 0; 613 mov_a.sz = MO_32; 614 trans_MOV_pr(ctx, &mov_a); 615 return true; 616 } 617 618 /* popc cr */ 619 static bool trans_POPC(DisasContext *ctx, arg_POPC *a) 620 { 621 TCGv val; 622 val = tcg_temp_new(); 623 pop(val); 624 move_to_cr(ctx, val, a->cr); 625 return true; 626 } 627 628 /* popm rd-rd2 */ 629 static bool trans_POPM(DisasContext *ctx, arg_POPM *a) 630 { 631 int r; 632 if (a->rd == 0 || a->rd >= a->rd2) { 633 qemu_log_mask(LOG_GUEST_ERROR, 634 "Invalid register ranges r%d-r%d", a->rd, a->rd2); 635 } 636 r = a->rd; 637 while (r <= a->rd2 && r < 16) { 638 pop(cpu_regs[r++]); 639 } 640 return true; 641 } 642 643 644 /* push.<bwl> rs */ 645 static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) 646 { 647 TCGv val; 648 val = tcg_temp_new(); 649 tcg_gen_mov_i32(val, cpu_regs[a->rs]); 650 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 651 rx_gen_st(a->sz, val, cpu_sp); 652 return true; 653 } 654 655 /* push.<bwl> dsp[rs] */ 656 static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) 657 { 658 TCGv mem, val, addr; 659 mem = tcg_temp_new(); 660 val = tcg_temp_new(); 661 addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs); 662 rx_gen_ld(a->sz, val, addr); 663 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 664 rx_gen_st(a->sz, val, cpu_sp); 665 return true; 666 } 667 668 /* pushc rx */ 669 static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) 670 { 671 TCGv val; 672 val = tcg_temp_new(); 673 move_from_cr(ctx, val, a->cr, ctx->pc); 674 push(val); 675 return true; 676 } 677 678 /* pushm rs-rs2 */ 679 static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) 680 { 681 int r; 682 683 if (a->rs == 0 || a->rs >= a->rs2) { 684 qemu_log_mask(LOG_GUEST_ERROR, 685 "Invalid register ranges r%d-r%d", a->rs, a->rs2); 686 } 687 r = a->rs2; 688 while (r >= a->rs && r >= 0) { 689 push(cpu_regs[r--]); 690 } 691 return true; 692 } 693 694 /* xchg rs,rd */ 695 static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) 696 { 697 TCGv tmp; 698 tmp = tcg_temp_new(); 699 tcg_gen_mov_i32(tmp, cpu_regs[a->rs]); 700 tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); 701 tcg_gen_mov_i32(cpu_regs[a->rd], tmp); 702 return true; 703 } 704 705 /* xchg dsp[rs].<mi>,rd */ 706 static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) 707 { 708 TCGv mem, addr; 709 mem = tcg_temp_new(); 710 switch (a->mi) { 711 case 0: /* dsp[rs].b */ 712 case 1: /* dsp[rs].w */ 713 case 2: /* dsp[rs].l */ 714 addr = rx_index_addr(ctx, mem, a->ld, a->mi, a->rs); 715 break; 716 case 3: /* dsp[rs].uw */ 717 case 4: /* dsp[rs].ub */ 718 addr = rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs); 719 break; 720 default: 721 g_assert_not_reached(); 722 } 723 tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd], 724 0, mi_to_mop(a->mi)); 725 return true; 726 } 727 728 static inline void stcond(TCGCond cond, int rd, int imm) 729 { 730 TCGv z; 731 TCGv _imm; 732 z = tcg_const_i32(0); 733 _imm = tcg_const_i32(imm); 734 tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, 735 _imm, cpu_regs[rd]); 736 } 737 738 /* stz #imm,rd */ 739 static bool trans_STZ(DisasContext *ctx, arg_STZ *a) 740 { 741 stcond(TCG_COND_EQ, a->rd, a->imm); 742 return true; 743 } 744 745 /* stnz #imm,rd */ 746 static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a) 747 { 748 stcond(TCG_COND_NE, a->rd, a->imm); 749 return true; 750 } 751 752 /* sccnd.<bwl> rd */ 753 /* sccnd.<bwl> dsp:[rd] */ 754 static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) 755 { 756 DisasCompare dc; 757 TCGv val, mem, addr; 758 dc.temp = tcg_temp_new(); 759 psw_cond(&dc, a->cd); 760 if (a->ld < 3) { 761 val = tcg_temp_new(); 762 mem = tcg_temp_new(); 763 tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0); 764 addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); 765 rx_gen_st(a->sz, val, addr); 766 } else { 767 tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); 768 } 769 return true; 770 } 771 772 /* rtsd #imm */ 773 static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a) 774 { 775 tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2); 776 pop(cpu_pc); 777 ctx->base.is_jmp = DISAS_JUMP; 778 return true; 779 } 780 781 /* rtsd #imm, rd-rd2 */ 782 static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a) 783 { 784 int dst; 785 int adj; 786 787 if (a->rd2 >= a->rd) { 788 adj = a->imm - (a->rd2 - a->rd + 1); 789 } else { 790 adj = a->imm - (15 - a->rd + 1); 791 } 792 793 tcg_gen_addi_i32(cpu_sp, cpu_sp, adj << 2); 794 dst = a->rd; 795 while (dst <= a->rd2 && dst < 16) { 796 pop(cpu_regs[dst++]); 797 } 798 pop(cpu_pc); 799 ctx->base.is_jmp = DISAS_JUMP; 800 return true; 801 } 802 803 typedef void (*op2fn)(TCGv ret, TCGv arg1); 804 typedef void (*op3fn)(TCGv ret, TCGv arg1, TCGv arg2); 805 806 static inline void rx_gen_op_rr(op2fn opr, int dst, int src) 807 { 808 opr(cpu_regs[dst], cpu_regs[src]); 809 } 810 811 static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2) 812 { 813 opr(cpu_regs[dst], cpu_regs[src], cpu_regs[src2]); 814 } 815 816 static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2) 817 { 818 TCGv imm = tcg_const_i32(src2); 819 opr(cpu_regs[dst], cpu_regs[src], imm); 820 } 821 822 static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx, 823 int dst, int src, int ld, int mi) 824 { 825 TCGv val, mem; 826 mem = tcg_temp_new(); 827 val = rx_load_source(ctx, mem, ld, mi, src); 828 opr(cpu_regs[dst], cpu_regs[dst], val); 829 } 830 831 static void rx_and(TCGv ret, TCGv arg1, TCGv arg2) 832 { 833 tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 834 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 835 tcg_gen_mov_i32(ret, cpu_psw_s); 836 } 837 838 /* and #uimm:4, rd */ 839 /* and #imm, rd */ 840 static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a) 841 { 842 rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm); 843 return true; 844 } 845 846 /* and dsp[rs], rd */ 847 /* and rs,rd */ 848 static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a) 849 { 850 rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi); 851 return true; 852 } 853 854 /* and rs,rs2,rd */ 855 static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a) 856 { 857 rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2); 858 return true; 859 } 860 861 static void rx_or(TCGv ret, TCGv arg1, TCGv arg2) 862 { 863 tcg_gen_or_i32(cpu_psw_s, arg1, arg2); 864 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 865 tcg_gen_mov_i32(ret, cpu_psw_s); 866 } 867 868 /* or #uimm:4, rd */ 869 /* or #imm, rd */ 870 static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a) 871 { 872 rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm); 873 return true; 874 } 875 876 /* or dsp[rs], rd */ 877 /* or rs,rd */ 878 static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a) 879 { 880 rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi); 881 return true; 882 } 883 884 /* or rs,rs2,rd */ 885 static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a) 886 { 887 rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2); 888 return true; 889 } 890 891 static void rx_xor(TCGv ret, TCGv arg1, TCGv arg2) 892 { 893 tcg_gen_xor_i32(cpu_psw_s, arg1, arg2); 894 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 895 tcg_gen_mov_i32(ret, cpu_psw_s); 896 } 897 898 /* xor #imm, rd */ 899 static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a) 900 { 901 rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm); 902 return true; 903 } 904 905 /* xor dsp[rs], rd */ 906 /* xor rs,rd */ 907 static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a) 908 { 909 rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi); 910 return true; 911 } 912 913 static void rx_tst(TCGv ret, TCGv arg1, TCGv arg2) 914 { 915 tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 916 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 917 } 918 919 /* tst #imm, rd */ 920 static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a) 921 { 922 rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm); 923 return true; 924 } 925 926 /* tst dsp[rs], rd */ 927 /* tst rs, rd */ 928 static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a) 929 { 930 rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi); 931 return true; 932 } 933 934 static void rx_not(TCGv ret, TCGv arg1) 935 { 936 tcg_gen_not_i32(ret, arg1); 937 tcg_gen_mov_i32(cpu_psw_z, ret); 938 tcg_gen_mov_i32(cpu_psw_s, ret); 939 } 940 941 /* not rd */ 942 /* not rs, rd */ 943 static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a) 944 { 945 rx_gen_op_rr(rx_not, a->rd, a->rs); 946 return true; 947 } 948 949 static void rx_neg(TCGv ret, TCGv arg1) 950 { 951 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000); 952 tcg_gen_neg_i32(ret, arg1); 953 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, ret, 0); 954 tcg_gen_mov_i32(cpu_psw_z, ret); 955 tcg_gen_mov_i32(cpu_psw_s, ret); 956 } 957 958 959 /* neg rd */ 960 /* neg rs, rd */ 961 static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) 962 { 963 rx_gen_op_rr(rx_neg, a->rd, a->rs); 964 return true; 965 } 966 967 /* ret = arg1 + arg2 + psw_c */ 968 static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) 969 { 970 TCGv z; 971 z = tcg_const_i32(0); 972 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); 973 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); 974 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 975 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 976 tcg_gen_xor_i32(z, arg1, arg2); 977 tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); 978 tcg_gen_mov_i32(ret, cpu_psw_s); 979 } 980 981 /* adc #imm, rd */ 982 static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a) 983 { 984 rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm); 985 return true; 986 } 987 988 /* adc rs, rd */ 989 static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a) 990 { 991 rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs); 992 return true; 993 } 994 995 /* adc dsp[rs], rd */ 996 static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) 997 { 998 /* mi only 2 */ 999 if (a->mi != 2) { 1000 return false; 1001 } 1002 rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi); 1003 return true; 1004 } 1005 1006 /* ret = arg1 + arg2 */ 1007 static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) 1008 { 1009 TCGv z; 1010 z = tcg_const_i32(0); 1011 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); 1012 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 1013 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1014 tcg_gen_xor_i32(z, arg1, arg2); 1015 tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); 1016 tcg_gen_mov_i32(ret, cpu_psw_s); 1017 } 1018 1019 /* add #uimm4, rd */ 1020 /* add #imm, rs, rd */ 1021 static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a) 1022 { 1023 rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm); 1024 return true; 1025 } 1026 1027 /* add rs, rd */ 1028 /* add dsp[rs], rd */ 1029 static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a) 1030 { 1031 rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi); 1032 return true; 1033 } 1034 1035 /* add rs, rs2, rd */ 1036 static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a) 1037 { 1038 rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2); 1039 return true; 1040 } 1041 1042 /* ret = arg1 - arg2 */ 1043 static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) 1044 { 1045 TCGv temp; 1046 tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); 1047 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 1048 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); 1049 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1050 temp = tcg_temp_new_i32(); 1051 tcg_gen_xor_i32(temp, arg1, arg2); 1052 tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp); 1053 /* CMP not required return */ 1054 if (ret) { 1055 tcg_gen_mov_i32(ret, cpu_psw_s); 1056 } 1057 } 1058 static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2) 1059 { 1060 rx_sub(NULL, arg1, arg2); 1061 } 1062 /* ret = arg1 - arg2 - !psw_c */ 1063 /* -> ret = arg1 + ~arg2 + psw_c */ 1064 static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) 1065 { 1066 TCGv temp; 1067 temp = tcg_temp_new(); 1068 tcg_gen_not_i32(temp, arg2); 1069 rx_adc(ret, arg1, temp); 1070 } 1071 1072 /* cmp #imm4, rs2 */ 1073 /* cmp #imm8, rs2 */ 1074 /* cmp #imm, rs2 */ 1075 static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a) 1076 { 1077 rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm); 1078 return true; 1079 } 1080 1081 /* cmp rs, rs2 */ 1082 /* cmp dsp[rs], rs2 */ 1083 static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a) 1084 { 1085 rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi); 1086 return true; 1087 } 1088 1089 /* sub #imm4, rd */ 1090 static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a) 1091 { 1092 rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm); 1093 return true; 1094 } 1095 1096 /* sub rs, rd */ 1097 /* sub dsp[rs], rd */ 1098 static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a) 1099 { 1100 rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi); 1101 return true; 1102 } 1103 1104 /* sub rs2, rs, rd */ 1105 static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a) 1106 { 1107 rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs); 1108 return true; 1109 } 1110 1111 /* sbb rs, rd */ 1112 static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a) 1113 { 1114 rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs); 1115 return true; 1116 } 1117 1118 /* sbb dsp[rs], rd */ 1119 static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) 1120 { 1121 /* mi only 2 */ 1122 if (a->mi != 2) { 1123 return false; 1124 } 1125 rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi); 1126 return true; 1127 } 1128 1129 static void rx_abs(TCGv ret, TCGv arg1) 1130 { 1131 TCGv neg; 1132 TCGv zero; 1133 neg = tcg_temp_new(); 1134 zero = tcg_const_i32(0); 1135 tcg_gen_neg_i32(neg, arg1); 1136 tcg_gen_movcond_i32(TCG_COND_LT, ret, arg1, zero, neg, arg1); 1137 } 1138 1139 /* abs rd */ 1140 /* abs rs, rd */ 1141 static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) 1142 { 1143 rx_gen_op_rr(rx_abs, a->rd, a->rs); 1144 return true; 1145 } 1146 1147 /* max #imm, rd */ 1148 static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a) 1149 { 1150 rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm); 1151 return true; 1152 } 1153 1154 /* max rs, rd */ 1155 /* max dsp[rs], rd */ 1156 static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a) 1157 { 1158 rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1159 return true; 1160 } 1161 1162 /* min #imm, rd */ 1163 static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a) 1164 { 1165 rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm); 1166 return true; 1167 } 1168 1169 /* min rs, rd */ 1170 /* min dsp[rs], rd */ 1171 static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a) 1172 { 1173 rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1174 return true; 1175 } 1176 1177 /* mul #uimm4, rd */ 1178 /* mul #imm, rd */ 1179 static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a) 1180 { 1181 rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm); 1182 return true; 1183 } 1184 1185 /* mul rs, rd */ 1186 /* mul dsp[rs], rd */ 1187 static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a) 1188 { 1189 rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1190 return true; 1191 } 1192 1193 /* mul rs, rs2, rd */ 1194 static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a) 1195 { 1196 rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2); 1197 return true; 1198 } 1199 1200 /* emul #imm, rd */ 1201 static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) 1202 { 1203 TCGv imm = tcg_const_i32(a->imm); 1204 if (a->rd > 14) { 1205 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1206 } 1207 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1208 cpu_regs[a->rd], imm); 1209 return true; 1210 } 1211 1212 /* emul rs, rd */ 1213 /* emul dsp[rs], rd */ 1214 static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) 1215 { 1216 TCGv val, mem; 1217 if (a->rd > 14) { 1218 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1219 } 1220 mem = tcg_temp_new(); 1221 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1222 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1223 cpu_regs[a->rd], val); 1224 return true; 1225 } 1226 1227 /* emulu #imm, rd */ 1228 static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) 1229 { 1230 TCGv imm = tcg_const_i32(a->imm); 1231 if (a->rd > 14) { 1232 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1233 } 1234 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1235 cpu_regs[a->rd], imm); 1236 return true; 1237 } 1238 1239 /* emulu rs, rd */ 1240 /* emulu dsp[rs], rd */ 1241 static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) 1242 { 1243 TCGv val, mem; 1244 if (a->rd > 14) { 1245 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1246 } 1247 mem = tcg_temp_new(); 1248 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1249 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1250 cpu_regs[a->rd], val); 1251 return true; 1252 } 1253 1254 static void rx_div(TCGv ret, TCGv arg1, TCGv arg2) 1255 { 1256 gen_helper_div(ret, cpu_env, arg1, arg2); 1257 } 1258 1259 static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2) 1260 { 1261 gen_helper_divu(ret, cpu_env, arg1, arg2); 1262 } 1263 1264 /* div #imm, rd */ 1265 static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a) 1266 { 1267 rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm); 1268 return true; 1269 } 1270 1271 /* div rs, rd */ 1272 /* div dsp[rs], rd */ 1273 static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a) 1274 { 1275 rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi); 1276 return true; 1277 } 1278 1279 /* divu #imm, rd */ 1280 static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a) 1281 { 1282 rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm); 1283 return true; 1284 } 1285 1286 /* divu rs, rd */ 1287 /* divu dsp[rs], rd */ 1288 static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a) 1289 { 1290 rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi); 1291 return true; 1292 } 1293 1294 1295 /* shll #imm:5, rd */ 1296 /* shll #imm:5, rs2, rd */ 1297 static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) 1298 { 1299 TCGv tmp; 1300 tmp = tcg_temp_new(); 1301 if (a->imm) { 1302 tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm); 1303 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm); 1304 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1305 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1306 tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1307 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1308 } else { 1309 tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]); 1310 tcg_gen_movi_i32(cpu_psw_c, 0); 1311 tcg_gen_movi_i32(cpu_psw_o, 0); 1312 } 1313 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1314 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1315 return true; 1316 } 1317 1318 /* shll rs, rd */ 1319 static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) 1320 { 1321 TCGLabel *noshift, *done; 1322 TCGv count, tmp; 1323 1324 noshift = gen_new_label(); 1325 done = gen_new_label(); 1326 /* if (cpu_regs[a->rs]) { */ 1327 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); 1328 count = tcg_const_i32(32); 1329 tmp = tcg_temp_new(); 1330 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); 1331 tcg_gen_sub_i32(count, count, tmp); 1332 tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); 1333 tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1334 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1335 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1336 tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1337 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1338 tcg_gen_br(done); 1339 /* } else { */ 1340 gen_set_label(noshift); 1341 tcg_gen_movi_i32(cpu_psw_c, 0); 1342 tcg_gen_movi_i32(cpu_psw_o, 0); 1343 /* } */ 1344 gen_set_label(done); 1345 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1346 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1347 return true; 1348 } 1349 1350 static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm, 1351 unsigned int alith) 1352 { 1353 static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1354 tcg_gen_shri_i32, tcg_gen_sari_i32, 1355 }; 1356 tcg_debug_assert(alith < 2); 1357 if (imm) { 1358 gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1); 1359 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1360 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1361 } else { 1362 tcg_gen_mov_i32(cpu_regs[rd], cpu_regs[rs]); 1363 tcg_gen_movi_i32(cpu_psw_c, 0); 1364 } 1365 tcg_gen_movi_i32(cpu_psw_o, 0); 1366 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1367 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1368 } 1369 1370 static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith) 1371 { 1372 TCGLabel *noshift, *done; 1373 TCGv count; 1374 static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1375 tcg_gen_shri_i32, tcg_gen_sari_i32, 1376 }; 1377 static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) = { 1378 tcg_gen_shr_i32, tcg_gen_sar_i32, 1379 }; 1380 tcg_debug_assert(alith < 2); 1381 noshift = gen_new_label(); 1382 done = gen_new_label(); 1383 count = tcg_temp_new(); 1384 /* if (cpu_regs[rs]) { */ 1385 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[rs], 0, noshift); 1386 tcg_gen_andi_i32(count, cpu_regs[rs], 31); 1387 tcg_gen_subi_i32(count, count, 1); 1388 gen_sXr[alith](cpu_regs[rd], cpu_regs[rd], count); 1389 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1390 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1391 tcg_gen_br(done); 1392 /* } else { */ 1393 gen_set_label(noshift); 1394 tcg_gen_movi_i32(cpu_psw_c, 0); 1395 /* } */ 1396 gen_set_label(done); 1397 tcg_gen_movi_i32(cpu_psw_o, 0); 1398 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1399 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1400 } 1401 1402 /* shar #imm:5, rd */ 1403 /* shar #imm:5, rs2, rd */ 1404 static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a) 1405 { 1406 shiftr_imm(a->rd, a->rs2, a->imm, 1); 1407 return true; 1408 } 1409 1410 /* shar rs, rd */ 1411 static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a) 1412 { 1413 shiftr_reg(a->rd, a->rs, 1); 1414 return true; 1415 } 1416 1417 /* shlr #imm:5, rd */ 1418 /* shlr #imm:5, rs2, rd */ 1419 static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a) 1420 { 1421 shiftr_imm(a->rd, a->rs2, a->imm, 0); 1422 return true; 1423 } 1424 1425 /* shlr rs, rd */ 1426 static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a) 1427 { 1428 shiftr_reg(a->rd, a->rs, 0); 1429 return true; 1430 } 1431 1432 /* rolc rd */ 1433 static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) 1434 { 1435 TCGv tmp; 1436 tmp = tcg_temp_new(); 1437 tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31); 1438 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1439 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1440 tcg_gen_mov_i32(cpu_psw_c, tmp); 1441 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1442 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1443 return true; 1444 } 1445 1446 /* rorc rd */ 1447 static bool trans_RORC(DisasContext *ctx, arg_RORC *a) 1448 { 1449 TCGv tmp; 1450 tmp = tcg_temp_new(); 1451 tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); 1452 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1453 tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, 31); 1454 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1455 tcg_gen_mov_i32(cpu_psw_c, tmp); 1456 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1457 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1458 return true; 1459 } 1460 1461 enum {ROTR = 0, ROTL = 1}; 1462 enum {ROT_IMM = 0, ROT_REG = 1}; 1463 static inline void rx_rot(int ir, int dir, int rd, int src) 1464 { 1465 switch (dir) { 1466 case ROTL: 1467 if (ir == ROT_IMM) { 1468 tcg_gen_rotli_i32(cpu_regs[rd], cpu_regs[rd], src); 1469 } else { 1470 tcg_gen_rotl_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1471 } 1472 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1473 break; 1474 case ROTR: 1475 if (ir == ROT_IMM) { 1476 tcg_gen_rotri_i32(cpu_regs[rd], cpu_regs[rd], src); 1477 } else { 1478 tcg_gen_rotr_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1479 } 1480 tcg_gen_shri_i32(cpu_psw_c, cpu_regs[rd], 31); 1481 break; 1482 } 1483 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1484 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1485 } 1486 1487 /* rotl #imm, rd */ 1488 static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a) 1489 { 1490 rx_rot(ROT_IMM, ROTL, a->rd, a->imm); 1491 return true; 1492 } 1493 1494 /* rotl rs, rd */ 1495 static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a) 1496 { 1497 rx_rot(ROT_REG, ROTL, a->rd, a->rs); 1498 return true; 1499 } 1500 1501 /* rotr #imm, rd */ 1502 static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a) 1503 { 1504 rx_rot(ROT_IMM, ROTR, a->rd, a->imm); 1505 return true; 1506 } 1507 1508 /* rotr rs, rd */ 1509 static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a) 1510 { 1511 rx_rot(ROT_REG, ROTR, a->rd, a->rs); 1512 return true; 1513 } 1514 1515 /* revl rs, rd */ 1516 static bool trans_REVL(DisasContext *ctx, arg_REVL *a) 1517 { 1518 tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]); 1519 return true; 1520 } 1521 1522 /* revw rs, rd */ 1523 static bool trans_REVW(DisasContext *ctx, arg_REVW *a) 1524 { 1525 TCGv tmp; 1526 tmp = tcg_temp_new(); 1527 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); 1528 tcg_gen_shli_i32(tmp, tmp, 8); 1529 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); 1530 tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); 1531 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1532 return true; 1533 } 1534 1535 /* conditional branch helper */ 1536 static void rx_bcnd_main(DisasContext *ctx, int cd, int dst) 1537 { 1538 DisasCompare dc; 1539 TCGLabel *t, *done; 1540 1541 switch (cd) { 1542 case 0 ... 13: 1543 dc.temp = tcg_temp_new(); 1544 psw_cond(&dc, cd); 1545 t = gen_new_label(); 1546 done = gen_new_label(); 1547 tcg_gen_brcondi_i32(dc.cond, dc.value, 0, t); 1548 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1549 tcg_gen_br(done); 1550 gen_set_label(t); 1551 gen_goto_tb(ctx, 1, ctx->pc + dst); 1552 gen_set_label(done); 1553 break; 1554 case 14: 1555 /* always true case */ 1556 gen_goto_tb(ctx, 0, ctx->pc + dst); 1557 break; 1558 case 15: 1559 /* always false case */ 1560 /* Nothing do */ 1561 break; 1562 } 1563 } 1564 1565 /* beq dsp:3 / bne dsp:3 */ 1566 /* beq dsp:8 / bne dsp:8 */ 1567 /* bc dsp:8 / bnc dsp:8 */ 1568 /* bgtu dsp:8 / bleu dsp:8 */ 1569 /* bpz dsp:8 / bn dsp:8 */ 1570 /* bge dsp:8 / blt dsp:8 */ 1571 /* bgt dsp:8 / ble dsp:8 */ 1572 /* bo dsp:8 / bno dsp:8 */ 1573 /* beq dsp:16 / bne dsp:16 */ 1574 static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a) 1575 { 1576 rx_bcnd_main(ctx, a->cd, a->dsp); 1577 return true; 1578 } 1579 1580 /* bra dsp:3 */ 1581 /* bra dsp:8 */ 1582 /* bra dsp:16 */ 1583 /* bra dsp:24 */ 1584 static bool trans_BRA(DisasContext *ctx, arg_BRA *a) 1585 { 1586 rx_bcnd_main(ctx, 14, a->dsp); 1587 return true; 1588 } 1589 1590 /* bra rs */ 1591 static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a) 1592 { 1593 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1594 ctx->base.is_jmp = DISAS_JUMP; 1595 return true; 1596 } 1597 1598 static inline void rx_save_pc(DisasContext *ctx) 1599 { 1600 TCGv pc = tcg_const_i32(ctx->base.pc_next); 1601 push(pc); 1602 } 1603 1604 /* jmp rs */ 1605 static bool trans_JMP(DisasContext *ctx, arg_JMP *a) 1606 { 1607 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1608 ctx->base.is_jmp = DISAS_JUMP; 1609 return true; 1610 } 1611 1612 /* jsr rs */ 1613 static bool trans_JSR(DisasContext *ctx, arg_JSR *a) 1614 { 1615 rx_save_pc(ctx); 1616 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1617 ctx->base.is_jmp = DISAS_JUMP; 1618 return true; 1619 } 1620 1621 /* bsr dsp:16 */ 1622 /* bsr dsp:24 */ 1623 static bool trans_BSR(DisasContext *ctx, arg_BSR *a) 1624 { 1625 rx_save_pc(ctx); 1626 rx_bcnd_main(ctx, 14, a->dsp); 1627 return true; 1628 } 1629 1630 /* bsr rs */ 1631 static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a) 1632 { 1633 rx_save_pc(ctx); 1634 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1635 ctx->base.is_jmp = DISAS_JUMP; 1636 return true; 1637 } 1638 1639 /* rts */ 1640 static bool trans_RTS(DisasContext *ctx, arg_RTS *a) 1641 { 1642 pop(cpu_pc); 1643 ctx->base.is_jmp = DISAS_JUMP; 1644 return true; 1645 } 1646 1647 /* nop */ 1648 static bool trans_NOP(DisasContext *ctx, arg_NOP *a) 1649 { 1650 return true; 1651 } 1652 1653 /* scmpu */ 1654 static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) 1655 { 1656 gen_helper_scmpu(cpu_env); 1657 return true; 1658 } 1659 1660 /* smovu */ 1661 static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) 1662 { 1663 gen_helper_smovu(cpu_env); 1664 return true; 1665 } 1666 1667 /* smovf */ 1668 static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) 1669 { 1670 gen_helper_smovf(cpu_env); 1671 return true; 1672 } 1673 1674 /* smovb */ 1675 static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) 1676 { 1677 gen_helper_smovb(cpu_env); 1678 return true; 1679 } 1680 1681 #define STRING(op) \ 1682 do { \ 1683 TCGv size = tcg_const_i32(a->sz); \ 1684 gen_helper_##op(cpu_env, size); \ 1685 } while (0) 1686 1687 /* suntile.<bwl> */ 1688 static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a) 1689 { 1690 STRING(suntil); 1691 return true; 1692 } 1693 1694 /* swhile.<bwl> */ 1695 static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a) 1696 { 1697 STRING(swhile); 1698 return true; 1699 } 1700 /* sstr.<bwl> */ 1701 static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a) 1702 { 1703 STRING(sstr); 1704 return true; 1705 } 1706 1707 /* rmpa.<bwl> */ 1708 static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a) 1709 { 1710 STRING(rmpa); 1711 return true; 1712 } 1713 1714 static void rx_mul64hi(TCGv_i64 ret, int rs, int rs2) 1715 { 1716 TCGv_i64 tmp0, tmp1; 1717 tmp0 = tcg_temp_new_i64(); 1718 tmp1 = tcg_temp_new_i64(); 1719 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1720 tcg_gen_sari_i64(tmp0, tmp0, 16); 1721 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1722 tcg_gen_sari_i64(tmp1, tmp1, 16); 1723 tcg_gen_mul_i64(ret, tmp0, tmp1); 1724 tcg_gen_shli_i64(ret, ret, 16); 1725 } 1726 1727 static void rx_mul64lo(TCGv_i64 ret, int rs, int rs2) 1728 { 1729 TCGv_i64 tmp0, tmp1; 1730 tmp0 = tcg_temp_new_i64(); 1731 tmp1 = tcg_temp_new_i64(); 1732 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1733 tcg_gen_ext16s_i64(tmp0, tmp0); 1734 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1735 tcg_gen_ext16s_i64(tmp1, tmp1); 1736 tcg_gen_mul_i64(ret, tmp0, tmp1); 1737 tcg_gen_shli_i64(ret, ret, 16); 1738 } 1739 1740 /* mulhi rs,rs2 */ 1741 static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a) 1742 { 1743 rx_mul64hi(cpu_acc, a->rs, a->rs2); 1744 return true; 1745 } 1746 1747 /* mullo rs,rs2 */ 1748 static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a) 1749 { 1750 rx_mul64lo(cpu_acc, a->rs, a->rs2); 1751 return true; 1752 } 1753 1754 /* machi rs,rs2 */ 1755 static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a) 1756 { 1757 TCGv_i64 tmp; 1758 tmp = tcg_temp_new_i64(); 1759 rx_mul64hi(tmp, a->rs, a->rs2); 1760 tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1761 return true; 1762 } 1763 1764 /* maclo rs,rs2 */ 1765 static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a) 1766 { 1767 TCGv_i64 tmp; 1768 tmp = tcg_temp_new_i64(); 1769 rx_mul64lo(tmp, a->rs, a->rs2); 1770 tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1771 return true; 1772 } 1773 1774 /* mvfachi rd */ 1775 static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a) 1776 { 1777 tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc); 1778 return true; 1779 } 1780 1781 /* mvfacmi rd */ 1782 static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a) 1783 { 1784 TCGv_i64 rd64; 1785 rd64 = tcg_temp_new_i64(); 1786 tcg_gen_extract_i64(rd64, cpu_acc, 16, 32); 1787 tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64); 1788 return true; 1789 } 1790 1791 /* mvtachi rs */ 1792 static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a) 1793 { 1794 TCGv_i64 rs64; 1795 rs64 = tcg_temp_new_i64(); 1796 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1797 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 32, 32); 1798 return true; 1799 } 1800 1801 /* mvtaclo rs */ 1802 static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a) 1803 { 1804 TCGv_i64 rs64; 1805 rs64 = tcg_temp_new_i64(); 1806 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1807 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 0, 32); 1808 return true; 1809 } 1810 1811 /* racw #imm */ 1812 static bool trans_RACW(DisasContext *ctx, arg_RACW *a) 1813 { 1814 TCGv imm = tcg_const_i32(a->imm + 1); 1815 gen_helper_racw(cpu_env, imm); 1816 return true; 1817 } 1818 1819 /* sat rd */ 1820 static bool trans_SAT(DisasContext *ctx, arg_SAT *a) 1821 { 1822 TCGv tmp, z; 1823 tmp = tcg_temp_new(); 1824 z = tcg_const_i32(0); 1825 /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */ 1826 tcg_gen_sari_i32(tmp, cpu_psw_s, 31); 1827 /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */ 1828 tcg_gen_xori_i32(tmp, tmp, 0x80000000); 1829 tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], 1830 cpu_psw_o, z, tmp, cpu_regs[a->rd]); 1831 return true; 1832 } 1833 1834 /* satr */ 1835 static bool trans_SATR(DisasContext *ctx, arg_SATR *a) 1836 { 1837 gen_helper_satr(cpu_env); 1838 return true; 1839 } 1840 1841 #define cat3(a, b, c) a##b##c 1842 #define FOP(name, op) \ 1843 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 1844 cat3(arg_, name, _ir) * a) \ 1845 { \ 1846 TCGv imm = tcg_const_i32(li(ctx, 0)); \ 1847 gen_helper_##op(cpu_regs[a->rd], cpu_env, \ 1848 cpu_regs[a->rd], imm); \ 1849 return true; \ 1850 } \ 1851 static bool cat3(trans_, name, _mr)(DisasContext *ctx, \ 1852 cat3(arg_, name, _mr) * a) \ 1853 { \ 1854 TCGv val, mem; \ 1855 mem = tcg_temp_new(); \ 1856 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1857 gen_helper_##op(cpu_regs[a->rd], cpu_env, \ 1858 cpu_regs[a->rd], val); \ 1859 return true; \ 1860 } 1861 1862 #define FCONVOP(name, op) \ 1863 static bool trans_##name(DisasContext *ctx, arg_##name * a) \ 1864 { \ 1865 TCGv val, mem; \ 1866 mem = tcg_temp_new(); \ 1867 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1868 gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \ 1869 return true; \ 1870 } 1871 1872 FOP(FADD, fadd) 1873 FOP(FSUB, fsub) 1874 FOP(FMUL, fmul) 1875 FOP(FDIV, fdiv) 1876 1877 /* fcmp #imm, rd */ 1878 static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) 1879 { 1880 TCGv imm = tcg_const_i32(li(ctx, 0)); 1881 gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm); 1882 return true; 1883 } 1884 1885 /* fcmp dsp[rs], rd */ 1886 /* fcmp rs, rd */ 1887 static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) 1888 { 1889 TCGv val, mem; 1890 mem = tcg_temp_new(); 1891 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); 1892 gen_helper_fcmp(cpu_env, cpu_regs[a->rd], val); 1893 return true; 1894 } 1895 1896 FCONVOP(FTOI, ftoi) 1897 FCONVOP(ROUND, round) 1898 1899 /* itof rs, rd */ 1900 /* itof dsp[rs], rd */ 1901 static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a) 1902 { 1903 TCGv val, mem; 1904 mem = tcg_temp_new(); 1905 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1906 gen_helper_itof(cpu_regs[a->rd], cpu_env, val); 1907 return true; 1908 } 1909 1910 static void rx_bsetm(TCGv mem, TCGv mask) 1911 { 1912 TCGv val; 1913 val = tcg_temp_new(); 1914 rx_gen_ld(MO_8, val, mem); 1915 tcg_gen_or_i32(val, val, mask); 1916 rx_gen_st(MO_8, val, mem); 1917 } 1918 1919 static void rx_bclrm(TCGv mem, TCGv mask) 1920 { 1921 TCGv val; 1922 val = tcg_temp_new(); 1923 rx_gen_ld(MO_8, val, mem); 1924 tcg_gen_andc_i32(val, val, mask); 1925 rx_gen_st(MO_8, val, mem); 1926 } 1927 1928 static void rx_btstm(TCGv mem, TCGv mask) 1929 { 1930 TCGv val; 1931 val = tcg_temp_new(); 1932 rx_gen_ld(MO_8, val, mem); 1933 tcg_gen_and_i32(val, val, mask); 1934 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0); 1935 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 1936 } 1937 1938 static void rx_bnotm(TCGv mem, TCGv mask) 1939 { 1940 TCGv val; 1941 val = tcg_temp_new(); 1942 rx_gen_ld(MO_8, val, mem); 1943 tcg_gen_xor_i32(val, val, mask); 1944 rx_gen_st(MO_8, val, mem); 1945 } 1946 1947 static void rx_bsetr(TCGv reg, TCGv mask) 1948 { 1949 tcg_gen_or_i32(reg, reg, mask); 1950 } 1951 1952 static void rx_bclrr(TCGv reg, TCGv mask) 1953 { 1954 tcg_gen_andc_i32(reg, reg, mask); 1955 } 1956 1957 static inline void rx_btstr(TCGv reg, TCGv mask) 1958 { 1959 TCGv t0; 1960 t0 = tcg_temp_new(); 1961 tcg_gen_and_i32(t0, reg, mask); 1962 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0); 1963 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 1964 } 1965 1966 static inline void rx_bnotr(TCGv reg, TCGv mask) 1967 { 1968 tcg_gen_xor_i32(reg, reg, mask); 1969 } 1970 1971 #define BITOP(name, op) \ 1972 static bool cat3(trans_, name, _im)(DisasContext *ctx, \ 1973 cat3(arg_, name, _im) * a) \ 1974 { \ 1975 TCGv mask, mem, addr; \ 1976 mem = tcg_temp_new(); \ 1977 mask = tcg_const_i32(1 << a->imm); \ 1978 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 1979 cat3(rx_, op, m)(addr, mask); \ 1980 return true; \ 1981 } \ 1982 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 1983 cat3(arg_, name, _ir) * a) \ 1984 { \ 1985 TCGv mask; \ 1986 mask = tcg_const_i32(1 << a->imm); \ 1987 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 1988 return true; \ 1989 } \ 1990 static bool cat3(trans_, name, _rr)(DisasContext *ctx, \ 1991 cat3(arg_, name, _rr) * a) \ 1992 { \ 1993 TCGv mask, b; \ 1994 mask = tcg_const_i32(1); \ 1995 b = tcg_temp_new(); \ 1996 tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ 1997 tcg_gen_shl_i32(mask, mask, b); \ 1998 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 1999 return true; \ 2000 } \ 2001 static bool cat3(trans_, name, _rm)(DisasContext *ctx, \ 2002 cat3(arg_, name, _rm) * a) \ 2003 { \ 2004 TCGv mask, mem, addr, b; \ 2005 mask = tcg_const_i32(1); \ 2006 b = tcg_temp_new(); \ 2007 tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \ 2008 tcg_gen_shl_i32(mask, mask, b); \ 2009 mem = tcg_temp_new(); \ 2010 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 2011 cat3(rx_, op, m)(addr, mask); \ 2012 return true; \ 2013 } 2014 2015 BITOP(BSET, bset) 2016 BITOP(BCLR, bclr) 2017 BITOP(BTST, btst) 2018 BITOP(BNOT, bnot) 2019 2020 static inline void bmcnd_op(TCGv val, TCGCond cond, int pos) 2021 { 2022 TCGv bit; 2023 DisasCompare dc; 2024 dc.temp = tcg_temp_new(); 2025 bit = tcg_temp_new(); 2026 psw_cond(&dc, cond); 2027 tcg_gen_andi_i32(val, val, ~(1 << pos)); 2028 tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0); 2029 tcg_gen_deposit_i32(val, val, bit, pos, 1); 2030 } 2031 2032 /* bmcnd #imm, dsp[rd] */ 2033 static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) 2034 { 2035 TCGv val, mem, addr; 2036 val = tcg_temp_new(); 2037 mem = tcg_temp_new(); 2038 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); 2039 rx_gen_ld(MO_8, val, addr); 2040 bmcnd_op(val, a->cd, a->imm); 2041 rx_gen_st(MO_8, val, addr); 2042 return true; 2043 } 2044 2045 /* bmcond #imm, rd */ 2046 static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a) 2047 { 2048 bmcnd_op(cpu_regs[a->rd], a->cd, a->imm); 2049 return true; 2050 } 2051 2052 enum { 2053 PSW_C = 0, 2054 PSW_Z = 1, 2055 PSW_S = 2, 2056 PSW_O = 3, 2057 PSW_I = 8, 2058 PSW_U = 9, 2059 }; 2060 2061 static inline void clrsetpsw(DisasContext *ctx, int cb, int val) 2062 { 2063 if (cb < 8) { 2064 switch (cb) { 2065 case PSW_C: 2066 tcg_gen_movi_i32(cpu_psw_c, val); 2067 break; 2068 case PSW_Z: 2069 tcg_gen_movi_i32(cpu_psw_z, val == 0); 2070 break; 2071 case PSW_S: 2072 tcg_gen_movi_i32(cpu_psw_s, val ? -1 : 0); 2073 break; 2074 case PSW_O: 2075 tcg_gen_movi_i32(cpu_psw_o, val << 31); 2076 break; 2077 default: 2078 qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); 2079 break; 2080 } 2081 } else if (is_privileged(ctx, 0)) { 2082 switch (cb) { 2083 case PSW_I: 2084 tcg_gen_movi_i32(cpu_psw_i, val); 2085 ctx->base.is_jmp = DISAS_UPDATE; 2086 break; 2087 case PSW_U: 2088 if (FIELD_EX32(ctx->tb_flags, PSW, U) != val) { 2089 ctx->tb_flags = FIELD_DP32(ctx->tb_flags, PSW, U, val); 2090 tcg_gen_movi_i32(cpu_psw_u, val); 2091 tcg_gen_mov_i32(val ? cpu_isp : cpu_usp, cpu_sp); 2092 tcg_gen_mov_i32(cpu_sp, val ? cpu_usp : cpu_isp); 2093 } 2094 break; 2095 default: 2096 qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); 2097 break; 2098 } 2099 } 2100 } 2101 2102 /* clrpsw psw */ 2103 static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a) 2104 { 2105 clrsetpsw(ctx, a->cb, 0); 2106 return true; 2107 } 2108 2109 /* setpsw psw */ 2110 static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a) 2111 { 2112 clrsetpsw(ctx, a->cb, 1); 2113 return true; 2114 } 2115 2116 /* mvtipl #imm */ 2117 static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a) 2118 { 2119 if (is_privileged(ctx, 1)) { 2120 tcg_gen_movi_i32(cpu_psw_ipl, a->imm); 2121 ctx->base.is_jmp = DISAS_UPDATE; 2122 } 2123 return true; 2124 } 2125 2126 /* mvtc #imm, rd */ 2127 static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) 2128 { 2129 TCGv imm; 2130 2131 imm = tcg_const_i32(a->imm); 2132 move_to_cr(ctx, imm, a->cr); 2133 return true; 2134 } 2135 2136 /* mvtc rs, rd */ 2137 static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) 2138 { 2139 move_to_cr(ctx, cpu_regs[a->rs], a->cr); 2140 return true; 2141 } 2142 2143 /* mvfc rs, rd */ 2144 static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) 2145 { 2146 move_from_cr(ctx, cpu_regs[a->rd], a->cr, ctx->pc); 2147 return true; 2148 } 2149 2150 /* rtfi */ 2151 static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) 2152 { 2153 TCGv psw; 2154 if (is_privileged(ctx, 1)) { 2155 psw = tcg_temp_new(); 2156 tcg_gen_mov_i32(cpu_pc, cpu_bpc); 2157 tcg_gen_mov_i32(psw, cpu_bpsw); 2158 gen_helper_set_psw_rte(cpu_env, psw); 2159 ctx->base.is_jmp = DISAS_EXIT; 2160 } 2161 return true; 2162 } 2163 2164 /* rte */ 2165 static bool trans_RTE(DisasContext *ctx, arg_RTE *a) 2166 { 2167 TCGv psw; 2168 if (is_privileged(ctx, 1)) { 2169 psw = tcg_temp_new(); 2170 pop(cpu_pc); 2171 pop(psw); 2172 gen_helper_set_psw_rte(cpu_env, psw); 2173 ctx->base.is_jmp = DISAS_EXIT; 2174 } 2175 return true; 2176 } 2177 2178 /* brk */ 2179 static bool trans_BRK(DisasContext *ctx, arg_BRK *a) 2180 { 2181 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2182 gen_helper_rxbrk(cpu_env); 2183 ctx->base.is_jmp = DISAS_NORETURN; 2184 return true; 2185 } 2186 2187 /* int #imm */ 2188 static bool trans_INT(DisasContext *ctx, arg_INT *a) 2189 { 2190 TCGv vec; 2191 2192 tcg_debug_assert(a->imm < 0x100); 2193 vec = tcg_const_i32(a->imm); 2194 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2195 gen_helper_rxint(cpu_env, vec); 2196 ctx->base.is_jmp = DISAS_NORETURN; 2197 return true; 2198 } 2199 2200 /* wait */ 2201 static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) 2202 { 2203 if (is_privileged(ctx, 1)) { 2204 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2205 gen_helper_wait(cpu_env); 2206 } 2207 return true; 2208 } 2209 2210 static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 2211 { 2212 CPURXState *env = cs->env_ptr; 2213 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2214 ctx->env = env; 2215 ctx->tb_flags = ctx->base.tb->flags; 2216 } 2217 2218 static void rx_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) 2219 { 2220 } 2221 2222 static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 2223 { 2224 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2225 2226 tcg_gen_insn_start(ctx->base.pc_next); 2227 } 2228 2229 static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 2230 { 2231 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2232 uint32_t insn; 2233 2234 ctx->pc = ctx->base.pc_next; 2235 insn = decode_load(ctx); 2236 if (!decode(ctx, insn)) { 2237 gen_helper_raise_illegal_instruction(cpu_env); 2238 } 2239 } 2240 2241 static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 2242 { 2243 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2244 2245 switch (ctx->base.is_jmp) { 2246 case DISAS_NEXT: 2247 case DISAS_TOO_MANY: 2248 gen_goto_tb(ctx, 0, dcbase->pc_next); 2249 break; 2250 case DISAS_JUMP: 2251 tcg_gen_lookup_and_goto_ptr(); 2252 break; 2253 case DISAS_UPDATE: 2254 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2255 /* fall through */ 2256 case DISAS_EXIT: 2257 tcg_gen_exit_tb(NULL, 0); 2258 break; 2259 case DISAS_NORETURN: 2260 break; 2261 default: 2262 g_assert_not_reached(); 2263 } 2264 } 2265 2266 static void rx_tr_disas_log(const DisasContextBase *dcbase, 2267 CPUState *cs, FILE *logfile) 2268 { 2269 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 2270 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 2271 } 2272 2273 static const TranslatorOps rx_tr_ops = { 2274 .init_disas_context = rx_tr_init_disas_context, 2275 .tb_start = rx_tr_tb_start, 2276 .insn_start = rx_tr_insn_start, 2277 .translate_insn = rx_tr_translate_insn, 2278 .tb_stop = rx_tr_tb_stop, 2279 .disas_log = rx_tr_disas_log, 2280 }; 2281 2282 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 2283 target_ulong pc, void *host_pc) 2284 { 2285 DisasContext dc; 2286 2287 translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base); 2288 } 2289 2290 #define ALLOC_REGISTER(sym, name) \ 2291 cpu_##sym = tcg_global_mem_new_i32(cpu_env, \ 2292 offsetof(CPURXState, sym), name) 2293 2294 void rx_translate_init(void) 2295 { 2296 static const char * const regnames[NUM_REGS] = { 2297 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", 2298 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15" 2299 }; 2300 int i; 2301 2302 for (i = 0; i < NUM_REGS; i++) { 2303 cpu_regs[i] = tcg_global_mem_new_i32(cpu_env, 2304 offsetof(CPURXState, regs[i]), 2305 regnames[i]); 2306 } 2307 ALLOC_REGISTER(pc, "PC"); 2308 ALLOC_REGISTER(psw_o, "PSW(O)"); 2309 ALLOC_REGISTER(psw_s, "PSW(S)"); 2310 ALLOC_REGISTER(psw_z, "PSW(Z)"); 2311 ALLOC_REGISTER(psw_c, "PSW(C)"); 2312 ALLOC_REGISTER(psw_u, "PSW(U)"); 2313 ALLOC_REGISTER(psw_i, "PSW(I)"); 2314 ALLOC_REGISTER(psw_pm, "PSW(PM)"); 2315 ALLOC_REGISTER(psw_ipl, "PSW(IPL)"); 2316 ALLOC_REGISTER(usp, "USP"); 2317 ALLOC_REGISTER(fpsw, "FPSW"); 2318 ALLOC_REGISTER(bpsw, "BPSW"); 2319 ALLOC_REGISTER(bpc, "BPC"); 2320 ALLOC_REGISTER(isp, "ISP"); 2321 ALLOC_REGISTER(fintv, "FINTV"); 2322 ALLOC_REGISTER(intb, "INTB"); 2323 cpu_acc = tcg_global_mem_new_i64(cpu_env, 2324 offsetof(CPURXState, acc), "ACC"); 2325 } 2326