1 /* 2 * RX translation 3 * 4 * Copyright (c) 2019 Yoshinori Sato 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/bswap.h" 21 #include "qemu/qemu-print.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "tcg/tcg-op.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 #include "exec/translator.h" 29 #include "exec/log.h" 30 31 #define HELPER_H "helper.h" 32 #include "exec/helper-info.c.inc" 33 #undef HELPER_H 34 35 36 typedef struct DisasContext { 37 DisasContextBase base; 38 CPURXState *env; 39 uint32_t pc; 40 uint32_t tb_flags; 41 } DisasContext; 42 43 typedef struct DisasCompare { 44 TCGv value; 45 TCGv temp; 46 TCGCond cond; 47 } DisasCompare; 48 49 const char *rx_crname(uint8_t cr) 50 { 51 static const char *cr_names[] = { 52 "psw", "pc", "usp", "fpsw", "", "", "", "", 53 "bpsw", "bpc", "isp", "fintv", "intb", "", "", "" 54 }; 55 if (cr >= ARRAY_SIZE(cr_names)) { 56 return "illegal"; 57 } 58 return cr_names[cr]; 59 } 60 61 /* Target-specific values for dc->base.is_jmp. */ 62 #define DISAS_JUMP DISAS_TARGET_0 63 #define DISAS_UPDATE DISAS_TARGET_1 64 #define DISAS_EXIT DISAS_TARGET_2 65 66 /* global register indexes */ 67 static TCGv cpu_regs[16]; 68 static TCGv cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c; 69 static TCGv cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl; 70 static TCGv cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp; 71 static TCGv cpu_fintv, cpu_intb, cpu_pc; 72 static TCGv_i64 cpu_acc; 73 74 #define cpu_sp cpu_regs[0] 75 76 /* decoder helper */ 77 static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, 78 int i, int n) 79 { 80 while (++i <= n) { 81 uint8_t b = cpu_ldub_code(ctx->env, ctx->base.pc_next++); 82 insn |= b << (32 - i * 8); 83 } 84 return insn; 85 } 86 87 static uint32_t li(DisasContext *ctx, int sz) 88 { 89 int32_t tmp, addr; 90 CPURXState *env = ctx->env; 91 addr = ctx->base.pc_next; 92 93 tcg_debug_assert(sz < 4); 94 switch (sz) { 95 case 1: 96 ctx->base.pc_next += 1; 97 return cpu_ldsb_code(env, addr); 98 case 2: 99 ctx->base.pc_next += 2; 100 return cpu_ldsw_code(env, addr); 101 case 3: 102 ctx->base.pc_next += 3; 103 tmp = cpu_ldsb_code(env, addr + 2) << 16; 104 tmp |= cpu_lduw_code(env, addr) & 0xffff; 105 return tmp; 106 case 0: 107 ctx->base.pc_next += 4; 108 return cpu_ldl_code(env, addr); 109 } 110 return 0; 111 } 112 113 static int bdsp_s(DisasContext *ctx, int d) 114 { 115 /* 116 * 0 -> 8 117 * 1 -> 9 118 * 2 -> 10 119 * 3 -> 3 120 * : 121 * 7 -> 7 122 */ 123 if (d < 3) { 124 d += 8; 125 } 126 return d; 127 } 128 129 /* Include the auto-generated decoder. */ 130 #include "decode-insns.c.inc" 131 132 void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) 133 { 134 CPURXState *env = cpu_env(cs); 135 int i; 136 uint32_t psw; 137 138 psw = rx_cpu_pack_psw(env); 139 qemu_fprintf(f, "pc=0x%08x psw=0x%08x\n", 140 env->pc, psw); 141 for (i = 0; i < 16; i += 4) { 142 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", 143 i, env->regs[i], i + 1, env->regs[i + 1], 144 i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]); 145 } 146 } 147 148 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) 149 { 150 if (translator_use_goto_tb(&dc->base, dest)) { 151 tcg_gen_goto_tb(n); 152 tcg_gen_movi_i32(cpu_pc, dest); 153 tcg_gen_exit_tb(dc->base.tb, n); 154 } else { 155 tcg_gen_movi_i32(cpu_pc, dest); 156 tcg_gen_lookup_and_goto_ptr(); 157 } 158 dc->base.is_jmp = DISAS_NORETURN; 159 } 160 161 /* generic load wrapper */ 162 static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem) 163 { 164 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); 165 } 166 167 /* unsigned load wrapper */ 168 static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem) 169 { 170 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); 171 } 172 173 /* generic store wrapper */ 174 static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem) 175 { 176 tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); 177 } 178 179 /* [ri, rb] */ 180 static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem, 181 int size, int ri, int rb) 182 { 183 tcg_gen_shli_i32(mem, cpu_regs[ri], size); 184 tcg_gen_add_i32(mem, mem, cpu_regs[rb]); 185 } 186 187 /* dsp[reg] */ 188 static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem, 189 int ld, int size, int reg) 190 { 191 uint32_t dsp; 192 193 tcg_debug_assert(ld < 3); 194 switch (ld) { 195 case 0: 196 return cpu_regs[reg]; 197 case 1: 198 dsp = cpu_ldub_code(ctx->env, ctx->base.pc_next) << size; 199 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 200 ctx->base.pc_next += 1; 201 return mem; 202 case 2: 203 dsp = cpu_lduw_code(ctx->env, ctx->base.pc_next) << size; 204 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 205 ctx->base.pc_next += 2; 206 return mem; 207 } 208 return NULL; 209 } 210 211 static inline MemOp mi_to_mop(unsigned mi) 212 { 213 static const MemOp mop[5] = { MO_SB, MO_SW, MO_UL, MO_UW, MO_UB }; 214 tcg_debug_assert(mi < 5); 215 return mop[mi]; 216 } 217 218 /* load source operand */ 219 static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem, 220 int ld, int mi, int rs) 221 { 222 TCGv addr; 223 MemOp mop; 224 if (ld < 3) { 225 mop = mi_to_mop(mi); 226 addr = rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs); 227 tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE); 228 return mem; 229 } else { 230 return cpu_regs[rs]; 231 } 232 } 233 234 /* Processor mode check */ 235 static int is_privileged(DisasContext *ctx, int is_exception) 236 { 237 if (FIELD_EX32(ctx->tb_flags, PSW, PM)) { 238 if (is_exception) { 239 gen_helper_raise_privilege_violation(tcg_env); 240 } 241 return 0; 242 } else { 243 return 1; 244 } 245 } 246 247 /* generate QEMU condition */ 248 static void psw_cond(DisasCompare *dc, uint32_t cond) 249 { 250 tcg_debug_assert(cond < 16); 251 switch (cond) { 252 case 0: /* z */ 253 dc->cond = TCG_COND_EQ; 254 dc->value = cpu_psw_z; 255 break; 256 case 1: /* nz */ 257 dc->cond = TCG_COND_NE; 258 dc->value = cpu_psw_z; 259 break; 260 case 2: /* c */ 261 dc->cond = TCG_COND_NE; 262 dc->value = cpu_psw_c; 263 break; 264 case 3: /* nc */ 265 dc->cond = TCG_COND_EQ; 266 dc->value = cpu_psw_c; 267 break; 268 case 4: /* gtu (C& ~Z) == 1 */ 269 case 5: /* leu (C& ~Z) == 0 */ 270 tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0); 271 tcg_gen_and_i32(dc->temp, dc->temp, cpu_psw_c); 272 dc->cond = (cond == 4) ? TCG_COND_NE : TCG_COND_EQ; 273 dc->value = dc->temp; 274 break; 275 case 6: /* pz (S == 0) */ 276 dc->cond = TCG_COND_GE; 277 dc->value = cpu_psw_s; 278 break; 279 case 7: /* n (S == 1) */ 280 dc->cond = TCG_COND_LT; 281 dc->value = cpu_psw_s; 282 break; 283 case 8: /* ge (S^O)==0 */ 284 case 9: /* lt (S^O)==1 */ 285 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 286 dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT; 287 dc->value = dc->temp; 288 break; 289 case 10: /* gt ((S^O)|Z)==0 */ 290 case 11: /* le ((S^O)|Z)==1 */ 291 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 292 tcg_gen_sari_i32(dc->temp, dc->temp, 31); 293 tcg_gen_andc_i32(dc->temp, cpu_psw_z, dc->temp); 294 dc->cond = (cond == 10) ? TCG_COND_NE : TCG_COND_EQ; 295 dc->value = dc->temp; 296 break; 297 case 12: /* o */ 298 dc->cond = TCG_COND_LT; 299 dc->value = cpu_psw_o; 300 break; 301 case 13: /* no */ 302 dc->cond = TCG_COND_GE; 303 dc->value = cpu_psw_o; 304 break; 305 case 14: /* always true */ 306 dc->cond = TCG_COND_ALWAYS; 307 dc->value = dc->temp; 308 break; 309 case 15: /* always false */ 310 dc->cond = TCG_COND_NEVER; 311 dc->value = dc->temp; 312 break; 313 } 314 } 315 316 static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc) 317 { 318 switch (cr) { 319 case 0: /* PSW */ 320 gen_helper_pack_psw(ret, tcg_env); 321 break; 322 case 1: /* PC */ 323 tcg_gen_movi_i32(ret, pc); 324 break; 325 case 2: /* USP */ 326 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 327 tcg_gen_mov_i32(ret, cpu_sp); 328 } else { 329 tcg_gen_mov_i32(ret, cpu_usp); 330 } 331 break; 332 case 3: /* FPSW */ 333 tcg_gen_mov_i32(ret, cpu_fpsw); 334 break; 335 case 8: /* BPSW */ 336 tcg_gen_mov_i32(ret, cpu_bpsw); 337 break; 338 case 9: /* BPC */ 339 tcg_gen_mov_i32(ret, cpu_bpc); 340 break; 341 case 10: /* ISP */ 342 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 343 tcg_gen_mov_i32(ret, cpu_isp); 344 } else { 345 tcg_gen_mov_i32(ret, cpu_sp); 346 } 347 break; 348 case 11: /* FINTV */ 349 tcg_gen_mov_i32(ret, cpu_fintv); 350 break; 351 case 12: /* INTB */ 352 tcg_gen_mov_i32(ret, cpu_intb); 353 break; 354 default: 355 qemu_log_mask(LOG_GUEST_ERROR, "Unimplement control register %d", cr); 356 /* Unimplement registers return 0 */ 357 tcg_gen_movi_i32(ret, 0); 358 break; 359 } 360 } 361 362 static void move_to_cr(DisasContext *ctx, TCGv val, int cr) 363 { 364 if (cr >= 8 && !is_privileged(ctx, 0)) { 365 /* Some control registers can only be written in privileged mode. */ 366 qemu_log_mask(LOG_GUEST_ERROR, 367 "disallow control register write %s", rx_crname(cr)); 368 return; 369 } 370 switch (cr) { 371 case 0: /* PSW */ 372 gen_helper_set_psw(tcg_env, val); 373 if (is_privileged(ctx, 0)) { 374 /* PSW.{I,U} may be updated here. exit TB. */ 375 ctx->base.is_jmp = DISAS_UPDATE; 376 } 377 break; 378 /* case 1: to PC not supported */ 379 case 2: /* USP */ 380 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 381 tcg_gen_mov_i32(cpu_sp, val); 382 } else { 383 tcg_gen_mov_i32(cpu_usp, val); 384 } 385 break; 386 case 3: /* FPSW */ 387 gen_helper_set_fpsw(tcg_env, val); 388 break; 389 case 8: /* BPSW */ 390 tcg_gen_mov_i32(cpu_bpsw, val); 391 break; 392 case 9: /* BPC */ 393 tcg_gen_mov_i32(cpu_bpc, val); 394 break; 395 case 10: /* ISP */ 396 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 397 tcg_gen_mov_i32(cpu_isp, val); 398 } else { 399 tcg_gen_mov_i32(cpu_sp, val); 400 } 401 break; 402 case 11: /* FINTV */ 403 tcg_gen_mov_i32(cpu_fintv, val); 404 break; 405 case 12: /* INTB */ 406 tcg_gen_mov_i32(cpu_intb, val); 407 break; 408 default: 409 qemu_log_mask(LOG_GUEST_ERROR, 410 "Unimplement control register %d", cr); 411 break; 412 } 413 } 414 415 static void push(TCGv val) 416 { 417 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 418 rx_gen_st(MO_32, val, cpu_sp); 419 } 420 421 static void pop(TCGv ret) 422 { 423 rx_gen_ld(MO_32, ret, cpu_sp); 424 tcg_gen_addi_i32(cpu_sp, cpu_sp, 4); 425 } 426 427 /* mov.<bwl> rs,dsp5[rd] */ 428 static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) 429 { 430 TCGv mem; 431 mem = tcg_temp_new(); 432 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 433 rx_gen_st(a->sz, cpu_regs[a->rs], mem); 434 return true; 435 } 436 437 /* mov.<bwl> dsp5[rs],rd */ 438 static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) 439 { 440 TCGv mem; 441 mem = tcg_temp_new(); 442 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 443 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 444 return true; 445 } 446 447 /* mov.l #uimm4,rd */ 448 /* mov.l #uimm8,rd */ 449 /* mov.l #imm,rd */ 450 static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) 451 { 452 tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); 453 return true; 454 } 455 456 /* mov.<bwl> #uimm8,dsp[rd] */ 457 /* mov.<bwl> #imm, dsp[rd] */ 458 static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) 459 { 460 TCGv imm, mem; 461 imm = tcg_constant_i32(a->imm); 462 mem = tcg_temp_new(); 463 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 464 rx_gen_st(a->sz, imm, mem); 465 return true; 466 } 467 468 /* mov.<bwl> [ri,rb],rd */ 469 static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a) 470 { 471 TCGv mem; 472 mem = tcg_temp_new(); 473 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 474 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 475 return true; 476 } 477 478 /* mov.<bwl> rd,[ri,rb] */ 479 static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) 480 { 481 TCGv mem; 482 mem = tcg_temp_new(); 483 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 484 rx_gen_st(a->sz, cpu_regs[a->rs], mem); 485 return true; 486 } 487 488 /* mov.<bwl> dsp[rs],dsp[rd] */ 489 /* mov.<bwl> rs,dsp[rd] */ 490 /* mov.<bwl> dsp[rs],rd */ 491 /* mov.<bwl> rs,rd */ 492 static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) 493 { 494 TCGv tmp, mem, addr; 495 496 if (a->lds == 3 && a->ldd == 3) { 497 /* mov.<bwl> rs,rd */ 498 tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz | MO_SIGN); 499 return true; 500 } 501 502 mem = tcg_temp_new(); 503 if (a->lds == 3) { 504 /* mov.<bwl> rs,dsp[rd] */ 505 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs); 506 rx_gen_st(a->sz, cpu_regs[a->rd], addr); 507 } else if (a->ldd == 3) { 508 /* mov.<bwl> dsp[rs],rd */ 509 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 510 rx_gen_ld(a->sz, cpu_regs[a->rd], addr); 511 } else { 512 /* mov.<bwl> dsp[rs],dsp[rd] */ 513 tmp = tcg_temp_new(); 514 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 515 rx_gen_ld(a->sz, tmp, addr); 516 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); 517 rx_gen_st(a->sz, tmp, addr); 518 } 519 return true; 520 } 521 522 /* mov.<bwl> rs,[rd+] */ 523 /* mov.<bwl> rs,[-rd] */ 524 static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) 525 { 526 TCGv val; 527 val = tcg_temp_new(); 528 tcg_gen_mov_i32(val, cpu_regs[a->rs]); 529 if (a->ad == 1) { 530 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 531 } 532 rx_gen_st(a->sz, val, cpu_regs[a->rd]); 533 if (a->ad == 0) { 534 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 535 } 536 return true; 537 } 538 539 /* mov.<bwl> [rd+],rs */ 540 /* mov.<bwl> [-rd],rs */ 541 static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) 542 { 543 TCGv val; 544 val = tcg_temp_new(); 545 if (a->ad == 1) { 546 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 547 } 548 rx_gen_ld(a->sz, val, cpu_regs[a->rd]); 549 if (a->ad == 0) { 550 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 551 } 552 tcg_gen_mov_i32(cpu_regs[a->rs], val); 553 return true; 554 } 555 556 /* movu.<bw> dsp5[rs],rd */ 557 /* movu.<bw> dsp[rs],rd */ 558 static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a) 559 { 560 TCGv mem; 561 mem = tcg_temp_new(); 562 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 563 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 564 return true; 565 } 566 567 /* movu.<bw> rs,rd */ 568 static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a) 569 { 570 tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz); 571 return true; 572 } 573 574 /* movu.<bw> [ri,rb],rd */ 575 static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a) 576 { 577 TCGv mem; 578 mem = tcg_temp_new(); 579 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 580 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 581 return true; 582 } 583 584 /* movu.<bw> [rd+],rs */ 585 /* mov.<bw> [-rd],rs */ 586 static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) 587 { 588 TCGv val; 589 val = tcg_temp_new(); 590 if (a->ad == 1) { 591 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 592 } 593 rx_gen_ldu(a->sz, val, cpu_regs[a->rd]); 594 if (a->ad == 0) { 595 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 596 } 597 tcg_gen_mov_i32(cpu_regs[a->rs], val); 598 return true; 599 } 600 601 602 /* pop rd */ 603 static bool trans_POP(DisasContext *ctx, arg_POP *a) 604 { 605 /* mov.l [r0+], rd */ 606 arg_MOV_rp mov_a; 607 mov_a.rd = 0; 608 mov_a.rs = a->rd; 609 mov_a.ad = 0; 610 mov_a.sz = MO_32; 611 trans_MOV_pr(ctx, &mov_a); 612 return true; 613 } 614 615 /* popc cr */ 616 static bool trans_POPC(DisasContext *ctx, arg_POPC *a) 617 { 618 TCGv val; 619 val = tcg_temp_new(); 620 pop(val); 621 move_to_cr(ctx, val, a->cr); 622 return true; 623 } 624 625 /* popm rd-rd2 */ 626 static bool trans_POPM(DisasContext *ctx, arg_POPM *a) 627 { 628 int r; 629 if (a->rd == 0 || a->rd >= a->rd2) { 630 qemu_log_mask(LOG_GUEST_ERROR, 631 "Invalid register ranges r%d-r%d", a->rd, a->rd2); 632 } 633 r = a->rd; 634 while (r <= a->rd2 && r < 16) { 635 pop(cpu_regs[r++]); 636 } 637 return true; 638 } 639 640 641 /* push.<bwl> rs */ 642 static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) 643 { 644 TCGv val; 645 val = tcg_temp_new(); 646 tcg_gen_mov_i32(val, cpu_regs[a->rs]); 647 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 648 rx_gen_st(a->sz, val, cpu_sp); 649 return true; 650 } 651 652 /* push.<bwl> dsp[rs] */ 653 static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) 654 { 655 TCGv mem, val, addr; 656 mem = tcg_temp_new(); 657 val = tcg_temp_new(); 658 addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs); 659 rx_gen_ld(a->sz, val, addr); 660 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 661 rx_gen_st(a->sz, val, cpu_sp); 662 return true; 663 } 664 665 /* pushc rx */ 666 static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) 667 { 668 TCGv val; 669 val = tcg_temp_new(); 670 move_from_cr(ctx, val, a->cr, ctx->pc); 671 push(val); 672 return true; 673 } 674 675 /* pushm rs-rs2 */ 676 static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) 677 { 678 int r; 679 680 if (a->rs == 0 || a->rs >= a->rs2) { 681 qemu_log_mask(LOG_GUEST_ERROR, 682 "Invalid register ranges r%d-r%d", a->rs, a->rs2); 683 } 684 r = a->rs2; 685 while (r >= a->rs && r >= 0) { 686 push(cpu_regs[r--]); 687 } 688 return true; 689 } 690 691 /* xchg rs,rd */ 692 static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) 693 { 694 TCGv tmp; 695 tmp = tcg_temp_new(); 696 tcg_gen_mov_i32(tmp, cpu_regs[a->rs]); 697 tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); 698 tcg_gen_mov_i32(cpu_regs[a->rd], tmp); 699 return true; 700 } 701 702 /* xchg dsp[rs].<mi>,rd */ 703 static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) 704 { 705 TCGv mem, addr; 706 mem = tcg_temp_new(); 707 switch (a->mi) { 708 case 0: /* dsp[rs].b */ 709 case 1: /* dsp[rs].w */ 710 case 2: /* dsp[rs].l */ 711 addr = rx_index_addr(ctx, mem, a->ld, a->mi, a->rs); 712 break; 713 case 3: /* dsp[rs].uw */ 714 case 4: /* dsp[rs].ub */ 715 addr = rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs); 716 break; 717 default: 718 g_assert_not_reached(); 719 } 720 tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd], 721 0, mi_to_mop(a->mi)); 722 return true; 723 } 724 725 static inline void stcond(TCGCond cond, int rd, int imm) 726 { 727 TCGv z; 728 TCGv _imm; 729 z = tcg_constant_i32(0); 730 _imm = tcg_constant_i32(imm); 731 tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, 732 _imm, cpu_regs[rd]); 733 } 734 735 /* stz #imm,rd */ 736 static bool trans_STZ(DisasContext *ctx, arg_STZ *a) 737 { 738 stcond(TCG_COND_EQ, a->rd, a->imm); 739 return true; 740 } 741 742 /* stnz #imm,rd */ 743 static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a) 744 { 745 stcond(TCG_COND_NE, a->rd, a->imm); 746 return true; 747 } 748 749 /* sccnd.<bwl> rd */ 750 /* sccnd.<bwl> dsp:[rd] */ 751 static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) 752 { 753 DisasCompare dc; 754 TCGv val, mem, addr; 755 dc.temp = tcg_temp_new(); 756 psw_cond(&dc, a->cd); 757 if (a->ld < 3) { 758 val = tcg_temp_new(); 759 mem = tcg_temp_new(); 760 tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0); 761 addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); 762 rx_gen_st(a->sz, val, addr); 763 } else { 764 tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); 765 } 766 return true; 767 } 768 769 /* rtsd #imm */ 770 static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a) 771 { 772 tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2); 773 pop(cpu_pc); 774 ctx->base.is_jmp = DISAS_JUMP; 775 return true; 776 } 777 778 /* rtsd #imm, rd-rd2 */ 779 static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a) 780 { 781 int dst; 782 int adj; 783 784 if (a->rd2 >= a->rd) { 785 adj = a->imm - (a->rd2 - a->rd + 1); 786 } else { 787 adj = a->imm - (15 - a->rd + 1); 788 } 789 790 tcg_gen_addi_i32(cpu_sp, cpu_sp, adj << 2); 791 dst = a->rd; 792 while (dst <= a->rd2 && dst < 16) { 793 pop(cpu_regs[dst++]); 794 } 795 pop(cpu_pc); 796 ctx->base.is_jmp = DISAS_JUMP; 797 return true; 798 } 799 800 typedef void (*op2fn)(TCGv ret, TCGv arg1); 801 typedef void (*op3fn)(TCGv ret, TCGv arg1, TCGv arg2); 802 803 static inline void rx_gen_op_rr(op2fn opr, int dst, int src) 804 { 805 opr(cpu_regs[dst], cpu_regs[src]); 806 } 807 808 static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2) 809 { 810 opr(cpu_regs[dst], cpu_regs[src], cpu_regs[src2]); 811 } 812 813 static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2) 814 { 815 TCGv imm = tcg_constant_i32(src2); 816 opr(cpu_regs[dst], cpu_regs[src], imm); 817 } 818 819 static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx, 820 int dst, int src, int ld, int mi) 821 { 822 TCGv val, mem; 823 mem = tcg_temp_new(); 824 val = rx_load_source(ctx, mem, ld, mi, src); 825 opr(cpu_regs[dst], cpu_regs[dst], val); 826 } 827 828 static void rx_and(TCGv ret, TCGv arg1, TCGv arg2) 829 { 830 tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 831 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 832 tcg_gen_mov_i32(ret, cpu_psw_s); 833 } 834 835 /* and #uimm:4, rd */ 836 /* and #imm, rd */ 837 static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a) 838 { 839 rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm); 840 return true; 841 } 842 843 /* and dsp[rs], rd */ 844 /* and rs,rd */ 845 static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a) 846 { 847 rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi); 848 return true; 849 } 850 851 /* and rs,rs2,rd */ 852 static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a) 853 { 854 rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2); 855 return true; 856 } 857 858 static void rx_or(TCGv ret, TCGv arg1, TCGv arg2) 859 { 860 tcg_gen_or_i32(cpu_psw_s, arg1, arg2); 861 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 862 tcg_gen_mov_i32(ret, cpu_psw_s); 863 } 864 865 /* or #uimm:4, rd */ 866 /* or #imm, rd */ 867 static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a) 868 { 869 rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm); 870 return true; 871 } 872 873 /* or dsp[rs], rd */ 874 /* or rs,rd */ 875 static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a) 876 { 877 rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi); 878 return true; 879 } 880 881 /* or rs,rs2,rd */ 882 static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a) 883 { 884 rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2); 885 return true; 886 } 887 888 static void rx_xor(TCGv ret, TCGv arg1, TCGv arg2) 889 { 890 tcg_gen_xor_i32(cpu_psw_s, arg1, arg2); 891 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 892 tcg_gen_mov_i32(ret, cpu_psw_s); 893 } 894 895 /* xor #imm, rd */ 896 static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a) 897 { 898 rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm); 899 return true; 900 } 901 902 /* xor dsp[rs], rd */ 903 /* xor rs,rd */ 904 static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a) 905 { 906 rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi); 907 return true; 908 } 909 910 static void rx_tst(TCGv ret, TCGv arg1, TCGv arg2) 911 { 912 tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 913 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 914 } 915 916 /* tst #imm, rd */ 917 static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a) 918 { 919 rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm); 920 return true; 921 } 922 923 /* tst dsp[rs], rd */ 924 /* tst rs, rd */ 925 static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a) 926 { 927 rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi); 928 return true; 929 } 930 931 static void rx_not(TCGv ret, TCGv arg1) 932 { 933 tcg_gen_not_i32(ret, arg1); 934 tcg_gen_mov_i32(cpu_psw_z, ret); 935 tcg_gen_mov_i32(cpu_psw_s, ret); 936 } 937 938 /* not rd */ 939 /* not rs, rd */ 940 static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a) 941 { 942 rx_gen_op_rr(rx_not, a->rd, a->rs); 943 return true; 944 } 945 946 static void rx_neg(TCGv ret, TCGv arg1) 947 { 948 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000); 949 tcg_gen_neg_i32(ret, arg1); 950 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, ret, 0); 951 tcg_gen_mov_i32(cpu_psw_z, ret); 952 tcg_gen_mov_i32(cpu_psw_s, ret); 953 } 954 955 956 /* neg rd */ 957 /* neg rs, rd */ 958 static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) 959 { 960 rx_gen_op_rr(rx_neg, a->rd, a->rs); 961 return true; 962 } 963 964 /* ret = arg1 + arg2 + psw_c */ 965 static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) 966 { 967 TCGv z = tcg_constant_i32(0); 968 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); 969 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); 970 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 971 tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); 972 tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); 973 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 974 tcg_gen_mov_i32(ret, cpu_psw_s); 975 } 976 977 /* adc #imm, rd */ 978 static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a) 979 { 980 rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm); 981 return true; 982 } 983 984 /* adc rs, rd */ 985 static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a) 986 { 987 rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs); 988 return true; 989 } 990 991 /* adc dsp[rs], rd */ 992 static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) 993 { 994 /* mi only 2 */ 995 if (a->mi != 2) { 996 return false; 997 } 998 rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi); 999 return true; 1000 } 1001 1002 /* ret = arg1 + arg2 */ 1003 static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) 1004 { 1005 TCGv z = tcg_constant_i32(0); 1006 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); 1007 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1008 tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); 1009 tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); 1010 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 1011 tcg_gen_mov_i32(ret, cpu_psw_s); 1012 } 1013 1014 /* add #uimm4, rd */ 1015 /* add #imm, rs, rd */ 1016 static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a) 1017 { 1018 rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm); 1019 return true; 1020 } 1021 1022 /* add rs, rd */ 1023 /* add dsp[rs], rd */ 1024 static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a) 1025 { 1026 rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi); 1027 return true; 1028 } 1029 1030 /* add rs, rs2, rd */ 1031 static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a) 1032 { 1033 rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2); 1034 return true; 1035 } 1036 1037 /* ret = arg1 - arg2 */ 1038 static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) 1039 { 1040 tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); 1041 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); 1042 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1043 tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); 1044 tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); 1045 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 1046 /* CMP not required return */ 1047 if (ret) { 1048 tcg_gen_mov_i32(ret, cpu_psw_s); 1049 } 1050 } 1051 1052 static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2) 1053 { 1054 rx_sub(NULL, arg1, arg2); 1055 } 1056 1057 /* ret = arg1 - arg2 - !psw_c */ 1058 /* -> ret = arg1 + ~arg2 + psw_c */ 1059 static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) 1060 { 1061 TCGv temp; 1062 temp = tcg_temp_new(); 1063 tcg_gen_not_i32(temp, arg2); 1064 rx_adc(ret, arg1, temp); 1065 } 1066 1067 /* cmp #imm4, rs2 */ 1068 /* cmp #imm8, rs2 */ 1069 /* cmp #imm, rs2 */ 1070 static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a) 1071 { 1072 rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm); 1073 return true; 1074 } 1075 1076 /* cmp rs, rs2 */ 1077 /* cmp dsp[rs], rs2 */ 1078 static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a) 1079 { 1080 rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi); 1081 return true; 1082 } 1083 1084 /* sub #imm4, rd */ 1085 static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a) 1086 { 1087 rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm); 1088 return true; 1089 } 1090 1091 /* sub rs, rd */ 1092 /* sub dsp[rs], rd */ 1093 static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a) 1094 { 1095 rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi); 1096 return true; 1097 } 1098 1099 /* sub rs2, rs, rd */ 1100 static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a) 1101 { 1102 rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs); 1103 return true; 1104 } 1105 1106 /* sbb rs, rd */ 1107 static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a) 1108 { 1109 rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs); 1110 return true; 1111 } 1112 1113 /* sbb dsp[rs], rd */ 1114 static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) 1115 { 1116 /* mi only 2 */ 1117 if (a->mi != 2) { 1118 return false; 1119 } 1120 rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi); 1121 return true; 1122 } 1123 1124 /* abs rd */ 1125 /* abs rs, rd */ 1126 static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) 1127 { 1128 rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs); 1129 return true; 1130 } 1131 1132 /* max #imm, rd */ 1133 static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a) 1134 { 1135 rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm); 1136 return true; 1137 } 1138 1139 /* max rs, rd */ 1140 /* max dsp[rs], rd */ 1141 static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a) 1142 { 1143 rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1144 return true; 1145 } 1146 1147 /* min #imm, rd */ 1148 static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a) 1149 { 1150 rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm); 1151 return true; 1152 } 1153 1154 /* min rs, rd */ 1155 /* min dsp[rs], rd */ 1156 static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a) 1157 { 1158 rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1159 return true; 1160 } 1161 1162 /* mul #uimm4, rd */ 1163 /* mul #imm, rd */ 1164 static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a) 1165 { 1166 rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm); 1167 return true; 1168 } 1169 1170 /* mul rs, rd */ 1171 /* mul dsp[rs], rd */ 1172 static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a) 1173 { 1174 rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1175 return true; 1176 } 1177 1178 /* mul rs, rs2, rd */ 1179 static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a) 1180 { 1181 rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2); 1182 return true; 1183 } 1184 1185 /* emul #imm, rd */ 1186 static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) 1187 { 1188 TCGv imm = tcg_constant_i32(a->imm); 1189 if (a->rd > 14) { 1190 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1191 } 1192 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1193 cpu_regs[a->rd], imm); 1194 return true; 1195 } 1196 1197 /* emul rs, rd */ 1198 /* emul dsp[rs], rd */ 1199 static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) 1200 { 1201 TCGv val, mem; 1202 if (a->rd > 14) { 1203 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1204 } 1205 mem = tcg_temp_new(); 1206 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1207 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1208 cpu_regs[a->rd], val); 1209 return true; 1210 } 1211 1212 /* emulu #imm, rd */ 1213 static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) 1214 { 1215 TCGv imm = tcg_constant_i32(a->imm); 1216 if (a->rd > 14) { 1217 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1218 } 1219 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1220 cpu_regs[a->rd], imm); 1221 return true; 1222 } 1223 1224 /* emulu rs, rd */ 1225 /* emulu dsp[rs], rd */ 1226 static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) 1227 { 1228 TCGv val, mem; 1229 if (a->rd > 14) { 1230 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1231 } 1232 mem = tcg_temp_new(); 1233 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1234 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1235 cpu_regs[a->rd], val); 1236 return true; 1237 } 1238 1239 static void rx_div(TCGv ret, TCGv arg1, TCGv arg2) 1240 { 1241 gen_helper_div(ret, tcg_env, arg1, arg2); 1242 } 1243 1244 static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2) 1245 { 1246 gen_helper_divu(ret, tcg_env, arg1, arg2); 1247 } 1248 1249 /* div #imm, rd */ 1250 static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a) 1251 { 1252 rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm); 1253 return true; 1254 } 1255 1256 /* div rs, rd */ 1257 /* div dsp[rs], rd */ 1258 static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a) 1259 { 1260 rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi); 1261 return true; 1262 } 1263 1264 /* divu #imm, rd */ 1265 static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a) 1266 { 1267 rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm); 1268 return true; 1269 } 1270 1271 /* divu rs, rd */ 1272 /* divu dsp[rs], rd */ 1273 static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a) 1274 { 1275 rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi); 1276 return true; 1277 } 1278 1279 1280 /* shll #imm:5, rd */ 1281 /* shll #imm:5, rs2, rd */ 1282 static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) 1283 { 1284 TCGv tmp; 1285 tmp = tcg_temp_new(); 1286 if (a->imm) { 1287 tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm); 1288 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm); 1289 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1290 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1291 tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1292 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1293 } else { 1294 tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]); 1295 tcg_gen_movi_i32(cpu_psw_c, 0); 1296 tcg_gen_movi_i32(cpu_psw_o, 0); 1297 } 1298 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1299 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1300 return true; 1301 } 1302 1303 /* shll rs, rd */ 1304 static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) 1305 { 1306 TCGLabel *noshift, *done; 1307 TCGv count, tmp; 1308 1309 noshift = gen_new_label(); 1310 done = gen_new_label(); 1311 /* if (cpu_regs[a->rs]) { */ 1312 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); 1313 count = tcg_temp_new(); 1314 tmp = tcg_temp_new(); 1315 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); 1316 tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp); 1317 tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); 1318 tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1319 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1320 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1321 tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1322 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1323 tcg_gen_br(done); 1324 /* } else { */ 1325 gen_set_label(noshift); 1326 tcg_gen_movi_i32(cpu_psw_c, 0); 1327 tcg_gen_movi_i32(cpu_psw_o, 0); 1328 /* } */ 1329 gen_set_label(done); 1330 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1331 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1332 return true; 1333 } 1334 1335 static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm, 1336 unsigned int alith) 1337 { 1338 static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1339 tcg_gen_shri_i32, tcg_gen_sari_i32, 1340 }; 1341 tcg_debug_assert(alith < 2); 1342 if (imm) { 1343 gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1); 1344 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1345 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1346 } else { 1347 tcg_gen_mov_i32(cpu_regs[rd], cpu_regs[rs]); 1348 tcg_gen_movi_i32(cpu_psw_c, 0); 1349 } 1350 tcg_gen_movi_i32(cpu_psw_o, 0); 1351 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1352 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1353 } 1354 1355 static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith) 1356 { 1357 TCGLabel *noshift, *done; 1358 TCGv count; 1359 static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1360 tcg_gen_shri_i32, tcg_gen_sari_i32, 1361 }; 1362 static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) = { 1363 tcg_gen_shr_i32, tcg_gen_sar_i32, 1364 }; 1365 tcg_debug_assert(alith < 2); 1366 noshift = gen_new_label(); 1367 done = gen_new_label(); 1368 count = tcg_temp_new(); 1369 /* if (cpu_regs[rs]) { */ 1370 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[rs], 0, noshift); 1371 tcg_gen_andi_i32(count, cpu_regs[rs], 31); 1372 tcg_gen_subi_i32(count, count, 1); 1373 gen_sXr[alith](cpu_regs[rd], cpu_regs[rd], count); 1374 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1375 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1376 tcg_gen_br(done); 1377 /* } else { */ 1378 gen_set_label(noshift); 1379 tcg_gen_movi_i32(cpu_psw_c, 0); 1380 /* } */ 1381 gen_set_label(done); 1382 tcg_gen_movi_i32(cpu_psw_o, 0); 1383 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1384 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1385 } 1386 1387 /* shar #imm:5, rd */ 1388 /* shar #imm:5, rs2, rd */ 1389 static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a) 1390 { 1391 shiftr_imm(a->rd, a->rs2, a->imm, 1); 1392 return true; 1393 } 1394 1395 /* shar rs, rd */ 1396 static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a) 1397 { 1398 shiftr_reg(a->rd, a->rs, 1); 1399 return true; 1400 } 1401 1402 /* shlr #imm:5, rd */ 1403 /* shlr #imm:5, rs2, rd */ 1404 static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a) 1405 { 1406 shiftr_imm(a->rd, a->rs2, a->imm, 0); 1407 return true; 1408 } 1409 1410 /* shlr rs, rd */ 1411 static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a) 1412 { 1413 shiftr_reg(a->rd, a->rs, 0); 1414 return true; 1415 } 1416 1417 /* rolc rd */ 1418 static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) 1419 { 1420 TCGv tmp; 1421 tmp = tcg_temp_new(); 1422 tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31); 1423 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1424 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1425 tcg_gen_mov_i32(cpu_psw_c, tmp); 1426 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1427 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1428 return true; 1429 } 1430 1431 /* rorc rd */ 1432 static bool trans_RORC(DisasContext *ctx, arg_RORC *a) 1433 { 1434 TCGv tmp; 1435 tmp = tcg_temp_new(); 1436 tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); 1437 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1438 tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, 31); 1439 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1440 tcg_gen_mov_i32(cpu_psw_c, tmp); 1441 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1442 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1443 return true; 1444 } 1445 1446 enum {ROTR = 0, ROTL = 1}; 1447 enum {ROT_IMM = 0, ROT_REG = 1}; 1448 static inline void rx_rot(int ir, int dir, int rd, int src) 1449 { 1450 switch (dir) { 1451 case ROTL: 1452 if (ir == ROT_IMM) { 1453 tcg_gen_rotli_i32(cpu_regs[rd], cpu_regs[rd], src); 1454 } else { 1455 tcg_gen_rotl_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1456 } 1457 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1458 break; 1459 case ROTR: 1460 if (ir == ROT_IMM) { 1461 tcg_gen_rotri_i32(cpu_regs[rd], cpu_regs[rd], src); 1462 } else { 1463 tcg_gen_rotr_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1464 } 1465 tcg_gen_shri_i32(cpu_psw_c, cpu_regs[rd], 31); 1466 break; 1467 } 1468 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1469 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1470 } 1471 1472 /* rotl #imm, rd */ 1473 static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a) 1474 { 1475 rx_rot(ROT_IMM, ROTL, a->rd, a->imm); 1476 return true; 1477 } 1478 1479 /* rotl rs, rd */ 1480 static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a) 1481 { 1482 rx_rot(ROT_REG, ROTL, a->rd, a->rs); 1483 return true; 1484 } 1485 1486 /* rotr #imm, rd */ 1487 static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a) 1488 { 1489 rx_rot(ROT_IMM, ROTR, a->rd, a->imm); 1490 return true; 1491 } 1492 1493 /* rotr rs, rd */ 1494 static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a) 1495 { 1496 rx_rot(ROT_REG, ROTR, a->rd, a->rs); 1497 return true; 1498 } 1499 1500 /* revl rs, rd */ 1501 static bool trans_REVL(DisasContext *ctx, arg_REVL *a) 1502 { 1503 tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]); 1504 return true; 1505 } 1506 1507 /* revw rs, rd */ 1508 static bool trans_REVW(DisasContext *ctx, arg_REVW *a) 1509 { 1510 TCGv tmp; 1511 tmp = tcg_temp_new(); 1512 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); 1513 tcg_gen_shli_i32(tmp, tmp, 8); 1514 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); 1515 tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); 1516 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1517 return true; 1518 } 1519 1520 /* conditional branch helper */ 1521 static void rx_bcnd_main(DisasContext *ctx, int cd, int dst) 1522 { 1523 DisasCompare dc; 1524 TCGLabel *t, *done; 1525 1526 switch (cd) { 1527 case 0 ... 13: 1528 dc.temp = tcg_temp_new(); 1529 psw_cond(&dc, cd); 1530 t = gen_new_label(); 1531 done = gen_new_label(); 1532 tcg_gen_brcondi_i32(dc.cond, dc.value, 0, t); 1533 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1534 tcg_gen_br(done); 1535 gen_set_label(t); 1536 gen_goto_tb(ctx, 1, ctx->pc + dst); 1537 gen_set_label(done); 1538 break; 1539 case 14: 1540 /* always true case */ 1541 gen_goto_tb(ctx, 0, ctx->pc + dst); 1542 break; 1543 case 15: 1544 /* always false case */ 1545 /* Nothing do */ 1546 break; 1547 } 1548 } 1549 1550 /* beq dsp:3 / bne dsp:3 */ 1551 /* beq dsp:8 / bne dsp:8 */ 1552 /* bc dsp:8 / bnc dsp:8 */ 1553 /* bgtu dsp:8 / bleu dsp:8 */ 1554 /* bpz dsp:8 / bn dsp:8 */ 1555 /* bge dsp:8 / blt dsp:8 */ 1556 /* bgt dsp:8 / ble dsp:8 */ 1557 /* bo dsp:8 / bno dsp:8 */ 1558 /* beq dsp:16 / bne dsp:16 */ 1559 static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a) 1560 { 1561 rx_bcnd_main(ctx, a->cd, a->dsp); 1562 return true; 1563 } 1564 1565 /* bra dsp:3 */ 1566 /* bra dsp:8 */ 1567 /* bra dsp:16 */ 1568 /* bra dsp:24 */ 1569 static bool trans_BRA(DisasContext *ctx, arg_BRA *a) 1570 { 1571 rx_bcnd_main(ctx, 14, a->dsp); 1572 return true; 1573 } 1574 1575 /* bra rs */ 1576 static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a) 1577 { 1578 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1579 ctx->base.is_jmp = DISAS_JUMP; 1580 return true; 1581 } 1582 1583 static inline void rx_save_pc(DisasContext *ctx) 1584 { 1585 TCGv pc = tcg_constant_i32(ctx->base.pc_next); 1586 push(pc); 1587 } 1588 1589 /* jmp rs */ 1590 static bool trans_JMP(DisasContext *ctx, arg_JMP *a) 1591 { 1592 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1593 ctx->base.is_jmp = DISAS_JUMP; 1594 return true; 1595 } 1596 1597 /* jsr rs */ 1598 static bool trans_JSR(DisasContext *ctx, arg_JSR *a) 1599 { 1600 rx_save_pc(ctx); 1601 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1602 ctx->base.is_jmp = DISAS_JUMP; 1603 return true; 1604 } 1605 1606 /* bsr dsp:16 */ 1607 /* bsr dsp:24 */ 1608 static bool trans_BSR(DisasContext *ctx, arg_BSR *a) 1609 { 1610 rx_save_pc(ctx); 1611 rx_bcnd_main(ctx, 14, a->dsp); 1612 return true; 1613 } 1614 1615 /* bsr rs */ 1616 static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a) 1617 { 1618 rx_save_pc(ctx); 1619 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1620 ctx->base.is_jmp = DISAS_JUMP; 1621 return true; 1622 } 1623 1624 /* rts */ 1625 static bool trans_RTS(DisasContext *ctx, arg_RTS *a) 1626 { 1627 pop(cpu_pc); 1628 ctx->base.is_jmp = DISAS_JUMP; 1629 return true; 1630 } 1631 1632 /* nop */ 1633 static bool trans_NOP(DisasContext *ctx, arg_NOP *a) 1634 { 1635 return true; 1636 } 1637 1638 /* scmpu */ 1639 static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) 1640 { 1641 gen_helper_scmpu(tcg_env); 1642 return true; 1643 } 1644 1645 /* smovu */ 1646 static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) 1647 { 1648 gen_helper_smovu(tcg_env); 1649 return true; 1650 } 1651 1652 /* smovf */ 1653 static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) 1654 { 1655 gen_helper_smovf(tcg_env); 1656 return true; 1657 } 1658 1659 /* smovb */ 1660 static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) 1661 { 1662 gen_helper_smovb(tcg_env); 1663 return true; 1664 } 1665 1666 #define STRING(op) \ 1667 do { \ 1668 TCGv size = tcg_constant_i32(a->sz); \ 1669 gen_helper_##op(tcg_env, size); \ 1670 } while (0) 1671 1672 /* suntile.<bwl> */ 1673 static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a) 1674 { 1675 STRING(suntil); 1676 return true; 1677 } 1678 1679 /* swhile.<bwl> */ 1680 static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a) 1681 { 1682 STRING(swhile); 1683 return true; 1684 } 1685 /* sstr.<bwl> */ 1686 static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a) 1687 { 1688 STRING(sstr); 1689 return true; 1690 } 1691 1692 /* rmpa.<bwl> */ 1693 static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a) 1694 { 1695 STRING(rmpa); 1696 return true; 1697 } 1698 1699 static void rx_mul64hi(TCGv_i64 ret, int rs, int rs2) 1700 { 1701 TCGv_i64 tmp0, tmp1; 1702 tmp0 = tcg_temp_new_i64(); 1703 tmp1 = tcg_temp_new_i64(); 1704 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1705 tcg_gen_sari_i64(tmp0, tmp0, 16); 1706 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1707 tcg_gen_sari_i64(tmp1, tmp1, 16); 1708 tcg_gen_mul_i64(ret, tmp0, tmp1); 1709 tcg_gen_shli_i64(ret, ret, 16); 1710 } 1711 1712 static void rx_mul64lo(TCGv_i64 ret, int rs, int rs2) 1713 { 1714 TCGv_i64 tmp0, tmp1; 1715 tmp0 = tcg_temp_new_i64(); 1716 tmp1 = tcg_temp_new_i64(); 1717 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1718 tcg_gen_ext16s_i64(tmp0, tmp0); 1719 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1720 tcg_gen_ext16s_i64(tmp1, tmp1); 1721 tcg_gen_mul_i64(ret, tmp0, tmp1); 1722 tcg_gen_shli_i64(ret, ret, 16); 1723 } 1724 1725 /* mulhi rs,rs2 */ 1726 static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a) 1727 { 1728 rx_mul64hi(cpu_acc, a->rs, a->rs2); 1729 return true; 1730 } 1731 1732 /* mullo rs,rs2 */ 1733 static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a) 1734 { 1735 rx_mul64lo(cpu_acc, a->rs, a->rs2); 1736 return true; 1737 } 1738 1739 /* machi rs,rs2 */ 1740 static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a) 1741 { 1742 TCGv_i64 tmp; 1743 tmp = tcg_temp_new_i64(); 1744 rx_mul64hi(tmp, a->rs, a->rs2); 1745 tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1746 return true; 1747 } 1748 1749 /* maclo rs,rs2 */ 1750 static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a) 1751 { 1752 TCGv_i64 tmp; 1753 tmp = tcg_temp_new_i64(); 1754 rx_mul64lo(tmp, a->rs, a->rs2); 1755 tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1756 return true; 1757 } 1758 1759 /* mvfachi rd */ 1760 static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a) 1761 { 1762 tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc); 1763 return true; 1764 } 1765 1766 /* mvfacmi rd */ 1767 static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a) 1768 { 1769 TCGv_i64 rd64; 1770 rd64 = tcg_temp_new_i64(); 1771 tcg_gen_extract_i64(rd64, cpu_acc, 16, 32); 1772 tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64); 1773 return true; 1774 } 1775 1776 /* mvtachi rs */ 1777 static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a) 1778 { 1779 TCGv_i64 rs64; 1780 rs64 = tcg_temp_new_i64(); 1781 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1782 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 32, 32); 1783 return true; 1784 } 1785 1786 /* mvtaclo rs */ 1787 static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a) 1788 { 1789 TCGv_i64 rs64; 1790 rs64 = tcg_temp_new_i64(); 1791 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1792 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 0, 32); 1793 return true; 1794 } 1795 1796 /* racw #imm */ 1797 static bool trans_RACW(DisasContext *ctx, arg_RACW *a) 1798 { 1799 TCGv imm = tcg_constant_i32(a->imm + 1); 1800 gen_helper_racw(tcg_env, imm); 1801 return true; 1802 } 1803 1804 /* sat rd */ 1805 static bool trans_SAT(DisasContext *ctx, arg_SAT *a) 1806 { 1807 TCGv tmp, z; 1808 tmp = tcg_temp_new(); 1809 z = tcg_constant_i32(0); 1810 /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */ 1811 tcg_gen_sari_i32(tmp, cpu_psw_s, 31); 1812 /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */ 1813 tcg_gen_xori_i32(tmp, tmp, 0x80000000); 1814 tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], 1815 cpu_psw_o, z, tmp, cpu_regs[a->rd]); 1816 return true; 1817 } 1818 1819 /* satr */ 1820 static bool trans_SATR(DisasContext *ctx, arg_SATR *a) 1821 { 1822 gen_helper_satr(tcg_env); 1823 return true; 1824 } 1825 1826 #define cat3(a, b, c) a##b##c 1827 #define FOP(name, op) \ 1828 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 1829 cat3(arg_, name, _ir) * a) \ 1830 { \ 1831 TCGv imm = tcg_constant_i32(li(ctx, 0)); \ 1832 gen_helper_##op(cpu_regs[a->rd], tcg_env, \ 1833 cpu_regs[a->rd], imm); \ 1834 return true; \ 1835 } \ 1836 static bool cat3(trans_, name, _mr)(DisasContext *ctx, \ 1837 cat3(arg_, name, _mr) * a) \ 1838 { \ 1839 TCGv val, mem; \ 1840 mem = tcg_temp_new(); \ 1841 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1842 gen_helper_##op(cpu_regs[a->rd], tcg_env, \ 1843 cpu_regs[a->rd], val); \ 1844 return true; \ 1845 } 1846 1847 #define FCONVOP(name, op) \ 1848 static bool trans_##name(DisasContext *ctx, arg_##name * a) \ 1849 { \ 1850 TCGv val, mem; \ 1851 mem = tcg_temp_new(); \ 1852 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1853 gen_helper_##op(cpu_regs[a->rd], tcg_env, val); \ 1854 return true; \ 1855 } 1856 1857 FOP(FADD, fadd) 1858 FOP(FSUB, fsub) 1859 FOP(FMUL, fmul) 1860 FOP(FDIV, fdiv) 1861 1862 /* fcmp #imm, rd */ 1863 static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) 1864 { 1865 TCGv imm = tcg_constant_i32(li(ctx, 0)); 1866 gen_helper_fcmp(tcg_env, cpu_regs[a->rd], imm); 1867 return true; 1868 } 1869 1870 /* fcmp dsp[rs], rd */ 1871 /* fcmp rs, rd */ 1872 static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) 1873 { 1874 TCGv val, mem; 1875 mem = tcg_temp_new(); 1876 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); 1877 gen_helper_fcmp(tcg_env, cpu_regs[a->rd], val); 1878 return true; 1879 } 1880 1881 FCONVOP(FTOI, ftoi) 1882 FCONVOP(ROUND, round) 1883 1884 /* itof rs, rd */ 1885 /* itof dsp[rs], rd */ 1886 static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a) 1887 { 1888 TCGv val, mem; 1889 mem = tcg_temp_new(); 1890 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1891 gen_helper_itof(cpu_regs[a->rd], tcg_env, val); 1892 return true; 1893 } 1894 1895 static void rx_bsetm(TCGv mem, TCGv mask) 1896 { 1897 TCGv val; 1898 val = tcg_temp_new(); 1899 rx_gen_ld(MO_8, val, mem); 1900 tcg_gen_or_i32(val, val, mask); 1901 rx_gen_st(MO_8, val, mem); 1902 } 1903 1904 static void rx_bclrm(TCGv mem, TCGv mask) 1905 { 1906 TCGv val; 1907 val = tcg_temp_new(); 1908 rx_gen_ld(MO_8, val, mem); 1909 tcg_gen_andc_i32(val, val, mask); 1910 rx_gen_st(MO_8, val, mem); 1911 } 1912 1913 static void rx_btstm(TCGv mem, TCGv mask) 1914 { 1915 TCGv val; 1916 val = tcg_temp_new(); 1917 rx_gen_ld(MO_8, val, mem); 1918 tcg_gen_and_i32(val, val, mask); 1919 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0); 1920 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 1921 } 1922 1923 static void rx_bnotm(TCGv mem, TCGv mask) 1924 { 1925 TCGv val; 1926 val = tcg_temp_new(); 1927 rx_gen_ld(MO_8, val, mem); 1928 tcg_gen_xor_i32(val, val, mask); 1929 rx_gen_st(MO_8, val, mem); 1930 } 1931 1932 static void rx_bsetr(TCGv reg, TCGv mask) 1933 { 1934 tcg_gen_or_i32(reg, reg, mask); 1935 } 1936 1937 static void rx_bclrr(TCGv reg, TCGv mask) 1938 { 1939 tcg_gen_andc_i32(reg, reg, mask); 1940 } 1941 1942 static inline void rx_btstr(TCGv reg, TCGv mask) 1943 { 1944 TCGv t0; 1945 t0 = tcg_temp_new(); 1946 tcg_gen_and_i32(t0, reg, mask); 1947 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0); 1948 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 1949 } 1950 1951 static inline void rx_bnotr(TCGv reg, TCGv mask) 1952 { 1953 tcg_gen_xor_i32(reg, reg, mask); 1954 } 1955 1956 #define BITOP(name, op) \ 1957 static bool cat3(trans_, name, _im)(DisasContext *ctx, \ 1958 cat3(arg_, name, _im) * a) \ 1959 { \ 1960 TCGv mask, mem, addr; \ 1961 mem = tcg_temp_new(); \ 1962 mask = tcg_constant_i32(1 << a->imm); \ 1963 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 1964 cat3(rx_, op, m)(addr, mask); \ 1965 return true; \ 1966 } \ 1967 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 1968 cat3(arg_, name, _ir) * a) \ 1969 { \ 1970 TCGv mask; \ 1971 mask = tcg_constant_i32(1 << a->imm); \ 1972 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 1973 return true; \ 1974 } \ 1975 static bool cat3(trans_, name, _rr)(DisasContext *ctx, \ 1976 cat3(arg_, name, _rr) * a) \ 1977 { \ 1978 TCGv mask, b; \ 1979 mask = tcg_temp_new(); \ 1980 b = tcg_temp_new(); \ 1981 tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ 1982 tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ 1983 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 1984 return true; \ 1985 } \ 1986 static bool cat3(trans_, name, _rm)(DisasContext *ctx, \ 1987 cat3(arg_, name, _rm) * a) \ 1988 { \ 1989 TCGv mask, mem, addr, b; \ 1990 mask = tcg_temp_new(); \ 1991 b = tcg_temp_new(); \ 1992 tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \ 1993 tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ 1994 mem = tcg_temp_new(); \ 1995 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 1996 cat3(rx_, op, m)(addr, mask); \ 1997 return true; \ 1998 } 1999 2000 BITOP(BSET, bset) 2001 BITOP(BCLR, bclr) 2002 BITOP(BTST, btst) 2003 BITOP(BNOT, bnot) 2004 2005 static inline void bmcnd_op(TCGv val, TCGCond cond, int pos) 2006 { 2007 TCGv bit; 2008 DisasCompare dc; 2009 dc.temp = tcg_temp_new(); 2010 bit = tcg_temp_new(); 2011 psw_cond(&dc, cond); 2012 tcg_gen_andi_i32(val, val, ~(1 << pos)); 2013 tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0); 2014 tcg_gen_deposit_i32(val, val, bit, pos, 1); 2015 } 2016 2017 /* bmcnd #imm, dsp[rd] */ 2018 static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) 2019 { 2020 TCGv val, mem, addr; 2021 val = tcg_temp_new(); 2022 mem = tcg_temp_new(); 2023 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); 2024 rx_gen_ld(MO_8, val, addr); 2025 bmcnd_op(val, a->cd, a->imm); 2026 rx_gen_st(MO_8, val, addr); 2027 return true; 2028 } 2029 2030 /* bmcond #imm, rd */ 2031 static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a) 2032 { 2033 bmcnd_op(cpu_regs[a->rd], a->cd, a->imm); 2034 return true; 2035 } 2036 2037 enum { 2038 PSW_C = 0, 2039 PSW_Z = 1, 2040 PSW_S = 2, 2041 PSW_O = 3, 2042 PSW_I = 8, 2043 PSW_U = 9, 2044 }; 2045 2046 static inline void clrsetpsw(DisasContext *ctx, int cb, int val) 2047 { 2048 if (cb < 8) { 2049 switch (cb) { 2050 case PSW_C: 2051 tcg_gen_movi_i32(cpu_psw_c, val); 2052 break; 2053 case PSW_Z: 2054 tcg_gen_movi_i32(cpu_psw_z, val == 0); 2055 break; 2056 case PSW_S: 2057 tcg_gen_movi_i32(cpu_psw_s, val ? -1 : 0); 2058 break; 2059 case PSW_O: 2060 tcg_gen_movi_i32(cpu_psw_o, val << 31); 2061 break; 2062 default: 2063 qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb); 2064 break; 2065 } 2066 } else if (is_privileged(ctx, 0)) { 2067 switch (cb) { 2068 case PSW_I: 2069 tcg_gen_movi_i32(cpu_psw_i, val); 2070 ctx->base.is_jmp = DISAS_UPDATE; 2071 break; 2072 case PSW_U: 2073 if (FIELD_EX32(ctx->tb_flags, PSW, U) != val) { 2074 ctx->tb_flags = FIELD_DP32(ctx->tb_flags, PSW, U, val); 2075 tcg_gen_movi_i32(cpu_psw_u, val); 2076 tcg_gen_mov_i32(val ? cpu_isp : cpu_usp, cpu_sp); 2077 tcg_gen_mov_i32(cpu_sp, val ? cpu_usp : cpu_isp); 2078 } 2079 break; 2080 default: 2081 qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb); 2082 break; 2083 } 2084 } 2085 } 2086 2087 /* clrpsw psw */ 2088 static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a) 2089 { 2090 clrsetpsw(ctx, a->cb, 0); 2091 return true; 2092 } 2093 2094 /* setpsw psw */ 2095 static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a) 2096 { 2097 clrsetpsw(ctx, a->cb, 1); 2098 return true; 2099 } 2100 2101 /* mvtipl #imm */ 2102 static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a) 2103 { 2104 if (is_privileged(ctx, 1)) { 2105 tcg_gen_movi_i32(cpu_psw_ipl, a->imm); 2106 ctx->base.is_jmp = DISAS_UPDATE; 2107 } 2108 return true; 2109 } 2110 2111 /* mvtc #imm, rd */ 2112 static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) 2113 { 2114 TCGv imm; 2115 2116 imm = tcg_constant_i32(a->imm); 2117 move_to_cr(ctx, imm, a->cr); 2118 return true; 2119 } 2120 2121 /* mvtc rs, rd */ 2122 static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) 2123 { 2124 move_to_cr(ctx, cpu_regs[a->rs], a->cr); 2125 return true; 2126 } 2127 2128 /* mvfc rs, rd */ 2129 static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) 2130 { 2131 move_from_cr(ctx, cpu_regs[a->rd], a->cr, ctx->pc); 2132 return true; 2133 } 2134 2135 /* rtfi */ 2136 static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) 2137 { 2138 TCGv psw; 2139 if (is_privileged(ctx, 1)) { 2140 psw = tcg_temp_new(); 2141 tcg_gen_mov_i32(cpu_pc, cpu_bpc); 2142 tcg_gen_mov_i32(psw, cpu_bpsw); 2143 gen_helper_set_psw_rte(tcg_env, psw); 2144 ctx->base.is_jmp = DISAS_EXIT; 2145 } 2146 return true; 2147 } 2148 2149 /* rte */ 2150 static bool trans_RTE(DisasContext *ctx, arg_RTE *a) 2151 { 2152 TCGv psw; 2153 if (is_privileged(ctx, 1)) { 2154 psw = tcg_temp_new(); 2155 pop(cpu_pc); 2156 pop(psw); 2157 gen_helper_set_psw_rte(tcg_env, psw); 2158 ctx->base.is_jmp = DISAS_EXIT; 2159 } 2160 return true; 2161 } 2162 2163 /* brk */ 2164 static bool trans_BRK(DisasContext *ctx, arg_BRK *a) 2165 { 2166 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2167 gen_helper_rxbrk(tcg_env); 2168 ctx->base.is_jmp = DISAS_NORETURN; 2169 return true; 2170 } 2171 2172 /* int #imm */ 2173 static bool trans_INT(DisasContext *ctx, arg_INT *a) 2174 { 2175 TCGv vec; 2176 2177 tcg_debug_assert(a->imm < 0x100); 2178 vec = tcg_constant_i32(a->imm); 2179 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2180 gen_helper_rxint(tcg_env, vec); 2181 ctx->base.is_jmp = DISAS_NORETURN; 2182 return true; 2183 } 2184 2185 /* wait */ 2186 static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) 2187 { 2188 if (is_privileged(ctx, 1)) { 2189 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2190 gen_helper_wait(tcg_env); 2191 } 2192 return true; 2193 } 2194 2195 static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 2196 { 2197 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2198 ctx->env = cpu_env(cs); 2199 ctx->tb_flags = ctx->base.tb->flags; 2200 } 2201 2202 static void rx_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) 2203 { 2204 } 2205 2206 static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 2207 { 2208 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2209 2210 tcg_gen_insn_start(ctx->base.pc_next); 2211 } 2212 2213 static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 2214 { 2215 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2216 uint32_t insn; 2217 2218 ctx->pc = ctx->base.pc_next; 2219 insn = decode_load(ctx); 2220 if (!decode(ctx, insn)) { 2221 gen_helper_raise_illegal_instruction(tcg_env); 2222 } 2223 } 2224 2225 static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 2226 { 2227 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2228 2229 switch (ctx->base.is_jmp) { 2230 case DISAS_NEXT: 2231 case DISAS_TOO_MANY: 2232 gen_goto_tb(ctx, 0, dcbase->pc_next); 2233 break; 2234 case DISAS_JUMP: 2235 tcg_gen_lookup_and_goto_ptr(); 2236 break; 2237 case DISAS_UPDATE: 2238 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2239 /* fall through */ 2240 case DISAS_EXIT: 2241 tcg_gen_exit_tb(NULL, 0); 2242 break; 2243 case DISAS_NORETURN: 2244 break; 2245 default: 2246 g_assert_not_reached(); 2247 } 2248 } 2249 2250 static void rx_tr_disas_log(const DisasContextBase *dcbase, 2251 CPUState *cs, FILE *logfile) 2252 { 2253 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 2254 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 2255 } 2256 2257 static const TranslatorOps rx_tr_ops = { 2258 .init_disas_context = rx_tr_init_disas_context, 2259 .tb_start = rx_tr_tb_start, 2260 .insn_start = rx_tr_insn_start, 2261 .translate_insn = rx_tr_translate_insn, 2262 .tb_stop = rx_tr_tb_stop, 2263 .disas_log = rx_tr_disas_log, 2264 }; 2265 2266 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 2267 vaddr pc, void *host_pc) 2268 { 2269 DisasContext dc; 2270 2271 translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base); 2272 } 2273 2274 #define ALLOC_REGISTER(sym, name) \ 2275 cpu_##sym = tcg_global_mem_new_i32(tcg_env, \ 2276 offsetof(CPURXState, sym), name) 2277 2278 void rx_translate_init(void) 2279 { 2280 static const char * const regnames[NUM_REGS] = { 2281 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", 2282 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15" 2283 }; 2284 int i; 2285 2286 for (i = 0; i < NUM_REGS; i++) { 2287 cpu_regs[i] = tcg_global_mem_new_i32(tcg_env, 2288 offsetof(CPURXState, regs[i]), 2289 regnames[i]); 2290 } 2291 ALLOC_REGISTER(pc, "PC"); 2292 ALLOC_REGISTER(psw_o, "PSW(O)"); 2293 ALLOC_REGISTER(psw_s, "PSW(S)"); 2294 ALLOC_REGISTER(psw_z, "PSW(Z)"); 2295 ALLOC_REGISTER(psw_c, "PSW(C)"); 2296 ALLOC_REGISTER(psw_u, "PSW(U)"); 2297 ALLOC_REGISTER(psw_i, "PSW(I)"); 2298 ALLOC_REGISTER(psw_pm, "PSW(PM)"); 2299 ALLOC_REGISTER(psw_ipl, "PSW(IPL)"); 2300 ALLOC_REGISTER(usp, "USP"); 2301 ALLOC_REGISTER(fpsw, "FPSW"); 2302 ALLOC_REGISTER(bpsw, "BPSW"); 2303 ALLOC_REGISTER(bpc, "BPC"); 2304 ALLOC_REGISTER(isp, "ISP"); 2305 ALLOC_REGISTER(fintv, "FINTV"); 2306 ALLOC_REGISTER(intb, "INTB"); 2307 cpu_acc = tcg_global_mem_new_i64(tcg_env, 2308 offsetof(CPURXState, acc), "ACC"); 2309 } 2310