1 /* 2 * RX translation 3 * 4 * Copyright (c) 2019 Yoshinori Sato 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/bswap.h" 21 #include "qemu/qemu-print.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "tcg/tcg-op.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 #include "exec/translator.h" 29 #include "exec/log.h" 30 31 typedef struct DisasContext { 32 DisasContextBase base; 33 CPURXState *env; 34 uint32_t pc; 35 uint32_t tb_flags; 36 } DisasContext; 37 38 typedef struct DisasCompare { 39 TCGv value; 40 TCGv temp; 41 TCGCond cond; 42 } DisasCompare; 43 44 const char *rx_crname(uint8_t cr) 45 { 46 static const char *cr_names[] = { 47 "psw", "pc", "usp", "fpsw", "", "", "", "", 48 "bpsw", "bpc", "isp", "fintv", "intb", "", "", "" 49 }; 50 if (cr >= ARRAY_SIZE(cr_names)) { 51 return "illegal"; 52 } 53 return cr_names[cr]; 54 } 55 56 /* Target-specific values for dc->base.is_jmp. */ 57 #define DISAS_JUMP DISAS_TARGET_0 58 #define DISAS_UPDATE DISAS_TARGET_1 59 #define DISAS_EXIT DISAS_TARGET_2 60 61 /* global register indexes */ 62 static TCGv cpu_regs[16]; 63 static TCGv cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c; 64 static TCGv cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl; 65 static TCGv cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp; 66 static TCGv cpu_fintv, cpu_intb, cpu_pc; 67 static TCGv_i64 cpu_acc; 68 69 #define cpu_sp cpu_regs[0] 70 71 #include "exec/gen-icount.h" 72 73 /* decoder helper */ 74 static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, 75 int i, int n) 76 { 77 while (++i <= n) { 78 uint8_t b = cpu_ldub_code(ctx->env, ctx->base.pc_next++); 79 insn |= b << (32 - i * 8); 80 } 81 return insn; 82 } 83 84 static uint32_t li(DisasContext *ctx, int sz) 85 { 86 int32_t tmp, addr; 87 CPURXState *env = ctx->env; 88 addr = ctx->base.pc_next; 89 90 tcg_debug_assert(sz < 4); 91 switch (sz) { 92 case 1: 93 ctx->base.pc_next += 1; 94 return cpu_ldsb_code(env, addr); 95 case 2: 96 ctx->base.pc_next += 2; 97 return cpu_ldsw_code(env, addr); 98 case 3: 99 ctx->base.pc_next += 3; 100 tmp = cpu_ldsb_code(env, addr + 2) << 16; 101 tmp |= cpu_lduw_code(env, addr) & 0xffff; 102 return tmp; 103 case 0: 104 ctx->base.pc_next += 4; 105 return cpu_ldl_code(env, addr); 106 } 107 return 0; 108 } 109 110 static int bdsp_s(DisasContext *ctx, int d) 111 { 112 /* 113 * 0 -> 8 114 * 1 -> 9 115 * 2 -> 10 116 * 3 -> 3 117 * : 118 * 7 -> 7 119 */ 120 if (d < 3) { 121 d += 8; 122 } 123 return d; 124 } 125 126 /* Include the auto-generated decoder. */ 127 #include "decode-insns.c.inc" 128 129 void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) 130 { 131 RXCPU *cpu = RX_CPU(cs); 132 CPURXState *env = &cpu->env; 133 int i; 134 uint32_t psw; 135 136 psw = rx_cpu_pack_psw(env); 137 qemu_fprintf(f, "pc=0x%08x psw=0x%08x\n", 138 env->pc, psw); 139 for (i = 0; i < 16; i += 4) { 140 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", 141 i, env->regs[i], i + 1, env->regs[i + 1], 142 i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]); 143 } 144 } 145 146 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) 147 { 148 if (translator_use_goto_tb(&dc->base, dest)) { 149 tcg_gen_goto_tb(n); 150 tcg_gen_movi_i32(cpu_pc, dest); 151 tcg_gen_exit_tb(dc->base.tb, n); 152 } else { 153 tcg_gen_movi_i32(cpu_pc, dest); 154 tcg_gen_lookup_and_goto_ptr(); 155 } 156 dc->base.is_jmp = DISAS_NORETURN; 157 } 158 159 /* generic load wrapper */ 160 static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem) 161 { 162 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); 163 } 164 165 /* unsigned load wrapper */ 166 static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem) 167 { 168 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); 169 } 170 171 /* generic store wrapper */ 172 static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem) 173 { 174 tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); 175 } 176 177 /* [ri, rb] */ 178 static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem, 179 int size, int ri, int rb) 180 { 181 tcg_gen_shli_i32(mem, cpu_regs[ri], size); 182 tcg_gen_add_i32(mem, mem, cpu_regs[rb]); 183 } 184 185 /* dsp[reg] */ 186 static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem, 187 int ld, int size, int reg) 188 { 189 uint32_t dsp; 190 191 tcg_debug_assert(ld < 3); 192 switch (ld) { 193 case 0: 194 return cpu_regs[reg]; 195 case 1: 196 dsp = cpu_ldub_code(ctx->env, ctx->base.pc_next) << size; 197 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 198 ctx->base.pc_next += 1; 199 return mem; 200 case 2: 201 dsp = cpu_lduw_code(ctx->env, ctx->base.pc_next) << size; 202 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 203 ctx->base.pc_next += 2; 204 return mem; 205 } 206 return NULL; 207 } 208 209 static inline MemOp mi_to_mop(unsigned mi) 210 { 211 static const MemOp mop[5] = { MO_SB, MO_SW, MO_UL, MO_UW, MO_UB }; 212 tcg_debug_assert(mi < 5); 213 return mop[mi]; 214 } 215 216 /* load source operand */ 217 static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem, 218 int ld, int mi, int rs) 219 { 220 TCGv addr; 221 MemOp mop; 222 if (ld < 3) { 223 mop = mi_to_mop(mi); 224 addr = rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs); 225 tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE); 226 return mem; 227 } else { 228 return cpu_regs[rs]; 229 } 230 } 231 232 /* Processor mode check */ 233 static int is_privileged(DisasContext *ctx, int is_exception) 234 { 235 if (FIELD_EX32(ctx->tb_flags, PSW, PM)) { 236 if (is_exception) { 237 gen_helper_raise_privilege_violation(cpu_env); 238 } 239 return 0; 240 } else { 241 return 1; 242 } 243 } 244 245 /* generate QEMU condition */ 246 static void psw_cond(DisasCompare *dc, uint32_t cond) 247 { 248 tcg_debug_assert(cond < 16); 249 switch (cond) { 250 case 0: /* z */ 251 dc->cond = TCG_COND_EQ; 252 dc->value = cpu_psw_z; 253 break; 254 case 1: /* nz */ 255 dc->cond = TCG_COND_NE; 256 dc->value = cpu_psw_z; 257 break; 258 case 2: /* c */ 259 dc->cond = TCG_COND_NE; 260 dc->value = cpu_psw_c; 261 break; 262 case 3: /* nc */ 263 dc->cond = TCG_COND_EQ; 264 dc->value = cpu_psw_c; 265 break; 266 case 4: /* gtu (C& ~Z) == 1 */ 267 case 5: /* leu (C& ~Z) == 0 */ 268 tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0); 269 tcg_gen_and_i32(dc->temp, dc->temp, cpu_psw_c); 270 dc->cond = (cond == 4) ? TCG_COND_NE : TCG_COND_EQ; 271 dc->value = dc->temp; 272 break; 273 case 6: /* pz (S == 0) */ 274 dc->cond = TCG_COND_GE; 275 dc->value = cpu_psw_s; 276 break; 277 case 7: /* n (S == 1) */ 278 dc->cond = TCG_COND_LT; 279 dc->value = cpu_psw_s; 280 break; 281 case 8: /* ge (S^O)==0 */ 282 case 9: /* lt (S^O)==1 */ 283 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 284 dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT; 285 dc->value = dc->temp; 286 break; 287 case 10: /* gt ((S^O)|Z)==0 */ 288 case 11: /* le ((S^O)|Z)==1 */ 289 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 290 tcg_gen_sari_i32(dc->temp, dc->temp, 31); 291 tcg_gen_andc_i32(dc->temp, cpu_psw_z, dc->temp); 292 dc->cond = (cond == 10) ? TCG_COND_NE : TCG_COND_EQ; 293 dc->value = dc->temp; 294 break; 295 case 12: /* o */ 296 dc->cond = TCG_COND_LT; 297 dc->value = cpu_psw_o; 298 break; 299 case 13: /* no */ 300 dc->cond = TCG_COND_GE; 301 dc->value = cpu_psw_o; 302 break; 303 case 14: /* always true */ 304 dc->cond = TCG_COND_ALWAYS; 305 dc->value = dc->temp; 306 break; 307 case 15: /* always false */ 308 dc->cond = TCG_COND_NEVER; 309 dc->value = dc->temp; 310 break; 311 } 312 } 313 314 static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc) 315 { 316 switch (cr) { 317 case 0: /* PSW */ 318 gen_helper_pack_psw(ret, cpu_env); 319 break; 320 case 1: /* PC */ 321 tcg_gen_movi_i32(ret, pc); 322 break; 323 case 2: /* USP */ 324 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 325 tcg_gen_mov_i32(ret, cpu_sp); 326 } else { 327 tcg_gen_mov_i32(ret, cpu_usp); 328 } 329 break; 330 case 3: /* FPSW */ 331 tcg_gen_mov_i32(ret, cpu_fpsw); 332 break; 333 case 8: /* BPSW */ 334 tcg_gen_mov_i32(ret, cpu_bpsw); 335 break; 336 case 9: /* BPC */ 337 tcg_gen_mov_i32(ret, cpu_bpc); 338 break; 339 case 10: /* ISP */ 340 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 341 tcg_gen_mov_i32(ret, cpu_isp); 342 } else { 343 tcg_gen_mov_i32(ret, cpu_sp); 344 } 345 break; 346 case 11: /* FINTV */ 347 tcg_gen_mov_i32(ret, cpu_fintv); 348 break; 349 case 12: /* INTB */ 350 tcg_gen_mov_i32(ret, cpu_intb); 351 break; 352 default: 353 qemu_log_mask(LOG_GUEST_ERROR, "Unimplement control register %d", cr); 354 /* Unimplement registers return 0 */ 355 tcg_gen_movi_i32(ret, 0); 356 break; 357 } 358 } 359 360 static void move_to_cr(DisasContext *ctx, TCGv val, int cr) 361 { 362 if (cr >= 8 && !is_privileged(ctx, 0)) { 363 /* Some control registers can only be written in privileged mode. */ 364 qemu_log_mask(LOG_GUEST_ERROR, 365 "disallow control register write %s", rx_crname(cr)); 366 return; 367 } 368 switch (cr) { 369 case 0: /* PSW */ 370 gen_helper_set_psw(cpu_env, val); 371 if (is_privileged(ctx, 0)) { 372 /* PSW.{I,U} may be updated here. exit TB. */ 373 ctx->base.is_jmp = DISAS_UPDATE; 374 } 375 break; 376 /* case 1: to PC not supported */ 377 case 2: /* USP */ 378 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 379 tcg_gen_mov_i32(cpu_sp, val); 380 } else { 381 tcg_gen_mov_i32(cpu_usp, val); 382 } 383 break; 384 case 3: /* FPSW */ 385 gen_helper_set_fpsw(cpu_env, val); 386 break; 387 case 8: /* BPSW */ 388 tcg_gen_mov_i32(cpu_bpsw, val); 389 break; 390 case 9: /* BPC */ 391 tcg_gen_mov_i32(cpu_bpc, val); 392 break; 393 case 10: /* ISP */ 394 if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 395 tcg_gen_mov_i32(cpu_isp, val); 396 } else { 397 tcg_gen_mov_i32(cpu_sp, val); 398 } 399 break; 400 case 11: /* FINTV */ 401 tcg_gen_mov_i32(cpu_fintv, val); 402 break; 403 case 12: /* INTB */ 404 tcg_gen_mov_i32(cpu_intb, val); 405 break; 406 default: 407 qemu_log_mask(LOG_GUEST_ERROR, 408 "Unimplement control register %d", cr); 409 break; 410 } 411 } 412 413 static void push(TCGv val) 414 { 415 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 416 rx_gen_st(MO_32, val, cpu_sp); 417 } 418 419 static void pop(TCGv ret) 420 { 421 rx_gen_ld(MO_32, ret, cpu_sp); 422 tcg_gen_addi_i32(cpu_sp, cpu_sp, 4); 423 } 424 425 /* mov.<bwl> rs,dsp5[rd] */ 426 static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) 427 { 428 TCGv mem; 429 mem = tcg_temp_new(); 430 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 431 rx_gen_st(a->sz, cpu_regs[a->rs], mem); 432 return true; 433 } 434 435 /* mov.<bwl> dsp5[rs],rd */ 436 static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) 437 { 438 TCGv mem; 439 mem = tcg_temp_new(); 440 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 441 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 442 return true; 443 } 444 445 /* mov.l #uimm4,rd */ 446 /* mov.l #uimm8,rd */ 447 /* mov.l #imm,rd */ 448 static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) 449 { 450 tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); 451 return true; 452 } 453 454 /* mov.<bwl> #uimm8,dsp[rd] */ 455 /* mov.<bwl> #imm, dsp[rd] */ 456 static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) 457 { 458 TCGv imm, mem; 459 imm = tcg_const_i32(a->imm); 460 mem = tcg_temp_new(); 461 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 462 rx_gen_st(a->sz, imm, mem); 463 return true; 464 } 465 466 /* mov.<bwl> [ri,rb],rd */ 467 static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a) 468 { 469 TCGv mem; 470 mem = tcg_temp_new(); 471 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 472 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 473 return true; 474 } 475 476 /* mov.<bwl> rd,[ri,rb] */ 477 static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) 478 { 479 TCGv mem; 480 mem = tcg_temp_new(); 481 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 482 rx_gen_st(a->sz, cpu_regs[a->rs], mem); 483 return true; 484 } 485 486 /* mov.<bwl> dsp[rs],dsp[rd] */ 487 /* mov.<bwl> rs,dsp[rd] */ 488 /* mov.<bwl> dsp[rs],rd */ 489 /* mov.<bwl> rs,rd */ 490 static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) 491 { 492 static void (* const mov[])(TCGv ret, TCGv arg) = { 493 tcg_gen_ext8s_i32, tcg_gen_ext16s_i32, tcg_gen_mov_i32, 494 }; 495 TCGv tmp, mem, addr; 496 if (a->lds == 3 && a->ldd == 3) { 497 /* mov.<bwl> rs,rd */ 498 mov[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]); 499 return true; 500 } 501 502 mem = tcg_temp_new(); 503 if (a->lds == 3) { 504 /* mov.<bwl> rs,dsp[rd] */ 505 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs); 506 rx_gen_st(a->sz, cpu_regs[a->rd], addr); 507 } else if (a->ldd == 3) { 508 /* mov.<bwl> dsp[rs],rd */ 509 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 510 rx_gen_ld(a->sz, cpu_regs[a->rd], addr); 511 } else { 512 /* mov.<bwl> dsp[rs],dsp[rd] */ 513 tmp = tcg_temp_new(); 514 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 515 rx_gen_ld(a->sz, tmp, addr); 516 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); 517 rx_gen_st(a->sz, tmp, addr); 518 } 519 return true; 520 } 521 522 /* mov.<bwl> rs,[rd+] */ 523 /* mov.<bwl> rs,[-rd] */ 524 static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) 525 { 526 TCGv val; 527 val = tcg_temp_new(); 528 tcg_gen_mov_i32(val, cpu_regs[a->rs]); 529 if (a->ad == 1) { 530 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 531 } 532 rx_gen_st(a->sz, val, cpu_regs[a->rd]); 533 if (a->ad == 0) { 534 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 535 } 536 return true; 537 } 538 539 /* mov.<bwl> [rd+],rs */ 540 /* mov.<bwl> [-rd],rs */ 541 static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) 542 { 543 TCGv val; 544 val = tcg_temp_new(); 545 if (a->ad == 1) { 546 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 547 } 548 rx_gen_ld(a->sz, val, cpu_regs[a->rd]); 549 if (a->ad == 0) { 550 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 551 } 552 tcg_gen_mov_i32(cpu_regs[a->rs], val); 553 return true; 554 } 555 556 /* movu.<bw> dsp5[rs],rd */ 557 /* movu.<bw> dsp[rs],rd */ 558 static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a) 559 { 560 TCGv mem; 561 mem = tcg_temp_new(); 562 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 563 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 564 return true; 565 } 566 567 /* movu.<bw> rs,rd */ 568 static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a) 569 { 570 static void (* const ext[])(TCGv ret, TCGv arg) = { 571 tcg_gen_ext8u_i32, tcg_gen_ext16u_i32, 572 }; 573 ext[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]); 574 return true; 575 } 576 577 /* movu.<bw> [ri,rb],rd */ 578 static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a) 579 { 580 TCGv mem; 581 mem = tcg_temp_new(); 582 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 583 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 584 return true; 585 } 586 587 /* movu.<bw> [rd+],rs */ 588 /* mov.<bw> [-rd],rs */ 589 static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) 590 { 591 TCGv val; 592 val = tcg_temp_new(); 593 if (a->ad == 1) { 594 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 595 } 596 rx_gen_ldu(a->sz, val, cpu_regs[a->rd]); 597 if (a->ad == 0) { 598 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 599 } 600 tcg_gen_mov_i32(cpu_regs[a->rs], val); 601 return true; 602 } 603 604 605 /* pop rd */ 606 static bool trans_POP(DisasContext *ctx, arg_POP *a) 607 { 608 /* mov.l [r0+], rd */ 609 arg_MOV_rp mov_a; 610 mov_a.rd = 0; 611 mov_a.rs = a->rd; 612 mov_a.ad = 0; 613 mov_a.sz = MO_32; 614 trans_MOV_pr(ctx, &mov_a); 615 return true; 616 } 617 618 /* popc cr */ 619 static bool trans_POPC(DisasContext *ctx, arg_POPC *a) 620 { 621 TCGv val; 622 val = tcg_temp_new(); 623 pop(val); 624 move_to_cr(ctx, val, a->cr); 625 return true; 626 } 627 628 /* popm rd-rd2 */ 629 static bool trans_POPM(DisasContext *ctx, arg_POPM *a) 630 { 631 int r; 632 if (a->rd == 0 || a->rd >= a->rd2) { 633 qemu_log_mask(LOG_GUEST_ERROR, 634 "Invalid register ranges r%d-r%d", a->rd, a->rd2); 635 } 636 r = a->rd; 637 while (r <= a->rd2 && r < 16) { 638 pop(cpu_regs[r++]); 639 } 640 return true; 641 } 642 643 644 /* push.<bwl> rs */ 645 static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) 646 { 647 TCGv val; 648 val = tcg_temp_new(); 649 tcg_gen_mov_i32(val, cpu_regs[a->rs]); 650 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 651 rx_gen_st(a->sz, val, cpu_sp); 652 return true; 653 } 654 655 /* push.<bwl> dsp[rs] */ 656 static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) 657 { 658 TCGv mem, val, addr; 659 mem = tcg_temp_new(); 660 val = tcg_temp_new(); 661 addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs); 662 rx_gen_ld(a->sz, val, addr); 663 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 664 rx_gen_st(a->sz, val, cpu_sp); 665 return true; 666 } 667 668 /* pushc rx */ 669 static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) 670 { 671 TCGv val; 672 val = tcg_temp_new(); 673 move_from_cr(ctx, val, a->cr, ctx->pc); 674 push(val); 675 return true; 676 } 677 678 /* pushm rs-rs2 */ 679 static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) 680 { 681 int r; 682 683 if (a->rs == 0 || a->rs >= a->rs2) { 684 qemu_log_mask(LOG_GUEST_ERROR, 685 "Invalid register ranges r%d-r%d", a->rs, a->rs2); 686 } 687 r = a->rs2; 688 while (r >= a->rs && r >= 0) { 689 push(cpu_regs[r--]); 690 } 691 return true; 692 } 693 694 /* xchg rs,rd */ 695 static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) 696 { 697 TCGv tmp; 698 tmp = tcg_temp_new(); 699 tcg_gen_mov_i32(tmp, cpu_regs[a->rs]); 700 tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); 701 tcg_gen_mov_i32(cpu_regs[a->rd], tmp); 702 return true; 703 } 704 705 /* xchg dsp[rs].<mi>,rd */ 706 static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) 707 { 708 TCGv mem, addr; 709 mem = tcg_temp_new(); 710 switch (a->mi) { 711 case 0: /* dsp[rs].b */ 712 case 1: /* dsp[rs].w */ 713 case 2: /* dsp[rs].l */ 714 addr = rx_index_addr(ctx, mem, a->ld, a->mi, a->rs); 715 break; 716 case 3: /* dsp[rs].uw */ 717 case 4: /* dsp[rs].ub */ 718 addr = rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs); 719 break; 720 default: 721 g_assert_not_reached(); 722 } 723 tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd], 724 0, mi_to_mop(a->mi)); 725 return true; 726 } 727 728 static inline void stcond(TCGCond cond, int rd, int imm) 729 { 730 TCGv z; 731 TCGv _imm; 732 z = tcg_const_i32(0); 733 _imm = tcg_const_i32(imm); 734 tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, 735 _imm, cpu_regs[rd]); 736 } 737 738 /* stz #imm,rd */ 739 static bool trans_STZ(DisasContext *ctx, arg_STZ *a) 740 { 741 stcond(TCG_COND_EQ, a->rd, a->imm); 742 return true; 743 } 744 745 /* stnz #imm,rd */ 746 static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a) 747 { 748 stcond(TCG_COND_NE, a->rd, a->imm); 749 return true; 750 } 751 752 /* sccnd.<bwl> rd */ 753 /* sccnd.<bwl> dsp:[rd] */ 754 static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) 755 { 756 DisasCompare dc; 757 TCGv val, mem, addr; 758 dc.temp = tcg_temp_new(); 759 psw_cond(&dc, a->cd); 760 if (a->ld < 3) { 761 val = tcg_temp_new(); 762 mem = tcg_temp_new(); 763 tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0); 764 addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); 765 rx_gen_st(a->sz, val, addr); 766 } else { 767 tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); 768 } 769 return true; 770 } 771 772 /* rtsd #imm */ 773 static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a) 774 { 775 tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2); 776 pop(cpu_pc); 777 ctx->base.is_jmp = DISAS_JUMP; 778 return true; 779 } 780 781 /* rtsd #imm, rd-rd2 */ 782 static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a) 783 { 784 int dst; 785 int adj; 786 787 if (a->rd2 >= a->rd) { 788 adj = a->imm - (a->rd2 - a->rd + 1); 789 } else { 790 adj = a->imm - (15 - a->rd + 1); 791 } 792 793 tcg_gen_addi_i32(cpu_sp, cpu_sp, adj << 2); 794 dst = a->rd; 795 while (dst <= a->rd2 && dst < 16) { 796 pop(cpu_regs[dst++]); 797 } 798 pop(cpu_pc); 799 ctx->base.is_jmp = DISAS_JUMP; 800 return true; 801 } 802 803 typedef void (*op2fn)(TCGv ret, TCGv arg1); 804 typedef void (*op3fn)(TCGv ret, TCGv arg1, TCGv arg2); 805 806 static inline void rx_gen_op_rr(op2fn opr, int dst, int src) 807 { 808 opr(cpu_regs[dst], cpu_regs[src]); 809 } 810 811 static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2) 812 { 813 opr(cpu_regs[dst], cpu_regs[src], cpu_regs[src2]); 814 } 815 816 static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2) 817 { 818 TCGv imm = tcg_const_i32(src2); 819 opr(cpu_regs[dst], cpu_regs[src], imm); 820 } 821 822 static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx, 823 int dst, int src, int ld, int mi) 824 { 825 TCGv val, mem; 826 mem = tcg_temp_new(); 827 val = rx_load_source(ctx, mem, ld, mi, src); 828 opr(cpu_regs[dst], cpu_regs[dst], val); 829 } 830 831 static void rx_and(TCGv ret, TCGv arg1, TCGv arg2) 832 { 833 tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 834 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 835 tcg_gen_mov_i32(ret, cpu_psw_s); 836 } 837 838 /* and #uimm:4, rd */ 839 /* and #imm, rd */ 840 static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a) 841 { 842 rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm); 843 return true; 844 } 845 846 /* and dsp[rs], rd */ 847 /* and rs,rd */ 848 static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a) 849 { 850 rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi); 851 return true; 852 } 853 854 /* and rs,rs2,rd */ 855 static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a) 856 { 857 rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2); 858 return true; 859 } 860 861 static void rx_or(TCGv ret, TCGv arg1, TCGv arg2) 862 { 863 tcg_gen_or_i32(cpu_psw_s, arg1, arg2); 864 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 865 tcg_gen_mov_i32(ret, cpu_psw_s); 866 } 867 868 /* or #uimm:4, rd */ 869 /* or #imm, rd */ 870 static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a) 871 { 872 rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm); 873 return true; 874 } 875 876 /* or dsp[rs], rd */ 877 /* or rs,rd */ 878 static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a) 879 { 880 rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi); 881 return true; 882 } 883 884 /* or rs,rs2,rd */ 885 static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a) 886 { 887 rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2); 888 return true; 889 } 890 891 static void rx_xor(TCGv ret, TCGv arg1, TCGv arg2) 892 { 893 tcg_gen_xor_i32(cpu_psw_s, arg1, arg2); 894 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 895 tcg_gen_mov_i32(ret, cpu_psw_s); 896 } 897 898 /* xor #imm, rd */ 899 static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a) 900 { 901 rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm); 902 return true; 903 } 904 905 /* xor dsp[rs], rd */ 906 /* xor rs,rd */ 907 static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a) 908 { 909 rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi); 910 return true; 911 } 912 913 static void rx_tst(TCGv ret, TCGv arg1, TCGv arg2) 914 { 915 tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 916 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 917 } 918 919 /* tst #imm, rd */ 920 static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a) 921 { 922 rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm); 923 return true; 924 } 925 926 /* tst dsp[rs], rd */ 927 /* tst rs, rd */ 928 static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a) 929 { 930 rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi); 931 return true; 932 } 933 934 static void rx_not(TCGv ret, TCGv arg1) 935 { 936 tcg_gen_not_i32(ret, arg1); 937 tcg_gen_mov_i32(cpu_psw_z, ret); 938 tcg_gen_mov_i32(cpu_psw_s, ret); 939 } 940 941 /* not rd */ 942 /* not rs, rd */ 943 static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a) 944 { 945 rx_gen_op_rr(rx_not, a->rd, a->rs); 946 return true; 947 } 948 949 static void rx_neg(TCGv ret, TCGv arg1) 950 { 951 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000); 952 tcg_gen_neg_i32(ret, arg1); 953 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, ret, 0); 954 tcg_gen_mov_i32(cpu_psw_z, ret); 955 tcg_gen_mov_i32(cpu_psw_s, ret); 956 } 957 958 959 /* neg rd */ 960 /* neg rs, rd */ 961 static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) 962 { 963 rx_gen_op_rr(rx_neg, a->rd, a->rs); 964 return true; 965 } 966 967 /* ret = arg1 + arg2 + psw_c */ 968 static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) 969 { 970 TCGv z; 971 z = tcg_const_i32(0); 972 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); 973 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); 974 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 975 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 976 tcg_gen_xor_i32(z, arg1, arg2); 977 tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); 978 tcg_gen_mov_i32(ret, cpu_psw_s); 979 } 980 981 /* adc #imm, rd */ 982 static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a) 983 { 984 rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm); 985 return true; 986 } 987 988 /* adc rs, rd */ 989 static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a) 990 { 991 rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs); 992 return true; 993 } 994 995 /* adc dsp[rs], rd */ 996 static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) 997 { 998 /* mi only 2 */ 999 if (a->mi != 2) { 1000 return false; 1001 } 1002 rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi); 1003 return true; 1004 } 1005 1006 /* ret = arg1 + arg2 */ 1007 static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) 1008 { 1009 TCGv z; 1010 z = tcg_const_i32(0); 1011 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); 1012 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 1013 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1014 tcg_gen_xor_i32(z, arg1, arg2); 1015 tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); 1016 tcg_gen_mov_i32(ret, cpu_psw_s); 1017 } 1018 1019 /* add #uimm4, rd */ 1020 /* add #imm, rs, rd */ 1021 static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a) 1022 { 1023 rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm); 1024 return true; 1025 } 1026 1027 /* add rs, rd */ 1028 /* add dsp[rs], rd */ 1029 static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a) 1030 { 1031 rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi); 1032 return true; 1033 } 1034 1035 /* add rs, rs2, rd */ 1036 static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a) 1037 { 1038 rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2); 1039 return true; 1040 } 1041 1042 /* ret = arg1 - arg2 */ 1043 static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) 1044 { 1045 TCGv temp; 1046 tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); 1047 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 1048 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); 1049 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1050 temp = tcg_temp_new_i32(); 1051 tcg_gen_xor_i32(temp, arg1, arg2); 1052 tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp); 1053 /* CMP not required return */ 1054 if (ret) { 1055 tcg_gen_mov_i32(ret, cpu_psw_s); 1056 } 1057 } 1058 static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2) 1059 { 1060 rx_sub(NULL, arg1, arg2); 1061 } 1062 /* ret = arg1 - arg2 - !psw_c */ 1063 /* -> ret = arg1 + ~arg2 + psw_c */ 1064 static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) 1065 { 1066 TCGv temp; 1067 temp = tcg_temp_new(); 1068 tcg_gen_not_i32(temp, arg2); 1069 rx_adc(ret, arg1, temp); 1070 } 1071 1072 /* cmp #imm4, rs2 */ 1073 /* cmp #imm8, rs2 */ 1074 /* cmp #imm, rs2 */ 1075 static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a) 1076 { 1077 rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm); 1078 return true; 1079 } 1080 1081 /* cmp rs, rs2 */ 1082 /* cmp dsp[rs], rs2 */ 1083 static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a) 1084 { 1085 rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi); 1086 return true; 1087 } 1088 1089 /* sub #imm4, rd */ 1090 static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a) 1091 { 1092 rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm); 1093 return true; 1094 } 1095 1096 /* sub rs, rd */ 1097 /* sub dsp[rs], rd */ 1098 static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a) 1099 { 1100 rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi); 1101 return true; 1102 } 1103 1104 /* sub rs2, rs, rd */ 1105 static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a) 1106 { 1107 rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs); 1108 return true; 1109 } 1110 1111 /* sbb rs, rd */ 1112 static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a) 1113 { 1114 rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs); 1115 return true; 1116 } 1117 1118 /* sbb dsp[rs], rd */ 1119 static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) 1120 { 1121 /* mi only 2 */ 1122 if (a->mi != 2) { 1123 return false; 1124 } 1125 rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi); 1126 return true; 1127 } 1128 1129 /* abs rd */ 1130 /* abs rs, rd */ 1131 static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) 1132 { 1133 rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs); 1134 return true; 1135 } 1136 1137 /* max #imm, rd */ 1138 static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a) 1139 { 1140 rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm); 1141 return true; 1142 } 1143 1144 /* max rs, rd */ 1145 /* max dsp[rs], rd */ 1146 static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a) 1147 { 1148 rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1149 return true; 1150 } 1151 1152 /* min #imm, rd */ 1153 static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a) 1154 { 1155 rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm); 1156 return true; 1157 } 1158 1159 /* min rs, rd */ 1160 /* min dsp[rs], rd */ 1161 static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a) 1162 { 1163 rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1164 return true; 1165 } 1166 1167 /* mul #uimm4, rd */ 1168 /* mul #imm, rd */ 1169 static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a) 1170 { 1171 rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm); 1172 return true; 1173 } 1174 1175 /* mul rs, rd */ 1176 /* mul dsp[rs], rd */ 1177 static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a) 1178 { 1179 rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1180 return true; 1181 } 1182 1183 /* mul rs, rs2, rd */ 1184 static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a) 1185 { 1186 rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2); 1187 return true; 1188 } 1189 1190 /* emul #imm, rd */ 1191 static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) 1192 { 1193 TCGv imm = tcg_const_i32(a->imm); 1194 if (a->rd > 14) { 1195 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1196 } 1197 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1198 cpu_regs[a->rd], imm); 1199 return true; 1200 } 1201 1202 /* emul rs, rd */ 1203 /* emul dsp[rs], rd */ 1204 static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) 1205 { 1206 TCGv val, mem; 1207 if (a->rd > 14) { 1208 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1209 } 1210 mem = tcg_temp_new(); 1211 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1212 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1213 cpu_regs[a->rd], val); 1214 return true; 1215 } 1216 1217 /* emulu #imm, rd */ 1218 static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) 1219 { 1220 TCGv imm = tcg_const_i32(a->imm); 1221 if (a->rd > 14) { 1222 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1223 } 1224 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1225 cpu_regs[a->rd], imm); 1226 return true; 1227 } 1228 1229 /* emulu rs, rd */ 1230 /* emulu dsp[rs], rd */ 1231 static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) 1232 { 1233 TCGv val, mem; 1234 if (a->rd > 14) { 1235 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1236 } 1237 mem = tcg_temp_new(); 1238 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1239 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1240 cpu_regs[a->rd], val); 1241 return true; 1242 } 1243 1244 static void rx_div(TCGv ret, TCGv arg1, TCGv arg2) 1245 { 1246 gen_helper_div(ret, cpu_env, arg1, arg2); 1247 } 1248 1249 static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2) 1250 { 1251 gen_helper_divu(ret, cpu_env, arg1, arg2); 1252 } 1253 1254 /* div #imm, rd */ 1255 static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a) 1256 { 1257 rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm); 1258 return true; 1259 } 1260 1261 /* div rs, rd */ 1262 /* div dsp[rs], rd */ 1263 static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a) 1264 { 1265 rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi); 1266 return true; 1267 } 1268 1269 /* divu #imm, rd */ 1270 static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a) 1271 { 1272 rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm); 1273 return true; 1274 } 1275 1276 /* divu rs, rd */ 1277 /* divu dsp[rs], rd */ 1278 static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a) 1279 { 1280 rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi); 1281 return true; 1282 } 1283 1284 1285 /* shll #imm:5, rd */ 1286 /* shll #imm:5, rs2, rd */ 1287 static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) 1288 { 1289 TCGv tmp; 1290 tmp = tcg_temp_new(); 1291 if (a->imm) { 1292 tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm); 1293 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm); 1294 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1295 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1296 tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1297 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1298 } else { 1299 tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]); 1300 tcg_gen_movi_i32(cpu_psw_c, 0); 1301 tcg_gen_movi_i32(cpu_psw_o, 0); 1302 } 1303 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1304 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1305 return true; 1306 } 1307 1308 /* shll rs, rd */ 1309 static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) 1310 { 1311 TCGLabel *noshift, *done; 1312 TCGv count, tmp; 1313 1314 noshift = gen_new_label(); 1315 done = gen_new_label(); 1316 /* if (cpu_regs[a->rs]) { */ 1317 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); 1318 count = tcg_const_i32(32); 1319 tmp = tcg_temp_new(); 1320 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); 1321 tcg_gen_sub_i32(count, count, tmp); 1322 tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); 1323 tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1324 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1325 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1326 tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1327 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1328 tcg_gen_br(done); 1329 /* } else { */ 1330 gen_set_label(noshift); 1331 tcg_gen_movi_i32(cpu_psw_c, 0); 1332 tcg_gen_movi_i32(cpu_psw_o, 0); 1333 /* } */ 1334 gen_set_label(done); 1335 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1336 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1337 return true; 1338 } 1339 1340 static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm, 1341 unsigned int alith) 1342 { 1343 static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1344 tcg_gen_shri_i32, tcg_gen_sari_i32, 1345 }; 1346 tcg_debug_assert(alith < 2); 1347 if (imm) { 1348 gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1); 1349 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1350 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1351 } else { 1352 tcg_gen_mov_i32(cpu_regs[rd], cpu_regs[rs]); 1353 tcg_gen_movi_i32(cpu_psw_c, 0); 1354 } 1355 tcg_gen_movi_i32(cpu_psw_o, 0); 1356 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1357 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1358 } 1359 1360 static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith) 1361 { 1362 TCGLabel *noshift, *done; 1363 TCGv count; 1364 static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1365 tcg_gen_shri_i32, tcg_gen_sari_i32, 1366 }; 1367 static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) = { 1368 tcg_gen_shr_i32, tcg_gen_sar_i32, 1369 }; 1370 tcg_debug_assert(alith < 2); 1371 noshift = gen_new_label(); 1372 done = gen_new_label(); 1373 count = tcg_temp_new(); 1374 /* if (cpu_regs[rs]) { */ 1375 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[rs], 0, noshift); 1376 tcg_gen_andi_i32(count, cpu_regs[rs], 31); 1377 tcg_gen_subi_i32(count, count, 1); 1378 gen_sXr[alith](cpu_regs[rd], cpu_regs[rd], count); 1379 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1380 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1381 tcg_gen_br(done); 1382 /* } else { */ 1383 gen_set_label(noshift); 1384 tcg_gen_movi_i32(cpu_psw_c, 0); 1385 /* } */ 1386 gen_set_label(done); 1387 tcg_gen_movi_i32(cpu_psw_o, 0); 1388 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1389 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1390 } 1391 1392 /* shar #imm:5, rd */ 1393 /* shar #imm:5, rs2, rd */ 1394 static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a) 1395 { 1396 shiftr_imm(a->rd, a->rs2, a->imm, 1); 1397 return true; 1398 } 1399 1400 /* shar rs, rd */ 1401 static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a) 1402 { 1403 shiftr_reg(a->rd, a->rs, 1); 1404 return true; 1405 } 1406 1407 /* shlr #imm:5, rd */ 1408 /* shlr #imm:5, rs2, rd */ 1409 static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a) 1410 { 1411 shiftr_imm(a->rd, a->rs2, a->imm, 0); 1412 return true; 1413 } 1414 1415 /* shlr rs, rd */ 1416 static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a) 1417 { 1418 shiftr_reg(a->rd, a->rs, 0); 1419 return true; 1420 } 1421 1422 /* rolc rd */ 1423 static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) 1424 { 1425 TCGv tmp; 1426 tmp = tcg_temp_new(); 1427 tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31); 1428 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1429 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1430 tcg_gen_mov_i32(cpu_psw_c, tmp); 1431 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1432 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1433 return true; 1434 } 1435 1436 /* rorc rd */ 1437 static bool trans_RORC(DisasContext *ctx, arg_RORC *a) 1438 { 1439 TCGv tmp; 1440 tmp = tcg_temp_new(); 1441 tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); 1442 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1443 tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, 31); 1444 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1445 tcg_gen_mov_i32(cpu_psw_c, tmp); 1446 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1447 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1448 return true; 1449 } 1450 1451 enum {ROTR = 0, ROTL = 1}; 1452 enum {ROT_IMM = 0, ROT_REG = 1}; 1453 static inline void rx_rot(int ir, int dir, int rd, int src) 1454 { 1455 switch (dir) { 1456 case ROTL: 1457 if (ir == ROT_IMM) { 1458 tcg_gen_rotli_i32(cpu_regs[rd], cpu_regs[rd], src); 1459 } else { 1460 tcg_gen_rotl_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1461 } 1462 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1463 break; 1464 case ROTR: 1465 if (ir == ROT_IMM) { 1466 tcg_gen_rotri_i32(cpu_regs[rd], cpu_regs[rd], src); 1467 } else { 1468 tcg_gen_rotr_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1469 } 1470 tcg_gen_shri_i32(cpu_psw_c, cpu_regs[rd], 31); 1471 break; 1472 } 1473 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1474 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1475 } 1476 1477 /* rotl #imm, rd */ 1478 static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a) 1479 { 1480 rx_rot(ROT_IMM, ROTL, a->rd, a->imm); 1481 return true; 1482 } 1483 1484 /* rotl rs, rd */ 1485 static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a) 1486 { 1487 rx_rot(ROT_REG, ROTL, a->rd, a->rs); 1488 return true; 1489 } 1490 1491 /* rotr #imm, rd */ 1492 static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a) 1493 { 1494 rx_rot(ROT_IMM, ROTR, a->rd, a->imm); 1495 return true; 1496 } 1497 1498 /* rotr rs, rd */ 1499 static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a) 1500 { 1501 rx_rot(ROT_REG, ROTR, a->rd, a->rs); 1502 return true; 1503 } 1504 1505 /* revl rs, rd */ 1506 static bool trans_REVL(DisasContext *ctx, arg_REVL *a) 1507 { 1508 tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]); 1509 return true; 1510 } 1511 1512 /* revw rs, rd */ 1513 static bool trans_REVW(DisasContext *ctx, arg_REVW *a) 1514 { 1515 TCGv tmp; 1516 tmp = tcg_temp_new(); 1517 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); 1518 tcg_gen_shli_i32(tmp, tmp, 8); 1519 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); 1520 tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); 1521 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1522 return true; 1523 } 1524 1525 /* conditional branch helper */ 1526 static void rx_bcnd_main(DisasContext *ctx, int cd, int dst) 1527 { 1528 DisasCompare dc; 1529 TCGLabel *t, *done; 1530 1531 switch (cd) { 1532 case 0 ... 13: 1533 dc.temp = tcg_temp_new(); 1534 psw_cond(&dc, cd); 1535 t = gen_new_label(); 1536 done = gen_new_label(); 1537 tcg_gen_brcondi_i32(dc.cond, dc.value, 0, t); 1538 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1539 tcg_gen_br(done); 1540 gen_set_label(t); 1541 gen_goto_tb(ctx, 1, ctx->pc + dst); 1542 gen_set_label(done); 1543 break; 1544 case 14: 1545 /* always true case */ 1546 gen_goto_tb(ctx, 0, ctx->pc + dst); 1547 break; 1548 case 15: 1549 /* always false case */ 1550 /* Nothing do */ 1551 break; 1552 } 1553 } 1554 1555 /* beq dsp:3 / bne dsp:3 */ 1556 /* beq dsp:8 / bne dsp:8 */ 1557 /* bc dsp:8 / bnc dsp:8 */ 1558 /* bgtu dsp:8 / bleu dsp:8 */ 1559 /* bpz dsp:8 / bn dsp:8 */ 1560 /* bge dsp:8 / blt dsp:8 */ 1561 /* bgt dsp:8 / ble dsp:8 */ 1562 /* bo dsp:8 / bno dsp:8 */ 1563 /* beq dsp:16 / bne dsp:16 */ 1564 static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a) 1565 { 1566 rx_bcnd_main(ctx, a->cd, a->dsp); 1567 return true; 1568 } 1569 1570 /* bra dsp:3 */ 1571 /* bra dsp:8 */ 1572 /* bra dsp:16 */ 1573 /* bra dsp:24 */ 1574 static bool trans_BRA(DisasContext *ctx, arg_BRA *a) 1575 { 1576 rx_bcnd_main(ctx, 14, a->dsp); 1577 return true; 1578 } 1579 1580 /* bra rs */ 1581 static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a) 1582 { 1583 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1584 ctx->base.is_jmp = DISAS_JUMP; 1585 return true; 1586 } 1587 1588 static inline void rx_save_pc(DisasContext *ctx) 1589 { 1590 TCGv pc = tcg_const_i32(ctx->base.pc_next); 1591 push(pc); 1592 } 1593 1594 /* jmp rs */ 1595 static bool trans_JMP(DisasContext *ctx, arg_JMP *a) 1596 { 1597 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1598 ctx->base.is_jmp = DISAS_JUMP; 1599 return true; 1600 } 1601 1602 /* jsr rs */ 1603 static bool trans_JSR(DisasContext *ctx, arg_JSR *a) 1604 { 1605 rx_save_pc(ctx); 1606 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1607 ctx->base.is_jmp = DISAS_JUMP; 1608 return true; 1609 } 1610 1611 /* bsr dsp:16 */ 1612 /* bsr dsp:24 */ 1613 static bool trans_BSR(DisasContext *ctx, arg_BSR *a) 1614 { 1615 rx_save_pc(ctx); 1616 rx_bcnd_main(ctx, 14, a->dsp); 1617 return true; 1618 } 1619 1620 /* bsr rs */ 1621 static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a) 1622 { 1623 rx_save_pc(ctx); 1624 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1625 ctx->base.is_jmp = DISAS_JUMP; 1626 return true; 1627 } 1628 1629 /* rts */ 1630 static bool trans_RTS(DisasContext *ctx, arg_RTS *a) 1631 { 1632 pop(cpu_pc); 1633 ctx->base.is_jmp = DISAS_JUMP; 1634 return true; 1635 } 1636 1637 /* nop */ 1638 static bool trans_NOP(DisasContext *ctx, arg_NOP *a) 1639 { 1640 return true; 1641 } 1642 1643 /* scmpu */ 1644 static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) 1645 { 1646 gen_helper_scmpu(cpu_env); 1647 return true; 1648 } 1649 1650 /* smovu */ 1651 static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) 1652 { 1653 gen_helper_smovu(cpu_env); 1654 return true; 1655 } 1656 1657 /* smovf */ 1658 static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) 1659 { 1660 gen_helper_smovf(cpu_env); 1661 return true; 1662 } 1663 1664 /* smovb */ 1665 static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) 1666 { 1667 gen_helper_smovb(cpu_env); 1668 return true; 1669 } 1670 1671 #define STRING(op) \ 1672 do { \ 1673 TCGv size = tcg_const_i32(a->sz); \ 1674 gen_helper_##op(cpu_env, size); \ 1675 } while (0) 1676 1677 /* suntile.<bwl> */ 1678 static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a) 1679 { 1680 STRING(suntil); 1681 return true; 1682 } 1683 1684 /* swhile.<bwl> */ 1685 static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a) 1686 { 1687 STRING(swhile); 1688 return true; 1689 } 1690 /* sstr.<bwl> */ 1691 static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a) 1692 { 1693 STRING(sstr); 1694 return true; 1695 } 1696 1697 /* rmpa.<bwl> */ 1698 static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a) 1699 { 1700 STRING(rmpa); 1701 return true; 1702 } 1703 1704 static void rx_mul64hi(TCGv_i64 ret, int rs, int rs2) 1705 { 1706 TCGv_i64 tmp0, tmp1; 1707 tmp0 = tcg_temp_new_i64(); 1708 tmp1 = tcg_temp_new_i64(); 1709 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1710 tcg_gen_sari_i64(tmp0, tmp0, 16); 1711 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1712 tcg_gen_sari_i64(tmp1, tmp1, 16); 1713 tcg_gen_mul_i64(ret, tmp0, tmp1); 1714 tcg_gen_shli_i64(ret, ret, 16); 1715 } 1716 1717 static void rx_mul64lo(TCGv_i64 ret, int rs, int rs2) 1718 { 1719 TCGv_i64 tmp0, tmp1; 1720 tmp0 = tcg_temp_new_i64(); 1721 tmp1 = tcg_temp_new_i64(); 1722 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1723 tcg_gen_ext16s_i64(tmp0, tmp0); 1724 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1725 tcg_gen_ext16s_i64(tmp1, tmp1); 1726 tcg_gen_mul_i64(ret, tmp0, tmp1); 1727 tcg_gen_shli_i64(ret, ret, 16); 1728 } 1729 1730 /* mulhi rs,rs2 */ 1731 static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a) 1732 { 1733 rx_mul64hi(cpu_acc, a->rs, a->rs2); 1734 return true; 1735 } 1736 1737 /* mullo rs,rs2 */ 1738 static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a) 1739 { 1740 rx_mul64lo(cpu_acc, a->rs, a->rs2); 1741 return true; 1742 } 1743 1744 /* machi rs,rs2 */ 1745 static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a) 1746 { 1747 TCGv_i64 tmp; 1748 tmp = tcg_temp_new_i64(); 1749 rx_mul64hi(tmp, a->rs, a->rs2); 1750 tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1751 return true; 1752 } 1753 1754 /* maclo rs,rs2 */ 1755 static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a) 1756 { 1757 TCGv_i64 tmp; 1758 tmp = tcg_temp_new_i64(); 1759 rx_mul64lo(tmp, a->rs, a->rs2); 1760 tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1761 return true; 1762 } 1763 1764 /* mvfachi rd */ 1765 static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a) 1766 { 1767 tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc); 1768 return true; 1769 } 1770 1771 /* mvfacmi rd */ 1772 static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a) 1773 { 1774 TCGv_i64 rd64; 1775 rd64 = tcg_temp_new_i64(); 1776 tcg_gen_extract_i64(rd64, cpu_acc, 16, 32); 1777 tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64); 1778 return true; 1779 } 1780 1781 /* mvtachi rs */ 1782 static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a) 1783 { 1784 TCGv_i64 rs64; 1785 rs64 = tcg_temp_new_i64(); 1786 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1787 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 32, 32); 1788 return true; 1789 } 1790 1791 /* mvtaclo rs */ 1792 static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a) 1793 { 1794 TCGv_i64 rs64; 1795 rs64 = tcg_temp_new_i64(); 1796 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1797 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 0, 32); 1798 return true; 1799 } 1800 1801 /* racw #imm */ 1802 static bool trans_RACW(DisasContext *ctx, arg_RACW *a) 1803 { 1804 TCGv imm = tcg_const_i32(a->imm + 1); 1805 gen_helper_racw(cpu_env, imm); 1806 return true; 1807 } 1808 1809 /* sat rd */ 1810 static bool trans_SAT(DisasContext *ctx, arg_SAT *a) 1811 { 1812 TCGv tmp, z; 1813 tmp = tcg_temp_new(); 1814 z = tcg_const_i32(0); 1815 /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */ 1816 tcg_gen_sari_i32(tmp, cpu_psw_s, 31); 1817 /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */ 1818 tcg_gen_xori_i32(tmp, tmp, 0x80000000); 1819 tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], 1820 cpu_psw_o, z, tmp, cpu_regs[a->rd]); 1821 return true; 1822 } 1823 1824 /* satr */ 1825 static bool trans_SATR(DisasContext *ctx, arg_SATR *a) 1826 { 1827 gen_helper_satr(cpu_env); 1828 return true; 1829 } 1830 1831 #define cat3(a, b, c) a##b##c 1832 #define FOP(name, op) \ 1833 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 1834 cat3(arg_, name, _ir) * a) \ 1835 { \ 1836 TCGv imm = tcg_const_i32(li(ctx, 0)); \ 1837 gen_helper_##op(cpu_regs[a->rd], cpu_env, \ 1838 cpu_regs[a->rd], imm); \ 1839 return true; \ 1840 } \ 1841 static bool cat3(trans_, name, _mr)(DisasContext *ctx, \ 1842 cat3(arg_, name, _mr) * a) \ 1843 { \ 1844 TCGv val, mem; \ 1845 mem = tcg_temp_new(); \ 1846 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1847 gen_helper_##op(cpu_regs[a->rd], cpu_env, \ 1848 cpu_regs[a->rd], val); \ 1849 return true; \ 1850 } 1851 1852 #define FCONVOP(name, op) \ 1853 static bool trans_##name(DisasContext *ctx, arg_##name * a) \ 1854 { \ 1855 TCGv val, mem; \ 1856 mem = tcg_temp_new(); \ 1857 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1858 gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \ 1859 return true; \ 1860 } 1861 1862 FOP(FADD, fadd) 1863 FOP(FSUB, fsub) 1864 FOP(FMUL, fmul) 1865 FOP(FDIV, fdiv) 1866 1867 /* fcmp #imm, rd */ 1868 static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) 1869 { 1870 TCGv imm = tcg_const_i32(li(ctx, 0)); 1871 gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm); 1872 return true; 1873 } 1874 1875 /* fcmp dsp[rs], rd */ 1876 /* fcmp rs, rd */ 1877 static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) 1878 { 1879 TCGv val, mem; 1880 mem = tcg_temp_new(); 1881 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); 1882 gen_helper_fcmp(cpu_env, cpu_regs[a->rd], val); 1883 return true; 1884 } 1885 1886 FCONVOP(FTOI, ftoi) 1887 FCONVOP(ROUND, round) 1888 1889 /* itof rs, rd */ 1890 /* itof dsp[rs], rd */ 1891 static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a) 1892 { 1893 TCGv val, mem; 1894 mem = tcg_temp_new(); 1895 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1896 gen_helper_itof(cpu_regs[a->rd], cpu_env, val); 1897 return true; 1898 } 1899 1900 static void rx_bsetm(TCGv mem, TCGv mask) 1901 { 1902 TCGv val; 1903 val = tcg_temp_new(); 1904 rx_gen_ld(MO_8, val, mem); 1905 tcg_gen_or_i32(val, val, mask); 1906 rx_gen_st(MO_8, val, mem); 1907 } 1908 1909 static void rx_bclrm(TCGv mem, TCGv mask) 1910 { 1911 TCGv val; 1912 val = tcg_temp_new(); 1913 rx_gen_ld(MO_8, val, mem); 1914 tcg_gen_andc_i32(val, val, mask); 1915 rx_gen_st(MO_8, val, mem); 1916 } 1917 1918 static void rx_btstm(TCGv mem, TCGv mask) 1919 { 1920 TCGv val; 1921 val = tcg_temp_new(); 1922 rx_gen_ld(MO_8, val, mem); 1923 tcg_gen_and_i32(val, val, mask); 1924 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0); 1925 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 1926 } 1927 1928 static void rx_bnotm(TCGv mem, TCGv mask) 1929 { 1930 TCGv val; 1931 val = tcg_temp_new(); 1932 rx_gen_ld(MO_8, val, mem); 1933 tcg_gen_xor_i32(val, val, mask); 1934 rx_gen_st(MO_8, val, mem); 1935 } 1936 1937 static void rx_bsetr(TCGv reg, TCGv mask) 1938 { 1939 tcg_gen_or_i32(reg, reg, mask); 1940 } 1941 1942 static void rx_bclrr(TCGv reg, TCGv mask) 1943 { 1944 tcg_gen_andc_i32(reg, reg, mask); 1945 } 1946 1947 static inline void rx_btstr(TCGv reg, TCGv mask) 1948 { 1949 TCGv t0; 1950 t0 = tcg_temp_new(); 1951 tcg_gen_and_i32(t0, reg, mask); 1952 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0); 1953 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 1954 } 1955 1956 static inline void rx_bnotr(TCGv reg, TCGv mask) 1957 { 1958 tcg_gen_xor_i32(reg, reg, mask); 1959 } 1960 1961 #define BITOP(name, op) \ 1962 static bool cat3(trans_, name, _im)(DisasContext *ctx, \ 1963 cat3(arg_, name, _im) * a) \ 1964 { \ 1965 TCGv mask, mem, addr; \ 1966 mem = tcg_temp_new(); \ 1967 mask = tcg_const_i32(1 << a->imm); \ 1968 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 1969 cat3(rx_, op, m)(addr, mask); \ 1970 return true; \ 1971 } \ 1972 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 1973 cat3(arg_, name, _ir) * a) \ 1974 { \ 1975 TCGv mask; \ 1976 mask = tcg_const_i32(1 << a->imm); \ 1977 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 1978 return true; \ 1979 } \ 1980 static bool cat3(trans_, name, _rr)(DisasContext *ctx, \ 1981 cat3(arg_, name, _rr) * a) \ 1982 { \ 1983 TCGv mask, b; \ 1984 mask = tcg_const_i32(1); \ 1985 b = tcg_temp_new(); \ 1986 tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ 1987 tcg_gen_shl_i32(mask, mask, b); \ 1988 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 1989 return true; \ 1990 } \ 1991 static bool cat3(trans_, name, _rm)(DisasContext *ctx, \ 1992 cat3(arg_, name, _rm) * a) \ 1993 { \ 1994 TCGv mask, mem, addr, b; \ 1995 mask = tcg_const_i32(1); \ 1996 b = tcg_temp_new(); \ 1997 tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \ 1998 tcg_gen_shl_i32(mask, mask, b); \ 1999 mem = tcg_temp_new(); \ 2000 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 2001 cat3(rx_, op, m)(addr, mask); \ 2002 return true; \ 2003 } 2004 2005 BITOP(BSET, bset) 2006 BITOP(BCLR, bclr) 2007 BITOP(BTST, btst) 2008 BITOP(BNOT, bnot) 2009 2010 static inline void bmcnd_op(TCGv val, TCGCond cond, int pos) 2011 { 2012 TCGv bit; 2013 DisasCompare dc; 2014 dc.temp = tcg_temp_new(); 2015 bit = tcg_temp_new(); 2016 psw_cond(&dc, cond); 2017 tcg_gen_andi_i32(val, val, ~(1 << pos)); 2018 tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0); 2019 tcg_gen_deposit_i32(val, val, bit, pos, 1); 2020 } 2021 2022 /* bmcnd #imm, dsp[rd] */ 2023 static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) 2024 { 2025 TCGv val, mem, addr; 2026 val = tcg_temp_new(); 2027 mem = tcg_temp_new(); 2028 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); 2029 rx_gen_ld(MO_8, val, addr); 2030 bmcnd_op(val, a->cd, a->imm); 2031 rx_gen_st(MO_8, val, addr); 2032 return true; 2033 } 2034 2035 /* bmcond #imm, rd */ 2036 static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a) 2037 { 2038 bmcnd_op(cpu_regs[a->rd], a->cd, a->imm); 2039 return true; 2040 } 2041 2042 enum { 2043 PSW_C = 0, 2044 PSW_Z = 1, 2045 PSW_S = 2, 2046 PSW_O = 3, 2047 PSW_I = 8, 2048 PSW_U = 9, 2049 }; 2050 2051 static inline void clrsetpsw(DisasContext *ctx, int cb, int val) 2052 { 2053 if (cb < 8) { 2054 switch (cb) { 2055 case PSW_C: 2056 tcg_gen_movi_i32(cpu_psw_c, val); 2057 break; 2058 case PSW_Z: 2059 tcg_gen_movi_i32(cpu_psw_z, val == 0); 2060 break; 2061 case PSW_S: 2062 tcg_gen_movi_i32(cpu_psw_s, val ? -1 : 0); 2063 break; 2064 case PSW_O: 2065 tcg_gen_movi_i32(cpu_psw_o, val << 31); 2066 break; 2067 default: 2068 qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); 2069 break; 2070 } 2071 } else if (is_privileged(ctx, 0)) { 2072 switch (cb) { 2073 case PSW_I: 2074 tcg_gen_movi_i32(cpu_psw_i, val); 2075 ctx->base.is_jmp = DISAS_UPDATE; 2076 break; 2077 case PSW_U: 2078 if (FIELD_EX32(ctx->tb_flags, PSW, U) != val) { 2079 ctx->tb_flags = FIELD_DP32(ctx->tb_flags, PSW, U, val); 2080 tcg_gen_movi_i32(cpu_psw_u, val); 2081 tcg_gen_mov_i32(val ? cpu_isp : cpu_usp, cpu_sp); 2082 tcg_gen_mov_i32(cpu_sp, val ? cpu_usp : cpu_isp); 2083 } 2084 break; 2085 default: 2086 qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); 2087 break; 2088 } 2089 } 2090 } 2091 2092 /* clrpsw psw */ 2093 static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a) 2094 { 2095 clrsetpsw(ctx, a->cb, 0); 2096 return true; 2097 } 2098 2099 /* setpsw psw */ 2100 static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a) 2101 { 2102 clrsetpsw(ctx, a->cb, 1); 2103 return true; 2104 } 2105 2106 /* mvtipl #imm */ 2107 static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a) 2108 { 2109 if (is_privileged(ctx, 1)) { 2110 tcg_gen_movi_i32(cpu_psw_ipl, a->imm); 2111 ctx->base.is_jmp = DISAS_UPDATE; 2112 } 2113 return true; 2114 } 2115 2116 /* mvtc #imm, rd */ 2117 static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) 2118 { 2119 TCGv imm; 2120 2121 imm = tcg_const_i32(a->imm); 2122 move_to_cr(ctx, imm, a->cr); 2123 return true; 2124 } 2125 2126 /* mvtc rs, rd */ 2127 static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) 2128 { 2129 move_to_cr(ctx, cpu_regs[a->rs], a->cr); 2130 return true; 2131 } 2132 2133 /* mvfc rs, rd */ 2134 static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) 2135 { 2136 move_from_cr(ctx, cpu_regs[a->rd], a->cr, ctx->pc); 2137 return true; 2138 } 2139 2140 /* rtfi */ 2141 static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) 2142 { 2143 TCGv psw; 2144 if (is_privileged(ctx, 1)) { 2145 psw = tcg_temp_new(); 2146 tcg_gen_mov_i32(cpu_pc, cpu_bpc); 2147 tcg_gen_mov_i32(psw, cpu_bpsw); 2148 gen_helper_set_psw_rte(cpu_env, psw); 2149 ctx->base.is_jmp = DISAS_EXIT; 2150 } 2151 return true; 2152 } 2153 2154 /* rte */ 2155 static bool trans_RTE(DisasContext *ctx, arg_RTE *a) 2156 { 2157 TCGv psw; 2158 if (is_privileged(ctx, 1)) { 2159 psw = tcg_temp_new(); 2160 pop(cpu_pc); 2161 pop(psw); 2162 gen_helper_set_psw_rte(cpu_env, psw); 2163 ctx->base.is_jmp = DISAS_EXIT; 2164 } 2165 return true; 2166 } 2167 2168 /* brk */ 2169 static bool trans_BRK(DisasContext *ctx, arg_BRK *a) 2170 { 2171 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2172 gen_helper_rxbrk(cpu_env); 2173 ctx->base.is_jmp = DISAS_NORETURN; 2174 return true; 2175 } 2176 2177 /* int #imm */ 2178 static bool trans_INT(DisasContext *ctx, arg_INT *a) 2179 { 2180 TCGv vec; 2181 2182 tcg_debug_assert(a->imm < 0x100); 2183 vec = tcg_const_i32(a->imm); 2184 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2185 gen_helper_rxint(cpu_env, vec); 2186 ctx->base.is_jmp = DISAS_NORETURN; 2187 return true; 2188 } 2189 2190 /* wait */ 2191 static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) 2192 { 2193 if (is_privileged(ctx, 1)) { 2194 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2195 gen_helper_wait(cpu_env); 2196 } 2197 return true; 2198 } 2199 2200 static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 2201 { 2202 CPURXState *env = cs->env_ptr; 2203 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2204 ctx->env = env; 2205 ctx->tb_flags = ctx->base.tb->flags; 2206 } 2207 2208 static void rx_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) 2209 { 2210 } 2211 2212 static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 2213 { 2214 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2215 2216 tcg_gen_insn_start(ctx->base.pc_next); 2217 } 2218 2219 static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 2220 { 2221 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2222 uint32_t insn; 2223 2224 ctx->pc = ctx->base.pc_next; 2225 insn = decode_load(ctx); 2226 if (!decode(ctx, insn)) { 2227 gen_helper_raise_illegal_instruction(cpu_env); 2228 } 2229 } 2230 2231 static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 2232 { 2233 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2234 2235 switch (ctx->base.is_jmp) { 2236 case DISAS_NEXT: 2237 case DISAS_TOO_MANY: 2238 gen_goto_tb(ctx, 0, dcbase->pc_next); 2239 break; 2240 case DISAS_JUMP: 2241 tcg_gen_lookup_and_goto_ptr(); 2242 break; 2243 case DISAS_UPDATE: 2244 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2245 /* fall through */ 2246 case DISAS_EXIT: 2247 tcg_gen_exit_tb(NULL, 0); 2248 break; 2249 case DISAS_NORETURN: 2250 break; 2251 default: 2252 g_assert_not_reached(); 2253 } 2254 } 2255 2256 static void rx_tr_disas_log(const DisasContextBase *dcbase, 2257 CPUState *cs, FILE *logfile) 2258 { 2259 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 2260 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 2261 } 2262 2263 static const TranslatorOps rx_tr_ops = { 2264 .init_disas_context = rx_tr_init_disas_context, 2265 .tb_start = rx_tr_tb_start, 2266 .insn_start = rx_tr_insn_start, 2267 .translate_insn = rx_tr_translate_insn, 2268 .tb_stop = rx_tr_tb_stop, 2269 .disas_log = rx_tr_disas_log, 2270 }; 2271 2272 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 2273 target_ulong pc, void *host_pc) 2274 { 2275 DisasContext dc; 2276 2277 translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base); 2278 } 2279 2280 #define ALLOC_REGISTER(sym, name) \ 2281 cpu_##sym = tcg_global_mem_new_i32(cpu_env, \ 2282 offsetof(CPURXState, sym), name) 2283 2284 void rx_translate_init(void) 2285 { 2286 static const char * const regnames[NUM_REGS] = { 2287 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", 2288 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15" 2289 }; 2290 int i; 2291 2292 for (i = 0; i < NUM_REGS; i++) { 2293 cpu_regs[i] = tcg_global_mem_new_i32(cpu_env, 2294 offsetof(CPURXState, regs[i]), 2295 regnames[i]); 2296 } 2297 ALLOC_REGISTER(pc, "PC"); 2298 ALLOC_REGISTER(psw_o, "PSW(O)"); 2299 ALLOC_REGISTER(psw_s, "PSW(S)"); 2300 ALLOC_REGISTER(psw_z, "PSW(Z)"); 2301 ALLOC_REGISTER(psw_c, "PSW(C)"); 2302 ALLOC_REGISTER(psw_u, "PSW(U)"); 2303 ALLOC_REGISTER(psw_i, "PSW(I)"); 2304 ALLOC_REGISTER(psw_pm, "PSW(PM)"); 2305 ALLOC_REGISTER(psw_ipl, "PSW(IPL)"); 2306 ALLOC_REGISTER(usp, "USP"); 2307 ALLOC_REGISTER(fpsw, "FPSW"); 2308 ALLOC_REGISTER(bpsw, "BPSW"); 2309 ALLOC_REGISTER(bpc, "BPC"); 2310 ALLOC_REGISTER(isp, "ISP"); 2311 ALLOC_REGISTER(fintv, "FINTV"); 2312 ALLOC_REGISTER(intb, "INTB"); 2313 cpu_acc = tcg_global_mem_new_i64(cpu_env, 2314 offsetof(CPURXState, acc), "ACC"); 2315 } 2316