1e5918d7dSYoshinori Sato /* 2e5918d7dSYoshinori Sato * RX translation 3e5918d7dSYoshinori Sato * 4e5918d7dSYoshinori Sato * Copyright (c) 2019 Yoshinori Sato 5e5918d7dSYoshinori Sato * 6e5918d7dSYoshinori Sato * This program is free software; you can redistribute it and/or modify it 7e5918d7dSYoshinori Sato * under the terms and conditions of the GNU General Public License, 8e5918d7dSYoshinori Sato * version 2 or later, as published by the Free Software Foundation. 9e5918d7dSYoshinori Sato * 10e5918d7dSYoshinori Sato * This program is distributed in the hope it will be useful, but WITHOUT 11e5918d7dSYoshinori Sato * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12e5918d7dSYoshinori Sato * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13e5918d7dSYoshinori Sato * more details. 14e5918d7dSYoshinori Sato * 15e5918d7dSYoshinori Sato * You should have received a copy of the GNU General Public License along with 16e5918d7dSYoshinori Sato * this program. If not, see <http://www.gnu.org/licenses/>. 17e5918d7dSYoshinori Sato */ 18e5918d7dSYoshinori Sato 19e5918d7dSYoshinori Sato #include "qemu/osdep.h" 20e5918d7dSYoshinori Sato #include "qemu/bswap.h" 21e5918d7dSYoshinori Sato #include "qemu/qemu-print.h" 22e5918d7dSYoshinori Sato #include "cpu.h" 23e5918d7dSYoshinori Sato #include "exec/exec-all.h" 24e5918d7dSYoshinori Sato #include "tcg/tcg-op.h" 25e5918d7dSYoshinori Sato #include "exec/cpu_ldst.h" 26e5918d7dSYoshinori Sato #include "exec/helper-proto.h" 27e5918d7dSYoshinori Sato #include "exec/helper-gen.h" 28e5918d7dSYoshinori Sato #include "exec/translator.h" 29e5918d7dSYoshinori Sato #include "trace-tcg.h" 30e5918d7dSYoshinori Sato #include "exec/log.h" 31e5918d7dSYoshinori Sato 32e5918d7dSYoshinori Sato typedef struct DisasContext { 33e5918d7dSYoshinori Sato DisasContextBase base; 34e5918d7dSYoshinori Sato CPURXState *env; 35e5918d7dSYoshinori Sato uint32_t pc; 36e5918d7dSYoshinori Sato } DisasContext; 37e5918d7dSYoshinori Sato 38e5918d7dSYoshinori Sato typedef struct DisasCompare { 39e5918d7dSYoshinori Sato TCGv value; 40e5918d7dSYoshinori Sato TCGv temp; 41e5918d7dSYoshinori Sato TCGCond cond; 42e5918d7dSYoshinori Sato } DisasCompare; 43e5918d7dSYoshinori Sato 4427a4a30eSYoshinori Sato const char *rx_crname(uint8_t cr) 4527a4a30eSYoshinori Sato { 4627a4a30eSYoshinori Sato static const char *cr_names[] = { 47e5918d7dSYoshinori Sato "psw", "pc", "usp", "fpsw", "", "", "", "", 4827a4a30eSYoshinori Sato "bpsw", "bpc", "isp", "fintv", "intb", "", "", "" 49e5918d7dSYoshinori Sato }; 5027a4a30eSYoshinori Sato if (cr >= ARRAY_SIZE(cr_names)) { 5127a4a30eSYoshinori Sato return "illegal"; 5227a4a30eSYoshinori Sato } 5327a4a30eSYoshinori Sato return cr_names[cr]; 5427a4a30eSYoshinori Sato } 55e5918d7dSYoshinori Sato 56e5918d7dSYoshinori Sato /* Target-specific values for dc->base.is_jmp. */ 57e5918d7dSYoshinori Sato #define DISAS_JUMP DISAS_TARGET_0 58e5918d7dSYoshinori Sato #define DISAS_UPDATE DISAS_TARGET_1 59e5918d7dSYoshinori Sato #define DISAS_EXIT DISAS_TARGET_2 60e5918d7dSYoshinori Sato 61e5918d7dSYoshinori Sato /* global register indexes */ 62e5918d7dSYoshinori Sato static TCGv cpu_regs[16]; 63e5918d7dSYoshinori Sato static TCGv cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c; 64e5918d7dSYoshinori Sato static TCGv cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl; 65e5918d7dSYoshinori Sato static TCGv cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp; 66e5918d7dSYoshinori Sato static TCGv cpu_fintv, cpu_intb, cpu_pc; 67e5918d7dSYoshinori Sato static TCGv_i64 cpu_acc; 68e5918d7dSYoshinori Sato 69e5918d7dSYoshinori Sato #define cpu_sp cpu_regs[0] 70e5918d7dSYoshinori Sato 71e5918d7dSYoshinori Sato #include "exec/gen-icount.h" 72e5918d7dSYoshinori Sato 73e5918d7dSYoshinori Sato /* decoder helper */ 74e5918d7dSYoshinori Sato static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, 75e5918d7dSYoshinori Sato int i, int n) 76e5918d7dSYoshinori Sato { 77e5918d7dSYoshinori Sato while (++i <= n) { 78e5918d7dSYoshinori Sato uint8_t b = cpu_ldub_code(ctx->env, ctx->base.pc_next++); 79e5918d7dSYoshinori Sato insn |= b << (32 - i * 8); 80e5918d7dSYoshinori Sato } 81e5918d7dSYoshinori Sato return insn; 82e5918d7dSYoshinori Sato } 83e5918d7dSYoshinori Sato 84e5918d7dSYoshinori Sato static uint32_t li(DisasContext *ctx, int sz) 85e5918d7dSYoshinori Sato { 86e5918d7dSYoshinori Sato int32_t tmp, addr; 87e5918d7dSYoshinori Sato CPURXState *env = ctx->env; 88e5918d7dSYoshinori Sato addr = ctx->base.pc_next; 89e5918d7dSYoshinori Sato 90e5918d7dSYoshinori Sato tcg_debug_assert(sz < 4); 91e5918d7dSYoshinori Sato switch (sz) { 92e5918d7dSYoshinori Sato case 1: 93e5918d7dSYoshinori Sato ctx->base.pc_next += 1; 94e5918d7dSYoshinori Sato return cpu_ldsb_code(env, addr); 95e5918d7dSYoshinori Sato case 2: 96e5918d7dSYoshinori Sato ctx->base.pc_next += 2; 97e5918d7dSYoshinori Sato return cpu_ldsw_code(env, addr); 98e5918d7dSYoshinori Sato case 3: 99e5918d7dSYoshinori Sato ctx->base.pc_next += 3; 100e5918d7dSYoshinori Sato tmp = cpu_ldsb_code(env, addr + 2) << 16; 101e5918d7dSYoshinori Sato tmp |= cpu_lduw_code(env, addr) & 0xffff; 102e5918d7dSYoshinori Sato return tmp; 103e5918d7dSYoshinori Sato case 0: 104e5918d7dSYoshinori Sato ctx->base.pc_next += 4; 105e5918d7dSYoshinori Sato return cpu_ldl_code(env, addr); 106e5918d7dSYoshinori Sato } 107e5918d7dSYoshinori Sato return 0; 108e5918d7dSYoshinori Sato } 109e5918d7dSYoshinori Sato 110e5918d7dSYoshinori Sato static int bdsp_s(DisasContext *ctx, int d) 111e5918d7dSYoshinori Sato { 112e5918d7dSYoshinori Sato /* 113e5918d7dSYoshinori Sato * 0 -> 8 114e5918d7dSYoshinori Sato * 1 -> 9 115e5918d7dSYoshinori Sato * 2 -> 10 116e5918d7dSYoshinori Sato * 3 -> 3 117e5918d7dSYoshinori Sato * : 118e5918d7dSYoshinori Sato * 7 -> 7 119e5918d7dSYoshinori Sato */ 120e5918d7dSYoshinori Sato if (d < 3) { 121e5918d7dSYoshinori Sato d += 8; 122e5918d7dSYoshinori Sato } 123e5918d7dSYoshinori Sato return d; 124e5918d7dSYoshinori Sato } 125e5918d7dSYoshinori Sato 126e5918d7dSYoshinori Sato /* Include the auto-generated decoder. */ 127abff1abfSPaolo Bonzini #include "decode-insns.c.inc" 128e5918d7dSYoshinori Sato 129e5918d7dSYoshinori Sato void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) 130e5918d7dSYoshinori Sato { 13138688fdbSEduardo Habkost RXCPU *cpu = RX_CPU(cs); 132e5918d7dSYoshinori Sato CPURXState *env = &cpu->env; 133e5918d7dSYoshinori Sato int i; 134e5918d7dSYoshinori Sato uint32_t psw; 135e5918d7dSYoshinori Sato 136e5918d7dSYoshinori Sato psw = rx_cpu_pack_psw(env); 137e5918d7dSYoshinori Sato qemu_fprintf(f, "pc=0x%08x psw=0x%08x\n", 138e5918d7dSYoshinori Sato env->pc, psw); 139e5918d7dSYoshinori Sato for (i = 0; i < 16; i += 4) { 140e5918d7dSYoshinori Sato qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", 141e5918d7dSYoshinori Sato i, env->regs[i], i + 1, env->regs[i + 1], 142e5918d7dSYoshinori Sato i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]); 143e5918d7dSYoshinori Sato } 144e5918d7dSYoshinori Sato } 145e5918d7dSYoshinori Sato 146e5918d7dSYoshinori Sato static bool use_goto_tb(DisasContext *dc, target_ulong dest) 147e5918d7dSYoshinori Sato { 148e5918d7dSYoshinori Sato if (unlikely(dc->base.singlestep_enabled)) { 149e5918d7dSYoshinori Sato return false; 150e5918d7dSYoshinori Sato } else { 151e5918d7dSYoshinori Sato return true; 152e5918d7dSYoshinori Sato } 153e5918d7dSYoshinori Sato } 154e5918d7dSYoshinori Sato 155e5918d7dSYoshinori Sato static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) 156e5918d7dSYoshinori Sato { 157e5918d7dSYoshinori Sato if (use_goto_tb(dc, dest)) { 158e5918d7dSYoshinori Sato tcg_gen_goto_tb(n); 159e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, dest); 160e5918d7dSYoshinori Sato tcg_gen_exit_tb(dc->base.tb, n); 161e5918d7dSYoshinori Sato } else { 162e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, dest); 163e5918d7dSYoshinori Sato if (dc->base.singlestep_enabled) { 164e5918d7dSYoshinori Sato gen_helper_debug(cpu_env); 165e5918d7dSYoshinori Sato } else { 166e5918d7dSYoshinori Sato tcg_gen_lookup_and_goto_ptr(); 167e5918d7dSYoshinori Sato } 168e5918d7dSYoshinori Sato } 169e5918d7dSYoshinori Sato dc->base.is_jmp = DISAS_NORETURN; 170e5918d7dSYoshinori Sato } 171e5918d7dSYoshinori Sato 172e5918d7dSYoshinori Sato /* generic load wrapper */ 173e5918d7dSYoshinori Sato static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem) 174e5918d7dSYoshinori Sato { 175e5918d7dSYoshinori Sato tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); 176e5918d7dSYoshinori Sato } 177e5918d7dSYoshinori Sato 178e5918d7dSYoshinori Sato /* unsigned load wrapper */ 179e5918d7dSYoshinori Sato static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem) 180e5918d7dSYoshinori Sato { 181e5918d7dSYoshinori Sato tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); 182e5918d7dSYoshinori Sato } 183e5918d7dSYoshinori Sato 184e5918d7dSYoshinori Sato /* generic store wrapper */ 185e5918d7dSYoshinori Sato static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem) 186e5918d7dSYoshinori Sato { 187e5918d7dSYoshinori Sato tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); 188e5918d7dSYoshinori Sato } 189e5918d7dSYoshinori Sato 190e5918d7dSYoshinori Sato /* [ri, rb] */ 191e5918d7dSYoshinori Sato static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem, 192e5918d7dSYoshinori Sato int size, int ri, int rb) 193e5918d7dSYoshinori Sato { 194e5918d7dSYoshinori Sato tcg_gen_shli_i32(mem, cpu_regs[ri], size); 195e5918d7dSYoshinori Sato tcg_gen_add_i32(mem, mem, cpu_regs[rb]); 196e5918d7dSYoshinori Sato } 197e5918d7dSYoshinori Sato 198e5918d7dSYoshinori Sato /* dsp[reg] */ 199e5918d7dSYoshinori Sato static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem, 200e5918d7dSYoshinori Sato int ld, int size, int reg) 201e5918d7dSYoshinori Sato { 202e5918d7dSYoshinori Sato uint32_t dsp; 203e5918d7dSYoshinori Sato 204e5918d7dSYoshinori Sato tcg_debug_assert(ld < 3); 205e5918d7dSYoshinori Sato switch (ld) { 206e5918d7dSYoshinori Sato case 0: 207e5918d7dSYoshinori Sato return cpu_regs[reg]; 208e5918d7dSYoshinori Sato case 1: 209e5918d7dSYoshinori Sato dsp = cpu_ldub_code(ctx->env, ctx->base.pc_next) << size; 210e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 211e5918d7dSYoshinori Sato ctx->base.pc_next += 1; 212e5918d7dSYoshinori Sato return mem; 213e5918d7dSYoshinori Sato case 2: 214e5918d7dSYoshinori Sato dsp = cpu_lduw_code(ctx->env, ctx->base.pc_next) << size; 215e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 216e5918d7dSYoshinori Sato ctx->base.pc_next += 2; 217e5918d7dSYoshinori Sato return mem; 218e5918d7dSYoshinori Sato } 219e5918d7dSYoshinori Sato return NULL; 220e5918d7dSYoshinori Sato } 221e5918d7dSYoshinori Sato 222e5918d7dSYoshinori Sato static inline MemOp mi_to_mop(unsigned mi) 223e5918d7dSYoshinori Sato { 224e5918d7dSYoshinori Sato static const MemOp mop[5] = { MO_SB, MO_SW, MO_UL, MO_UW, MO_UB }; 225e5918d7dSYoshinori Sato tcg_debug_assert(mi < 5); 226e5918d7dSYoshinori Sato return mop[mi]; 227e5918d7dSYoshinori Sato } 228e5918d7dSYoshinori Sato 229e5918d7dSYoshinori Sato /* load source operand */ 230e5918d7dSYoshinori Sato static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem, 231e5918d7dSYoshinori Sato int ld, int mi, int rs) 232e5918d7dSYoshinori Sato { 233e5918d7dSYoshinori Sato TCGv addr; 234e5918d7dSYoshinori Sato MemOp mop; 235e5918d7dSYoshinori Sato if (ld < 3) { 236e5918d7dSYoshinori Sato mop = mi_to_mop(mi); 237e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs); 238e5918d7dSYoshinori Sato tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE); 239e5918d7dSYoshinori Sato return mem; 240e5918d7dSYoshinori Sato } else { 241e5918d7dSYoshinori Sato return cpu_regs[rs]; 242e5918d7dSYoshinori Sato } 243e5918d7dSYoshinori Sato } 244e5918d7dSYoshinori Sato 245e5918d7dSYoshinori Sato /* Processor mode check */ 246e5918d7dSYoshinori Sato static int is_privileged(DisasContext *ctx, int is_exception) 247e5918d7dSYoshinori Sato { 248e5918d7dSYoshinori Sato if (FIELD_EX32(ctx->base.tb->flags, PSW, PM)) { 249e5918d7dSYoshinori Sato if (is_exception) { 250e5918d7dSYoshinori Sato gen_helper_raise_privilege_violation(cpu_env); 251e5918d7dSYoshinori Sato } 252e5918d7dSYoshinori Sato return 0; 253e5918d7dSYoshinori Sato } else { 254e5918d7dSYoshinori Sato return 1; 255e5918d7dSYoshinori Sato } 256e5918d7dSYoshinori Sato } 257e5918d7dSYoshinori Sato 258e5918d7dSYoshinori Sato /* generate QEMU condition */ 259e5918d7dSYoshinori Sato static void psw_cond(DisasCompare *dc, uint32_t cond) 260e5918d7dSYoshinori Sato { 261e5918d7dSYoshinori Sato tcg_debug_assert(cond < 16); 262e5918d7dSYoshinori Sato switch (cond) { 263e5918d7dSYoshinori Sato case 0: /* z */ 264e5918d7dSYoshinori Sato dc->cond = TCG_COND_EQ; 265e5918d7dSYoshinori Sato dc->value = cpu_psw_z; 266e5918d7dSYoshinori Sato break; 267e5918d7dSYoshinori Sato case 1: /* nz */ 268e5918d7dSYoshinori Sato dc->cond = TCG_COND_NE; 269e5918d7dSYoshinori Sato dc->value = cpu_psw_z; 270e5918d7dSYoshinori Sato break; 271e5918d7dSYoshinori Sato case 2: /* c */ 272e5918d7dSYoshinori Sato dc->cond = TCG_COND_NE; 273e5918d7dSYoshinori Sato dc->value = cpu_psw_c; 274e5918d7dSYoshinori Sato break; 275e5918d7dSYoshinori Sato case 3: /* nc */ 276e5918d7dSYoshinori Sato dc->cond = TCG_COND_EQ; 277e5918d7dSYoshinori Sato dc->value = cpu_psw_c; 278e5918d7dSYoshinori Sato break; 279e5918d7dSYoshinori Sato case 4: /* gtu (C& ~Z) == 1 */ 280e5918d7dSYoshinori Sato case 5: /* leu (C& ~Z) == 0 */ 281e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0); 282e5918d7dSYoshinori Sato tcg_gen_and_i32(dc->temp, dc->temp, cpu_psw_c); 283e5918d7dSYoshinori Sato dc->cond = (cond == 4) ? TCG_COND_NE : TCG_COND_EQ; 284e5918d7dSYoshinori Sato dc->value = dc->temp; 285e5918d7dSYoshinori Sato break; 286e5918d7dSYoshinori Sato case 6: /* pz (S == 0) */ 287e5918d7dSYoshinori Sato dc->cond = TCG_COND_GE; 288e5918d7dSYoshinori Sato dc->value = cpu_psw_s; 289e5918d7dSYoshinori Sato break; 290e5918d7dSYoshinori Sato case 7: /* n (S == 1) */ 291e5918d7dSYoshinori Sato dc->cond = TCG_COND_LT; 292e5918d7dSYoshinori Sato dc->value = cpu_psw_s; 293e5918d7dSYoshinori Sato break; 294e5918d7dSYoshinori Sato case 8: /* ge (S^O)==0 */ 295e5918d7dSYoshinori Sato case 9: /* lt (S^O)==1 */ 296e5918d7dSYoshinori Sato tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 297e5918d7dSYoshinori Sato dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT; 298e5918d7dSYoshinori Sato dc->value = dc->temp; 299e5918d7dSYoshinori Sato break; 300e5918d7dSYoshinori Sato case 10: /* gt ((S^O)|Z)==0 */ 301e5918d7dSYoshinori Sato case 11: /* le ((S^O)|Z)==1 */ 302e5918d7dSYoshinori Sato tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 303e5918d7dSYoshinori Sato tcg_gen_sari_i32(dc->temp, dc->temp, 31); 304e5918d7dSYoshinori Sato tcg_gen_andc_i32(dc->temp, cpu_psw_z, dc->temp); 305e5918d7dSYoshinori Sato dc->cond = (cond == 10) ? TCG_COND_NE : TCG_COND_EQ; 306e5918d7dSYoshinori Sato dc->value = dc->temp; 307e5918d7dSYoshinori Sato break; 308e5918d7dSYoshinori Sato case 12: /* o */ 309e5918d7dSYoshinori Sato dc->cond = TCG_COND_LT; 310e5918d7dSYoshinori Sato dc->value = cpu_psw_o; 311e5918d7dSYoshinori Sato break; 312e5918d7dSYoshinori Sato case 13: /* no */ 313e5918d7dSYoshinori Sato dc->cond = TCG_COND_GE; 314e5918d7dSYoshinori Sato dc->value = cpu_psw_o; 315e5918d7dSYoshinori Sato break; 316e5918d7dSYoshinori Sato case 14: /* always true */ 317e5918d7dSYoshinori Sato dc->cond = TCG_COND_ALWAYS; 318e5918d7dSYoshinori Sato dc->value = dc->temp; 319e5918d7dSYoshinori Sato break; 320e5918d7dSYoshinori Sato case 15: /* always false */ 321e5918d7dSYoshinori Sato dc->cond = TCG_COND_NEVER; 322e5918d7dSYoshinori Sato dc->value = dc->temp; 323e5918d7dSYoshinori Sato break; 324e5918d7dSYoshinori Sato } 325e5918d7dSYoshinori Sato } 326e5918d7dSYoshinori Sato 327e5918d7dSYoshinori Sato static void move_from_cr(TCGv ret, int cr, uint32_t pc) 328e5918d7dSYoshinori Sato { 329e5918d7dSYoshinori Sato TCGv z = tcg_const_i32(0); 330e5918d7dSYoshinori Sato switch (cr) { 331e5918d7dSYoshinori Sato case 0: /* PSW */ 332e5918d7dSYoshinori Sato gen_helper_pack_psw(ret, cpu_env); 333e5918d7dSYoshinori Sato break; 334e5918d7dSYoshinori Sato case 1: /* PC */ 335e5918d7dSYoshinori Sato tcg_gen_movi_i32(ret, pc); 336e5918d7dSYoshinori Sato break; 337e5918d7dSYoshinori Sato case 2: /* USP */ 338e5918d7dSYoshinori Sato tcg_gen_movcond_i32(TCG_COND_NE, ret, 339e5918d7dSYoshinori Sato cpu_psw_u, z, cpu_sp, cpu_usp); 340e5918d7dSYoshinori Sato break; 341e5918d7dSYoshinori Sato case 3: /* FPSW */ 342e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_fpsw); 343e5918d7dSYoshinori Sato break; 344e5918d7dSYoshinori Sato case 8: /* BPSW */ 345e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_bpsw); 346e5918d7dSYoshinori Sato break; 347e5918d7dSYoshinori Sato case 9: /* BPC */ 348e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_bpc); 349e5918d7dSYoshinori Sato break; 350e5918d7dSYoshinori Sato case 10: /* ISP */ 351e5918d7dSYoshinori Sato tcg_gen_movcond_i32(TCG_COND_EQ, ret, 352e5918d7dSYoshinori Sato cpu_psw_u, z, cpu_sp, cpu_isp); 353e5918d7dSYoshinori Sato break; 354e5918d7dSYoshinori Sato case 11: /* FINTV */ 355e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_fintv); 356e5918d7dSYoshinori Sato break; 357e5918d7dSYoshinori Sato case 12: /* INTB */ 358e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_intb); 359e5918d7dSYoshinori Sato break; 360e5918d7dSYoshinori Sato default: 361e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "Unimplement control register %d", cr); 362e5918d7dSYoshinori Sato /* Unimplement registers return 0 */ 363e5918d7dSYoshinori Sato tcg_gen_movi_i32(ret, 0); 364e5918d7dSYoshinori Sato break; 365e5918d7dSYoshinori Sato } 366e5918d7dSYoshinori Sato tcg_temp_free(z); 367e5918d7dSYoshinori Sato } 368e5918d7dSYoshinori Sato 369e5918d7dSYoshinori Sato static void move_to_cr(DisasContext *ctx, TCGv val, int cr) 370e5918d7dSYoshinori Sato { 371e5918d7dSYoshinori Sato TCGv z; 372e5918d7dSYoshinori Sato if (cr >= 8 && !is_privileged(ctx, 0)) { 373e5918d7dSYoshinori Sato /* Some control registers can only be written in privileged mode. */ 374e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 37527a4a30eSYoshinori Sato "disallow control register write %s", rx_crname(cr)); 376e5918d7dSYoshinori Sato return; 377e5918d7dSYoshinori Sato } 378e5918d7dSYoshinori Sato z = tcg_const_i32(0); 379e5918d7dSYoshinori Sato switch (cr) { 380e5918d7dSYoshinori Sato case 0: /* PSW */ 381e5918d7dSYoshinori Sato gen_helper_set_psw(cpu_env, val); 382e5918d7dSYoshinori Sato break; 383e5918d7dSYoshinori Sato /* case 1: to PC not supported */ 384e5918d7dSYoshinori Sato case 2: /* USP */ 385e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_usp, val); 386e5918d7dSYoshinori Sato tcg_gen_movcond_i32(TCG_COND_NE, cpu_sp, 387e5918d7dSYoshinori Sato cpu_psw_u, z, cpu_usp, cpu_sp); 388e5918d7dSYoshinori Sato break; 389e5918d7dSYoshinori Sato case 3: /* FPSW */ 390e5918d7dSYoshinori Sato gen_helper_set_fpsw(cpu_env, val); 391e5918d7dSYoshinori Sato break; 392e5918d7dSYoshinori Sato case 8: /* BPSW */ 393e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_bpsw, val); 394e5918d7dSYoshinori Sato break; 395e5918d7dSYoshinori Sato case 9: /* BPC */ 396e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_bpc, val); 397e5918d7dSYoshinori Sato break; 398e5918d7dSYoshinori Sato case 10: /* ISP */ 399e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_isp, val); 400e5918d7dSYoshinori Sato /* if PSW.U is 0, copy isp to r0 */ 401e5918d7dSYoshinori Sato tcg_gen_movcond_i32(TCG_COND_EQ, cpu_sp, 402e5918d7dSYoshinori Sato cpu_psw_u, z, cpu_isp, cpu_sp); 403e5918d7dSYoshinori Sato break; 404e5918d7dSYoshinori Sato case 11: /* FINTV */ 405e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_fintv, val); 406e5918d7dSYoshinori Sato break; 407e5918d7dSYoshinori Sato case 12: /* INTB */ 408e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_intb, val); 409e5918d7dSYoshinori Sato break; 410e5918d7dSYoshinori Sato default: 411e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 412e5918d7dSYoshinori Sato "Unimplement control register %d", cr); 413e5918d7dSYoshinori Sato break; 414e5918d7dSYoshinori Sato } 415e5918d7dSYoshinori Sato tcg_temp_free(z); 416e5918d7dSYoshinori Sato } 417e5918d7dSYoshinori Sato 418e5918d7dSYoshinori Sato static void push(TCGv val) 419e5918d7dSYoshinori Sato { 420e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 421e5918d7dSYoshinori Sato rx_gen_st(MO_32, val, cpu_sp); 422e5918d7dSYoshinori Sato } 423e5918d7dSYoshinori Sato 424e5918d7dSYoshinori Sato static void pop(TCGv ret) 425e5918d7dSYoshinori Sato { 426e5918d7dSYoshinori Sato rx_gen_ld(MO_32, ret, cpu_sp); 427e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_sp, cpu_sp, 4); 428e5918d7dSYoshinori Sato } 429e5918d7dSYoshinori Sato 430e5918d7dSYoshinori Sato /* mov.<bwl> rs,dsp5[rd] */ 431e5918d7dSYoshinori Sato static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) 432e5918d7dSYoshinori Sato { 433e5918d7dSYoshinori Sato TCGv mem; 434e5918d7dSYoshinori Sato mem = tcg_temp_new(); 435e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 436e5918d7dSYoshinori Sato rx_gen_st(a->sz, cpu_regs[a->rs], mem); 437e5918d7dSYoshinori Sato tcg_temp_free(mem); 438e5918d7dSYoshinori Sato return true; 439e5918d7dSYoshinori Sato } 440e5918d7dSYoshinori Sato 441e5918d7dSYoshinori Sato /* mov.<bwl> dsp5[rs],rd */ 442e5918d7dSYoshinori Sato static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) 443e5918d7dSYoshinori Sato { 444e5918d7dSYoshinori Sato TCGv mem; 445e5918d7dSYoshinori Sato mem = tcg_temp_new(); 446e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 447e5918d7dSYoshinori Sato rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 448e5918d7dSYoshinori Sato tcg_temp_free(mem); 449e5918d7dSYoshinori Sato return true; 450e5918d7dSYoshinori Sato } 451e5918d7dSYoshinori Sato 452e5918d7dSYoshinori Sato /* mov.l #uimm4,rd */ 453e5918d7dSYoshinori Sato /* mov.l #uimm8,rd */ 454e5918d7dSYoshinori Sato /* mov.l #imm,rd */ 455e5918d7dSYoshinori Sato static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) 456e5918d7dSYoshinori Sato { 457e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); 458e5918d7dSYoshinori Sato return true; 459e5918d7dSYoshinori Sato } 460e5918d7dSYoshinori Sato 461e5918d7dSYoshinori Sato /* mov.<bwl> #uimm8,dsp[rd] */ 462e5918d7dSYoshinori Sato /* mov.<bwl> #imm, dsp[rd] */ 463e5918d7dSYoshinori Sato static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) 464e5918d7dSYoshinori Sato { 465e5918d7dSYoshinori Sato TCGv imm, mem; 466e5918d7dSYoshinori Sato imm = tcg_const_i32(a->imm); 467e5918d7dSYoshinori Sato mem = tcg_temp_new(); 468e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 469e5918d7dSYoshinori Sato rx_gen_st(a->sz, imm, mem); 470e5918d7dSYoshinori Sato tcg_temp_free(imm); 471e5918d7dSYoshinori Sato tcg_temp_free(mem); 472e5918d7dSYoshinori Sato return true; 473e5918d7dSYoshinori Sato } 474e5918d7dSYoshinori Sato 475e5918d7dSYoshinori Sato /* mov.<bwl> [ri,rb],rd */ 476e5918d7dSYoshinori Sato static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a) 477e5918d7dSYoshinori Sato { 478e5918d7dSYoshinori Sato TCGv mem; 479e5918d7dSYoshinori Sato mem = tcg_temp_new(); 480e5918d7dSYoshinori Sato rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 481e5918d7dSYoshinori Sato rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 482e5918d7dSYoshinori Sato tcg_temp_free(mem); 483e5918d7dSYoshinori Sato return true; 484e5918d7dSYoshinori Sato } 485e5918d7dSYoshinori Sato 486e5918d7dSYoshinori Sato /* mov.<bwl> rd,[ri,rb] */ 487e5918d7dSYoshinori Sato static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) 488e5918d7dSYoshinori Sato { 489e5918d7dSYoshinori Sato TCGv mem; 490e5918d7dSYoshinori Sato mem = tcg_temp_new(); 491e5918d7dSYoshinori Sato rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 492e5918d7dSYoshinori Sato rx_gen_st(a->sz, cpu_regs[a->rs], mem); 493e5918d7dSYoshinori Sato tcg_temp_free(mem); 494e5918d7dSYoshinori Sato return true; 495e5918d7dSYoshinori Sato } 496e5918d7dSYoshinori Sato 497e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],dsp[rd] */ 498e5918d7dSYoshinori Sato /* mov.<bwl> rs,dsp[rd] */ 499e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],rd */ 500e5918d7dSYoshinori Sato /* mov.<bwl> rs,rd */ 501e5918d7dSYoshinori Sato static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) 502e5918d7dSYoshinori Sato { 503e5918d7dSYoshinori Sato static void (* const mov[])(TCGv ret, TCGv arg) = { 504e5918d7dSYoshinori Sato tcg_gen_ext8s_i32, tcg_gen_ext16s_i32, tcg_gen_mov_i32, 505e5918d7dSYoshinori Sato }; 506e5918d7dSYoshinori Sato TCGv tmp, mem, addr; 507e5918d7dSYoshinori Sato if (a->lds == 3 && a->ldd == 3) { 508e5918d7dSYoshinori Sato /* mov.<bwl> rs,rd */ 509e5918d7dSYoshinori Sato mov[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]); 510e5918d7dSYoshinori Sato return true; 511e5918d7dSYoshinori Sato } 512e5918d7dSYoshinori Sato 513e5918d7dSYoshinori Sato mem = tcg_temp_new(); 514e5918d7dSYoshinori Sato if (a->lds == 3) { 515e5918d7dSYoshinori Sato /* mov.<bwl> rs,dsp[rd] */ 516e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs); 517e5918d7dSYoshinori Sato rx_gen_st(a->sz, cpu_regs[a->rd], addr); 518e5918d7dSYoshinori Sato } else if (a->ldd == 3) { 519e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],rd */ 520e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 521e5918d7dSYoshinori Sato rx_gen_ld(a->sz, cpu_regs[a->rd], addr); 522e5918d7dSYoshinori Sato } else { 523e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],dsp[rd] */ 524e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 525e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 526e5918d7dSYoshinori Sato rx_gen_ld(a->sz, tmp, addr); 527e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); 528e5918d7dSYoshinori Sato rx_gen_st(a->sz, tmp, addr); 529e5918d7dSYoshinori Sato tcg_temp_free(tmp); 530e5918d7dSYoshinori Sato } 531e5918d7dSYoshinori Sato tcg_temp_free(mem); 532e5918d7dSYoshinori Sato return true; 533e5918d7dSYoshinori Sato } 534e5918d7dSYoshinori Sato 535e5918d7dSYoshinori Sato /* mov.<bwl> rs,[rd+] */ 536e5918d7dSYoshinori Sato /* mov.<bwl> rs,[-rd] */ 537e5918d7dSYoshinori Sato static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) 538e5918d7dSYoshinori Sato { 539e5918d7dSYoshinori Sato TCGv val; 540e5918d7dSYoshinori Sato val = tcg_temp_new(); 541e5918d7dSYoshinori Sato tcg_gen_mov_i32(val, cpu_regs[a->rs]); 542e5918d7dSYoshinori Sato if (a->ad == 1) { 543e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 544e5918d7dSYoshinori Sato } 545e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, cpu_regs[a->rd]); 546e5918d7dSYoshinori Sato if (a->ad == 0) { 547e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 548e5918d7dSYoshinori Sato } 549e5918d7dSYoshinori Sato tcg_temp_free(val); 550e5918d7dSYoshinori Sato return true; 551e5918d7dSYoshinori Sato } 552e5918d7dSYoshinori Sato 553e5918d7dSYoshinori Sato /* mov.<bwl> [rd+],rs */ 554e5918d7dSYoshinori Sato /* mov.<bwl> [-rd],rs */ 555e5918d7dSYoshinori Sato static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) 556e5918d7dSYoshinori Sato { 557e5918d7dSYoshinori Sato TCGv val; 558e5918d7dSYoshinori Sato val = tcg_temp_new(); 559e5918d7dSYoshinori Sato if (a->ad == 1) { 560e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 561e5918d7dSYoshinori Sato } 562e5918d7dSYoshinori Sato rx_gen_ld(a->sz, val, cpu_regs[a->rd]); 563e5918d7dSYoshinori Sato if (a->ad == 0) { 564e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 565e5918d7dSYoshinori Sato } 566e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rs], val); 567e5918d7dSYoshinori Sato tcg_temp_free(val); 568e5918d7dSYoshinori Sato return true; 569e5918d7dSYoshinori Sato } 570e5918d7dSYoshinori Sato 571e5918d7dSYoshinori Sato /* movu.<bw> dsp5[rs],rd */ 572e5918d7dSYoshinori Sato /* movu.<bw> dsp[rs],rd */ 573e5918d7dSYoshinori Sato static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a) 574e5918d7dSYoshinori Sato { 575e5918d7dSYoshinori Sato TCGv mem; 576e5918d7dSYoshinori Sato mem = tcg_temp_new(); 577e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 578e5918d7dSYoshinori Sato rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 579e5918d7dSYoshinori Sato tcg_temp_free(mem); 580e5918d7dSYoshinori Sato return true; 581e5918d7dSYoshinori Sato } 582e5918d7dSYoshinori Sato 583e5918d7dSYoshinori Sato /* movu.<bw> rs,rd */ 584e5918d7dSYoshinori Sato static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a) 585e5918d7dSYoshinori Sato { 586e5918d7dSYoshinori Sato static void (* const ext[])(TCGv ret, TCGv arg) = { 587e5918d7dSYoshinori Sato tcg_gen_ext8u_i32, tcg_gen_ext16u_i32, 588e5918d7dSYoshinori Sato }; 589e5918d7dSYoshinori Sato ext[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]); 590e5918d7dSYoshinori Sato return true; 591e5918d7dSYoshinori Sato } 592e5918d7dSYoshinori Sato 593e5918d7dSYoshinori Sato /* movu.<bw> [ri,rb],rd */ 594e5918d7dSYoshinori Sato static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a) 595e5918d7dSYoshinori Sato { 596e5918d7dSYoshinori Sato TCGv mem; 597e5918d7dSYoshinori Sato mem = tcg_temp_new(); 598e5918d7dSYoshinori Sato rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 599e5918d7dSYoshinori Sato rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 600e5918d7dSYoshinori Sato tcg_temp_free(mem); 601e5918d7dSYoshinori Sato return true; 602e5918d7dSYoshinori Sato } 603e5918d7dSYoshinori Sato 604e5918d7dSYoshinori Sato /* movu.<bw> [rd+],rs */ 605e5918d7dSYoshinori Sato /* mov.<bw> [-rd],rs */ 606e5918d7dSYoshinori Sato static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) 607e5918d7dSYoshinori Sato { 608e5918d7dSYoshinori Sato TCGv val; 609e5918d7dSYoshinori Sato val = tcg_temp_new(); 610e5918d7dSYoshinori Sato if (a->ad == 1) { 611e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 612e5918d7dSYoshinori Sato } 613e5918d7dSYoshinori Sato rx_gen_ldu(a->sz, val, cpu_regs[a->rd]); 614e5918d7dSYoshinori Sato if (a->ad == 0) { 615e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 616e5918d7dSYoshinori Sato } 617e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rs], val); 618e5918d7dSYoshinori Sato tcg_temp_free(val); 619e5918d7dSYoshinori Sato return true; 620e5918d7dSYoshinori Sato } 621e5918d7dSYoshinori Sato 622e5918d7dSYoshinori Sato 623e5918d7dSYoshinori Sato /* pop rd */ 624e5918d7dSYoshinori Sato static bool trans_POP(DisasContext *ctx, arg_POP *a) 625e5918d7dSYoshinori Sato { 626e5918d7dSYoshinori Sato /* mov.l [r0+], rd */ 627e5918d7dSYoshinori Sato arg_MOV_rp mov_a; 628e5918d7dSYoshinori Sato mov_a.rd = 0; 629e5918d7dSYoshinori Sato mov_a.rs = a->rd; 630e5918d7dSYoshinori Sato mov_a.ad = 0; 631e5918d7dSYoshinori Sato mov_a.sz = MO_32; 632e5918d7dSYoshinori Sato trans_MOV_pr(ctx, &mov_a); 633e5918d7dSYoshinori Sato return true; 634e5918d7dSYoshinori Sato } 635e5918d7dSYoshinori Sato 636e5918d7dSYoshinori Sato /* popc cr */ 637e5918d7dSYoshinori Sato static bool trans_POPC(DisasContext *ctx, arg_POPC *a) 638e5918d7dSYoshinori Sato { 639e5918d7dSYoshinori Sato TCGv val; 640e5918d7dSYoshinori Sato val = tcg_temp_new(); 641e5918d7dSYoshinori Sato pop(val); 642e5918d7dSYoshinori Sato move_to_cr(ctx, val, a->cr); 643e5918d7dSYoshinori Sato if (a->cr == 0 && is_privileged(ctx, 0)) { 644e5918d7dSYoshinori Sato /* PSW.I may be updated here. exit TB. */ 645e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_UPDATE; 646e5918d7dSYoshinori Sato } 647e5918d7dSYoshinori Sato tcg_temp_free(val); 648e5918d7dSYoshinori Sato return true; 649e5918d7dSYoshinori Sato } 650e5918d7dSYoshinori Sato 651e5918d7dSYoshinori Sato /* popm rd-rd2 */ 652e5918d7dSYoshinori Sato static bool trans_POPM(DisasContext *ctx, arg_POPM *a) 653e5918d7dSYoshinori Sato { 654e5918d7dSYoshinori Sato int r; 655e5918d7dSYoshinori Sato if (a->rd == 0 || a->rd >= a->rd2) { 656e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 657e5918d7dSYoshinori Sato "Invalid register ranges r%d-r%d", a->rd, a->rd2); 658e5918d7dSYoshinori Sato } 659e5918d7dSYoshinori Sato r = a->rd; 660e5918d7dSYoshinori Sato while (r <= a->rd2 && r < 16) { 661e5918d7dSYoshinori Sato pop(cpu_regs[r++]); 662e5918d7dSYoshinori Sato } 663e5918d7dSYoshinori Sato return true; 664e5918d7dSYoshinori Sato } 665e5918d7dSYoshinori Sato 666e5918d7dSYoshinori Sato 667e5918d7dSYoshinori Sato /* push.<bwl> rs */ 668e5918d7dSYoshinori Sato static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) 669e5918d7dSYoshinori Sato { 670e5918d7dSYoshinori Sato TCGv val; 671e5918d7dSYoshinori Sato val = tcg_temp_new(); 672e5918d7dSYoshinori Sato tcg_gen_mov_i32(val, cpu_regs[a->rs]); 673e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 674e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, cpu_sp); 675e5918d7dSYoshinori Sato tcg_temp_free(val); 676e5918d7dSYoshinori Sato return true; 677e5918d7dSYoshinori Sato } 678e5918d7dSYoshinori Sato 679e5918d7dSYoshinori Sato /* push.<bwl> dsp[rs] */ 680e5918d7dSYoshinori Sato static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) 681e5918d7dSYoshinori Sato { 682e5918d7dSYoshinori Sato TCGv mem, val, addr; 683e5918d7dSYoshinori Sato mem = tcg_temp_new(); 684e5918d7dSYoshinori Sato val = tcg_temp_new(); 685e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs); 686e5918d7dSYoshinori Sato rx_gen_ld(a->sz, val, addr); 687e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 688e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, cpu_sp); 689e5918d7dSYoshinori Sato tcg_temp_free(mem); 690e5918d7dSYoshinori Sato tcg_temp_free(val); 691e5918d7dSYoshinori Sato return true; 692e5918d7dSYoshinori Sato } 693e5918d7dSYoshinori Sato 694e5918d7dSYoshinori Sato /* pushc rx */ 695e5918d7dSYoshinori Sato static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) 696e5918d7dSYoshinori Sato { 697e5918d7dSYoshinori Sato TCGv val; 698e5918d7dSYoshinori Sato val = tcg_temp_new(); 699e5918d7dSYoshinori Sato move_from_cr(val, a->cr, ctx->pc); 700e5918d7dSYoshinori Sato push(val); 701e5918d7dSYoshinori Sato tcg_temp_free(val); 702e5918d7dSYoshinori Sato return true; 703e5918d7dSYoshinori Sato } 704e5918d7dSYoshinori Sato 705e5918d7dSYoshinori Sato /* pushm rs-rs2 */ 706e5918d7dSYoshinori Sato static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) 707e5918d7dSYoshinori Sato { 708e5918d7dSYoshinori Sato int r; 709e5918d7dSYoshinori Sato 710e5918d7dSYoshinori Sato if (a->rs == 0 || a->rs >= a->rs2) { 711e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 712e5918d7dSYoshinori Sato "Invalid register ranges r%d-r%d", a->rs, a->rs2); 713e5918d7dSYoshinori Sato } 714e5918d7dSYoshinori Sato r = a->rs2; 715e5918d7dSYoshinori Sato while (r >= a->rs && r >= 0) { 716e5918d7dSYoshinori Sato push(cpu_regs[r--]); 717e5918d7dSYoshinori Sato } 718e5918d7dSYoshinori Sato return true; 719e5918d7dSYoshinori Sato } 720e5918d7dSYoshinori Sato 721e5918d7dSYoshinori Sato /* xchg rs,rd */ 722e5918d7dSYoshinori Sato static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) 723e5918d7dSYoshinori Sato { 724e5918d7dSYoshinori Sato TCGv tmp; 725e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 726e5918d7dSYoshinori Sato tcg_gen_mov_i32(tmp, cpu_regs[a->rs]); 727e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); 728e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rd], tmp); 729e5918d7dSYoshinori Sato tcg_temp_free(tmp); 730e5918d7dSYoshinori Sato return true; 731e5918d7dSYoshinori Sato } 732e5918d7dSYoshinori Sato 733e5918d7dSYoshinori Sato /* xchg dsp[rs].<mi>,rd */ 734e5918d7dSYoshinori Sato static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) 735e5918d7dSYoshinori Sato { 736e5918d7dSYoshinori Sato TCGv mem, addr; 737e5918d7dSYoshinori Sato mem = tcg_temp_new(); 738e5918d7dSYoshinori Sato switch (a->mi) { 739e5918d7dSYoshinori Sato case 0: /* dsp[rs].b */ 740e5918d7dSYoshinori Sato case 1: /* dsp[rs].w */ 741e5918d7dSYoshinori Sato case 2: /* dsp[rs].l */ 742e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, a->mi, a->rs); 743e5918d7dSYoshinori Sato break; 744e5918d7dSYoshinori Sato case 3: /* dsp[rs].uw */ 745e5918d7dSYoshinori Sato case 4: /* dsp[rs].ub */ 746e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs); 747e5918d7dSYoshinori Sato break; 748e5918d7dSYoshinori Sato default: 749e5918d7dSYoshinori Sato g_assert_not_reached(); 750e5918d7dSYoshinori Sato } 751e5918d7dSYoshinori Sato tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd], 752e5918d7dSYoshinori Sato 0, mi_to_mop(a->mi)); 753e5918d7dSYoshinori Sato tcg_temp_free(mem); 754e5918d7dSYoshinori Sato return true; 755e5918d7dSYoshinori Sato } 756e5918d7dSYoshinori Sato 757e5918d7dSYoshinori Sato static inline void stcond(TCGCond cond, int rd, int imm) 758e5918d7dSYoshinori Sato { 759e5918d7dSYoshinori Sato TCGv z; 760e5918d7dSYoshinori Sato TCGv _imm; 761e5918d7dSYoshinori Sato z = tcg_const_i32(0); 762e5918d7dSYoshinori Sato _imm = tcg_const_i32(imm); 763e5918d7dSYoshinori Sato tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, 764e5918d7dSYoshinori Sato _imm, cpu_regs[rd]); 765e5918d7dSYoshinori Sato tcg_temp_free(z); 766e5918d7dSYoshinori Sato tcg_temp_free(_imm); 767e5918d7dSYoshinori Sato } 768e5918d7dSYoshinori Sato 769e5918d7dSYoshinori Sato /* stz #imm,rd */ 770e5918d7dSYoshinori Sato static bool trans_STZ(DisasContext *ctx, arg_STZ *a) 771e5918d7dSYoshinori Sato { 772e5918d7dSYoshinori Sato stcond(TCG_COND_EQ, a->rd, a->imm); 773e5918d7dSYoshinori Sato return true; 774e5918d7dSYoshinori Sato } 775e5918d7dSYoshinori Sato 776e5918d7dSYoshinori Sato /* stnz #imm,rd */ 777e5918d7dSYoshinori Sato static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a) 778e5918d7dSYoshinori Sato { 779e5918d7dSYoshinori Sato stcond(TCG_COND_NE, a->rd, a->imm); 780e5918d7dSYoshinori Sato return true; 781e5918d7dSYoshinori Sato } 782e5918d7dSYoshinori Sato 783e5918d7dSYoshinori Sato /* sccnd.<bwl> rd */ 784e5918d7dSYoshinori Sato /* sccnd.<bwl> dsp:[rd] */ 785e5918d7dSYoshinori Sato static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) 786e5918d7dSYoshinori Sato { 787e5918d7dSYoshinori Sato DisasCompare dc; 788e5918d7dSYoshinori Sato TCGv val, mem, addr; 789e5918d7dSYoshinori Sato dc.temp = tcg_temp_new(); 790e5918d7dSYoshinori Sato psw_cond(&dc, a->cd); 791e5918d7dSYoshinori Sato if (a->ld < 3) { 792e5918d7dSYoshinori Sato val = tcg_temp_new(); 793e5918d7dSYoshinori Sato mem = tcg_temp_new(); 794e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0); 795e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); 796e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, addr); 797e5918d7dSYoshinori Sato tcg_temp_free(val); 798e5918d7dSYoshinori Sato tcg_temp_free(mem); 799e5918d7dSYoshinori Sato } else { 800e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); 801e5918d7dSYoshinori Sato } 802e5918d7dSYoshinori Sato tcg_temp_free(dc.temp); 803e5918d7dSYoshinori Sato return true; 804e5918d7dSYoshinori Sato } 805e5918d7dSYoshinori Sato 806e5918d7dSYoshinori Sato /* rtsd #imm */ 807e5918d7dSYoshinori Sato static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a) 808e5918d7dSYoshinori Sato { 809e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2); 810e5918d7dSYoshinori Sato pop(cpu_pc); 811e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 812e5918d7dSYoshinori Sato return true; 813e5918d7dSYoshinori Sato } 814e5918d7dSYoshinori Sato 815e5918d7dSYoshinori Sato /* rtsd #imm, rd-rd2 */ 816e5918d7dSYoshinori Sato static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a) 817e5918d7dSYoshinori Sato { 818e5918d7dSYoshinori Sato int dst; 819e5918d7dSYoshinori Sato int adj; 820e5918d7dSYoshinori Sato 821e5918d7dSYoshinori Sato if (a->rd2 >= a->rd) { 822e5918d7dSYoshinori Sato adj = a->imm - (a->rd2 - a->rd + 1); 823e5918d7dSYoshinori Sato } else { 824e5918d7dSYoshinori Sato adj = a->imm - (15 - a->rd + 1); 825e5918d7dSYoshinori Sato } 826e5918d7dSYoshinori Sato 827e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_sp, cpu_sp, adj << 2); 828e5918d7dSYoshinori Sato dst = a->rd; 829e5918d7dSYoshinori Sato while (dst <= a->rd2 && dst < 16) { 830e5918d7dSYoshinori Sato pop(cpu_regs[dst++]); 831e5918d7dSYoshinori Sato } 832e5918d7dSYoshinori Sato pop(cpu_pc); 833e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 834e5918d7dSYoshinori Sato return true; 835e5918d7dSYoshinori Sato } 836e5918d7dSYoshinori Sato 837e5918d7dSYoshinori Sato typedef void (*op2fn)(TCGv ret, TCGv arg1); 838e5918d7dSYoshinori Sato typedef void (*op3fn)(TCGv ret, TCGv arg1, TCGv arg2); 839e5918d7dSYoshinori Sato 840e5918d7dSYoshinori Sato static inline void rx_gen_op_rr(op2fn opr, int dst, int src) 841e5918d7dSYoshinori Sato { 842e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[src]); 843e5918d7dSYoshinori Sato } 844e5918d7dSYoshinori Sato 845e5918d7dSYoshinori Sato static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2) 846e5918d7dSYoshinori Sato { 847e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[src], cpu_regs[src2]); 848e5918d7dSYoshinori Sato } 849e5918d7dSYoshinori Sato 850e5918d7dSYoshinori Sato static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2) 851e5918d7dSYoshinori Sato { 852e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(src2); 853e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[src], imm); 854e5918d7dSYoshinori Sato tcg_temp_free(imm); 855e5918d7dSYoshinori Sato } 856e5918d7dSYoshinori Sato 857e5918d7dSYoshinori Sato static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx, 858e5918d7dSYoshinori Sato int dst, int src, int ld, int mi) 859e5918d7dSYoshinori Sato { 860e5918d7dSYoshinori Sato TCGv val, mem; 861e5918d7dSYoshinori Sato mem = tcg_temp_new(); 862e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, ld, mi, src); 863e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[dst], val); 864e5918d7dSYoshinori Sato tcg_temp_free(mem); 865e5918d7dSYoshinori Sato } 866e5918d7dSYoshinori Sato 867e5918d7dSYoshinori Sato static void rx_and(TCGv ret, TCGv arg1, TCGv arg2) 868e5918d7dSYoshinori Sato { 869e5918d7dSYoshinori Sato tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 870e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 871e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 872e5918d7dSYoshinori Sato } 873e5918d7dSYoshinori Sato 874e5918d7dSYoshinori Sato /* and #uimm:4, rd */ 875e5918d7dSYoshinori Sato /* and #imm, rd */ 876e5918d7dSYoshinori Sato static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a) 877e5918d7dSYoshinori Sato { 878e5918d7dSYoshinori Sato rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm); 879e5918d7dSYoshinori Sato return true; 880e5918d7dSYoshinori Sato } 881e5918d7dSYoshinori Sato 882e5918d7dSYoshinori Sato /* and dsp[rs], rd */ 883e5918d7dSYoshinori Sato /* and rs,rd */ 884e5918d7dSYoshinori Sato static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a) 885e5918d7dSYoshinori Sato { 886e5918d7dSYoshinori Sato rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi); 887e5918d7dSYoshinori Sato return true; 888e5918d7dSYoshinori Sato } 889e5918d7dSYoshinori Sato 890e5918d7dSYoshinori Sato /* and rs,rs2,rd */ 891e5918d7dSYoshinori Sato static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a) 892e5918d7dSYoshinori Sato { 893e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2); 894e5918d7dSYoshinori Sato return true; 895e5918d7dSYoshinori Sato } 896e5918d7dSYoshinori Sato 897e5918d7dSYoshinori Sato static void rx_or(TCGv ret, TCGv arg1, TCGv arg2) 898e5918d7dSYoshinori Sato { 899e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_psw_s, arg1, arg2); 900e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 901e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 902e5918d7dSYoshinori Sato } 903e5918d7dSYoshinori Sato 904e5918d7dSYoshinori Sato /* or #uimm:4, rd */ 905e5918d7dSYoshinori Sato /* or #imm, rd */ 906e5918d7dSYoshinori Sato static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a) 907e5918d7dSYoshinori Sato { 908e5918d7dSYoshinori Sato rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm); 909e5918d7dSYoshinori Sato return true; 910e5918d7dSYoshinori Sato } 911e5918d7dSYoshinori Sato 912e5918d7dSYoshinori Sato /* or dsp[rs], rd */ 913e5918d7dSYoshinori Sato /* or rs,rd */ 914e5918d7dSYoshinori Sato static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a) 915e5918d7dSYoshinori Sato { 916e5918d7dSYoshinori Sato rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi); 917e5918d7dSYoshinori Sato return true; 918e5918d7dSYoshinori Sato } 919e5918d7dSYoshinori Sato 920e5918d7dSYoshinori Sato /* or rs,rs2,rd */ 921e5918d7dSYoshinori Sato static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a) 922e5918d7dSYoshinori Sato { 923e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2); 924e5918d7dSYoshinori Sato return true; 925e5918d7dSYoshinori Sato } 926e5918d7dSYoshinori Sato 927e5918d7dSYoshinori Sato static void rx_xor(TCGv ret, TCGv arg1, TCGv arg2) 928e5918d7dSYoshinori Sato { 929e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_s, arg1, arg2); 930e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 931e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 932e5918d7dSYoshinori Sato } 933e5918d7dSYoshinori Sato 934e5918d7dSYoshinori Sato /* xor #imm, rd */ 935e5918d7dSYoshinori Sato static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a) 936e5918d7dSYoshinori Sato { 937e5918d7dSYoshinori Sato rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm); 938e5918d7dSYoshinori Sato return true; 939e5918d7dSYoshinori Sato } 940e5918d7dSYoshinori Sato 941e5918d7dSYoshinori Sato /* xor dsp[rs], rd */ 942e5918d7dSYoshinori Sato /* xor rs,rd */ 943e5918d7dSYoshinori Sato static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a) 944e5918d7dSYoshinori Sato { 945e5918d7dSYoshinori Sato rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi); 946e5918d7dSYoshinori Sato return true; 947e5918d7dSYoshinori Sato } 948e5918d7dSYoshinori Sato 949e5918d7dSYoshinori Sato static void rx_tst(TCGv ret, TCGv arg1, TCGv arg2) 950e5918d7dSYoshinori Sato { 951e5918d7dSYoshinori Sato tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 952e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 953e5918d7dSYoshinori Sato } 954e5918d7dSYoshinori Sato 955e5918d7dSYoshinori Sato /* tst #imm, rd */ 956e5918d7dSYoshinori Sato static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a) 957e5918d7dSYoshinori Sato { 958e5918d7dSYoshinori Sato rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm); 959e5918d7dSYoshinori Sato return true; 960e5918d7dSYoshinori Sato } 961e5918d7dSYoshinori Sato 962e5918d7dSYoshinori Sato /* tst dsp[rs], rd */ 963e5918d7dSYoshinori Sato /* tst rs, rd */ 964e5918d7dSYoshinori Sato static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a) 965e5918d7dSYoshinori Sato { 966e5918d7dSYoshinori Sato rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi); 967e5918d7dSYoshinori Sato return true; 968e5918d7dSYoshinori Sato } 969e5918d7dSYoshinori Sato 970e5918d7dSYoshinori Sato static void rx_not(TCGv ret, TCGv arg1) 971e5918d7dSYoshinori Sato { 972e5918d7dSYoshinori Sato tcg_gen_not_i32(ret, arg1); 973e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, ret); 974e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, ret); 975e5918d7dSYoshinori Sato } 976e5918d7dSYoshinori Sato 977e5918d7dSYoshinori Sato /* not rd */ 978e5918d7dSYoshinori Sato /* not rs, rd */ 979e5918d7dSYoshinori Sato static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a) 980e5918d7dSYoshinori Sato { 981e5918d7dSYoshinori Sato rx_gen_op_rr(rx_not, a->rd, a->rs); 982e5918d7dSYoshinori Sato return true; 983e5918d7dSYoshinori Sato } 984e5918d7dSYoshinori Sato 985e5918d7dSYoshinori Sato static void rx_neg(TCGv ret, TCGv arg1) 986e5918d7dSYoshinori Sato { 987e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000); 988e5918d7dSYoshinori Sato tcg_gen_neg_i32(ret, arg1); 989e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, ret, 0); 990e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, ret); 991e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, ret); 992e5918d7dSYoshinori Sato } 993e5918d7dSYoshinori Sato 994e5918d7dSYoshinori Sato 995e5918d7dSYoshinori Sato /* neg rd */ 996e5918d7dSYoshinori Sato /* neg rs, rd */ 997e5918d7dSYoshinori Sato static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) 998e5918d7dSYoshinori Sato { 999e5918d7dSYoshinori Sato rx_gen_op_rr(rx_neg, a->rd, a->rs); 1000e5918d7dSYoshinori Sato return true; 1001e5918d7dSYoshinori Sato } 1002e5918d7dSYoshinori Sato 1003e5918d7dSYoshinori Sato /* ret = arg1 + arg2 + psw_c */ 1004e5918d7dSYoshinori Sato static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) 1005e5918d7dSYoshinori Sato { 1006e5918d7dSYoshinori Sato TCGv z; 1007e5918d7dSYoshinori Sato z = tcg_const_i32(0); 1008e5918d7dSYoshinori Sato tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); 1009e5918d7dSYoshinori Sato tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); 1010e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 1011e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1012e5918d7dSYoshinori Sato tcg_gen_xor_i32(z, arg1, arg2); 1013e5918d7dSYoshinori Sato tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); 1014e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 1015e5918d7dSYoshinori Sato tcg_temp_free(z); 1016e5918d7dSYoshinori Sato } 1017e5918d7dSYoshinori Sato 1018e5918d7dSYoshinori Sato /* adc #imm, rd */ 1019e5918d7dSYoshinori Sato static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a) 1020e5918d7dSYoshinori Sato { 1021e5918d7dSYoshinori Sato rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm); 1022e5918d7dSYoshinori Sato return true; 1023e5918d7dSYoshinori Sato } 1024e5918d7dSYoshinori Sato 1025e5918d7dSYoshinori Sato /* adc rs, rd */ 1026e5918d7dSYoshinori Sato static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a) 1027e5918d7dSYoshinori Sato { 1028e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs); 1029e5918d7dSYoshinori Sato return true; 1030e5918d7dSYoshinori Sato } 1031e5918d7dSYoshinori Sato 1032e5918d7dSYoshinori Sato /* adc dsp[rs], rd */ 1033e5918d7dSYoshinori Sato static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) 1034e5918d7dSYoshinori Sato { 1035e5918d7dSYoshinori Sato /* mi only 2 */ 1036e5918d7dSYoshinori Sato if (a->mi != 2) { 1037e5918d7dSYoshinori Sato return false; 1038e5918d7dSYoshinori Sato } 1039e5918d7dSYoshinori Sato rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi); 1040e5918d7dSYoshinori Sato return true; 1041e5918d7dSYoshinori Sato } 1042e5918d7dSYoshinori Sato 1043e5918d7dSYoshinori Sato /* ret = arg1 + arg2 */ 1044e5918d7dSYoshinori Sato static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) 1045e5918d7dSYoshinori Sato { 1046e5918d7dSYoshinori Sato TCGv z; 1047e5918d7dSYoshinori Sato z = tcg_const_i32(0); 1048e5918d7dSYoshinori Sato tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); 1049e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 1050e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1051e5918d7dSYoshinori Sato tcg_gen_xor_i32(z, arg1, arg2); 1052e5918d7dSYoshinori Sato tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); 1053e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 1054e5918d7dSYoshinori Sato tcg_temp_free(z); 1055e5918d7dSYoshinori Sato } 1056e5918d7dSYoshinori Sato 1057e5918d7dSYoshinori Sato /* add #uimm4, rd */ 1058e5918d7dSYoshinori Sato /* add #imm, rs, rd */ 1059e5918d7dSYoshinori Sato static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a) 1060e5918d7dSYoshinori Sato { 1061e5918d7dSYoshinori Sato rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm); 1062e5918d7dSYoshinori Sato return true; 1063e5918d7dSYoshinori Sato } 1064e5918d7dSYoshinori Sato 1065e5918d7dSYoshinori Sato /* add rs, rd */ 1066e5918d7dSYoshinori Sato /* add dsp[rs], rd */ 1067e5918d7dSYoshinori Sato static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a) 1068e5918d7dSYoshinori Sato { 1069e5918d7dSYoshinori Sato rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi); 1070e5918d7dSYoshinori Sato return true; 1071e5918d7dSYoshinori Sato } 1072e5918d7dSYoshinori Sato 1073e5918d7dSYoshinori Sato /* add rs, rs2, rd */ 1074e5918d7dSYoshinori Sato static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a) 1075e5918d7dSYoshinori Sato { 1076e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2); 1077e5918d7dSYoshinori Sato return true; 1078e5918d7dSYoshinori Sato } 1079e5918d7dSYoshinori Sato 1080e5918d7dSYoshinori Sato /* ret = arg1 - arg2 */ 1081e5918d7dSYoshinori Sato static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) 1082e5918d7dSYoshinori Sato { 1083e5918d7dSYoshinori Sato TCGv temp; 1084e5918d7dSYoshinori Sato tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); 1085e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 1086e5918d7dSYoshinori Sato tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); 1087e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1088e5918d7dSYoshinori Sato temp = tcg_temp_new_i32(); 1089e5918d7dSYoshinori Sato tcg_gen_xor_i32(temp, arg1, arg2); 1090e5918d7dSYoshinori Sato tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp); 1091e5918d7dSYoshinori Sato tcg_temp_free_i32(temp); 1092*97841438SLichang Zhao /* CMP not required return */ 1093e5918d7dSYoshinori Sato if (ret) { 1094e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 1095e5918d7dSYoshinori Sato } 1096e5918d7dSYoshinori Sato } 1097e5918d7dSYoshinori Sato static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2) 1098e5918d7dSYoshinori Sato { 1099e5918d7dSYoshinori Sato rx_sub(NULL, arg1, arg2); 1100e5918d7dSYoshinori Sato } 1101e5918d7dSYoshinori Sato /* ret = arg1 - arg2 - !psw_c */ 1102e5918d7dSYoshinori Sato /* -> ret = arg1 + ~arg2 + psw_c */ 1103e5918d7dSYoshinori Sato static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) 1104e5918d7dSYoshinori Sato { 1105e5918d7dSYoshinori Sato TCGv temp; 1106e5918d7dSYoshinori Sato temp = tcg_temp_new(); 1107e5918d7dSYoshinori Sato tcg_gen_not_i32(temp, arg2); 1108e5918d7dSYoshinori Sato rx_adc(ret, arg1, temp); 1109e5918d7dSYoshinori Sato tcg_temp_free(temp); 1110e5918d7dSYoshinori Sato } 1111e5918d7dSYoshinori Sato 1112e5918d7dSYoshinori Sato /* cmp #imm4, rs2 */ 1113e5918d7dSYoshinori Sato /* cmp #imm8, rs2 */ 1114e5918d7dSYoshinori Sato /* cmp #imm, rs2 */ 1115e5918d7dSYoshinori Sato static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a) 1116e5918d7dSYoshinori Sato { 1117e5918d7dSYoshinori Sato rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm); 1118e5918d7dSYoshinori Sato return true; 1119e5918d7dSYoshinori Sato } 1120e5918d7dSYoshinori Sato 1121e5918d7dSYoshinori Sato /* cmp rs, rs2 */ 1122e5918d7dSYoshinori Sato /* cmp dsp[rs], rs2 */ 1123e5918d7dSYoshinori Sato static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a) 1124e5918d7dSYoshinori Sato { 1125e5918d7dSYoshinori Sato rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi); 1126e5918d7dSYoshinori Sato return true; 1127e5918d7dSYoshinori Sato } 1128e5918d7dSYoshinori Sato 1129e5918d7dSYoshinori Sato /* sub #imm4, rd */ 1130e5918d7dSYoshinori Sato static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a) 1131e5918d7dSYoshinori Sato { 1132e5918d7dSYoshinori Sato rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm); 1133e5918d7dSYoshinori Sato return true; 1134e5918d7dSYoshinori Sato } 1135e5918d7dSYoshinori Sato 1136e5918d7dSYoshinori Sato /* sub rs, rd */ 1137e5918d7dSYoshinori Sato /* sub dsp[rs], rd */ 1138e5918d7dSYoshinori Sato static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a) 1139e5918d7dSYoshinori Sato { 1140e5918d7dSYoshinori Sato rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi); 1141e5918d7dSYoshinori Sato return true; 1142e5918d7dSYoshinori Sato } 1143e5918d7dSYoshinori Sato 1144e5918d7dSYoshinori Sato /* sub rs2, rs, rd */ 1145e5918d7dSYoshinori Sato static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a) 1146e5918d7dSYoshinori Sato { 1147e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs); 1148e5918d7dSYoshinori Sato return true; 1149e5918d7dSYoshinori Sato } 1150e5918d7dSYoshinori Sato 1151e5918d7dSYoshinori Sato /* sbb rs, rd */ 1152e5918d7dSYoshinori Sato static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a) 1153e5918d7dSYoshinori Sato { 1154e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs); 1155e5918d7dSYoshinori Sato return true; 1156e5918d7dSYoshinori Sato } 1157e5918d7dSYoshinori Sato 1158e5918d7dSYoshinori Sato /* sbb dsp[rs], rd */ 1159e5918d7dSYoshinori Sato static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) 1160e5918d7dSYoshinori Sato { 1161e5918d7dSYoshinori Sato /* mi only 2 */ 1162e5918d7dSYoshinori Sato if (a->mi != 2) { 1163e5918d7dSYoshinori Sato return false; 1164e5918d7dSYoshinori Sato } 1165e5918d7dSYoshinori Sato rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi); 1166e5918d7dSYoshinori Sato return true; 1167e5918d7dSYoshinori Sato } 1168e5918d7dSYoshinori Sato 1169e5918d7dSYoshinori Sato static void rx_abs(TCGv ret, TCGv arg1) 1170e5918d7dSYoshinori Sato { 1171e5918d7dSYoshinori Sato TCGv neg; 1172e5918d7dSYoshinori Sato TCGv zero; 1173e5918d7dSYoshinori Sato neg = tcg_temp_new(); 1174e5918d7dSYoshinori Sato zero = tcg_const_i32(0); 1175e5918d7dSYoshinori Sato tcg_gen_neg_i32(neg, arg1); 1176e5918d7dSYoshinori Sato tcg_gen_movcond_i32(TCG_COND_LT, ret, arg1, zero, neg, arg1); 1177e5918d7dSYoshinori Sato tcg_temp_free(neg); 1178e5918d7dSYoshinori Sato tcg_temp_free(zero); 1179e5918d7dSYoshinori Sato } 1180e5918d7dSYoshinori Sato 1181e5918d7dSYoshinori Sato /* abs rd */ 1182e5918d7dSYoshinori Sato /* abs rs, rd */ 1183e5918d7dSYoshinori Sato static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) 1184e5918d7dSYoshinori Sato { 1185e5918d7dSYoshinori Sato rx_gen_op_rr(rx_abs, a->rd, a->rs); 1186e5918d7dSYoshinori Sato return true; 1187e5918d7dSYoshinori Sato } 1188e5918d7dSYoshinori Sato 1189e5918d7dSYoshinori Sato /* max #imm, rd */ 1190e5918d7dSYoshinori Sato static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a) 1191e5918d7dSYoshinori Sato { 1192e5918d7dSYoshinori Sato rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm); 1193e5918d7dSYoshinori Sato return true; 1194e5918d7dSYoshinori Sato } 1195e5918d7dSYoshinori Sato 1196e5918d7dSYoshinori Sato /* max rs, rd */ 1197e5918d7dSYoshinori Sato /* max dsp[rs], rd */ 1198e5918d7dSYoshinori Sato static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a) 1199e5918d7dSYoshinori Sato { 1200e5918d7dSYoshinori Sato rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1201e5918d7dSYoshinori Sato return true; 1202e5918d7dSYoshinori Sato } 1203e5918d7dSYoshinori Sato 1204e5918d7dSYoshinori Sato /* min #imm, rd */ 1205e5918d7dSYoshinori Sato static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a) 1206e5918d7dSYoshinori Sato { 1207e5918d7dSYoshinori Sato rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm); 1208e5918d7dSYoshinori Sato return true; 1209e5918d7dSYoshinori Sato } 1210e5918d7dSYoshinori Sato 1211e5918d7dSYoshinori Sato /* min rs, rd */ 1212e5918d7dSYoshinori Sato /* min dsp[rs], rd */ 1213e5918d7dSYoshinori Sato static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a) 1214e5918d7dSYoshinori Sato { 1215e5918d7dSYoshinori Sato rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1216e5918d7dSYoshinori Sato return true; 1217e5918d7dSYoshinori Sato } 1218e5918d7dSYoshinori Sato 1219e5918d7dSYoshinori Sato /* mul #uimm4, rd */ 1220e5918d7dSYoshinori Sato /* mul #imm, rd */ 1221e5918d7dSYoshinori Sato static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a) 1222e5918d7dSYoshinori Sato { 1223e5918d7dSYoshinori Sato rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm); 1224e5918d7dSYoshinori Sato return true; 1225e5918d7dSYoshinori Sato } 1226e5918d7dSYoshinori Sato 1227e5918d7dSYoshinori Sato /* mul rs, rd */ 1228e5918d7dSYoshinori Sato /* mul dsp[rs], rd */ 1229e5918d7dSYoshinori Sato static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a) 1230e5918d7dSYoshinori Sato { 1231e5918d7dSYoshinori Sato rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1232e5918d7dSYoshinori Sato return true; 1233e5918d7dSYoshinori Sato } 1234e5918d7dSYoshinori Sato 1235e5918d7dSYoshinori Sato /* mul rs, rs2, rd */ 1236e5918d7dSYoshinori Sato static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a) 1237e5918d7dSYoshinori Sato { 1238e5918d7dSYoshinori Sato rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2); 1239e5918d7dSYoshinori Sato return true; 1240e5918d7dSYoshinori Sato } 1241e5918d7dSYoshinori Sato 1242e5918d7dSYoshinori Sato /* emul #imm, rd */ 1243e5918d7dSYoshinori Sato static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) 1244e5918d7dSYoshinori Sato { 1245e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(a->imm); 1246e5918d7dSYoshinori Sato if (a->rd > 14) { 1247e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1248e5918d7dSYoshinori Sato } 1249e5918d7dSYoshinori Sato tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1250e5918d7dSYoshinori Sato cpu_regs[a->rd], imm); 1251e5918d7dSYoshinori Sato tcg_temp_free(imm); 1252e5918d7dSYoshinori Sato return true; 1253e5918d7dSYoshinori Sato } 1254e5918d7dSYoshinori Sato 1255e5918d7dSYoshinori Sato /* emul rs, rd */ 1256e5918d7dSYoshinori Sato /* emul dsp[rs], rd */ 1257e5918d7dSYoshinori Sato static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) 1258e5918d7dSYoshinori Sato { 1259e5918d7dSYoshinori Sato TCGv val, mem; 1260e5918d7dSYoshinori Sato if (a->rd > 14) { 1261e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1262e5918d7dSYoshinori Sato } 1263e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1264e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1265e5918d7dSYoshinori Sato tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1266e5918d7dSYoshinori Sato cpu_regs[a->rd], val); 1267e5918d7dSYoshinori Sato tcg_temp_free(mem); 1268e5918d7dSYoshinori Sato return true; 1269e5918d7dSYoshinori Sato } 1270e5918d7dSYoshinori Sato 1271e5918d7dSYoshinori Sato /* emulu #imm, rd */ 1272e5918d7dSYoshinori Sato static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) 1273e5918d7dSYoshinori Sato { 1274e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(a->imm); 1275e5918d7dSYoshinori Sato if (a->rd > 14) { 1276e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1277e5918d7dSYoshinori Sato } 1278e5918d7dSYoshinori Sato tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1279e5918d7dSYoshinori Sato cpu_regs[a->rd], imm); 1280e5918d7dSYoshinori Sato tcg_temp_free(imm); 1281e5918d7dSYoshinori Sato return true; 1282e5918d7dSYoshinori Sato } 1283e5918d7dSYoshinori Sato 1284e5918d7dSYoshinori Sato /* emulu rs, rd */ 1285e5918d7dSYoshinori Sato /* emulu dsp[rs], rd */ 1286e5918d7dSYoshinori Sato static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) 1287e5918d7dSYoshinori Sato { 1288e5918d7dSYoshinori Sato TCGv val, mem; 1289e5918d7dSYoshinori Sato if (a->rd > 14) { 1290e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1291e5918d7dSYoshinori Sato } 1292e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1293e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1294e5918d7dSYoshinori Sato tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1295e5918d7dSYoshinori Sato cpu_regs[a->rd], val); 1296e5918d7dSYoshinori Sato tcg_temp_free(mem); 1297e5918d7dSYoshinori Sato return true; 1298e5918d7dSYoshinori Sato } 1299e5918d7dSYoshinori Sato 1300e5918d7dSYoshinori Sato static void rx_div(TCGv ret, TCGv arg1, TCGv arg2) 1301e5918d7dSYoshinori Sato { 1302e5918d7dSYoshinori Sato gen_helper_div(ret, cpu_env, arg1, arg2); 1303e5918d7dSYoshinori Sato } 1304e5918d7dSYoshinori Sato 1305e5918d7dSYoshinori Sato static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2) 1306e5918d7dSYoshinori Sato { 1307e5918d7dSYoshinori Sato gen_helper_divu(ret, cpu_env, arg1, arg2); 1308e5918d7dSYoshinori Sato } 1309e5918d7dSYoshinori Sato 1310e5918d7dSYoshinori Sato /* div #imm, rd */ 1311e5918d7dSYoshinori Sato static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a) 1312e5918d7dSYoshinori Sato { 1313e5918d7dSYoshinori Sato rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm); 1314e5918d7dSYoshinori Sato return true; 1315e5918d7dSYoshinori Sato } 1316e5918d7dSYoshinori Sato 1317e5918d7dSYoshinori Sato /* div rs, rd */ 1318e5918d7dSYoshinori Sato /* div dsp[rs], rd */ 1319e5918d7dSYoshinori Sato static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a) 1320e5918d7dSYoshinori Sato { 1321e5918d7dSYoshinori Sato rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi); 1322e5918d7dSYoshinori Sato return true; 1323e5918d7dSYoshinori Sato } 1324e5918d7dSYoshinori Sato 1325e5918d7dSYoshinori Sato /* divu #imm, rd */ 1326e5918d7dSYoshinori Sato static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a) 1327e5918d7dSYoshinori Sato { 1328e5918d7dSYoshinori Sato rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm); 1329e5918d7dSYoshinori Sato return true; 1330e5918d7dSYoshinori Sato } 1331e5918d7dSYoshinori Sato 1332e5918d7dSYoshinori Sato /* divu rs, rd */ 1333e5918d7dSYoshinori Sato /* divu dsp[rs], rd */ 1334e5918d7dSYoshinori Sato static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a) 1335e5918d7dSYoshinori Sato { 1336e5918d7dSYoshinori Sato rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi); 1337e5918d7dSYoshinori Sato return true; 1338e5918d7dSYoshinori Sato } 1339e5918d7dSYoshinori Sato 1340e5918d7dSYoshinori Sato 1341e5918d7dSYoshinori Sato /* shll #imm:5, rd */ 1342e5918d7dSYoshinori Sato /* shll #imm:5, rs2, rd */ 1343e5918d7dSYoshinori Sato static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) 1344e5918d7dSYoshinori Sato { 1345e5918d7dSYoshinori Sato TCGv tmp; 1346e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1347e5918d7dSYoshinori Sato if (a->imm) { 1348e5918d7dSYoshinori Sato tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm); 1349e5918d7dSYoshinori Sato tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm); 1350e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1351e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1352e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1353e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1354e5918d7dSYoshinori Sato } else { 1355e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]); 1356e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1357e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1358e5918d7dSYoshinori Sato } 1359e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1360e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1361e5918d7dSYoshinori Sato return true; 1362e5918d7dSYoshinori Sato } 1363e5918d7dSYoshinori Sato 1364e5918d7dSYoshinori Sato /* shll rs, rd */ 1365e5918d7dSYoshinori Sato static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) 1366e5918d7dSYoshinori Sato { 1367e5918d7dSYoshinori Sato TCGLabel *noshift, *done; 1368e5918d7dSYoshinori Sato TCGv count, tmp; 1369e5918d7dSYoshinori Sato 1370e5918d7dSYoshinori Sato noshift = gen_new_label(); 1371e5918d7dSYoshinori Sato done = gen_new_label(); 1372e5918d7dSYoshinori Sato /* if (cpu_regs[a->rs]) { */ 1373e5918d7dSYoshinori Sato tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); 1374e5918d7dSYoshinori Sato count = tcg_const_i32(32); 1375e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1376e5918d7dSYoshinori Sato tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); 1377e5918d7dSYoshinori Sato tcg_gen_sub_i32(count, count, tmp); 1378e5918d7dSYoshinori Sato tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); 1379e5918d7dSYoshinori Sato tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1380e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1381e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1382e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1383e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1384e5918d7dSYoshinori Sato tcg_gen_br(done); 1385e5918d7dSYoshinori Sato /* } else { */ 1386e5918d7dSYoshinori Sato gen_set_label(noshift); 1387e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1388e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1389e5918d7dSYoshinori Sato /* } */ 1390e5918d7dSYoshinori Sato gen_set_label(done); 1391e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1392e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1393e5918d7dSYoshinori Sato tcg_temp_free(count); 1394e5918d7dSYoshinori Sato tcg_temp_free(tmp); 1395e5918d7dSYoshinori Sato return true; 1396e5918d7dSYoshinori Sato } 1397e5918d7dSYoshinori Sato 1398e5918d7dSYoshinori Sato static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm, 1399e5918d7dSYoshinori Sato unsigned int alith) 1400e5918d7dSYoshinori Sato { 1401e5918d7dSYoshinori Sato static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1402e5918d7dSYoshinori Sato tcg_gen_shri_i32, tcg_gen_sari_i32, 1403e5918d7dSYoshinori Sato }; 1404e5918d7dSYoshinori Sato tcg_debug_assert(alith < 2); 1405e5918d7dSYoshinori Sato if (imm) { 1406e5918d7dSYoshinori Sato gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1); 1407e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1408e5918d7dSYoshinori Sato gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1409e5918d7dSYoshinori Sato } else { 1410e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[rd], cpu_regs[rs]); 1411e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1412e5918d7dSYoshinori Sato } 1413e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1414e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1415e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1416e5918d7dSYoshinori Sato } 1417e5918d7dSYoshinori Sato 1418e5918d7dSYoshinori Sato static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith) 1419e5918d7dSYoshinori Sato { 1420e5918d7dSYoshinori Sato TCGLabel *noshift, *done; 1421e5918d7dSYoshinori Sato TCGv count; 1422e5918d7dSYoshinori Sato static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1423e5918d7dSYoshinori Sato tcg_gen_shri_i32, tcg_gen_sari_i32, 1424e5918d7dSYoshinori Sato }; 1425e5918d7dSYoshinori Sato static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) = { 1426e5918d7dSYoshinori Sato tcg_gen_shr_i32, tcg_gen_sar_i32, 1427e5918d7dSYoshinori Sato }; 1428e5918d7dSYoshinori Sato tcg_debug_assert(alith < 2); 1429e5918d7dSYoshinori Sato noshift = gen_new_label(); 1430e5918d7dSYoshinori Sato done = gen_new_label(); 1431e5918d7dSYoshinori Sato count = tcg_temp_new(); 1432e5918d7dSYoshinori Sato /* if (cpu_regs[rs]) { */ 1433e5918d7dSYoshinori Sato tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[rs], 0, noshift); 1434e5918d7dSYoshinori Sato tcg_gen_andi_i32(count, cpu_regs[rs], 31); 1435e5918d7dSYoshinori Sato tcg_gen_subi_i32(count, count, 1); 1436e5918d7dSYoshinori Sato gen_sXr[alith](cpu_regs[rd], cpu_regs[rd], count); 1437e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1438e5918d7dSYoshinori Sato gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1439e5918d7dSYoshinori Sato tcg_gen_br(done); 1440e5918d7dSYoshinori Sato /* } else { */ 1441e5918d7dSYoshinori Sato gen_set_label(noshift); 1442e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1443e5918d7dSYoshinori Sato /* } */ 1444e5918d7dSYoshinori Sato gen_set_label(done); 1445e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1446e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1447e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1448e5918d7dSYoshinori Sato tcg_temp_free(count); 1449e5918d7dSYoshinori Sato } 1450e5918d7dSYoshinori Sato 1451e5918d7dSYoshinori Sato /* shar #imm:5, rd */ 1452e5918d7dSYoshinori Sato /* shar #imm:5, rs2, rd */ 1453e5918d7dSYoshinori Sato static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a) 1454e5918d7dSYoshinori Sato { 1455e5918d7dSYoshinori Sato shiftr_imm(a->rd, a->rs2, a->imm, 1); 1456e5918d7dSYoshinori Sato return true; 1457e5918d7dSYoshinori Sato } 1458e5918d7dSYoshinori Sato 1459e5918d7dSYoshinori Sato /* shar rs, rd */ 1460e5918d7dSYoshinori Sato static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a) 1461e5918d7dSYoshinori Sato { 1462e5918d7dSYoshinori Sato shiftr_reg(a->rd, a->rs, 1); 1463e5918d7dSYoshinori Sato return true; 1464e5918d7dSYoshinori Sato } 1465e5918d7dSYoshinori Sato 1466e5918d7dSYoshinori Sato /* shlr #imm:5, rd */ 1467e5918d7dSYoshinori Sato /* shlr #imm:5, rs2, rd */ 1468e5918d7dSYoshinori Sato static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a) 1469e5918d7dSYoshinori Sato { 1470e5918d7dSYoshinori Sato shiftr_imm(a->rd, a->rs2, a->imm, 0); 1471e5918d7dSYoshinori Sato return true; 1472e5918d7dSYoshinori Sato } 1473e5918d7dSYoshinori Sato 1474e5918d7dSYoshinori Sato /* shlr rs, rd */ 1475e5918d7dSYoshinori Sato static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a) 1476e5918d7dSYoshinori Sato { 1477e5918d7dSYoshinori Sato shiftr_reg(a->rd, a->rs, 0); 1478e5918d7dSYoshinori Sato return true; 1479e5918d7dSYoshinori Sato } 1480e5918d7dSYoshinori Sato 1481e5918d7dSYoshinori Sato /* rolc rd */ 1482e5918d7dSYoshinori Sato static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) 1483e5918d7dSYoshinori Sato { 1484e5918d7dSYoshinori Sato TCGv tmp; 1485e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1486e5918d7dSYoshinori Sato tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31); 1487e5918d7dSYoshinori Sato tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1488e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1489e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_c, tmp); 1490e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1491e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1492e5918d7dSYoshinori Sato tcg_temp_free(tmp); 1493e5918d7dSYoshinori Sato return true; 1494e5918d7dSYoshinori Sato } 1495e5918d7dSYoshinori Sato 1496e5918d7dSYoshinori Sato /* rorc rd */ 1497e5918d7dSYoshinori Sato static bool trans_RORC(DisasContext *ctx, arg_RORC *a) 1498e5918d7dSYoshinori Sato { 1499e5918d7dSYoshinori Sato TCGv tmp; 1500e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1501e5918d7dSYoshinori Sato tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); 1502e5918d7dSYoshinori Sato tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1503e5918d7dSYoshinori Sato tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, 31); 1504e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1505e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_c, tmp); 1506e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1507e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1508e5918d7dSYoshinori Sato return true; 1509e5918d7dSYoshinori Sato } 1510e5918d7dSYoshinori Sato 1511e5918d7dSYoshinori Sato enum {ROTR = 0, ROTL = 1}; 1512e5918d7dSYoshinori Sato enum {ROT_IMM = 0, ROT_REG = 1}; 1513e5918d7dSYoshinori Sato static inline void rx_rot(int ir, int dir, int rd, int src) 1514e5918d7dSYoshinori Sato { 1515e5918d7dSYoshinori Sato switch (dir) { 1516e5918d7dSYoshinori Sato case ROTL: 1517e5918d7dSYoshinori Sato if (ir == ROT_IMM) { 1518e5918d7dSYoshinori Sato tcg_gen_rotli_i32(cpu_regs[rd], cpu_regs[rd], src); 1519e5918d7dSYoshinori Sato } else { 1520e5918d7dSYoshinori Sato tcg_gen_rotl_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1521e5918d7dSYoshinori Sato } 1522e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1523e5918d7dSYoshinori Sato break; 1524e5918d7dSYoshinori Sato case ROTR: 1525e5918d7dSYoshinori Sato if (ir == ROT_IMM) { 1526e5918d7dSYoshinori Sato tcg_gen_rotri_i32(cpu_regs[rd], cpu_regs[rd], src); 1527e5918d7dSYoshinori Sato } else { 1528e5918d7dSYoshinori Sato tcg_gen_rotr_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1529e5918d7dSYoshinori Sato } 1530e5918d7dSYoshinori Sato tcg_gen_shri_i32(cpu_psw_c, cpu_regs[rd], 31); 1531e5918d7dSYoshinori Sato break; 1532e5918d7dSYoshinori Sato } 1533e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1534e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1535e5918d7dSYoshinori Sato } 1536e5918d7dSYoshinori Sato 1537e5918d7dSYoshinori Sato /* rotl #imm, rd */ 1538e5918d7dSYoshinori Sato static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a) 1539e5918d7dSYoshinori Sato { 1540e5918d7dSYoshinori Sato rx_rot(ROT_IMM, ROTL, a->rd, a->imm); 1541e5918d7dSYoshinori Sato return true; 1542e5918d7dSYoshinori Sato } 1543e5918d7dSYoshinori Sato 1544e5918d7dSYoshinori Sato /* rotl rs, rd */ 1545e5918d7dSYoshinori Sato static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a) 1546e5918d7dSYoshinori Sato { 1547e5918d7dSYoshinori Sato rx_rot(ROT_REG, ROTL, a->rd, a->rs); 1548e5918d7dSYoshinori Sato return true; 1549e5918d7dSYoshinori Sato } 1550e5918d7dSYoshinori Sato 1551e5918d7dSYoshinori Sato /* rotr #imm, rd */ 1552e5918d7dSYoshinori Sato static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a) 1553e5918d7dSYoshinori Sato { 1554e5918d7dSYoshinori Sato rx_rot(ROT_IMM, ROTR, a->rd, a->imm); 1555e5918d7dSYoshinori Sato return true; 1556e5918d7dSYoshinori Sato } 1557e5918d7dSYoshinori Sato 1558e5918d7dSYoshinori Sato /* rotr rs, rd */ 1559e5918d7dSYoshinori Sato static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a) 1560e5918d7dSYoshinori Sato { 1561e5918d7dSYoshinori Sato rx_rot(ROT_REG, ROTR, a->rd, a->rs); 1562e5918d7dSYoshinori Sato return true; 1563e5918d7dSYoshinori Sato } 1564e5918d7dSYoshinori Sato 1565e5918d7dSYoshinori Sato /* revl rs, rd */ 1566e5918d7dSYoshinori Sato static bool trans_REVL(DisasContext *ctx, arg_REVL *a) 1567e5918d7dSYoshinori Sato { 1568e5918d7dSYoshinori Sato tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]); 1569e5918d7dSYoshinori Sato return true; 1570e5918d7dSYoshinori Sato } 1571e5918d7dSYoshinori Sato 1572e5918d7dSYoshinori Sato /* revw rs, rd */ 1573e5918d7dSYoshinori Sato static bool trans_REVW(DisasContext *ctx, arg_REVW *a) 1574e5918d7dSYoshinori Sato { 1575e5918d7dSYoshinori Sato TCGv tmp; 1576e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1577e5918d7dSYoshinori Sato tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); 1578e5918d7dSYoshinori Sato tcg_gen_shli_i32(tmp, tmp, 8); 1579e5918d7dSYoshinori Sato tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); 1580e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); 1581e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1582e5918d7dSYoshinori Sato tcg_temp_free(tmp); 1583e5918d7dSYoshinori Sato return true; 1584e5918d7dSYoshinori Sato } 1585e5918d7dSYoshinori Sato 1586e5918d7dSYoshinori Sato /* conditional branch helper */ 1587e5918d7dSYoshinori Sato static void rx_bcnd_main(DisasContext *ctx, int cd, int dst) 1588e5918d7dSYoshinori Sato { 1589e5918d7dSYoshinori Sato DisasCompare dc; 1590e5918d7dSYoshinori Sato TCGLabel *t, *done; 1591e5918d7dSYoshinori Sato 1592e5918d7dSYoshinori Sato switch (cd) { 1593e5918d7dSYoshinori Sato case 0 ... 13: 1594e5918d7dSYoshinori Sato dc.temp = tcg_temp_new(); 1595e5918d7dSYoshinori Sato psw_cond(&dc, cd); 1596e5918d7dSYoshinori Sato t = gen_new_label(); 1597e5918d7dSYoshinori Sato done = gen_new_label(); 1598e5918d7dSYoshinori Sato tcg_gen_brcondi_i32(dc.cond, dc.value, 0, t); 1599e5918d7dSYoshinori Sato gen_goto_tb(ctx, 0, ctx->base.pc_next); 1600e5918d7dSYoshinori Sato tcg_gen_br(done); 1601e5918d7dSYoshinori Sato gen_set_label(t); 1602e5918d7dSYoshinori Sato gen_goto_tb(ctx, 1, ctx->pc + dst); 1603e5918d7dSYoshinori Sato gen_set_label(done); 1604e5918d7dSYoshinori Sato tcg_temp_free(dc.temp); 1605e5918d7dSYoshinori Sato break; 1606e5918d7dSYoshinori Sato case 14: 1607e5918d7dSYoshinori Sato /* always true case */ 1608e5918d7dSYoshinori Sato gen_goto_tb(ctx, 0, ctx->pc + dst); 1609e5918d7dSYoshinori Sato break; 1610e5918d7dSYoshinori Sato case 15: 1611e5918d7dSYoshinori Sato /* always false case */ 1612e5918d7dSYoshinori Sato /* Nothing do */ 1613e5918d7dSYoshinori Sato break; 1614e5918d7dSYoshinori Sato } 1615e5918d7dSYoshinori Sato } 1616e5918d7dSYoshinori Sato 1617e5918d7dSYoshinori Sato /* beq dsp:3 / bne dsp:3 */ 1618e5918d7dSYoshinori Sato /* beq dsp:8 / bne dsp:8 */ 1619e5918d7dSYoshinori Sato /* bc dsp:8 / bnc dsp:8 */ 1620e5918d7dSYoshinori Sato /* bgtu dsp:8 / bleu dsp:8 */ 1621e5918d7dSYoshinori Sato /* bpz dsp:8 / bn dsp:8 */ 1622e5918d7dSYoshinori Sato /* bge dsp:8 / blt dsp:8 */ 1623e5918d7dSYoshinori Sato /* bgt dsp:8 / ble dsp:8 */ 1624e5918d7dSYoshinori Sato /* bo dsp:8 / bno dsp:8 */ 1625e5918d7dSYoshinori Sato /* beq dsp:16 / bne dsp:16 */ 1626e5918d7dSYoshinori Sato static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a) 1627e5918d7dSYoshinori Sato { 1628e5918d7dSYoshinori Sato rx_bcnd_main(ctx, a->cd, a->dsp); 1629e5918d7dSYoshinori Sato return true; 1630e5918d7dSYoshinori Sato } 1631e5918d7dSYoshinori Sato 1632e5918d7dSYoshinori Sato /* bra dsp:3 */ 1633e5918d7dSYoshinori Sato /* bra dsp:8 */ 1634e5918d7dSYoshinori Sato /* bra dsp:16 */ 1635e5918d7dSYoshinori Sato /* bra dsp:24 */ 1636e5918d7dSYoshinori Sato static bool trans_BRA(DisasContext *ctx, arg_BRA *a) 1637e5918d7dSYoshinori Sato { 1638e5918d7dSYoshinori Sato rx_bcnd_main(ctx, 14, a->dsp); 1639e5918d7dSYoshinori Sato return true; 1640e5918d7dSYoshinori Sato } 1641e5918d7dSYoshinori Sato 1642e5918d7dSYoshinori Sato /* bra rs */ 1643e5918d7dSYoshinori Sato static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a) 1644e5918d7dSYoshinori Sato { 1645e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1646e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1647e5918d7dSYoshinori Sato return true; 1648e5918d7dSYoshinori Sato } 1649e5918d7dSYoshinori Sato 1650e5918d7dSYoshinori Sato static inline void rx_save_pc(DisasContext *ctx) 1651e5918d7dSYoshinori Sato { 1652e5918d7dSYoshinori Sato TCGv pc = tcg_const_i32(ctx->base.pc_next); 1653e5918d7dSYoshinori Sato push(pc); 1654e5918d7dSYoshinori Sato tcg_temp_free(pc); 1655e5918d7dSYoshinori Sato } 1656e5918d7dSYoshinori Sato 1657e5918d7dSYoshinori Sato /* jmp rs */ 1658e5918d7dSYoshinori Sato static bool trans_JMP(DisasContext *ctx, arg_JMP *a) 1659e5918d7dSYoshinori Sato { 1660e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1661e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1662e5918d7dSYoshinori Sato return true; 1663e5918d7dSYoshinori Sato } 1664e5918d7dSYoshinori Sato 1665e5918d7dSYoshinori Sato /* jsr rs */ 1666e5918d7dSYoshinori Sato static bool trans_JSR(DisasContext *ctx, arg_JSR *a) 1667e5918d7dSYoshinori Sato { 1668e5918d7dSYoshinori Sato rx_save_pc(ctx); 1669e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1670e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1671e5918d7dSYoshinori Sato return true; 1672e5918d7dSYoshinori Sato } 1673e5918d7dSYoshinori Sato 1674e5918d7dSYoshinori Sato /* bsr dsp:16 */ 1675e5918d7dSYoshinori Sato /* bsr dsp:24 */ 1676e5918d7dSYoshinori Sato static bool trans_BSR(DisasContext *ctx, arg_BSR *a) 1677e5918d7dSYoshinori Sato { 1678e5918d7dSYoshinori Sato rx_save_pc(ctx); 1679e5918d7dSYoshinori Sato rx_bcnd_main(ctx, 14, a->dsp); 1680e5918d7dSYoshinori Sato return true; 1681e5918d7dSYoshinori Sato } 1682e5918d7dSYoshinori Sato 1683e5918d7dSYoshinori Sato /* bsr rs */ 1684e5918d7dSYoshinori Sato static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a) 1685e5918d7dSYoshinori Sato { 1686e5918d7dSYoshinori Sato rx_save_pc(ctx); 1687e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1688e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1689e5918d7dSYoshinori Sato return true; 1690e5918d7dSYoshinori Sato } 1691e5918d7dSYoshinori Sato 1692e5918d7dSYoshinori Sato /* rts */ 1693e5918d7dSYoshinori Sato static bool trans_RTS(DisasContext *ctx, arg_RTS *a) 1694e5918d7dSYoshinori Sato { 1695e5918d7dSYoshinori Sato pop(cpu_pc); 1696e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1697e5918d7dSYoshinori Sato return true; 1698e5918d7dSYoshinori Sato } 1699e5918d7dSYoshinori Sato 1700e5918d7dSYoshinori Sato /* nop */ 1701e5918d7dSYoshinori Sato static bool trans_NOP(DisasContext *ctx, arg_NOP *a) 1702e5918d7dSYoshinori Sato { 1703e5918d7dSYoshinori Sato return true; 1704e5918d7dSYoshinori Sato } 1705e5918d7dSYoshinori Sato 1706e5918d7dSYoshinori Sato /* scmpu */ 1707e5918d7dSYoshinori Sato static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) 1708e5918d7dSYoshinori Sato { 1709e5918d7dSYoshinori Sato gen_helper_scmpu(cpu_env); 1710e5918d7dSYoshinori Sato return true; 1711e5918d7dSYoshinori Sato } 1712e5918d7dSYoshinori Sato 1713e5918d7dSYoshinori Sato /* smovu */ 1714e5918d7dSYoshinori Sato static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) 1715e5918d7dSYoshinori Sato { 1716e5918d7dSYoshinori Sato gen_helper_smovu(cpu_env); 1717e5918d7dSYoshinori Sato return true; 1718e5918d7dSYoshinori Sato } 1719e5918d7dSYoshinori Sato 1720e5918d7dSYoshinori Sato /* smovf */ 1721e5918d7dSYoshinori Sato static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) 1722e5918d7dSYoshinori Sato { 1723e5918d7dSYoshinori Sato gen_helper_smovf(cpu_env); 1724e5918d7dSYoshinori Sato return true; 1725e5918d7dSYoshinori Sato } 1726e5918d7dSYoshinori Sato 1727e5918d7dSYoshinori Sato /* smovb */ 1728e5918d7dSYoshinori Sato static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) 1729e5918d7dSYoshinori Sato { 1730e5918d7dSYoshinori Sato gen_helper_smovb(cpu_env); 1731e5918d7dSYoshinori Sato return true; 1732e5918d7dSYoshinori Sato } 1733e5918d7dSYoshinori Sato 1734e5918d7dSYoshinori Sato #define STRING(op) \ 1735e5918d7dSYoshinori Sato do { \ 1736e5918d7dSYoshinori Sato TCGv size = tcg_const_i32(a->sz); \ 1737e5918d7dSYoshinori Sato gen_helper_##op(cpu_env, size); \ 1738e5918d7dSYoshinori Sato tcg_temp_free(size); \ 1739e5918d7dSYoshinori Sato } while (0) 1740e5918d7dSYoshinori Sato 1741e5918d7dSYoshinori Sato /* suntile.<bwl> */ 1742e5918d7dSYoshinori Sato static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a) 1743e5918d7dSYoshinori Sato { 1744e5918d7dSYoshinori Sato STRING(suntil); 1745e5918d7dSYoshinori Sato return true; 1746e5918d7dSYoshinori Sato } 1747e5918d7dSYoshinori Sato 1748e5918d7dSYoshinori Sato /* swhile.<bwl> */ 1749e5918d7dSYoshinori Sato static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a) 1750e5918d7dSYoshinori Sato { 1751e5918d7dSYoshinori Sato STRING(swhile); 1752e5918d7dSYoshinori Sato return true; 1753e5918d7dSYoshinori Sato } 1754e5918d7dSYoshinori Sato /* sstr.<bwl> */ 1755e5918d7dSYoshinori Sato static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a) 1756e5918d7dSYoshinori Sato { 1757e5918d7dSYoshinori Sato STRING(sstr); 1758e5918d7dSYoshinori Sato return true; 1759e5918d7dSYoshinori Sato } 1760e5918d7dSYoshinori Sato 1761e5918d7dSYoshinori Sato /* rmpa.<bwl> */ 1762e5918d7dSYoshinori Sato static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a) 1763e5918d7dSYoshinori Sato { 1764e5918d7dSYoshinori Sato STRING(rmpa); 1765e5918d7dSYoshinori Sato return true; 1766e5918d7dSYoshinori Sato } 1767e5918d7dSYoshinori Sato 1768e5918d7dSYoshinori Sato static void rx_mul64hi(TCGv_i64 ret, int rs, int rs2) 1769e5918d7dSYoshinori Sato { 1770e5918d7dSYoshinori Sato TCGv_i64 tmp0, tmp1; 1771e5918d7dSYoshinori Sato tmp0 = tcg_temp_new_i64(); 1772e5918d7dSYoshinori Sato tmp1 = tcg_temp_new_i64(); 1773e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1774e5918d7dSYoshinori Sato tcg_gen_sari_i64(tmp0, tmp0, 16); 1775e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1776e5918d7dSYoshinori Sato tcg_gen_sari_i64(tmp1, tmp1, 16); 1777e5918d7dSYoshinori Sato tcg_gen_mul_i64(ret, tmp0, tmp1); 1778e5918d7dSYoshinori Sato tcg_gen_shli_i64(ret, ret, 16); 1779e5918d7dSYoshinori Sato tcg_temp_free_i64(tmp0); 1780e5918d7dSYoshinori Sato tcg_temp_free_i64(tmp1); 1781e5918d7dSYoshinori Sato } 1782e5918d7dSYoshinori Sato 1783e5918d7dSYoshinori Sato static void rx_mul64lo(TCGv_i64 ret, int rs, int rs2) 1784e5918d7dSYoshinori Sato { 1785e5918d7dSYoshinori Sato TCGv_i64 tmp0, tmp1; 1786e5918d7dSYoshinori Sato tmp0 = tcg_temp_new_i64(); 1787e5918d7dSYoshinori Sato tmp1 = tcg_temp_new_i64(); 1788e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1789e5918d7dSYoshinori Sato tcg_gen_ext16s_i64(tmp0, tmp0); 1790e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1791e5918d7dSYoshinori Sato tcg_gen_ext16s_i64(tmp1, tmp1); 1792e5918d7dSYoshinori Sato tcg_gen_mul_i64(ret, tmp0, tmp1); 1793e5918d7dSYoshinori Sato tcg_gen_shli_i64(ret, ret, 16); 1794e5918d7dSYoshinori Sato tcg_temp_free_i64(tmp0); 1795e5918d7dSYoshinori Sato tcg_temp_free_i64(tmp1); 1796e5918d7dSYoshinori Sato } 1797e5918d7dSYoshinori Sato 1798e5918d7dSYoshinori Sato /* mulhi rs,rs2 */ 1799e5918d7dSYoshinori Sato static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a) 1800e5918d7dSYoshinori Sato { 1801e5918d7dSYoshinori Sato rx_mul64hi(cpu_acc, a->rs, a->rs2); 1802e5918d7dSYoshinori Sato return true; 1803e5918d7dSYoshinori Sato } 1804e5918d7dSYoshinori Sato 1805e5918d7dSYoshinori Sato /* mullo rs,rs2 */ 1806e5918d7dSYoshinori Sato static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a) 1807e5918d7dSYoshinori Sato { 1808e5918d7dSYoshinori Sato rx_mul64lo(cpu_acc, a->rs, a->rs2); 1809e5918d7dSYoshinori Sato return true; 1810e5918d7dSYoshinori Sato } 1811e5918d7dSYoshinori Sato 1812e5918d7dSYoshinori Sato /* machi rs,rs2 */ 1813e5918d7dSYoshinori Sato static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a) 1814e5918d7dSYoshinori Sato { 1815e5918d7dSYoshinori Sato TCGv_i64 tmp; 1816e5918d7dSYoshinori Sato tmp = tcg_temp_new_i64(); 1817e5918d7dSYoshinori Sato rx_mul64hi(tmp, a->rs, a->rs2); 1818e5918d7dSYoshinori Sato tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1819e5918d7dSYoshinori Sato tcg_temp_free_i64(tmp); 1820e5918d7dSYoshinori Sato return true; 1821e5918d7dSYoshinori Sato } 1822e5918d7dSYoshinori Sato 1823e5918d7dSYoshinori Sato /* maclo rs,rs2 */ 1824e5918d7dSYoshinori Sato static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a) 1825e5918d7dSYoshinori Sato { 1826e5918d7dSYoshinori Sato TCGv_i64 tmp; 1827e5918d7dSYoshinori Sato tmp = tcg_temp_new_i64(); 1828e5918d7dSYoshinori Sato rx_mul64lo(tmp, a->rs, a->rs2); 1829e5918d7dSYoshinori Sato tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1830e5918d7dSYoshinori Sato tcg_temp_free_i64(tmp); 1831e5918d7dSYoshinori Sato return true; 1832e5918d7dSYoshinori Sato } 1833e5918d7dSYoshinori Sato 1834e5918d7dSYoshinori Sato /* mvfachi rd */ 1835e5918d7dSYoshinori Sato static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a) 1836e5918d7dSYoshinori Sato { 1837e5918d7dSYoshinori Sato tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc); 1838e5918d7dSYoshinori Sato return true; 1839e5918d7dSYoshinori Sato } 1840e5918d7dSYoshinori Sato 1841e5918d7dSYoshinori Sato /* mvfacmi rd */ 1842e5918d7dSYoshinori Sato static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a) 1843e5918d7dSYoshinori Sato { 1844e5918d7dSYoshinori Sato TCGv_i64 rd64; 1845e5918d7dSYoshinori Sato rd64 = tcg_temp_new_i64(); 1846e5918d7dSYoshinori Sato tcg_gen_extract_i64(rd64, cpu_acc, 16, 32); 1847e5918d7dSYoshinori Sato tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64); 1848e5918d7dSYoshinori Sato tcg_temp_free_i64(rd64); 1849e5918d7dSYoshinori Sato return true; 1850e5918d7dSYoshinori Sato } 1851e5918d7dSYoshinori Sato 1852e5918d7dSYoshinori Sato /* mvtachi rs */ 1853e5918d7dSYoshinori Sato static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a) 1854e5918d7dSYoshinori Sato { 1855e5918d7dSYoshinori Sato TCGv_i64 rs64; 1856e5918d7dSYoshinori Sato rs64 = tcg_temp_new_i64(); 1857e5918d7dSYoshinori Sato tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1858e5918d7dSYoshinori Sato tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 32, 32); 1859e5918d7dSYoshinori Sato tcg_temp_free_i64(rs64); 1860e5918d7dSYoshinori Sato return true; 1861e5918d7dSYoshinori Sato } 1862e5918d7dSYoshinori Sato 1863e5918d7dSYoshinori Sato /* mvtaclo rs */ 1864e5918d7dSYoshinori Sato static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a) 1865e5918d7dSYoshinori Sato { 1866e5918d7dSYoshinori Sato TCGv_i64 rs64; 1867e5918d7dSYoshinori Sato rs64 = tcg_temp_new_i64(); 1868e5918d7dSYoshinori Sato tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1869e5918d7dSYoshinori Sato tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 0, 32); 1870e5918d7dSYoshinori Sato tcg_temp_free_i64(rs64); 1871e5918d7dSYoshinori Sato return true; 1872e5918d7dSYoshinori Sato } 1873e5918d7dSYoshinori Sato 1874e5918d7dSYoshinori Sato /* racw #imm */ 1875e5918d7dSYoshinori Sato static bool trans_RACW(DisasContext *ctx, arg_RACW *a) 1876e5918d7dSYoshinori Sato { 1877e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(a->imm + 1); 1878e5918d7dSYoshinori Sato gen_helper_racw(cpu_env, imm); 1879e5918d7dSYoshinori Sato tcg_temp_free(imm); 1880e5918d7dSYoshinori Sato return true; 1881e5918d7dSYoshinori Sato } 1882e5918d7dSYoshinori Sato 1883e5918d7dSYoshinori Sato /* sat rd */ 1884e5918d7dSYoshinori Sato static bool trans_SAT(DisasContext *ctx, arg_SAT *a) 1885e5918d7dSYoshinori Sato { 1886e5918d7dSYoshinori Sato TCGv tmp, z; 1887e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1888e5918d7dSYoshinori Sato z = tcg_const_i32(0); 1889e5918d7dSYoshinori Sato /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */ 1890e5918d7dSYoshinori Sato tcg_gen_sari_i32(tmp, cpu_psw_s, 31); 1891e5918d7dSYoshinori Sato /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */ 1892e5918d7dSYoshinori Sato tcg_gen_xori_i32(tmp, tmp, 0x80000000); 1893e5918d7dSYoshinori Sato tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], 1894e5918d7dSYoshinori Sato cpu_psw_o, z, tmp, cpu_regs[a->rd]); 1895e5918d7dSYoshinori Sato tcg_temp_free(tmp); 1896e5918d7dSYoshinori Sato tcg_temp_free(z); 1897e5918d7dSYoshinori Sato return true; 1898e5918d7dSYoshinori Sato } 1899e5918d7dSYoshinori Sato 1900e5918d7dSYoshinori Sato /* satr */ 1901e5918d7dSYoshinori Sato static bool trans_SATR(DisasContext *ctx, arg_SATR *a) 1902e5918d7dSYoshinori Sato { 1903e5918d7dSYoshinori Sato gen_helper_satr(cpu_env); 1904e5918d7dSYoshinori Sato return true; 1905e5918d7dSYoshinori Sato } 1906e5918d7dSYoshinori Sato 1907e5918d7dSYoshinori Sato #define cat3(a, b, c) a##b##c 1908e5918d7dSYoshinori Sato #define FOP(name, op) \ 1909e5918d7dSYoshinori Sato static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 1910e5918d7dSYoshinori Sato cat3(arg_, name, _ir) * a) \ 1911e5918d7dSYoshinori Sato { \ 1912e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(li(ctx, 0)); \ 1913e5918d7dSYoshinori Sato gen_helper_##op(cpu_regs[a->rd], cpu_env, \ 1914e5918d7dSYoshinori Sato cpu_regs[a->rd], imm); \ 1915e5918d7dSYoshinori Sato tcg_temp_free(imm); \ 1916e5918d7dSYoshinori Sato return true; \ 1917e5918d7dSYoshinori Sato } \ 1918e5918d7dSYoshinori Sato static bool cat3(trans_, name, _mr)(DisasContext *ctx, \ 1919e5918d7dSYoshinori Sato cat3(arg_, name, _mr) * a) \ 1920e5918d7dSYoshinori Sato { \ 1921e5918d7dSYoshinori Sato TCGv val, mem; \ 1922e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 1923e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1924e5918d7dSYoshinori Sato gen_helper_##op(cpu_regs[a->rd], cpu_env, \ 1925e5918d7dSYoshinori Sato cpu_regs[a->rd], val); \ 1926e5918d7dSYoshinori Sato tcg_temp_free(mem); \ 1927e5918d7dSYoshinori Sato return true; \ 1928e5918d7dSYoshinori Sato } 1929e5918d7dSYoshinori Sato 1930e5918d7dSYoshinori Sato #define FCONVOP(name, op) \ 1931e5918d7dSYoshinori Sato static bool trans_##name(DisasContext *ctx, arg_##name * a) \ 1932e5918d7dSYoshinori Sato { \ 1933e5918d7dSYoshinori Sato TCGv val, mem; \ 1934e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 1935e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1936e5918d7dSYoshinori Sato gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \ 1937e5918d7dSYoshinori Sato tcg_temp_free(mem); \ 1938e5918d7dSYoshinori Sato return true; \ 1939e5918d7dSYoshinori Sato } 1940e5918d7dSYoshinori Sato 1941e5918d7dSYoshinori Sato FOP(FADD, fadd) 1942e5918d7dSYoshinori Sato FOP(FSUB, fsub) 1943e5918d7dSYoshinori Sato FOP(FMUL, fmul) 1944e5918d7dSYoshinori Sato FOP(FDIV, fdiv) 1945e5918d7dSYoshinori Sato 1946e5918d7dSYoshinori Sato /* fcmp #imm, rd */ 1947e5918d7dSYoshinori Sato static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) 1948e5918d7dSYoshinori Sato { 1949e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(li(ctx, 0)); 1950e5918d7dSYoshinori Sato gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm); 1951e5918d7dSYoshinori Sato tcg_temp_free(imm); 1952e5918d7dSYoshinori Sato return true; 1953e5918d7dSYoshinori Sato } 1954e5918d7dSYoshinori Sato 1955e5918d7dSYoshinori Sato /* fcmp dsp[rs], rd */ 1956e5918d7dSYoshinori Sato /* fcmp rs, rd */ 1957e5918d7dSYoshinori Sato static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) 1958e5918d7dSYoshinori Sato { 1959e5918d7dSYoshinori Sato TCGv val, mem; 1960e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1961e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); 1962e5918d7dSYoshinori Sato gen_helper_fcmp(cpu_env, cpu_regs[a->rd], val); 1963e5918d7dSYoshinori Sato tcg_temp_free(mem); 1964e5918d7dSYoshinori Sato return true; 1965e5918d7dSYoshinori Sato } 1966e5918d7dSYoshinori Sato 1967e5918d7dSYoshinori Sato FCONVOP(FTOI, ftoi) 1968e5918d7dSYoshinori Sato FCONVOP(ROUND, round) 1969e5918d7dSYoshinori Sato 1970e5918d7dSYoshinori Sato /* itof rs, rd */ 1971e5918d7dSYoshinori Sato /* itof dsp[rs], rd */ 1972e5918d7dSYoshinori Sato static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a) 1973e5918d7dSYoshinori Sato { 1974e5918d7dSYoshinori Sato TCGv val, mem; 1975e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1976e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1977e5918d7dSYoshinori Sato gen_helper_itof(cpu_regs[a->rd], cpu_env, val); 1978e5918d7dSYoshinori Sato tcg_temp_free(mem); 1979e5918d7dSYoshinori Sato return true; 1980e5918d7dSYoshinori Sato } 1981e5918d7dSYoshinori Sato 1982e5918d7dSYoshinori Sato static void rx_bsetm(TCGv mem, TCGv mask) 1983e5918d7dSYoshinori Sato { 1984e5918d7dSYoshinori Sato TCGv val; 1985e5918d7dSYoshinori Sato val = tcg_temp_new(); 1986e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 1987e5918d7dSYoshinori Sato tcg_gen_or_i32(val, val, mask); 1988e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, mem); 1989e5918d7dSYoshinori Sato tcg_temp_free(val); 1990e5918d7dSYoshinori Sato } 1991e5918d7dSYoshinori Sato 1992e5918d7dSYoshinori Sato static void rx_bclrm(TCGv mem, TCGv mask) 1993e5918d7dSYoshinori Sato { 1994e5918d7dSYoshinori Sato TCGv val; 1995e5918d7dSYoshinori Sato val = tcg_temp_new(); 1996e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 1997e5918d7dSYoshinori Sato tcg_gen_andc_i32(val, val, mask); 1998e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, mem); 1999e5918d7dSYoshinori Sato tcg_temp_free(val); 2000e5918d7dSYoshinori Sato } 2001e5918d7dSYoshinori Sato 2002e5918d7dSYoshinori Sato static void rx_btstm(TCGv mem, TCGv mask) 2003e5918d7dSYoshinori Sato { 2004e5918d7dSYoshinori Sato TCGv val; 2005e5918d7dSYoshinori Sato val = tcg_temp_new(); 2006e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 2007e5918d7dSYoshinori Sato tcg_gen_and_i32(val, val, mask); 2008e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0); 2009e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 2010e5918d7dSYoshinori Sato tcg_temp_free(val); 2011e5918d7dSYoshinori Sato } 2012e5918d7dSYoshinori Sato 2013e5918d7dSYoshinori Sato static void rx_bnotm(TCGv mem, TCGv mask) 2014e5918d7dSYoshinori Sato { 2015e5918d7dSYoshinori Sato TCGv val; 2016e5918d7dSYoshinori Sato val = tcg_temp_new(); 2017e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 2018e5918d7dSYoshinori Sato tcg_gen_xor_i32(val, val, mask); 2019e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, mem); 2020e5918d7dSYoshinori Sato tcg_temp_free(val); 2021e5918d7dSYoshinori Sato } 2022e5918d7dSYoshinori Sato 2023e5918d7dSYoshinori Sato static void rx_bsetr(TCGv reg, TCGv mask) 2024e5918d7dSYoshinori Sato { 2025e5918d7dSYoshinori Sato tcg_gen_or_i32(reg, reg, mask); 2026e5918d7dSYoshinori Sato } 2027e5918d7dSYoshinori Sato 2028e5918d7dSYoshinori Sato static void rx_bclrr(TCGv reg, TCGv mask) 2029e5918d7dSYoshinori Sato { 2030e5918d7dSYoshinori Sato tcg_gen_andc_i32(reg, reg, mask); 2031e5918d7dSYoshinori Sato } 2032e5918d7dSYoshinori Sato 2033e5918d7dSYoshinori Sato static inline void rx_btstr(TCGv reg, TCGv mask) 2034e5918d7dSYoshinori Sato { 2035e5918d7dSYoshinori Sato TCGv t0; 2036e5918d7dSYoshinori Sato t0 = tcg_temp_new(); 2037e5918d7dSYoshinori Sato tcg_gen_and_i32(t0, reg, mask); 2038e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0); 2039e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 2040e5918d7dSYoshinori Sato tcg_temp_free(t0); 2041e5918d7dSYoshinori Sato } 2042e5918d7dSYoshinori Sato 2043e5918d7dSYoshinori Sato static inline void rx_bnotr(TCGv reg, TCGv mask) 2044e5918d7dSYoshinori Sato { 2045e5918d7dSYoshinori Sato tcg_gen_xor_i32(reg, reg, mask); 2046e5918d7dSYoshinori Sato } 2047e5918d7dSYoshinori Sato 2048e5918d7dSYoshinori Sato #define BITOP(name, op) \ 2049e5918d7dSYoshinori Sato static bool cat3(trans_, name, _im)(DisasContext *ctx, \ 2050e5918d7dSYoshinori Sato cat3(arg_, name, _im) * a) \ 2051e5918d7dSYoshinori Sato { \ 2052e5918d7dSYoshinori Sato TCGv mask, mem, addr; \ 2053e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 2054e5918d7dSYoshinori Sato mask = tcg_const_i32(1 << a->imm); \ 2055e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 2056e5918d7dSYoshinori Sato cat3(rx_, op, m)(addr, mask); \ 2057e5918d7dSYoshinori Sato tcg_temp_free(mask); \ 2058e5918d7dSYoshinori Sato tcg_temp_free(mem); \ 2059e5918d7dSYoshinori Sato return true; \ 2060e5918d7dSYoshinori Sato } \ 2061e5918d7dSYoshinori Sato static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 2062e5918d7dSYoshinori Sato cat3(arg_, name, _ir) * a) \ 2063e5918d7dSYoshinori Sato { \ 2064e5918d7dSYoshinori Sato TCGv mask; \ 2065e5918d7dSYoshinori Sato mask = tcg_const_i32(1 << a->imm); \ 2066e5918d7dSYoshinori Sato cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 2067e5918d7dSYoshinori Sato tcg_temp_free(mask); \ 2068e5918d7dSYoshinori Sato return true; \ 2069e5918d7dSYoshinori Sato } \ 2070e5918d7dSYoshinori Sato static bool cat3(trans_, name, _rr)(DisasContext *ctx, \ 2071e5918d7dSYoshinori Sato cat3(arg_, name, _rr) * a) \ 2072e5918d7dSYoshinori Sato { \ 2073e5918d7dSYoshinori Sato TCGv mask, b; \ 2074e5918d7dSYoshinori Sato mask = tcg_const_i32(1); \ 2075e5918d7dSYoshinori Sato b = tcg_temp_new(); \ 2076e5918d7dSYoshinori Sato tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ 2077e5918d7dSYoshinori Sato tcg_gen_shl_i32(mask, mask, b); \ 2078e5918d7dSYoshinori Sato cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 2079e5918d7dSYoshinori Sato tcg_temp_free(mask); \ 2080e5918d7dSYoshinori Sato tcg_temp_free(b); \ 2081e5918d7dSYoshinori Sato return true; \ 2082e5918d7dSYoshinori Sato } \ 2083e5918d7dSYoshinori Sato static bool cat3(trans_, name, _rm)(DisasContext *ctx, \ 2084e5918d7dSYoshinori Sato cat3(arg_, name, _rm) * a) \ 2085e5918d7dSYoshinori Sato { \ 2086e5918d7dSYoshinori Sato TCGv mask, mem, addr, b; \ 2087e5918d7dSYoshinori Sato mask = tcg_const_i32(1); \ 2088e5918d7dSYoshinori Sato b = tcg_temp_new(); \ 2089e5918d7dSYoshinori Sato tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \ 2090e5918d7dSYoshinori Sato tcg_gen_shl_i32(mask, mask, b); \ 2091e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 2092e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 2093e5918d7dSYoshinori Sato cat3(rx_, op, m)(addr, mask); \ 2094e5918d7dSYoshinori Sato tcg_temp_free(mem); \ 2095e5918d7dSYoshinori Sato tcg_temp_free(mask); \ 2096e5918d7dSYoshinori Sato tcg_temp_free(b); \ 2097e5918d7dSYoshinori Sato return true; \ 2098e5918d7dSYoshinori Sato } 2099e5918d7dSYoshinori Sato 2100e5918d7dSYoshinori Sato BITOP(BSET, bset) 2101e5918d7dSYoshinori Sato BITOP(BCLR, bclr) 2102e5918d7dSYoshinori Sato BITOP(BTST, btst) 2103e5918d7dSYoshinori Sato BITOP(BNOT, bnot) 2104e5918d7dSYoshinori Sato 2105e5918d7dSYoshinori Sato static inline void bmcnd_op(TCGv val, TCGCond cond, int pos) 2106e5918d7dSYoshinori Sato { 2107e5918d7dSYoshinori Sato TCGv bit; 2108e5918d7dSYoshinori Sato DisasCompare dc; 2109e5918d7dSYoshinori Sato dc.temp = tcg_temp_new(); 2110e5918d7dSYoshinori Sato bit = tcg_temp_new(); 2111e5918d7dSYoshinori Sato psw_cond(&dc, cond); 2112e5918d7dSYoshinori Sato tcg_gen_andi_i32(val, val, ~(1 << pos)); 2113e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0); 2114e5918d7dSYoshinori Sato tcg_gen_deposit_i32(val, val, bit, pos, 1); 2115e5918d7dSYoshinori Sato tcg_temp_free(bit); 2116e5918d7dSYoshinori Sato tcg_temp_free(dc.temp); 2117e5918d7dSYoshinori Sato } 2118e5918d7dSYoshinori Sato 2119e5918d7dSYoshinori Sato /* bmcnd #imm, dsp[rd] */ 2120e5918d7dSYoshinori Sato static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) 2121e5918d7dSYoshinori Sato { 2122e5918d7dSYoshinori Sato TCGv val, mem, addr; 2123e5918d7dSYoshinori Sato val = tcg_temp_new(); 2124e5918d7dSYoshinori Sato mem = tcg_temp_new(); 2125e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); 2126e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, addr); 2127e5918d7dSYoshinori Sato bmcnd_op(val, a->cd, a->imm); 2128e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, addr); 2129e5918d7dSYoshinori Sato tcg_temp_free(val); 2130e5918d7dSYoshinori Sato tcg_temp_free(mem); 2131e5918d7dSYoshinori Sato return true; 2132e5918d7dSYoshinori Sato } 2133e5918d7dSYoshinori Sato 2134e5918d7dSYoshinori Sato /* bmcond #imm, rd */ 2135e5918d7dSYoshinori Sato static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a) 2136e5918d7dSYoshinori Sato { 2137e5918d7dSYoshinori Sato bmcnd_op(cpu_regs[a->rd], a->cd, a->imm); 2138e5918d7dSYoshinori Sato return true; 2139e5918d7dSYoshinori Sato } 2140e5918d7dSYoshinori Sato 2141e5918d7dSYoshinori Sato enum { 2142e5918d7dSYoshinori Sato PSW_C = 0, 2143e5918d7dSYoshinori Sato PSW_Z = 1, 2144e5918d7dSYoshinori Sato PSW_S = 2, 2145e5918d7dSYoshinori Sato PSW_O = 3, 2146e5918d7dSYoshinori Sato PSW_I = 8, 2147e5918d7dSYoshinori Sato PSW_U = 9, 2148e5918d7dSYoshinori Sato }; 2149e5918d7dSYoshinori Sato 2150e5918d7dSYoshinori Sato static inline void clrsetpsw(DisasContext *ctx, int cb, int val) 2151e5918d7dSYoshinori Sato { 2152e5918d7dSYoshinori Sato if (cb < 8) { 2153e5918d7dSYoshinori Sato switch (cb) { 2154e5918d7dSYoshinori Sato case PSW_C: 2155e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, val); 2156e5918d7dSYoshinori Sato break; 2157e5918d7dSYoshinori Sato case PSW_Z: 2158e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_z, val == 0); 2159e5918d7dSYoshinori Sato break; 2160e5918d7dSYoshinori Sato case PSW_S: 2161e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_s, val ? -1 : 0); 2162e5918d7dSYoshinori Sato break; 2163e5918d7dSYoshinori Sato case PSW_O: 2164e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, val << 31); 2165e5918d7dSYoshinori Sato break; 2166e5918d7dSYoshinori Sato default: 2167e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); 2168e5918d7dSYoshinori Sato break; 2169e5918d7dSYoshinori Sato } 2170e5918d7dSYoshinori Sato } else if (is_privileged(ctx, 0)) { 2171e5918d7dSYoshinori Sato switch (cb) { 2172e5918d7dSYoshinori Sato case PSW_I: 2173e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_i, val); 2174e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_UPDATE; 2175e5918d7dSYoshinori Sato break; 2176e5918d7dSYoshinori Sato case PSW_U: 2177e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_u, val); 2178e5918d7dSYoshinori Sato break; 2179e5918d7dSYoshinori Sato default: 2180e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); 2181e5918d7dSYoshinori Sato break; 2182e5918d7dSYoshinori Sato } 2183e5918d7dSYoshinori Sato } 2184e5918d7dSYoshinori Sato } 2185e5918d7dSYoshinori Sato 2186e5918d7dSYoshinori Sato /* clrpsw psw */ 2187e5918d7dSYoshinori Sato static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a) 2188e5918d7dSYoshinori Sato { 2189e5918d7dSYoshinori Sato clrsetpsw(ctx, a->cb, 0); 2190e5918d7dSYoshinori Sato return true; 2191e5918d7dSYoshinori Sato } 2192e5918d7dSYoshinori Sato 2193e5918d7dSYoshinori Sato /* setpsw psw */ 2194e5918d7dSYoshinori Sato static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a) 2195e5918d7dSYoshinori Sato { 2196e5918d7dSYoshinori Sato clrsetpsw(ctx, a->cb, 1); 2197e5918d7dSYoshinori Sato return true; 2198e5918d7dSYoshinori Sato } 2199e5918d7dSYoshinori Sato 2200e5918d7dSYoshinori Sato /* mvtipl #imm */ 2201e5918d7dSYoshinori Sato static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a) 2202e5918d7dSYoshinori Sato { 2203e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2204e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_ipl, a->imm); 2205e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_UPDATE; 2206e5918d7dSYoshinori Sato } 2207e5918d7dSYoshinori Sato return true; 2208e5918d7dSYoshinori Sato } 2209e5918d7dSYoshinori Sato 2210e5918d7dSYoshinori Sato /* mvtc #imm, rd */ 2211e5918d7dSYoshinori Sato static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) 2212e5918d7dSYoshinori Sato { 2213e5918d7dSYoshinori Sato TCGv imm; 2214e5918d7dSYoshinori Sato 2215e5918d7dSYoshinori Sato imm = tcg_const_i32(a->imm); 2216e5918d7dSYoshinori Sato move_to_cr(ctx, imm, a->cr); 2217e5918d7dSYoshinori Sato if (a->cr == 0 && is_privileged(ctx, 0)) { 2218e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_UPDATE; 2219e5918d7dSYoshinori Sato } 2220e5918d7dSYoshinori Sato tcg_temp_free(imm); 2221e5918d7dSYoshinori Sato return true; 2222e5918d7dSYoshinori Sato } 2223e5918d7dSYoshinori Sato 2224e5918d7dSYoshinori Sato /* mvtc rs, rd */ 2225e5918d7dSYoshinori Sato static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) 2226e5918d7dSYoshinori Sato { 2227e5918d7dSYoshinori Sato move_to_cr(ctx, cpu_regs[a->rs], a->cr); 2228e5918d7dSYoshinori Sato if (a->cr == 0 && is_privileged(ctx, 0)) { 2229e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_UPDATE; 2230e5918d7dSYoshinori Sato } 2231e5918d7dSYoshinori Sato return true; 2232e5918d7dSYoshinori Sato } 2233e5918d7dSYoshinori Sato 2234e5918d7dSYoshinori Sato /* mvfc rs, rd */ 2235e5918d7dSYoshinori Sato static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) 2236e5918d7dSYoshinori Sato { 2237e5918d7dSYoshinori Sato move_from_cr(cpu_regs[a->rd], a->cr, ctx->pc); 2238e5918d7dSYoshinori Sato return true; 2239e5918d7dSYoshinori Sato } 2240e5918d7dSYoshinori Sato 2241e5918d7dSYoshinori Sato /* rtfi */ 2242e5918d7dSYoshinori Sato static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) 2243e5918d7dSYoshinori Sato { 2244e5918d7dSYoshinori Sato TCGv psw; 2245e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2246e5918d7dSYoshinori Sato psw = tcg_temp_new(); 2247e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_pc, cpu_bpc); 2248e5918d7dSYoshinori Sato tcg_gen_mov_i32(psw, cpu_bpsw); 2249e5918d7dSYoshinori Sato gen_helper_set_psw_rte(cpu_env, psw); 2250e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_EXIT; 2251e5918d7dSYoshinori Sato tcg_temp_free(psw); 2252e5918d7dSYoshinori Sato } 2253e5918d7dSYoshinori Sato return true; 2254e5918d7dSYoshinori Sato } 2255e5918d7dSYoshinori Sato 2256e5918d7dSYoshinori Sato /* rte */ 2257e5918d7dSYoshinori Sato static bool trans_RTE(DisasContext *ctx, arg_RTE *a) 2258e5918d7dSYoshinori Sato { 2259e5918d7dSYoshinori Sato TCGv psw; 2260e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2261e5918d7dSYoshinori Sato psw = tcg_temp_new(); 2262e5918d7dSYoshinori Sato pop(cpu_pc); 2263e5918d7dSYoshinori Sato pop(psw); 2264e5918d7dSYoshinori Sato gen_helper_set_psw_rte(cpu_env, psw); 2265e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_EXIT; 2266e5918d7dSYoshinori Sato tcg_temp_free(psw); 2267e5918d7dSYoshinori Sato } 2268e5918d7dSYoshinori Sato return true; 2269e5918d7dSYoshinori Sato } 2270e5918d7dSYoshinori Sato 2271e5918d7dSYoshinori Sato /* brk */ 2272e5918d7dSYoshinori Sato static bool trans_BRK(DisasContext *ctx, arg_BRK *a) 2273e5918d7dSYoshinori Sato { 2274e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2275e5918d7dSYoshinori Sato gen_helper_rxbrk(cpu_env); 2276e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_NORETURN; 2277e5918d7dSYoshinori Sato return true; 2278e5918d7dSYoshinori Sato } 2279e5918d7dSYoshinori Sato 2280e5918d7dSYoshinori Sato /* int #imm */ 2281e5918d7dSYoshinori Sato static bool trans_INT(DisasContext *ctx, arg_INT *a) 2282e5918d7dSYoshinori Sato { 2283e5918d7dSYoshinori Sato TCGv vec; 2284e5918d7dSYoshinori Sato 2285e5918d7dSYoshinori Sato tcg_debug_assert(a->imm < 0x100); 2286e5918d7dSYoshinori Sato vec = tcg_const_i32(a->imm); 2287e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2288e5918d7dSYoshinori Sato gen_helper_rxint(cpu_env, vec); 2289e5918d7dSYoshinori Sato tcg_temp_free(vec); 2290e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_NORETURN; 2291e5918d7dSYoshinori Sato return true; 2292e5918d7dSYoshinori Sato } 2293e5918d7dSYoshinori Sato 2294e5918d7dSYoshinori Sato /* wait */ 2295e5918d7dSYoshinori Sato static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) 2296e5918d7dSYoshinori Sato { 2297e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2298e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_pc, cpu_pc, 2); 2299e5918d7dSYoshinori Sato gen_helper_wait(cpu_env); 2300e5918d7dSYoshinori Sato } 2301e5918d7dSYoshinori Sato return true; 2302e5918d7dSYoshinori Sato } 2303e5918d7dSYoshinori Sato 2304e5918d7dSYoshinori Sato static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 2305e5918d7dSYoshinori Sato { 2306e5918d7dSYoshinori Sato CPURXState *env = cs->env_ptr; 2307e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2308e5918d7dSYoshinori Sato ctx->env = env; 2309e5918d7dSYoshinori Sato } 2310e5918d7dSYoshinori Sato 2311e5918d7dSYoshinori Sato static void rx_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) 2312e5918d7dSYoshinori Sato { 2313e5918d7dSYoshinori Sato } 2314e5918d7dSYoshinori Sato 2315e5918d7dSYoshinori Sato static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 2316e5918d7dSYoshinori Sato { 2317e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2318e5918d7dSYoshinori Sato 2319e5918d7dSYoshinori Sato tcg_gen_insn_start(ctx->base.pc_next); 2320e5918d7dSYoshinori Sato } 2321e5918d7dSYoshinori Sato 2322e5918d7dSYoshinori Sato static bool rx_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 2323e5918d7dSYoshinori Sato const CPUBreakpoint *bp) 2324e5918d7dSYoshinori Sato { 2325e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2326e5918d7dSYoshinori Sato 2327e5918d7dSYoshinori Sato /* We have hit a breakpoint - make sure PC is up-to-date */ 2328e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2329e5918d7dSYoshinori Sato gen_helper_debug(cpu_env); 2330e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_NORETURN; 2331e5918d7dSYoshinori Sato ctx->base.pc_next += 1; 2332e5918d7dSYoshinori Sato return true; 2333e5918d7dSYoshinori Sato } 2334e5918d7dSYoshinori Sato 2335e5918d7dSYoshinori Sato static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 2336e5918d7dSYoshinori Sato { 2337e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2338e5918d7dSYoshinori Sato uint32_t insn; 2339e5918d7dSYoshinori Sato 2340e5918d7dSYoshinori Sato ctx->pc = ctx->base.pc_next; 2341e5918d7dSYoshinori Sato insn = decode_load(ctx); 2342e5918d7dSYoshinori Sato if (!decode(ctx, insn)) { 2343e5918d7dSYoshinori Sato gen_helper_raise_illegal_instruction(cpu_env); 2344e5918d7dSYoshinori Sato } 2345e5918d7dSYoshinori Sato } 2346e5918d7dSYoshinori Sato 2347e5918d7dSYoshinori Sato static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 2348e5918d7dSYoshinori Sato { 2349e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2350e5918d7dSYoshinori Sato 2351e5918d7dSYoshinori Sato switch (ctx->base.is_jmp) { 2352e5918d7dSYoshinori Sato case DISAS_NEXT: 2353e5918d7dSYoshinori Sato case DISAS_TOO_MANY: 2354e5918d7dSYoshinori Sato gen_goto_tb(ctx, 0, dcbase->pc_next); 2355e5918d7dSYoshinori Sato break; 2356e5918d7dSYoshinori Sato case DISAS_JUMP: 2357e5918d7dSYoshinori Sato if (ctx->base.singlestep_enabled) { 2358e5918d7dSYoshinori Sato gen_helper_debug(cpu_env); 2359e5918d7dSYoshinori Sato } else { 2360e5918d7dSYoshinori Sato tcg_gen_lookup_and_goto_ptr(); 2361e5918d7dSYoshinori Sato } 2362e5918d7dSYoshinori Sato break; 2363e5918d7dSYoshinori Sato case DISAS_UPDATE: 2364e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 236540bd0502SPhilippe Mathieu-Daudé /* fall through */ 2366e5918d7dSYoshinori Sato case DISAS_EXIT: 2367e5918d7dSYoshinori Sato tcg_gen_exit_tb(NULL, 0); 2368e5918d7dSYoshinori Sato break; 2369e5918d7dSYoshinori Sato case DISAS_NORETURN: 2370e5918d7dSYoshinori Sato break; 2371e5918d7dSYoshinori Sato default: 2372e5918d7dSYoshinori Sato g_assert_not_reached(); 2373e5918d7dSYoshinori Sato } 2374e5918d7dSYoshinori Sato } 2375e5918d7dSYoshinori Sato 2376e5918d7dSYoshinori Sato static void rx_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 2377e5918d7dSYoshinori Sato { 2378e5918d7dSYoshinori Sato qemu_log("IN:\n"); /* , lookup_symbol(dcbase->pc_first)); */ 2379e5918d7dSYoshinori Sato log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 2380e5918d7dSYoshinori Sato } 2381e5918d7dSYoshinori Sato 2382e5918d7dSYoshinori Sato static const TranslatorOps rx_tr_ops = { 2383e5918d7dSYoshinori Sato .init_disas_context = rx_tr_init_disas_context, 2384e5918d7dSYoshinori Sato .tb_start = rx_tr_tb_start, 2385e5918d7dSYoshinori Sato .insn_start = rx_tr_insn_start, 2386e5918d7dSYoshinori Sato .breakpoint_check = rx_tr_breakpoint_check, 2387e5918d7dSYoshinori Sato .translate_insn = rx_tr_translate_insn, 2388e5918d7dSYoshinori Sato .tb_stop = rx_tr_tb_stop, 2389e5918d7dSYoshinori Sato .disas_log = rx_tr_disas_log, 2390e5918d7dSYoshinori Sato }; 2391e5918d7dSYoshinori Sato 2392e5918d7dSYoshinori Sato void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 2393e5918d7dSYoshinori Sato { 2394e5918d7dSYoshinori Sato DisasContext dc; 2395e5918d7dSYoshinori Sato 2396e5918d7dSYoshinori Sato translator_loop(&rx_tr_ops, &dc.base, cs, tb, max_insns); 2397e5918d7dSYoshinori Sato } 2398e5918d7dSYoshinori Sato 2399e5918d7dSYoshinori Sato void restore_state_to_opc(CPURXState *env, TranslationBlock *tb, 2400e5918d7dSYoshinori Sato target_ulong *data) 2401e5918d7dSYoshinori Sato { 2402e5918d7dSYoshinori Sato env->pc = data[0]; 2403e5918d7dSYoshinori Sato } 2404e5918d7dSYoshinori Sato 2405e5918d7dSYoshinori Sato #define ALLOC_REGISTER(sym, name) \ 2406e5918d7dSYoshinori Sato cpu_##sym = tcg_global_mem_new_i32(cpu_env, \ 2407e5918d7dSYoshinori Sato offsetof(CPURXState, sym), name) 2408e5918d7dSYoshinori Sato 2409e5918d7dSYoshinori Sato void rx_translate_init(void) 2410e5918d7dSYoshinori Sato { 2411e5918d7dSYoshinori Sato static const char * const regnames[NUM_REGS] = { 2412e5918d7dSYoshinori Sato "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", 2413e5918d7dSYoshinori Sato "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15" 2414e5918d7dSYoshinori Sato }; 2415e5918d7dSYoshinori Sato int i; 2416e5918d7dSYoshinori Sato 2417e5918d7dSYoshinori Sato for (i = 0; i < NUM_REGS; i++) { 2418e5918d7dSYoshinori Sato cpu_regs[i] = tcg_global_mem_new_i32(cpu_env, 2419e5918d7dSYoshinori Sato offsetof(CPURXState, regs[i]), 2420e5918d7dSYoshinori Sato regnames[i]); 2421e5918d7dSYoshinori Sato } 2422e5918d7dSYoshinori Sato ALLOC_REGISTER(pc, "PC"); 2423e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_o, "PSW(O)"); 2424e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_s, "PSW(S)"); 2425e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_z, "PSW(Z)"); 2426e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_c, "PSW(C)"); 2427e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_u, "PSW(U)"); 2428e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_i, "PSW(I)"); 2429e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_pm, "PSW(PM)"); 2430e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_ipl, "PSW(IPL)"); 2431e5918d7dSYoshinori Sato ALLOC_REGISTER(usp, "USP"); 2432e5918d7dSYoshinori Sato ALLOC_REGISTER(fpsw, "FPSW"); 2433e5918d7dSYoshinori Sato ALLOC_REGISTER(bpsw, "BPSW"); 2434e5918d7dSYoshinori Sato ALLOC_REGISTER(bpc, "BPC"); 2435e5918d7dSYoshinori Sato ALLOC_REGISTER(isp, "ISP"); 2436e5918d7dSYoshinori Sato ALLOC_REGISTER(fintv, "FINTV"); 2437e5918d7dSYoshinori Sato ALLOC_REGISTER(intb, "INTB"); 2438e5918d7dSYoshinori Sato cpu_acc = tcg_global_mem_new_i64(cpu_env, 2439e5918d7dSYoshinori Sato offsetof(CPURXState, acc), "ACC"); 2440e5918d7dSYoshinori Sato } 2441