1e5918d7dSYoshinori Sato /* 2e5918d7dSYoshinori Sato * RX translation 3e5918d7dSYoshinori Sato * 4e5918d7dSYoshinori Sato * Copyright (c) 2019 Yoshinori Sato 5e5918d7dSYoshinori Sato * 6e5918d7dSYoshinori Sato * This program is free software; you can redistribute it and/or modify it 7e5918d7dSYoshinori Sato * under the terms and conditions of the GNU General Public License, 8e5918d7dSYoshinori Sato * version 2 or later, as published by the Free Software Foundation. 9e5918d7dSYoshinori Sato * 10e5918d7dSYoshinori Sato * This program is distributed in the hope it will be useful, but WITHOUT 11e5918d7dSYoshinori Sato * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12e5918d7dSYoshinori Sato * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13e5918d7dSYoshinori Sato * more details. 14e5918d7dSYoshinori Sato * 15e5918d7dSYoshinori Sato * You should have received a copy of the GNU General Public License along with 16e5918d7dSYoshinori Sato * this program. If not, see <http://www.gnu.org/licenses/>. 17e5918d7dSYoshinori Sato */ 18e5918d7dSYoshinori Sato 19e5918d7dSYoshinori Sato #include "qemu/osdep.h" 20e5918d7dSYoshinori Sato #include "qemu/bswap.h" 21e5918d7dSYoshinori Sato #include "qemu/qemu-print.h" 22e5918d7dSYoshinori Sato #include "cpu.h" 23e5918d7dSYoshinori Sato #include "exec/exec-all.h" 24e5918d7dSYoshinori Sato #include "tcg/tcg-op.h" 25e5918d7dSYoshinori Sato #include "exec/cpu_ldst.h" 26e5918d7dSYoshinori Sato #include "exec/helper-proto.h" 27e5918d7dSYoshinori Sato #include "exec/helper-gen.h" 28e5918d7dSYoshinori Sato #include "exec/translator.h" 29e5918d7dSYoshinori Sato #include "exec/log.h" 30e5918d7dSYoshinori Sato 31e5918d7dSYoshinori Sato typedef struct DisasContext { 32e5918d7dSYoshinori Sato DisasContextBase base; 33e5918d7dSYoshinori Sato CPURXState *env; 34e5918d7dSYoshinori Sato uint32_t pc; 354341631eSRichard Henderson uint32_t tb_flags; 36e5918d7dSYoshinori Sato } DisasContext; 37e5918d7dSYoshinori Sato 38e5918d7dSYoshinori Sato typedef struct DisasCompare { 39e5918d7dSYoshinori Sato TCGv value; 40e5918d7dSYoshinori Sato TCGv temp; 41e5918d7dSYoshinori Sato TCGCond cond; 42e5918d7dSYoshinori Sato } DisasCompare; 43e5918d7dSYoshinori Sato 4427a4a30eSYoshinori Sato const char *rx_crname(uint8_t cr) 4527a4a30eSYoshinori Sato { 4627a4a30eSYoshinori Sato static const char *cr_names[] = { 47e5918d7dSYoshinori Sato "psw", "pc", "usp", "fpsw", "", "", "", "", 4827a4a30eSYoshinori Sato "bpsw", "bpc", "isp", "fintv", "intb", "", "", "" 49e5918d7dSYoshinori Sato }; 5027a4a30eSYoshinori Sato if (cr >= ARRAY_SIZE(cr_names)) { 5127a4a30eSYoshinori Sato return "illegal"; 5227a4a30eSYoshinori Sato } 5327a4a30eSYoshinori Sato return cr_names[cr]; 5427a4a30eSYoshinori Sato } 55e5918d7dSYoshinori Sato 56e5918d7dSYoshinori Sato /* Target-specific values for dc->base.is_jmp. */ 57e5918d7dSYoshinori Sato #define DISAS_JUMP DISAS_TARGET_0 58e5918d7dSYoshinori Sato #define DISAS_UPDATE DISAS_TARGET_1 59e5918d7dSYoshinori Sato #define DISAS_EXIT DISAS_TARGET_2 60e5918d7dSYoshinori Sato 61e5918d7dSYoshinori Sato /* global register indexes */ 62e5918d7dSYoshinori Sato static TCGv cpu_regs[16]; 63e5918d7dSYoshinori Sato static TCGv cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c; 64e5918d7dSYoshinori Sato static TCGv cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl; 65e5918d7dSYoshinori Sato static TCGv cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp; 66e5918d7dSYoshinori Sato static TCGv cpu_fintv, cpu_intb, cpu_pc; 67e5918d7dSYoshinori Sato static TCGv_i64 cpu_acc; 68e5918d7dSYoshinori Sato 69e5918d7dSYoshinori Sato #define cpu_sp cpu_regs[0] 70e5918d7dSYoshinori Sato 71e5918d7dSYoshinori Sato #include "exec/gen-icount.h" 72e5918d7dSYoshinori Sato 73e5918d7dSYoshinori Sato /* decoder helper */ 74e5918d7dSYoshinori Sato static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, 75e5918d7dSYoshinori Sato int i, int n) 76e5918d7dSYoshinori Sato { 77e5918d7dSYoshinori Sato while (++i <= n) { 78e5918d7dSYoshinori Sato uint8_t b = cpu_ldub_code(ctx->env, ctx->base.pc_next++); 79e5918d7dSYoshinori Sato insn |= b << (32 - i * 8); 80e5918d7dSYoshinori Sato } 81e5918d7dSYoshinori Sato return insn; 82e5918d7dSYoshinori Sato } 83e5918d7dSYoshinori Sato 84e5918d7dSYoshinori Sato static uint32_t li(DisasContext *ctx, int sz) 85e5918d7dSYoshinori Sato { 86e5918d7dSYoshinori Sato int32_t tmp, addr; 87e5918d7dSYoshinori Sato CPURXState *env = ctx->env; 88e5918d7dSYoshinori Sato addr = ctx->base.pc_next; 89e5918d7dSYoshinori Sato 90e5918d7dSYoshinori Sato tcg_debug_assert(sz < 4); 91e5918d7dSYoshinori Sato switch (sz) { 92e5918d7dSYoshinori Sato case 1: 93e5918d7dSYoshinori Sato ctx->base.pc_next += 1; 94e5918d7dSYoshinori Sato return cpu_ldsb_code(env, addr); 95e5918d7dSYoshinori Sato case 2: 96e5918d7dSYoshinori Sato ctx->base.pc_next += 2; 97e5918d7dSYoshinori Sato return cpu_ldsw_code(env, addr); 98e5918d7dSYoshinori Sato case 3: 99e5918d7dSYoshinori Sato ctx->base.pc_next += 3; 100e5918d7dSYoshinori Sato tmp = cpu_ldsb_code(env, addr + 2) << 16; 101e5918d7dSYoshinori Sato tmp |= cpu_lduw_code(env, addr) & 0xffff; 102e5918d7dSYoshinori Sato return tmp; 103e5918d7dSYoshinori Sato case 0: 104e5918d7dSYoshinori Sato ctx->base.pc_next += 4; 105e5918d7dSYoshinori Sato return cpu_ldl_code(env, addr); 106e5918d7dSYoshinori Sato } 107e5918d7dSYoshinori Sato return 0; 108e5918d7dSYoshinori Sato } 109e5918d7dSYoshinori Sato 110e5918d7dSYoshinori Sato static int bdsp_s(DisasContext *ctx, int d) 111e5918d7dSYoshinori Sato { 112e5918d7dSYoshinori Sato /* 113e5918d7dSYoshinori Sato * 0 -> 8 114e5918d7dSYoshinori Sato * 1 -> 9 115e5918d7dSYoshinori Sato * 2 -> 10 116e5918d7dSYoshinori Sato * 3 -> 3 117e5918d7dSYoshinori Sato * : 118e5918d7dSYoshinori Sato * 7 -> 7 119e5918d7dSYoshinori Sato */ 120e5918d7dSYoshinori Sato if (d < 3) { 121e5918d7dSYoshinori Sato d += 8; 122e5918d7dSYoshinori Sato } 123e5918d7dSYoshinori Sato return d; 124e5918d7dSYoshinori Sato } 125e5918d7dSYoshinori Sato 126e5918d7dSYoshinori Sato /* Include the auto-generated decoder. */ 127abff1abfSPaolo Bonzini #include "decode-insns.c.inc" 128e5918d7dSYoshinori Sato 129e5918d7dSYoshinori Sato void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) 130e5918d7dSYoshinori Sato { 13138688fdbSEduardo Habkost RXCPU *cpu = RX_CPU(cs); 132e5918d7dSYoshinori Sato CPURXState *env = &cpu->env; 133e5918d7dSYoshinori Sato int i; 134e5918d7dSYoshinori Sato uint32_t psw; 135e5918d7dSYoshinori Sato 136e5918d7dSYoshinori Sato psw = rx_cpu_pack_psw(env); 137e5918d7dSYoshinori Sato qemu_fprintf(f, "pc=0x%08x psw=0x%08x\n", 138e5918d7dSYoshinori Sato env->pc, psw); 139e5918d7dSYoshinori Sato for (i = 0; i < 16; i += 4) { 140e5918d7dSYoshinori Sato qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", 141e5918d7dSYoshinori Sato i, env->regs[i], i + 1, env->regs[i + 1], 142e5918d7dSYoshinori Sato i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]); 143e5918d7dSYoshinori Sato } 144e5918d7dSYoshinori Sato } 145e5918d7dSYoshinori Sato 146e5918d7dSYoshinori Sato static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) 147e5918d7dSYoshinori Sato { 148f3f713ccSRichard Henderson if (translator_use_goto_tb(&dc->base, dest)) { 149e5918d7dSYoshinori Sato tcg_gen_goto_tb(n); 150e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, dest); 151e5918d7dSYoshinori Sato tcg_gen_exit_tb(dc->base.tb, n); 152e5918d7dSYoshinori Sato } else { 153e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, dest); 154e5918d7dSYoshinori Sato tcg_gen_lookup_and_goto_ptr(); 155e5918d7dSYoshinori Sato } 156e5918d7dSYoshinori Sato dc->base.is_jmp = DISAS_NORETURN; 157e5918d7dSYoshinori Sato } 158e5918d7dSYoshinori Sato 159e5918d7dSYoshinori Sato /* generic load wrapper */ 160e5918d7dSYoshinori Sato static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem) 161e5918d7dSYoshinori Sato { 162e5918d7dSYoshinori Sato tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); 163e5918d7dSYoshinori Sato } 164e5918d7dSYoshinori Sato 165e5918d7dSYoshinori Sato /* unsigned load wrapper */ 166e5918d7dSYoshinori Sato static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem) 167e5918d7dSYoshinori Sato { 168e5918d7dSYoshinori Sato tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); 169e5918d7dSYoshinori Sato } 170e5918d7dSYoshinori Sato 171e5918d7dSYoshinori Sato /* generic store wrapper */ 172e5918d7dSYoshinori Sato static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem) 173e5918d7dSYoshinori Sato { 174e5918d7dSYoshinori Sato tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); 175e5918d7dSYoshinori Sato } 176e5918d7dSYoshinori Sato 177e5918d7dSYoshinori Sato /* [ri, rb] */ 178e5918d7dSYoshinori Sato static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem, 179e5918d7dSYoshinori Sato int size, int ri, int rb) 180e5918d7dSYoshinori Sato { 181e5918d7dSYoshinori Sato tcg_gen_shli_i32(mem, cpu_regs[ri], size); 182e5918d7dSYoshinori Sato tcg_gen_add_i32(mem, mem, cpu_regs[rb]); 183e5918d7dSYoshinori Sato } 184e5918d7dSYoshinori Sato 185e5918d7dSYoshinori Sato /* dsp[reg] */ 186e5918d7dSYoshinori Sato static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem, 187e5918d7dSYoshinori Sato int ld, int size, int reg) 188e5918d7dSYoshinori Sato { 189e5918d7dSYoshinori Sato uint32_t dsp; 190e5918d7dSYoshinori Sato 191e5918d7dSYoshinori Sato tcg_debug_assert(ld < 3); 192e5918d7dSYoshinori Sato switch (ld) { 193e5918d7dSYoshinori Sato case 0: 194e5918d7dSYoshinori Sato return cpu_regs[reg]; 195e5918d7dSYoshinori Sato case 1: 196e5918d7dSYoshinori Sato dsp = cpu_ldub_code(ctx->env, ctx->base.pc_next) << size; 197e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 198e5918d7dSYoshinori Sato ctx->base.pc_next += 1; 199e5918d7dSYoshinori Sato return mem; 200e5918d7dSYoshinori Sato case 2: 201e5918d7dSYoshinori Sato dsp = cpu_lduw_code(ctx->env, ctx->base.pc_next) << size; 202e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); 203e5918d7dSYoshinori Sato ctx->base.pc_next += 2; 204e5918d7dSYoshinori Sato return mem; 205e5918d7dSYoshinori Sato } 206e5918d7dSYoshinori Sato return NULL; 207e5918d7dSYoshinori Sato } 208e5918d7dSYoshinori Sato 209e5918d7dSYoshinori Sato static inline MemOp mi_to_mop(unsigned mi) 210e5918d7dSYoshinori Sato { 211e5918d7dSYoshinori Sato static const MemOp mop[5] = { MO_SB, MO_SW, MO_UL, MO_UW, MO_UB }; 212e5918d7dSYoshinori Sato tcg_debug_assert(mi < 5); 213e5918d7dSYoshinori Sato return mop[mi]; 214e5918d7dSYoshinori Sato } 215e5918d7dSYoshinori Sato 216e5918d7dSYoshinori Sato /* load source operand */ 217e5918d7dSYoshinori Sato static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem, 218e5918d7dSYoshinori Sato int ld, int mi, int rs) 219e5918d7dSYoshinori Sato { 220e5918d7dSYoshinori Sato TCGv addr; 221e5918d7dSYoshinori Sato MemOp mop; 222e5918d7dSYoshinori Sato if (ld < 3) { 223e5918d7dSYoshinori Sato mop = mi_to_mop(mi); 224e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs); 225e5918d7dSYoshinori Sato tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE); 226e5918d7dSYoshinori Sato return mem; 227e5918d7dSYoshinori Sato } else { 228e5918d7dSYoshinori Sato return cpu_regs[rs]; 229e5918d7dSYoshinori Sato } 230e5918d7dSYoshinori Sato } 231e5918d7dSYoshinori Sato 232e5918d7dSYoshinori Sato /* Processor mode check */ 233e5918d7dSYoshinori Sato static int is_privileged(DisasContext *ctx, int is_exception) 234e5918d7dSYoshinori Sato { 2354341631eSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, PM)) { 236e5918d7dSYoshinori Sato if (is_exception) { 237e5918d7dSYoshinori Sato gen_helper_raise_privilege_violation(cpu_env); 238e5918d7dSYoshinori Sato } 239e5918d7dSYoshinori Sato return 0; 240e5918d7dSYoshinori Sato } else { 241e5918d7dSYoshinori Sato return 1; 242e5918d7dSYoshinori Sato } 243e5918d7dSYoshinori Sato } 244e5918d7dSYoshinori Sato 245e5918d7dSYoshinori Sato /* generate QEMU condition */ 246e5918d7dSYoshinori Sato static void psw_cond(DisasCompare *dc, uint32_t cond) 247e5918d7dSYoshinori Sato { 248e5918d7dSYoshinori Sato tcg_debug_assert(cond < 16); 249e5918d7dSYoshinori Sato switch (cond) { 250e5918d7dSYoshinori Sato case 0: /* z */ 251e5918d7dSYoshinori Sato dc->cond = TCG_COND_EQ; 252e5918d7dSYoshinori Sato dc->value = cpu_psw_z; 253e5918d7dSYoshinori Sato break; 254e5918d7dSYoshinori Sato case 1: /* nz */ 255e5918d7dSYoshinori Sato dc->cond = TCG_COND_NE; 256e5918d7dSYoshinori Sato dc->value = cpu_psw_z; 257e5918d7dSYoshinori Sato break; 258e5918d7dSYoshinori Sato case 2: /* c */ 259e5918d7dSYoshinori Sato dc->cond = TCG_COND_NE; 260e5918d7dSYoshinori Sato dc->value = cpu_psw_c; 261e5918d7dSYoshinori Sato break; 262e5918d7dSYoshinori Sato case 3: /* nc */ 263e5918d7dSYoshinori Sato dc->cond = TCG_COND_EQ; 264e5918d7dSYoshinori Sato dc->value = cpu_psw_c; 265e5918d7dSYoshinori Sato break; 266e5918d7dSYoshinori Sato case 4: /* gtu (C& ~Z) == 1 */ 267e5918d7dSYoshinori Sato case 5: /* leu (C& ~Z) == 0 */ 268e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0); 269e5918d7dSYoshinori Sato tcg_gen_and_i32(dc->temp, dc->temp, cpu_psw_c); 270e5918d7dSYoshinori Sato dc->cond = (cond == 4) ? TCG_COND_NE : TCG_COND_EQ; 271e5918d7dSYoshinori Sato dc->value = dc->temp; 272e5918d7dSYoshinori Sato break; 273e5918d7dSYoshinori Sato case 6: /* pz (S == 0) */ 274e5918d7dSYoshinori Sato dc->cond = TCG_COND_GE; 275e5918d7dSYoshinori Sato dc->value = cpu_psw_s; 276e5918d7dSYoshinori Sato break; 277e5918d7dSYoshinori Sato case 7: /* n (S == 1) */ 278e5918d7dSYoshinori Sato dc->cond = TCG_COND_LT; 279e5918d7dSYoshinori Sato dc->value = cpu_psw_s; 280e5918d7dSYoshinori Sato break; 281e5918d7dSYoshinori Sato case 8: /* ge (S^O)==0 */ 282e5918d7dSYoshinori Sato case 9: /* lt (S^O)==1 */ 283e5918d7dSYoshinori Sato tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 284e5918d7dSYoshinori Sato dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT; 285e5918d7dSYoshinori Sato dc->value = dc->temp; 286e5918d7dSYoshinori Sato break; 287e5918d7dSYoshinori Sato case 10: /* gt ((S^O)|Z)==0 */ 288e5918d7dSYoshinori Sato case 11: /* le ((S^O)|Z)==1 */ 289e5918d7dSYoshinori Sato tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); 290e5918d7dSYoshinori Sato tcg_gen_sari_i32(dc->temp, dc->temp, 31); 291e5918d7dSYoshinori Sato tcg_gen_andc_i32(dc->temp, cpu_psw_z, dc->temp); 292e5918d7dSYoshinori Sato dc->cond = (cond == 10) ? TCG_COND_NE : TCG_COND_EQ; 293e5918d7dSYoshinori Sato dc->value = dc->temp; 294e5918d7dSYoshinori Sato break; 295e5918d7dSYoshinori Sato case 12: /* o */ 296e5918d7dSYoshinori Sato dc->cond = TCG_COND_LT; 297e5918d7dSYoshinori Sato dc->value = cpu_psw_o; 298e5918d7dSYoshinori Sato break; 299e5918d7dSYoshinori Sato case 13: /* no */ 300e5918d7dSYoshinori Sato dc->cond = TCG_COND_GE; 301e5918d7dSYoshinori Sato dc->value = cpu_psw_o; 302e5918d7dSYoshinori Sato break; 303e5918d7dSYoshinori Sato case 14: /* always true */ 304e5918d7dSYoshinori Sato dc->cond = TCG_COND_ALWAYS; 305e5918d7dSYoshinori Sato dc->value = dc->temp; 306e5918d7dSYoshinori Sato break; 307e5918d7dSYoshinori Sato case 15: /* always false */ 308e5918d7dSYoshinori Sato dc->cond = TCG_COND_NEVER; 309e5918d7dSYoshinori Sato dc->value = dc->temp; 310e5918d7dSYoshinori Sato break; 311e5918d7dSYoshinori Sato } 312e5918d7dSYoshinori Sato } 313e5918d7dSYoshinori Sato 3143626a3feSRichard Henderson static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc) 315e5918d7dSYoshinori Sato { 316e5918d7dSYoshinori Sato switch (cr) { 317e5918d7dSYoshinori Sato case 0: /* PSW */ 318e5918d7dSYoshinori Sato gen_helper_pack_psw(ret, cpu_env); 319e5918d7dSYoshinori Sato break; 320e5918d7dSYoshinori Sato case 1: /* PC */ 321e5918d7dSYoshinori Sato tcg_gen_movi_i32(ret, pc); 322e5918d7dSYoshinori Sato break; 323e5918d7dSYoshinori Sato case 2: /* USP */ 3243626a3feSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 3253626a3feSRichard Henderson tcg_gen_mov_i32(ret, cpu_sp); 3263626a3feSRichard Henderson } else { 3273626a3feSRichard Henderson tcg_gen_mov_i32(ret, cpu_usp); 3283626a3feSRichard Henderson } 329e5918d7dSYoshinori Sato break; 330e5918d7dSYoshinori Sato case 3: /* FPSW */ 331e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_fpsw); 332e5918d7dSYoshinori Sato break; 333e5918d7dSYoshinori Sato case 8: /* BPSW */ 334e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_bpsw); 335e5918d7dSYoshinori Sato break; 336e5918d7dSYoshinori Sato case 9: /* BPC */ 337e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_bpc); 338e5918d7dSYoshinori Sato break; 339e5918d7dSYoshinori Sato case 10: /* ISP */ 3403626a3feSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 3413626a3feSRichard Henderson tcg_gen_mov_i32(ret, cpu_isp); 3423626a3feSRichard Henderson } else { 3433626a3feSRichard Henderson tcg_gen_mov_i32(ret, cpu_sp); 3443626a3feSRichard Henderson } 345e5918d7dSYoshinori Sato break; 346e5918d7dSYoshinori Sato case 11: /* FINTV */ 347e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_fintv); 348e5918d7dSYoshinori Sato break; 349e5918d7dSYoshinori Sato case 12: /* INTB */ 350e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_intb); 351e5918d7dSYoshinori Sato break; 352e5918d7dSYoshinori Sato default: 353e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "Unimplement control register %d", cr); 354e5918d7dSYoshinori Sato /* Unimplement registers return 0 */ 355e5918d7dSYoshinori Sato tcg_gen_movi_i32(ret, 0); 356e5918d7dSYoshinori Sato break; 357e5918d7dSYoshinori Sato } 358e5918d7dSYoshinori Sato } 359e5918d7dSYoshinori Sato 360e5918d7dSYoshinori Sato static void move_to_cr(DisasContext *ctx, TCGv val, int cr) 361e5918d7dSYoshinori Sato { 362e5918d7dSYoshinori Sato if (cr >= 8 && !is_privileged(ctx, 0)) { 363e5918d7dSYoshinori Sato /* Some control registers can only be written in privileged mode. */ 364e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 36527a4a30eSYoshinori Sato "disallow control register write %s", rx_crname(cr)); 366e5918d7dSYoshinori Sato return; 367e5918d7dSYoshinori Sato } 368e5918d7dSYoshinori Sato switch (cr) { 369e5918d7dSYoshinori Sato case 0: /* PSW */ 370e5918d7dSYoshinori Sato gen_helper_set_psw(cpu_env, val); 371d3562fe2SRichard Henderson if (is_privileged(ctx, 0)) { 372d3562fe2SRichard Henderson /* PSW.{I,U} may be updated here. exit TB. */ 373d3562fe2SRichard Henderson ctx->base.is_jmp = DISAS_UPDATE; 374d3562fe2SRichard Henderson } 375e5918d7dSYoshinori Sato break; 376e5918d7dSYoshinori Sato /* case 1: to PC not supported */ 377e5918d7dSYoshinori Sato case 2: /* USP */ 3783626a3feSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 3793626a3feSRichard Henderson tcg_gen_mov_i32(cpu_sp, val); 3803626a3feSRichard Henderson } else { 381e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_usp, val); 3823626a3feSRichard Henderson } 383e5918d7dSYoshinori Sato break; 384e5918d7dSYoshinori Sato case 3: /* FPSW */ 385e5918d7dSYoshinori Sato gen_helper_set_fpsw(cpu_env, val); 386e5918d7dSYoshinori Sato break; 387e5918d7dSYoshinori Sato case 8: /* BPSW */ 388e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_bpsw, val); 389e5918d7dSYoshinori Sato break; 390e5918d7dSYoshinori Sato case 9: /* BPC */ 391e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_bpc, val); 392e5918d7dSYoshinori Sato break; 393e5918d7dSYoshinori Sato case 10: /* ISP */ 3943626a3feSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, U)) { 395e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_isp, val); 3963626a3feSRichard Henderson } else { 3973626a3feSRichard Henderson tcg_gen_mov_i32(cpu_sp, val); 3983626a3feSRichard Henderson } 399e5918d7dSYoshinori Sato break; 400e5918d7dSYoshinori Sato case 11: /* FINTV */ 401e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_fintv, val); 402e5918d7dSYoshinori Sato break; 403e5918d7dSYoshinori Sato case 12: /* INTB */ 404e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_intb, val); 405e5918d7dSYoshinori Sato break; 406e5918d7dSYoshinori Sato default: 407e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 408e5918d7dSYoshinori Sato "Unimplement control register %d", cr); 409e5918d7dSYoshinori Sato break; 410e5918d7dSYoshinori Sato } 411e5918d7dSYoshinori Sato } 412e5918d7dSYoshinori Sato 413e5918d7dSYoshinori Sato static void push(TCGv val) 414e5918d7dSYoshinori Sato { 415e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 416e5918d7dSYoshinori Sato rx_gen_st(MO_32, val, cpu_sp); 417e5918d7dSYoshinori Sato } 418e5918d7dSYoshinori Sato 419e5918d7dSYoshinori Sato static void pop(TCGv ret) 420e5918d7dSYoshinori Sato { 421e5918d7dSYoshinori Sato rx_gen_ld(MO_32, ret, cpu_sp); 422e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_sp, cpu_sp, 4); 423e5918d7dSYoshinori Sato } 424e5918d7dSYoshinori Sato 425e5918d7dSYoshinori Sato /* mov.<bwl> rs,dsp5[rd] */ 426e5918d7dSYoshinori Sato static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) 427e5918d7dSYoshinori Sato { 428e5918d7dSYoshinori Sato TCGv mem; 429e5918d7dSYoshinori Sato mem = tcg_temp_new(); 430e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 431e5918d7dSYoshinori Sato rx_gen_st(a->sz, cpu_regs[a->rs], mem); 432e5918d7dSYoshinori Sato return true; 433e5918d7dSYoshinori Sato } 434e5918d7dSYoshinori Sato 435e5918d7dSYoshinori Sato /* mov.<bwl> dsp5[rs],rd */ 436e5918d7dSYoshinori Sato static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) 437e5918d7dSYoshinori Sato { 438e5918d7dSYoshinori Sato TCGv mem; 439e5918d7dSYoshinori Sato mem = tcg_temp_new(); 440e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 441e5918d7dSYoshinori Sato rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 442e5918d7dSYoshinori Sato return true; 443e5918d7dSYoshinori Sato } 444e5918d7dSYoshinori Sato 445e5918d7dSYoshinori Sato /* mov.l #uimm4,rd */ 446e5918d7dSYoshinori Sato /* mov.l #uimm8,rd */ 447e5918d7dSYoshinori Sato /* mov.l #imm,rd */ 448e5918d7dSYoshinori Sato static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) 449e5918d7dSYoshinori Sato { 450e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); 451e5918d7dSYoshinori Sato return true; 452e5918d7dSYoshinori Sato } 453e5918d7dSYoshinori Sato 454e5918d7dSYoshinori Sato /* mov.<bwl> #uimm8,dsp[rd] */ 455e5918d7dSYoshinori Sato /* mov.<bwl> #imm, dsp[rd] */ 456e5918d7dSYoshinori Sato static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) 457e5918d7dSYoshinori Sato { 458e5918d7dSYoshinori Sato TCGv imm, mem; 459e5918d7dSYoshinori Sato imm = tcg_const_i32(a->imm); 460e5918d7dSYoshinori Sato mem = tcg_temp_new(); 461e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); 462e5918d7dSYoshinori Sato rx_gen_st(a->sz, imm, mem); 463e5918d7dSYoshinori Sato return true; 464e5918d7dSYoshinori Sato } 465e5918d7dSYoshinori Sato 466e5918d7dSYoshinori Sato /* mov.<bwl> [ri,rb],rd */ 467e5918d7dSYoshinori Sato static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a) 468e5918d7dSYoshinori Sato { 469e5918d7dSYoshinori Sato TCGv mem; 470e5918d7dSYoshinori Sato mem = tcg_temp_new(); 471e5918d7dSYoshinori Sato rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 472e5918d7dSYoshinori Sato rx_gen_ld(a->sz, cpu_regs[a->rd], mem); 473e5918d7dSYoshinori Sato return true; 474e5918d7dSYoshinori Sato } 475e5918d7dSYoshinori Sato 476e5918d7dSYoshinori Sato /* mov.<bwl> rd,[ri,rb] */ 477e5918d7dSYoshinori Sato static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) 478e5918d7dSYoshinori Sato { 479e5918d7dSYoshinori Sato TCGv mem; 480e5918d7dSYoshinori Sato mem = tcg_temp_new(); 481e5918d7dSYoshinori Sato rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 482e5918d7dSYoshinori Sato rx_gen_st(a->sz, cpu_regs[a->rs], mem); 483e5918d7dSYoshinori Sato return true; 484e5918d7dSYoshinori Sato } 485e5918d7dSYoshinori Sato 486e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],dsp[rd] */ 487e5918d7dSYoshinori Sato /* mov.<bwl> rs,dsp[rd] */ 488e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],rd */ 489e5918d7dSYoshinori Sato /* mov.<bwl> rs,rd */ 490e5918d7dSYoshinori Sato static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) 491e5918d7dSYoshinori Sato { 492e5918d7dSYoshinori Sato static void (* const mov[])(TCGv ret, TCGv arg) = { 493e5918d7dSYoshinori Sato tcg_gen_ext8s_i32, tcg_gen_ext16s_i32, tcg_gen_mov_i32, 494e5918d7dSYoshinori Sato }; 495e5918d7dSYoshinori Sato TCGv tmp, mem, addr; 496e5918d7dSYoshinori Sato if (a->lds == 3 && a->ldd == 3) { 497e5918d7dSYoshinori Sato /* mov.<bwl> rs,rd */ 498e5918d7dSYoshinori Sato mov[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]); 499e5918d7dSYoshinori Sato return true; 500e5918d7dSYoshinori Sato } 501e5918d7dSYoshinori Sato 502e5918d7dSYoshinori Sato mem = tcg_temp_new(); 503e5918d7dSYoshinori Sato if (a->lds == 3) { 504e5918d7dSYoshinori Sato /* mov.<bwl> rs,dsp[rd] */ 505e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs); 506e5918d7dSYoshinori Sato rx_gen_st(a->sz, cpu_regs[a->rd], addr); 507e5918d7dSYoshinori Sato } else if (a->ldd == 3) { 508e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],rd */ 509e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 510e5918d7dSYoshinori Sato rx_gen_ld(a->sz, cpu_regs[a->rd], addr); 511e5918d7dSYoshinori Sato } else { 512e5918d7dSYoshinori Sato /* mov.<bwl> dsp[rs],dsp[rd] */ 513e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 514e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); 515e5918d7dSYoshinori Sato rx_gen_ld(a->sz, tmp, addr); 516e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); 517e5918d7dSYoshinori Sato rx_gen_st(a->sz, tmp, addr); 518e5918d7dSYoshinori Sato } 519e5918d7dSYoshinori Sato return true; 520e5918d7dSYoshinori Sato } 521e5918d7dSYoshinori Sato 522e5918d7dSYoshinori Sato /* mov.<bwl> rs,[rd+] */ 523e5918d7dSYoshinori Sato /* mov.<bwl> rs,[-rd] */ 524e5918d7dSYoshinori Sato static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) 525e5918d7dSYoshinori Sato { 526e5918d7dSYoshinori Sato TCGv val; 527e5918d7dSYoshinori Sato val = tcg_temp_new(); 528e5918d7dSYoshinori Sato tcg_gen_mov_i32(val, cpu_regs[a->rs]); 529e5918d7dSYoshinori Sato if (a->ad == 1) { 530e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 531e5918d7dSYoshinori Sato } 532e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, cpu_regs[a->rd]); 533e5918d7dSYoshinori Sato if (a->ad == 0) { 534e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 535e5918d7dSYoshinori Sato } 536e5918d7dSYoshinori Sato return true; 537e5918d7dSYoshinori Sato } 538e5918d7dSYoshinori Sato 539e5918d7dSYoshinori Sato /* mov.<bwl> [rd+],rs */ 540e5918d7dSYoshinori Sato /* mov.<bwl> [-rd],rs */ 541e5918d7dSYoshinori Sato static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) 542e5918d7dSYoshinori Sato { 543e5918d7dSYoshinori Sato TCGv val; 544e5918d7dSYoshinori Sato val = tcg_temp_new(); 545e5918d7dSYoshinori Sato if (a->ad == 1) { 546e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 547e5918d7dSYoshinori Sato } 548e5918d7dSYoshinori Sato rx_gen_ld(a->sz, val, cpu_regs[a->rd]); 549e5918d7dSYoshinori Sato if (a->ad == 0) { 550e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 551e5918d7dSYoshinori Sato } 552e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rs], val); 553e5918d7dSYoshinori Sato return true; 554e5918d7dSYoshinori Sato } 555e5918d7dSYoshinori Sato 556e5918d7dSYoshinori Sato /* movu.<bw> dsp5[rs],rd */ 557e5918d7dSYoshinori Sato /* movu.<bw> dsp[rs],rd */ 558e5918d7dSYoshinori Sato static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a) 559e5918d7dSYoshinori Sato { 560e5918d7dSYoshinori Sato TCGv mem; 561e5918d7dSYoshinori Sato mem = tcg_temp_new(); 562e5918d7dSYoshinori Sato tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); 563e5918d7dSYoshinori Sato rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 564e5918d7dSYoshinori Sato return true; 565e5918d7dSYoshinori Sato } 566e5918d7dSYoshinori Sato 567e5918d7dSYoshinori Sato /* movu.<bw> rs,rd */ 568e5918d7dSYoshinori Sato static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a) 569e5918d7dSYoshinori Sato { 570e5918d7dSYoshinori Sato static void (* const ext[])(TCGv ret, TCGv arg) = { 571e5918d7dSYoshinori Sato tcg_gen_ext8u_i32, tcg_gen_ext16u_i32, 572e5918d7dSYoshinori Sato }; 573e5918d7dSYoshinori Sato ext[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]); 574e5918d7dSYoshinori Sato return true; 575e5918d7dSYoshinori Sato } 576e5918d7dSYoshinori Sato 577e5918d7dSYoshinori Sato /* movu.<bw> [ri,rb],rd */ 578e5918d7dSYoshinori Sato static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a) 579e5918d7dSYoshinori Sato { 580e5918d7dSYoshinori Sato TCGv mem; 581e5918d7dSYoshinori Sato mem = tcg_temp_new(); 582e5918d7dSYoshinori Sato rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); 583e5918d7dSYoshinori Sato rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); 584e5918d7dSYoshinori Sato return true; 585e5918d7dSYoshinori Sato } 586e5918d7dSYoshinori Sato 587e5918d7dSYoshinori Sato /* movu.<bw> [rd+],rs */ 588e5918d7dSYoshinori Sato /* mov.<bw> [-rd],rs */ 589e5918d7dSYoshinori Sato static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) 590e5918d7dSYoshinori Sato { 591e5918d7dSYoshinori Sato TCGv val; 592e5918d7dSYoshinori Sato val = tcg_temp_new(); 593e5918d7dSYoshinori Sato if (a->ad == 1) { 594e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 595e5918d7dSYoshinori Sato } 596e5918d7dSYoshinori Sato rx_gen_ldu(a->sz, val, cpu_regs[a->rd]); 597e5918d7dSYoshinori Sato if (a->ad == 0) { 598e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); 599e5918d7dSYoshinori Sato } 600e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rs], val); 601e5918d7dSYoshinori Sato return true; 602e5918d7dSYoshinori Sato } 603e5918d7dSYoshinori Sato 604e5918d7dSYoshinori Sato 605e5918d7dSYoshinori Sato /* pop rd */ 606e5918d7dSYoshinori Sato static bool trans_POP(DisasContext *ctx, arg_POP *a) 607e5918d7dSYoshinori Sato { 608e5918d7dSYoshinori Sato /* mov.l [r0+], rd */ 609e5918d7dSYoshinori Sato arg_MOV_rp mov_a; 610e5918d7dSYoshinori Sato mov_a.rd = 0; 611e5918d7dSYoshinori Sato mov_a.rs = a->rd; 612e5918d7dSYoshinori Sato mov_a.ad = 0; 613e5918d7dSYoshinori Sato mov_a.sz = MO_32; 614e5918d7dSYoshinori Sato trans_MOV_pr(ctx, &mov_a); 615e5918d7dSYoshinori Sato return true; 616e5918d7dSYoshinori Sato } 617e5918d7dSYoshinori Sato 618e5918d7dSYoshinori Sato /* popc cr */ 619e5918d7dSYoshinori Sato static bool trans_POPC(DisasContext *ctx, arg_POPC *a) 620e5918d7dSYoshinori Sato { 621e5918d7dSYoshinori Sato TCGv val; 622e5918d7dSYoshinori Sato val = tcg_temp_new(); 623e5918d7dSYoshinori Sato pop(val); 624e5918d7dSYoshinori Sato move_to_cr(ctx, val, a->cr); 625e5918d7dSYoshinori Sato return true; 626e5918d7dSYoshinori Sato } 627e5918d7dSYoshinori Sato 628e5918d7dSYoshinori Sato /* popm rd-rd2 */ 629e5918d7dSYoshinori Sato static bool trans_POPM(DisasContext *ctx, arg_POPM *a) 630e5918d7dSYoshinori Sato { 631e5918d7dSYoshinori Sato int r; 632e5918d7dSYoshinori Sato if (a->rd == 0 || a->rd >= a->rd2) { 633e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 634e5918d7dSYoshinori Sato "Invalid register ranges r%d-r%d", a->rd, a->rd2); 635e5918d7dSYoshinori Sato } 636e5918d7dSYoshinori Sato r = a->rd; 637e5918d7dSYoshinori Sato while (r <= a->rd2 && r < 16) { 638e5918d7dSYoshinori Sato pop(cpu_regs[r++]); 639e5918d7dSYoshinori Sato } 640e5918d7dSYoshinori Sato return true; 641e5918d7dSYoshinori Sato } 642e5918d7dSYoshinori Sato 643e5918d7dSYoshinori Sato 644e5918d7dSYoshinori Sato /* push.<bwl> rs */ 645e5918d7dSYoshinori Sato static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) 646e5918d7dSYoshinori Sato { 647e5918d7dSYoshinori Sato TCGv val; 648e5918d7dSYoshinori Sato val = tcg_temp_new(); 649e5918d7dSYoshinori Sato tcg_gen_mov_i32(val, cpu_regs[a->rs]); 650e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 651e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, cpu_sp); 652e5918d7dSYoshinori Sato return true; 653e5918d7dSYoshinori Sato } 654e5918d7dSYoshinori Sato 655e5918d7dSYoshinori Sato /* push.<bwl> dsp[rs] */ 656e5918d7dSYoshinori Sato static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) 657e5918d7dSYoshinori Sato { 658e5918d7dSYoshinori Sato TCGv mem, val, addr; 659e5918d7dSYoshinori Sato mem = tcg_temp_new(); 660e5918d7dSYoshinori Sato val = tcg_temp_new(); 661e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs); 662e5918d7dSYoshinori Sato rx_gen_ld(a->sz, val, addr); 663e5918d7dSYoshinori Sato tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); 664e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, cpu_sp); 665e5918d7dSYoshinori Sato return true; 666e5918d7dSYoshinori Sato } 667e5918d7dSYoshinori Sato 668e5918d7dSYoshinori Sato /* pushc rx */ 669e5918d7dSYoshinori Sato static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) 670e5918d7dSYoshinori Sato { 671e5918d7dSYoshinori Sato TCGv val; 672e5918d7dSYoshinori Sato val = tcg_temp_new(); 6733626a3feSRichard Henderson move_from_cr(ctx, val, a->cr, ctx->pc); 674e5918d7dSYoshinori Sato push(val); 675e5918d7dSYoshinori Sato return true; 676e5918d7dSYoshinori Sato } 677e5918d7dSYoshinori Sato 678e5918d7dSYoshinori Sato /* pushm rs-rs2 */ 679e5918d7dSYoshinori Sato static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) 680e5918d7dSYoshinori Sato { 681e5918d7dSYoshinori Sato int r; 682e5918d7dSYoshinori Sato 683e5918d7dSYoshinori Sato if (a->rs == 0 || a->rs >= a->rs2) { 684e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, 685e5918d7dSYoshinori Sato "Invalid register ranges r%d-r%d", a->rs, a->rs2); 686e5918d7dSYoshinori Sato } 687e5918d7dSYoshinori Sato r = a->rs2; 688e5918d7dSYoshinori Sato while (r >= a->rs && r >= 0) { 689e5918d7dSYoshinori Sato push(cpu_regs[r--]); 690e5918d7dSYoshinori Sato } 691e5918d7dSYoshinori Sato return true; 692e5918d7dSYoshinori Sato } 693e5918d7dSYoshinori Sato 694e5918d7dSYoshinori Sato /* xchg rs,rd */ 695e5918d7dSYoshinori Sato static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) 696e5918d7dSYoshinori Sato { 697e5918d7dSYoshinori Sato TCGv tmp; 698e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 699e5918d7dSYoshinori Sato tcg_gen_mov_i32(tmp, cpu_regs[a->rs]); 700e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); 701e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rd], tmp); 702e5918d7dSYoshinori Sato return true; 703e5918d7dSYoshinori Sato } 704e5918d7dSYoshinori Sato 705e5918d7dSYoshinori Sato /* xchg dsp[rs].<mi>,rd */ 706e5918d7dSYoshinori Sato static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) 707e5918d7dSYoshinori Sato { 708e5918d7dSYoshinori Sato TCGv mem, addr; 709e5918d7dSYoshinori Sato mem = tcg_temp_new(); 710e5918d7dSYoshinori Sato switch (a->mi) { 711e5918d7dSYoshinori Sato case 0: /* dsp[rs].b */ 712e5918d7dSYoshinori Sato case 1: /* dsp[rs].w */ 713e5918d7dSYoshinori Sato case 2: /* dsp[rs].l */ 714e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, a->mi, a->rs); 715e5918d7dSYoshinori Sato break; 716e5918d7dSYoshinori Sato case 3: /* dsp[rs].uw */ 717e5918d7dSYoshinori Sato case 4: /* dsp[rs].ub */ 718e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs); 719e5918d7dSYoshinori Sato break; 720e5918d7dSYoshinori Sato default: 721e5918d7dSYoshinori Sato g_assert_not_reached(); 722e5918d7dSYoshinori Sato } 723e5918d7dSYoshinori Sato tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd], 724e5918d7dSYoshinori Sato 0, mi_to_mop(a->mi)); 725e5918d7dSYoshinori Sato return true; 726e5918d7dSYoshinori Sato } 727e5918d7dSYoshinori Sato 728e5918d7dSYoshinori Sato static inline void stcond(TCGCond cond, int rd, int imm) 729e5918d7dSYoshinori Sato { 730e5918d7dSYoshinori Sato TCGv z; 731e5918d7dSYoshinori Sato TCGv _imm; 732e5918d7dSYoshinori Sato z = tcg_const_i32(0); 733e5918d7dSYoshinori Sato _imm = tcg_const_i32(imm); 734e5918d7dSYoshinori Sato tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, 735e5918d7dSYoshinori Sato _imm, cpu_regs[rd]); 736e5918d7dSYoshinori Sato } 737e5918d7dSYoshinori Sato 738e5918d7dSYoshinori Sato /* stz #imm,rd */ 739e5918d7dSYoshinori Sato static bool trans_STZ(DisasContext *ctx, arg_STZ *a) 740e5918d7dSYoshinori Sato { 741e5918d7dSYoshinori Sato stcond(TCG_COND_EQ, a->rd, a->imm); 742e5918d7dSYoshinori Sato return true; 743e5918d7dSYoshinori Sato } 744e5918d7dSYoshinori Sato 745e5918d7dSYoshinori Sato /* stnz #imm,rd */ 746e5918d7dSYoshinori Sato static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a) 747e5918d7dSYoshinori Sato { 748e5918d7dSYoshinori Sato stcond(TCG_COND_NE, a->rd, a->imm); 749e5918d7dSYoshinori Sato return true; 750e5918d7dSYoshinori Sato } 751e5918d7dSYoshinori Sato 752e5918d7dSYoshinori Sato /* sccnd.<bwl> rd */ 753e5918d7dSYoshinori Sato /* sccnd.<bwl> dsp:[rd] */ 754e5918d7dSYoshinori Sato static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) 755e5918d7dSYoshinori Sato { 756e5918d7dSYoshinori Sato DisasCompare dc; 757e5918d7dSYoshinori Sato TCGv val, mem, addr; 758e5918d7dSYoshinori Sato dc.temp = tcg_temp_new(); 759e5918d7dSYoshinori Sato psw_cond(&dc, a->cd); 760e5918d7dSYoshinori Sato if (a->ld < 3) { 761e5918d7dSYoshinori Sato val = tcg_temp_new(); 762e5918d7dSYoshinori Sato mem = tcg_temp_new(); 763e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0); 764e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); 765e5918d7dSYoshinori Sato rx_gen_st(a->sz, val, addr); 766e5918d7dSYoshinori Sato } else { 767e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); 768e5918d7dSYoshinori Sato } 769e5918d7dSYoshinori Sato return true; 770e5918d7dSYoshinori Sato } 771e5918d7dSYoshinori Sato 772e5918d7dSYoshinori Sato /* rtsd #imm */ 773e5918d7dSYoshinori Sato static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a) 774e5918d7dSYoshinori Sato { 775e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2); 776e5918d7dSYoshinori Sato pop(cpu_pc); 777e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 778e5918d7dSYoshinori Sato return true; 779e5918d7dSYoshinori Sato } 780e5918d7dSYoshinori Sato 781e5918d7dSYoshinori Sato /* rtsd #imm, rd-rd2 */ 782e5918d7dSYoshinori Sato static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a) 783e5918d7dSYoshinori Sato { 784e5918d7dSYoshinori Sato int dst; 785e5918d7dSYoshinori Sato int adj; 786e5918d7dSYoshinori Sato 787e5918d7dSYoshinori Sato if (a->rd2 >= a->rd) { 788e5918d7dSYoshinori Sato adj = a->imm - (a->rd2 - a->rd + 1); 789e5918d7dSYoshinori Sato } else { 790e5918d7dSYoshinori Sato adj = a->imm - (15 - a->rd + 1); 791e5918d7dSYoshinori Sato } 792e5918d7dSYoshinori Sato 793e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_sp, cpu_sp, adj << 2); 794e5918d7dSYoshinori Sato dst = a->rd; 795e5918d7dSYoshinori Sato while (dst <= a->rd2 && dst < 16) { 796e5918d7dSYoshinori Sato pop(cpu_regs[dst++]); 797e5918d7dSYoshinori Sato } 798e5918d7dSYoshinori Sato pop(cpu_pc); 799e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 800e5918d7dSYoshinori Sato return true; 801e5918d7dSYoshinori Sato } 802e5918d7dSYoshinori Sato 803e5918d7dSYoshinori Sato typedef void (*op2fn)(TCGv ret, TCGv arg1); 804e5918d7dSYoshinori Sato typedef void (*op3fn)(TCGv ret, TCGv arg1, TCGv arg2); 805e5918d7dSYoshinori Sato 806e5918d7dSYoshinori Sato static inline void rx_gen_op_rr(op2fn opr, int dst, int src) 807e5918d7dSYoshinori Sato { 808e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[src]); 809e5918d7dSYoshinori Sato } 810e5918d7dSYoshinori Sato 811e5918d7dSYoshinori Sato static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2) 812e5918d7dSYoshinori Sato { 813e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[src], cpu_regs[src2]); 814e5918d7dSYoshinori Sato } 815e5918d7dSYoshinori Sato 816e5918d7dSYoshinori Sato static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2) 817e5918d7dSYoshinori Sato { 818e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(src2); 819e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[src], imm); 820e5918d7dSYoshinori Sato } 821e5918d7dSYoshinori Sato 822e5918d7dSYoshinori Sato static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx, 823e5918d7dSYoshinori Sato int dst, int src, int ld, int mi) 824e5918d7dSYoshinori Sato { 825e5918d7dSYoshinori Sato TCGv val, mem; 826e5918d7dSYoshinori Sato mem = tcg_temp_new(); 827e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, ld, mi, src); 828e5918d7dSYoshinori Sato opr(cpu_regs[dst], cpu_regs[dst], val); 829e5918d7dSYoshinori Sato } 830e5918d7dSYoshinori Sato 831e5918d7dSYoshinori Sato static void rx_and(TCGv ret, TCGv arg1, TCGv arg2) 832e5918d7dSYoshinori Sato { 833e5918d7dSYoshinori Sato tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 834e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 835e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 836e5918d7dSYoshinori Sato } 837e5918d7dSYoshinori Sato 838e5918d7dSYoshinori Sato /* and #uimm:4, rd */ 839e5918d7dSYoshinori Sato /* and #imm, rd */ 840e5918d7dSYoshinori Sato static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a) 841e5918d7dSYoshinori Sato { 842e5918d7dSYoshinori Sato rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm); 843e5918d7dSYoshinori Sato return true; 844e5918d7dSYoshinori Sato } 845e5918d7dSYoshinori Sato 846e5918d7dSYoshinori Sato /* and dsp[rs], rd */ 847e5918d7dSYoshinori Sato /* and rs,rd */ 848e5918d7dSYoshinori Sato static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a) 849e5918d7dSYoshinori Sato { 850e5918d7dSYoshinori Sato rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi); 851e5918d7dSYoshinori Sato return true; 852e5918d7dSYoshinori Sato } 853e5918d7dSYoshinori Sato 854e5918d7dSYoshinori Sato /* and rs,rs2,rd */ 855e5918d7dSYoshinori Sato static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a) 856e5918d7dSYoshinori Sato { 857e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2); 858e5918d7dSYoshinori Sato return true; 859e5918d7dSYoshinori Sato } 860e5918d7dSYoshinori Sato 861e5918d7dSYoshinori Sato static void rx_or(TCGv ret, TCGv arg1, TCGv arg2) 862e5918d7dSYoshinori Sato { 863e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_psw_s, arg1, arg2); 864e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 865e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 866e5918d7dSYoshinori Sato } 867e5918d7dSYoshinori Sato 868e5918d7dSYoshinori Sato /* or #uimm:4, rd */ 869e5918d7dSYoshinori Sato /* or #imm, rd */ 870e5918d7dSYoshinori Sato static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a) 871e5918d7dSYoshinori Sato { 872e5918d7dSYoshinori Sato rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm); 873e5918d7dSYoshinori Sato return true; 874e5918d7dSYoshinori Sato } 875e5918d7dSYoshinori Sato 876e5918d7dSYoshinori Sato /* or dsp[rs], rd */ 877e5918d7dSYoshinori Sato /* or rs,rd */ 878e5918d7dSYoshinori Sato static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a) 879e5918d7dSYoshinori Sato { 880e5918d7dSYoshinori Sato rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi); 881e5918d7dSYoshinori Sato return true; 882e5918d7dSYoshinori Sato } 883e5918d7dSYoshinori Sato 884e5918d7dSYoshinori Sato /* or rs,rs2,rd */ 885e5918d7dSYoshinori Sato static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a) 886e5918d7dSYoshinori Sato { 887e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2); 888e5918d7dSYoshinori Sato return true; 889e5918d7dSYoshinori Sato } 890e5918d7dSYoshinori Sato 891e5918d7dSYoshinori Sato static void rx_xor(TCGv ret, TCGv arg1, TCGv arg2) 892e5918d7dSYoshinori Sato { 893e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_s, arg1, arg2); 894e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 895e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 896e5918d7dSYoshinori Sato } 897e5918d7dSYoshinori Sato 898e5918d7dSYoshinori Sato /* xor #imm, rd */ 899e5918d7dSYoshinori Sato static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a) 900e5918d7dSYoshinori Sato { 901e5918d7dSYoshinori Sato rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm); 902e5918d7dSYoshinori Sato return true; 903e5918d7dSYoshinori Sato } 904e5918d7dSYoshinori Sato 905e5918d7dSYoshinori Sato /* xor dsp[rs], rd */ 906e5918d7dSYoshinori Sato /* xor rs,rd */ 907e5918d7dSYoshinori Sato static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a) 908e5918d7dSYoshinori Sato { 909e5918d7dSYoshinori Sato rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi); 910e5918d7dSYoshinori Sato return true; 911e5918d7dSYoshinori Sato } 912e5918d7dSYoshinori Sato 913e5918d7dSYoshinori Sato static void rx_tst(TCGv ret, TCGv arg1, TCGv arg2) 914e5918d7dSYoshinori Sato { 915e5918d7dSYoshinori Sato tcg_gen_and_i32(cpu_psw_s, arg1, arg2); 916e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 917e5918d7dSYoshinori Sato } 918e5918d7dSYoshinori Sato 919e5918d7dSYoshinori Sato /* tst #imm, rd */ 920e5918d7dSYoshinori Sato static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a) 921e5918d7dSYoshinori Sato { 922e5918d7dSYoshinori Sato rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm); 923e5918d7dSYoshinori Sato return true; 924e5918d7dSYoshinori Sato } 925e5918d7dSYoshinori Sato 926e5918d7dSYoshinori Sato /* tst dsp[rs], rd */ 927e5918d7dSYoshinori Sato /* tst rs, rd */ 928e5918d7dSYoshinori Sato static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a) 929e5918d7dSYoshinori Sato { 930e5918d7dSYoshinori Sato rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi); 931e5918d7dSYoshinori Sato return true; 932e5918d7dSYoshinori Sato } 933e5918d7dSYoshinori Sato 934e5918d7dSYoshinori Sato static void rx_not(TCGv ret, TCGv arg1) 935e5918d7dSYoshinori Sato { 936e5918d7dSYoshinori Sato tcg_gen_not_i32(ret, arg1); 937e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, ret); 938e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, ret); 939e5918d7dSYoshinori Sato } 940e5918d7dSYoshinori Sato 941e5918d7dSYoshinori Sato /* not rd */ 942e5918d7dSYoshinori Sato /* not rs, rd */ 943e5918d7dSYoshinori Sato static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a) 944e5918d7dSYoshinori Sato { 945e5918d7dSYoshinori Sato rx_gen_op_rr(rx_not, a->rd, a->rs); 946e5918d7dSYoshinori Sato return true; 947e5918d7dSYoshinori Sato } 948e5918d7dSYoshinori Sato 949e5918d7dSYoshinori Sato static void rx_neg(TCGv ret, TCGv arg1) 950e5918d7dSYoshinori Sato { 951e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000); 952e5918d7dSYoshinori Sato tcg_gen_neg_i32(ret, arg1); 953e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, ret, 0); 954e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, ret); 955e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, ret); 956e5918d7dSYoshinori Sato } 957e5918d7dSYoshinori Sato 958e5918d7dSYoshinori Sato 959e5918d7dSYoshinori Sato /* neg rd */ 960e5918d7dSYoshinori Sato /* neg rs, rd */ 961e5918d7dSYoshinori Sato static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) 962e5918d7dSYoshinori Sato { 963e5918d7dSYoshinori Sato rx_gen_op_rr(rx_neg, a->rd, a->rs); 964e5918d7dSYoshinori Sato return true; 965e5918d7dSYoshinori Sato } 966e5918d7dSYoshinori Sato 967e5918d7dSYoshinori Sato /* ret = arg1 + arg2 + psw_c */ 968e5918d7dSYoshinori Sato static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) 969e5918d7dSYoshinori Sato { 970bb09b540SRichard Henderson TCGv z = tcg_constant_i32(0); 971e5918d7dSYoshinori Sato tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); 972e5918d7dSYoshinori Sato tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); 973e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 974bb09b540SRichard Henderson tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); 975bb09b540SRichard Henderson tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); 976bb09b540SRichard Henderson tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 977e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 978e5918d7dSYoshinori Sato } 979e5918d7dSYoshinori Sato 980e5918d7dSYoshinori Sato /* adc #imm, rd */ 981e5918d7dSYoshinori Sato static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a) 982e5918d7dSYoshinori Sato { 983e5918d7dSYoshinori Sato rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm); 984e5918d7dSYoshinori Sato return true; 985e5918d7dSYoshinori Sato } 986e5918d7dSYoshinori Sato 987e5918d7dSYoshinori Sato /* adc rs, rd */ 988e5918d7dSYoshinori Sato static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a) 989e5918d7dSYoshinori Sato { 990e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs); 991e5918d7dSYoshinori Sato return true; 992e5918d7dSYoshinori Sato } 993e5918d7dSYoshinori Sato 994e5918d7dSYoshinori Sato /* adc dsp[rs], rd */ 995e5918d7dSYoshinori Sato static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) 996e5918d7dSYoshinori Sato { 997e5918d7dSYoshinori Sato /* mi only 2 */ 998e5918d7dSYoshinori Sato if (a->mi != 2) { 999e5918d7dSYoshinori Sato return false; 1000e5918d7dSYoshinori Sato } 1001e5918d7dSYoshinori Sato rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi); 1002e5918d7dSYoshinori Sato return true; 1003e5918d7dSYoshinori Sato } 1004e5918d7dSYoshinori Sato 1005e5918d7dSYoshinori Sato /* ret = arg1 + arg2 */ 1006e5918d7dSYoshinori Sato static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) 1007e5918d7dSYoshinori Sato { 1008bb09b540SRichard Henderson TCGv z = tcg_constant_i32(0); 1009e5918d7dSYoshinori Sato tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); 1010e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1011bb09b540SRichard Henderson tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); 1012bb09b540SRichard Henderson tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); 1013bb09b540SRichard Henderson tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 1014e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 1015e5918d7dSYoshinori Sato } 1016e5918d7dSYoshinori Sato 1017e5918d7dSYoshinori Sato /* add #uimm4, rd */ 1018e5918d7dSYoshinori Sato /* add #imm, rs, rd */ 1019e5918d7dSYoshinori Sato static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a) 1020e5918d7dSYoshinori Sato { 1021e5918d7dSYoshinori Sato rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm); 1022e5918d7dSYoshinori Sato return true; 1023e5918d7dSYoshinori Sato } 1024e5918d7dSYoshinori Sato 1025e5918d7dSYoshinori Sato /* add rs, rd */ 1026e5918d7dSYoshinori Sato /* add dsp[rs], rd */ 1027e5918d7dSYoshinori Sato static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a) 1028e5918d7dSYoshinori Sato { 1029e5918d7dSYoshinori Sato rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi); 1030e5918d7dSYoshinori Sato return true; 1031e5918d7dSYoshinori Sato } 1032e5918d7dSYoshinori Sato 1033e5918d7dSYoshinori Sato /* add rs, rs2, rd */ 1034e5918d7dSYoshinori Sato static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a) 1035e5918d7dSYoshinori Sato { 1036e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2); 1037e5918d7dSYoshinori Sato return true; 1038e5918d7dSYoshinori Sato } 1039e5918d7dSYoshinori Sato 1040e5918d7dSYoshinori Sato /* ret = arg1 - arg2 */ 1041e5918d7dSYoshinori Sato static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) 1042e5918d7dSYoshinori Sato { 1043e5918d7dSYoshinori Sato tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); 1044e5918d7dSYoshinori Sato tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); 1045e5918d7dSYoshinori Sato tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); 1046bb09b540SRichard Henderson tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); 1047bb09b540SRichard Henderson tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); 1048bb09b540SRichard Henderson tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); 104997841438SLichang Zhao /* CMP not required return */ 1050e5918d7dSYoshinori Sato if (ret) { 1051e5918d7dSYoshinori Sato tcg_gen_mov_i32(ret, cpu_psw_s); 1052e5918d7dSYoshinori Sato } 1053e5918d7dSYoshinori Sato } 1054bb09b540SRichard Henderson 1055e5918d7dSYoshinori Sato static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2) 1056e5918d7dSYoshinori Sato { 1057e5918d7dSYoshinori Sato rx_sub(NULL, arg1, arg2); 1058e5918d7dSYoshinori Sato } 1059bb09b540SRichard Henderson 1060e5918d7dSYoshinori Sato /* ret = arg1 - arg2 - !psw_c */ 1061e5918d7dSYoshinori Sato /* -> ret = arg1 + ~arg2 + psw_c */ 1062e5918d7dSYoshinori Sato static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) 1063e5918d7dSYoshinori Sato { 1064e5918d7dSYoshinori Sato TCGv temp; 1065e5918d7dSYoshinori Sato temp = tcg_temp_new(); 1066e5918d7dSYoshinori Sato tcg_gen_not_i32(temp, arg2); 1067e5918d7dSYoshinori Sato rx_adc(ret, arg1, temp); 1068e5918d7dSYoshinori Sato } 1069e5918d7dSYoshinori Sato 1070e5918d7dSYoshinori Sato /* cmp #imm4, rs2 */ 1071e5918d7dSYoshinori Sato /* cmp #imm8, rs2 */ 1072e5918d7dSYoshinori Sato /* cmp #imm, rs2 */ 1073e5918d7dSYoshinori Sato static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a) 1074e5918d7dSYoshinori Sato { 1075e5918d7dSYoshinori Sato rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm); 1076e5918d7dSYoshinori Sato return true; 1077e5918d7dSYoshinori Sato } 1078e5918d7dSYoshinori Sato 1079e5918d7dSYoshinori Sato /* cmp rs, rs2 */ 1080e5918d7dSYoshinori Sato /* cmp dsp[rs], rs2 */ 1081e5918d7dSYoshinori Sato static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a) 1082e5918d7dSYoshinori Sato { 1083e5918d7dSYoshinori Sato rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi); 1084e5918d7dSYoshinori Sato return true; 1085e5918d7dSYoshinori Sato } 1086e5918d7dSYoshinori Sato 1087e5918d7dSYoshinori Sato /* sub #imm4, rd */ 1088e5918d7dSYoshinori Sato static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a) 1089e5918d7dSYoshinori Sato { 1090e5918d7dSYoshinori Sato rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm); 1091e5918d7dSYoshinori Sato return true; 1092e5918d7dSYoshinori Sato } 1093e5918d7dSYoshinori Sato 1094e5918d7dSYoshinori Sato /* sub rs, rd */ 1095e5918d7dSYoshinori Sato /* sub dsp[rs], rd */ 1096e5918d7dSYoshinori Sato static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a) 1097e5918d7dSYoshinori Sato { 1098e5918d7dSYoshinori Sato rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi); 1099e5918d7dSYoshinori Sato return true; 1100e5918d7dSYoshinori Sato } 1101e5918d7dSYoshinori Sato 1102e5918d7dSYoshinori Sato /* sub rs2, rs, rd */ 1103e5918d7dSYoshinori Sato static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a) 1104e5918d7dSYoshinori Sato { 1105e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs); 1106e5918d7dSYoshinori Sato return true; 1107e5918d7dSYoshinori Sato } 1108e5918d7dSYoshinori Sato 1109e5918d7dSYoshinori Sato /* sbb rs, rd */ 1110e5918d7dSYoshinori Sato static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a) 1111e5918d7dSYoshinori Sato { 1112e5918d7dSYoshinori Sato rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs); 1113e5918d7dSYoshinori Sato return true; 1114e5918d7dSYoshinori Sato } 1115e5918d7dSYoshinori Sato 1116e5918d7dSYoshinori Sato /* sbb dsp[rs], rd */ 1117e5918d7dSYoshinori Sato static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) 1118e5918d7dSYoshinori Sato { 1119e5918d7dSYoshinori Sato /* mi only 2 */ 1120e5918d7dSYoshinori Sato if (a->mi != 2) { 1121e5918d7dSYoshinori Sato return false; 1122e5918d7dSYoshinori Sato } 1123e5918d7dSYoshinori Sato rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi); 1124e5918d7dSYoshinori Sato return true; 1125e5918d7dSYoshinori Sato } 1126e5918d7dSYoshinori Sato 1127e5918d7dSYoshinori Sato /* abs rd */ 1128e5918d7dSYoshinori Sato /* abs rs, rd */ 1129e5918d7dSYoshinori Sato static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) 1130e5918d7dSYoshinori Sato { 11314b01ff25SRichard Henderson rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs); 1132e5918d7dSYoshinori Sato return true; 1133e5918d7dSYoshinori Sato } 1134e5918d7dSYoshinori Sato 1135e5918d7dSYoshinori Sato /* max #imm, rd */ 1136e5918d7dSYoshinori Sato static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a) 1137e5918d7dSYoshinori Sato { 1138e5918d7dSYoshinori Sato rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm); 1139e5918d7dSYoshinori Sato return true; 1140e5918d7dSYoshinori Sato } 1141e5918d7dSYoshinori Sato 1142e5918d7dSYoshinori Sato /* max rs, rd */ 1143e5918d7dSYoshinori Sato /* max dsp[rs], rd */ 1144e5918d7dSYoshinori Sato static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a) 1145e5918d7dSYoshinori Sato { 1146e5918d7dSYoshinori Sato rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1147e5918d7dSYoshinori Sato return true; 1148e5918d7dSYoshinori Sato } 1149e5918d7dSYoshinori Sato 1150e5918d7dSYoshinori Sato /* min #imm, rd */ 1151e5918d7dSYoshinori Sato static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a) 1152e5918d7dSYoshinori Sato { 1153e5918d7dSYoshinori Sato rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm); 1154e5918d7dSYoshinori Sato return true; 1155e5918d7dSYoshinori Sato } 1156e5918d7dSYoshinori Sato 1157e5918d7dSYoshinori Sato /* min rs, rd */ 1158e5918d7dSYoshinori Sato /* min dsp[rs], rd */ 1159e5918d7dSYoshinori Sato static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a) 1160e5918d7dSYoshinori Sato { 1161e5918d7dSYoshinori Sato rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1162e5918d7dSYoshinori Sato return true; 1163e5918d7dSYoshinori Sato } 1164e5918d7dSYoshinori Sato 1165e5918d7dSYoshinori Sato /* mul #uimm4, rd */ 1166e5918d7dSYoshinori Sato /* mul #imm, rd */ 1167e5918d7dSYoshinori Sato static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a) 1168e5918d7dSYoshinori Sato { 1169e5918d7dSYoshinori Sato rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm); 1170e5918d7dSYoshinori Sato return true; 1171e5918d7dSYoshinori Sato } 1172e5918d7dSYoshinori Sato 1173e5918d7dSYoshinori Sato /* mul rs, rd */ 1174e5918d7dSYoshinori Sato /* mul dsp[rs], rd */ 1175e5918d7dSYoshinori Sato static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a) 1176e5918d7dSYoshinori Sato { 1177e5918d7dSYoshinori Sato rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi); 1178e5918d7dSYoshinori Sato return true; 1179e5918d7dSYoshinori Sato } 1180e5918d7dSYoshinori Sato 1181e5918d7dSYoshinori Sato /* mul rs, rs2, rd */ 1182e5918d7dSYoshinori Sato static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a) 1183e5918d7dSYoshinori Sato { 1184e5918d7dSYoshinori Sato rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2); 1185e5918d7dSYoshinori Sato return true; 1186e5918d7dSYoshinori Sato } 1187e5918d7dSYoshinori Sato 1188e5918d7dSYoshinori Sato /* emul #imm, rd */ 1189e5918d7dSYoshinori Sato static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) 1190e5918d7dSYoshinori Sato { 1191e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(a->imm); 1192e5918d7dSYoshinori Sato if (a->rd > 14) { 1193e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1194e5918d7dSYoshinori Sato } 1195e5918d7dSYoshinori Sato tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1196e5918d7dSYoshinori Sato cpu_regs[a->rd], imm); 1197e5918d7dSYoshinori Sato return true; 1198e5918d7dSYoshinori Sato } 1199e5918d7dSYoshinori Sato 1200e5918d7dSYoshinori Sato /* emul rs, rd */ 1201e5918d7dSYoshinori Sato /* emul dsp[rs], rd */ 1202e5918d7dSYoshinori Sato static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) 1203e5918d7dSYoshinori Sato { 1204e5918d7dSYoshinori Sato TCGv val, mem; 1205e5918d7dSYoshinori Sato if (a->rd > 14) { 1206e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1207e5918d7dSYoshinori Sato } 1208e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1209e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1210e5918d7dSYoshinori Sato tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1211e5918d7dSYoshinori Sato cpu_regs[a->rd], val); 1212e5918d7dSYoshinori Sato return true; 1213e5918d7dSYoshinori Sato } 1214e5918d7dSYoshinori Sato 1215e5918d7dSYoshinori Sato /* emulu #imm, rd */ 1216e5918d7dSYoshinori Sato static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) 1217e5918d7dSYoshinori Sato { 1218e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(a->imm); 1219e5918d7dSYoshinori Sato if (a->rd > 14) { 1220e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1221e5918d7dSYoshinori Sato } 1222e5918d7dSYoshinori Sato tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1223e5918d7dSYoshinori Sato cpu_regs[a->rd], imm); 1224e5918d7dSYoshinori Sato return true; 1225e5918d7dSYoshinori Sato } 1226e5918d7dSYoshinori Sato 1227e5918d7dSYoshinori Sato /* emulu rs, rd */ 1228e5918d7dSYoshinori Sato /* emulu dsp[rs], rd */ 1229e5918d7dSYoshinori Sato static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) 1230e5918d7dSYoshinori Sato { 1231e5918d7dSYoshinori Sato TCGv val, mem; 1232e5918d7dSYoshinori Sato if (a->rd > 14) { 1233e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); 1234e5918d7dSYoshinori Sato } 1235e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1236e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1237e5918d7dSYoshinori Sato tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], 1238e5918d7dSYoshinori Sato cpu_regs[a->rd], val); 1239e5918d7dSYoshinori Sato return true; 1240e5918d7dSYoshinori Sato } 1241e5918d7dSYoshinori Sato 1242e5918d7dSYoshinori Sato static void rx_div(TCGv ret, TCGv arg1, TCGv arg2) 1243e5918d7dSYoshinori Sato { 1244e5918d7dSYoshinori Sato gen_helper_div(ret, cpu_env, arg1, arg2); 1245e5918d7dSYoshinori Sato } 1246e5918d7dSYoshinori Sato 1247e5918d7dSYoshinori Sato static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2) 1248e5918d7dSYoshinori Sato { 1249e5918d7dSYoshinori Sato gen_helper_divu(ret, cpu_env, arg1, arg2); 1250e5918d7dSYoshinori Sato } 1251e5918d7dSYoshinori Sato 1252e5918d7dSYoshinori Sato /* div #imm, rd */ 1253e5918d7dSYoshinori Sato static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a) 1254e5918d7dSYoshinori Sato { 1255e5918d7dSYoshinori Sato rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm); 1256e5918d7dSYoshinori Sato return true; 1257e5918d7dSYoshinori Sato } 1258e5918d7dSYoshinori Sato 1259e5918d7dSYoshinori Sato /* div rs, rd */ 1260e5918d7dSYoshinori Sato /* div dsp[rs], rd */ 1261e5918d7dSYoshinori Sato static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a) 1262e5918d7dSYoshinori Sato { 1263e5918d7dSYoshinori Sato rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi); 1264e5918d7dSYoshinori Sato return true; 1265e5918d7dSYoshinori Sato } 1266e5918d7dSYoshinori Sato 1267e5918d7dSYoshinori Sato /* divu #imm, rd */ 1268e5918d7dSYoshinori Sato static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a) 1269e5918d7dSYoshinori Sato { 1270e5918d7dSYoshinori Sato rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm); 1271e5918d7dSYoshinori Sato return true; 1272e5918d7dSYoshinori Sato } 1273e5918d7dSYoshinori Sato 1274e5918d7dSYoshinori Sato /* divu rs, rd */ 1275e5918d7dSYoshinori Sato /* divu dsp[rs], rd */ 1276e5918d7dSYoshinori Sato static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a) 1277e5918d7dSYoshinori Sato { 1278e5918d7dSYoshinori Sato rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi); 1279e5918d7dSYoshinori Sato return true; 1280e5918d7dSYoshinori Sato } 1281e5918d7dSYoshinori Sato 1282e5918d7dSYoshinori Sato 1283e5918d7dSYoshinori Sato /* shll #imm:5, rd */ 1284e5918d7dSYoshinori Sato /* shll #imm:5, rs2, rd */ 1285e5918d7dSYoshinori Sato static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) 1286e5918d7dSYoshinori Sato { 1287e5918d7dSYoshinori Sato TCGv tmp; 1288e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1289e5918d7dSYoshinori Sato if (a->imm) { 1290e5918d7dSYoshinori Sato tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm); 1291e5918d7dSYoshinori Sato tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm); 1292e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1293e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1294e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1295e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1296e5918d7dSYoshinori Sato } else { 1297e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]); 1298e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1299e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1300e5918d7dSYoshinori Sato } 1301e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1302e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1303e5918d7dSYoshinori Sato return true; 1304e5918d7dSYoshinori Sato } 1305e5918d7dSYoshinori Sato 1306e5918d7dSYoshinori Sato /* shll rs, rd */ 1307e5918d7dSYoshinori Sato static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) 1308e5918d7dSYoshinori Sato { 1309e5918d7dSYoshinori Sato TCGLabel *noshift, *done; 1310e5918d7dSYoshinori Sato TCGv count, tmp; 1311e5918d7dSYoshinori Sato 1312e5918d7dSYoshinori Sato noshift = gen_new_label(); 1313e5918d7dSYoshinori Sato done = gen_new_label(); 1314e5918d7dSYoshinori Sato /* if (cpu_regs[a->rs]) { */ 1315e5918d7dSYoshinori Sato tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); 1316*09374ee2SRichard Henderson count = tcg_temp_new(); 1317e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1318e5918d7dSYoshinori Sato tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); 1319*09374ee2SRichard Henderson tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp); 1320e5918d7dSYoshinori Sato tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); 1321e5918d7dSYoshinori Sato tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1322e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); 1323e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); 1324e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); 1325e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); 1326e5918d7dSYoshinori Sato tcg_gen_br(done); 1327e5918d7dSYoshinori Sato /* } else { */ 1328e5918d7dSYoshinori Sato gen_set_label(noshift); 1329e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1330e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1331e5918d7dSYoshinori Sato /* } */ 1332e5918d7dSYoshinori Sato gen_set_label(done); 1333e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1334e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1335e5918d7dSYoshinori Sato return true; 1336e5918d7dSYoshinori Sato } 1337e5918d7dSYoshinori Sato 1338e5918d7dSYoshinori Sato static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm, 1339e5918d7dSYoshinori Sato unsigned int alith) 1340e5918d7dSYoshinori Sato { 1341e5918d7dSYoshinori Sato static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1342e5918d7dSYoshinori Sato tcg_gen_shri_i32, tcg_gen_sari_i32, 1343e5918d7dSYoshinori Sato }; 1344e5918d7dSYoshinori Sato tcg_debug_assert(alith < 2); 1345e5918d7dSYoshinori Sato if (imm) { 1346e5918d7dSYoshinori Sato gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1); 1347e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1348e5918d7dSYoshinori Sato gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1349e5918d7dSYoshinori Sato } else { 1350e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_regs[rd], cpu_regs[rs]); 1351e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1352e5918d7dSYoshinori Sato } 1353e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1354e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1355e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1356e5918d7dSYoshinori Sato } 1357e5918d7dSYoshinori Sato 1358e5918d7dSYoshinori Sato static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith) 1359e5918d7dSYoshinori Sato { 1360e5918d7dSYoshinori Sato TCGLabel *noshift, *done; 1361e5918d7dSYoshinori Sato TCGv count; 1362e5918d7dSYoshinori Sato static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = { 1363e5918d7dSYoshinori Sato tcg_gen_shri_i32, tcg_gen_sari_i32, 1364e5918d7dSYoshinori Sato }; 1365e5918d7dSYoshinori Sato static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) = { 1366e5918d7dSYoshinori Sato tcg_gen_shr_i32, tcg_gen_sar_i32, 1367e5918d7dSYoshinori Sato }; 1368e5918d7dSYoshinori Sato tcg_debug_assert(alith < 2); 1369e5918d7dSYoshinori Sato noshift = gen_new_label(); 1370e5918d7dSYoshinori Sato done = gen_new_label(); 1371e5918d7dSYoshinori Sato count = tcg_temp_new(); 1372e5918d7dSYoshinori Sato /* if (cpu_regs[rs]) { */ 1373e5918d7dSYoshinori Sato tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[rs], 0, noshift); 1374e5918d7dSYoshinori Sato tcg_gen_andi_i32(count, cpu_regs[rs], 31); 1375e5918d7dSYoshinori Sato tcg_gen_subi_i32(count, count, 1); 1376e5918d7dSYoshinori Sato gen_sXr[alith](cpu_regs[rd], cpu_regs[rd], count); 1377e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1378e5918d7dSYoshinori Sato gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); 1379e5918d7dSYoshinori Sato tcg_gen_br(done); 1380e5918d7dSYoshinori Sato /* } else { */ 1381e5918d7dSYoshinori Sato gen_set_label(noshift); 1382e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, 0); 1383e5918d7dSYoshinori Sato /* } */ 1384e5918d7dSYoshinori Sato gen_set_label(done); 1385e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, 0); 1386e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1387e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1388e5918d7dSYoshinori Sato } 1389e5918d7dSYoshinori Sato 1390e5918d7dSYoshinori Sato /* shar #imm:5, rd */ 1391e5918d7dSYoshinori Sato /* shar #imm:5, rs2, rd */ 1392e5918d7dSYoshinori Sato static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a) 1393e5918d7dSYoshinori Sato { 1394e5918d7dSYoshinori Sato shiftr_imm(a->rd, a->rs2, a->imm, 1); 1395e5918d7dSYoshinori Sato return true; 1396e5918d7dSYoshinori Sato } 1397e5918d7dSYoshinori Sato 1398e5918d7dSYoshinori Sato /* shar rs, rd */ 1399e5918d7dSYoshinori Sato static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a) 1400e5918d7dSYoshinori Sato { 1401e5918d7dSYoshinori Sato shiftr_reg(a->rd, a->rs, 1); 1402e5918d7dSYoshinori Sato return true; 1403e5918d7dSYoshinori Sato } 1404e5918d7dSYoshinori Sato 1405e5918d7dSYoshinori Sato /* shlr #imm:5, rd */ 1406e5918d7dSYoshinori Sato /* shlr #imm:5, rs2, rd */ 1407e5918d7dSYoshinori Sato static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a) 1408e5918d7dSYoshinori Sato { 1409e5918d7dSYoshinori Sato shiftr_imm(a->rd, a->rs2, a->imm, 0); 1410e5918d7dSYoshinori Sato return true; 1411e5918d7dSYoshinori Sato } 1412e5918d7dSYoshinori Sato 1413e5918d7dSYoshinori Sato /* shlr rs, rd */ 1414e5918d7dSYoshinori Sato static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a) 1415e5918d7dSYoshinori Sato { 1416e5918d7dSYoshinori Sato shiftr_reg(a->rd, a->rs, 0); 1417e5918d7dSYoshinori Sato return true; 1418e5918d7dSYoshinori Sato } 1419e5918d7dSYoshinori Sato 1420e5918d7dSYoshinori Sato /* rolc rd */ 1421e5918d7dSYoshinori Sato static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) 1422e5918d7dSYoshinori Sato { 1423e5918d7dSYoshinori Sato TCGv tmp; 1424e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1425e5918d7dSYoshinori Sato tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31); 1426e5918d7dSYoshinori Sato tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1427e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1428e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_c, tmp); 1429e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1430e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1431e5918d7dSYoshinori Sato return true; 1432e5918d7dSYoshinori Sato } 1433e5918d7dSYoshinori Sato 1434e5918d7dSYoshinori Sato /* rorc rd */ 1435e5918d7dSYoshinori Sato static bool trans_RORC(DisasContext *ctx, arg_RORC *a) 1436e5918d7dSYoshinori Sato { 1437e5918d7dSYoshinori Sato TCGv tmp; 1438e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1439e5918d7dSYoshinori Sato tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); 1440e5918d7dSYoshinori Sato tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); 1441e5918d7dSYoshinori Sato tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, 31); 1442e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); 1443e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_c, tmp); 1444e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); 1445e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); 1446e5918d7dSYoshinori Sato return true; 1447e5918d7dSYoshinori Sato } 1448e5918d7dSYoshinori Sato 1449e5918d7dSYoshinori Sato enum {ROTR = 0, ROTL = 1}; 1450e5918d7dSYoshinori Sato enum {ROT_IMM = 0, ROT_REG = 1}; 1451e5918d7dSYoshinori Sato static inline void rx_rot(int ir, int dir, int rd, int src) 1452e5918d7dSYoshinori Sato { 1453e5918d7dSYoshinori Sato switch (dir) { 1454e5918d7dSYoshinori Sato case ROTL: 1455e5918d7dSYoshinori Sato if (ir == ROT_IMM) { 1456e5918d7dSYoshinori Sato tcg_gen_rotli_i32(cpu_regs[rd], cpu_regs[rd], src); 1457e5918d7dSYoshinori Sato } else { 1458e5918d7dSYoshinori Sato tcg_gen_rotl_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1459e5918d7dSYoshinori Sato } 1460e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); 1461e5918d7dSYoshinori Sato break; 1462e5918d7dSYoshinori Sato case ROTR: 1463e5918d7dSYoshinori Sato if (ir == ROT_IMM) { 1464e5918d7dSYoshinori Sato tcg_gen_rotri_i32(cpu_regs[rd], cpu_regs[rd], src); 1465e5918d7dSYoshinori Sato } else { 1466e5918d7dSYoshinori Sato tcg_gen_rotr_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); 1467e5918d7dSYoshinori Sato } 1468e5918d7dSYoshinori Sato tcg_gen_shri_i32(cpu_psw_c, cpu_regs[rd], 31); 1469e5918d7dSYoshinori Sato break; 1470e5918d7dSYoshinori Sato } 1471e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); 1472e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); 1473e5918d7dSYoshinori Sato } 1474e5918d7dSYoshinori Sato 1475e5918d7dSYoshinori Sato /* rotl #imm, rd */ 1476e5918d7dSYoshinori Sato static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a) 1477e5918d7dSYoshinori Sato { 1478e5918d7dSYoshinori Sato rx_rot(ROT_IMM, ROTL, a->rd, a->imm); 1479e5918d7dSYoshinori Sato return true; 1480e5918d7dSYoshinori Sato } 1481e5918d7dSYoshinori Sato 1482e5918d7dSYoshinori Sato /* rotl rs, rd */ 1483e5918d7dSYoshinori Sato static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a) 1484e5918d7dSYoshinori Sato { 1485e5918d7dSYoshinori Sato rx_rot(ROT_REG, ROTL, a->rd, a->rs); 1486e5918d7dSYoshinori Sato return true; 1487e5918d7dSYoshinori Sato } 1488e5918d7dSYoshinori Sato 1489e5918d7dSYoshinori Sato /* rotr #imm, rd */ 1490e5918d7dSYoshinori Sato static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a) 1491e5918d7dSYoshinori Sato { 1492e5918d7dSYoshinori Sato rx_rot(ROT_IMM, ROTR, a->rd, a->imm); 1493e5918d7dSYoshinori Sato return true; 1494e5918d7dSYoshinori Sato } 1495e5918d7dSYoshinori Sato 1496e5918d7dSYoshinori Sato /* rotr rs, rd */ 1497e5918d7dSYoshinori Sato static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a) 1498e5918d7dSYoshinori Sato { 1499e5918d7dSYoshinori Sato rx_rot(ROT_REG, ROTR, a->rd, a->rs); 1500e5918d7dSYoshinori Sato return true; 1501e5918d7dSYoshinori Sato } 1502e5918d7dSYoshinori Sato 1503e5918d7dSYoshinori Sato /* revl rs, rd */ 1504e5918d7dSYoshinori Sato static bool trans_REVL(DisasContext *ctx, arg_REVL *a) 1505e5918d7dSYoshinori Sato { 1506e5918d7dSYoshinori Sato tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]); 1507e5918d7dSYoshinori Sato return true; 1508e5918d7dSYoshinori Sato } 1509e5918d7dSYoshinori Sato 1510e5918d7dSYoshinori Sato /* revw rs, rd */ 1511e5918d7dSYoshinori Sato static bool trans_REVW(DisasContext *ctx, arg_REVW *a) 1512e5918d7dSYoshinori Sato { 1513e5918d7dSYoshinori Sato TCGv tmp; 1514e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1515e5918d7dSYoshinori Sato tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); 1516e5918d7dSYoshinori Sato tcg_gen_shli_i32(tmp, tmp, 8); 1517e5918d7dSYoshinori Sato tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); 1518e5918d7dSYoshinori Sato tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); 1519e5918d7dSYoshinori Sato tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); 1520e5918d7dSYoshinori Sato return true; 1521e5918d7dSYoshinori Sato } 1522e5918d7dSYoshinori Sato 1523e5918d7dSYoshinori Sato /* conditional branch helper */ 1524e5918d7dSYoshinori Sato static void rx_bcnd_main(DisasContext *ctx, int cd, int dst) 1525e5918d7dSYoshinori Sato { 1526e5918d7dSYoshinori Sato DisasCompare dc; 1527e5918d7dSYoshinori Sato TCGLabel *t, *done; 1528e5918d7dSYoshinori Sato 1529e5918d7dSYoshinori Sato switch (cd) { 1530e5918d7dSYoshinori Sato case 0 ... 13: 1531e5918d7dSYoshinori Sato dc.temp = tcg_temp_new(); 1532e5918d7dSYoshinori Sato psw_cond(&dc, cd); 1533e5918d7dSYoshinori Sato t = gen_new_label(); 1534e5918d7dSYoshinori Sato done = gen_new_label(); 1535e5918d7dSYoshinori Sato tcg_gen_brcondi_i32(dc.cond, dc.value, 0, t); 1536e5918d7dSYoshinori Sato gen_goto_tb(ctx, 0, ctx->base.pc_next); 1537e5918d7dSYoshinori Sato tcg_gen_br(done); 1538e5918d7dSYoshinori Sato gen_set_label(t); 1539e5918d7dSYoshinori Sato gen_goto_tb(ctx, 1, ctx->pc + dst); 1540e5918d7dSYoshinori Sato gen_set_label(done); 1541e5918d7dSYoshinori Sato break; 1542e5918d7dSYoshinori Sato case 14: 1543e5918d7dSYoshinori Sato /* always true case */ 1544e5918d7dSYoshinori Sato gen_goto_tb(ctx, 0, ctx->pc + dst); 1545e5918d7dSYoshinori Sato break; 1546e5918d7dSYoshinori Sato case 15: 1547e5918d7dSYoshinori Sato /* always false case */ 1548e5918d7dSYoshinori Sato /* Nothing do */ 1549e5918d7dSYoshinori Sato break; 1550e5918d7dSYoshinori Sato } 1551e5918d7dSYoshinori Sato } 1552e5918d7dSYoshinori Sato 1553e5918d7dSYoshinori Sato /* beq dsp:3 / bne dsp:3 */ 1554e5918d7dSYoshinori Sato /* beq dsp:8 / bne dsp:8 */ 1555e5918d7dSYoshinori Sato /* bc dsp:8 / bnc dsp:8 */ 1556e5918d7dSYoshinori Sato /* bgtu dsp:8 / bleu dsp:8 */ 1557e5918d7dSYoshinori Sato /* bpz dsp:8 / bn dsp:8 */ 1558e5918d7dSYoshinori Sato /* bge dsp:8 / blt dsp:8 */ 1559e5918d7dSYoshinori Sato /* bgt dsp:8 / ble dsp:8 */ 1560e5918d7dSYoshinori Sato /* bo dsp:8 / bno dsp:8 */ 1561e5918d7dSYoshinori Sato /* beq dsp:16 / bne dsp:16 */ 1562e5918d7dSYoshinori Sato static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a) 1563e5918d7dSYoshinori Sato { 1564e5918d7dSYoshinori Sato rx_bcnd_main(ctx, a->cd, a->dsp); 1565e5918d7dSYoshinori Sato return true; 1566e5918d7dSYoshinori Sato } 1567e5918d7dSYoshinori Sato 1568e5918d7dSYoshinori Sato /* bra dsp:3 */ 1569e5918d7dSYoshinori Sato /* bra dsp:8 */ 1570e5918d7dSYoshinori Sato /* bra dsp:16 */ 1571e5918d7dSYoshinori Sato /* bra dsp:24 */ 1572e5918d7dSYoshinori Sato static bool trans_BRA(DisasContext *ctx, arg_BRA *a) 1573e5918d7dSYoshinori Sato { 1574e5918d7dSYoshinori Sato rx_bcnd_main(ctx, 14, a->dsp); 1575e5918d7dSYoshinori Sato return true; 1576e5918d7dSYoshinori Sato } 1577e5918d7dSYoshinori Sato 1578e5918d7dSYoshinori Sato /* bra rs */ 1579e5918d7dSYoshinori Sato static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a) 1580e5918d7dSYoshinori Sato { 1581e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1582e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1583e5918d7dSYoshinori Sato return true; 1584e5918d7dSYoshinori Sato } 1585e5918d7dSYoshinori Sato 1586e5918d7dSYoshinori Sato static inline void rx_save_pc(DisasContext *ctx) 1587e5918d7dSYoshinori Sato { 1588e5918d7dSYoshinori Sato TCGv pc = tcg_const_i32(ctx->base.pc_next); 1589e5918d7dSYoshinori Sato push(pc); 1590e5918d7dSYoshinori Sato } 1591e5918d7dSYoshinori Sato 1592e5918d7dSYoshinori Sato /* jmp rs */ 1593e5918d7dSYoshinori Sato static bool trans_JMP(DisasContext *ctx, arg_JMP *a) 1594e5918d7dSYoshinori Sato { 1595e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1596e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1597e5918d7dSYoshinori Sato return true; 1598e5918d7dSYoshinori Sato } 1599e5918d7dSYoshinori Sato 1600e5918d7dSYoshinori Sato /* jsr rs */ 1601e5918d7dSYoshinori Sato static bool trans_JSR(DisasContext *ctx, arg_JSR *a) 1602e5918d7dSYoshinori Sato { 1603e5918d7dSYoshinori Sato rx_save_pc(ctx); 1604e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); 1605e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1606e5918d7dSYoshinori Sato return true; 1607e5918d7dSYoshinori Sato } 1608e5918d7dSYoshinori Sato 1609e5918d7dSYoshinori Sato /* bsr dsp:16 */ 1610e5918d7dSYoshinori Sato /* bsr dsp:24 */ 1611e5918d7dSYoshinori Sato static bool trans_BSR(DisasContext *ctx, arg_BSR *a) 1612e5918d7dSYoshinori Sato { 1613e5918d7dSYoshinori Sato rx_save_pc(ctx); 1614e5918d7dSYoshinori Sato rx_bcnd_main(ctx, 14, a->dsp); 1615e5918d7dSYoshinori Sato return true; 1616e5918d7dSYoshinori Sato } 1617e5918d7dSYoshinori Sato 1618e5918d7dSYoshinori Sato /* bsr rs */ 1619e5918d7dSYoshinori Sato static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a) 1620e5918d7dSYoshinori Sato { 1621e5918d7dSYoshinori Sato rx_save_pc(ctx); 1622e5918d7dSYoshinori Sato tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); 1623e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1624e5918d7dSYoshinori Sato return true; 1625e5918d7dSYoshinori Sato } 1626e5918d7dSYoshinori Sato 1627e5918d7dSYoshinori Sato /* rts */ 1628e5918d7dSYoshinori Sato static bool trans_RTS(DisasContext *ctx, arg_RTS *a) 1629e5918d7dSYoshinori Sato { 1630e5918d7dSYoshinori Sato pop(cpu_pc); 1631e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_JUMP; 1632e5918d7dSYoshinori Sato return true; 1633e5918d7dSYoshinori Sato } 1634e5918d7dSYoshinori Sato 1635e5918d7dSYoshinori Sato /* nop */ 1636e5918d7dSYoshinori Sato static bool trans_NOP(DisasContext *ctx, arg_NOP *a) 1637e5918d7dSYoshinori Sato { 1638e5918d7dSYoshinori Sato return true; 1639e5918d7dSYoshinori Sato } 1640e5918d7dSYoshinori Sato 1641e5918d7dSYoshinori Sato /* scmpu */ 1642e5918d7dSYoshinori Sato static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) 1643e5918d7dSYoshinori Sato { 1644e5918d7dSYoshinori Sato gen_helper_scmpu(cpu_env); 1645e5918d7dSYoshinori Sato return true; 1646e5918d7dSYoshinori Sato } 1647e5918d7dSYoshinori Sato 1648e5918d7dSYoshinori Sato /* smovu */ 1649e5918d7dSYoshinori Sato static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) 1650e5918d7dSYoshinori Sato { 1651e5918d7dSYoshinori Sato gen_helper_smovu(cpu_env); 1652e5918d7dSYoshinori Sato return true; 1653e5918d7dSYoshinori Sato } 1654e5918d7dSYoshinori Sato 1655e5918d7dSYoshinori Sato /* smovf */ 1656e5918d7dSYoshinori Sato static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) 1657e5918d7dSYoshinori Sato { 1658e5918d7dSYoshinori Sato gen_helper_smovf(cpu_env); 1659e5918d7dSYoshinori Sato return true; 1660e5918d7dSYoshinori Sato } 1661e5918d7dSYoshinori Sato 1662e5918d7dSYoshinori Sato /* smovb */ 1663e5918d7dSYoshinori Sato static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) 1664e5918d7dSYoshinori Sato { 1665e5918d7dSYoshinori Sato gen_helper_smovb(cpu_env); 1666e5918d7dSYoshinori Sato return true; 1667e5918d7dSYoshinori Sato } 1668e5918d7dSYoshinori Sato 1669e5918d7dSYoshinori Sato #define STRING(op) \ 1670e5918d7dSYoshinori Sato do { \ 1671e5918d7dSYoshinori Sato TCGv size = tcg_const_i32(a->sz); \ 1672e5918d7dSYoshinori Sato gen_helper_##op(cpu_env, size); \ 1673e5918d7dSYoshinori Sato } while (0) 1674e5918d7dSYoshinori Sato 1675e5918d7dSYoshinori Sato /* suntile.<bwl> */ 1676e5918d7dSYoshinori Sato static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a) 1677e5918d7dSYoshinori Sato { 1678e5918d7dSYoshinori Sato STRING(suntil); 1679e5918d7dSYoshinori Sato return true; 1680e5918d7dSYoshinori Sato } 1681e5918d7dSYoshinori Sato 1682e5918d7dSYoshinori Sato /* swhile.<bwl> */ 1683e5918d7dSYoshinori Sato static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a) 1684e5918d7dSYoshinori Sato { 1685e5918d7dSYoshinori Sato STRING(swhile); 1686e5918d7dSYoshinori Sato return true; 1687e5918d7dSYoshinori Sato } 1688e5918d7dSYoshinori Sato /* sstr.<bwl> */ 1689e5918d7dSYoshinori Sato static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a) 1690e5918d7dSYoshinori Sato { 1691e5918d7dSYoshinori Sato STRING(sstr); 1692e5918d7dSYoshinori Sato return true; 1693e5918d7dSYoshinori Sato } 1694e5918d7dSYoshinori Sato 1695e5918d7dSYoshinori Sato /* rmpa.<bwl> */ 1696e5918d7dSYoshinori Sato static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a) 1697e5918d7dSYoshinori Sato { 1698e5918d7dSYoshinori Sato STRING(rmpa); 1699e5918d7dSYoshinori Sato return true; 1700e5918d7dSYoshinori Sato } 1701e5918d7dSYoshinori Sato 1702e5918d7dSYoshinori Sato static void rx_mul64hi(TCGv_i64 ret, int rs, int rs2) 1703e5918d7dSYoshinori Sato { 1704e5918d7dSYoshinori Sato TCGv_i64 tmp0, tmp1; 1705e5918d7dSYoshinori Sato tmp0 = tcg_temp_new_i64(); 1706e5918d7dSYoshinori Sato tmp1 = tcg_temp_new_i64(); 1707e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1708e5918d7dSYoshinori Sato tcg_gen_sari_i64(tmp0, tmp0, 16); 1709e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1710e5918d7dSYoshinori Sato tcg_gen_sari_i64(tmp1, tmp1, 16); 1711e5918d7dSYoshinori Sato tcg_gen_mul_i64(ret, tmp0, tmp1); 1712e5918d7dSYoshinori Sato tcg_gen_shli_i64(ret, ret, 16); 1713e5918d7dSYoshinori Sato } 1714e5918d7dSYoshinori Sato 1715e5918d7dSYoshinori Sato static void rx_mul64lo(TCGv_i64 ret, int rs, int rs2) 1716e5918d7dSYoshinori Sato { 1717e5918d7dSYoshinori Sato TCGv_i64 tmp0, tmp1; 1718e5918d7dSYoshinori Sato tmp0 = tcg_temp_new_i64(); 1719e5918d7dSYoshinori Sato tmp1 = tcg_temp_new_i64(); 1720e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); 1721e5918d7dSYoshinori Sato tcg_gen_ext16s_i64(tmp0, tmp0); 1722e5918d7dSYoshinori Sato tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); 1723e5918d7dSYoshinori Sato tcg_gen_ext16s_i64(tmp1, tmp1); 1724e5918d7dSYoshinori Sato tcg_gen_mul_i64(ret, tmp0, tmp1); 1725e5918d7dSYoshinori Sato tcg_gen_shli_i64(ret, ret, 16); 1726e5918d7dSYoshinori Sato } 1727e5918d7dSYoshinori Sato 1728e5918d7dSYoshinori Sato /* mulhi rs,rs2 */ 1729e5918d7dSYoshinori Sato static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a) 1730e5918d7dSYoshinori Sato { 1731e5918d7dSYoshinori Sato rx_mul64hi(cpu_acc, a->rs, a->rs2); 1732e5918d7dSYoshinori Sato return true; 1733e5918d7dSYoshinori Sato } 1734e5918d7dSYoshinori Sato 1735e5918d7dSYoshinori Sato /* mullo rs,rs2 */ 1736e5918d7dSYoshinori Sato static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a) 1737e5918d7dSYoshinori Sato { 1738e5918d7dSYoshinori Sato rx_mul64lo(cpu_acc, a->rs, a->rs2); 1739e5918d7dSYoshinori Sato return true; 1740e5918d7dSYoshinori Sato } 1741e5918d7dSYoshinori Sato 1742e5918d7dSYoshinori Sato /* machi rs,rs2 */ 1743e5918d7dSYoshinori Sato static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a) 1744e5918d7dSYoshinori Sato { 1745e5918d7dSYoshinori Sato TCGv_i64 tmp; 1746e5918d7dSYoshinori Sato tmp = tcg_temp_new_i64(); 1747e5918d7dSYoshinori Sato rx_mul64hi(tmp, a->rs, a->rs2); 1748e5918d7dSYoshinori Sato tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1749e5918d7dSYoshinori Sato return true; 1750e5918d7dSYoshinori Sato } 1751e5918d7dSYoshinori Sato 1752e5918d7dSYoshinori Sato /* maclo rs,rs2 */ 1753e5918d7dSYoshinori Sato static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a) 1754e5918d7dSYoshinori Sato { 1755e5918d7dSYoshinori Sato TCGv_i64 tmp; 1756e5918d7dSYoshinori Sato tmp = tcg_temp_new_i64(); 1757e5918d7dSYoshinori Sato rx_mul64lo(tmp, a->rs, a->rs2); 1758e5918d7dSYoshinori Sato tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); 1759e5918d7dSYoshinori Sato return true; 1760e5918d7dSYoshinori Sato } 1761e5918d7dSYoshinori Sato 1762e5918d7dSYoshinori Sato /* mvfachi rd */ 1763e5918d7dSYoshinori Sato static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a) 1764e5918d7dSYoshinori Sato { 1765e5918d7dSYoshinori Sato tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc); 1766e5918d7dSYoshinori Sato return true; 1767e5918d7dSYoshinori Sato } 1768e5918d7dSYoshinori Sato 1769e5918d7dSYoshinori Sato /* mvfacmi rd */ 1770e5918d7dSYoshinori Sato static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a) 1771e5918d7dSYoshinori Sato { 1772e5918d7dSYoshinori Sato TCGv_i64 rd64; 1773e5918d7dSYoshinori Sato rd64 = tcg_temp_new_i64(); 1774e5918d7dSYoshinori Sato tcg_gen_extract_i64(rd64, cpu_acc, 16, 32); 1775e5918d7dSYoshinori Sato tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64); 1776e5918d7dSYoshinori Sato return true; 1777e5918d7dSYoshinori Sato } 1778e5918d7dSYoshinori Sato 1779e5918d7dSYoshinori Sato /* mvtachi rs */ 1780e5918d7dSYoshinori Sato static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a) 1781e5918d7dSYoshinori Sato { 1782e5918d7dSYoshinori Sato TCGv_i64 rs64; 1783e5918d7dSYoshinori Sato rs64 = tcg_temp_new_i64(); 1784e5918d7dSYoshinori Sato tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1785e5918d7dSYoshinori Sato tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 32, 32); 1786e5918d7dSYoshinori Sato return true; 1787e5918d7dSYoshinori Sato } 1788e5918d7dSYoshinori Sato 1789e5918d7dSYoshinori Sato /* mvtaclo rs */ 1790e5918d7dSYoshinori Sato static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a) 1791e5918d7dSYoshinori Sato { 1792e5918d7dSYoshinori Sato TCGv_i64 rs64; 1793e5918d7dSYoshinori Sato rs64 = tcg_temp_new_i64(); 1794e5918d7dSYoshinori Sato tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); 1795e5918d7dSYoshinori Sato tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 0, 32); 1796e5918d7dSYoshinori Sato return true; 1797e5918d7dSYoshinori Sato } 1798e5918d7dSYoshinori Sato 1799e5918d7dSYoshinori Sato /* racw #imm */ 1800e5918d7dSYoshinori Sato static bool trans_RACW(DisasContext *ctx, arg_RACW *a) 1801e5918d7dSYoshinori Sato { 1802e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(a->imm + 1); 1803e5918d7dSYoshinori Sato gen_helper_racw(cpu_env, imm); 1804e5918d7dSYoshinori Sato return true; 1805e5918d7dSYoshinori Sato } 1806e5918d7dSYoshinori Sato 1807e5918d7dSYoshinori Sato /* sat rd */ 1808e5918d7dSYoshinori Sato static bool trans_SAT(DisasContext *ctx, arg_SAT *a) 1809e5918d7dSYoshinori Sato { 1810e5918d7dSYoshinori Sato TCGv tmp, z; 1811e5918d7dSYoshinori Sato tmp = tcg_temp_new(); 1812e5918d7dSYoshinori Sato z = tcg_const_i32(0); 1813e5918d7dSYoshinori Sato /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */ 1814e5918d7dSYoshinori Sato tcg_gen_sari_i32(tmp, cpu_psw_s, 31); 1815e5918d7dSYoshinori Sato /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */ 1816e5918d7dSYoshinori Sato tcg_gen_xori_i32(tmp, tmp, 0x80000000); 1817e5918d7dSYoshinori Sato tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], 1818e5918d7dSYoshinori Sato cpu_psw_o, z, tmp, cpu_regs[a->rd]); 1819e5918d7dSYoshinori Sato return true; 1820e5918d7dSYoshinori Sato } 1821e5918d7dSYoshinori Sato 1822e5918d7dSYoshinori Sato /* satr */ 1823e5918d7dSYoshinori Sato static bool trans_SATR(DisasContext *ctx, arg_SATR *a) 1824e5918d7dSYoshinori Sato { 1825e5918d7dSYoshinori Sato gen_helper_satr(cpu_env); 1826e5918d7dSYoshinori Sato return true; 1827e5918d7dSYoshinori Sato } 1828e5918d7dSYoshinori Sato 1829e5918d7dSYoshinori Sato #define cat3(a, b, c) a##b##c 1830e5918d7dSYoshinori Sato #define FOP(name, op) \ 1831e5918d7dSYoshinori Sato static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 1832e5918d7dSYoshinori Sato cat3(arg_, name, _ir) * a) \ 1833e5918d7dSYoshinori Sato { \ 1834e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(li(ctx, 0)); \ 1835e5918d7dSYoshinori Sato gen_helper_##op(cpu_regs[a->rd], cpu_env, \ 1836e5918d7dSYoshinori Sato cpu_regs[a->rd], imm); \ 1837e5918d7dSYoshinori Sato return true; \ 1838e5918d7dSYoshinori Sato } \ 1839e5918d7dSYoshinori Sato static bool cat3(trans_, name, _mr)(DisasContext *ctx, \ 1840e5918d7dSYoshinori Sato cat3(arg_, name, _mr) * a) \ 1841e5918d7dSYoshinori Sato { \ 1842e5918d7dSYoshinori Sato TCGv val, mem; \ 1843e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 1844e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1845e5918d7dSYoshinori Sato gen_helper_##op(cpu_regs[a->rd], cpu_env, \ 1846e5918d7dSYoshinori Sato cpu_regs[a->rd], val); \ 1847e5918d7dSYoshinori Sato return true; \ 1848e5918d7dSYoshinori Sato } 1849e5918d7dSYoshinori Sato 1850e5918d7dSYoshinori Sato #define FCONVOP(name, op) \ 1851e5918d7dSYoshinori Sato static bool trans_##name(DisasContext *ctx, arg_##name * a) \ 1852e5918d7dSYoshinori Sato { \ 1853e5918d7dSYoshinori Sato TCGv val, mem; \ 1854e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 1855e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ 1856e5918d7dSYoshinori Sato gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \ 1857e5918d7dSYoshinori Sato return true; \ 1858e5918d7dSYoshinori Sato } 1859e5918d7dSYoshinori Sato 1860e5918d7dSYoshinori Sato FOP(FADD, fadd) 1861e5918d7dSYoshinori Sato FOP(FSUB, fsub) 1862e5918d7dSYoshinori Sato FOP(FMUL, fmul) 1863e5918d7dSYoshinori Sato FOP(FDIV, fdiv) 1864e5918d7dSYoshinori Sato 1865e5918d7dSYoshinori Sato /* fcmp #imm, rd */ 1866e5918d7dSYoshinori Sato static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) 1867e5918d7dSYoshinori Sato { 1868e5918d7dSYoshinori Sato TCGv imm = tcg_const_i32(li(ctx, 0)); 1869e5918d7dSYoshinori Sato gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm); 1870e5918d7dSYoshinori Sato return true; 1871e5918d7dSYoshinori Sato } 1872e5918d7dSYoshinori Sato 1873e5918d7dSYoshinori Sato /* fcmp dsp[rs], rd */ 1874e5918d7dSYoshinori Sato /* fcmp rs, rd */ 1875e5918d7dSYoshinori Sato static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) 1876e5918d7dSYoshinori Sato { 1877e5918d7dSYoshinori Sato TCGv val, mem; 1878e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1879e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); 1880e5918d7dSYoshinori Sato gen_helper_fcmp(cpu_env, cpu_regs[a->rd], val); 1881e5918d7dSYoshinori Sato return true; 1882e5918d7dSYoshinori Sato } 1883e5918d7dSYoshinori Sato 1884e5918d7dSYoshinori Sato FCONVOP(FTOI, ftoi) 1885e5918d7dSYoshinori Sato FCONVOP(ROUND, round) 1886e5918d7dSYoshinori Sato 1887e5918d7dSYoshinori Sato /* itof rs, rd */ 1888e5918d7dSYoshinori Sato /* itof dsp[rs], rd */ 1889e5918d7dSYoshinori Sato static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a) 1890e5918d7dSYoshinori Sato { 1891e5918d7dSYoshinori Sato TCGv val, mem; 1892e5918d7dSYoshinori Sato mem = tcg_temp_new(); 1893e5918d7dSYoshinori Sato val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs); 1894e5918d7dSYoshinori Sato gen_helper_itof(cpu_regs[a->rd], cpu_env, val); 1895e5918d7dSYoshinori Sato return true; 1896e5918d7dSYoshinori Sato } 1897e5918d7dSYoshinori Sato 1898e5918d7dSYoshinori Sato static void rx_bsetm(TCGv mem, TCGv mask) 1899e5918d7dSYoshinori Sato { 1900e5918d7dSYoshinori Sato TCGv val; 1901e5918d7dSYoshinori Sato val = tcg_temp_new(); 1902e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 1903e5918d7dSYoshinori Sato tcg_gen_or_i32(val, val, mask); 1904e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, mem); 1905e5918d7dSYoshinori Sato } 1906e5918d7dSYoshinori Sato 1907e5918d7dSYoshinori Sato static void rx_bclrm(TCGv mem, TCGv mask) 1908e5918d7dSYoshinori Sato { 1909e5918d7dSYoshinori Sato TCGv val; 1910e5918d7dSYoshinori Sato val = tcg_temp_new(); 1911e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 1912e5918d7dSYoshinori Sato tcg_gen_andc_i32(val, val, mask); 1913e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, mem); 1914e5918d7dSYoshinori Sato } 1915e5918d7dSYoshinori Sato 1916e5918d7dSYoshinori Sato static void rx_btstm(TCGv mem, TCGv mask) 1917e5918d7dSYoshinori Sato { 1918e5918d7dSYoshinori Sato TCGv val; 1919e5918d7dSYoshinori Sato val = tcg_temp_new(); 1920e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 1921e5918d7dSYoshinori Sato tcg_gen_and_i32(val, val, mask); 1922e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0); 1923e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 1924e5918d7dSYoshinori Sato } 1925e5918d7dSYoshinori Sato 1926e5918d7dSYoshinori Sato static void rx_bnotm(TCGv mem, TCGv mask) 1927e5918d7dSYoshinori Sato { 1928e5918d7dSYoshinori Sato TCGv val; 1929e5918d7dSYoshinori Sato val = tcg_temp_new(); 1930e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, mem); 1931e5918d7dSYoshinori Sato tcg_gen_xor_i32(val, val, mask); 1932e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, mem); 1933e5918d7dSYoshinori Sato } 1934e5918d7dSYoshinori Sato 1935e5918d7dSYoshinori Sato static void rx_bsetr(TCGv reg, TCGv mask) 1936e5918d7dSYoshinori Sato { 1937e5918d7dSYoshinori Sato tcg_gen_or_i32(reg, reg, mask); 1938e5918d7dSYoshinori Sato } 1939e5918d7dSYoshinori Sato 1940e5918d7dSYoshinori Sato static void rx_bclrr(TCGv reg, TCGv mask) 1941e5918d7dSYoshinori Sato { 1942e5918d7dSYoshinori Sato tcg_gen_andc_i32(reg, reg, mask); 1943e5918d7dSYoshinori Sato } 1944e5918d7dSYoshinori Sato 1945e5918d7dSYoshinori Sato static inline void rx_btstr(TCGv reg, TCGv mask) 1946e5918d7dSYoshinori Sato { 1947e5918d7dSYoshinori Sato TCGv t0; 1948e5918d7dSYoshinori Sato t0 = tcg_temp_new(); 1949e5918d7dSYoshinori Sato tcg_gen_and_i32(t0, reg, mask); 1950e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0); 1951e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); 1952e5918d7dSYoshinori Sato } 1953e5918d7dSYoshinori Sato 1954e5918d7dSYoshinori Sato static inline void rx_bnotr(TCGv reg, TCGv mask) 1955e5918d7dSYoshinori Sato { 1956e5918d7dSYoshinori Sato tcg_gen_xor_i32(reg, reg, mask); 1957e5918d7dSYoshinori Sato } 1958e5918d7dSYoshinori Sato 1959e5918d7dSYoshinori Sato #define BITOP(name, op) \ 1960e5918d7dSYoshinori Sato static bool cat3(trans_, name, _im)(DisasContext *ctx, \ 1961e5918d7dSYoshinori Sato cat3(arg_, name, _im) * a) \ 1962e5918d7dSYoshinori Sato { \ 1963e5918d7dSYoshinori Sato TCGv mask, mem, addr; \ 1964e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 1965e5918d7dSYoshinori Sato mask = tcg_const_i32(1 << a->imm); \ 1966e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 1967e5918d7dSYoshinori Sato cat3(rx_, op, m)(addr, mask); \ 1968e5918d7dSYoshinori Sato return true; \ 1969e5918d7dSYoshinori Sato } \ 1970e5918d7dSYoshinori Sato static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ 1971e5918d7dSYoshinori Sato cat3(arg_, name, _ir) * a) \ 1972e5918d7dSYoshinori Sato { \ 1973e5918d7dSYoshinori Sato TCGv mask; \ 1974e5918d7dSYoshinori Sato mask = tcg_const_i32(1 << a->imm); \ 1975e5918d7dSYoshinori Sato cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 1976e5918d7dSYoshinori Sato return true; \ 1977e5918d7dSYoshinori Sato } \ 1978e5918d7dSYoshinori Sato static bool cat3(trans_, name, _rr)(DisasContext *ctx, \ 1979e5918d7dSYoshinori Sato cat3(arg_, name, _rr) * a) \ 1980e5918d7dSYoshinori Sato { \ 1981e5918d7dSYoshinori Sato TCGv mask, b; \ 1982*09374ee2SRichard Henderson mask = tcg_temp_new(); \ 1983e5918d7dSYoshinori Sato b = tcg_temp_new(); \ 1984e5918d7dSYoshinori Sato tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ 1985*09374ee2SRichard Henderson tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ 1986e5918d7dSYoshinori Sato cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ 1987e5918d7dSYoshinori Sato return true; \ 1988e5918d7dSYoshinori Sato } \ 1989e5918d7dSYoshinori Sato static bool cat3(trans_, name, _rm)(DisasContext *ctx, \ 1990e5918d7dSYoshinori Sato cat3(arg_, name, _rm) * a) \ 1991e5918d7dSYoshinori Sato { \ 1992e5918d7dSYoshinori Sato TCGv mask, mem, addr, b; \ 1993*09374ee2SRichard Henderson mask = tcg_temp_new(); \ 1994e5918d7dSYoshinori Sato b = tcg_temp_new(); \ 1995e5918d7dSYoshinori Sato tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \ 1996*09374ee2SRichard Henderson tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ 1997e5918d7dSYoshinori Sato mem = tcg_temp_new(); \ 1998e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ 1999e5918d7dSYoshinori Sato cat3(rx_, op, m)(addr, mask); \ 2000e5918d7dSYoshinori Sato return true; \ 2001e5918d7dSYoshinori Sato } 2002e5918d7dSYoshinori Sato 2003e5918d7dSYoshinori Sato BITOP(BSET, bset) 2004e5918d7dSYoshinori Sato BITOP(BCLR, bclr) 2005e5918d7dSYoshinori Sato BITOP(BTST, btst) 2006e5918d7dSYoshinori Sato BITOP(BNOT, bnot) 2007e5918d7dSYoshinori Sato 2008e5918d7dSYoshinori Sato static inline void bmcnd_op(TCGv val, TCGCond cond, int pos) 2009e5918d7dSYoshinori Sato { 2010e5918d7dSYoshinori Sato TCGv bit; 2011e5918d7dSYoshinori Sato DisasCompare dc; 2012e5918d7dSYoshinori Sato dc.temp = tcg_temp_new(); 2013e5918d7dSYoshinori Sato bit = tcg_temp_new(); 2014e5918d7dSYoshinori Sato psw_cond(&dc, cond); 2015e5918d7dSYoshinori Sato tcg_gen_andi_i32(val, val, ~(1 << pos)); 2016e5918d7dSYoshinori Sato tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0); 2017e5918d7dSYoshinori Sato tcg_gen_deposit_i32(val, val, bit, pos, 1); 2018e5918d7dSYoshinori Sato } 2019e5918d7dSYoshinori Sato 2020e5918d7dSYoshinori Sato /* bmcnd #imm, dsp[rd] */ 2021e5918d7dSYoshinori Sato static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) 2022e5918d7dSYoshinori Sato { 2023e5918d7dSYoshinori Sato TCGv val, mem, addr; 2024e5918d7dSYoshinori Sato val = tcg_temp_new(); 2025e5918d7dSYoshinori Sato mem = tcg_temp_new(); 2026e5918d7dSYoshinori Sato addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); 2027e5918d7dSYoshinori Sato rx_gen_ld(MO_8, val, addr); 2028e5918d7dSYoshinori Sato bmcnd_op(val, a->cd, a->imm); 2029e5918d7dSYoshinori Sato rx_gen_st(MO_8, val, addr); 2030e5918d7dSYoshinori Sato return true; 2031e5918d7dSYoshinori Sato } 2032e5918d7dSYoshinori Sato 2033e5918d7dSYoshinori Sato /* bmcond #imm, rd */ 2034e5918d7dSYoshinori Sato static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a) 2035e5918d7dSYoshinori Sato { 2036e5918d7dSYoshinori Sato bmcnd_op(cpu_regs[a->rd], a->cd, a->imm); 2037e5918d7dSYoshinori Sato return true; 2038e5918d7dSYoshinori Sato } 2039e5918d7dSYoshinori Sato 2040e5918d7dSYoshinori Sato enum { 2041e5918d7dSYoshinori Sato PSW_C = 0, 2042e5918d7dSYoshinori Sato PSW_Z = 1, 2043e5918d7dSYoshinori Sato PSW_S = 2, 2044e5918d7dSYoshinori Sato PSW_O = 3, 2045e5918d7dSYoshinori Sato PSW_I = 8, 2046e5918d7dSYoshinori Sato PSW_U = 9, 2047e5918d7dSYoshinori Sato }; 2048e5918d7dSYoshinori Sato 2049e5918d7dSYoshinori Sato static inline void clrsetpsw(DisasContext *ctx, int cb, int val) 2050e5918d7dSYoshinori Sato { 2051e5918d7dSYoshinori Sato if (cb < 8) { 2052e5918d7dSYoshinori Sato switch (cb) { 2053e5918d7dSYoshinori Sato case PSW_C: 2054e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_c, val); 2055e5918d7dSYoshinori Sato break; 2056e5918d7dSYoshinori Sato case PSW_Z: 2057e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_z, val == 0); 2058e5918d7dSYoshinori Sato break; 2059e5918d7dSYoshinori Sato case PSW_S: 2060e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_s, val ? -1 : 0); 2061e5918d7dSYoshinori Sato break; 2062e5918d7dSYoshinori Sato case PSW_O: 2063e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_o, val << 31); 2064e5918d7dSYoshinori Sato break; 2065e5918d7dSYoshinori Sato default: 2066e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); 2067e5918d7dSYoshinori Sato break; 2068e5918d7dSYoshinori Sato } 2069e5918d7dSYoshinori Sato } else if (is_privileged(ctx, 0)) { 2070e5918d7dSYoshinori Sato switch (cb) { 2071e5918d7dSYoshinori Sato case PSW_I: 2072e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_i, val); 2073e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_UPDATE; 2074e5918d7dSYoshinori Sato break; 2075e5918d7dSYoshinori Sato case PSW_U: 20763c69336aSRichard Henderson if (FIELD_EX32(ctx->tb_flags, PSW, U) != val) { 20773c69336aSRichard Henderson ctx->tb_flags = FIELD_DP32(ctx->tb_flags, PSW, U, val); 2078e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_u, val); 20793c69336aSRichard Henderson tcg_gen_mov_i32(val ? cpu_isp : cpu_usp, cpu_sp); 20803c69336aSRichard Henderson tcg_gen_mov_i32(cpu_sp, val ? cpu_usp : cpu_isp); 20813c69336aSRichard Henderson } 2082e5918d7dSYoshinori Sato break; 2083e5918d7dSYoshinori Sato default: 2084e5918d7dSYoshinori Sato qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); 2085e5918d7dSYoshinori Sato break; 2086e5918d7dSYoshinori Sato } 2087e5918d7dSYoshinori Sato } 2088e5918d7dSYoshinori Sato } 2089e5918d7dSYoshinori Sato 2090e5918d7dSYoshinori Sato /* clrpsw psw */ 2091e5918d7dSYoshinori Sato static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a) 2092e5918d7dSYoshinori Sato { 2093e5918d7dSYoshinori Sato clrsetpsw(ctx, a->cb, 0); 2094e5918d7dSYoshinori Sato return true; 2095e5918d7dSYoshinori Sato } 2096e5918d7dSYoshinori Sato 2097e5918d7dSYoshinori Sato /* setpsw psw */ 2098e5918d7dSYoshinori Sato static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a) 2099e5918d7dSYoshinori Sato { 2100e5918d7dSYoshinori Sato clrsetpsw(ctx, a->cb, 1); 2101e5918d7dSYoshinori Sato return true; 2102e5918d7dSYoshinori Sato } 2103e5918d7dSYoshinori Sato 2104e5918d7dSYoshinori Sato /* mvtipl #imm */ 2105e5918d7dSYoshinori Sato static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a) 2106e5918d7dSYoshinori Sato { 2107e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2108e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_psw_ipl, a->imm); 2109e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_UPDATE; 2110e5918d7dSYoshinori Sato } 2111e5918d7dSYoshinori Sato return true; 2112e5918d7dSYoshinori Sato } 2113e5918d7dSYoshinori Sato 2114e5918d7dSYoshinori Sato /* mvtc #imm, rd */ 2115e5918d7dSYoshinori Sato static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) 2116e5918d7dSYoshinori Sato { 2117e5918d7dSYoshinori Sato TCGv imm; 2118e5918d7dSYoshinori Sato 2119e5918d7dSYoshinori Sato imm = tcg_const_i32(a->imm); 2120e5918d7dSYoshinori Sato move_to_cr(ctx, imm, a->cr); 2121e5918d7dSYoshinori Sato return true; 2122e5918d7dSYoshinori Sato } 2123e5918d7dSYoshinori Sato 2124e5918d7dSYoshinori Sato /* mvtc rs, rd */ 2125e5918d7dSYoshinori Sato static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) 2126e5918d7dSYoshinori Sato { 2127e5918d7dSYoshinori Sato move_to_cr(ctx, cpu_regs[a->rs], a->cr); 2128e5918d7dSYoshinori Sato return true; 2129e5918d7dSYoshinori Sato } 2130e5918d7dSYoshinori Sato 2131e5918d7dSYoshinori Sato /* mvfc rs, rd */ 2132e5918d7dSYoshinori Sato static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) 2133e5918d7dSYoshinori Sato { 21343626a3feSRichard Henderson move_from_cr(ctx, cpu_regs[a->rd], a->cr, ctx->pc); 2135e5918d7dSYoshinori Sato return true; 2136e5918d7dSYoshinori Sato } 2137e5918d7dSYoshinori Sato 2138e5918d7dSYoshinori Sato /* rtfi */ 2139e5918d7dSYoshinori Sato static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) 2140e5918d7dSYoshinori Sato { 2141e5918d7dSYoshinori Sato TCGv psw; 2142e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2143e5918d7dSYoshinori Sato psw = tcg_temp_new(); 2144e5918d7dSYoshinori Sato tcg_gen_mov_i32(cpu_pc, cpu_bpc); 2145e5918d7dSYoshinori Sato tcg_gen_mov_i32(psw, cpu_bpsw); 2146e5918d7dSYoshinori Sato gen_helper_set_psw_rte(cpu_env, psw); 2147e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_EXIT; 2148e5918d7dSYoshinori Sato } 2149e5918d7dSYoshinori Sato return true; 2150e5918d7dSYoshinori Sato } 2151e5918d7dSYoshinori Sato 2152e5918d7dSYoshinori Sato /* rte */ 2153e5918d7dSYoshinori Sato static bool trans_RTE(DisasContext *ctx, arg_RTE *a) 2154e5918d7dSYoshinori Sato { 2155e5918d7dSYoshinori Sato TCGv psw; 2156e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2157e5918d7dSYoshinori Sato psw = tcg_temp_new(); 2158e5918d7dSYoshinori Sato pop(cpu_pc); 2159e5918d7dSYoshinori Sato pop(psw); 2160e5918d7dSYoshinori Sato gen_helper_set_psw_rte(cpu_env, psw); 2161e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_EXIT; 2162e5918d7dSYoshinori Sato } 2163e5918d7dSYoshinori Sato return true; 2164e5918d7dSYoshinori Sato } 2165e5918d7dSYoshinori Sato 2166e5918d7dSYoshinori Sato /* brk */ 2167e5918d7dSYoshinori Sato static bool trans_BRK(DisasContext *ctx, arg_BRK *a) 2168e5918d7dSYoshinori Sato { 2169e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2170e5918d7dSYoshinori Sato gen_helper_rxbrk(cpu_env); 2171e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_NORETURN; 2172e5918d7dSYoshinori Sato return true; 2173e5918d7dSYoshinori Sato } 2174e5918d7dSYoshinori Sato 2175e5918d7dSYoshinori Sato /* int #imm */ 2176e5918d7dSYoshinori Sato static bool trans_INT(DisasContext *ctx, arg_INT *a) 2177e5918d7dSYoshinori Sato { 2178e5918d7dSYoshinori Sato TCGv vec; 2179e5918d7dSYoshinori Sato 2180e5918d7dSYoshinori Sato tcg_debug_assert(a->imm < 0x100); 2181e5918d7dSYoshinori Sato vec = tcg_const_i32(a->imm); 2182e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2183e5918d7dSYoshinori Sato gen_helper_rxint(cpu_env, vec); 2184e5918d7dSYoshinori Sato ctx->base.is_jmp = DISAS_NORETURN; 2185e5918d7dSYoshinori Sato return true; 2186e5918d7dSYoshinori Sato } 2187e5918d7dSYoshinori Sato 2188e5918d7dSYoshinori Sato /* wait */ 2189e5918d7dSYoshinori Sato static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) 2190e5918d7dSYoshinori Sato { 2191e5918d7dSYoshinori Sato if (is_privileged(ctx, 1)) { 2192724eaeceSTomoaki Kawada tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 2193e5918d7dSYoshinori Sato gen_helper_wait(cpu_env); 2194e5918d7dSYoshinori Sato } 2195e5918d7dSYoshinori Sato return true; 2196e5918d7dSYoshinori Sato } 2197e5918d7dSYoshinori Sato 2198e5918d7dSYoshinori Sato static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 2199e5918d7dSYoshinori Sato { 2200e5918d7dSYoshinori Sato CPURXState *env = cs->env_ptr; 2201e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2202e5918d7dSYoshinori Sato ctx->env = env; 22034341631eSRichard Henderson ctx->tb_flags = ctx->base.tb->flags; 2204e5918d7dSYoshinori Sato } 2205e5918d7dSYoshinori Sato 2206e5918d7dSYoshinori Sato static void rx_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) 2207e5918d7dSYoshinori Sato { 2208e5918d7dSYoshinori Sato } 2209e5918d7dSYoshinori Sato 2210e5918d7dSYoshinori Sato static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 2211e5918d7dSYoshinori Sato { 2212e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2213e5918d7dSYoshinori Sato 2214e5918d7dSYoshinori Sato tcg_gen_insn_start(ctx->base.pc_next); 2215e5918d7dSYoshinori Sato } 2216e5918d7dSYoshinori Sato 2217e5918d7dSYoshinori Sato static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 2218e5918d7dSYoshinori Sato { 2219e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2220e5918d7dSYoshinori Sato uint32_t insn; 2221e5918d7dSYoshinori Sato 2222e5918d7dSYoshinori Sato ctx->pc = ctx->base.pc_next; 2223e5918d7dSYoshinori Sato insn = decode_load(ctx); 2224e5918d7dSYoshinori Sato if (!decode(ctx, insn)) { 2225e5918d7dSYoshinori Sato gen_helper_raise_illegal_instruction(cpu_env); 2226e5918d7dSYoshinori Sato } 2227e5918d7dSYoshinori Sato } 2228e5918d7dSYoshinori Sato 2229e5918d7dSYoshinori Sato static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 2230e5918d7dSYoshinori Sato { 2231e5918d7dSYoshinori Sato DisasContext *ctx = container_of(dcbase, DisasContext, base); 2232e5918d7dSYoshinori Sato 2233e5918d7dSYoshinori Sato switch (ctx->base.is_jmp) { 2234e5918d7dSYoshinori Sato case DISAS_NEXT: 2235e5918d7dSYoshinori Sato case DISAS_TOO_MANY: 2236e5918d7dSYoshinori Sato gen_goto_tb(ctx, 0, dcbase->pc_next); 2237e5918d7dSYoshinori Sato break; 2238e5918d7dSYoshinori Sato case DISAS_JUMP: 2239e5918d7dSYoshinori Sato tcg_gen_lookup_and_goto_ptr(); 2240e5918d7dSYoshinori Sato break; 2241e5918d7dSYoshinori Sato case DISAS_UPDATE: 2242e5918d7dSYoshinori Sato tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); 224340bd0502SPhilippe Mathieu-Daudé /* fall through */ 2244e5918d7dSYoshinori Sato case DISAS_EXIT: 2245e5918d7dSYoshinori Sato tcg_gen_exit_tb(NULL, 0); 2246e5918d7dSYoshinori Sato break; 2247e5918d7dSYoshinori Sato case DISAS_NORETURN: 2248e5918d7dSYoshinori Sato break; 2249e5918d7dSYoshinori Sato default: 2250e5918d7dSYoshinori Sato g_assert_not_reached(); 2251e5918d7dSYoshinori Sato } 2252e5918d7dSYoshinori Sato } 2253e5918d7dSYoshinori Sato 22548eb806a7SRichard Henderson static void rx_tr_disas_log(const DisasContextBase *dcbase, 22558eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 2256e5918d7dSYoshinori Sato { 22578eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 22588eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 2259e5918d7dSYoshinori Sato } 2260e5918d7dSYoshinori Sato 2261e5918d7dSYoshinori Sato static const TranslatorOps rx_tr_ops = { 2262e5918d7dSYoshinori Sato .init_disas_context = rx_tr_init_disas_context, 2263e5918d7dSYoshinori Sato .tb_start = rx_tr_tb_start, 2264e5918d7dSYoshinori Sato .insn_start = rx_tr_insn_start, 2265e5918d7dSYoshinori Sato .translate_insn = rx_tr_translate_insn, 2266e5918d7dSYoshinori Sato .tb_stop = rx_tr_tb_stop, 2267e5918d7dSYoshinori Sato .disas_log = rx_tr_disas_log, 2268e5918d7dSYoshinori Sato }; 2269e5918d7dSYoshinori Sato 2270597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 2271306c8721SRichard Henderson target_ulong pc, void *host_pc) 2272e5918d7dSYoshinori Sato { 2273e5918d7dSYoshinori Sato DisasContext dc; 2274e5918d7dSYoshinori Sato 2275306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base); 2276e5918d7dSYoshinori Sato } 2277e5918d7dSYoshinori Sato 2278e5918d7dSYoshinori Sato #define ALLOC_REGISTER(sym, name) \ 2279e5918d7dSYoshinori Sato cpu_##sym = tcg_global_mem_new_i32(cpu_env, \ 2280e5918d7dSYoshinori Sato offsetof(CPURXState, sym), name) 2281e5918d7dSYoshinori Sato 2282e5918d7dSYoshinori Sato void rx_translate_init(void) 2283e5918d7dSYoshinori Sato { 2284e5918d7dSYoshinori Sato static const char * const regnames[NUM_REGS] = { 2285e5918d7dSYoshinori Sato "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", 2286e5918d7dSYoshinori Sato "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15" 2287e5918d7dSYoshinori Sato }; 2288e5918d7dSYoshinori Sato int i; 2289e5918d7dSYoshinori Sato 2290e5918d7dSYoshinori Sato for (i = 0; i < NUM_REGS; i++) { 2291e5918d7dSYoshinori Sato cpu_regs[i] = tcg_global_mem_new_i32(cpu_env, 2292e5918d7dSYoshinori Sato offsetof(CPURXState, regs[i]), 2293e5918d7dSYoshinori Sato regnames[i]); 2294e5918d7dSYoshinori Sato } 2295e5918d7dSYoshinori Sato ALLOC_REGISTER(pc, "PC"); 2296e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_o, "PSW(O)"); 2297e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_s, "PSW(S)"); 2298e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_z, "PSW(Z)"); 2299e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_c, "PSW(C)"); 2300e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_u, "PSW(U)"); 2301e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_i, "PSW(I)"); 2302e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_pm, "PSW(PM)"); 2303e5918d7dSYoshinori Sato ALLOC_REGISTER(psw_ipl, "PSW(IPL)"); 2304e5918d7dSYoshinori Sato ALLOC_REGISTER(usp, "USP"); 2305e5918d7dSYoshinori Sato ALLOC_REGISTER(fpsw, "FPSW"); 2306e5918d7dSYoshinori Sato ALLOC_REGISTER(bpsw, "BPSW"); 2307e5918d7dSYoshinori Sato ALLOC_REGISTER(bpc, "BPC"); 2308e5918d7dSYoshinori Sato ALLOC_REGISTER(isp, "ISP"); 2309e5918d7dSYoshinori Sato ALLOC_REGISTER(fintv, "FINTV"); 2310e5918d7dSYoshinori Sato ALLOC_REGISTER(intb, "INTB"); 2311e5918d7dSYoshinori Sato cpu_acc = tcg_global_mem_new_i64(cpu_env, 2312e5918d7dSYoshinori Sato offsetof(CPURXState, acc), "ACC"); 2313e5918d7dSYoshinori Sato } 2314