1# 2# Translation routines for the instructions of the XThead* ISA extensions 3# 4# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu 5# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu 6# 7# SPDX-License-Identifier: LGPL-2.1-or-later 8# 9# The documentation of the ISA extensions can be found here: 10# https://github.com/T-head-Semi/thead-extension-spec/releases/latest 11 12# Fields: 13%rd 7:5 14%rs1 15:5 15%rs2 20:5 16 17# Argument sets 18&r rd rs1 rs2 !extern 19 20# Formats 21@sfence_vm ....... ..... ..... ... ..... ....... %rs1 22@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 23@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 24 25# XTheadBa 26# Instead of defining a new encoding, we simply use the decoder to 27# extract the imm[0:1] field and dispatch to separate translation 28# functions (mirroring the `sh[123]add` instructions from Zba and 29# the regular RVI `add` instruction. 30# 31# The only difference between sh[123]add and addsl is that the shift 32# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add). 33# 34# Note that shift-by-0 is a valid operation according to the manual. 35# This will be equivalent to a regular add. 36add 0000000 ..... ..... 001 ..... 0001011 @r 37th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r 38th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r 39th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r 40 41# XTheadCmo 42th_dcache_call 0000000 00001 00000 000 00000 0001011 43th_dcache_ciall 0000000 00011 00000 000 00000 0001011 44th_dcache_iall 0000000 00010 00000 000 00000 0001011 45th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm 46th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm 47th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm 48th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm 49th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm 50th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm 51th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm 52th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm 53th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm 54th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm 55th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm 56th_icache_iall 0000000 10000 00000 000 00000 0001011 57th_icache_ialls 0000000 10001 00000 000 00000 0001011 58th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm 59th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm 60th_l2cache_call 0000000 10101 00000 000 00000 0001011 61th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 62th_l2cache_iall 0000000 10110 00000 000 00000 0001011 63 64# XTheadSync 65th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s 66th_sync 0000000 11000 00000 000 00000 0001011 67th_sync_i 0000000 11010 00000 000 00000 0001011 68th_sync_is 0000000 11011 00000 000 00000 0001011 69th_sync_s 0000000 11001 00000 000 00000 0001011 70