#
# Translation routines for the instructions of the XThead* ISA extensions
#
# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
#                    Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
# The documentation of the ISA extensions can be found here:
#   https://github.com/T-head-Semi/thead-extension-spec/releases/latest

# Fields:
%rd        7:5
%rs1       15:5
%rs2       20:5

# Argument sets
&r         rd rs1 rs2                               !extern

# Formats
@sfence_vm  ....... ..... .....   ... ..... ....... %rs1
@rs2_s      ....... ..... ..... ... ..... .......   %rs2 %rs1
@r          ....... ..... .....  ... ..... .......  &r %rs2 %rs1 %rd

# XTheadBa
# Instead of defining a new encoding, we simply use the decoder to
# extract the imm[0:1] field and dispatch to separate translation
# functions (mirroring the `sh[123]add` instructions from Zba and
# the regular RVI `add` instruction.
#
# The only difference between sh[123]add and addsl is that the shift
# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
#
# Note that shift-by-0 is a valid operation according to the manual.
# This will be equivalent to a regular add.
add              0000000 ..... ..... 001 ..... 0001011 @r
th_addsl1        0000001 ..... ..... 001 ..... 0001011 @r
th_addsl2        0000010 ..... ..... 001 ..... 0001011 @r
th_addsl3        0000011 ..... ..... 001 ..... 0001011 @r

# XTheadCmo
th_dcache_call   0000000 00001 00000 000 00000 0001011
th_dcache_ciall  0000000 00011 00000 000 00000 0001011
th_dcache_iall   0000000 00010 00000 000 00000 0001011
th_dcache_cpa    0000001 01001 ..... 000 00000 0001011 @sfence_vm
th_dcache_cipa   0000001 01011 ..... 000 00000 0001011 @sfence_vm
th_dcache_ipa    0000001 01010 ..... 000 00000 0001011 @sfence_vm
th_dcache_cva    0000001 00101 ..... 000 00000 0001011 @sfence_vm
th_dcache_civa   0000001 00111 ..... 000 00000 0001011 @sfence_vm
th_dcache_iva    0000001 00110 ..... 000 00000 0001011 @sfence_vm
th_dcache_csw    0000001 00001 ..... 000 00000 0001011 @sfence_vm
th_dcache_cisw   0000001 00011 ..... 000 00000 0001011 @sfence_vm
th_dcache_isw    0000001 00010 ..... 000 00000 0001011 @sfence_vm
th_dcache_cpal1  0000001 01000 ..... 000 00000 0001011 @sfence_vm
th_dcache_cval1  0000001 00100 ..... 000 00000 0001011 @sfence_vm
th_icache_iall   0000000 10000 00000 000 00000 0001011
th_icache_ialls  0000000 10001 00000 000 00000 0001011
th_icache_ipa    0000001 11000 ..... 000 00000 0001011 @sfence_vm
th_icache_iva    0000001 10000 ..... 000 00000 0001011 @sfence_vm
th_l2cache_call  0000000 10101 00000 000 00000 0001011
th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
th_l2cache_iall  0000000 10110 00000 000 00000 0001011

# XTheadSync
th_sfence_vmas   0000010 ..... ..... 000 00000 0001011 @rs2_s
th_sync          0000000 11000 00000 000 00000 0001011
th_sync_i        0000000 11010 00000 000 00000 0001011
th_sync_is       0000000 11011 00000 000 00000 0001011
th_sync_s        0000000 11001 00000 000 00000 0001011