xref: /openbmc/qemu/target/riscv/trace-events (revision b097ba37)
1# target/riscv/cpu_helper.c
2riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"
3