xref: /openbmc/qemu/target/riscv/trace-events (revision 929f0a7fc40d7123ddda4c9dbd78a1806999b4f7)
1*929f0a7fSMichael Clark# target/riscv/cpu_helper.c
2*929f0a7fSMichael Clarkriscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"
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