1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 #include "qemu/main-loop.h" 30 #include "exec/cpu_ldst.h" 31 32 #include "exec/helper-proto.h" 33 #include "exec/helper-gen.h" 34 35 #include "exec/translator.h" 36 #include "exec/log.h" 37 #include "qemu/atomic128.h" 38 #include "spr_tcg.h" 39 40 #include "qemu/qemu-print.h" 41 #include "qapi/error.h" 42 43 #define CPU_SINGLE_STEP 0x1 44 #define CPU_BRANCH_STEP 0x2 45 #define GDBSTUB_SINGLE_STEP 0x4 46 47 /* Include definitions for instructions classes and implementations flags */ 48 /* #define PPC_DEBUG_DISAS */ 49 50 #ifdef PPC_DEBUG_DISAS 51 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 52 #else 53 # define LOG_DISAS(...) do { } while (0) 54 #endif 55 /*****************************************************************************/ 56 /* Code translation helpers */ 57 58 /* global register indexes */ 59 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 60 + 10 * 4 + 22 * 5 /* SPE GPRh */ 61 + 8 * 5 /* CRF */]; 62 static TCGv cpu_gpr[32]; 63 static TCGv cpu_gprh[32]; 64 static TCGv_i32 cpu_crf[8]; 65 static TCGv cpu_nip; 66 static TCGv cpu_msr; 67 static TCGv cpu_ctr; 68 static TCGv cpu_lr; 69 #if defined(TARGET_PPC64) 70 static TCGv cpu_cfar; 71 #endif 72 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 73 static TCGv cpu_reserve; 74 static TCGv cpu_reserve_val; 75 static TCGv cpu_fpscr; 76 static TCGv_i32 cpu_access_type; 77 78 #include "exec/gen-icount.h" 79 80 void ppc_translate_init(void) 81 { 82 int i; 83 char *p; 84 size_t cpu_reg_names_size; 85 86 p = cpu_reg_names; 87 cpu_reg_names_size = sizeof(cpu_reg_names); 88 89 for (i = 0; i < 8; i++) { 90 snprintf(p, cpu_reg_names_size, "crf%d", i); 91 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 92 offsetof(CPUPPCState, crf[i]), p); 93 p += 5; 94 cpu_reg_names_size -= 5; 95 } 96 97 for (i = 0; i < 32; i++) { 98 snprintf(p, cpu_reg_names_size, "r%d", i); 99 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 100 offsetof(CPUPPCState, gpr[i]), p); 101 p += (i < 10) ? 3 : 4; 102 cpu_reg_names_size -= (i < 10) ? 3 : 4; 103 snprintf(p, cpu_reg_names_size, "r%dH", i); 104 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 105 offsetof(CPUPPCState, gprh[i]), p); 106 p += (i < 10) ? 4 : 5; 107 cpu_reg_names_size -= (i < 10) ? 4 : 5; 108 } 109 110 cpu_nip = tcg_global_mem_new(cpu_env, 111 offsetof(CPUPPCState, nip), "nip"); 112 113 cpu_msr = tcg_global_mem_new(cpu_env, 114 offsetof(CPUPPCState, msr), "msr"); 115 116 cpu_ctr = tcg_global_mem_new(cpu_env, 117 offsetof(CPUPPCState, ctr), "ctr"); 118 119 cpu_lr = tcg_global_mem_new(cpu_env, 120 offsetof(CPUPPCState, lr), "lr"); 121 122 #if defined(TARGET_PPC64) 123 cpu_cfar = tcg_global_mem_new(cpu_env, 124 offsetof(CPUPPCState, cfar), "cfar"); 125 #endif 126 127 cpu_xer = tcg_global_mem_new(cpu_env, 128 offsetof(CPUPPCState, xer), "xer"); 129 cpu_so = tcg_global_mem_new(cpu_env, 130 offsetof(CPUPPCState, so), "SO"); 131 cpu_ov = tcg_global_mem_new(cpu_env, 132 offsetof(CPUPPCState, ov), "OV"); 133 cpu_ca = tcg_global_mem_new(cpu_env, 134 offsetof(CPUPPCState, ca), "CA"); 135 cpu_ov32 = tcg_global_mem_new(cpu_env, 136 offsetof(CPUPPCState, ov32), "OV32"); 137 cpu_ca32 = tcg_global_mem_new(cpu_env, 138 offsetof(CPUPPCState, ca32), "CA32"); 139 140 cpu_reserve = tcg_global_mem_new(cpu_env, 141 offsetof(CPUPPCState, reserve_addr), 142 "reserve_addr"); 143 cpu_reserve_val = tcg_global_mem_new(cpu_env, 144 offsetof(CPUPPCState, reserve_val), 145 "reserve_val"); 146 147 cpu_fpscr = tcg_global_mem_new(cpu_env, 148 offsetof(CPUPPCState, fpscr), "fpscr"); 149 150 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 151 offsetof(CPUPPCState, access_type), 152 "access_type"); 153 } 154 155 /* internal defines */ 156 struct DisasContext { 157 DisasContextBase base; 158 target_ulong cia; /* current instruction address */ 159 uint32_t opcode; 160 /* Routine used to access memory */ 161 bool pr, hv, dr, le_mode; 162 bool lazy_tlb_flush; 163 bool need_access_type; 164 int mem_idx; 165 int access_type; 166 /* Translation flags */ 167 MemOp default_tcg_memop_mask; 168 #if defined(TARGET_PPC64) 169 bool sf_mode; 170 bool has_cfar; 171 #endif 172 bool fpu_enabled; 173 bool altivec_enabled; 174 bool vsx_enabled; 175 bool spe_enabled; 176 bool tm_enabled; 177 bool gtse; 178 bool hr; 179 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 180 int singlestep_enabled; 181 uint32_t flags; 182 uint64_t insns_flags; 183 uint64_t insns_flags2; 184 }; 185 186 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 187 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 188 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 189 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 190 191 /* Return true iff byteswap is needed in a scalar memop */ 192 static inline bool need_byteswap(const DisasContext *ctx) 193 { 194 #if defined(TARGET_WORDS_BIGENDIAN) 195 return ctx->le_mode; 196 #else 197 return !ctx->le_mode; 198 #endif 199 } 200 201 /* True when active word size < size of target_long. */ 202 #ifdef TARGET_PPC64 203 # define NARROW_MODE(C) (!(C)->sf_mode) 204 #else 205 # define NARROW_MODE(C) 0 206 #endif 207 208 struct opc_handler_t { 209 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 210 uint32_t inval1; 211 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 212 uint32_t inval2; 213 /* instruction type */ 214 uint64_t type; 215 /* extended instruction type */ 216 uint64_t type2; 217 /* handler */ 218 void (*handler)(DisasContext *ctx); 219 }; 220 221 /* SPR load/store helpers */ 222 static inline void gen_load_spr(TCGv t, int reg) 223 { 224 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 225 } 226 227 static inline void gen_store_spr(int reg, TCGv t) 228 { 229 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 230 } 231 232 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 233 { 234 if (ctx->need_access_type && ctx->access_type != access_type) { 235 tcg_gen_movi_i32(cpu_access_type, access_type); 236 ctx->access_type = access_type; 237 } 238 } 239 240 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 241 { 242 if (NARROW_MODE(ctx)) { 243 nip = (uint32_t)nip; 244 } 245 tcg_gen_movi_tl(cpu_nip, nip); 246 } 247 248 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 249 { 250 TCGv_i32 t0, t1; 251 252 /* 253 * These are all synchronous exceptions, we set the PC back to the 254 * faulting instruction 255 */ 256 gen_update_nip(ctx, ctx->cia); 257 t0 = tcg_const_i32(excp); 258 t1 = tcg_const_i32(error); 259 gen_helper_raise_exception_err(cpu_env, t0, t1); 260 tcg_temp_free_i32(t0); 261 tcg_temp_free_i32(t1); 262 ctx->base.is_jmp = DISAS_NORETURN; 263 } 264 265 static void gen_exception(DisasContext *ctx, uint32_t excp) 266 { 267 TCGv_i32 t0; 268 269 /* 270 * These are all synchronous exceptions, we set the PC back to the 271 * faulting instruction 272 */ 273 gen_update_nip(ctx, ctx->cia); 274 t0 = tcg_const_i32(excp); 275 gen_helper_raise_exception(cpu_env, t0); 276 tcg_temp_free_i32(t0); 277 ctx->base.is_jmp = DISAS_NORETURN; 278 } 279 280 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 281 target_ulong nip) 282 { 283 TCGv_i32 t0; 284 285 gen_update_nip(ctx, nip); 286 t0 = tcg_const_i32(excp); 287 gen_helper_raise_exception(cpu_env, t0); 288 tcg_temp_free_i32(t0); 289 ctx->base.is_jmp = DISAS_NORETURN; 290 } 291 292 static void gen_icount_io_start(DisasContext *ctx) 293 { 294 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 295 gen_io_start(); 296 /* 297 * An I/O instruction must be last in the TB. 298 * Chain to the next TB, and let the code from gen_tb_start 299 * decide if we need to return to the main loop. 300 * Doing this first also allows this value to be overridden. 301 */ 302 ctx->base.is_jmp = DISAS_TOO_MANY; 303 } 304 } 305 306 /* 307 * Tells the caller what is the appropriate exception to generate and prepares 308 * SPR registers for this exception. 309 * 310 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 311 * POWERPC_EXCP_DEBUG (on BookE). 312 */ 313 static uint32_t gen_prep_dbgex(DisasContext *ctx) 314 { 315 if (ctx->flags & POWERPC_FLAG_DE) { 316 target_ulong dbsr = 0; 317 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 318 dbsr = DBCR0_ICMP; 319 } else { 320 /* Must have been branch */ 321 dbsr = DBCR0_BRT; 322 } 323 TCGv t0 = tcg_temp_new(); 324 gen_load_spr(t0, SPR_BOOKE_DBSR); 325 tcg_gen_ori_tl(t0, t0, dbsr); 326 gen_store_spr(SPR_BOOKE_DBSR, t0); 327 tcg_temp_free(t0); 328 return POWERPC_EXCP_DEBUG; 329 } else { 330 return POWERPC_EXCP_TRACE; 331 } 332 } 333 334 static void gen_debug_exception(DisasContext *ctx) 335 { 336 gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); 337 ctx->base.is_jmp = DISAS_NORETURN; 338 } 339 340 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 341 { 342 /* Will be converted to program check if needed */ 343 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 344 } 345 346 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 347 { 348 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 349 } 350 351 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 352 { 353 /* Will be converted to program check if needed */ 354 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 355 } 356 357 /*****************************************************************************/ 358 /* SPR READ/WRITE CALLBACKS */ 359 360 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 361 { 362 #if 0 363 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 364 printf("ERROR: try to access SPR %d !\n", sprn); 365 #endif 366 } 367 368 /* #define PPC_DUMP_SPR_ACCESSES */ 369 370 /* 371 * Generic callbacks: 372 * do nothing but store/retrieve spr value 373 */ 374 static void spr_load_dump_spr(int sprn) 375 { 376 #ifdef PPC_DUMP_SPR_ACCESSES 377 TCGv_i32 t0 = tcg_const_i32(sprn); 378 gen_helper_load_dump_spr(cpu_env, t0); 379 tcg_temp_free_i32(t0); 380 #endif 381 } 382 383 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 384 { 385 gen_load_spr(cpu_gpr[gprn], sprn); 386 spr_load_dump_spr(sprn); 387 } 388 389 static void spr_store_dump_spr(int sprn) 390 { 391 #ifdef PPC_DUMP_SPR_ACCESSES 392 TCGv_i32 t0 = tcg_const_i32(sprn); 393 gen_helper_store_dump_spr(cpu_env, t0); 394 tcg_temp_free_i32(t0); 395 #endif 396 } 397 398 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 399 { 400 gen_store_spr(sprn, cpu_gpr[gprn]); 401 spr_store_dump_spr(sprn); 402 } 403 404 #if !defined(CONFIG_USER_ONLY) 405 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 406 { 407 #ifdef TARGET_PPC64 408 TCGv t0 = tcg_temp_new(); 409 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 410 gen_store_spr(sprn, t0); 411 tcg_temp_free(t0); 412 spr_store_dump_spr(sprn); 413 #else 414 spr_write_generic(ctx, sprn, gprn); 415 #endif 416 } 417 418 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 419 { 420 TCGv t0 = tcg_temp_new(); 421 TCGv t1 = tcg_temp_new(); 422 gen_load_spr(t0, sprn); 423 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 424 tcg_gen_and_tl(t0, t0, t1); 425 gen_store_spr(sprn, t0); 426 tcg_temp_free(t0); 427 tcg_temp_free(t1); 428 } 429 430 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 431 { 432 } 433 434 #endif 435 436 /* SPR common to all PowerPC */ 437 /* XER */ 438 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 439 { 440 TCGv dst = cpu_gpr[gprn]; 441 TCGv t0 = tcg_temp_new(); 442 TCGv t1 = tcg_temp_new(); 443 TCGv t2 = tcg_temp_new(); 444 tcg_gen_mov_tl(dst, cpu_xer); 445 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 446 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 447 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 448 tcg_gen_or_tl(t0, t0, t1); 449 tcg_gen_or_tl(dst, dst, t2); 450 tcg_gen_or_tl(dst, dst, t0); 451 if (is_isa300(ctx)) { 452 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 453 tcg_gen_or_tl(dst, dst, t0); 454 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 455 tcg_gen_or_tl(dst, dst, t0); 456 } 457 tcg_temp_free(t0); 458 tcg_temp_free(t1); 459 tcg_temp_free(t2); 460 } 461 462 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 463 { 464 TCGv src = cpu_gpr[gprn]; 465 /* Write all flags, while reading back check for isa300 */ 466 tcg_gen_andi_tl(cpu_xer, src, 467 ~((1u << XER_SO) | 468 (1u << XER_OV) | (1u << XER_OV32) | 469 (1u << XER_CA) | (1u << XER_CA32))); 470 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 471 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 472 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 473 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 474 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 475 } 476 477 /* LR */ 478 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 479 { 480 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 481 } 482 483 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 484 { 485 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 486 } 487 488 /* CFAR */ 489 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 490 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 491 { 492 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 493 } 494 495 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 496 { 497 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 498 } 499 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 500 501 /* CTR */ 502 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 503 { 504 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 505 } 506 507 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 508 { 509 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 510 } 511 512 /* User read access to SPR */ 513 /* USPRx */ 514 /* UMMCRx */ 515 /* UPMCx */ 516 /* USIA */ 517 /* UDECR */ 518 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 519 { 520 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 521 } 522 523 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 524 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 525 { 526 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 527 } 528 #endif 529 530 /* SPR common to all non-embedded PowerPC */ 531 /* DECR */ 532 #if !defined(CONFIG_USER_ONLY) 533 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 534 { 535 gen_icount_io_start(ctx); 536 gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 537 } 538 539 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 540 { 541 gen_icount_io_start(ctx); 542 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 543 } 544 #endif 545 546 /* SPR common to all non-embedded PowerPC, except 601 */ 547 /* Time base */ 548 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 549 { 550 gen_icount_io_start(ctx); 551 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 552 } 553 554 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 555 { 556 gen_icount_io_start(ctx); 557 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 558 } 559 560 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 561 { 562 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 563 } 564 565 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 566 { 567 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 568 } 569 570 #if !defined(CONFIG_USER_ONLY) 571 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 572 { 573 gen_icount_io_start(ctx); 574 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 575 } 576 577 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 578 { 579 gen_icount_io_start(ctx); 580 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 581 } 582 583 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 584 { 585 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 586 } 587 588 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 589 { 590 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 591 } 592 593 #if defined(TARGET_PPC64) 594 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 595 { 596 gen_icount_io_start(ctx); 597 gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 598 } 599 600 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 601 { 602 gen_icount_io_start(ctx); 603 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 604 } 605 606 /* HDECR */ 607 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 608 { 609 gen_icount_io_start(ctx); 610 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 611 } 612 613 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 614 { 615 gen_icount_io_start(ctx); 616 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 617 } 618 619 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 620 { 621 gen_icount_io_start(ctx); 622 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 623 } 624 625 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 626 { 627 gen_icount_io_start(ctx); 628 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 629 } 630 631 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 632 { 633 gen_icount_io_start(ctx); 634 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 635 } 636 637 #endif 638 #endif 639 640 #if !defined(CONFIG_USER_ONLY) 641 /* IBAT0U...IBAT0U */ 642 /* IBAT0L...IBAT7L */ 643 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 644 { 645 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 646 offsetof(CPUPPCState, 647 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 648 } 649 650 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 651 { 652 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 653 offsetof(CPUPPCState, 654 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 655 } 656 657 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 658 { 659 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 660 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 661 tcg_temp_free_i32(t0); 662 } 663 664 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 665 { 666 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 667 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 668 tcg_temp_free_i32(t0); 669 } 670 671 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 672 { 673 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 674 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 675 tcg_temp_free_i32(t0); 676 } 677 678 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 679 { 680 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 681 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 682 tcg_temp_free_i32(t0); 683 } 684 685 /* DBAT0U...DBAT7U */ 686 /* DBAT0L...DBAT7L */ 687 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 688 { 689 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 690 offsetof(CPUPPCState, 691 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 692 } 693 694 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 695 { 696 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 697 offsetof(CPUPPCState, 698 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 699 } 700 701 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 702 { 703 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 704 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 705 tcg_temp_free_i32(t0); 706 } 707 708 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 709 { 710 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 711 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 712 tcg_temp_free_i32(t0); 713 } 714 715 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 716 { 717 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 718 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 719 tcg_temp_free_i32(t0); 720 } 721 722 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 723 { 724 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 725 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 726 tcg_temp_free_i32(t0); 727 } 728 729 /* SDR1 */ 730 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 731 { 732 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 733 } 734 735 #if defined(TARGET_PPC64) 736 /* 64 bits PowerPC specific SPRs */ 737 /* PIDR */ 738 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 739 { 740 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 741 } 742 743 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 744 { 745 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 746 } 747 748 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 749 { 750 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 751 } 752 753 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 754 { 755 TCGv t0 = tcg_temp_new(); 756 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 757 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 758 tcg_temp_free(t0); 759 } 760 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 761 { 762 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 763 } 764 765 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 766 { 767 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 768 } 769 770 /* DPDES */ 771 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 772 { 773 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 774 } 775 776 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 777 { 778 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 779 } 780 #endif 781 #endif 782 783 /* PowerPC 601 specific registers */ 784 /* RTC */ 785 void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 786 { 787 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 788 } 789 790 void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 791 { 792 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 793 } 794 795 #if !defined(CONFIG_USER_ONLY) 796 void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 797 { 798 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 799 } 800 801 void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 802 { 803 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 804 } 805 806 void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 807 { 808 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 809 /* Must stop the translation as endianness may have changed */ 810 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 811 } 812 #endif 813 814 /* Unified bats */ 815 #if !defined(CONFIG_USER_ONLY) 816 void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 817 { 818 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 819 offsetof(CPUPPCState, 820 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 821 } 822 823 void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 824 { 825 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 826 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 827 tcg_temp_free_i32(t0); 828 } 829 830 void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 831 { 832 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 833 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 834 tcg_temp_free_i32(t0); 835 } 836 #endif 837 838 /* PowerPC 40x specific registers */ 839 #if !defined(CONFIG_USER_ONLY) 840 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 841 { 842 gen_icount_io_start(ctx); 843 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 844 } 845 846 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 847 { 848 gen_icount_io_start(ctx); 849 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 850 } 851 852 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 853 { 854 gen_icount_io_start(ctx); 855 gen_store_spr(sprn, cpu_gpr[gprn]); 856 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 857 /* We must stop translation as we may have rebooted */ 858 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 859 } 860 861 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 862 { 863 gen_icount_io_start(ctx); 864 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 865 } 866 867 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 868 { 869 gen_icount_io_start(ctx); 870 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 871 } 872 873 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 874 { 875 gen_icount_io_start(ctx); 876 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 877 } 878 #endif 879 880 /* PowerPC 403 specific registers */ 881 /* PBL1 / PBU1 / PBL2 / PBU2 */ 882 #if !defined(CONFIG_USER_ONLY) 883 void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 884 { 885 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 886 offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 887 } 888 889 void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 890 { 891 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 892 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 893 tcg_temp_free_i32(t0); 894 } 895 896 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 897 { 898 TCGv t0 = tcg_temp_new(); 899 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 900 gen_store_spr(SPR_PIR, t0); 901 tcg_temp_free(t0); 902 } 903 #endif 904 905 /* SPE specific registers */ 906 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 907 { 908 TCGv_i32 t0 = tcg_temp_new_i32(); 909 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 910 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 911 tcg_temp_free_i32(t0); 912 } 913 914 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 915 { 916 TCGv_i32 t0 = tcg_temp_new_i32(); 917 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 918 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 919 tcg_temp_free_i32(t0); 920 } 921 922 #if !defined(CONFIG_USER_ONLY) 923 /* Callback used to write the exception vector base */ 924 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 925 { 926 TCGv t0 = tcg_temp_new(); 927 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 928 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 929 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 930 gen_store_spr(sprn, t0); 931 tcg_temp_free(t0); 932 } 933 934 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 935 { 936 int sprn_offs; 937 938 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 939 sprn_offs = sprn - SPR_BOOKE_IVOR0; 940 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 941 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 942 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 943 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 944 } else { 945 printf("Trying to write an unknown exception vector %d %03x\n", 946 sprn, sprn); 947 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 948 return; 949 } 950 951 TCGv t0 = tcg_temp_new(); 952 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 953 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 954 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 955 gen_store_spr(sprn, t0); 956 tcg_temp_free(t0); 957 } 958 #endif 959 960 #ifdef TARGET_PPC64 961 #ifndef CONFIG_USER_ONLY 962 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 963 { 964 TCGv t0 = tcg_temp_new(); 965 TCGv t1 = tcg_temp_new(); 966 TCGv t2 = tcg_temp_new(); 967 968 /* 969 * Note, the HV=1 PR=0 case is handled earlier by simply using 970 * spr_write_generic for HV mode in the SPR table 971 */ 972 973 /* Build insertion mask into t1 based on context */ 974 if (ctx->pr) { 975 gen_load_spr(t1, SPR_UAMOR); 976 } else { 977 gen_load_spr(t1, SPR_AMOR); 978 } 979 980 /* Mask new bits into t2 */ 981 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 982 983 /* Load AMR and clear new bits in t0 */ 984 gen_load_spr(t0, SPR_AMR); 985 tcg_gen_andc_tl(t0, t0, t1); 986 987 /* Or'in new bits and write it out */ 988 tcg_gen_or_tl(t0, t0, t2); 989 gen_store_spr(SPR_AMR, t0); 990 spr_store_dump_spr(SPR_AMR); 991 992 tcg_temp_free(t0); 993 tcg_temp_free(t1); 994 tcg_temp_free(t2); 995 } 996 997 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 998 { 999 TCGv t0 = tcg_temp_new(); 1000 TCGv t1 = tcg_temp_new(); 1001 TCGv t2 = tcg_temp_new(); 1002 1003 /* 1004 * Note, the HV=1 case is handled earlier by simply using 1005 * spr_write_generic for HV mode in the SPR table 1006 */ 1007 1008 /* Build insertion mask into t1 based on context */ 1009 gen_load_spr(t1, SPR_AMOR); 1010 1011 /* Mask new bits into t2 */ 1012 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1013 1014 /* Load AMR and clear new bits in t0 */ 1015 gen_load_spr(t0, SPR_UAMOR); 1016 tcg_gen_andc_tl(t0, t0, t1); 1017 1018 /* Or'in new bits and write it out */ 1019 tcg_gen_or_tl(t0, t0, t2); 1020 gen_store_spr(SPR_UAMOR, t0); 1021 spr_store_dump_spr(SPR_UAMOR); 1022 1023 tcg_temp_free(t0); 1024 tcg_temp_free(t1); 1025 tcg_temp_free(t2); 1026 } 1027 1028 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1029 { 1030 TCGv t0 = tcg_temp_new(); 1031 TCGv t1 = tcg_temp_new(); 1032 TCGv t2 = tcg_temp_new(); 1033 1034 /* 1035 * Note, the HV=1 case is handled earlier by simply using 1036 * spr_write_generic for HV mode in the SPR table 1037 */ 1038 1039 /* Build insertion mask into t1 based on context */ 1040 gen_load_spr(t1, SPR_AMOR); 1041 1042 /* Mask new bits into t2 */ 1043 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1044 1045 /* Load AMR and clear new bits in t0 */ 1046 gen_load_spr(t0, SPR_IAMR); 1047 tcg_gen_andc_tl(t0, t0, t1); 1048 1049 /* Or'in new bits and write it out */ 1050 tcg_gen_or_tl(t0, t0, t2); 1051 gen_store_spr(SPR_IAMR, t0); 1052 spr_store_dump_spr(SPR_IAMR); 1053 1054 tcg_temp_free(t0); 1055 tcg_temp_free(t1); 1056 tcg_temp_free(t2); 1057 } 1058 #endif 1059 #endif 1060 1061 #ifndef CONFIG_USER_ONLY 1062 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1063 { 1064 gen_helper_fixup_thrm(cpu_env); 1065 gen_load_spr(cpu_gpr[gprn], sprn); 1066 spr_load_dump_spr(sprn); 1067 } 1068 #endif /* !CONFIG_USER_ONLY */ 1069 1070 #if !defined(CONFIG_USER_ONLY) 1071 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1072 { 1073 TCGv t0 = tcg_temp_new(); 1074 1075 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1076 gen_store_spr(sprn, t0); 1077 tcg_temp_free(t0); 1078 } 1079 1080 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1081 { 1082 TCGv t0 = tcg_temp_new(); 1083 1084 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1085 gen_store_spr(sprn, t0); 1086 tcg_temp_free(t0); 1087 } 1088 1089 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1090 { 1091 TCGv t0 = tcg_temp_new(); 1092 1093 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1094 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1095 gen_store_spr(sprn, t0); 1096 tcg_temp_free(t0); 1097 } 1098 1099 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1100 { 1101 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1102 } 1103 1104 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1105 { 1106 TCGv_i32 t0 = tcg_const_i32(sprn); 1107 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1108 tcg_temp_free_i32(t0); 1109 } 1110 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1111 { 1112 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1113 } 1114 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1115 { 1116 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1117 } 1118 1119 #endif 1120 1121 #if !defined(CONFIG_USER_ONLY) 1122 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1123 { 1124 TCGv val = tcg_temp_new(); 1125 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1126 gen_store_spr(SPR_BOOKE_MAS3, val); 1127 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1128 gen_store_spr(SPR_BOOKE_MAS7, val); 1129 tcg_temp_free(val); 1130 } 1131 1132 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1133 { 1134 TCGv mas7 = tcg_temp_new(); 1135 TCGv mas3 = tcg_temp_new(); 1136 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1137 tcg_gen_shli_tl(mas7, mas7, 32); 1138 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1139 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1140 tcg_temp_free(mas3); 1141 tcg_temp_free(mas7); 1142 } 1143 1144 #endif 1145 1146 #ifdef TARGET_PPC64 1147 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1148 int bit, int sprn, int cause) 1149 { 1150 TCGv_i32 t1 = tcg_const_i32(bit); 1151 TCGv_i32 t2 = tcg_const_i32(sprn); 1152 TCGv_i32 t3 = tcg_const_i32(cause); 1153 1154 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 1155 1156 tcg_temp_free_i32(t3); 1157 tcg_temp_free_i32(t2); 1158 tcg_temp_free_i32(t1); 1159 } 1160 1161 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1162 int bit, int sprn, int cause) 1163 { 1164 TCGv_i32 t1 = tcg_const_i32(bit); 1165 TCGv_i32 t2 = tcg_const_i32(sprn); 1166 TCGv_i32 t3 = tcg_const_i32(cause); 1167 1168 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 1169 1170 tcg_temp_free_i32(t3); 1171 tcg_temp_free_i32(t2); 1172 tcg_temp_free_i32(t1); 1173 } 1174 1175 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1176 { 1177 TCGv spr_up = tcg_temp_new(); 1178 TCGv spr = tcg_temp_new(); 1179 1180 gen_load_spr(spr, sprn - 1); 1181 tcg_gen_shri_tl(spr_up, spr, 32); 1182 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1183 1184 tcg_temp_free(spr); 1185 tcg_temp_free(spr_up); 1186 } 1187 1188 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1189 { 1190 TCGv spr = tcg_temp_new(); 1191 1192 gen_load_spr(spr, sprn - 1); 1193 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1194 gen_store_spr(sprn - 1, spr); 1195 1196 tcg_temp_free(spr); 1197 } 1198 1199 #if !defined(CONFIG_USER_ONLY) 1200 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1201 { 1202 TCGv hmer = tcg_temp_new(); 1203 1204 gen_load_spr(hmer, sprn); 1205 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1206 gen_store_spr(sprn, hmer); 1207 spr_store_dump_spr(sprn); 1208 tcg_temp_free(hmer); 1209 } 1210 1211 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1212 { 1213 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 1214 } 1215 #endif /* !defined(CONFIG_USER_ONLY) */ 1216 1217 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1218 { 1219 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1220 spr_read_generic(ctx, gprn, sprn); 1221 } 1222 1223 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1224 { 1225 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1226 spr_write_generic(ctx, sprn, gprn); 1227 } 1228 1229 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1230 { 1231 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1232 spr_read_generic(ctx, gprn, sprn); 1233 } 1234 1235 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1236 { 1237 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1238 spr_write_generic(ctx, sprn, gprn); 1239 } 1240 1241 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1242 { 1243 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1244 spr_read_prev_upper32(ctx, gprn, sprn); 1245 } 1246 1247 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1248 { 1249 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1250 spr_write_prev_upper32(ctx, sprn, gprn); 1251 } 1252 1253 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1254 { 1255 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1256 spr_read_generic(ctx, gprn, sprn); 1257 } 1258 1259 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1260 { 1261 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1262 spr_write_generic(ctx, sprn, gprn); 1263 } 1264 1265 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1266 { 1267 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1268 spr_read_prev_upper32(ctx, gprn, sprn); 1269 } 1270 1271 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1272 { 1273 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1274 spr_write_prev_upper32(ctx, sprn, gprn); 1275 } 1276 #endif 1277 1278 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1279 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1280 1281 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1282 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1283 1284 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1285 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1286 1287 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1288 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1289 1290 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1291 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1292 1293 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1294 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1295 1296 typedef struct opcode_t { 1297 unsigned char opc1, opc2, opc3, opc4; 1298 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1299 unsigned char pad[4]; 1300 #endif 1301 opc_handler_t handler; 1302 const char *oname; 1303 } opcode_t; 1304 1305 /* Helpers for priv. check */ 1306 #define GEN_PRIV \ 1307 do { \ 1308 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1309 } while (0) 1310 1311 #if defined(CONFIG_USER_ONLY) 1312 #define CHK_HV GEN_PRIV 1313 #define CHK_SV GEN_PRIV 1314 #define CHK_HVRM GEN_PRIV 1315 #else 1316 #define CHK_HV \ 1317 do { \ 1318 if (unlikely(ctx->pr || !ctx->hv)) { \ 1319 GEN_PRIV; \ 1320 } \ 1321 } while (0) 1322 #define CHK_SV \ 1323 do { \ 1324 if (unlikely(ctx->pr)) { \ 1325 GEN_PRIV; \ 1326 } \ 1327 } while (0) 1328 #define CHK_HVRM \ 1329 do { \ 1330 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1331 GEN_PRIV; \ 1332 } \ 1333 } while (0) 1334 #endif 1335 1336 #define CHK_NONE 1337 1338 /*****************************************************************************/ 1339 /* PowerPC instructions table */ 1340 1341 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1342 { \ 1343 .opc1 = op1, \ 1344 .opc2 = op2, \ 1345 .opc3 = op3, \ 1346 .opc4 = 0xff, \ 1347 .handler = { \ 1348 .inval1 = invl, \ 1349 .type = _typ, \ 1350 .type2 = _typ2, \ 1351 .handler = &gen_##name, \ 1352 }, \ 1353 .oname = stringify(name), \ 1354 } 1355 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1356 { \ 1357 .opc1 = op1, \ 1358 .opc2 = op2, \ 1359 .opc3 = op3, \ 1360 .opc4 = 0xff, \ 1361 .handler = { \ 1362 .inval1 = invl1, \ 1363 .inval2 = invl2, \ 1364 .type = _typ, \ 1365 .type2 = _typ2, \ 1366 .handler = &gen_##name, \ 1367 }, \ 1368 .oname = stringify(name), \ 1369 } 1370 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1371 { \ 1372 .opc1 = op1, \ 1373 .opc2 = op2, \ 1374 .opc3 = op3, \ 1375 .opc4 = 0xff, \ 1376 .handler = { \ 1377 .inval1 = invl, \ 1378 .type = _typ, \ 1379 .type2 = _typ2, \ 1380 .handler = &gen_##name, \ 1381 }, \ 1382 .oname = onam, \ 1383 } 1384 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1385 { \ 1386 .opc1 = op1, \ 1387 .opc2 = op2, \ 1388 .opc3 = op3, \ 1389 .opc4 = op4, \ 1390 .handler = { \ 1391 .inval1 = invl, \ 1392 .type = _typ, \ 1393 .type2 = _typ2, \ 1394 .handler = &gen_##name, \ 1395 }, \ 1396 .oname = stringify(name), \ 1397 } 1398 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1399 { \ 1400 .opc1 = op1, \ 1401 .opc2 = op2, \ 1402 .opc3 = op3, \ 1403 .opc4 = op4, \ 1404 .handler = { \ 1405 .inval1 = invl, \ 1406 .type = _typ, \ 1407 .type2 = _typ2, \ 1408 .handler = &gen_##name, \ 1409 }, \ 1410 .oname = onam, \ 1411 } 1412 1413 /* Invalid instruction */ 1414 static void gen_invalid(DisasContext *ctx) 1415 { 1416 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1417 } 1418 1419 static opc_handler_t invalid_handler = { 1420 .inval1 = 0xFFFFFFFF, 1421 .inval2 = 0xFFFFFFFF, 1422 .type = PPC_NONE, 1423 .type2 = PPC_NONE, 1424 .handler = gen_invalid, 1425 }; 1426 1427 /*** Integer comparison ***/ 1428 1429 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1430 { 1431 TCGv t0 = tcg_temp_new(); 1432 TCGv t1 = tcg_temp_new(); 1433 TCGv_i32 t = tcg_temp_new_i32(); 1434 1435 tcg_gen_movi_tl(t0, CRF_EQ); 1436 tcg_gen_movi_tl(t1, CRF_LT); 1437 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1438 t0, arg0, arg1, t1, t0); 1439 tcg_gen_movi_tl(t1, CRF_GT); 1440 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1441 t0, arg0, arg1, t1, t0); 1442 1443 tcg_gen_trunc_tl_i32(t, t0); 1444 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1445 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1446 1447 tcg_temp_free(t0); 1448 tcg_temp_free(t1); 1449 tcg_temp_free_i32(t); 1450 } 1451 1452 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1453 { 1454 TCGv t0 = tcg_const_tl(arg1); 1455 gen_op_cmp(arg0, t0, s, crf); 1456 tcg_temp_free(t0); 1457 } 1458 1459 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1460 { 1461 TCGv t0, t1; 1462 t0 = tcg_temp_new(); 1463 t1 = tcg_temp_new(); 1464 if (s) { 1465 tcg_gen_ext32s_tl(t0, arg0); 1466 tcg_gen_ext32s_tl(t1, arg1); 1467 } else { 1468 tcg_gen_ext32u_tl(t0, arg0); 1469 tcg_gen_ext32u_tl(t1, arg1); 1470 } 1471 gen_op_cmp(t0, t1, s, crf); 1472 tcg_temp_free(t1); 1473 tcg_temp_free(t0); 1474 } 1475 1476 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1477 { 1478 TCGv t0 = tcg_const_tl(arg1); 1479 gen_op_cmp32(arg0, t0, s, crf); 1480 tcg_temp_free(t0); 1481 } 1482 1483 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1484 { 1485 if (NARROW_MODE(ctx)) { 1486 gen_op_cmpi32(reg, 0, 1, 0); 1487 } else { 1488 gen_op_cmpi(reg, 0, 1, 0); 1489 } 1490 } 1491 1492 /* cmprb - range comparison: isupper, isaplha, islower*/ 1493 static void gen_cmprb(DisasContext *ctx) 1494 { 1495 TCGv_i32 src1 = tcg_temp_new_i32(); 1496 TCGv_i32 src2 = tcg_temp_new_i32(); 1497 TCGv_i32 src2lo = tcg_temp_new_i32(); 1498 TCGv_i32 src2hi = tcg_temp_new_i32(); 1499 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1500 1501 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1502 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1503 1504 tcg_gen_andi_i32(src1, src1, 0xFF); 1505 tcg_gen_ext8u_i32(src2lo, src2); 1506 tcg_gen_shri_i32(src2, src2, 8); 1507 tcg_gen_ext8u_i32(src2hi, src2); 1508 1509 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1510 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1511 tcg_gen_and_i32(crf, src2lo, src2hi); 1512 1513 if (ctx->opcode & 0x00200000) { 1514 tcg_gen_shri_i32(src2, src2, 8); 1515 tcg_gen_ext8u_i32(src2lo, src2); 1516 tcg_gen_shri_i32(src2, src2, 8); 1517 tcg_gen_ext8u_i32(src2hi, src2); 1518 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1519 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1520 tcg_gen_and_i32(src2lo, src2lo, src2hi); 1521 tcg_gen_or_i32(crf, crf, src2lo); 1522 } 1523 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1524 tcg_temp_free_i32(src1); 1525 tcg_temp_free_i32(src2); 1526 tcg_temp_free_i32(src2lo); 1527 tcg_temp_free_i32(src2hi); 1528 } 1529 1530 #if defined(TARGET_PPC64) 1531 /* cmpeqb */ 1532 static void gen_cmpeqb(DisasContext *ctx) 1533 { 1534 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1535 cpu_gpr[rB(ctx->opcode)]); 1536 } 1537 #endif 1538 1539 /* isel (PowerPC 2.03 specification) */ 1540 static void gen_isel(DisasContext *ctx) 1541 { 1542 uint32_t bi = rC(ctx->opcode); 1543 uint32_t mask = 0x08 >> (bi & 0x03); 1544 TCGv t0 = tcg_temp_new(); 1545 TCGv zr; 1546 1547 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1548 tcg_gen_andi_tl(t0, t0, mask); 1549 1550 zr = tcg_const_tl(0); 1551 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1552 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1553 cpu_gpr[rB(ctx->opcode)]); 1554 tcg_temp_free(zr); 1555 tcg_temp_free(t0); 1556 } 1557 1558 /* cmpb: PowerPC 2.05 specification */ 1559 static void gen_cmpb(DisasContext *ctx) 1560 { 1561 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1562 cpu_gpr[rB(ctx->opcode)]); 1563 } 1564 1565 /*** Integer arithmetic ***/ 1566 1567 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1568 TCGv arg1, TCGv arg2, int sub) 1569 { 1570 TCGv t0 = tcg_temp_new(); 1571 1572 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1573 tcg_gen_xor_tl(t0, arg1, arg2); 1574 if (sub) { 1575 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1576 } else { 1577 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1578 } 1579 tcg_temp_free(t0); 1580 if (NARROW_MODE(ctx)) { 1581 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1582 if (is_isa300(ctx)) { 1583 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1584 } 1585 } else { 1586 if (is_isa300(ctx)) { 1587 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1588 } 1589 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1590 } 1591 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1592 } 1593 1594 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1595 TCGv res, TCGv arg0, TCGv arg1, 1596 TCGv ca32, int sub) 1597 { 1598 TCGv t0; 1599 1600 if (!is_isa300(ctx)) { 1601 return; 1602 } 1603 1604 t0 = tcg_temp_new(); 1605 if (sub) { 1606 tcg_gen_eqv_tl(t0, arg0, arg1); 1607 } else { 1608 tcg_gen_xor_tl(t0, arg0, arg1); 1609 } 1610 tcg_gen_xor_tl(t0, t0, res); 1611 tcg_gen_extract_tl(ca32, t0, 32, 1); 1612 tcg_temp_free(t0); 1613 } 1614 1615 /* Common add function */ 1616 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1617 TCGv arg2, TCGv ca, TCGv ca32, 1618 bool add_ca, bool compute_ca, 1619 bool compute_ov, bool compute_rc0) 1620 { 1621 TCGv t0 = ret; 1622 1623 if (compute_ca || compute_ov) { 1624 t0 = tcg_temp_new(); 1625 } 1626 1627 if (compute_ca) { 1628 if (NARROW_MODE(ctx)) { 1629 /* 1630 * Caution: a non-obvious corner case of the spec is that 1631 * we must produce the *entire* 64-bit addition, but 1632 * produce the carry into bit 32. 1633 */ 1634 TCGv t1 = tcg_temp_new(); 1635 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1636 tcg_gen_add_tl(t0, arg1, arg2); 1637 if (add_ca) { 1638 tcg_gen_add_tl(t0, t0, ca); 1639 } 1640 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1641 tcg_temp_free(t1); 1642 tcg_gen_extract_tl(ca, ca, 32, 1); 1643 if (is_isa300(ctx)) { 1644 tcg_gen_mov_tl(ca32, ca); 1645 } 1646 } else { 1647 TCGv zero = tcg_const_tl(0); 1648 if (add_ca) { 1649 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1650 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1651 } else { 1652 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1653 } 1654 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1655 tcg_temp_free(zero); 1656 } 1657 } else { 1658 tcg_gen_add_tl(t0, arg1, arg2); 1659 if (add_ca) { 1660 tcg_gen_add_tl(t0, t0, ca); 1661 } 1662 } 1663 1664 if (compute_ov) { 1665 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1666 } 1667 if (unlikely(compute_rc0)) { 1668 gen_set_Rc0(ctx, t0); 1669 } 1670 1671 if (t0 != ret) { 1672 tcg_gen_mov_tl(ret, t0); 1673 tcg_temp_free(t0); 1674 } 1675 } 1676 /* Add functions with two operands */ 1677 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1678 static void glue(gen_, name)(DisasContext *ctx) \ 1679 { \ 1680 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1681 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1682 ca, glue(ca, 32), \ 1683 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1684 } 1685 /* Add functions with one operand and one immediate */ 1686 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1687 add_ca, compute_ca, compute_ov) \ 1688 static void glue(gen_, name)(DisasContext *ctx) \ 1689 { \ 1690 TCGv t0 = tcg_const_tl(const_val); \ 1691 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1692 cpu_gpr[rA(ctx->opcode)], t0, \ 1693 ca, glue(ca, 32), \ 1694 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1695 tcg_temp_free(t0); \ 1696 } 1697 1698 /* add add. addo addo. */ 1699 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 1700 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1701 /* addc addc. addco addco. */ 1702 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 1703 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1704 /* adde adde. addeo addeo. */ 1705 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 1706 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1707 /* addme addme. addmeo addmeo. */ 1708 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 1709 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 1710 /* addex */ 1711 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1712 /* addze addze. addzeo addzeo.*/ 1713 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 1714 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1715 /* addic addic.*/ 1716 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1717 { 1718 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1719 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1720 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1721 tcg_temp_free(c); 1722 } 1723 1724 static void gen_addic(DisasContext *ctx) 1725 { 1726 gen_op_addic(ctx, 0); 1727 } 1728 1729 static void gen_addic_(DisasContext *ctx) 1730 { 1731 gen_op_addic(ctx, 1); 1732 } 1733 1734 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1735 TCGv arg2, int sign, int compute_ov) 1736 { 1737 TCGv_i32 t0 = tcg_temp_new_i32(); 1738 TCGv_i32 t1 = tcg_temp_new_i32(); 1739 TCGv_i32 t2 = tcg_temp_new_i32(); 1740 TCGv_i32 t3 = tcg_temp_new_i32(); 1741 1742 tcg_gen_trunc_tl_i32(t0, arg1); 1743 tcg_gen_trunc_tl_i32(t1, arg2); 1744 if (sign) { 1745 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1746 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1747 tcg_gen_and_i32(t2, t2, t3); 1748 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1749 tcg_gen_or_i32(t2, t2, t3); 1750 tcg_gen_movi_i32(t3, 0); 1751 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1752 tcg_gen_div_i32(t3, t0, t1); 1753 tcg_gen_extu_i32_tl(ret, t3); 1754 } else { 1755 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1756 tcg_gen_movi_i32(t3, 0); 1757 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1758 tcg_gen_divu_i32(t3, t0, t1); 1759 tcg_gen_extu_i32_tl(ret, t3); 1760 } 1761 if (compute_ov) { 1762 tcg_gen_extu_i32_tl(cpu_ov, t2); 1763 if (is_isa300(ctx)) { 1764 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1765 } 1766 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1767 } 1768 tcg_temp_free_i32(t0); 1769 tcg_temp_free_i32(t1); 1770 tcg_temp_free_i32(t2); 1771 tcg_temp_free_i32(t3); 1772 1773 if (unlikely(Rc(ctx->opcode) != 0)) { 1774 gen_set_Rc0(ctx, ret); 1775 } 1776 } 1777 /* Div functions */ 1778 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1779 static void glue(gen_, name)(DisasContext *ctx) \ 1780 { \ 1781 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1782 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1783 sign, compute_ov); \ 1784 } 1785 /* divwu divwu. divwuo divwuo. */ 1786 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1787 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1788 /* divw divw. divwo divwo. */ 1789 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1790 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1791 1792 /* div[wd]eu[o][.] */ 1793 #define GEN_DIVE(name, hlpr, compute_ov) \ 1794 static void gen_##name(DisasContext *ctx) \ 1795 { \ 1796 TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1797 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1798 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1799 tcg_temp_free_i32(t0); \ 1800 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1801 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1802 } \ 1803 } 1804 1805 GEN_DIVE(divweu, divweu, 0); 1806 GEN_DIVE(divweuo, divweu, 1); 1807 GEN_DIVE(divwe, divwe, 0); 1808 GEN_DIVE(divweo, divwe, 1); 1809 1810 #if defined(TARGET_PPC64) 1811 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1812 TCGv arg2, int sign, int compute_ov) 1813 { 1814 TCGv_i64 t0 = tcg_temp_new_i64(); 1815 TCGv_i64 t1 = tcg_temp_new_i64(); 1816 TCGv_i64 t2 = tcg_temp_new_i64(); 1817 TCGv_i64 t3 = tcg_temp_new_i64(); 1818 1819 tcg_gen_mov_i64(t0, arg1); 1820 tcg_gen_mov_i64(t1, arg2); 1821 if (sign) { 1822 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1823 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1824 tcg_gen_and_i64(t2, t2, t3); 1825 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1826 tcg_gen_or_i64(t2, t2, t3); 1827 tcg_gen_movi_i64(t3, 0); 1828 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1829 tcg_gen_div_i64(ret, t0, t1); 1830 } else { 1831 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1832 tcg_gen_movi_i64(t3, 0); 1833 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1834 tcg_gen_divu_i64(ret, t0, t1); 1835 } 1836 if (compute_ov) { 1837 tcg_gen_mov_tl(cpu_ov, t2); 1838 if (is_isa300(ctx)) { 1839 tcg_gen_mov_tl(cpu_ov32, t2); 1840 } 1841 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1842 } 1843 tcg_temp_free_i64(t0); 1844 tcg_temp_free_i64(t1); 1845 tcg_temp_free_i64(t2); 1846 tcg_temp_free_i64(t3); 1847 1848 if (unlikely(Rc(ctx->opcode) != 0)) { 1849 gen_set_Rc0(ctx, ret); 1850 } 1851 } 1852 1853 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1854 static void glue(gen_, name)(DisasContext *ctx) \ 1855 { \ 1856 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1857 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1858 sign, compute_ov); \ 1859 } 1860 /* divdu divdu. divduo divduo. */ 1861 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1862 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1863 /* divd divd. divdo divdo. */ 1864 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1865 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1866 1867 GEN_DIVE(divdeu, divdeu, 0); 1868 GEN_DIVE(divdeuo, divdeu, 1); 1869 GEN_DIVE(divde, divde, 0); 1870 GEN_DIVE(divdeo, divde, 1); 1871 #endif 1872 1873 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1874 TCGv arg2, int sign) 1875 { 1876 TCGv_i32 t0 = tcg_temp_new_i32(); 1877 TCGv_i32 t1 = tcg_temp_new_i32(); 1878 1879 tcg_gen_trunc_tl_i32(t0, arg1); 1880 tcg_gen_trunc_tl_i32(t1, arg2); 1881 if (sign) { 1882 TCGv_i32 t2 = tcg_temp_new_i32(); 1883 TCGv_i32 t3 = tcg_temp_new_i32(); 1884 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1885 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1886 tcg_gen_and_i32(t2, t2, t3); 1887 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1888 tcg_gen_or_i32(t2, t2, t3); 1889 tcg_gen_movi_i32(t3, 0); 1890 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1891 tcg_gen_rem_i32(t3, t0, t1); 1892 tcg_gen_ext_i32_tl(ret, t3); 1893 tcg_temp_free_i32(t2); 1894 tcg_temp_free_i32(t3); 1895 } else { 1896 TCGv_i32 t2 = tcg_const_i32(1); 1897 TCGv_i32 t3 = tcg_const_i32(0); 1898 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1899 tcg_gen_remu_i32(t3, t0, t1); 1900 tcg_gen_extu_i32_tl(ret, t3); 1901 tcg_temp_free_i32(t2); 1902 tcg_temp_free_i32(t3); 1903 } 1904 tcg_temp_free_i32(t0); 1905 tcg_temp_free_i32(t1); 1906 } 1907 1908 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1909 static void glue(gen_, name)(DisasContext *ctx) \ 1910 { \ 1911 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1912 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1913 sign); \ 1914 } 1915 1916 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1917 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1918 1919 #if defined(TARGET_PPC64) 1920 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1921 TCGv arg2, int sign) 1922 { 1923 TCGv_i64 t0 = tcg_temp_new_i64(); 1924 TCGv_i64 t1 = tcg_temp_new_i64(); 1925 1926 tcg_gen_mov_i64(t0, arg1); 1927 tcg_gen_mov_i64(t1, arg2); 1928 if (sign) { 1929 TCGv_i64 t2 = tcg_temp_new_i64(); 1930 TCGv_i64 t3 = tcg_temp_new_i64(); 1931 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1932 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1933 tcg_gen_and_i64(t2, t2, t3); 1934 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1935 tcg_gen_or_i64(t2, t2, t3); 1936 tcg_gen_movi_i64(t3, 0); 1937 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1938 tcg_gen_rem_i64(ret, t0, t1); 1939 tcg_temp_free_i64(t2); 1940 tcg_temp_free_i64(t3); 1941 } else { 1942 TCGv_i64 t2 = tcg_const_i64(1); 1943 TCGv_i64 t3 = tcg_const_i64(0); 1944 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1945 tcg_gen_remu_i64(ret, t0, t1); 1946 tcg_temp_free_i64(t2); 1947 tcg_temp_free_i64(t3); 1948 } 1949 tcg_temp_free_i64(t0); 1950 tcg_temp_free_i64(t1); 1951 } 1952 1953 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1954 static void glue(gen_, name)(DisasContext *ctx) \ 1955 { \ 1956 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1957 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1958 sign); \ 1959 } 1960 1961 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1962 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1963 #endif 1964 1965 /* mulhw mulhw. */ 1966 static void gen_mulhw(DisasContext *ctx) 1967 { 1968 TCGv_i32 t0 = tcg_temp_new_i32(); 1969 TCGv_i32 t1 = tcg_temp_new_i32(); 1970 1971 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1972 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1973 tcg_gen_muls2_i32(t0, t1, t0, t1); 1974 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1975 tcg_temp_free_i32(t0); 1976 tcg_temp_free_i32(t1); 1977 if (unlikely(Rc(ctx->opcode) != 0)) { 1978 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1979 } 1980 } 1981 1982 /* mulhwu mulhwu. */ 1983 static void gen_mulhwu(DisasContext *ctx) 1984 { 1985 TCGv_i32 t0 = tcg_temp_new_i32(); 1986 TCGv_i32 t1 = tcg_temp_new_i32(); 1987 1988 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1989 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1990 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1991 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1992 tcg_temp_free_i32(t0); 1993 tcg_temp_free_i32(t1); 1994 if (unlikely(Rc(ctx->opcode) != 0)) { 1995 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1996 } 1997 } 1998 1999 /* mullw mullw. */ 2000 static void gen_mullw(DisasContext *ctx) 2001 { 2002 #if defined(TARGET_PPC64) 2003 TCGv_i64 t0, t1; 2004 t0 = tcg_temp_new_i64(); 2005 t1 = tcg_temp_new_i64(); 2006 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2007 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2008 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2009 tcg_temp_free(t0); 2010 tcg_temp_free(t1); 2011 #else 2012 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2013 cpu_gpr[rB(ctx->opcode)]); 2014 #endif 2015 if (unlikely(Rc(ctx->opcode) != 0)) { 2016 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2017 } 2018 } 2019 2020 /* mullwo mullwo. */ 2021 static void gen_mullwo(DisasContext *ctx) 2022 { 2023 TCGv_i32 t0 = tcg_temp_new_i32(); 2024 TCGv_i32 t1 = tcg_temp_new_i32(); 2025 2026 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2027 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2028 tcg_gen_muls2_i32(t0, t1, t0, t1); 2029 #if defined(TARGET_PPC64) 2030 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2031 #else 2032 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2033 #endif 2034 2035 tcg_gen_sari_i32(t0, t0, 31); 2036 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2037 tcg_gen_extu_i32_tl(cpu_ov, t0); 2038 if (is_isa300(ctx)) { 2039 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2040 } 2041 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2042 2043 tcg_temp_free_i32(t0); 2044 tcg_temp_free_i32(t1); 2045 if (unlikely(Rc(ctx->opcode) != 0)) { 2046 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2047 } 2048 } 2049 2050 /* mulli */ 2051 static void gen_mulli(DisasContext *ctx) 2052 { 2053 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2054 SIMM(ctx->opcode)); 2055 } 2056 2057 #if defined(TARGET_PPC64) 2058 /* mulhd mulhd. */ 2059 static void gen_mulhd(DisasContext *ctx) 2060 { 2061 TCGv lo = tcg_temp_new(); 2062 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2063 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2064 tcg_temp_free(lo); 2065 if (unlikely(Rc(ctx->opcode) != 0)) { 2066 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2067 } 2068 } 2069 2070 /* mulhdu mulhdu. */ 2071 static void gen_mulhdu(DisasContext *ctx) 2072 { 2073 TCGv lo = tcg_temp_new(); 2074 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2075 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2076 tcg_temp_free(lo); 2077 if (unlikely(Rc(ctx->opcode) != 0)) { 2078 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2079 } 2080 } 2081 2082 /* mulld mulld. */ 2083 static void gen_mulld(DisasContext *ctx) 2084 { 2085 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2086 cpu_gpr[rB(ctx->opcode)]); 2087 if (unlikely(Rc(ctx->opcode) != 0)) { 2088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2089 } 2090 } 2091 2092 /* mulldo mulldo. */ 2093 static void gen_mulldo(DisasContext *ctx) 2094 { 2095 TCGv_i64 t0 = tcg_temp_new_i64(); 2096 TCGv_i64 t1 = tcg_temp_new_i64(); 2097 2098 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2099 cpu_gpr[rB(ctx->opcode)]); 2100 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2101 2102 tcg_gen_sari_i64(t0, t0, 63); 2103 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 2104 if (is_isa300(ctx)) { 2105 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2106 } 2107 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2108 2109 tcg_temp_free_i64(t0); 2110 tcg_temp_free_i64(t1); 2111 2112 if (unlikely(Rc(ctx->opcode) != 0)) { 2113 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2114 } 2115 } 2116 #endif 2117 2118 /* Common subf function */ 2119 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2120 TCGv arg2, bool add_ca, bool compute_ca, 2121 bool compute_ov, bool compute_rc0) 2122 { 2123 TCGv t0 = ret; 2124 2125 if (compute_ca || compute_ov) { 2126 t0 = tcg_temp_new(); 2127 } 2128 2129 if (compute_ca) { 2130 /* dest = ~arg1 + arg2 [+ ca]. */ 2131 if (NARROW_MODE(ctx)) { 2132 /* 2133 * Caution: a non-obvious corner case of the spec is that 2134 * we must produce the *entire* 64-bit addition, but 2135 * produce the carry into bit 32. 2136 */ 2137 TCGv inv1 = tcg_temp_new(); 2138 TCGv t1 = tcg_temp_new(); 2139 tcg_gen_not_tl(inv1, arg1); 2140 if (add_ca) { 2141 tcg_gen_add_tl(t0, arg2, cpu_ca); 2142 } else { 2143 tcg_gen_addi_tl(t0, arg2, 1); 2144 } 2145 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2146 tcg_gen_add_tl(t0, t0, inv1); 2147 tcg_temp_free(inv1); 2148 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2149 tcg_temp_free(t1); 2150 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 2151 if (is_isa300(ctx)) { 2152 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2153 } 2154 } else if (add_ca) { 2155 TCGv zero, inv1 = tcg_temp_new(); 2156 tcg_gen_not_tl(inv1, arg1); 2157 zero = tcg_const_tl(0); 2158 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2159 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 2160 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2161 tcg_temp_free(zero); 2162 tcg_temp_free(inv1); 2163 } else { 2164 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2165 tcg_gen_sub_tl(t0, arg2, arg1); 2166 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2167 } 2168 } else if (add_ca) { 2169 /* 2170 * Since we're ignoring carry-out, we can simplify the 2171 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2172 */ 2173 tcg_gen_sub_tl(t0, arg2, arg1); 2174 tcg_gen_add_tl(t0, t0, cpu_ca); 2175 tcg_gen_subi_tl(t0, t0, 1); 2176 } else { 2177 tcg_gen_sub_tl(t0, arg2, arg1); 2178 } 2179 2180 if (compute_ov) { 2181 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2182 } 2183 if (unlikely(compute_rc0)) { 2184 gen_set_Rc0(ctx, t0); 2185 } 2186 2187 if (t0 != ret) { 2188 tcg_gen_mov_tl(ret, t0); 2189 tcg_temp_free(t0); 2190 } 2191 } 2192 /* Sub functions with Two operands functions */ 2193 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2194 static void glue(gen_, name)(DisasContext *ctx) \ 2195 { \ 2196 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2197 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2198 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2199 } 2200 /* Sub functions with one operand and one immediate */ 2201 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2202 add_ca, compute_ca, compute_ov) \ 2203 static void glue(gen_, name)(DisasContext *ctx) \ 2204 { \ 2205 TCGv t0 = tcg_const_tl(const_val); \ 2206 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2207 cpu_gpr[rA(ctx->opcode)], t0, \ 2208 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2209 tcg_temp_free(t0); \ 2210 } 2211 /* subf subf. subfo subfo. */ 2212 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2213 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2214 /* subfc subfc. subfco subfco. */ 2215 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2216 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2217 /* subfe subfe. subfeo subfo. */ 2218 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2219 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2220 /* subfme subfme. subfmeo subfmeo. */ 2221 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2222 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2223 /* subfze subfze. subfzeo subfzeo.*/ 2224 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2225 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2226 2227 /* subfic */ 2228 static void gen_subfic(DisasContext *ctx) 2229 { 2230 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2231 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2232 c, 0, 1, 0, 0); 2233 tcg_temp_free(c); 2234 } 2235 2236 /* neg neg. nego nego. */ 2237 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2238 { 2239 TCGv zero = tcg_const_tl(0); 2240 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2241 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2242 tcg_temp_free(zero); 2243 } 2244 2245 static void gen_neg(DisasContext *ctx) 2246 { 2247 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2248 if (unlikely(Rc(ctx->opcode))) { 2249 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2250 } 2251 } 2252 2253 static void gen_nego(DisasContext *ctx) 2254 { 2255 gen_op_arith_neg(ctx, 1); 2256 } 2257 2258 /*** Integer logical ***/ 2259 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2260 static void glue(gen_, name)(DisasContext *ctx) \ 2261 { \ 2262 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2263 cpu_gpr[rB(ctx->opcode)]); \ 2264 if (unlikely(Rc(ctx->opcode) != 0)) \ 2265 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2266 } 2267 2268 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2269 static void glue(gen_, name)(DisasContext *ctx) \ 2270 { \ 2271 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2272 if (unlikely(Rc(ctx->opcode) != 0)) \ 2273 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2274 } 2275 2276 /* and & and. */ 2277 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2278 /* andc & andc. */ 2279 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2280 2281 /* andi. */ 2282 static void gen_andi_(DisasContext *ctx) 2283 { 2284 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2285 UIMM(ctx->opcode)); 2286 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2287 } 2288 2289 /* andis. */ 2290 static void gen_andis_(DisasContext *ctx) 2291 { 2292 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2293 UIMM(ctx->opcode) << 16); 2294 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2295 } 2296 2297 /* cntlzw */ 2298 static void gen_cntlzw(DisasContext *ctx) 2299 { 2300 TCGv_i32 t = tcg_temp_new_i32(); 2301 2302 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2303 tcg_gen_clzi_i32(t, t, 32); 2304 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2305 tcg_temp_free_i32(t); 2306 2307 if (unlikely(Rc(ctx->opcode) != 0)) { 2308 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2309 } 2310 } 2311 2312 /* cnttzw */ 2313 static void gen_cnttzw(DisasContext *ctx) 2314 { 2315 TCGv_i32 t = tcg_temp_new_i32(); 2316 2317 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2318 tcg_gen_ctzi_i32(t, t, 32); 2319 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2320 tcg_temp_free_i32(t); 2321 2322 if (unlikely(Rc(ctx->opcode) != 0)) { 2323 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2324 } 2325 } 2326 2327 /* eqv & eqv. */ 2328 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2329 /* extsb & extsb. */ 2330 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2331 /* extsh & extsh. */ 2332 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2333 /* nand & nand. */ 2334 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2335 /* nor & nor. */ 2336 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2337 2338 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2339 static void gen_pause(DisasContext *ctx) 2340 { 2341 TCGv_i32 t0 = tcg_const_i32(0); 2342 tcg_gen_st_i32(t0, cpu_env, 2343 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2344 tcg_temp_free_i32(t0); 2345 2346 /* Stop translation, this gives other CPUs a chance to run */ 2347 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2348 } 2349 #endif /* defined(TARGET_PPC64) */ 2350 2351 /* or & or. */ 2352 static void gen_or(DisasContext *ctx) 2353 { 2354 int rs, ra, rb; 2355 2356 rs = rS(ctx->opcode); 2357 ra = rA(ctx->opcode); 2358 rb = rB(ctx->opcode); 2359 /* Optimisation for mr. ri case */ 2360 if (rs != ra || rs != rb) { 2361 if (rs != rb) { 2362 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2363 } else { 2364 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2365 } 2366 if (unlikely(Rc(ctx->opcode) != 0)) { 2367 gen_set_Rc0(ctx, cpu_gpr[ra]); 2368 } 2369 } else if (unlikely(Rc(ctx->opcode) != 0)) { 2370 gen_set_Rc0(ctx, cpu_gpr[rs]); 2371 #if defined(TARGET_PPC64) 2372 } else if (rs != 0) { /* 0 is nop */ 2373 int prio = 0; 2374 2375 switch (rs) { 2376 case 1: 2377 /* Set process priority to low */ 2378 prio = 2; 2379 break; 2380 case 6: 2381 /* Set process priority to medium-low */ 2382 prio = 3; 2383 break; 2384 case 2: 2385 /* Set process priority to normal */ 2386 prio = 4; 2387 break; 2388 #if !defined(CONFIG_USER_ONLY) 2389 case 31: 2390 if (!ctx->pr) { 2391 /* Set process priority to very low */ 2392 prio = 1; 2393 } 2394 break; 2395 case 5: 2396 if (!ctx->pr) { 2397 /* Set process priority to medium-hight */ 2398 prio = 5; 2399 } 2400 break; 2401 case 3: 2402 if (!ctx->pr) { 2403 /* Set process priority to high */ 2404 prio = 6; 2405 } 2406 break; 2407 case 7: 2408 if (ctx->hv && !ctx->pr) { 2409 /* Set process priority to very high */ 2410 prio = 7; 2411 } 2412 break; 2413 #endif 2414 default: 2415 break; 2416 } 2417 if (prio) { 2418 TCGv t0 = tcg_temp_new(); 2419 gen_load_spr(t0, SPR_PPR); 2420 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2421 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2422 gen_store_spr(SPR_PPR, t0); 2423 tcg_temp_free(t0); 2424 } 2425 #if !defined(CONFIG_USER_ONLY) 2426 /* 2427 * Pause out of TCG otherwise spin loops with smt_low eat too 2428 * much CPU and the kernel hangs. This applies to all 2429 * encodings other than no-op, e.g., miso(rs=26), yield(27), 2430 * mdoio(29), mdoom(30), and all currently undefined. 2431 */ 2432 gen_pause(ctx); 2433 #endif 2434 #endif 2435 } 2436 } 2437 /* orc & orc. */ 2438 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2439 2440 /* xor & xor. */ 2441 static void gen_xor(DisasContext *ctx) 2442 { 2443 /* Optimisation for "set to zero" case */ 2444 if (rS(ctx->opcode) != rB(ctx->opcode)) { 2445 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2446 cpu_gpr[rB(ctx->opcode)]); 2447 } else { 2448 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2449 } 2450 if (unlikely(Rc(ctx->opcode) != 0)) { 2451 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2452 } 2453 } 2454 2455 /* ori */ 2456 static void gen_ori(DisasContext *ctx) 2457 { 2458 target_ulong uimm = UIMM(ctx->opcode); 2459 2460 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2461 return; 2462 } 2463 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2464 } 2465 2466 /* oris */ 2467 static void gen_oris(DisasContext *ctx) 2468 { 2469 target_ulong uimm = UIMM(ctx->opcode); 2470 2471 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2472 /* NOP */ 2473 return; 2474 } 2475 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2476 uimm << 16); 2477 } 2478 2479 /* xori */ 2480 static void gen_xori(DisasContext *ctx) 2481 { 2482 target_ulong uimm = UIMM(ctx->opcode); 2483 2484 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2485 /* NOP */ 2486 return; 2487 } 2488 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2489 } 2490 2491 /* xoris */ 2492 static void gen_xoris(DisasContext *ctx) 2493 { 2494 target_ulong uimm = UIMM(ctx->opcode); 2495 2496 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2497 /* NOP */ 2498 return; 2499 } 2500 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2501 uimm << 16); 2502 } 2503 2504 /* popcntb : PowerPC 2.03 specification */ 2505 static void gen_popcntb(DisasContext *ctx) 2506 { 2507 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2508 } 2509 2510 static void gen_popcntw(DisasContext *ctx) 2511 { 2512 #if defined(TARGET_PPC64) 2513 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2514 #else 2515 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2516 #endif 2517 } 2518 2519 #if defined(TARGET_PPC64) 2520 /* popcntd: PowerPC 2.06 specification */ 2521 static void gen_popcntd(DisasContext *ctx) 2522 { 2523 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2524 } 2525 #endif 2526 2527 /* prtyw: PowerPC 2.05 specification */ 2528 static void gen_prtyw(DisasContext *ctx) 2529 { 2530 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2531 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2532 TCGv t0 = tcg_temp_new(); 2533 tcg_gen_shri_tl(t0, rs, 16); 2534 tcg_gen_xor_tl(ra, rs, t0); 2535 tcg_gen_shri_tl(t0, ra, 8); 2536 tcg_gen_xor_tl(ra, ra, t0); 2537 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2538 tcg_temp_free(t0); 2539 } 2540 2541 #if defined(TARGET_PPC64) 2542 /* prtyd: PowerPC 2.05 specification */ 2543 static void gen_prtyd(DisasContext *ctx) 2544 { 2545 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2546 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2547 TCGv t0 = tcg_temp_new(); 2548 tcg_gen_shri_tl(t0, rs, 32); 2549 tcg_gen_xor_tl(ra, rs, t0); 2550 tcg_gen_shri_tl(t0, ra, 16); 2551 tcg_gen_xor_tl(ra, ra, t0); 2552 tcg_gen_shri_tl(t0, ra, 8); 2553 tcg_gen_xor_tl(ra, ra, t0); 2554 tcg_gen_andi_tl(ra, ra, 1); 2555 tcg_temp_free(t0); 2556 } 2557 #endif 2558 2559 #if defined(TARGET_PPC64) 2560 /* bpermd */ 2561 static void gen_bpermd(DisasContext *ctx) 2562 { 2563 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2564 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2565 } 2566 #endif 2567 2568 #if defined(TARGET_PPC64) 2569 /* extsw & extsw. */ 2570 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2571 2572 /* cntlzd */ 2573 static void gen_cntlzd(DisasContext *ctx) 2574 { 2575 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2576 if (unlikely(Rc(ctx->opcode) != 0)) { 2577 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2578 } 2579 } 2580 2581 /* cnttzd */ 2582 static void gen_cnttzd(DisasContext *ctx) 2583 { 2584 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2585 if (unlikely(Rc(ctx->opcode) != 0)) { 2586 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2587 } 2588 } 2589 2590 /* darn */ 2591 static void gen_darn(DisasContext *ctx) 2592 { 2593 int l = L(ctx->opcode); 2594 2595 if (l > 2) { 2596 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 2597 } else { 2598 gen_icount_io_start(ctx); 2599 if (l == 0) { 2600 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 2601 } else { 2602 /* Return 64-bit random for both CRN and RRN */ 2603 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 2604 } 2605 } 2606 } 2607 #endif 2608 2609 /*** Integer rotate ***/ 2610 2611 /* rlwimi & rlwimi. */ 2612 static void gen_rlwimi(DisasContext *ctx) 2613 { 2614 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2615 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2616 uint32_t sh = SH(ctx->opcode); 2617 uint32_t mb = MB(ctx->opcode); 2618 uint32_t me = ME(ctx->opcode); 2619 2620 if (sh == (31 - me) && mb <= me) { 2621 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2622 } else { 2623 target_ulong mask; 2624 bool mask_in_32b = true; 2625 TCGv t1; 2626 2627 #if defined(TARGET_PPC64) 2628 mb += 32; 2629 me += 32; 2630 #endif 2631 mask = MASK(mb, me); 2632 2633 #if defined(TARGET_PPC64) 2634 if (mask > 0xffffffffu) { 2635 mask_in_32b = false; 2636 } 2637 #endif 2638 t1 = tcg_temp_new(); 2639 if (mask_in_32b) { 2640 TCGv_i32 t0 = tcg_temp_new_i32(); 2641 tcg_gen_trunc_tl_i32(t0, t_rs); 2642 tcg_gen_rotli_i32(t0, t0, sh); 2643 tcg_gen_extu_i32_tl(t1, t0); 2644 tcg_temp_free_i32(t0); 2645 } else { 2646 #if defined(TARGET_PPC64) 2647 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2648 tcg_gen_rotli_i64(t1, t1, sh); 2649 #else 2650 g_assert_not_reached(); 2651 #endif 2652 } 2653 2654 tcg_gen_andi_tl(t1, t1, mask); 2655 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2656 tcg_gen_or_tl(t_ra, t_ra, t1); 2657 tcg_temp_free(t1); 2658 } 2659 if (unlikely(Rc(ctx->opcode) != 0)) { 2660 gen_set_Rc0(ctx, t_ra); 2661 } 2662 } 2663 2664 /* rlwinm & rlwinm. */ 2665 static void gen_rlwinm(DisasContext *ctx) 2666 { 2667 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2668 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2669 int sh = SH(ctx->opcode); 2670 int mb = MB(ctx->opcode); 2671 int me = ME(ctx->opcode); 2672 int len = me - mb + 1; 2673 int rsh = (32 - sh) & 31; 2674 2675 if (sh != 0 && len > 0 && me == (31 - sh)) { 2676 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2677 } else if (me == 31 && rsh + len <= 32) { 2678 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2679 } else { 2680 target_ulong mask; 2681 bool mask_in_32b = true; 2682 #if defined(TARGET_PPC64) 2683 mb += 32; 2684 me += 32; 2685 #endif 2686 mask = MASK(mb, me); 2687 #if defined(TARGET_PPC64) 2688 if (mask > 0xffffffffu) { 2689 mask_in_32b = false; 2690 } 2691 #endif 2692 if (mask_in_32b) { 2693 if (sh == 0) { 2694 tcg_gen_andi_tl(t_ra, t_rs, mask); 2695 } else { 2696 TCGv_i32 t0 = tcg_temp_new_i32(); 2697 tcg_gen_trunc_tl_i32(t0, t_rs); 2698 tcg_gen_rotli_i32(t0, t0, sh); 2699 tcg_gen_andi_i32(t0, t0, mask); 2700 tcg_gen_extu_i32_tl(t_ra, t0); 2701 tcg_temp_free_i32(t0); 2702 } 2703 } else { 2704 #if defined(TARGET_PPC64) 2705 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2706 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2707 tcg_gen_andi_i64(t_ra, t_ra, mask); 2708 #else 2709 g_assert_not_reached(); 2710 #endif 2711 } 2712 } 2713 if (unlikely(Rc(ctx->opcode) != 0)) { 2714 gen_set_Rc0(ctx, t_ra); 2715 } 2716 } 2717 2718 /* rlwnm & rlwnm. */ 2719 static void gen_rlwnm(DisasContext *ctx) 2720 { 2721 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2722 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2723 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2724 uint32_t mb = MB(ctx->opcode); 2725 uint32_t me = ME(ctx->opcode); 2726 target_ulong mask; 2727 bool mask_in_32b = true; 2728 2729 #if defined(TARGET_PPC64) 2730 mb += 32; 2731 me += 32; 2732 #endif 2733 mask = MASK(mb, me); 2734 2735 #if defined(TARGET_PPC64) 2736 if (mask > 0xffffffffu) { 2737 mask_in_32b = false; 2738 } 2739 #endif 2740 if (mask_in_32b) { 2741 TCGv_i32 t0 = tcg_temp_new_i32(); 2742 TCGv_i32 t1 = tcg_temp_new_i32(); 2743 tcg_gen_trunc_tl_i32(t0, t_rb); 2744 tcg_gen_trunc_tl_i32(t1, t_rs); 2745 tcg_gen_andi_i32(t0, t0, 0x1f); 2746 tcg_gen_rotl_i32(t1, t1, t0); 2747 tcg_gen_extu_i32_tl(t_ra, t1); 2748 tcg_temp_free_i32(t0); 2749 tcg_temp_free_i32(t1); 2750 } else { 2751 #if defined(TARGET_PPC64) 2752 TCGv_i64 t0 = tcg_temp_new_i64(); 2753 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2754 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2755 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2756 tcg_temp_free_i64(t0); 2757 #else 2758 g_assert_not_reached(); 2759 #endif 2760 } 2761 2762 tcg_gen_andi_tl(t_ra, t_ra, mask); 2763 2764 if (unlikely(Rc(ctx->opcode) != 0)) { 2765 gen_set_Rc0(ctx, t_ra); 2766 } 2767 } 2768 2769 #if defined(TARGET_PPC64) 2770 #define GEN_PPC64_R2(name, opc1, opc2) \ 2771 static void glue(gen_, name##0)(DisasContext *ctx) \ 2772 { \ 2773 gen_##name(ctx, 0); \ 2774 } \ 2775 \ 2776 static void glue(gen_, name##1)(DisasContext *ctx) \ 2777 { \ 2778 gen_##name(ctx, 1); \ 2779 } 2780 #define GEN_PPC64_R4(name, opc1, opc2) \ 2781 static void glue(gen_, name##0)(DisasContext *ctx) \ 2782 { \ 2783 gen_##name(ctx, 0, 0); \ 2784 } \ 2785 \ 2786 static void glue(gen_, name##1)(DisasContext *ctx) \ 2787 { \ 2788 gen_##name(ctx, 0, 1); \ 2789 } \ 2790 \ 2791 static void glue(gen_, name##2)(DisasContext *ctx) \ 2792 { \ 2793 gen_##name(ctx, 1, 0); \ 2794 } \ 2795 \ 2796 static void glue(gen_, name##3)(DisasContext *ctx) \ 2797 { \ 2798 gen_##name(ctx, 1, 1); \ 2799 } 2800 2801 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2802 { 2803 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2804 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2805 int len = me - mb + 1; 2806 int rsh = (64 - sh) & 63; 2807 2808 if (sh != 0 && len > 0 && me == (63 - sh)) { 2809 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2810 } else if (me == 63 && rsh + len <= 64) { 2811 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2812 } else { 2813 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2814 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2815 } 2816 if (unlikely(Rc(ctx->opcode) != 0)) { 2817 gen_set_Rc0(ctx, t_ra); 2818 } 2819 } 2820 2821 /* rldicl - rldicl. */ 2822 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2823 { 2824 uint32_t sh, mb; 2825 2826 sh = SH(ctx->opcode) | (shn << 5); 2827 mb = MB(ctx->opcode) | (mbn << 5); 2828 gen_rldinm(ctx, mb, 63, sh); 2829 } 2830 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2831 2832 /* rldicr - rldicr. */ 2833 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2834 { 2835 uint32_t sh, me; 2836 2837 sh = SH(ctx->opcode) | (shn << 5); 2838 me = MB(ctx->opcode) | (men << 5); 2839 gen_rldinm(ctx, 0, me, sh); 2840 } 2841 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2842 2843 /* rldic - rldic. */ 2844 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2845 { 2846 uint32_t sh, mb; 2847 2848 sh = SH(ctx->opcode) | (shn << 5); 2849 mb = MB(ctx->opcode) | (mbn << 5); 2850 gen_rldinm(ctx, mb, 63 - sh, sh); 2851 } 2852 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2853 2854 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2855 { 2856 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2857 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2858 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2859 TCGv t0; 2860 2861 t0 = tcg_temp_new(); 2862 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2863 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2864 tcg_temp_free(t0); 2865 2866 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2867 if (unlikely(Rc(ctx->opcode) != 0)) { 2868 gen_set_Rc0(ctx, t_ra); 2869 } 2870 } 2871 2872 /* rldcl - rldcl. */ 2873 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2874 { 2875 uint32_t mb; 2876 2877 mb = MB(ctx->opcode) | (mbn << 5); 2878 gen_rldnm(ctx, mb, 63); 2879 } 2880 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2881 2882 /* rldcr - rldcr. */ 2883 static inline void gen_rldcr(DisasContext *ctx, int men) 2884 { 2885 uint32_t me; 2886 2887 me = MB(ctx->opcode) | (men << 5); 2888 gen_rldnm(ctx, 0, me); 2889 } 2890 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2891 2892 /* rldimi - rldimi. */ 2893 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2894 { 2895 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2896 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2897 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2898 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2899 uint32_t me = 63 - sh; 2900 2901 if (mb <= me) { 2902 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2903 } else { 2904 target_ulong mask = MASK(mb, me); 2905 TCGv t1 = tcg_temp_new(); 2906 2907 tcg_gen_rotli_tl(t1, t_rs, sh); 2908 tcg_gen_andi_tl(t1, t1, mask); 2909 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2910 tcg_gen_or_tl(t_ra, t_ra, t1); 2911 tcg_temp_free(t1); 2912 } 2913 if (unlikely(Rc(ctx->opcode) != 0)) { 2914 gen_set_Rc0(ctx, t_ra); 2915 } 2916 } 2917 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2918 #endif 2919 2920 /*** Integer shift ***/ 2921 2922 /* slw & slw. */ 2923 static void gen_slw(DisasContext *ctx) 2924 { 2925 TCGv t0, t1; 2926 2927 t0 = tcg_temp_new(); 2928 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2929 #if defined(TARGET_PPC64) 2930 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2931 tcg_gen_sari_tl(t0, t0, 0x3f); 2932 #else 2933 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2934 tcg_gen_sari_tl(t0, t0, 0x1f); 2935 #endif 2936 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2937 t1 = tcg_temp_new(); 2938 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2939 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2940 tcg_temp_free(t1); 2941 tcg_temp_free(t0); 2942 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2943 if (unlikely(Rc(ctx->opcode) != 0)) { 2944 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2945 } 2946 } 2947 2948 /* sraw & sraw. */ 2949 static void gen_sraw(DisasContext *ctx) 2950 { 2951 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2952 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2953 if (unlikely(Rc(ctx->opcode) != 0)) { 2954 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2955 } 2956 } 2957 2958 /* srawi & srawi. */ 2959 static void gen_srawi(DisasContext *ctx) 2960 { 2961 int sh = SH(ctx->opcode); 2962 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2963 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2964 if (sh == 0) { 2965 tcg_gen_ext32s_tl(dst, src); 2966 tcg_gen_movi_tl(cpu_ca, 0); 2967 if (is_isa300(ctx)) { 2968 tcg_gen_movi_tl(cpu_ca32, 0); 2969 } 2970 } else { 2971 TCGv t0; 2972 tcg_gen_ext32s_tl(dst, src); 2973 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2974 t0 = tcg_temp_new(); 2975 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2976 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2977 tcg_temp_free(t0); 2978 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2979 if (is_isa300(ctx)) { 2980 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2981 } 2982 tcg_gen_sari_tl(dst, dst, sh); 2983 } 2984 if (unlikely(Rc(ctx->opcode) != 0)) { 2985 gen_set_Rc0(ctx, dst); 2986 } 2987 } 2988 2989 /* srw & srw. */ 2990 static void gen_srw(DisasContext *ctx) 2991 { 2992 TCGv t0, t1; 2993 2994 t0 = tcg_temp_new(); 2995 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2996 #if defined(TARGET_PPC64) 2997 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2998 tcg_gen_sari_tl(t0, t0, 0x3f); 2999 #else 3000 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3001 tcg_gen_sari_tl(t0, t0, 0x1f); 3002 #endif 3003 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3004 tcg_gen_ext32u_tl(t0, t0); 3005 t1 = tcg_temp_new(); 3006 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3007 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3008 tcg_temp_free(t1); 3009 tcg_temp_free(t0); 3010 if (unlikely(Rc(ctx->opcode) != 0)) { 3011 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3012 } 3013 } 3014 3015 #if defined(TARGET_PPC64) 3016 /* sld & sld. */ 3017 static void gen_sld(DisasContext *ctx) 3018 { 3019 TCGv t0, t1; 3020 3021 t0 = tcg_temp_new(); 3022 /* AND rS with a mask that is 0 when rB >= 0x40 */ 3023 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3024 tcg_gen_sari_tl(t0, t0, 0x3f); 3025 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3026 t1 = tcg_temp_new(); 3027 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3028 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3029 tcg_temp_free(t1); 3030 tcg_temp_free(t0); 3031 if (unlikely(Rc(ctx->opcode) != 0)) { 3032 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3033 } 3034 } 3035 3036 /* srad & srad. */ 3037 static void gen_srad(DisasContext *ctx) 3038 { 3039 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3040 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3041 if (unlikely(Rc(ctx->opcode) != 0)) { 3042 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3043 } 3044 } 3045 /* sradi & sradi. */ 3046 static inline void gen_sradi(DisasContext *ctx, int n) 3047 { 3048 int sh = SH(ctx->opcode) + (n << 5); 3049 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3050 TCGv src = cpu_gpr[rS(ctx->opcode)]; 3051 if (sh == 0) { 3052 tcg_gen_mov_tl(dst, src); 3053 tcg_gen_movi_tl(cpu_ca, 0); 3054 if (is_isa300(ctx)) { 3055 tcg_gen_movi_tl(cpu_ca32, 0); 3056 } 3057 } else { 3058 TCGv t0; 3059 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3060 t0 = tcg_temp_new(); 3061 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3062 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3063 tcg_temp_free(t0); 3064 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3065 if (is_isa300(ctx)) { 3066 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3067 } 3068 tcg_gen_sari_tl(dst, src, sh); 3069 } 3070 if (unlikely(Rc(ctx->opcode) != 0)) { 3071 gen_set_Rc0(ctx, dst); 3072 } 3073 } 3074 3075 static void gen_sradi0(DisasContext *ctx) 3076 { 3077 gen_sradi(ctx, 0); 3078 } 3079 3080 static void gen_sradi1(DisasContext *ctx) 3081 { 3082 gen_sradi(ctx, 1); 3083 } 3084 3085 /* extswsli & extswsli. */ 3086 static inline void gen_extswsli(DisasContext *ctx, int n) 3087 { 3088 int sh = SH(ctx->opcode) + (n << 5); 3089 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3090 TCGv src = cpu_gpr[rS(ctx->opcode)]; 3091 3092 tcg_gen_ext32s_tl(dst, src); 3093 tcg_gen_shli_tl(dst, dst, sh); 3094 if (unlikely(Rc(ctx->opcode) != 0)) { 3095 gen_set_Rc0(ctx, dst); 3096 } 3097 } 3098 3099 static void gen_extswsli0(DisasContext *ctx) 3100 { 3101 gen_extswsli(ctx, 0); 3102 } 3103 3104 static void gen_extswsli1(DisasContext *ctx) 3105 { 3106 gen_extswsli(ctx, 1); 3107 } 3108 3109 /* srd & srd. */ 3110 static void gen_srd(DisasContext *ctx) 3111 { 3112 TCGv t0, t1; 3113 3114 t0 = tcg_temp_new(); 3115 /* AND rS with a mask that is 0 when rB >= 0x40 */ 3116 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3117 tcg_gen_sari_tl(t0, t0, 0x3f); 3118 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3119 t1 = tcg_temp_new(); 3120 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3121 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3122 tcg_temp_free(t1); 3123 tcg_temp_free(t0); 3124 if (unlikely(Rc(ctx->opcode) != 0)) { 3125 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3126 } 3127 } 3128 #endif 3129 3130 /*** Addressing modes ***/ 3131 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3132 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3133 target_long maskl) 3134 { 3135 target_long simm = SIMM(ctx->opcode); 3136 3137 simm &= ~maskl; 3138 if (rA(ctx->opcode) == 0) { 3139 if (NARROW_MODE(ctx)) { 3140 simm = (uint32_t)simm; 3141 } 3142 tcg_gen_movi_tl(EA, simm); 3143 } else if (likely(simm != 0)) { 3144 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3145 if (NARROW_MODE(ctx)) { 3146 tcg_gen_ext32u_tl(EA, EA); 3147 } 3148 } else { 3149 if (NARROW_MODE(ctx)) { 3150 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3151 } else { 3152 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3153 } 3154 } 3155 } 3156 3157 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3158 { 3159 if (rA(ctx->opcode) == 0) { 3160 if (NARROW_MODE(ctx)) { 3161 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3162 } else { 3163 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3164 } 3165 } else { 3166 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3167 if (NARROW_MODE(ctx)) { 3168 tcg_gen_ext32u_tl(EA, EA); 3169 } 3170 } 3171 } 3172 3173 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3174 { 3175 if (rA(ctx->opcode) == 0) { 3176 tcg_gen_movi_tl(EA, 0); 3177 } else if (NARROW_MODE(ctx)) { 3178 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3179 } else { 3180 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3181 } 3182 } 3183 3184 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3185 target_long val) 3186 { 3187 tcg_gen_addi_tl(ret, arg1, val); 3188 if (NARROW_MODE(ctx)) { 3189 tcg_gen_ext32u_tl(ret, ret); 3190 } 3191 } 3192 3193 static inline void gen_align_no_le(DisasContext *ctx) 3194 { 3195 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3196 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3197 } 3198 3199 /*** Integer load ***/ 3200 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3201 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3202 3203 #define GEN_QEMU_LOAD_TL(ldop, op) \ 3204 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3205 TCGv val, \ 3206 TCGv addr) \ 3207 { \ 3208 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3209 } 3210 3211 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3212 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3213 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3214 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3215 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3216 3217 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3218 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3219 3220 #define GEN_QEMU_LOAD_64(ldop, op) \ 3221 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3222 TCGv_i64 val, \ 3223 TCGv addr) \ 3224 { \ 3225 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3226 } 3227 3228 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3229 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3230 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3231 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3232 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3233 3234 #if defined(TARGET_PPC64) 3235 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3236 #endif 3237 3238 #define GEN_QEMU_STORE_TL(stop, op) \ 3239 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3240 TCGv val, \ 3241 TCGv addr) \ 3242 { \ 3243 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3244 } 3245 3246 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3247 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3248 #endif 3249 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3250 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3251 3252 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3253 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3254 3255 #define GEN_QEMU_STORE_64(stop, op) \ 3256 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3257 TCGv_i64 val, \ 3258 TCGv addr) \ 3259 { \ 3260 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3261 } 3262 3263 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3264 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3265 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3266 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3267 3268 #if defined(TARGET_PPC64) 3269 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3270 #endif 3271 3272 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3273 static void glue(gen_, name##x)(DisasContext *ctx) \ 3274 { \ 3275 TCGv EA; \ 3276 chk; \ 3277 gen_set_access_type(ctx, ACCESS_INT); \ 3278 EA = tcg_temp_new(); \ 3279 gen_addr_reg_index(ctx, EA); \ 3280 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3281 tcg_temp_free(EA); \ 3282 } 3283 3284 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3285 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3286 3287 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3288 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3289 3290 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 3291 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3292 { \ 3293 TCGv EA; \ 3294 CHK_SV; \ 3295 gen_set_access_type(ctx, ACCESS_INT); \ 3296 EA = tcg_temp_new(); \ 3297 gen_addr_reg_index(ctx, EA); \ 3298 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 3299 tcg_temp_free(EA); \ 3300 } 3301 3302 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 3303 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 3304 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 3305 #if defined(TARGET_PPC64) 3306 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 3307 #endif 3308 3309 #if defined(TARGET_PPC64) 3310 /* CI load/store variants */ 3311 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3312 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3313 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3314 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3315 3316 /* lq */ 3317 static void gen_lq(DisasContext *ctx) 3318 { 3319 int ra, rd; 3320 TCGv EA, hi, lo; 3321 3322 /* lq is a legal user mode instruction starting in ISA 2.07 */ 3323 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3324 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3325 3326 if (!legal_in_user_mode && ctx->pr) { 3327 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3328 return; 3329 } 3330 3331 if (!le_is_supported && ctx->le_mode) { 3332 gen_align_no_le(ctx); 3333 return; 3334 } 3335 ra = rA(ctx->opcode); 3336 rd = rD(ctx->opcode); 3337 if (unlikely((rd & 1) || rd == ra)) { 3338 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3339 return; 3340 } 3341 3342 gen_set_access_type(ctx, ACCESS_INT); 3343 EA = tcg_temp_new(); 3344 gen_addr_imm_index(ctx, EA, 0x0F); 3345 3346 /* Note that the low part is always in RD+1, even in LE mode. */ 3347 lo = cpu_gpr[rd + 1]; 3348 hi = cpu_gpr[rd]; 3349 3350 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3351 if (HAVE_ATOMIC128) { 3352 TCGv_i32 oi = tcg_temp_new_i32(); 3353 if (ctx->le_mode) { 3354 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 3355 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3356 } else { 3357 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 3358 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3359 } 3360 tcg_temp_free_i32(oi); 3361 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3362 } else { 3363 /* Restart with exclusive lock. */ 3364 gen_helper_exit_atomic(cpu_env); 3365 ctx->base.is_jmp = DISAS_NORETURN; 3366 } 3367 } else if (ctx->le_mode) { 3368 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3369 gen_addr_add(ctx, EA, EA, 8); 3370 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3371 } else { 3372 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3373 gen_addr_add(ctx, EA, EA, 8); 3374 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3375 } 3376 tcg_temp_free(EA); 3377 } 3378 #endif 3379 3380 /*** Integer store ***/ 3381 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3382 static void glue(gen_, name##x)(DisasContext *ctx) \ 3383 { \ 3384 TCGv EA; \ 3385 chk; \ 3386 gen_set_access_type(ctx, ACCESS_INT); \ 3387 EA = tcg_temp_new(); \ 3388 gen_addr_reg_index(ctx, EA); \ 3389 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3390 tcg_temp_free(EA); \ 3391 } 3392 #define GEN_STX(name, stop, opc2, opc3, type) \ 3393 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3394 3395 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3396 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3397 3398 #define GEN_STEPX(name, stop, opc2, opc3) \ 3399 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3400 { \ 3401 TCGv EA; \ 3402 CHK_SV; \ 3403 gen_set_access_type(ctx, ACCESS_INT); \ 3404 EA = tcg_temp_new(); \ 3405 gen_addr_reg_index(ctx, EA); \ 3406 tcg_gen_qemu_st_tl( \ 3407 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 3408 tcg_temp_free(EA); \ 3409 } 3410 3411 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 3412 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 3413 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 3414 #if defined(TARGET_PPC64) 3415 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 3416 #endif 3417 3418 #if defined(TARGET_PPC64) 3419 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3420 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3421 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3422 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3423 3424 static void gen_std(DisasContext *ctx) 3425 { 3426 int rs; 3427 TCGv EA; 3428 3429 rs = rS(ctx->opcode); 3430 if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3431 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3432 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3433 TCGv hi, lo; 3434 3435 if (!(ctx->insns_flags & PPC_64BX)) { 3436 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3437 } 3438 3439 if (!legal_in_user_mode && ctx->pr) { 3440 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3441 return; 3442 } 3443 3444 if (!le_is_supported && ctx->le_mode) { 3445 gen_align_no_le(ctx); 3446 return; 3447 } 3448 3449 if (unlikely(rs & 1)) { 3450 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3451 return; 3452 } 3453 gen_set_access_type(ctx, ACCESS_INT); 3454 EA = tcg_temp_new(); 3455 gen_addr_imm_index(ctx, EA, 0x03); 3456 3457 /* Note that the low part is always in RS+1, even in LE mode. */ 3458 lo = cpu_gpr[rs + 1]; 3459 hi = cpu_gpr[rs]; 3460 3461 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3462 if (HAVE_ATOMIC128) { 3463 TCGv_i32 oi = tcg_temp_new_i32(); 3464 if (ctx->le_mode) { 3465 tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128, 3466 ctx->mem_idx)); 3467 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3468 } else { 3469 tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128, 3470 ctx->mem_idx)); 3471 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3472 } 3473 tcg_temp_free_i32(oi); 3474 } else { 3475 /* Restart with exclusive lock. */ 3476 gen_helper_exit_atomic(cpu_env); 3477 ctx->base.is_jmp = DISAS_NORETURN; 3478 } 3479 } else if (ctx->le_mode) { 3480 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3481 gen_addr_add(ctx, EA, EA, 8); 3482 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3483 } else { 3484 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3485 gen_addr_add(ctx, EA, EA, 8); 3486 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3487 } 3488 tcg_temp_free(EA); 3489 } else { 3490 /* std / stdu */ 3491 if (Rc(ctx->opcode)) { 3492 if (unlikely(rA(ctx->opcode) == 0)) { 3493 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3494 return; 3495 } 3496 } 3497 gen_set_access_type(ctx, ACCESS_INT); 3498 EA = tcg_temp_new(); 3499 gen_addr_imm_index(ctx, EA, 0x03); 3500 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3501 if (Rc(ctx->opcode)) { 3502 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3503 } 3504 tcg_temp_free(EA); 3505 } 3506 } 3507 #endif 3508 /*** Integer load and store with byte reverse ***/ 3509 3510 /* lhbrx */ 3511 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3512 3513 /* lwbrx */ 3514 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3515 3516 #if defined(TARGET_PPC64) 3517 /* ldbrx */ 3518 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3519 /* stdbrx */ 3520 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3521 #endif /* TARGET_PPC64 */ 3522 3523 /* sthbrx */ 3524 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3525 /* stwbrx */ 3526 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3527 3528 /*** Integer load and store multiple ***/ 3529 3530 /* lmw */ 3531 static void gen_lmw(DisasContext *ctx) 3532 { 3533 TCGv t0; 3534 TCGv_i32 t1; 3535 3536 if (ctx->le_mode) { 3537 gen_align_no_le(ctx); 3538 return; 3539 } 3540 gen_set_access_type(ctx, ACCESS_INT); 3541 t0 = tcg_temp_new(); 3542 t1 = tcg_const_i32(rD(ctx->opcode)); 3543 gen_addr_imm_index(ctx, t0, 0); 3544 gen_helper_lmw(cpu_env, t0, t1); 3545 tcg_temp_free(t0); 3546 tcg_temp_free_i32(t1); 3547 } 3548 3549 /* stmw */ 3550 static void gen_stmw(DisasContext *ctx) 3551 { 3552 TCGv t0; 3553 TCGv_i32 t1; 3554 3555 if (ctx->le_mode) { 3556 gen_align_no_le(ctx); 3557 return; 3558 } 3559 gen_set_access_type(ctx, ACCESS_INT); 3560 t0 = tcg_temp_new(); 3561 t1 = tcg_const_i32(rS(ctx->opcode)); 3562 gen_addr_imm_index(ctx, t0, 0); 3563 gen_helper_stmw(cpu_env, t0, t1); 3564 tcg_temp_free(t0); 3565 tcg_temp_free_i32(t1); 3566 } 3567 3568 /*** Integer load and store strings ***/ 3569 3570 /* lswi */ 3571 /* 3572 * PowerPC32 specification says we must generate an exception if rA is 3573 * in the range of registers to be loaded. In an other hand, IBM says 3574 * this is valid, but rA won't be loaded. For now, I'll follow the 3575 * spec... 3576 */ 3577 static void gen_lswi(DisasContext *ctx) 3578 { 3579 TCGv t0; 3580 TCGv_i32 t1, t2; 3581 int nb = NB(ctx->opcode); 3582 int start = rD(ctx->opcode); 3583 int ra = rA(ctx->opcode); 3584 int nr; 3585 3586 if (ctx->le_mode) { 3587 gen_align_no_le(ctx); 3588 return; 3589 } 3590 if (nb == 0) { 3591 nb = 32; 3592 } 3593 nr = DIV_ROUND_UP(nb, 4); 3594 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3595 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3596 return; 3597 } 3598 gen_set_access_type(ctx, ACCESS_INT); 3599 t0 = tcg_temp_new(); 3600 gen_addr_register(ctx, t0); 3601 t1 = tcg_const_i32(nb); 3602 t2 = tcg_const_i32(start); 3603 gen_helper_lsw(cpu_env, t0, t1, t2); 3604 tcg_temp_free(t0); 3605 tcg_temp_free_i32(t1); 3606 tcg_temp_free_i32(t2); 3607 } 3608 3609 /* lswx */ 3610 static void gen_lswx(DisasContext *ctx) 3611 { 3612 TCGv t0; 3613 TCGv_i32 t1, t2, t3; 3614 3615 if (ctx->le_mode) { 3616 gen_align_no_le(ctx); 3617 return; 3618 } 3619 gen_set_access_type(ctx, ACCESS_INT); 3620 t0 = tcg_temp_new(); 3621 gen_addr_reg_index(ctx, t0); 3622 t1 = tcg_const_i32(rD(ctx->opcode)); 3623 t2 = tcg_const_i32(rA(ctx->opcode)); 3624 t3 = tcg_const_i32(rB(ctx->opcode)); 3625 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3626 tcg_temp_free(t0); 3627 tcg_temp_free_i32(t1); 3628 tcg_temp_free_i32(t2); 3629 tcg_temp_free_i32(t3); 3630 } 3631 3632 /* stswi */ 3633 static void gen_stswi(DisasContext *ctx) 3634 { 3635 TCGv t0; 3636 TCGv_i32 t1, t2; 3637 int nb = NB(ctx->opcode); 3638 3639 if (ctx->le_mode) { 3640 gen_align_no_le(ctx); 3641 return; 3642 } 3643 gen_set_access_type(ctx, ACCESS_INT); 3644 t0 = tcg_temp_new(); 3645 gen_addr_register(ctx, t0); 3646 if (nb == 0) { 3647 nb = 32; 3648 } 3649 t1 = tcg_const_i32(nb); 3650 t2 = tcg_const_i32(rS(ctx->opcode)); 3651 gen_helper_stsw(cpu_env, t0, t1, t2); 3652 tcg_temp_free(t0); 3653 tcg_temp_free_i32(t1); 3654 tcg_temp_free_i32(t2); 3655 } 3656 3657 /* stswx */ 3658 static void gen_stswx(DisasContext *ctx) 3659 { 3660 TCGv t0; 3661 TCGv_i32 t1, t2; 3662 3663 if (ctx->le_mode) { 3664 gen_align_no_le(ctx); 3665 return; 3666 } 3667 gen_set_access_type(ctx, ACCESS_INT); 3668 t0 = tcg_temp_new(); 3669 gen_addr_reg_index(ctx, t0); 3670 t1 = tcg_temp_new_i32(); 3671 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3672 tcg_gen_andi_i32(t1, t1, 0x7F); 3673 t2 = tcg_const_i32(rS(ctx->opcode)); 3674 gen_helper_stsw(cpu_env, t0, t1, t2); 3675 tcg_temp_free(t0); 3676 tcg_temp_free_i32(t1); 3677 tcg_temp_free_i32(t2); 3678 } 3679 3680 /*** Memory synchronisation ***/ 3681 /* eieio */ 3682 static void gen_eieio(DisasContext *ctx) 3683 { 3684 TCGBar bar = TCG_MO_LD_ST; 3685 3686 /* 3687 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3688 * tell the CPU it is a store-forwarding barrier. 3689 */ 3690 if (ctx->opcode & 0x2000000) { 3691 /* 3692 * ISA says that "Reserved fields in instructions are ignored 3693 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3694 * as this is not an instruction software should be using, 3695 * complain to the user. 3696 */ 3697 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3698 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3699 TARGET_FMT_lx "\n", ctx->cia); 3700 } else { 3701 bar = TCG_MO_ST_LD; 3702 } 3703 } 3704 3705 tcg_gen_mb(bar | TCG_BAR_SC); 3706 } 3707 3708 #if !defined(CONFIG_USER_ONLY) 3709 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3710 { 3711 TCGv_i32 t; 3712 TCGLabel *l; 3713 3714 if (!ctx->lazy_tlb_flush) { 3715 return; 3716 } 3717 l = gen_new_label(); 3718 t = tcg_temp_new_i32(); 3719 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3720 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3721 if (global) { 3722 gen_helper_check_tlb_flush_global(cpu_env); 3723 } else { 3724 gen_helper_check_tlb_flush_local(cpu_env); 3725 } 3726 gen_set_label(l); 3727 tcg_temp_free_i32(t); 3728 } 3729 #else 3730 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3731 #endif 3732 3733 /* isync */ 3734 static void gen_isync(DisasContext *ctx) 3735 { 3736 /* 3737 * We need to check for a pending TLB flush. This can only happen in 3738 * kernel mode however so check MSR_PR 3739 */ 3740 if (!ctx->pr) { 3741 gen_check_tlb_flush(ctx, false); 3742 } 3743 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3744 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3745 } 3746 3747 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3748 3749 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3750 { 3751 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3752 TCGv t0 = tcg_temp_new(); 3753 3754 gen_set_access_type(ctx, ACCESS_RES); 3755 gen_addr_reg_index(ctx, t0); 3756 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3757 tcg_gen_mov_tl(cpu_reserve, t0); 3758 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3759 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 3760 tcg_temp_free(t0); 3761 } 3762 3763 #define LARX(name, memop) \ 3764 static void gen_##name(DisasContext *ctx) \ 3765 { \ 3766 gen_load_locked(ctx, memop); \ 3767 } 3768 3769 /* lwarx */ 3770 LARX(lbarx, DEF_MEMOP(MO_UB)) 3771 LARX(lharx, DEF_MEMOP(MO_UW)) 3772 LARX(lwarx, DEF_MEMOP(MO_UL)) 3773 3774 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3775 TCGv EA, TCGCond cond, int addend) 3776 { 3777 TCGv t = tcg_temp_new(); 3778 TCGv t2 = tcg_temp_new(); 3779 TCGv u = tcg_temp_new(); 3780 3781 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3782 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3783 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3784 tcg_gen_addi_tl(u, t, addend); 3785 3786 /* E.g. for fetch and increment bounded... */ 3787 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3788 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3789 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3790 3791 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3792 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3793 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3794 3795 tcg_temp_free(t); 3796 tcg_temp_free(t2); 3797 tcg_temp_free(u); 3798 } 3799 3800 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3801 { 3802 uint32_t gpr_FC = FC(ctx->opcode); 3803 TCGv EA = tcg_temp_new(); 3804 int rt = rD(ctx->opcode); 3805 bool need_serial; 3806 TCGv src, dst; 3807 3808 gen_addr_register(ctx, EA); 3809 dst = cpu_gpr[rt]; 3810 src = cpu_gpr[(rt + 1) & 31]; 3811 3812 need_serial = false; 3813 memop |= MO_ALIGN; 3814 switch (gpr_FC) { 3815 case 0: /* Fetch and add */ 3816 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3817 break; 3818 case 1: /* Fetch and xor */ 3819 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3820 break; 3821 case 2: /* Fetch and or */ 3822 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3823 break; 3824 case 3: /* Fetch and 'and' */ 3825 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3826 break; 3827 case 4: /* Fetch and max unsigned */ 3828 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3829 break; 3830 case 5: /* Fetch and max signed */ 3831 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3832 break; 3833 case 6: /* Fetch and min unsigned */ 3834 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3835 break; 3836 case 7: /* Fetch and min signed */ 3837 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3838 break; 3839 case 8: /* Swap */ 3840 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3841 break; 3842 3843 case 16: /* Compare and swap not equal */ 3844 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3845 need_serial = true; 3846 } else { 3847 TCGv t0 = tcg_temp_new(); 3848 TCGv t1 = tcg_temp_new(); 3849 3850 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3851 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3852 tcg_gen_mov_tl(t1, src); 3853 } else { 3854 tcg_gen_ext32u_tl(t1, src); 3855 } 3856 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3857 cpu_gpr[(rt + 2) & 31], t0); 3858 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3859 tcg_gen_mov_tl(dst, t0); 3860 3861 tcg_temp_free(t0); 3862 tcg_temp_free(t1); 3863 } 3864 break; 3865 3866 case 24: /* Fetch and increment bounded */ 3867 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3868 need_serial = true; 3869 } else { 3870 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3871 } 3872 break; 3873 case 25: /* Fetch and increment equal */ 3874 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3875 need_serial = true; 3876 } else { 3877 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3878 } 3879 break; 3880 case 28: /* Fetch and decrement bounded */ 3881 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3882 need_serial = true; 3883 } else { 3884 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3885 } 3886 break; 3887 3888 default: 3889 /* invoke data storage error handler */ 3890 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3891 } 3892 tcg_temp_free(EA); 3893 3894 if (need_serial) { 3895 /* Restart with exclusive lock. */ 3896 gen_helper_exit_atomic(cpu_env); 3897 ctx->base.is_jmp = DISAS_NORETURN; 3898 } 3899 } 3900 3901 static void gen_lwat(DisasContext *ctx) 3902 { 3903 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3904 } 3905 3906 #ifdef TARGET_PPC64 3907 static void gen_ldat(DisasContext *ctx) 3908 { 3909 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 3910 } 3911 #endif 3912 3913 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3914 { 3915 uint32_t gpr_FC = FC(ctx->opcode); 3916 TCGv EA = tcg_temp_new(); 3917 TCGv src, discard; 3918 3919 gen_addr_register(ctx, EA); 3920 src = cpu_gpr[rD(ctx->opcode)]; 3921 discard = tcg_temp_new(); 3922 3923 memop |= MO_ALIGN; 3924 switch (gpr_FC) { 3925 case 0: /* add and Store */ 3926 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3927 break; 3928 case 1: /* xor and Store */ 3929 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3930 break; 3931 case 2: /* Or and Store */ 3932 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3933 break; 3934 case 3: /* 'and' and Store */ 3935 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3936 break; 3937 case 4: /* Store max unsigned */ 3938 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3939 break; 3940 case 5: /* Store max signed */ 3941 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3942 break; 3943 case 6: /* Store min unsigned */ 3944 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3945 break; 3946 case 7: /* Store min signed */ 3947 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3948 break; 3949 case 24: /* Store twin */ 3950 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3951 /* Restart with exclusive lock. */ 3952 gen_helper_exit_atomic(cpu_env); 3953 ctx->base.is_jmp = DISAS_NORETURN; 3954 } else { 3955 TCGv t = tcg_temp_new(); 3956 TCGv t2 = tcg_temp_new(); 3957 TCGv s = tcg_temp_new(); 3958 TCGv s2 = tcg_temp_new(); 3959 TCGv ea_plus_s = tcg_temp_new(); 3960 3961 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3962 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3963 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3964 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3965 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3966 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3967 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3968 3969 tcg_temp_free(ea_plus_s); 3970 tcg_temp_free(s2); 3971 tcg_temp_free(s); 3972 tcg_temp_free(t2); 3973 tcg_temp_free(t); 3974 } 3975 break; 3976 default: 3977 /* invoke data storage error handler */ 3978 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3979 } 3980 tcg_temp_free(discard); 3981 tcg_temp_free(EA); 3982 } 3983 3984 static void gen_stwat(DisasContext *ctx) 3985 { 3986 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3987 } 3988 3989 #ifdef TARGET_PPC64 3990 static void gen_stdat(DisasContext *ctx) 3991 { 3992 gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 3993 } 3994 #endif 3995 3996 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3997 { 3998 TCGLabel *l1 = gen_new_label(); 3999 TCGLabel *l2 = gen_new_label(); 4000 TCGv t0 = tcg_temp_new(); 4001 int reg = rS(ctx->opcode); 4002 4003 gen_set_access_type(ctx, ACCESS_RES); 4004 gen_addr_reg_index(ctx, t0); 4005 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4006 tcg_temp_free(t0); 4007 4008 t0 = tcg_temp_new(); 4009 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4010 cpu_gpr[reg], ctx->mem_idx, 4011 DEF_MEMOP(memop) | MO_ALIGN); 4012 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4013 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4014 tcg_gen_or_tl(t0, t0, cpu_so); 4015 tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4016 tcg_temp_free(t0); 4017 tcg_gen_br(l2); 4018 4019 gen_set_label(l1); 4020 4021 /* 4022 * Address mismatch implies failure. But we still need to provide 4023 * the memory barrier semantics of the instruction. 4024 */ 4025 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4026 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4027 4028 gen_set_label(l2); 4029 tcg_gen_movi_tl(cpu_reserve, -1); 4030 } 4031 4032 #define STCX(name, memop) \ 4033 static void gen_##name(DisasContext *ctx) \ 4034 { \ 4035 gen_conditional_store(ctx, memop); \ 4036 } 4037 4038 STCX(stbcx_, DEF_MEMOP(MO_UB)) 4039 STCX(sthcx_, DEF_MEMOP(MO_UW)) 4040 STCX(stwcx_, DEF_MEMOP(MO_UL)) 4041 4042 #if defined(TARGET_PPC64) 4043 /* ldarx */ 4044 LARX(ldarx, DEF_MEMOP(MO_Q)) 4045 /* stdcx. */ 4046 STCX(stdcx_, DEF_MEMOP(MO_Q)) 4047 4048 /* lqarx */ 4049 static void gen_lqarx(DisasContext *ctx) 4050 { 4051 int rd = rD(ctx->opcode); 4052 TCGv EA, hi, lo; 4053 4054 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4055 (rd == rB(ctx->opcode)))) { 4056 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4057 return; 4058 } 4059 4060 gen_set_access_type(ctx, ACCESS_RES); 4061 EA = tcg_temp_new(); 4062 gen_addr_reg_index(ctx, EA); 4063 4064 /* Note that the low part is always in RD+1, even in LE mode. */ 4065 lo = cpu_gpr[rd + 1]; 4066 hi = cpu_gpr[rd]; 4067 4068 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4069 if (HAVE_ATOMIC128) { 4070 TCGv_i32 oi = tcg_temp_new_i32(); 4071 if (ctx->le_mode) { 4072 tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN, 4073 ctx->mem_idx)); 4074 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4075 } else { 4076 tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN, 4077 ctx->mem_idx)); 4078 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4079 } 4080 tcg_temp_free_i32(oi); 4081 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4082 } else { 4083 /* Restart with exclusive lock. */ 4084 gen_helper_exit_atomic(cpu_env); 4085 ctx->base.is_jmp = DISAS_NORETURN; 4086 tcg_temp_free(EA); 4087 return; 4088 } 4089 } else if (ctx->le_mode) { 4090 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4091 tcg_gen_mov_tl(cpu_reserve, EA); 4092 gen_addr_add(ctx, EA, EA, 8); 4093 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 4094 } else { 4095 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 4096 tcg_gen_mov_tl(cpu_reserve, EA); 4097 gen_addr_add(ctx, EA, EA, 8); 4098 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 4099 } 4100 tcg_temp_free(EA); 4101 4102 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 4103 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4104 } 4105 4106 /* stqcx. */ 4107 static void gen_stqcx_(DisasContext *ctx) 4108 { 4109 int rs = rS(ctx->opcode); 4110 TCGv EA, hi, lo; 4111 4112 if (unlikely(rs & 1)) { 4113 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4114 return; 4115 } 4116 4117 gen_set_access_type(ctx, ACCESS_RES); 4118 EA = tcg_temp_new(); 4119 gen_addr_reg_index(ctx, EA); 4120 4121 /* Note that the low part is always in RS+1, even in LE mode. */ 4122 lo = cpu_gpr[rs + 1]; 4123 hi = cpu_gpr[rs]; 4124 4125 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4126 if (HAVE_CMPXCHG128) { 4127 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); 4128 if (ctx->le_mode) { 4129 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4130 EA, lo, hi, oi); 4131 } else { 4132 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4133 EA, lo, hi, oi); 4134 } 4135 tcg_temp_free_i32(oi); 4136 } else { 4137 /* Restart with exclusive lock. */ 4138 gen_helper_exit_atomic(cpu_env); 4139 ctx->base.is_jmp = DISAS_NORETURN; 4140 } 4141 tcg_temp_free(EA); 4142 } else { 4143 TCGLabel *lab_fail = gen_new_label(); 4144 TCGLabel *lab_over = gen_new_label(); 4145 TCGv_i64 t0 = tcg_temp_new_i64(); 4146 TCGv_i64 t1 = tcg_temp_new_i64(); 4147 4148 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 4149 tcg_temp_free(EA); 4150 4151 gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 4152 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 4153 ? offsetof(CPUPPCState, reserve_val2) 4154 : offsetof(CPUPPCState, reserve_val))); 4155 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 4156 4157 tcg_gen_addi_i64(t0, cpu_reserve, 8); 4158 gen_qemu_ld64_i64(ctx, t0, t0); 4159 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 4160 ? offsetof(CPUPPCState, reserve_val) 4161 : offsetof(CPUPPCState, reserve_val2))); 4162 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 4163 4164 /* Success */ 4165 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 4166 tcg_gen_addi_i64(t0, cpu_reserve, 8); 4167 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 4168 4169 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4170 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4171 tcg_gen_br(lab_over); 4172 4173 gen_set_label(lab_fail); 4174 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4175 4176 gen_set_label(lab_over); 4177 tcg_gen_movi_tl(cpu_reserve, -1); 4178 tcg_temp_free_i64(t0); 4179 tcg_temp_free_i64(t1); 4180 } 4181 } 4182 #endif /* defined(TARGET_PPC64) */ 4183 4184 /* sync */ 4185 static void gen_sync(DisasContext *ctx) 4186 { 4187 uint32_t l = (ctx->opcode >> 21) & 3; 4188 4189 /* 4190 * We may need to check for a pending TLB flush. 4191 * 4192 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4193 * 4194 * Additionally, this can only happen in kernel mode however so 4195 * check MSR_PR as well. 4196 */ 4197 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4198 gen_check_tlb_flush(ctx, true); 4199 } 4200 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4201 } 4202 4203 /* wait */ 4204 static void gen_wait(DisasContext *ctx) 4205 { 4206 TCGv_i32 t0 = tcg_const_i32(1); 4207 tcg_gen_st_i32(t0, cpu_env, 4208 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4209 tcg_temp_free_i32(t0); 4210 /* Stop translation, as the CPU is supposed to sleep from now */ 4211 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4212 } 4213 4214 #if defined(TARGET_PPC64) 4215 static void gen_doze(DisasContext *ctx) 4216 { 4217 #if defined(CONFIG_USER_ONLY) 4218 GEN_PRIV; 4219 #else 4220 TCGv_i32 t; 4221 4222 CHK_HV; 4223 t = tcg_const_i32(PPC_PM_DOZE); 4224 gen_helper_pminsn(cpu_env, t); 4225 tcg_temp_free_i32(t); 4226 /* Stop translation, as the CPU is supposed to sleep from now */ 4227 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4228 #endif /* defined(CONFIG_USER_ONLY) */ 4229 } 4230 4231 static void gen_nap(DisasContext *ctx) 4232 { 4233 #if defined(CONFIG_USER_ONLY) 4234 GEN_PRIV; 4235 #else 4236 TCGv_i32 t; 4237 4238 CHK_HV; 4239 t = tcg_const_i32(PPC_PM_NAP); 4240 gen_helper_pminsn(cpu_env, t); 4241 tcg_temp_free_i32(t); 4242 /* Stop translation, as the CPU is supposed to sleep from now */ 4243 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4244 #endif /* defined(CONFIG_USER_ONLY) */ 4245 } 4246 4247 static void gen_stop(DisasContext *ctx) 4248 { 4249 #if defined(CONFIG_USER_ONLY) 4250 GEN_PRIV; 4251 #else 4252 TCGv_i32 t; 4253 4254 CHK_HV; 4255 t = tcg_const_i32(PPC_PM_STOP); 4256 gen_helper_pminsn(cpu_env, t); 4257 tcg_temp_free_i32(t); 4258 /* Stop translation, as the CPU is supposed to sleep from now */ 4259 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4260 #endif /* defined(CONFIG_USER_ONLY) */ 4261 } 4262 4263 static void gen_sleep(DisasContext *ctx) 4264 { 4265 #if defined(CONFIG_USER_ONLY) 4266 GEN_PRIV; 4267 #else 4268 TCGv_i32 t; 4269 4270 CHK_HV; 4271 t = tcg_const_i32(PPC_PM_SLEEP); 4272 gen_helper_pminsn(cpu_env, t); 4273 tcg_temp_free_i32(t); 4274 /* Stop translation, as the CPU is supposed to sleep from now */ 4275 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4276 #endif /* defined(CONFIG_USER_ONLY) */ 4277 } 4278 4279 static void gen_rvwinkle(DisasContext *ctx) 4280 { 4281 #if defined(CONFIG_USER_ONLY) 4282 GEN_PRIV; 4283 #else 4284 TCGv_i32 t; 4285 4286 CHK_HV; 4287 t = tcg_const_i32(PPC_PM_RVWINKLE); 4288 gen_helper_pminsn(cpu_env, t); 4289 tcg_temp_free_i32(t); 4290 /* Stop translation, as the CPU is supposed to sleep from now */ 4291 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4292 #endif /* defined(CONFIG_USER_ONLY) */ 4293 } 4294 #endif /* #if defined(TARGET_PPC64) */ 4295 4296 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4297 { 4298 #if defined(TARGET_PPC64) 4299 if (ctx->has_cfar) { 4300 tcg_gen_movi_tl(cpu_cfar, nip); 4301 } 4302 #endif 4303 } 4304 4305 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4306 { 4307 return translator_use_goto_tb(&ctx->base, dest); 4308 } 4309 4310 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 4311 { 4312 int sse = ctx->singlestep_enabled; 4313 if (unlikely(sse)) { 4314 if (sse & GDBSTUB_SINGLE_STEP) { 4315 gen_debug_exception(ctx); 4316 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 4317 gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 4318 } else { 4319 tcg_gen_exit_tb(NULL, 0); 4320 } 4321 } else { 4322 tcg_gen_lookup_and_goto_ptr(); 4323 } 4324 } 4325 4326 /*** Branch ***/ 4327 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4328 { 4329 if (NARROW_MODE(ctx)) { 4330 dest = (uint32_t) dest; 4331 } 4332 if (use_goto_tb(ctx, dest)) { 4333 tcg_gen_goto_tb(n); 4334 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4335 tcg_gen_exit_tb(ctx->base.tb, n); 4336 } else { 4337 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4338 gen_lookup_and_goto_ptr(ctx); 4339 } 4340 } 4341 4342 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4343 { 4344 if (NARROW_MODE(ctx)) { 4345 nip = (uint32_t)nip; 4346 } 4347 tcg_gen_movi_tl(cpu_lr, nip); 4348 } 4349 4350 /* b ba bl bla */ 4351 static void gen_b(DisasContext *ctx) 4352 { 4353 target_ulong li, target; 4354 4355 /* sign extend LI */ 4356 li = LI(ctx->opcode); 4357 li = (li ^ 0x02000000) - 0x02000000; 4358 if (likely(AA(ctx->opcode) == 0)) { 4359 target = ctx->cia + li; 4360 } else { 4361 target = li; 4362 } 4363 if (LK(ctx->opcode)) { 4364 gen_setlr(ctx, ctx->base.pc_next); 4365 } 4366 gen_update_cfar(ctx, ctx->cia); 4367 gen_goto_tb(ctx, 0, target); 4368 ctx->base.is_jmp = DISAS_NORETURN; 4369 } 4370 4371 #define BCOND_IM 0 4372 #define BCOND_LR 1 4373 #define BCOND_CTR 2 4374 #define BCOND_TAR 3 4375 4376 static void gen_bcond(DisasContext *ctx, int type) 4377 { 4378 uint32_t bo = BO(ctx->opcode); 4379 TCGLabel *l1; 4380 TCGv target; 4381 4382 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4383 target = tcg_temp_local_new(); 4384 if (type == BCOND_CTR) { 4385 tcg_gen_mov_tl(target, cpu_ctr); 4386 } else if (type == BCOND_TAR) { 4387 gen_load_spr(target, SPR_TAR); 4388 } else { 4389 tcg_gen_mov_tl(target, cpu_lr); 4390 } 4391 } else { 4392 target = NULL; 4393 } 4394 if (LK(ctx->opcode)) { 4395 gen_setlr(ctx, ctx->base.pc_next); 4396 } 4397 l1 = gen_new_label(); 4398 if ((bo & 0x4) == 0) { 4399 /* Decrement and test CTR */ 4400 TCGv temp = tcg_temp_new(); 4401 4402 if (type == BCOND_CTR) { 4403 /* 4404 * All ISAs up to v3 describe this form of bcctr as invalid but 4405 * some processors, ie. 64-bit server processors compliant with 4406 * arch 2.x, do implement a "test and decrement" logic instead, 4407 * as described in their respective UMs. This logic involves CTR 4408 * to act as both the branch target and a counter, which makes 4409 * it basically useless and thus never used in real code. 4410 * 4411 * This form was hence chosen to trigger extra micro-architectural 4412 * side-effect on real HW needed for the Spectre v2 workaround. 4413 * It is up to guests that implement such workaround, ie. linux, to 4414 * use this form in a way it just triggers the side-effect without 4415 * doing anything else harmful. 4416 */ 4417 if (unlikely(!is_book3s_arch2x(ctx))) { 4418 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4419 tcg_temp_free(temp); 4420 tcg_temp_free(target); 4421 return; 4422 } 4423 4424 if (NARROW_MODE(ctx)) { 4425 tcg_gen_ext32u_tl(temp, cpu_ctr); 4426 } else { 4427 tcg_gen_mov_tl(temp, cpu_ctr); 4428 } 4429 if (bo & 0x2) { 4430 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4431 } else { 4432 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4433 } 4434 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4435 } else { 4436 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4437 if (NARROW_MODE(ctx)) { 4438 tcg_gen_ext32u_tl(temp, cpu_ctr); 4439 } else { 4440 tcg_gen_mov_tl(temp, cpu_ctr); 4441 } 4442 if (bo & 0x2) { 4443 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4444 } else { 4445 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4446 } 4447 } 4448 tcg_temp_free(temp); 4449 } 4450 if ((bo & 0x10) == 0) { 4451 /* Test CR */ 4452 uint32_t bi = BI(ctx->opcode); 4453 uint32_t mask = 0x08 >> (bi & 0x03); 4454 TCGv_i32 temp = tcg_temp_new_i32(); 4455 4456 if (bo & 0x8) { 4457 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4458 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4459 } else { 4460 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4461 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4462 } 4463 tcg_temp_free_i32(temp); 4464 } 4465 gen_update_cfar(ctx, ctx->cia); 4466 if (type == BCOND_IM) { 4467 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4468 if (likely(AA(ctx->opcode) == 0)) { 4469 gen_goto_tb(ctx, 0, ctx->cia + li); 4470 } else { 4471 gen_goto_tb(ctx, 0, li); 4472 } 4473 } else { 4474 if (NARROW_MODE(ctx)) { 4475 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4476 } else { 4477 tcg_gen_andi_tl(cpu_nip, target, ~3); 4478 } 4479 gen_lookup_and_goto_ptr(ctx); 4480 tcg_temp_free(target); 4481 } 4482 if ((bo & 0x14) != 0x14) { 4483 /* fallthrough case */ 4484 gen_set_label(l1); 4485 gen_goto_tb(ctx, 1, ctx->base.pc_next); 4486 } 4487 ctx->base.is_jmp = DISAS_NORETURN; 4488 } 4489 4490 static void gen_bc(DisasContext *ctx) 4491 { 4492 gen_bcond(ctx, BCOND_IM); 4493 } 4494 4495 static void gen_bcctr(DisasContext *ctx) 4496 { 4497 gen_bcond(ctx, BCOND_CTR); 4498 } 4499 4500 static void gen_bclr(DisasContext *ctx) 4501 { 4502 gen_bcond(ctx, BCOND_LR); 4503 } 4504 4505 static void gen_bctar(DisasContext *ctx) 4506 { 4507 gen_bcond(ctx, BCOND_TAR); 4508 } 4509 4510 /*** Condition register logical ***/ 4511 #define GEN_CRLOGIC(name, tcg_op, opc) \ 4512 static void glue(gen_, name)(DisasContext *ctx) \ 4513 { \ 4514 uint8_t bitmask; \ 4515 int sh; \ 4516 TCGv_i32 t0, t1; \ 4517 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4518 t0 = tcg_temp_new_i32(); \ 4519 if (sh > 0) \ 4520 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4521 else if (sh < 0) \ 4522 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4523 else \ 4524 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4525 t1 = tcg_temp_new_i32(); \ 4526 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4527 if (sh > 0) \ 4528 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4529 else if (sh < 0) \ 4530 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4531 else \ 4532 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4533 tcg_op(t0, t0, t1); \ 4534 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4535 tcg_gen_andi_i32(t0, t0, bitmask); \ 4536 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4537 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4538 tcg_temp_free_i32(t0); \ 4539 tcg_temp_free_i32(t1); \ 4540 } 4541 4542 /* crand */ 4543 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4544 /* crandc */ 4545 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4546 /* creqv */ 4547 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4548 /* crnand */ 4549 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4550 /* crnor */ 4551 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4552 /* cror */ 4553 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4554 /* crorc */ 4555 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4556 /* crxor */ 4557 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4558 4559 /* mcrf */ 4560 static void gen_mcrf(DisasContext *ctx) 4561 { 4562 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4563 } 4564 4565 /*** System linkage ***/ 4566 4567 /* rfi (supervisor only) */ 4568 static void gen_rfi(DisasContext *ctx) 4569 { 4570 #if defined(CONFIG_USER_ONLY) 4571 GEN_PRIV; 4572 #else 4573 /* 4574 * This instruction doesn't exist anymore on 64-bit server 4575 * processors compliant with arch 2.x 4576 */ 4577 if (is_book3s_arch2x(ctx)) { 4578 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4579 return; 4580 } 4581 /* Restore CPU state */ 4582 CHK_SV; 4583 gen_icount_io_start(ctx); 4584 gen_update_cfar(ctx, ctx->cia); 4585 gen_helper_rfi(cpu_env); 4586 ctx->base.is_jmp = DISAS_EXIT; 4587 #endif 4588 } 4589 4590 #if defined(TARGET_PPC64) 4591 static void gen_rfid(DisasContext *ctx) 4592 { 4593 #if defined(CONFIG_USER_ONLY) 4594 GEN_PRIV; 4595 #else 4596 /* Restore CPU state */ 4597 CHK_SV; 4598 gen_icount_io_start(ctx); 4599 gen_update_cfar(ctx, ctx->cia); 4600 gen_helper_rfid(cpu_env); 4601 ctx->base.is_jmp = DISAS_EXIT; 4602 #endif 4603 } 4604 4605 #if !defined(CONFIG_USER_ONLY) 4606 static void gen_rfscv(DisasContext *ctx) 4607 { 4608 #if defined(CONFIG_USER_ONLY) 4609 GEN_PRIV; 4610 #else 4611 /* Restore CPU state */ 4612 CHK_SV; 4613 gen_icount_io_start(ctx); 4614 gen_update_cfar(ctx, ctx->cia); 4615 gen_helper_rfscv(cpu_env); 4616 ctx->base.is_jmp = DISAS_EXIT; 4617 #endif 4618 } 4619 #endif 4620 4621 static void gen_hrfid(DisasContext *ctx) 4622 { 4623 #if defined(CONFIG_USER_ONLY) 4624 GEN_PRIV; 4625 #else 4626 /* Restore CPU state */ 4627 CHK_HV; 4628 gen_helper_hrfid(cpu_env); 4629 ctx->base.is_jmp = DISAS_EXIT; 4630 #endif 4631 } 4632 #endif 4633 4634 /* sc */ 4635 #if defined(CONFIG_USER_ONLY) 4636 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4637 #else 4638 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4639 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4640 #endif 4641 static void gen_sc(DisasContext *ctx) 4642 { 4643 uint32_t lev; 4644 4645 lev = (ctx->opcode >> 5) & 0x7F; 4646 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4647 } 4648 4649 #if defined(TARGET_PPC64) 4650 #if !defined(CONFIG_USER_ONLY) 4651 static void gen_scv(DisasContext *ctx) 4652 { 4653 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 4654 4655 /* Set the PC back to the faulting instruction. */ 4656 gen_update_nip(ctx, ctx->cia); 4657 gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 4658 4659 ctx->base.is_jmp = DISAS_NORETURN; 4660 } 4661 #endif 4662 #endif 4663 4664 /*** Trap ***/ 4665 4666 /* Check for unconditional traps (always or never) */ 4667 static bool check_unconditional_trap(DisasContext *ctx) 4668 { 4669 /* Trap never */ 4670 if (TO(ctx->opcode) == 0) { 4671 return true; 4672 } 4673 /* Trap always */ 4674 if (TO(ctx->opcode) == 31) { 4675 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4676 return true; 4677 } 4678 return false; 4679 } 4680 4681 /* tw */ 4682 static void gen_tw(DisasContext *ctx) 4683 { 4684 TCGv_i32 t0; 4685 4686 if (check_unconditional_trap(ctx)) { 4687 return; 4688 } 4689 t0 = tcg_const_i32(TO(ctx->opcode)); 4690 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4691 t0); 4692 tcg_temp_free_i32(t0); 4693 } 4694 4695 /* twi */ 4696 static void gen_twi(DisasContext *ctx) 4697 { 4698 TCGv t0; 4699 TCGv_i32 t1; 4700 4701 if (check_unconditional_trap(ctx)) { 4702 return; 4703 } 4704 t0 = tcg_const_tl(SIMM(ctx->opcode)); 4705 t1 = tcg_const_i32(TO(ctx->opcode)); 4706 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4707 tcg_temp_free(t0); 4708 tcg_temp_free_i32(t1); 4709 } 4710 4711 #if defined(TARGET_PPC64) 4712 /* td */ 4713 static void gen_td(DisasContext *ctx) 4714 { 4715 TCGv_i32 t0; 4716 4717 if (check_unconditional_trap(ctx)) { 4718 return; 4719 } 4720 t0 = tcg_const_i32(TO(ctx->opcode)); 4721 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4722 t0); 4723 tcg_temp_free_i32(t0); 4724 } 4725 4726 /* tdi */ 4727 static void gen_tdi(DisasContext *ctx) 4728 { 4729 TCGv t0; 4730 TCGv_i32 t1; 4731 4732 if (check_unconditional_trap(ctx)) { 4733 return; 4734 } 4735 t0 = tcg_const_tl(SIMM(ctx->opcode)); 4736 t1 = tcg_const_i32(TO(ctx->opcode)); 4737 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4738 tcg_temp_free(t0); 4739 tcg_temp_free_i32(t1); 4740 } 4741 #endif 4742 4743 /*** Processor control ***/ 4744 4745 /* mcrxr */ 4746 static void gen_mcrxr(DisasContext *ctx) 4747 { 4748 TCGv_i32 t0 = tcg_temp_new_i32(); 4749 TCGv_i32 t1 = tcg_temp_new_i32(); 4750 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4751 4752 tcg_gen_trunc_tl_i32(t0, cpu_so); 4753 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4754 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4755 tcg_gen_shli_i32(t0, t0, 3); 4756 tcg_gen_shli_i32(t1, t1, 2); 4757 tcg_gen_shli_i32(dst, dst, 1); 4758 tcg_gen_or_i32(dst, dst, t0); 4759 tcg_gen_or_i32(dst, dst, t1); 4760 tcg_temp_free_i32(t0); 4761 tcg_temp_free_i32(t1); 4762 4763 tcg_gen_movi_tl(cpu_so, 0); 4764 tcg_gen_movi_tl(cpu_ov, 0); 4765 tcg_gen_movi_tl(cpu_ca, 0); 4766 } 4767 4768 #ifdef TARGET_PPC64 4769 /* mcrxrx */ 4770 static void gen_mcrxrx(DisasContext *ctx) 4771 { 4772 TCGv t0 = tcg_temp_new(); 4773 TCGv t1 = tcg_temp_new(); 4774 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4775 4776 /* copy OV and OV32 */ 4777 tcg_gen_shli_tl(t0, cpu_ov, 1); 4778 tcg_gen_or_tl(t0, t0, cpu_ov32); 4779 tcg_gen_shli_tl(t0, t0, 2); 4780 /* copy CA and CA32 */ 4781 tcg_gen_shli_tl(t1, cpu_ca, 1); 4782 tcg_gen_or_tl(t1, t1, cpu_ca32); 4783 tcg_gen_or_tl(t0, t0, t1); 4784 tcg_gen_trunc_tl_i32(dst, t0); 4785 tcg_temp_free(t0); 4786 tcg_temp_free(t1); 4787 } 4788 #endif 4789 4790 /* mfcr mfocrf */ 4791 static void gen_mfcr(DisasContext *ctx) 4792 { 4793 uint32_t crm, crn; 4794 4795 if (likely(ctx->opcode & 0x00100000)) { 4796 crm = CRM(ctx->opcode); 4797 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4798 crn = ctz32(crm); 4799 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4800 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4801 cpu_gpr[rD(ctx->opcode)], crn * 4); 4802 } 4803 } else { 4804 TCGv_i32 t0 = tcg_temp_new_i32(); 4805 tcg_gen_mov_i32(t0, cpu_crf[0]); 4806 tcg_gen_shli_i32(t0, t0, 4); 4807 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4808 tcg_gen_shli_i32(t0, t0, 4); 4809 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4810 tcg_gen_shli_i32(t0, t0, 4); 4811 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4812 tcg_gen_shli_i32(t0, t0, 4); 4813 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4814 tcg_gen_shli_i32(t0, t0, 4); 4815 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4816 tcg_gen_shli_i32(t0, t0, 4); 4817 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4818 tcg_gen_shli_i32(t0, t0, 4); 4819 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4820 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4821 tcg_temp_free_i32(t0); 4822 } 4823 } 4824 4825 /* mfmsr */ 4826 static void gen_mfmsr(DisasContext *ctx) 4827 { 4828 CHK_SV; 4829 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4830 } 4831 4832 /* mfspr */ 4833 static inline void gen_op_mfspr(DisasContext *ctx) 4834 { 4835 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4836 uint32_t sprn = SPR(ctx->opcode); 4837 4838 #if defined(CONFIG_USER_ONLY) 4839 read_cb = ctx->spr_cb[sprn].uea_read; 4840 #else 4841 if (ctx->pr) { 4842 read_cb = ctx->spr_cb[sprn].uea_read; 4843 } else if (ctx->hv) { 4844 read_cb = ctx->spr_cb[sprn].hea_read; 4845 } else { 4846 read_cb = ctx->spr_cb[sprn].oea_read; 4847 } 4848 #endif 4849 if (likely(read_cb != NULL)) { 4850 if (likely(read_cb != SPR_NOACCESS)) { 4851 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4852 } else { 4853 /* Privilege exception */ 4854 /* 4855 * This is a hack to avoid warnings when running Linux: 4856 * this OS breaks the PowerPC virtualisation model, 4857 * allowing userland application to read the PVR 4858 */ 4859 if (sprn != SPR_PVR) { 4860 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4861 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4862 ctx->cia); 4863 } 4864 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4865 } 4866 } else { 4867 /* ISA 2.07 defines these as no-ops */ 4868 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4869 (sprn >= 808 && sprn <= 811)) { 4870 /* This is a nop */ 4871 return; 4872 } 4873 /* Not defined */ 4874 qemu_log_mask(LOG_GUEST_ERROR, 4875 "Trying to read invalid spr %d (0x%03x) at " 4876 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4877 4878 /* 4879 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4880 * generate a priv, a hv emu or a no-op 4881 */ 4882 if (sprn & 0x10) { 4883 if (ctx->pr) { 4884 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4885 } 4886 } else { 4887 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4888 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4889 } 4890 } 4891 } 4892 } 4893 4894 static void gen_mfspr(DisasContext *ctx) 4895 { 4896 gen_op_mfspr(ctx); 4897 } 4898 4899 /* mftb */ 4900 static void gen_mftb(DisasContext *ctx) 4901 { 4902 gen_op_mfspr(ctx); 4903 } 4904 4905 /* mtcrf mtocrf*/ 4906 static void gen_mtcrf(DisasContext *ctx) 4907 { 4908 uint32_t crm, crn; 4909 4910 crm = CRM(ctx->opcode); 4911 if (likely((ctx->opcode & 0x00100000))) { 4912 if (crm && ((crm & (crm - 1)) == 0)) { 4913 TCGv_i32 temp = tcg_temp_new_i32(); 4914 crn = ctz32(crm); 4915 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4916 tcg_gen_shri_i32(temp, temp, crn * 4); 4917 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4918 tcg_temp_free_i32(temp); 4919 } 4920 } else { 4921 TCGv_i32 temp = tcg_temp_new_i32(); 4922 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4923 for (crn = 0 ; crn < 8 ; crn++) { 4924 if (crm & (1 << crn)) { 4925 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4926 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4927 } 4928 } 4929 tcg_temp_free_i32(temp); 4930 } 4931 } 4932 4933 /* mtmsr */ 4934 #if defined(TARGET_PPC64) 4935 static void gen_mtmsrd(DisasContext *ctx) 4936 { 4937 if (unlikely(!is_book3s_arch2x(ctx))) { 4938 gen_invalid(ctx); 4939 return; 4940 } 4941 4942 CHK_SV; 4943 4944 #if !defined(CONFIG_USER_ONLY) 4945 gen_icount_io_start(ctx); 4946 if (ctx->opcode & 0x00010000) { 4947 /* L=1 form only updates EE and RI */ 4948 TCGv t0 = tcg_temp_new(); 4949 TCGv t1 = tcg_temp_new(); 4950 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4951 (1 << MSR_RI) | (1 << MSR_EE)); 4952 tcg_gen_andi_tl(t1, cpu_msr, 4953 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4954 tcg_gen_or_tl(t1, t1, t0); 4955 4956 gen_helper_store_msr(cpu_env, t1); 4957 tcg_temp_free(t0); 4958 tcg_temp_free(t1); 4959 4960 } else { 4961 /* 4962 * XXX: we need to update nip before the store if we enter 4963 * power saving mode, we will exit the loop directly from 4964 * ppc_store_msr 4965 */ 4966 gen_update_nip(ctx, ctx->base.pc_next); 4967 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4968 } 4969 /* Must stop the translation as machine state (may have) changed */ 4970 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4971 #endif /* !defined(CONFIG_USER_ONLY) */ 4972 } 4973 #endif /* defined(TARGET_PPC64) */ 4974 4975 static void gen_mtmsr(DisasContext *ctx) 4976 { 4977 CHK_SV; 4978 4979 #if !defined(CONFIG_USER_ONLY) 4980 gen_icount_io_start(ctx); 4981 if (ctx->opcode & 0x00010000) { 4982 /* L=1 form only updates EE and RI */ 4983 TCGv t0 = tcg_temp_new(); 4984 TCGv t1 = tcg_temp_new(); 4985 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4986 (1 << MSR_RI) | (1 << MSR_EE)); 4987 tcg_gen_andi_tl(t1, cpu_msr, 4988 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4989 tcg_gen_or_tl(t1, t1, t0); 4990 4991 gen_helper_store_msr(cpu_env, t1); 4992 tcg_temp_free(t0); 4993 tcg_temp_free(t1); 4994 4995 } else { 4996 TCGv msr = tcg_temp_new(); 4997 4998 /* 4999 * XXX: we need to update nip before the store if we enter 5000 * power saving mode, we will exit the loop directly from 5001 * ppc_store_msr 5002 */ 5003 gen_update_nip(ctx, ctx->base.pc_next); 5004 #if defined(TARGET_PPC64) 5005 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 5006 #else 5007 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 5008 #endif 5009 gen_helper_store_msr(cpu_env, msr); 5010 tcg_temp_free(msr); 5011 } 5012 /* Must stop the translation as machine state (may have) changed */ 5013 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5014 #endif 5015 } 5016 5017 /* mtspr */ 5018 static void gen_mtspr(DisasContext *ctx) 5019 { 5020 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5021 uint32_t sprn = SPR(ctx->opcode); 5022 5023 #if defined(CONFIG_USER_ONLY) 5024 write_cb = ctx->spr_cb[sprn].uea_write; 5025 #else 5026 if (ctx->pr) { 5027 write_cb = ctx->spr_cb[sprn].uea_write; 5028 } else if (ctx->hv) { 5029 write_cb = ctx->spr_cb[sprn].hea_write; 5030 } else { 5031 write_cb = ctx->spr_cb[sprn].oea_write; 5032 } 5033 #endif 5034 if (likely(write_cb != NULL)) { 5035 if (likely(write_cb != SPR_NOACCESS)) { 5036 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5037 } else { 5038 /* Privilege exception */ 5039 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 5040 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 5041 ctx->cia); 5042 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5043 } 5044 } else { 5045 /* ISA 2.07 defines these as no-ops */ 5046 if ((ctx->insns_flags2 & PPC2_ISA207S) && 5047 (sprn >= 808 && sprn <= 811)) { 5048 /* This is a nop */ 5049 return; 5050 } 5051 5052 /* Not defined */ 5053 qemu_log_mask(LOG_GUEST_ERROR, 5054 "Trying to write invalid spr %d (0x%03x) at " 5055 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5056 5057 5058 /* 5059 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5060 * generate a priv, a hv emu or a no-op 5061 */ 5062 if (sprn & 0x10) { 5063 if (ctx->pr) { 5064 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5065 } 5066 } else { 5067 if (ctx->pr || sprn == 0) { 5068 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5069 } 5070 } 5071 } 5072 } 5073 5074 #if defined(TARGET_PPC64) 5075 /* setb */ 5076 static void gen_setb(DisasContext *ctx) 5077 { 5078 TCGv_i32 t0 = tcg_temp_new_i32(); 5079 TCGv_i32 t8 = tcg_temp_new_i32(); 5080 TCGv_i32 tm1 = tcg_temp_new_i32(); 5081 int crf = crfS(ctx->opcode); 5082 5083 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5084 tcg_gen_movi_i32(t8, 8); 5085 tcg_gen_movi_i32(tm1, -1); 5086 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5087 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5088 5089 tcg_temp_free_i32(t0); 5090 tcg_temp_free_i32(t8); 5091 tcg_temp_free_i32(tm1); 5092 } 5093 #endif 5094 5095 /*** Cache management ***/ 5096 5097 /* dcbf */ 5098 static void gen_dcbf(DisasContext *ctx) 5099 { 5100 /* XXX: specification says this is treated as a load by the MMU */ 5101 TCGv t0; 5102 gen_set_access_type(ctx, ACCESS_CACHE); 5103 t0 = tcg_temp_new(); 5104 gen_addr_reg_index(ctx, t0); 5105 gen_qemu_ld8u(ctx, t0, t0); 5106 tcg_temp_free(t0); 5107 } 5108 5109 /* dcbfep (external PID dcbf) */ 5110 static void gen_dcbfep(DisasContext *ctx) 5111 { 5112 /* XXX: specification says this is treated as a load by the MMU */ 5113 TCGv t0; 5114 CHK_SV; 5115 gen_set_access_type(ctx, ACCESS_CACHE); 5116 t0 = tcg_temp_new(); 5117 gen_addr_reg_index(ctx, t0); 5118 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 5119 tcg_temp_free(t0); 5120 } 5121 5122 /* dcbi (Supervisor only) */ 5123 static void gen_dcbi(DisasContext *ctx) 5124 { 5125 #if defined(CONFIG_USER_ONLY) 5126 GEN_PRIV; 5127 #else 5128 TCGv EA, val; 5129 5130 CHK_SV; 5131 EA = tcg_temp_new(); 5132 gen_set_access_type(ctx, ACCESS_CACHE); 5133 gen_addr_reg_index(ctx, EA); 5134 val = tcg_temp_new(); 5135 /* XXX: specification says this should be treated as a store by the MMU */ 5136 gen_qemu_ld8u(ctx, val, EA); 5137 gen_qemu_st8(ctx, val, EA); 5138 tcg_temp_free(val); 5139 tcg_temp_free(EA); 5140 #endif /* defined(CONFIG_USER_ONLY) */ 5141 } 5142 5143 /* dcdst */ 5144 static void gen_dcbst(DisasContext *ctx) 5145 { 5146 /* XXX: specification say this is treated as a load by the MMU */ 5147 TCGv t0; 5148 gen_set_access_type(ctx, ACCESS_CACHE); 5149 t0 = tcg_temp_new(); 5150 gen_addr_reg_index(ctx, t0); 5151 gen_qemu_ld8u(ctx, t0, t0); 5152 tcg_temp_free(t0); 5153 } 5154 5155 /* dcbstep (dcbstep External PID version) */ 5156 static void gen_dcbstep(DisasContext *ctx) 5157 { 5158 /* XXX: specification say this is treated as a load by the MMU */ 5159 TCGv t0; 5160 gen_set_access_type(ctx, ACCESS_CACHE); 5161 t0 = tcg_temp_new(); 5162 gen_addr_reg_index(ctx, t0); 5163 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 5164 tcg_temp_free(t0); 5165 } 5166 5167 /* dcbt */ 5168 static void gen_dcbt(DisasContext *ctx) 5169 { 5170 /* 5171 * interpreted as no-op 5172 * XXX: specification say this is treated as a load by the MMU but 5173 * does not generate any exception 5174 */ 5175 } 5176 5177 /* dcbtep */ 5178 static void gen_dcbtep(DisasContext *ctx) 5179 { 5180 /* 5181 * interpreted as no-op 5182 * XXX: specification say this is treated as a load by the MMU but 5183 * does not generate any exception 5184 */ 5185 } 5186 5187 /* dcbtst */ 5188 static void gen_dcbtst(DisasContext *ctx) 5189 { 5190 /* 5191 * interpreted as no-op 5192 * XXX: specification say this is treated as a load by the MMU but 5193 * does not generate any exception 5194 */ 5195 } 5196 5197 /* dcbtstep */ 5198 static void gen_dcbtstep(DisasContext *ctx) 5199 { 5200 /* 5201 * interpreted as no-op 5202 * XXX: specification say this is treated as a load by the MMU but 5203 * does not generate any exception 5204 */ 5205 } 5206 5207 /* dcbtls */ 5208 static void gen_dcbtls(DisasContext *ctx) 5209 { 5210 /* Always fails locking the cache */ 5211 TCGv t0 = tcg_temp_new(); 5212 gen_load_spr(t0, SPR_Exxx_L1CSR0); 5213 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5214 gen_store_spr(SPR_Exxx_L1CSR0, t0); 5215 tcg_temp_free(t0); 5216 } 5217 5218 /* dcbz */ 5219 static void gen_dcbz(DisasContext *ctx) 5220 { 5221 TCGv tcgv_addr; 5222 TCGv_i32 tcgv_op; 5223 5224 gen_set_access_type(ctx, ACCESS_CACHE); 5225 tcgv_addr = tcg_temp_new(); 5226 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5227 gen_addr_reg_index(ctx, tcgv_addr); 5228 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5229 tcg_temp_free(tcgv_addr); 5230 tcg_temp_free_i32(tcgv_op); 5231 } 5232 5233 /* dcbzep */ 5234 static void gen_dcbzep(DisasContext *ctx) 5235 { 5236 TCGv tcgv_addr; 5237 TCGv_i32 tcgv_op; 5238 5239 gen_set_access_type(ctx, ACCESS_CACHE); 5240 tcgv_addr = tcg_temp_new(); 5241 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5242 gen_addr_reg_index(ctx, tcgv_addr); 5243 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 5244 tcg_temp_free(tcgv_addr); 5245 tcg_temp_free_i32(tcgv_op); 5246 } 5247 5248 /* dst / dstt */ 5249 static void gen_dst(DisasContext *ctx) 5250 { 5251 if (rA(ctx->opcode) == 0) { 5252 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5253 } else { 5254 /* interpreted as no-op */ 5255 } 5256 } 5257 5258 /* dstst /dststt */ 5259 static void gen_dstst(DisasContext *ctx) 5260 { 5261 if (rA(ctx->opcode) == 0) { 5262 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5263 } else { 5264 /* interpreted as no-op */ 5265 } 5266 5267 } 5268 5269 /* dss / dssall */ 5270 static void gen_dss(DisasContext *ctx) 5271 { 5272 /* interpreted as no-op */ 5273 } 5274 5275 /* icbi */ 5276 static void gen_icbi(DisasContext *ctx) 5277 { 5278 TCGv t0; 5279 gen_set_access_type(ctx, ACCESS_CACHE); 5280 t0 = tcg_temp_new(); 5281 gen_addr_reg_index(ctx, t0); 5282 gen_helper_icbi(cpu_env, t0); 5283 tcg_temp_free(t0); 5284 } 5285 5286 /* icbiep */ 5287 static void gen_icbiep(DisasContext *ctx) 5288 { 5289 TCGv t0; 5290 gen_set_access_type(ctx, ACCESS_CACHE); 5291 t0 = tcg_temp_new(); 5292 gen_addr_reg_index(ctx, t0); 5293 gen_helper_icbiep(cpu_env, t0); 5294 tcg_temp_free(t0); 5295 } 5296 5297 /* Optional: */ 5298 /* dcba */ 5299 static void gen_dcba(DisasContext *ctx) 5300 { 5301 /* 5302 * interpreted as no-op 5303 * XXX: specification say this is treated as a store by the MMU 5304 * but does not generate any exception 5305 */ 5306 } 5307 5308 /*** Segment register manipulation ***/ 5309 /* Supervisor only: */ 5310 5311 /* mfsr */ 5312 static void gen_mfsr(DisasContext *ctx) 5313 { 5314 #if defined(CONFIG_USER_ONLY) 5315 GEN_PRIV; 5316 #else 5317 TCGv t0; 5318 5319 CHK_SV; 5320 t0 = tcg_const_tl(SR(ctx->opcode)); 5321 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5322 tcg_temp_free(t0); 5323 #endif /* defined(CONFIG_USER_ONLY) */ 5324 } 5325 5326 /* mfsrin */ 5327 static void gen_mfsrin(DisasContext *ctx) 5328 { 5329 #if defined(CONFIG_USER_ONLY) 5330 GEN_PRIV; 5331 #else 5332 TCGv t0; 5333 5334 CHK_SV; 5335 t0 = tcg_temp_new(); 5336 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5337 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5338 tcg_temp_free(t0); 5339 #endif /* defined(CONFIG_USER_ONLY) */ 5340 } 5341 5342 /* mtsr */ 5343 static void gen_mtsr(DisasContext *ctx) 5344 { 5345 #if defined(CONFIG_USER_ONLY) 5346 GEN_PRIV; 5347 #else 5348 TCGv t0; 5349 5350 CHK_SV; 5351 t0 = tcg_const_tl(SR(ctx->opcode)); 5352 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5353 tcg_temp_free(t0); 5354 #endif /* defined(CONFIG_USER_ONLY) */ 5355 } 5356 5357 /* mtsrin */ 5358 static void gen_mtsrin(DisasContext *ctx) 5359 { 5360 #if defined(CONFIG_USER_ONLY) 5361 GEN_PRIV; 5362 #else 5363 TCGv t0; 5364 CHK_SV; 5365 5366 t0 = tcg_temp_new(); 5367 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5368 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5369 tcg_temp_free(t0); 5370 #endif /* defined(CONFIG_USER_ONLY) */ 5371 } 5372 5373 #if defined(TARGET_PPC64) 5374 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5375 5376 /* mfsr */ 5377 static void gen_mfsr_64b(DisasContext *ctx) 5378 { 5379 #if defined(CONFIG_USER_ONLY) 5380 GEN_PRIV; 5381 #else 5382 TCGv t0; 5383 5384 CHK_SV; 5385 t0 = tcg_const_tl(SR(ctx->opcode)); 5386 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5387 tcg_temp_free(t0); 5388 #endif /* defined(CONFIG_USER_ONLY) */ 5389 } 5390 5391 /* mfsrin */ 5392 static void gen_mfsrin_64b(DisasContext *ctx) 5393 { 5394 #if defined(CONFIG_USER_ONLY) 5395 GEN_PRIV; 5396 #else 5397 TCGv t0; 5398 5399 CHK_SV; 5400 t0 = tcg_temp_new(); 5401 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5402 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5403 tcg_temp_free(t0); 5404 #endif /* defined(CONFIG_USER_ONLY) */ 5405 } 5406 5407 /* mtsr */ 5408 static void gen_mtsr_64b(DisasContext *ctx) 5409 { 5410 #if defined(CONFIG_USER_ONLY) 5411 GEN_PRIV; 5412 #else 5413 TCGv t0; 5414 5415 CHK_SV; 5416 t0 = tcg_const_tl(SR(ctx->opcode)); 5417 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5418 tcg_temp_free(t0); 5419 #endif /* defined(CONFIG_USER_ONLY) */ 5420 } 5421 5422 /* mtsrin */ 5423 static void gen_mtsrin_64b(DisasContext *ctx) 5424 { 5425 #if defined(CONFIG_USER_ONLY) 5426 GEN_PRIV; 5427 #else 5428 TCGv t0; 5429 5430 CHK_SV; 5431 t0 = tcg_temp_new(); 5432 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5433 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5434 tcg_temp_free(t0); 5435 #endif /* defined(CONFIG_USER_ONLY) */ 5436 } 5437 5438 /* slbmte */ 5439 static void gen_slbmte(DisasContext *ctx) 5440 { 5441 #if defined(CONFIG_USER_ONLY) 5442 GEN_PRIV; 5443 #else 5444 CHK_SV; 5445 5446 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5447 cpu_gpr[rS(ctx->opcode)]); 5448 #endif /* defined(CONFIG_USER_ONLY) */ 5449 } 5450 5451 static void gen_slbmfee(DisasContext *ctx) 5452 { 5453 #if defined(CONFIG_USER_ONLY) 5454 GEN_PRIV; 5455 #else 5456 CHK_SV; 5457 5458 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5459 cpu_gpr[rB(ctx->opcode)]); 5460 #endif /* defined(CONFIG_USER_ONLY) */ 5461 } 5462 5463 static void gen_slbmfev(DisasContext *ctx) 5464 { 5465 #if defined(CONFIG_USER_ONLY) 5466 GEN_PRIV; 5467 #else 5468 CHK_SV; 5469 5470 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5471 cpu_gpr[rB(ctx->opcode)]); 5472 #endif /* defined(CONFIG_USER_ONLY) */ 5473 } 5474 5475 static void gen_slbfee_(DisasContext *ctx) 5476 { 5477 #if defined(CONFIG_USER_ONLY) 5478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5479 #else 5480 TCGLabel *l1, *l2; 5481 5482 if (unlikely(ctx->pr)) { 5483 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5484 return; 5485 } 5486 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5487 cpu_gpr[rB(ctx->opcode)]); 5488 l1 = gen_new_label(); 5489 l2 = gen_new_label(); 5490 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5491 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5492 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5493 tcg_gen_br(l2); 5494 gen_set_label(l1); 5495 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5496 gen_set_label(l2); 5497 #endif 5498 } 5499 #endif /* defined(TARGET_PPC64) */ 5500 5501 /*** Lookaside buffer management ***/ 5502 /* Optional & supervisor only: */ 5503 5504 /* tlbia */ 5505 static void gen_tlbia(DisasContext *ctx) 5506 { 5507 #if defined(CONFIG_USER_ONLY) 5508 GEN_PRIV; 5509 #else 5510 CHK_HV; 5511 5512 gen_helper_tlbia(cpu_env); 5513 #endif /* defined(CONFIG_USER_ONLY) */ 5514 } 5515 5516 /* tlbiel */ 5517 static void gen_tlbiel(DisasContext *ctx) 5518 { 5519 #if defined(CONFIG_USER_ONLY) 5520 GEN_PRIV; 5521 #else 5522 bool psr = (ctx->opcode >> 17) & 0x1; 5523 5524 if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) { 5525 /* 5526 * tlbiel is privileged except when PSR=0 and HR=1, making it 5527 * hypervisor privileged. 5528 */ 5529 GEN_PRIV; 5530 } 5531 5532 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5533 #endif /* defined(CONFIG_USER_ONLY) */ 5534 } 5535 5536 /* tlbie */ 5537 static void gen_tlbie(DisasContext *ctx) 5538 { 5539 #if defined(CONFIG_USER_ONLY) 5540 GEN_PRIV; 5541 #else 5542 bool psr = (ctx->opcode >> 17) & 0x1; 5543 TCGv_i32 t1; 5544 5545 if (ctx->pr) { 5546 /* tlbie is privileged... */ 5547 GEN_PRIV; 5548 } else if (!ctx->hv) { 5549 if (!ctx->gtse || (!psr && ctx->hr)) { 5550 /* 5551 * ... except when GTSE=0 or when PSR=0 and HR=1, making it 5552 * hypervisor privileged. 5553 */ 5554 GEN_PRIV; 5555 } 5556 } 5557 5558 if (NARROW_MODE(ctx)) { 5559 TCGv t0 = tcg_temp_new(); 5560 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5561 gen_helper_tlbie(cpu_env, t0); 5562 tcg_temp_free(t0); 5563 } else { 5564 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5565 } 5566 t1 = tcg_temp_new_i32(); 5567 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5568 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5569 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5570 tcg_temp_free_i32(t1); 5571 #endif /* defined(CONFIG_USER_ONLY) */ 5572 } 5573 5574 /* tlbsync */ 5575 static void gen_tlbsync(DisasContext *ctx) 5576 { 5577 #if defined(CONFIG_USER_ONLY) 5578 GEN_PRIV; 5579 #else 5580 5581 if (ctx->gtse) { 5582 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 5583 } else { 5584 CHK_HV; /* Else hypervisor privileged */ 5585 } 5586 5587 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5588 if (ctx->insns_flags & PPC_BOOKE) { 5589 gen_check_tlb_flush(ctx, true); 5590 } 5591 #endif /* defined(CONFIG_USER_ONLY) */ 5592 } 5593 5594 #if defined(TARGET_PPC64) 5595 /* slbia */ 5596 static void gen_slbia(DisasContext *ctx) 5597 { 5598 #if defined(CONFIG_USER_ONLY) 5599 GEN_PRIV; 5600 #else 5601 uint32_t ih = (ctx->opcode >> 21) & 0x7; 5602 TCGv_i32 t0 = tcg_const_i32(ih); 5603 5604 CHK_SV; 5605 5606 gen_helper_slbia(cpu_env, t0); 5607 tcg_temp_free_i32(t0); 5608 #endif /* defined(CONFIG_USER_ONLY) */ 5609 } 5610 5611 /* slbie */ 5612 static void gen_slbie(DisasContext *ctx) 5613 { 5614 #if defined(CONFIG_USER_ONLY) 5615 GEN_PRIV; 5616 #else 5617 CHK_SV; 5618 5619 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5620 #endif /* defined(CONFIG_USER_ONLY) */ 5621 } 5622 5623 /* slbieg */ 5624 static void gen_slbieg(DisasContext *ctx) 5625 { 5626 #if defined(CONFIG_USER_ONLY) 5627 GEN_PRIV; 5628 #else 5629 CHK_SV; 5630 5631 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5632 #endif /* defined(CONFIG_USER_ONLY) */ 5633 } 5634 5635 /* slbsync */ 5636 static void gen_slbsync(DisasContext *ctx) 5637 { 5638 #if defined(CONFIG_USER_ONLY) 5639 GEN_PRIV; 5640 #else 5641 CHK_SV; 5642 gen_check_tlb_flush(ctx, true); 5643 #endif /* defined(CONFIG_USER_ONLY) */ 5644 } 5645 5646 #endif /* defined(TARGET_PPC64) */ 5647 5648 /*** External control ***/ 5649 /* Optional: */ 5650 5651 /* eciwx */ 5652 static void gen_eciwx(DisasContext *ctx) 5653 { 5654 TCGv t0; 5655 /* Should check EAR[E] ! */ 5656 gen_set_access_type(ctx, ACCESS_EXT); 5657 t0 = tcg_temp_new(); 5658 gen_addr_reg_index(ctx, t0); 5659 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5660 DEF_MEMOP(MO_UL | MO_ALIGN)); 5661 tcg_temp_free(t0); 5662 } 5663 5664 /* ecowx */ 5665 static void gen_ecowx(DisasContext *ctx) 5666 { 5667 TCGv t0; 5668 /* Should check EAR[E] ! */ 5669 gen_set_access_type(ctx, ACCESS_EXT); 5670 t0 = tcg_temp_new(); 5671 gen_addr_reg_index(ctx, t0); 5672 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5673 DEF_MEMOP(MO_UL | MO_ALIGN)); 5674 tcg_temp_free(t0); 5675 } 5676 5677 /* PowerPC 601 specific instructions */ 5678 5679 /* abs - abs. */ 5680 static void gen_abs(DisasContext *ctx) 5681 { 5682 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5683 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5684 5685 tcg_gen_abs_tl(d, a); 5686 if (unlikely(Rc(ctx->opcode) != 0)) { 5687 gen_set_Rc0(ctx, d); 5688 } 5689 } 5690 5691 /* abso - abso. */ 5692 static void gen_abso(DisasContext *ctx) 5693 { 5694 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5695 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5696 5697 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5698 tcg_gen_abs_tl(d, a); 5699 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5700 if (unlikely(Rc(ctx->opcode) != 0)) { 5701 gen_set_Rc0(ctx, d); 5702 } 5703 } 5704 5705 /* clcs */ 5706 static void gen_clcs(DisasContext *ctx) 5707 { 5708 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5709 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5710 tcg_temp_free_i32(t0); 5711 /* Rc=1 sets CR0 to an undefined state */ 5712 } 5713 5714 /* div - div. */ 5715 static void gen_div(DisasContext *ctx) 5716 { 5717 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5718 cpu_gpr[rB(ctx->opcode)]); 5719 if (unlikely(Rc(ctx->opcode) != 0)) { 5720 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5721 } 5722 } 5723 5724 /* divo - divo. */ 5725 static void gen_divo(DisasContext *ctx) 5726 { 5727 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5728 cpu_gpr[rB(ctx->opcode)]); 5729 if (unlikely(Rc(ctx->opcode) != 0)) { 5730 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5731 } 5732 } 5733 5734 /* divs - divs. */ 5735 static void gen_divs(DisasContext *ctx) 5736 { 5737 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5738 cpu_gpr[rB(ctx->opcode)]); 5739 if (unlikely(Rc(ctx->opcode) != 0)) { 5740 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5741 } 5742 } 5743 5744 /* divso - divso. */ 5745 static void gen_divso(DisasContext *ctx) 5746 { 5747 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5748 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5749 if (unlikely(Rc(ctx->opcode) != 0)) { 5750 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5751 } 5752 } 5753 5754 /* doz - doz. */ 5755 static void gen_doz(DisasContext *ctx) 5756 { 5757 TCGLabel *l1 = gen_new_label(); 5758 TCGLabel *l2 = gen_new_label(); 5759 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5760 cpu_gpr[rA(ctx->opcode)], l1); 5761 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5762 cpu_gpr[rA(ctx->opcode)]); 5763 tcg_gen_br(l2); 5764 gen_set_label(l1); 5765 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5766 gen_set_label(l2); 5767 if (unlikely(Rc(ctx->opcode) != 0)) { 5768 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5769 } 5770 } 5771 5772 /* dozo - dozo. */ 5773 static void gen_dozo(DisasContext *ctx) 5774 { 5775 TCGLabel *l1 = gen_new_label(); 5776 TCGLabel *l2 = gen_new_label(); 5777 TCGv t0 = tcg_temp_new(); 5778 TCGv t1 = tcg_temp_new(); 5779 TCGv t2 = tcg_temp_new(); 5780 /* Start with XER OV disabled, the most likely case */ 5781 tcg_gen_movi_tl(cpu_ov, 0); 5782 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5783 cpu_gpr[rA(ctx->opcode)], l1); 5784 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5785 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5786 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5787 tcg_gen_andc_tl(t1, t1, t2); 5788 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5789 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5790 tcg_gen_movi_tl(cpu_ov, 1); 5791 tcg_gen_movi_tl(cpu_so, 1); 5792 tcg_gen_br(l2); 5793 gen_set_label(l1); 5794 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5795 gen_set_label(l2); 5796 tcg_temp_free(t0); 5797 tcg_temp_free(t1); 5798 tcg_temp_free(t2); 5799 if (unlikely(Rc(ctx->opcode) != 0)) { 5800 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5801 } 5802 } 5803 5804 /* dozi */ 5805 static void gen_dozi(DisasContext *ctx) 5806 { 5807 target_long simm = SIMM(ctx->opcode); 5808 TCGLabel *l1 = gen_new_label(); 5809 TCGLabel *l2 = gen_new_label(); 5810 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5811 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5812 tcg_gen_br(l2); 5813 gen_set_label(l1); 5814 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5815 gen_set_label(l2); 5816 if (unlikely(Rc(ctx->opcode) != 0)) { 5817 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5818 } 5819 } 5820 5821 /* lscbx - lscbx. */ 5822 static void gen_lscbx(DisasContext *ctx) 5823 { 5824 TCGv t0 = tcg_temp_new(); 5825 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5826 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5827 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5828 5829 gen_addr_reg_index(ctx, t0); 5830 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5831 tcg_temp_free_i32(t1); 5832 tcg_temp_free_i32(t2); 5833 tcg_temp_free_i32(t3); 5834 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5835 tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5836 if (unlikely(Rc(ctx->opcode) != 0)) { 5837 gen_set_Rc0(ctx, t0); 5838 } 5839 tcg_temp_free(t0); 5840 } 5841 5842 /* maskg - maskg. */ 5843 static void gen_maskg(DisasContext *ctx) 5844 { 5845 TCGLabel *l1 = gen_new_label(); 5846 TCGv t0 = tcg_temp_new(); 5847 TCGv t1 = tcg_temp_new(); 5848 TCGv t2 = tcg_temp_new(); 5849 TCGv t3 = tcg_temp_new(); 5850 tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5851 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5852 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5853 tcg_gen_addi_tl(t2, t0, 1); 5854 tcg_gen_shr_tl(t2, t3, t2); 5855 tcg_gen_shr_tl(t3, t3, t1); 5856 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5857 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5858 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5859 gen_set_label(l1); 5860 tcg_temp_free(t0); 5861 tcg_temp_free(t1); 5862 tcg_temp_free(t2); 5863 tcg_temp_free(t3); 5864 if (unlikely(Rc(ctx->opcode) != 0)) { 5865 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5866 } 5867 } 5868 5869 /* maskir - maskir. */ 5870 static void gen_maskir(DisasContext *ctx) 5871 { 5872 TCGv t0 = tcg_temp_new(); 5873 TCGv t1 = tcg_temp_new(); 5874 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5875 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5876 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5877 tcg_temp_free(t0); 5878 tcg_temp_free(t1); 5879 if (unlikely(Rc(ctx->opcode) != 0)) { 5880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5881 } 5882 } 5883 5884 /* mul - mul. */ 5885 static void gen_mul(DisasContext *ctx) 5886 { 5887 TCGv_i64 t0 = tcg_temp_new_i64(); 5888 TCGv_i64 t1 = tcg_temp_new_i64(); 5889 TCGv t2 = tcg_temp_new(); 5890 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5891 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5892 tcg_gen_mul_i64(t0, t0, t1); 5893 tcg_gen_trunc_i64_tl(t2, t0); 5894 gen_store_spr(SPR_MQ, t2); 5895 tcg_gen_shri_i64(t1, t0, 32); 5896 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5897 tcg_temp_free_i64(t0); 5898 tcg_temp_free_i64(t1); 5899 tcg_temp_free(t2); 5900 if (unlikely(Rc(ctx->opcode) != 0)) { 5901 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5902 } 5903 } 5904 5905 /* mulo - mulo. */ 5906 static void gen_mulo(DisasContext *ctx) 5907 { 5908 TCGLabel *l1 = gen_new_label(); 5909 TCGv_i64 t0 = tcg_temp_new_i64(); 5910 TCGv_i64 t1 = tcg_temp_new_i64(); 5911 TCGv t2 = tcg_temp_new(); 5912 /* Start with XER OV disabled, the most likely case */ 5913 tcg_gen_movi_tl(cpu_ov, 0); 5914 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5915 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5916 tcg_gen_mul_i64(t0, t0, t1); 5917 tcg_gen_trunc_i64_tl(t2, t0); 5918 gen_store_spr(SPR_MQ, t2); 5919 tcg_gen_shri_i64(t1, t0, 32); 5920 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5921 tcg_gen_ext32s_i64(t1, t0); 5922 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5923 tcg_gen_movi_tl(cpu_ov, 1); 5924 tcg_gen_movi_tl(cpu_so, 1); 5925 gen_set_label(l1); 5926 tcg_temp_free_i64(t0); 5927 tcg_temp_free_i64(t1); 5928 tcg_temp_free(t2); 5929 if (unlikely(Rc(ctx->opcode) != 0)) { 5930 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5931 } 5932 } 5933 5934 /* nabs - nabs. */ 5935 static void gen_nabs(DisasContext *ctx) 5936 { 5937 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5938 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5939 5940 tcg_gen_abs_tl(d, a); 5941 tcg_gen_neg_tl(d, d); 5942 if (unlikely(Rc(ctx->opcode) != 0)) { 5943 gen_set_Rc0(ctx, d); 5944 } 5945 } 5946 5947 /* nabso - nabso. */ 5948 static void gen_nabso(DisasContext *ctx) 5949 { 5950 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5951 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5952 5953 tcg_gen_abs_tl(d, a); 5954 tcg_gen_neg_tl(d, d); 5955 /* nabs never overflows */ 5956 tcg_gen_movi_tl(cpu_ov, 0); 5957 if (unlikely(Rc(ctx->opcode) != 0)) { 5958 gen_set_Rc0(ctx, d); 5959 } 5960 } 5961 5962 /* rlmi - rlmi. */ 5963 static void gen_rlmi(DisasContext *ctx) 5964 { 5965 uint32_t mb = MB(ctx->opcode); 5966 uint32_t me = ME(ctx->opcode); 5967 TCGv t0 = tcg_temp_new(); 5968 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5969 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5970 tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5971 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5972 ~MASK(mb, me)); 5973 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5974 tcg_temp_free(t0); 5975 if (unlikely(Rc(ctx->opcode) != 0)) { 5976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5977 } 5978 } 5979 5980 /* rrib - rrib. */ 5981 static void gen_rrib(DisasContext *ctx) 5982 { 5983 TCGv t0 = tcg_temp_new(); 5984 TCGv t1 = tcg_temp_new(); 5985 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5986 tcg_gen_movi_tl(t1, 0x80000000); 5987 tcg_gen_shr_tl(t1, t1, t0); 5988 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5989 tcg_gen_and_tl(t0, t0, t1); 5990 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5991 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5992 tcg_temp_free(t0); 5993 tcg_temp_free(t1); 5994 if (unlikely(Rc(ctx->opcode) != 0)) { 5995 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5996 } 5997 } 5998 5999 /* sle - sle. */ 6000 static void gen_sle(DisasContext *ctx) 6001 { 6002 TCGv t0 = tcg_temp_new(); 6003 TCGv t1 = tcg_temp_new(); 6004 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6005 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6006 tcg_gen_subfi_tl(t1, 32, t1); 6007 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6008 tcg_gen_or_tl(t1, t0, t1); 6009 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6010 gen_store_spr(SPR_MQ, t1); 6011 tcg_temp_free(t0); 6012 tcg_temp_free(t1); 6013 if (unlikely(Rc(ctx->opcode) != 0)) { 6014 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6015 } 6016 } 6017 6018 /* sleq - sleq. */ 6019 static void gen_sleq(DisasContext *ctx) 6020 { 6021 TCGv t0 = tcg_temp_new(); 6022 TCGv t1 = tcg_temp_new(); 6023 TCGv t2 = tcg_temp_new(); 6024 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6025 tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6026 tcg_gen_shl_tl(t2, t2, t0); 6027 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6028 gen_load_spr(t1, SPR_MQ); 6029 gen_store_spr(SPR_MQ, t0); 6030 tcg_gen_and_tl(t0, t0, t2); 6031 tcg_gen_andc_tl(t1, t1, t2); 6032 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6033 tcg_temp_free(t0); 6034 tcg_temp_free(t1); 6035 tcg_temp_free(t2); 6036 if (unlikely(Rc(ctx->opcode) != 0)) { 6037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6038 } 6039 } 6040 6041 /* sliq - sliq. */ 6042 static void gen_sliq(DisasContext *ctx) 6043 { 6044 int sh = SH(ctx->opcode); 6045 TCGv t0 = tcg_temp_new(); 6046 TCGv t1 = tcg_temp_new(); 6047 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6048 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6049 tcg_gen_or_tl(t1, t0, t1); 6050 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6051 gen_store_spr(SPR_MQ, t1); 6052 tcg_temp_free(t0); 6053 tcg_temp_free(t1); 6054 if (unlikely(Rc(ctx->opcode) != 0)) { 6055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6056 } 6057 } 6058 6059 /* slliq - slliq. */ 6060 static void gen_slliq(DisasContext *ctx) 6061 { 6062 int sh = SH(ctx->opcode); 6063 TCGv t0 = tcg_temp_new(); 6064 TCGv t1 = tcg_temp_new(); 6065 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6066 gen_load_spr(t1, SPR_MQ); 6067 gen_store_spr(SPR_MQ, t0); 6068 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6069 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6070 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6071 tcg_temp_free(t0); 6072 tcg_temp_free(t1); 6073 if (unlikely(Rc(ctx->opcode) != 0)) { 6074 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6075 } 6076 } 6077 6078 /* sllq - sllq. */ 6079 static void gen_sllq(DisasContext *ctx) 6080 { 6081 TCGLabel *l1 = gen_new_label(); 6082 TCGLabel *l2 = gen_new_label(); 6083 TCGv t0 = tcg_temp_local_new(); 6084 TCGv t1 = tcg_temp_local_new(); 6085 TCGv t2 = tcg_temp_local_new(); 6086 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6087 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6088 tcg_gen_shl_tl(t1, t1, t2); 6089 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6090 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6091 gen_load_spr(t0, SPR_MQ); 6092 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6093 tcg_gen_br(l2); 6094 gen_set_label(l1); 6095 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6096 gen_load_spr(t2, SPR_MQ); 6097 tcg_gen_andc_tl(t1, t2, t1); 6098 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6099 gen_set_label(l2); 6100 tcg_temp_free(t0); 6101 tcg_temp_free(t1); 6102 tcg_temp_free(t2); 6103 if (unlikely(Rc(ctx->opcode) != 0)) { 6104 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6105 } 6106 } 6107 6108 /* slq - slq. */ 6109 static void gen_slq(DisasContext *ctx) 6110 { 6111 TCGLabel *l1 = gen_new_label(); 6112 TCGv t0 = tcg_temp_new(); 6113 TCGv t1 = tcg_temp_new(); 6114 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6115 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6116 tcg_gen_subfi_tl(t1, 32, t1); 6117 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6118 tcg_gen_or_tl(t1, t0, t1); 6119 gen_store_spr(SPR_MQ, t1); 6120 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6121 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6122 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6123 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6124 gen_set_label(l1); 6125 tcg_temp_free(t0); 6126 tcg_temp_free(t1); 6127 if (unlikely(Rc(ctx->opcode) != 0)) { 6128 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6129 } 6130 } 6131 6132 /* sraiq - sraiq. */ 6133 static void gen_sraiq(DisasContext *ctx) 6134 { 6135 int sh = SH(ctx->opcode); 6136 TCGLabel *l1 = gen_new_label(); 6137 TCGv t0 = tcg_temp_new(); 6138 TCGv t1 = tcg_temp_new(); 6139 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6140 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6141 tcg_gen_or_tl(t0, t0, t1); 6142 gen_store_spr(SPR_MQ, t0); 6143 tcg_gen_movi_tl(cpu_ca, 0); 6144 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6145 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6146 tcg_gen_movi_tl(cpu_ca, 1); 6147 gen_set_label(l1); 6148 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6149 tcg_temp_free(t0); 6150 tcg_temp_free(t1); 6151 if (unlikely(Rc(ctx->opcode) != 0)) { 6152 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6153 } 6154 } 6155 6156 /* sraq - sraq. */ 6157 static void gen_sraq(DisasContext *ctx) 6158 { 6159 TCGLabel *l1 = gen_new_label(); 6160 TCGLabel *l2 = gen_new_label(); 6161 TCGv t0 = tcg_temp_new(); 6162 TCGv t1 = tcg_temp_local_new(); 6163 TCGv t2 = tcg_temp_local_new(); 6164 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6165 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6166 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6167 tcg_gen_subfi_tl(t2, 32, t2); 6168 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6169 tcg_gen_or_tl(t0, t0, t2); 6170 gen_store_spr(SPR_MQ, t0); 6171 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6172 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6173 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6174 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6175 gen_set_label(l1); 6176 tcg_temp_free(t0); 6177 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6178 tcg_gen_movi_tl(cpu_ca, 0); 6179 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6180 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6181 tcg_gen_movi_tl(cpu_ca, 1); 6182 gen_set_label(l2); 6183 tcg_temp_free(t1); 6184 tcg_temp_free(t2); 6185 if (unlikely(Rc(ctx->opcode) != 0)) { 6186 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6187 } 6188 } 6189 6190 /* sre - sre. */ 6191 static void gen_sre(DisasContext *ctx) 6192 { 6193 TCGv t0 = tcg_temp_new(); 6194 TCGv t1 = tcg_temp_new(); 6195 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6196 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6197 tcg_gen_subfi_tl(t1, 32, t1); 6198 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6199 tcg_gen_or_tl(t1, t0, t1); 6200 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6201 gen_store_spr(SPR_MQ, t1); 6202 tcg_temp_free(t0); 6203 tcg_temp_free(t1); 6204 if (unlikely(Rc(ctx->opcode) != 0)) { 6205 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6206 } 6207 } 6208 6209 /* srea - srea. */ 6210 static void gen_srea(DisasContext *ctx) 6211 { 6212 TCGv t0 = tcg_temp_new(); 6213 TCGv t1 = tcg_temp_new(); 6214 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6215 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6216 gen_store_spr(SPR_MQ, t0); 6217 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6218 tcg_temp_free(t0); 6219 tcg_temp_free(t1); 6220 if (unlikely(Rc(ctx->opcode) != 0)) { 6221 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6222 } 6223 } 6224 6225 /* sreq */ 6226 static void gen_sreq(DisasContext *ctx) 6227 { 6228 TCGv t0 = tcg_temp_new(); 6229 TCGv t1 = tcg_temp_new(); 6230 TCGv t2 = tcg_temp_new(); 6231 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6232 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6233 tcg_gen_shr_tl(t1, t1, t0); 6234 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6235 gen_load_spr(t2, SPR_MQ); 6236 gen_store_spr(SPR_MQ, t0); 6237 tcg_gen_and_tl(t0, t0, t1); 6238 tcg_gen_andc_tl(t2, t2, t1); 6239 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6240 tcg_temp_free(t0); 6241 tcg_temp_free(t1); 6242 tcg_temp_free(t2); 6243 if (unlikely(Rc(ctx->opcode) != 0)) { 6244 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6245 } 6246 } 6247 6248 /* sriq */ 6249 static void gen_sriq(DisasContext *ctx) 6250 { 6251 int sh = SH(ctx->opcode); 6252 TCGv t0 = tcg_temp_new(); 6253 TCGv t1 = tcg_temp_new(); 6254 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6255 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6256 tcg_gen_or_tl(t1, t0, t1); 6257 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6258 gen_store_spr(SPR_MQ, t1); 6259 tcg_temp_free(t0); 6260 tcg_temp_free(t1); 6261 if (unlikely(Rc(ctx->opcode) != 0)) { 6262 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6263 } 6264 } 6265 6266 /* srliq */ 6267 static void gen_srliq(DisasContext *ctx) 6268 { 6269 int sh = SH(ctx->opcode); 6270 TCGv t0 = tcg_temp_new(); 6271 TCGv t1 = tcg_temp_new(); 6272 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6273 gen_load_spr(t1, SPR_MQ); 6274 gen_store_spr(SPR_MQ, t0); 6275 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6276 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6277 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6278 tcg_temp_free(t0); 6279 tcg_temp_free(t1); 6280 if (unlikely(Rc(ctx->opcode) != 0)) { 6281 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6282 } 6283 } 6284 6285 /* srlq */ 6286 static void gen_srlq(DisasContext *ctx) 6287 { 6288 TCGLabel *l1 = gen_new_label(); 6289 TCGLabel *l2 = gen_new_label(); 6290 TCGv t0 = tcg_temp_local_new(); 6291 TCGv t1 = tcg_temp_local_new(); 6292 TCGv t2 = tcg_temp_local_new(); 6293 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6294 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6295 tcg_gen_shr_tl(t2, t1, t2); 6296 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6297 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6298 gen_load_spr(t0, SPR_MQ); 6299 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6300 tcg_gen_br(l2); 6301 gen_set_label(l1); 6302 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6303 tcg_gen_and_tl(t0, t0, t2); 6304 gen_load_spr(t1, SPR_MQ); 6305 tcg_gen_andc_tl(t1, t1, t2); 6306 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6307 gen_set_label(l2); 6308 tcg_temp_free(t0); 6309 tcg_temp_free(t1); 6310 tcg_temp_free(t2); 6311 if (unlikely(Rc(ctx->opcode) != 0)) { 6312 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6313 } 6314 } 6315 6316 /* srq */ 6317 static void gen_srq(DisasContext *ctx) 6318 { 6319 TCGLabel *l1 = gen_new_label(); 6320 TCGv t0 = tcg_temp_new(); 6321 TCGv t1 = tcg_temp_new(); 6322 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6323 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6324 tcg_gen_subfi_tl(t1, 32, t1); 6325 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6326 tcg_gen_or_tl(t1, t0, t1); 6327 gen_store_spr(SPR_MQ, t1); 6328 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6329 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6330 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6331 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6332 gen_set_label(l1); 6333 tcg_temp_free(t0); 6334 tcg_temp_free(t1); 6335 if (unlikely(Rc(ctx->opcode) != 0)) { 6336 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6337 } 6338 } 6339 6340 /* PowerPC 602 specific instructions */ 6341 6342 /* dsa */ 6343 static void gen_dsa(DisasContext *ctx) 6344 { 6345 /* XXX: TODO */ 6346 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6347 } 6348 6349 /* esa */ 6350 static void gen_esa(DisasContext *ctx) 6351 { 6352 /* XXX: TODO */ 6353 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6354 } 6355 6356 /* mfrom */ 6357 static void gen_mfrom(DisasContext *ctx) 6358 { 6359 #if defined(CONFIG_USER_ONLY) 6360 GEN_PRIV; 6361 #else 6362 CHK_SV; 6363 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6364 #endif /* defined(CONFIG_USER_ONLY) */ 6365 } 6366 6367 /* 602 - 603 - G2 TLB management */ 6368 6369 /* tlbld */ 6370 static void gen_tlbld_6xx(DisasContext *ctx) 6371 { 6372 #if defined(CONFIG_USER_ONLY) 6373 GEN_PRIV; 6374 #else 6375 CHK_SV; 6376 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6377 #endif /* defined(CONFIG_USER_ONLY) */ 6378 } 6379 6380 /* tlbli */ 6381 static void gen_tlbli_6xx(DisasContext *ctx) 6382 { 6383 #if defined(CONFIG_USER_ONLY) 6384 GEN_PRIV; 6385 #else 6386 CHK_SV; 6387 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6388 #endif /* defined(CONFIG_USER_ONLY) */ 6389 } 6390 6391 /* 74xx TLB management */ 6392 6393 /* tlbld */ 6394 static void gen_tlbld_74xx(DisasContext *ctx) 6395 { 6396 #if defined(CONFIG_USER_ONLY) 6397 GEN_PRIV; 6398 #else 6399 CHK_SV; 6400 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6401 #endif /* defined(CONFIG_USER_ONLY) */ 6402 } 6403 6404 /* tlbli */ 6405 static void gen_tlbli_74xx(DisasContext *ctx) 6406 { 6407 #if defined(CONFIG_USER_ONLY) 6408 GEN_PRIV; 6409 #else 6410 CHK_SV; 6411 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6412 #endif /* defined(CONFIG_USER_ONLY) */ 6413 } 6414 6415 /* POWER instructions not in PowerPC 601 */ 6416 6417 /* clf */ 6418 static void gen_clf(DisasContext *ctx) 6419 { 6420 /* Cache line flush: implemented as no-op */ 6421 } 6422 6423 /* cli */ 6424 static void gen_cli(DisasContext *ctx) 6425 { 6426 #if defined(CONFIG_USER_ONLY) 6427 GEN_PRIV; 6428 #else 6429 /* Cache line invalidate: privileged and treated as no-op */ 6430 CHK_SV; 6431 #endif /* defined(CONFIG_USER_ONLY) */ 6432 } 6433 6434 /* dclst */ 6435 static void gen_dclst(DisasContext *ctx) 6436 { 6437 /* Data cache line store: treated as no-op */ 6438 } 6439 6440 static void gen_mfsri(DisasContext *ctx) 6441 { 6442 #if defined(CONFIG_USER_ONLY) 6443 GEN_PRIV; 6444 #else 6445 int ra = rA(ctx->opcode); 6446 int rd = rD(ctx->opcode); 6447 TCGv t0; 6448 6449 CHK_SV; 6450 t0 = tcg_temp_new(); 6451 gen_addr_reg_index(ctx, t0); 6452 tcg_gen_extract_tl(t0, t0, 28, 4); 6453 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6454 tcg_temp_free(t0); 6455 if (ra != 0 && ra != rd) { 6456 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6457 } 6458 #endif /* defined(CONFIG_USER_ONLY) */ 6459 } 6460 6461 static void gen_rac(DisasContext *ctx) 6462 { 6463 #if defined(CONFIG_USER_ONLY) 6464 GEN_PRIV; 6465 #else 6466 TCGv t0; 6467 6468 CHK_SV; 6469 t0 = tcg_temp_new(); 6470 gen_addr_reg_index(ctx, t0); 6471 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6472 tcg_temp_free(t0); 6473 #endif /* defined(CONFIG_USER_ONLY) */ 6474 } 6475 6476 static void gen_rfsvc(DisasContext *ctx) 6477 { 6478 #if defined(CONFIG_USER_ONLY) 6479 GEN_PRIV; 6480 #else 6481 CHK_SV; 6482 6483 gen_helper_rfsvc(cpu_env); 6484 ctx->base.is_jmp = DISAS_EXIT; 6485 #endif /* defined(CONFIG_USER_ONLY) */ 6486 } 6487 6488 /* svc is not implemented for now */ 6489 6490 /* BookE specific instructions */ 6491 6492 /* XXX: not implemented on 440 ? */ 6493 static void gen_mfapidi(DisasContext *ctx) 6494 { 6495 /* XXX: TODO */ 6496 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6497 } 6498 6499 /* XXX: not implemented on 440 ? */ 6500 static void gen_tlbiva(DisasContext *ctx) 6501 { 6502 #if defined(CONFIG_USER_ONLY) 6503 GEN_PRIV; 6504 #else 6505 TCGv t0; 6506 6507 CHK_SV; 6508 t0 = tcg_temp_new(); 6509 gen_addr_reg_index(ctx, t0); 6510 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6511 tcg_temp_free(t0); 6512 #endif /* defined(CONFIG_USER_ONLY) */ 6513 } 6514 6515 /* All 405 MAC instructions are translated here */ 6516 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6517 int ra, int rb, int rt, int Rc) 6518 { 6519 TCGv t0, t1; 6520 6521 t0 = tcg_temp_local_new(); 6522 t1 = tcg_temp_local_new(); 6523 6524 switch (opc3 & 0x0D) { 6525 case 0x05: 6526 /* macchw - macchw. - macchwo - macchwo. */ 6527 /* macchws - macchws. - macchwso - macchwso. */ 6528 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6529 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6530 /* mulchw - mulchw. */ 6531 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6532 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6533 tcg_gen_ext16s_tl(t1, t1); 6534 break; 6535 case 0x04: 6536 /* macchwu - macchwu. - macchwuo - macchwuo. */ 6537 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6538 /* mulchwu - mulchwu. */ 6539 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6540 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6541 tcg_gen_ext16u_tl(t1, t1); 6542 break; 6543 case 0x01: 6544 /* machhw - machhw. - machhwo - machhwo. */ 6545 /* machhws - machhws. - machhwso - machhwso. */ 6546 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6547 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6548 /* mulhhw - mulhhw. */ 6549 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6550 tcg_gen_ext16s_tl(t0, t0); 6551 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6552 tcg_gen_ext16s_tl(t1, t1); 6553 break; 6554 case 0x00: 6555 /* machhwu - machhwu. - machhwuo - machhwuo. */ 6556 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6557 /* mulhhwu - mulhhwu. */ 6558 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6559 tcg_gen_ext16u_tl(t0, t0); 6560 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6561 tcg_gen_ext16u_tl(t1, t1); 6562 break; 6563 case 0x0D: 6564 /* maclhw - maclhw. - maclhwo - maclhwo. */ 6565 /* maclhws - maclhws. - maclhwso - maclhwso. */ 6566 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6567 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6568 /* mullhw - mullhw. */ 6569 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6570 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6571 break; 6572 case 0x0C: 6573 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6574 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6575 /* mullhwu - mullhwu. */ 6576 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6577 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6578 break; 6579 } 6580 if (opc2 & 0x04) { 6581 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6582 tcg_gen_mul_tl(t1, t0, t1); 6583 if (opc2 & 0x02) { 6584 /* nmultiply-and-accumulate (0x0E) */ 6585 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6586 } else { 6587 /* multiply-and-accumulate (0x0C) */ 6588 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6589 } 6590 6591 if (opc3 & 0x12) { 6592 /* Check overflow and/or saturate */ 6593 TCGLabel *l1 = gen_new_label(); 6594 6595 if (opc3 & 0x10) { 6596 /* Start with XER OV disabled, the most likely case */ 6597 tcg_gen_movi_tl(cpu_ov, 0); 6598 } 6599 if (opc3 & 0x01) { 6600 /* Signed */ 6601 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6602 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6603 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6604 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6605 if (opc3 & 0x02) { 6606 /* Saturate */ 6607 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6608 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6609 } 6610 } else { 6611 /* Unsigned */ 6612 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6613 if (opc3 & 0x02) { 6614 /* Saturate */ 6615 tcg_gen_movi_tl(t0, UINT32_MAX); 6616 } 6617 } 6618 if (opc3 & 0x10) { 6619 /* Check overflow */ 6620 tcg_gen_movi_tl(cpu_ov, 1); 6621 tcg_gen_movi_tl(cpu_so, 1); 6622 } 6623 gen_set_label(l1); 6624 tcg_gen_mov_tl(cpu_gpr[rt], t0); 6625 } 6626 } else { 6627 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6628 } 6629 tcg_temp_free(t0); 6630 tcg_temp_free(t1); 6631 if (unlikely(Rc) != 0) { 6632 /* Update Rc0 */ 6633 gen_set_Rc0(ctx, cpu_gpr[rt]); 6634 } 6635 } 6636 6637 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6638 static void glue(gen_, name)(DisasContext *ctx) \ 6639 { \ 6640 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6641 rD(ctx->opcode), Rc(ctx->opcode)); \ 6642 } 6643 6644 /* macchw - macchw. */ 6645 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6646 /* macchwo - macchwo. */ 6647 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6648 /* macchws - macchws. */ 6649 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6650 /* macchwso - macchwso. */ 6651 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6652 /* macchwsu - macchwsu. */ 6653 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6654 /* macchwsuo - macchwsuo. */ 6655 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6656 /* macchwu - macchwu. */ 6657 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6658 /* macchwuo - macchwuo. */ 6659 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6660 /* machhw - machhw. */ 6661 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6662 /* machhwo - machhwo. */ 6663 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6664 /* machhws - machhws. */ 6665 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6666 /* machhwso - machhwso. */ 6667 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6668 /* machhwsu - machhwsu. */ 6669 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6670 /* machhwsuo - machhwsuo. */ 6671 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6672 /* machhwu - machhwu. */ 6673 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6674 /* machhwuo - machhwuo. */ 6675 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6676 /* maclhw - maclhw. */ 6677 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6678 /* maclhwo - maclhwo. */ 6679 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6680 /* maclhws - maclhws. */ 6681 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6682 /* maclhwso - maclhwso. */ 6683 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6684 /* maclhwu - maclhwu. */ 6685 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6686 /* maclhwuo - maclhwuo. */ 6687 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6688 /* maclhwsu - maclhwsu. */ 6689 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6690 /* maclhwsuo - maclhwsuo. */ 6691 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6692 /* nmacchw - nmacchw. */ 6693 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6694 /* nmacchwo - nmacchwo. */ 6695 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6696 /* nmacchws - nmacchws. */ 6697 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6698 /* nmacchwso - nmacchwso. */ 6699 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6700 /* nmachhw - nmachhw. */ 6701 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6702 /* nmachhwo - nmachhwo. */ 6703 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6704 /* nmachhws - nmachhws. */ 6705 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6706 /* nmachhwso - nmachhwso. */ 6707 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6708 /* nmaclhw - nmaclhw. */ 6709 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6710 /* nmaclhwo - nmaclhwo. */ 6711 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6712 /* nmaclhws - nmaclhws. */ 6713 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6714 /* nmaclhwso - nmaclhwso. */ 6715 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6716 6717 /* mulchw - mulchw. */ 6718 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6719 /* mulchwu - mulchwu. */ 6720 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6721 /* mulhhw - mulhhw. */ 6722 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6723 /* mulhhwu - mulhhwu. */ 6724 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6725 /* mullhw - mullhw. */ 6726 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6727 /* mullhwu - mullhwu. */ 6728 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6729 6730 /* mfdcr */ 6731 static void gen_mfdcr(DisasContext *ctx) 6732 { 6733 #if defined(CONFIG_USER_ONLY) 6734 GEN_PRIV; 6735 #else 6736 TCGv dcrn; 6737 6738 CHK_SV; 6739 dcrn = tcg_const_tl(SPR(ctx->opcode)); 6740 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6741 tcg_temp_free(dcrn); 6742 #endif /* defined(CONFIG_USER_ONLY) */ 6743 } 6744 6745 /* mtdcr */ 6746 static void gen_mtdcr(DisasContext *ctx) 6747 { 6748 #if defined(CONFIG_USER_ONLY) 6749 GEN_PRIV; 6750 #else 6751 TCGv dcrn; 6752 6753 CHK_SV; 6754 dcrn = tcg_const_tl(SPR(ctx->opcode)); 6755 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6756 tcg_temp_free(dcrn); 6757 #endif /* defined(CONFIG_USER_ONLY) */ 6758 } 6759 6760 /* mfdcrx */ 6761 /* XXX: not implemented on 440 ? */ 6762 static void gen_mfdcrx(DisasContext *ctx) 6763 { 6764 #if defined(CONFIG_USER_ONLY) 6765 GEN_PRIV; 6766 #else 6767 CHK_SV; 6768 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6769 cpu_gpr[rA(ctx->opcode)]); 6770 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6771 #endif /* defined(CONFIG_USER_ONLY) */ 6772 } 6773 6774 /* mtdcrx */ 6775 /* XXX: not implemented on 440 ? */ 6776 static void gen_mtdcrx(DisasContext *ctx) 6777 { 6778 #if defined(CONFIG_USER_ONLY) 6779 GEN_PRIV; 6780 #else 6781 CHK_SV; 6782 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6783 cpu_gpr[rS(ctx->opcode)]); 6784 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6785 #endif /* defined(CONFIG_USER_ONLY) */ 6786 } 6787 6788 /* mfdcrux (PPC 460) : user-mode access to DCR */ 6789 static void gen_mfdcrux(DisasContext *ctx) 6790 { 6791 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6792 cpu_gpr[rA(ctx->opcode)]); 6793 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6794 } 6795 6796 /* mtdcrux (PPC 460) : user-mode access to DCR */ 6797 static void gen_mtdcrux(DisasContext *ctx) 6798 { 6799 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6800 cpu_gpr[rS(ctx->opcode)]); 6801 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6802 } 6803 6804 /* dccci */ 6805 static void gen_dccci(DisasContext *ctx) 6806 { 6807 CHK_SV; 6808 /* interpreted as no-op */ 6809 } 6810 6811 /* dcread */ 6812 static void gen_dcread(DisasContext *ctx) 6813 { 6814 #if defined(CONFIG_USER_ONLY) 6815 GEN_PRIV; 6816 #else 6817 TCGv EA, val; 6818 6819 CHK_SV; 6820 gen_set_access_type(ctx, ACCESS_CACHE); 6821 EA = tcg_temp_new(); 6822 gen_addr_reg_index(ctx, EA); 6823 val = tcg_temp_new(); 6824 gen_qemu_ld32u(ctx, val, EA); 6825 tcg_temp_free(val); 6826 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6827 tcg_temp_free(EA); 6828 #endif /* defined(CONFIG_USER_ONLY) */ 6829 } 6830 6831 /* icbt */ 6832 static void gen_icbt_40x(DisasContext *ctx) 6833 { 6834 /* 6835 * interpreted as no-op 6836 * XXX: specification say this is treated as a load by the MMU but 6837 * does not generate any exception 6838 */ 6839 } 6840 6841 /* iccci */ 6842 static void gen_iccci(DisasContext *ctx) 6843 { 6844 CHK_SV; 6845 /* interpreted as no-op */ 6846 } 6847 6848 /* icread */ 6849 static void gen_icread(DisasContext *ctx) 6850 { 6851 CHK_SV; 6852 /* interpreted as no-op */ 6853 } 6854 6855 /* rfci (supervisor only) */ 6856 static void gen_rfci_40x(DisasContext *ctx) 6857 { 6858 #if defined(CONFIG_USER_ONLY) 6859 GEN_PRIV; 6860 #else 6861 CHK_SV; 6862 /* Restore CPU state */ 6863 gen_helper_40x_rfci(cpu_env); 6864 ctx->base.is_jmp = DISAS_EXIT; 6865 #endif /* defined(CONFIG_USER_ONLY) */ 6866 } 6867 6868 static void gen_rfci(DisasContext *ctx) 6869 { 6870 #if defined(CONFIG_USER_ONLY) 6871 GEN_PRIV; 6872 #else 6873 CHK_SV; 6874 /* Restore CPU state */ 6875 gen_helper_rfci(cpu_env); 6876 ctx->base.is_jmp = DISAS_EXIT; 6877 #endif /* defined(CONFIG_USER_ONLY) */ 6878 } 6879 6880 /* BookE specific */ 6881 6882 /* XXX: not implemented on 440 ? */ 6883 static void gen_rfdi(DisasContext *ctx) 6884 { 6885 #if defined(CONFIG_USER_ONLY) 6886 GEN_PRIV; 6887 #else 6888 CHK_SV; 6889 /* Restore CPU state */ 6890 gen_helper_rfdi(cpu_env); 6891 ctx->base.is_jmp = DISAS_EXIT; 6892 #endif /* defined(CONFIG_USER_ONLY) */ 6893 } 6894 6895 /* XXX: not implemented on 440 ? */ 6896 static void gen_rfmci(DisasContext *ctx) 6897 { 6898 #if defined(CONFIG_USER_ONLY) 6899 GEN_PRIV; 6900 #else 6901 CHK_SV; 6902 /* Restore CPU state */ 6903 gen_helper_rfmci(cpu_env); 6904 ctx->base.is_jmp = DISAS_EXIT; 6905 #endif /* defined(CONFIG_USER_ONLY) */ 6906 } 6907 6908 /* TLB management - PowerPC 405 implementation */ 6909 6910 /* tlbre */ 6911 static void gen_tlbre_40x(DisasContext *ctx) 6912 { 6913 #if defined(CONFIG_USER_ONLY) 6914 GEN_PRIV; 6915 #else 6916 CHK_SV; 6917 switch (rB(ctx->opcode)) { 6918 case 0: 6919 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6920 cpu_gpr[rA(ctx->opcode)]); 6921 break; 6922 case 1: 6923 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6924 cpu_gpr[rA(ctx->opcode)]); 6925 break; 6926 default: 6927 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6928 break; 6929 } 6930 #endif /* defined(CONFIG_USER_ONLY) */ 6931 } 6932 6933 /* tlbsx - tlbsx. */ 6934 static void gen_tlbsx_40x(DisasContext *ctx) 6935 { 6936 #if defined(CONFIG_USER_ONLY) 6937 GEN_PRIV; 6938 #else 6939 TCGv t0; 6940 6941 CHK_SV; 6942 t0 = tcg_temp_new(); 6943 gen_addr_reg_index(ctx, t0); 6944 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6945 tcg_temp_free(t0); 6946 if (Rc(ctx->opcode)) { 6947 TCGLabel *l1 = gen_new_label(); 6948 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6949 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6950 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6951 gen_set_label(l1); 6952 } 6953 #endif /* defined(CONFIG_USER_ONLY) */ 6954 } 6955 6956 /* tlbwe */ 6957 static void gen_tlbwe_40x(DisasContext *ctx) 6958 { 6959 #if defined(CONFIG_USER_ONLY) 6960 GEN_PRIV; 6961 #else 6962 CHK_SV; 6963 6964 switch (rB(ctx->opcode)) { 6965 case 0: 6966 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6967 cpu_gpr[rS(ctx->opcode)]); 6968 break; 6969 case 1: 6970 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6971 cpu_gpr[rS(ctx->opcode)]); 6972 break; 6973 default: 6974 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6975 break; 6976 } 6977 #endif /* defined(CONFIG_USER_ONLY) */ 6978 } 6979 6980 /* TLB management - PowerPC 440 implementation */ 6981 6982 /* tlbre */ 6983 static void gen_tlbre_440(DisasContext *ctx) 6984 { 6985 #if defined(CONFIG_USER_ONLY) 6986 GEN_PRIV; 6987 #else 6988 CHK_SV; 6989 6990 switch (rB(ctx->opcode)) { 6991 case 0: 6992 case 1: 6993 case 2: 6994 { 6995 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6996 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6997 t0, cpu_gpr[rA(ctx->opcode)]); 6998 tcg_temp_free_i32(t0); 6999 } 7000 break; 7001 default: 7002 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7003 break; 7004 } 7005 #endif /* defined(CONFIG_USER_ONLY) */ 7006 } 7007 7008 /* tlbsx - tlbsx. */ 7009 static void gen_tlbsx_440(DisasContext *ctx) 7010 { 7011 #if defined(CONFIG_USER_ONLY) 7012 GEN_PRIV; 7013 #else 7014 TCGv t0; 7015 7016 CHK_SV; 7017 t0 = tcg_temp_new(); 7018 gen_addr_reg_index(ctx, t0); 7019 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7020 tcg_temp_free(t0); 7021 if (Rc(ctx->opcode)) { 7022 TCGLabel *l1 = gen_new_label(); 7023 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7024 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7025 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7026 gen_set_label(l1); 7027 } 7028 #endif /* defined(CONFIG_USER_ONLY) */ 7029 } 7030 7031 /* tlbwe */ 7032 static void gen_tlbwe_440(DisasContext *ctx) 7033 { 7034 #if defined(CONFIG_USER_ONLY) 7035 GEN_PRIV; 7036 #else 7037 CHK_SV; 7038 switch (rB(ctx->opcode)) { 7039 case 0: 7040 case 1: 7041 case 2: 7042 { 7043 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7044 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7045 cpu_gpr[rS(ctx->opcode)]); 7046 tcg_temp_free_i32(t0); 7047 } 7048 break; 7049 default: 7050 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7051 break; 7052 } 7053 #endif /* defined(CONFIG_USER_ONLY) */ 7054 } 7055 7056 /* TLB management - PowerPC BookE 2.06 implementation */ 7057 7058 /* tlbre */ 7059 static void gen_tlbre_booke206(DisasContext *ctx) 7060 { 7061 #if defined(CONFIG_USER_ONLY) 7062 GEN_PRIV; 7063 #else 7064 CHK_SV; 7065 gen_helper_booke206_tlbre(cpu_env); 7066 #endif /* defined(CONFIG_USER_ONLY) */ 7067 } 7068 7069 /* tlbsx - tlbsx. */ 7070 static void gen_tlbsx_booke206(DisasContext *ctx) 7071 { 7072 #if defined(CONFIG_USER_ONLY) 7073 GEN_PRIV; 7074 #else 7075 TCGv t0; 7076 7077 CHK_SV; 7078 if (rA(ctx->opcode)) { 7079 t0 = tcg_temp_new(); 7080 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7081 } else { 7082 t0 = tcg_const_tl(0); 7083 } 7084 7085 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7086 gen_helper_booke206_tlbsx(cpu_env, t0); 7087 tcg_temp_free(t0); 7088 #endif /* defined(CONFIG_USER_ONLY) */ 7089 } 7090 7091 /* tlbwe */ 7092 static void gen_tlbwe_booke206(DisasContext *ctx) 7093 { 7094 #if defined(CONFIG_USER_ONLY) 7095 GEN_PRIV; 7096 #else 7097 CHK_SV; 7098 gen_helper_booke206_tlbwe(cpu_env); 7099 #endif /* defined(CONFIG_USER_ONLY) */ 7100 } 7101 7102 static void gen_tlbivax_booke206(DisasContext *ctx) 7103 { 7104 #if defined(CONFIG_USER_ONLY) 7105 GEN_PRIV; 7106 #else 7107 TCGv t0; 7108 7109 CHK_SV; 7110 t0 = tcg_temp_new(); 7111 gen_addr_reg_index(ctx, t0); 7112 gen_helper_booke206_tlbivax(cpu_env, t0); 7113 tcg_temp_free(t0); 7114 #endif /* defined(CONFIG_USER_ONLY) */ 7115 } 7116 7117 static void gen_tlbilx_booke206(DisasContext *ctx) 7118 { 7119 #if defined(CONFIG_USER_ONLY) 7120 GEN_PRIV; 7121 #else 7122 TCGv t0; 7123 7124 CHK_SV; 7125 t0 = tcg_temp_new(); 7126 gen_addr_reg_index(ctx, t0); 7127 7128 switch ((ctx->opcode >> 21) & 0x3) { 7129 case 0: 7130 gen_helper_booke206_tlbilx0(cpu_env, t0); 7131 break; 7132 case 1: 7133 gen_helper_booke206_tlbilx1(cpu_env, t0); 7134 break; 7135 case 3: 7136 gen_helper_booke206_tlbilx3(cpu_env, t0); 7137 break; 7138 default: 7139 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7140 break; 7141 } 7142 7143 tcg_temp_free(t0); 7144 #endif /* defined(CONFIG_USER_ONLY) */ 7145 } 7146 7147 7148 /* wrtee */ 7149 static void gen_wrtee(DisasContext *ctx) 7150 { 7151 #if defined(CONFIG_USER_ONLY) 7152 GEN_PRIV; 7153 #else 7154 TCGv t0; 7155 7156 CHK_SV; 7157 t0 = tcg_temp_new(); 7158 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7159 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7160 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7161 tcg_temp_free(t0); 7162 /* 7163 * Stop translation to have a chance to raise an exception if we 7164 * just set msr_ee to 1 7165 */ 7166 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7167 #endif /* defined(CONFIG_USER_ONLY) */ 7168 } 7169 7170 /* wrteei */ 7171 static void gen_wrteei(DisasContext *ctx) 7172 { 7173 #if defined(CONFIG_USER_ONLY) 7174 GEN_PRIV; 7175 #else 7176 CHK_SV; 7177 if (ctx->opcode & 0x00008000) { 7178 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7179 /* Stop translation to have a chance to raise an exception */ 7180 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7181 } else { 7182 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7183 } 7184 #endif /* defined(CONFIG_USER_ONLY) */ 7185 } 7186 7187 /* PowerPC 440 specific instructions */ 7188 7189 /* dlmzb */ 7190 static void gen_dlmzb(DisasContext *ctx) 7191 { 7192 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7193 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7194 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7195 tcg_temp_free_i32(t0); 7196 } 7197 7198 /* mbar replaces eieio on 440 */ 7199 static void gen_mbar(DisasContext *ctx) 7200 { 7201 /* interpreted as no-op */ 7202 } 7203 7204 /* msync replaces sync on 440 */ 7205 static void gen_msync_4xx(DisasContext *ctx) 7206 { 7207 /* Only e500 seems to treat reserved bits as invalid */ 7208 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 7209 (ctx->opcode & 0x03FFF801)) { 7210 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7211 } 7212 /* otherwise interpreted as no-op */ 7213 } 7214 7215 /* icbt */ 7216 static void gen_icbt_440(DisasContext *ctx) 7217 { 7218 /* 7219 * interpreted as no-op 7220 * XXX: specification say this is treated as a load by the MMU but 7221 * does not generate any exception 7222 */ 7223 } 7224 7225 /* Embedded.Processor Control */ 7226 7227 static void gen_msgclr(DisasContext *ctx) 7228 { 7229 #if defined(CONFIG_USER_ONLY) 7230 GEN_PRIV; 7231 #else 7232 CHK_HV; 7233 if (is_book3s_arch2x(ctx)) { 7234 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 7235 } else { 7236 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 7237 } 7238 #endif /* defined(CONFIG_USER_ONLY) */ 7239 } 7240 7241 static void gen_msgsnd(DisasContext *ctx) 7242 { 7243 #if defined(CONFIG_USER_ONLY) 7244 GEN_PRIV; 7245 #else 7246 CHK_HV; 7247 if (is_book3s_arch2x(ctx)) { 7248 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 7249 } else { 7250 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 7251 } 7252 #endif /* defined(CONFIG_USER_ONLY) */ 7253 } 7254 7255 #if defined(TARGET_PPC64) 7256 static void gen_msgclrp(DisasContext *ctx) 7257 { 7258 #if defined(CONFIG_USER_ONLY) 7259 GEN_PRIV; 7260 #else 7261 CHK_SV; 7262 gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 7263 #endif /* defined(CONFIG_USER_ONLY) */ 7264 } 7265 7266 static void gen_msgsndp(DisasContext *ctx) 7267 { 7268 #if defined(CONFIG_USER_ONLY) 7269 GEN_PRIV; 7270 #else 7271 CHK_SV; 7272 gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 7273 #endif /* defined(CONFIG_USER_ONLY) */ 7274 } 7275 #endif 7276 7277 static void gen_msgsync(DisasContext *ctx) 7278 { 7279 #if defined(CONFIG_USER_ONLY) 7280 GEN_PRIV; 7281 #else 7282 CHK_HV; 7283 #endif /* defined(CONFIG_USER_ONLY) */ 7284 /* interpreted as no-op */ 7285 } 7286 7287 #if defined(TARGET_PPC64) 7288 static void gen_maddld(DisasContext *ctx) 7289 { 7290 TCGv_i64 t1 = tcg_temp_new_i64(); 7291 7292 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7293 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7294 tcg_temp_free_i64(t1); 7295 } 7296 7297 /* maddhd maddhdu */ 7298 static void gen_maddhd_maddhdu(DisasContext *ctx) 7299 { 7300 TCGv_i64 lo = tcg_temp_new_i64(); 7301 TCGv_i64 hi = tcg_temp_new_i64(); 7302 TCGv_i64 t1 = tcg_temp_new_i64(); 7303 7304 if (Rc(ctx->opcode)) { 7305 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7306 cpu_gpr[rB(ctx->opcode)]); 7307 tcg_gen_movi_i64(t1, 0); 7308 } else { 7309 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7310 cpu_gpr[rB(ctx->opcode)]); 7311 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7312 } 7313 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7314 cpu_gpr[rC(ctx->opcode)], t1); 7315 tcg_temp_free_i64(lo); 7316 tcg_temp_free_i64(hi); 7317 tcg_temp_free_i64(t1); 7318 } 7319 #endif /* defined(TARGET_PPC64) */ 7320 7321 static void gen_tbegin(DisasContext *ctx) 7322 { 7323 if (unlikely(!ctx->tm_enabled)) { 7324 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7325 return; 7326 } 7327 gen_helper_tbegin(cpu_env); 7328 } 7329 7330 #define GEN_TM_NOOP(name) \ 7331 static inline void gen_##name(DisasContext *ctx) \ 7332 { \ 7333 if (unlikely(!ctx->tm_enabled)) { \ 7334 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7335 return; \ 7336 } \ 7337 /* \ 7338 * Because tbegin always fails in QEMU, these user \ 7339 * space instructions all have a simple implementation: \ 7340 * \ 7341 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7342 * = 0b0 || 0b00 || 0b0 \ 7343 */ \ 7344 tcg_gen_movi_i32(cpu_crf[0], 0); \ 7345 } 7346 7347 GEN_TM_NOOP(tend); 7348 GEN_TM_NOOP(tabort); 7349 GEN_TM_NOOP(tabortwc); 7350 GEN_TM_NOOP(tabortwci); 7351 GEN_TM_NOOP(tabortdc); 7352 GEN_TM_NOOP(tabortdci); 7353 GEN_TM_NOOP(tsr); 7354 7355 static inline void gen_cp_abort(DisasContext *ctx) 7356 { 7357 /* Do Nothing */ 7358 } 7359 7360 #define GEN_CP_PASTE_NOOP(name) \ 7361 static inline void gen_##name(DisasContext *ctx) \ 7362 { \ 7363 /* \ 7364 * Generate invalid exception until we have an \ 7365 * implementation of the copy paste facility \ 7366 */ \ 7367 gen_invalid(ctx); \ 7368 } 7369 7370 GEN_CP_PASTE_NOOP(copy) 7371 GEN_CP_PASTE_NOOP(paste) 7372 7373 static void gen_tcheck(DisasContext *ctx) 7374 { 7375 if (unlikely(!ctx->tm_enabled)) { 7376 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7377 return; 7378 } 7379 /* 7380 * Because tbegin always fails, the tcheck implementation is 7381 * simple: 7382 * 7383 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7384 * = 0b1 || 0b00 || 0b0 7385 */ 7386 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7387 } 7388 7389 #if defined(CONFIG_USER_ONLY) 7390 #define GEN_TM_PRIV_NOOP(name) \ 7391 static inline void gen_##name(DisasContext *ctx) \ 7392 { \ 7393 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7394 } 7395 7396 #else 7397 7398 #define GEN_TM_PRIV_NOOP(name) \ 7399 static inline void gen_##name(DisasContext *ctx) \ 7400 { \ 7401 CHK_SV; \ 7402 if (unlikely(!ctx->tm_enabled)) { \ 7403 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7404 return; \ 7405 } \ 7406 /* \ 7407 * Because tbegin always fails, the implementation is \ 7408 * simple: \ 7409 * \ 7410 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7411 * = 0b0 || 0b00 | 0b0 \ 7412 */ \ 7413 tcg_gen_movi_i32(cpu_crf[0], 0); \ 7414 } 7415 7416 #endif 7417 7418 GEN_TM_PRIV_NOOP(treclaim); 7419 GEN_TM_PRIV_NOOP(trechkpt); 7420 7421 static inline void get_fpr(TCGv_i64 dst, int regno) 7422 { 7423 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 7424 } 7425 7426 static inline void set_fpr(int regno, TCGv_i64 src) 7427 { 7428 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 7429 } 7430 7431 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7432 { 7433 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7434 } 7435 7436 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7437 { 7438 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7439 } 7440 7441 /* 7442 * Helpers for decodetree used by !function for decoding arguments. 7443 */ 7444 static int times_4(DisasContext *ctx, int x) 7445 { 7446 return x * 4; 7447 } 7448 7449 /* 7450 * Helpers for trans_* functions to check for specific insns flags. 7451 * Use token pasting to ensure that we use the proper flag with the 7452 * proper variable. 7453 */ 7454 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 7455 do { \ 7456 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 7457 return false; \ 7458 } \ 7459 } while (0) 7460 7461 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 7462 do { \ 7463 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 7464 return false; \ 7465 } \ 7466 } while (0) 7467 7468 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 7469 #if TARGET_LONG_BITS == 32 7470 # define REQUIRE_64BIT(CTX) return false 7471 #else 7472 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 7473 #endif 7474 7475 /* 7476 * Helpers for implementing sets of trans_* functions. 7477 * Defer the implementation of NAME to FUNC, with optional extra arguments. 7478 */ 7479 #define TRANS(NAME, FUNC, ...) \ 7480 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7481 { return FUNC(ctx, a, __VA_ARGS__); } 7482 7483 #define TRANS64(NAME, FUNC, ...) \ 7484 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7485 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 7486 7487 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 7488 7489 7490 #include "decode-insn32.c.inc" 7491 #include "decode-insn64.c.inc" 7492 #include "translate/fixedpoint-impl.c.inc" 7493 7494 #include "translate/fp-impl.c.inc" 7495 7496 #include "translate/vmx-impl.c.inc" 7497 7498 #include "translate/vsx-impl.c.inc" 7499 #include "translate/vector-impl.c.inc" 7500 7501 #include "translate/dfp-impl.c.inc" 7502 7503 #include "translate/spe-impl.c.inc" 7504 7505 /* Handles lfdp, lxsd, lxssp */ 7506 static void gen_dform39(DisasContext *ctx) 7507 { 7508 switch (ctx->opcode & 0x3) { 7509 case 0: /* lfdp */ 7510 if (ctx->insns_flags2 & PPC2_ISA205) { 7511 return gen_lfdp(ctx); 7512 } 7513 break; 7514 case 2: /* lxsd */ 7515 if (ctx->insns_flags2 & PPC2_ISA300) { 7516 return gen_lxsd(ctx); 7517 } 7518 break; 7519 case 3: /* lxssp */ 7520 if (ctx->insns_flags2 & PPC2_ISA300) { 7521 return gen_lxssp(ctx); 7522 } 7523 break; 7524 } 7525 return gen_invalid(ctx); 7526 } 7527 7528 /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7529 static void gen_dform3D(DisasContext *ctx) 7530 { 7531 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7532 switch (ctx->opcode & 0x7) { 7533 case 1: /* lxv */ 7534 if (ctx->insns_flags2 & PPC2_ISA300) { 7535 return gen_lxv(ctx); 7536 } 7537 break; 7538 case 5: /* stxv */ 7539 if (ctx->insns_flags2 & PPC2_ISA300) { 7540 return gen_stxv(ctx); 7541 } 7542 break; 7543 } 7544 } else { /* DS-FORM */ 7545 switch (ctx->opcode & 0x3) { 7546 case 0: /* stfdp */ 7547 if (ctx->insns_flags2 & PPC2_ISA205) { 7548 return gen_stfdp(ctx); 7549 } 7550 break; 7551 case 2: /* stxsd */ 7552 if (ctx->insns_flags2 & PPC2_ISA300) { 7553 return gen_stxsd(ctx); 7554 } 7555 break; 7556 case 3: /* stxssp */ 7557 if (ctx->insns_flags2 & PPC2_ISA300) { 7558 return gen_stxssp(ctx); 7559 } 7560 break; 7561 } 7562 } 7563 return gen_invalid(ctx); 7564 } 7565 7566 #if defined(TARGET_PPC64) 7567 /* brd */ 7568 static void gen_brd(DisasContext *ctx) 7569 { 7570 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 7571 } 7572 7573 /* brw */ 7574 static void gen_brw(DisasContext *ctx) 7575 { 7576 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 7577 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 7578 7579 } 7580 7581 /* brh */ 7582 static void gen_brh(DisasContext *ctx) 7583 { 7584 TCGv_i64 t0 = tcg_temp_new_i64(); 7585 TCGv_i64 t1 = tcg_temp_new_i64(); 7586 TCGv_i64 t2 = tcg_temp_new_i64(); 7587 7588 tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 7589 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 7590 tcg_gen_and_i64(t2, t1, t0); 7591 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 7592 tcg_gen_shli_i64(t1, t1, 8); 7593 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 7594 7595 tcg_temp_free_i64(t0); 7596 tcg_temp_free_i64(t1); 7597 tcg_temp_free_i64(t2); 7598 } 7599 #endif 7600 7601 static opcode_t opcodes[] = { 7602 #if defined(TARGET_PPC64) 7603 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 7604 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 7605 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 7606 #endif 7607 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7608 #if defined(TARGET_PPC64) 7609 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7610 #endif 7611 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7612 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7613 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7614 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7615 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7616 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7617 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7618 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7619 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7620 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7621 #if defined(TARGET_PPC64) 7622 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7623 #endif 7624 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7625 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7626 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7627 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7628 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7629 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7630 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 7631 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7632 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7633 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7634 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7635 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7636 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7637 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7638 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7639 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7640 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7641 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7642 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7643 #if defined(TARGET_PPC64) 7644 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7645 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7646 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7647 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7648 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7649 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7650 #endif 7651 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7652 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7653 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7654 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7655 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7656 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7657 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7658 #if defined(TARGET_PPC64) 7659 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7660 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7661 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7662 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7663 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7664 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7665 PPC_NONE, PPC2_ISA300), 7666 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7667 PPC_NONE, PPC2_ISA300), 7668 #endif 7669 #if defined(TARGET_PPC64) 7670 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 7671 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 7672 #endif 7673 /* handles lfdp, lxsd, lxssp */ 7674 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7675 /* handles stfdp, lxv, stxsd, stxssp, stxv */ 7676 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7677 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7678 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7679 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7680 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7681 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7682 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7683 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7684 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7685 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7686 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7687 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7688 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7689 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7690 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7691 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7692 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7693 #if defined(TARGET_PPC64) 7694 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7695 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7696 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7697 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7698 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7699 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7700 #endif 7701 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7702 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7703 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7704 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7705 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7706 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7707 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7708 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7709 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7710 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7711 #if defined(TARGET_PPC64) 7712 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 7713 #if !defined(CONFIG_USER_ONLY) 7714 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 7715 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 7716 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 7717 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 7718 #endif 7719 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7720 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7721 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7722 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7723 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7724 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7725 #endif 7726 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 7727 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 7728 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7729 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7730 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7731 #if defined(TARGET_PPC64) 7732 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7733 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7734 #endif 7735 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7736 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7737 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7738 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7739 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7740 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7741 #if defined(TARGET_PPC64) 7742 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7743 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7744 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7745 #endif 7746 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7747 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7748 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 7749 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7750 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7751 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 7752 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7753 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 7754 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7755 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 7756 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7757 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7758 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 7759 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7760 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 7761 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7762 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7763 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 7764 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7765 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7766 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7767 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7768 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7769 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7770 #if defined(TARGET_PPC64) 7771 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7772 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7773 PPC_SEGMENT_64B), 7774 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7775 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7776 PPC_SEGMENT_64B), 7777 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7778 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7779 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7780 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7781 #endif 7782 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7783 /* 7784 * XXX Those instructions will need to be handled differently for 7785 * different ISA versions 7786 */ 7787 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7788 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7789 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7790 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7791 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7792 #if defined(TARGET_PPC64) 7793 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7794 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7795 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 7796 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7797 #endif 7798 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7799 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7800 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7801 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7802 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7803 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7804 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7805 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7806 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7807 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7808 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7809 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7810 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7811 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7812 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7813 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7814 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7815 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7816 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7817 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7818 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7819 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7820 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7821 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7822 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7823 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7824 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7825 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7826 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7827 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7828 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7829 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7830 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7831 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7832 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7833 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7834 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7835 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7836 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7837 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7838 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7839 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7840 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7841 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7842 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7843 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7844 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7845 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7846 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7847 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7848 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7849 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7850 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7851 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7852 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7853 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7854 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7855 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7856 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7857 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7858 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7859 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7860 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7861 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7862 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7863 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7864 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7865 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7866 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7867 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7868 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7869 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7870 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7871 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7872 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7873 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7874 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7875 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7876 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7877 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7878 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7879 PPC_NONE, PPC2_BOOKE206), 7880 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7881 PPC_NONE, PPC2_BOOKE206), 7882 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7883 PPC_NONE, PPC2_BOOKE206), 7884 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7885 PPC_NONE, PPC2_BOOKE206), 7886 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7887 PPC_NONE, PPC2_BOOKE206), 7888 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7889 PPC_NONE, PPC2_PRCNTL), 7890 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7891 PPC_NONE, PPC2_PRCNTL), 7892 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 7893 PPC_NONE, PPC2_PRCNTL), 7894 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7895 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7896 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7897 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7898 PPC_BOOKE, PPC2_BOOKE206), 7899 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7900 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7901 PPC_BOOKE, PPC2_BOOKE206), 7902 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 7903 PPC_440_SPEC), 7904 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7905 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7906 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7907 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7908 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7909 #if defined(TARGET_PPC64) 7910 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7911 PPC2_ISA300), 7912 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7913 GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 7914 PPC_NONE, PPC2_ISA207S), 7915 GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 7916 PPC_NONE, PPC2_ISA207S), 7917 #endif 7918 7919 #undef GEN_INT_ARITH_ADD 7920 #undef GEN_INT_ARITH_ADD_CONST 7921 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7922 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7923 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7924 add_ca, compute_ca, compute_ov) \ 7925 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7926 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7927 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7928 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7929 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7930 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7931 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7932 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7933 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 7934 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7935 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7936 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7937 7938 #undef GEN_INT_ARITH_DIVW 7939 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7940 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7941 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7942 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7943 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7944 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7945 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7946 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7947 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7948 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7949 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7950 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7951 7952 #if defined(TARGET_PPC64) 7953 #undef GEN_INT_ARITH_DIVD 7954 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7955 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7956 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7957 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7958 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7959 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7960 7961 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7962 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7963 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7964 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7965 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7966 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7967 7968 #undef GEN_INT_ARITH_MUL_HELPER 7969 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7970 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7971 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7972 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7973 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7974 #endif 7975 7976 #undef GEN_INT_ARITH_SUBF 7977 #undef GEN_INT_ARITH_SUBF_CONST 7978 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7979 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7980 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7981 add_ca, compute_ca, compute_ov) \ 7982 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7983 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7984 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7985 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7986 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7987 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7988 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7989 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7990 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7991 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7992 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7993 7994 #undef GEN_LOGICAL1 7995 #undef GEN_LOGICAL2 7996 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7997 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7998 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7999 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 8000 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 8001 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 8002 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 8003 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 8004 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 8005 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 8006 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8007 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8008 #if defined(TARGET_PPC64) 8009 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8010 #endif 8011 8012 #if defined(TARGET_PPC64) 8013 #undef GEN_PPC64_R2 8014 #undef GEN_PPC64_R4 8015 #define GEN_PPC64_R2(name, opc1, opc2) \ 8016 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8017 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8018 PPC_64B) 8019 #define GEN_PPC64_R4(name, opc1, opc2) \ 8020 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8021 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8022 PPC_64B), \ 8023 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8024 PPC_64B), \ 8025 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8026 PPC_64B) 8027 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8028 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8029 GEN_PPC64_R4(rldic, 0x1E, 0x04), 8030 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8031 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8032 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8033 #endif 8034 8035 #undef GEN_LDX_E 8036 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8037 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8038 8039 #if defined(TARGET_PPC64) 8040 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8041 8042 /* HV/P7 and later only */ 8043 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8044 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8045 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8046 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8047 #endif 8048 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8049 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8050 8051 /* External PID based load */ 8052 #undef GEN_LDEPX 8053 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 8054 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 8055 0x00000001, PPC_NONE, PPC2_BOOKE206), 8056 8057 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 8058 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 8059 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 8060 #if defined(TARGET_PPC64) 8061 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 8062 #endif 8063 8064 #undef GEN_STX_E 8065 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 8066 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8067 8068 #if defined(TARGET_PPC64) 8069 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8070 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8071 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8072 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8073 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8074 #endif 8075 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8076 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8077 8078 #undef GEN_STEPX 8079 #define GEN_STEPX(name, ldop, opc2, opc3) \ 8080 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 8081 0x00000001, PPC_NONE, PPC2_BOOKE206), 8082 8083 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 8084 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 8085 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 8086 #if defined(TARGET_PPC64) 8087 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 8088 #endif 8089 8090 #undef GEN_CRLOGIC 8091 #define GEN_CRLOGIC(name, tcg_op, opc) \ 8092 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8093 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8094 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8095 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8096 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8097 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8098 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8099 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8100 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8101 8102 #undef GEN_MAC_HANDLER 8103 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8104 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8105 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8106 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8107 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8108 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8109 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8110 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8111 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8112 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8113 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8114 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8115 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8116 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8117 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8118 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8119 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8120 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8121 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8122 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8123 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8124 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8125 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8126 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8127 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8128 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8129 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8130 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8131 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8132 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8133 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8134 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8135 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8136 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8137 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8138 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8139 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8140 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8141 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8142 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8143 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8144 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8145 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8146 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8147 8148 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8149 PPC_NONE, PPC2_TM), 8150 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8151 PPC_NONE, PPC2_TM), 8152 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8153 PPC_NONE, PPC2_TM), 8154 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8155 PPC_NONE, PPC2_TM), 8156 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8157 PPC_NONE, PPC2_TM), 8158 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8159 PPC_NONE, PPC2_TM), 8160 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8161 PPC_NONE, PPC2_TM), 8162 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8163 PPC_NONE, PPC2_TM), 8164 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8165 PPC_NONE, PPC2_TM), 8166 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8167 PPC_NONE, PPC2_TM), 8168 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8169 PPC_NONE, PPC2_TM), 8170 8171 #include "translate/fp-ops.c.inc" 8172 8173 #include "translate/vmx-ops.c.inc" 8174 8175 #include "translate/vsx-ops.c.inc" 8176 8177 #include "translate/dfp-ops.c.inc" 8178 8179 #include "translate/spe-ops.c.inc" 8180 }; 8181 8182 /*****************************************************************************/ 8183 /* Opcode types */ 8184 enum { 8185 PPC_DIRECT = 0, /* Opcode routine */ 8186 PPC_INDIRECT = 1, /* Indirect opcode table */ 8187 }; 8188 8189 #define PPC_OPCODE_MASK 0x3 8190 8191 static inline int is_indirect_opcode(void *handler) 8192 { 8193 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 8194 } 8195 8196 static inline opc_handler_t **ind_table(void *handler) 8197 { 8198 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 8199 } 8200 8201 /* Instruction table creation */ 8202 /* Opcodes tables creation */ 8203 static void fill_new_table(opc_handler_t **table, int len) 8204 { 8205 int i; 8206 8207 for (i = 0; i < len; i++) { 8208 table[i] = &invalid_handler; 8209 } 8210 } 8211 8212 static int create_new_table(opc_handler_t **table, unsigned char idx) 8213 { 8214 opc_handler_t **tmp; 8215 8216 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 8217 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 8218 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 8219 8220 return 0; 8221 } 8222 8223 static int insert_in_table(opc_handler_t **table, unsigned char idx, 8224 opc_handler_t *handler) 8225 { 8226 if (table[idx] != &invalid_handler) { 8227 return -1; 8228 } 8229 table[idx] = handler; 8230 8231 return 0; 8232 } 8233 8234 static int register_direct_insn(opc_handler_t **ppc_opcodes, 8235 unsigned char idx, opc_handler_t *handler) 8236 { 8237 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 8238 printf("*** ERROR: opcode %02x already assigned in main " 8239 "opcode table\n", idx); 8240 return -1; 8241 } 8242 8243 return 0; 8244 } 8245 8246 static int register_ind_in_table(opc_handler_t **table, 8247 unsigned char idx1, unsigned char idx2, 8248 opc_handler_t *handler) 8249 { 8250 if (table[idx1] == &invalid_handler) { 8251 if (create_new_table(table, idx1) < 0) { 8252 printf("*** ERROR: unable to create indirect table " 8253 "idx=%02x\n", idx1); 8254 return -1; 8255 } 8256 } else { 8257 if (!is_indirect_opcode(table[idx1])) { 8258 printf("*** ERROR: idx %02x already assigned to a direct " 8259 "opcode\n", idx1); 8260 return -1; 8261 } 8262 } 8263 if (handler != NULL && 8264 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 8265 printf("*** ERROR: opcode %02x already assigned in " 8266 "opcode table %02x\n", idx2, idx1); 8267 return -1; 8268 } 8269 8270 return 0; 8271 } 8272 8273 static int register_ind_insn(opc_handler_t **ppc_opcodes, 8274 unsigned char idx1, unsigned char idx2, 8275 opc_handler_t *handler) 8276 { 8277 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 8278 } 8279 8280 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 8281 unsigned char idx1, unsigned char idx2, 8282 unsigned char idx3, opc_handler_t *handler) 8283 { 8284 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 8285 printf("*** ERROR: unable to join indirect table idx " 8286 "[%02x-%02x]\n", idx1, idx2); 8287 return -1; 8288 } 8289 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 8290 handler) < 0) { 8291 printf("*** ERROR: unable to insert opcode " 8292 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 8293 return -1; 8294 } 8295 8296 return 0; 8297 } 8298 8299 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 8300 unsigned char idx1, unsigned char idx2, 8301 unsigned char idx3, unsigned char idx4, 8302 opc_handler_t *handler) 8303 { 8304 opc_handler_t **table; 8305 8306 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 8307 printf("*** ERROR: unable to join indirect table idx " 8308 "[%02x-%02x]\n", idx1, idx2); 8309 return -1; 8310 } 8311 table = ind_table(ppc_opcodes[idx1]); 8312 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 8313 printf("*** ERROR: unable to join 2nd-level indirect table idx " 8314 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 8315 return -1; 8316 } 8317 table = ind_table(table[idx2]); 8318 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 8319 printf("*** ERROR: unable to insert opcode " 8320 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 8321 return -1; 8322 } 8323 return 0; 8324 } 8325 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 8326 { 8327 if (insn->opc2 != 0xFF) { 8328 if (insn->opc3 != 0xFF) { 8329 if (insn->opc4 != 0xFF) { 8330 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 8331 insn->opc3, insn->opc4, 8332 &insn->handler) < 0) { 8333 return -1; 8334 } 8335 } else { 8336 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 8337 insn->opc3, &insn->handler) < 0) { 8338 return -1; 8339 } 8340 } 8341 } else { 8342 if (register_ind_insn(ppc_opcodes, insn->opc1, 8343 insn->opc2, &insn->handler) < 0) { 8344 return -1; 8345 } 8346 } 8347 } else { 8348 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 8349 return -1; 8350 } 8351 } 8352 8353 return 0; 8354 } 8355 8356 static int test_opcode_table(opc_handler_t **table, int len) 8357 { 8358 int i, count, tmp; 8359 8360 for (i = 0, count = 0; i < len; i++) { 8361 /* Consistency fixup */ 8362 if (table[i] == NULL) { 8363 table[i] = &invalid_handler; 8364 } 8365 if (table[i] != &invalid_handler) { 8366 if (is_indirect_opcode(table[i])) { 8367 tmp = test_opcode_table(ind_table(table[i]), 8368 PPC_CPU_INDIRECT_OPCODES_LEN); 8369 if (tmp == 0) { 8370 free(table[i]); 8371 table[i] = &invalid_handler; 8372 } else { 8373 count++; 8374 } 8375 } else { 8376 count++; 8377 } 8378 } 8379 } 8380 8381 return count; 8382 } 8383 8384 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 8385 { 8386 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 8387 printf("*** WARNING: no opcode defined !\n"); 8388 } 8389 } 8390 8391 /*****************************************************************************/ 8392 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 8393 { 8394 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8395 opcode_t *opc; 8396 8397 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 8398 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 8399 if (((opc->handler.type & pcc->insns_flags) != 0) || 8400 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 8401 if (register_insn(cpu->opcodes, opc) < 0) { 8402 error_setg(errp, "ERROR initializing PowerPC instruction " 8403 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 8404 opc->opc3); 8405 return; 8406 } 8407 } 8408 } 8409 fix_opcode_tables(cpu->opcodes); 8410 fflush(stdout); 8411 fflush(stderr); 8412 } 8413 8414 void destroy_ppc_opcodes(PowerPCCPU *cpu) 8415 { 8416 opc_handler_t **table, **table_2; 8417 int i, j, k; 8418 8419 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 8420 if (cpu->opcodes[i] == &invalid_handler) { 8421 continue; 8422 } 8423 if (is_indirect_opcode(cpu->opcodes[i])) { 8424 table = ind_table(cpu->opcodes[i]); 8425 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 8426 if (table[j] == &invalid_handler) { 8427 continue; 8428 } 8429 if (is_indirect_opcode(table[j])) { 8430 table_2 = ind_table(table[j]); 8431 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 8432 if (table_2[k] != &invalid_handler && 8433 is_indirect_opcode(table_2[k])) { 8434 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 8435 ~PPC_INDIRECT)); 8436 } 8437 } 8438 g_free((opc_handler_t *)((uintptr_t)table[j] & 8439 ~PPC_INDIRECT)); 8440 } 8441 } 8442 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 8443 ~PPC_INDIRECT)); 8444 } 8445 } 8446 } 8447 8448 int ppc_fixup_cpu(PowerPCCPU *cpu) 8449 { 8450 CPUPPCState *env = &cpu->env; 8451 8452 /* 8453 * TCG doesn't (yet) emulate some groups of instructions that are 8454 * implemented on some otherwise supported CPUs (e.g. VSX and 8455 * decimal floating point instructions on POWER7). We remove 8456 * unsupported instruction groups from the cpu state's instruction 8457 * masks and hope the guest can cope. For at least the pseries 8458 * machine, the unavailability of these instructions can be 8459 * advertised to the guest via the device tree. 8460 */ 8461 if ((env->insns_flags & ~PPC_TCG_INSNS) 8462 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 8463 warn_report("Disabling some instructions which are not " 8464 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 8465 env->insns_flags & ~PPC_TCG_INSNS, 8466 env->insns_flags2 & ~PPC_TCG_INSNS2); 8467 } 8468 env->insns_flags &= PPC_TCG_INSNS; 8469 env->insns_flags2 &= PPC_TCG_INSNS2; 8470 return 0; 8471 } 8472 8473 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 8474 { 8475 opc_handler_t **table, *handler; 8476 uint32_t inval; 8477 8478 ctx->opcode = insn; 8479 8480 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8481 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8482 ctx->le_mode ? "little" : "big"); 8483 8484 table = cpu->opcodes; 8485 handler = table[opc1(insn)]; 8486 if (is_indirect_opcode(handler)) { 8487 table = ind_table(handler); 8488 handler = table[opc2(insn)]; 8489 if (is_indirect_opcode(handler)) { 8490 table = ind_table(handler); 8491 handler = table[opc3(insn)]; 8492 if (is_indirect_opcode(handler)) { 8493 table = ind_table(handler); 8494 handler = table[opc4(insn)]; 8495 } 8496 } 8497 } 8498 8499 /* Is opcode *REALLY* valid ? */ 8500 if (unlikely(handler->handler == &gen_invalid)) { 8501 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8502 "%02x - %02x - %02x - %02x (%08x) " 8503 TARGET_FMT_lx "\n", 8504 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8505 insn, ctx->cia); 8506 return false; 8507 } 8508 8509 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8510 && Rc(insn))) { 8511 inval = handler->inval2; 8512 } else { 8513 inval = handler->inval1; 8514 } 8515 8516 if (unlikely((insn & inval) != 0)) { 8517 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8518 "%02x - %02x - %02x - %02x (%08x) " 8519 TARGET_FMT_lx "\n", insn & inval, 8520 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8521 insn, ctx->cia); 8522 return false; 8523 } 8524 8525 handler->handler(ctx); 8526 return true; 8527 } 8528 8529 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 8530 { 8531 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8532 CPUPPCState *env = cs->env_ptr; 8533 uint32_t hflags = ctx->base.tb->flags; 8534 8535 ctx->spr_cb = env->spr_cb; 8536 ctx->pr = (hflags >> HFLAGS_PR) & 1; 8537 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 8538 ctx->dr = (hflags >> HFLAGS_DR) & 1; 8539 ctx->hv = (hflags >> HFLAGS_HV) & 1; 8540 ctx->insns_flags = env->insns_flags; 8541 ctx->insns_flags2 = env->insns_flags2; 8542 ctx->access_type = -1; 8543 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 8544 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 8545 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 8546 ctx->flags = env->flags; 8547 #if defined(TARGET_PPC64) 8548 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 8549 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 8550 #endif 8551 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 8552 || env->mmu_model == POWERPC_MMU_601 8553 || env->mmu_model & POWERPC_MMU_64; 8554 8555 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 8556 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 8557 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 8558 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 8559 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 8560 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 8561 ctx->hr = (hflags >> HFLAGS_HR) & 1; 8562 8563 ctx->singlestep_enabled = 0; 8564 if ((hflags >> HFLAGS_SE) & 1) { 8565 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 8566 } 8567 if ((hflags >> HFLAGS_BE) & 1) { 8568 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 8569 } 8570 if (unlikely(ctx->base.singlestep_enabled)) { 8571 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 8572 } 8573 8574 if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) { 8575 ctx->base.max_insns = 1; 8576 } 8577 } 8578 8579 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 8580 { 8581 } 8582 8583 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 8584 { 8585 tcg_gen_insn_start(dcbase->pc_next); 8586 } 8587 8588 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 8589 { 8590 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 8591 return opc1(insn) == 1; 8592 } 8593 8594 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 8595 { 8596 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8597 PowerPCCPU *cpu = POWERPC_CPU(cs); 8598 CPUPPCState *env = cs->env_ptr; 8599 target_ulong pc; 8600 uint32_t insn; 8601 bool ok; 8602 8603 LOG_DISAS("----------------\n"); 8604 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 8605 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 8606 8607 ctx->cia = pc = ctx->base.pc_next; 8608 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 8609 ctx->base.pc_next = pc += 4; 8610 8611 if (!is_prefix_insn(ctx, insn)) { 8612 ok = (decode_insn32(ctx, insn) || 8613 decode_legacy(cpu, ctx, insn)); 8614 } else if ((pc & 63) == 0) { 8615 /* 8616 * Power v3.1, section 1.9 Exceptions: 8617 * attempt to execute a prefixed instruction that crosses a 8618 * 64-byte address boundary (system alignment error). 8619 */ 8620 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 8621 ok = true; 8622 } else { 8623 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 8624 need_byteswap(ctx)); 8625 ctx->base.pc_next = pc += 4; 8626 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 8627 } 8628 if (!ok) { 8629 gen_invalid(ctx); 8630 } 8631 8632 /* End the TB when crossing a page boundary. */ 8633 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 8634 ctx->base.is_jmp = DISAS_TOO_MANY; 8635 } 8636 8637 translator_loop_temp_check(&ctx->base); 8638 } 8639 8640 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 8641 { 8642 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8643 DisasJumpType is_jmp = ctx->base.is_jmp; 8644 target_ulong nip = ctx->base.pc_next; 8645 int sse; 8646 8647 if (is_jmp == DISAS_NORETURN) { 8648 /* We have already exited the TB. */ 8649 return; 8650 } 8651 8652 /* Honor single stepping. */ 8653 sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP); 8654 if (unlikely(sse)) { 8655 switch (is_jmp) { 8656 case DISAS_TOO_MANY: 8657 case DISAS_EXIT_UPDATE: 8658 case DISAS_CHAIN_UPDATE: 8659 gen_update_nip(ctx, nip); 8660 break; 8661 case DISAS_EXIT: 8662 case DISAS_CHAIN: 8663 break; 8664 default: 8665 g_assert_not_reached(); 8666 } 8667 8668 if (sse & GDBSTUB_SINGLE_STEP) { 8669 gen_debug_exception(ctx); 8670 return; 8671 } 8672 /* else CPU_SINGLE_STEP... */ 8673 if (nip <= 0x100 || nip > 0xf00) { 8674 gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 8675 return; 8676 } 8677 } 8678 8679 switch (is_jmp) { 8680 case DISAS_TOO_MANY: 8681 if (use_goto_tb(ctx, nip)) { 8682 tcg_gen_goto_tb(0); 8683 gen_update_nip(ctx, nip); 8684 tcg_gen_exit_tb(ctx->base.tb, 0); 8685 break; 8686 } 8687 /* fall through */ 8688 case DISAS_CHAIN_UPDATE: 8689 gen_update_nip(ctx, nip); 8690 /* fall through */ 8691 case DISAS_CHAIN: 8692 tcg_gen_lookup_and_goto_ptr(); 8693 break; 8694 8695 case DISAS_EXIT_UPDATE: 8696 gen_update_nip(ctx, nip); 8697 /* fall through */ 8698 case DISAS_EXIT: 8699 tcg_gen_exit_tb(NULL, 0); 8700 break; 8701 8702 default: 8703 g_assert_not_reached(); 8704 } 8705 } 8706 8707 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8708 { 8709 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8710 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8711 } 8712 8713 static const TranslatorOps ppc_tr_ops = { 8714 .init_disas_context = ppc_tr_init_disas_context, 8715 .tb_start = ppc_tr_tb_start, 8716 .insn_start = ppc_tr_insn_start, 8717 .translate_insn = ppc_tr_translate_insn, 8718 .tb_stop = ppc_tr_tb_stop, 8719 .disas_log = ppc_tr_disas_log, 8720 }; 8721 8722 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8723 { 8724 DisasContext ctx; 8725 8726 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8727 } 8728 8729 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8730 target_ulong *data) 8731 { 8732 env->nip = data[0]; 8733 } 8734