1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 30 #include "exec/helper-proto.h" 31 #include "exec/helper-gen.h" 32 33 #include "exec/translator.h" 34 #include "exec/log.h" 35 #include "qemu/atomic128.h" 36 #include "spr_common.h" 37 #include "power8-pmu.h" 38 39 #include "qemu/qemu-print.h" 40 #include "qapi/error.h" 41 42 #define HELPER_H "helper.h" 43 #include "exec/helper-info.c.inc" 44 #undef HELPER_H 45 46 #define CPU_SINGLE_STEP 0x1 47 #define CPU_BRANCH_STEP 0x2 48 49 /* Include definitions for instructions classes and implementations flags */ 50 /* #define PPC_DEBUG_DISAS */ 51 52 #ifdef PPC_DEBUG_DISAS 53 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54 #else 55 # define LOG_DISAS(...) do { } while (0) 56 #endif 57 /*****************************************************************************/ 58 /* Code translation helpers */ 59 60 /* global register indexes */ 61 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62 + 10 * 4 + 22 * 5 /* SPE GPRh */ 63 + 8 * 5 /* CRF */]; 64 static TCGv cpu_gpr[32]; 65 static TCGv cpu_gprh[32]; 66 static TCGv_i32 cpu_crf[8]; 67 static TCGv cpu_nip; 68 static TCGv cpu_msr; 69 static TCGv cpu_ctr; 70 static TCGv cpu_lr; 71 #if defined(TARGET_PPC64) 72 static TCGv cpu_cfar; 73 #endif 74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75 static TCGv cpu_reserve; 76 static TCGv cpu_reserve_length; 77 static TCGv cpu_reserve_val; 78 #if defined(TARGET_PPC64) 79 static TCGv cpu_reserve_val2; 80 #endif 81 static TCGv cpu_fpscr; 82 static TCGv_i32 cpu_access_type; 83 84 void ppc_translate_init(void) 85 { 86 int i; 87 char *p; 88 size_t cpu_reg_names_size; 89 90 p = cpu_reg_names; 91 cpu_reg_names_size = sizeof(cpu_reg_names); 92 93 for (i = 0; i < 8; i++) { 94 snprintf(p, cpu_reg_names_size, "crf%d", i); 95 cpu_crf[i] = tcg_global_mem_new_i32(tcg_env, 96 offsetof(CPUPPCState, crf[i]), p); 97 p += 5; 98 cpu_reg_names_size -= 5; 99 } 100 101 for (i = 0; i < 32; i++) { 102 snprintf(p, cpu_reg_names_size, "r%d", i); 103 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 104 offsetof(CPUPPCState, gpr[i]), p); 105 p += (i < 10) ? 3 : 4; 106 cpu_reg_names_size -= (i < 10) ? 3 : 4; 107 snprintf(p, cpu_reg_names_size, "r%dH", i); 108 cpu_gprh[i] = tcg_global_mem_new(tcg_env, 109 offsetof(CPUPPCState, gprh[i]), p); 110 p += (i < 10) ? 4 : 5; 111 cpu_reg_names_size -= (i < 10) ? 4 : 5; 112 } 113 114 cpu_nip = tcg_global_mem_new(tcg_env, 115 offsetof(CPUPPCState, nip), "nip"); 116 117 cpu_msr = tcg_global_mem_new(tcg_env, 118 offsetof(CPUPPCState, msr), "msr"); 119 120 cpu_ctr = tcg_global_mem_new(tcg_env, 121 offsetof(CPUPPCState, ctr), "ctr"); 122 123 cpu_lr = tcg_global_mem_new(tcg_env, 124 offsetof(CPUPPCState, lr), "lr"); 125 126 #if defined(TARGET_PPC64) 127 cpu_cfar = tcg_global_mem_new(tcg_env, 128 offsetof(CPUPPCState, cfar), "cfar"); 129 #endif 130 131 cpu_xer = tcg_global_mem_new(tcg_env, 132 offsetof(CPUPPCState, xer), "xer"); 133 cpu_so = tcg_global_mem_new(tcg_env, 134 offsetof(CPUPPCState, so), "SO"); 135 cpu_ov = tcg_global_mem_new(tcg_env, 136 offsetof(CPUPPCState, ov), "OV"); 137 cpu_ca = tcg_global_mem_new(tcg_env, 138 offsetof(CPUPPCState, ca), "CA"); 139 cpu_ov32 = tcg_global_mem_new(tcg_env, 140 offsetof(CPUPPCState, ov32), "OV32"); 141 cpu_ca32 = tcg_global_mem_new(tcg_env, 142 offsetof(CPUPPCState, ca32), "CA32"); 143 144 cpu_reserve = tcg_global_mem_new(tcg_env, 145 offsetof(CPUPPCState, reserve_addr), 146 "reserve_addr"); 147 cpu_reserve_length = tcg_global_mem_new(tcg_env, 148 offsetof(CPUPPCState, 149 reserve_length), 150 "reserve_length"); 151 cpu_reserve_val = tcg_global_mem_new(tcg_env, 152 offsetof(CPUPPCState, reserve_val), 153 "reserve_val"); 154 #if defined(TARGET_PPC64) 155 cpu_reserve_val2 = tcg_global_mem_new(tcg_env, 156 offsetof(CPUPPCState, reserve_val2), 157 "reserve_val2"); 158 #endif 159 160 cpu_fpscr = tcg_global_mem_new(tcg_env, 161 offsetof(CPUPPCState, fpscr), "fpscr"); 162 163 cpu_access_type = tcg_global_mem_new_i32(tcg_env, 164 offsetof(CPUPPCState, access_type), 165 "access_type"); 166 } 167 168 /* internal defines */ 169 struct DisasContext { 170 DisasContextBase base; 171 target_ulong cia; /* current instruction address */ 172 uint32_t opcode; 173 /* Routine used to access memory */ 174 bool pr, hv, dr, le_mode; 175 bool lazy_tlb_flush; 176 bool need_access_type; 177 int mem_idx; 178 int access_type; 179 /* Translation flags */ 180 MemOp default_tcg_memop_mask; 181 #if defined(TARGET_PPC64) 182 bool sf_mode; 183 bool has_cfar; 184 #endif 185 bool fpu_enabled; 186 bool altivec_enabled; 187 bool vsx_enabled; 188 bool spe_enabled; 189 bool tm_enabled; 190 bool gtse; 191 bool hr; 192 bool mmcr0_pmcc0; 193 bool mmcr0_pmcc1; 194 bool mmcr0_pmcjce; 195 bool pmc_other; 196 bool pmu_insn_cnt; 197 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 198 int singlestep_enabled; 199 uint32_t flags; 200 uint64_t insns_flags; 201 uint64_t insns_flags2; 202 }; 203 204 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 205 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 206 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 207 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 208 209 /* Return true iff byteswap is needed in a scalar memop */ 210 static inline bool need_byteswap(const DisasContext *ctx) 211 { 212 #if TARGET_BIG_ENDIAN 213 return ctx->le_mode; 214 #else 215 return !ctx->le_mode; 216 #endif 217 } 218 219 /* True when active word size < size of target_long. */ 220 #ifdef TARGET_PPC64 221 # define NARROW_MODE(C) (!(C)->sf_mode) 222 #else 223 # define NARROW_MODE(C) 0 224 #endif 225 226 struct opc_handler_t { 227 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 228 uint32_t inval1; 229 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 230 uint32_t inval2; 231 /* instruction type */ 232 uint64_t type; 233 /* extended instruction type */ 234 uint64_t type2; 235 /* handler */ 236 void (*handler)(DisasContext *ctx); 237 }; 238 239 static inline bool gen_serialize(DisasContext *ctx) 240 { 241 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 242 /* Restart with exclusive lock. */ 243 gen_helper_exit_atomic(tcg_env); 244 ctx->base.is_jmp = DISAS_NORETURN; 245 return false; 246 } 247 return true; 248 } 249 250 #if !defined(CONFIG_USER_ONLY) 251 #if defined(TARGET_PPC64) 252 static inline bool gen_serialize_core(DisasContext *ctx) 253 { 254 if (ctx->flags & POWERPC_FLAG_SMT) { 255 return gen_serialize(ctx); 256 } 257 return true; 258 } 259 #endif 260 261 static inline bool gen_serialize_core_lpar(DisasContext *ctx) 262 { 263 #if defined(TARGET_PPC64) 264 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 265 return gen_serialize(ctx); 266 } 267 #endif 268 return true; 269 } 270 #endif 271 272 /* SPR load/store helpers */ 273 static inline void gen_load_spr(TCGv t, int reg) 274 { 275 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); 276 } 277 278 static inline void gen_store_spr(int reg, TCGv t) 279 { 280 tcg_gen_st_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); 281 } 282 283 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 284 { 285 if (ctx->need_access_type && ctx->access_type != access_type) { 286 tcg_gen_movi_i32(cpu_access_type, access_type); 287 ctx->access_type = access_type; 288 } 289 } 290 291 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 292 { 293 if (NARROW_MODE(ctx)) { 294 nip = (uint32_t)nip; 295 } 296 tcg_gen_movi_tl(cpu_nip, nip); 297 } 298 299 static void gen_exception_err_nip(DisasContext *ctx, uint32_t excp, 300 uint32_t error, target_ulong nip) 301 { 302 TCGv_i32 t0, t1; 303 304 gen_update_nip(ctx, nip); 305 t0 = tcg_constant_i32(excp); 306 t1 = tcg_constant_i32(error); 307 gen_helper_raise_exception_err(tcg_env, t0, t1); 308 ctx->base.is_jmp = DISAS_NORETURN; 309 } 310 311 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, 312 uint32_t error) 313 { 314 /* 315 * These are all synchronous exceptions, we set the PC back to the 316 * faulting instruction 317 */ 318 gen_exception_err_nip(ctx, excp, error, ctx->cia); 319 } 320 321 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 322 target_ulong nip) 323 { 324 TCGv_i32 t0; 325 326 gen_update_nip(ctx, nip); 327 t0 = tcg_constant_i32(excp); 328 gen_helper_raise_exception(tcg_env, t0); 329 ctx->base.is_jmp = DISAS_NORETURN; 330 } 331 332 static inline void gen_exception(DisasContext *ctx, uint32_t excp) 333 { 334 /* 335 * These are all synchronous exceptions, we set the PC back to the 336 * faulting instruction 337 */ 338 gen_exception_nip(ctx, excp, ctx->cia); 339 } 340 341 #if !defined(CONFIG_USER_ONLY) 342 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 343 { 344 translator_io_start(&ctx->base); 345 gen_helper_ppc_maybe_interrupt(tcg_env); 346 } 347 #endif 348 349 /* 350 * Tells the caller what is the appropriate exception to generate and prepares 351 * SPR registers for this exception. 352 * 353 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 354 * POWERPC_EXCP_DEBUG (on BookE). 355 */ 356 static void gen_debug_exception(DisasContext *ctx, bool rfi_type) 357 { 358 #if !defined(CONFIG_USER_ONLY) 359 if (ctx->flags & POWERPC_FLAG_DE) { 360 target_ulong dbsr = 0; 361 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 362 dbsr = DBCR0_ICMP; 363 } else { 364 /* Must have been branch */ 365 dbsr = DBCR0_BRT; 366 } 367 TCGv t0 = tcg_temp_new(); 368 gen_load_spr(t0, SPR_BOOKE_DBSR); 369 tcg_gen_ori_tl(t0, t0, dbsr); 370 gen_store_spr(SPR_BOOKE_DBSR, t0); 371 gen_helper_raise_exception(tcg_env, 372 tcg_constant_i32(POWERPC_EXCP_DEBUG)); 373 ctx->base.is_jmp = DISAS_NORETURN; 374 } else { 375 if (!rfi_type) { /* BookS does not single step rfi type instructions */ 376 TCGv t0 = tcg_temp_new(); 377 tcg_gen_movi_tl(t0, ctx->cia); 378 gen_helper_book3s_trace(tcg_env, t0); 379 ctx->base.is_jmp = DISAS_NORETURN; 380 } 381 } 382 #endif 383 } 384 385 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 386 { 387 /* Will be converted to program check if needed */ 388 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 389 } 390 391 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 392 { 393 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 394 } 395 396 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 397 { 398 /* Will be converted to program check if needed */ 399 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 400 } 401 402 /*****************************************************************************/ 403 /* SPR READ/WRITE CALLBACKS */ 404 405 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 406 { 407 #if 0 408 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 409 printf("ERROR: try to access SPR %d !\n", sprn); 410 #endif 411 } 412 413 /* #define PPC_DUMP_SPR_ACCESSES */ 414 415 /* 416 * Generic callbacks: 417 * do nothing but store/retrieve spr value 418 */ 419 static void spr_load_dump_spr(int sprn) 420 { 421 #ifdef PPC_DUMP_SPR_ACCESSES 422 TCGv_i32 t0 = tcg_constant_i32(sprn); 423 gen_helper_load_dump_spr(tcg_env, t0); 424 #endif 425 } 426 427 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 428 { 429 gen_load_spr(cpu_gpr[gprn], sprn); 430 spr_load_dump_spr(sprn); 431 } 432 433 static void spr_store_dump_spr(int sprn) 434 { 435 #ifdef PPC_DUMP_SPR_ACCESSES 436 TCGv_i32 t0 = tcg_constant_i32(sprn); 437 gen_helper_store_dump_spr(tcg_env, t0); 438 #endif 439 } 440 441 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 442 { 443 gen_store_spr(sprn, cpu_gpr[gprn]); 444 spr_store_dump_spr(sprn); 445 } 446 447 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 448 { 449 #ifdef TARGET_PPC64 450 TCGv t0 = tcg_temp_new(); 451 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 452 gen_store_spr(sprn, t0); 453 spr_store_dump_spr(sprn); 454 #else 455 spr_write_generic(ctx, sprn, gprn); 456 #endif 457 } 458 459 void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) 460 { 461 if (!(ctx->flags & POWERPC_FLAG_SMT)) { 462 spr_write_generic(ctx, sprn, gprn); 463 return; 464 } 465 466 if (!gen_serialize(ctx)) { 467 return; 468 } 469 470 gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), 471 cpu_gpr[gprn]); 472 spr_store_dump_spr(sprn); 473 } 474 475 static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 476 { 477 /* This does not implement >1 thread */ 478 TCGv t0 = tcg_temp_new(); 479 TCGv t1 = tcg_temp_new(); 480 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 481 tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 482 tcg_gen_or_tl(t1, t1, t0); 483 gen_store_spr(sprn, t1); 484 } 485 486 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 487 { 488 if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { 489 /* CTRL behaves as 1-thread in LPAR-per-thread mode */ 490 spr_write_CTRL_ST(ctx, sprn, gprn); 491 goto out; 492 } 493 494 if (!gen_serialize(ctx)) { 495 return; 496 } 497 498 gen_helper_spr_write_CTRL(tcg_env, tcg_constant_i32(sprn), 499 cpu_gpr[gprn]); 500 out: 501 spr_store_dump_spr(sprn); 502 503 /* 504 * SPR_CTRL writes must force a new translation block, 505 * allowing the PMU to calculate the run latch events with 506 * more accuracy. 507 */ 508 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 509 } 510 511 #if !defined(CONFIG_USER_ONLY) 512 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 513 { 514 TCGv t0 = tcg_temp_new(); 515 TCGv t1 = tcg_temp_new(); 516 gen_load_spr(t0, sprn); 517 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 518 tcg_gen_and_tl(t0, t0, t1); 519 gen_store_spr(sprn, t0); 520 } 521 522 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 523 { 524 } 525 526 #endif 527 528 /* SPR common to all PowerPC */ 529 /* XER */ 530 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 531 { 532 TCGv dst = cpu_gpr[gprn]; 533 TCGv t0 = tcg_temp_new(); 534 TCGv t1 = tcg_temp_new(); 535 TCGv t2 = tcg_temp_new(); 536 tcg_gen_mov_tl(dst, cpu_xer); 537 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 538 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 539 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 540 tcg_gen_or_tl(t0, t0, t1); 541 tcg_gen_or_tl(dst, dst, t2); 542 tcg_gen_or_tl(dst, dst, t0); 543 if (is_isa300(ctx)) { 544 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 545 tcg_gen_or_tl(dst, dst, t0); 546 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 547 tcg_gen_or_tl(dst, dst, t0); 548 } 549 } 550 551 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 552 { 553 TCGv src = cpu_gpr[gprn]; 554 /* Write all flags, while reading back check for isa300 */ 555 tcg_gen_andi_tl(cpu_xer, src, 556 ~((1u << XER_SO) | 557 (1u << XER_OV) | (1u << XER_OV32) | 558 (1u << XER_CA) | (1u << XER_CA32))); 559 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 560 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 561 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 562 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 563 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 564 } 565 566 /* LR */ 567 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 568 { 569 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 570 } 571 572 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 573 { 574 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 575 } 576 577 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 578 /* Debug facilities */ 579 /* CFAR */ 580 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 581 { 582 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 583 } 584 585 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 586 { 587 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 588 } 589 590 /* Breakpoint */ 591 void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn) 592 { 593 translator_io_start(&ctx->base); 594 gen_helper_store_ciabr(tcg_env, cpu_gpr[gprn]); 595 } 596 597 /* Watchpoint */ 598 void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn) 599 { 600 translator_io_start(&ctx->base); 601 gen_helper_store_dawr0(tcg_env, cpu_gpr[gprn]); 602 } 603 604 void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn) 605 { 606 translator_io_start(&ctx->base); 607 gen_helper_store_dawrx0(tcg_env, cpu_gpr[gprn]); 608 } 609 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 610 611 /* CTR */ 612 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 613 { 614 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 615 } 616 617 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 618 { 619 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 620 } 621 622 /* User read access to SPR */ 623 /* USPRx */ 624 /* UMMCRx */ 625 /* UPMCx */ 626 /* USIA */ 627 /* UDECR */ 628 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 629 { 630 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 631 } 632 633 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 634 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 635 { 636 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 637 } 638 #endif 639 640 /* SPR common to all non-embedded PowerPC */ 641 /* DECR */ 642 #if !defined(CONFIG_USER_ONLY) 643 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 644 { 645 translator_io_start(&ctx->base); 646 gen_helper_load_decr(cpu_gpr[gprn], tcg_env); 647 } 648 649 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 650 { 651 translator_io_start(&ctx->base); 652 gen_helper_store_decr(tcg_env, cpu_gpr[gprn]); 653 } 654 #endif 655 656 /* SPR common to all non-embedded PowerPC, except 601 */ 657 /* Time base */ 658 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 659 { 660 translator_io_start(&ctx->base); 661 gen_helper_load_tbl(cpu_gpr[gprn], tcg_env); 662 } 663 664 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 665 { 666 translator_io_start(&ctx->base); 667 gen_helper_load_tbu(cpu_gpr[gprn], tcg_env); 668 } 669 670 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 671 { 672 gen_helper_load_atbl(cpu_gpr[gprn], tcg_env); 673 } 674 675 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 676 { 677 gen_helper_load_atbu(cpu_gpr[gprn], tcg_env); 678 } 679 680 #if !defined(CONFIG_USER_ONLY) 681 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 682 { 683 if (!gen_serialize_core_lpar(ctx)) { 684 return; 685 } 686 687 translator_io_start(&ctx->base); 688 gen_helper_store_tbl(tcg_env, cpu_gpr[gprn]); 689 } 690 691 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 692 { 693 if (!gen_serialize_core_lpar(ctx)) { 694 return; 695 } 696 697 translator_io_start(&ctx->base); 698 gen_helper_store_tbu(tcg_env, cpu_gpr[gprn]); 699 } 700 701 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 702 { 703 gen_helper_store_atbl(tcg_env, cpu_gpr[gprn]); 704 } 705 706 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 707 { 708 gen_helper_store_atbu(tcg_env, cpu_gpr[gprn]); 709 } 710 711 #if defined(TARGET_PPC64) 712 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 713 { 714 translator_io_start(&ctx->base); 715 gen_helper_load_purr(cpu_gpr[gprn], tcg_env); 716 } 717 718 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 719 { 720 if (!gen_serialize_core_lpar(ctx)) { 721 return; 722 } 723 translator_io_start(&ctx->base); 724 gen_helper_store_purr(tcg_env, cpu_gpr[gprn]); 725 } 726 727 /* HDECR */ 728 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 729 { 730 translator_io_start(&ctx->base); 731 gen_helper_load_hdecr(cpu_gpr[gprn], tcg_env); 732 } 733 734 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 735 { 736 if (!gen_serialize_core_lpar(ctx)) { 737 return; 738 } 739 translator_io_start(&ctx->base); 740 gen_helper_store_hdecr(tcg_env, cpu_gpr[gprn]); 741 } 742 743 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 744 { 745 translator_io_start(&ctx->base); 746 gen_helper_load_vtb(cpu_gpr[gprn], tcg_env); 747 } 748 749 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 750 { 751 if (!gen_serialize_core_lpar(ctx)) { 752 return; 753 } 754 translator_io_start(&ctx->base); 755 gen_helper_store_vtb(tcg_env, cpu_gpr[gprn]); 756 } 757 758 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 759 { 760 if (!gen_serialize_core_lpar(ctx)) { 761 return; 762 } 763 translator_io_start(&ctx->base); 764 gen_helper_store_tbu40(tcg_env, cpu_gpr[gprn]); 765 } 766 767 #endif 768 #endif 769 770 #if !defined(CONFIG_USER_ONLY) 771 /* IBAT0U...IBAT0U */ 772 /* IBAT0L...IBAT7L */ 773 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 774 { 775 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 776 offsetof(CPUPPCState, 777 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 778 } 779 780 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 781 { 782 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 783 offsetof(CPUPPCState, 784 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 785 } 786 787 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 788 { 789 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 790 gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); 791 } 792 793 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 794 { 795 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 796 gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); 797 } 798 799 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 800 { 801 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 802 gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); 803 } 804 805 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 806 { 807 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 808 gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); 809 } 810 811 /* DBAT0U...DBAT7U */ 812 /* DBAT0L...DBAT7L */ 813 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 814 { 815 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 816 offsetof(CPUPPCState, 817 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 818 } 819 820 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 821 { 822 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 823 offsetof(CPUPPCState, 824 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 825 } 826 827 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 828 { 829 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 830 gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); 831 } 832 833 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 834 { 835 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 836 gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); 837 } 838 839 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 840 { 841 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 842 gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); 843 } 844 845 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 846 { 847 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 848 gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); 849 } 850 851 /* SDR1 */ 852 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 853 { 854 gen_helper_store_sdr1(tcg_env, cpu_gpr[gprn]); 855 } 856 857 #if defined(TARGET_PPC64) 858 /* 64 bits PowerPC specific SPRs */ 859 /* PIDR */ 860 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 861 { 862 gen_helper_store_pidr(tcg_env, cpu_gpr[gprn]); 863 } 864 865 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 866 { 867 gen_helper_store_lpidr(tcg_env, cpu_gpr[gprn]); 868 } 869 870 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 871 { 872 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, excp_prefix)); 873 } 874 875 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 876 { 877 TCGv t0 = tcg_temp_new(); 878 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 879 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); 880 } 881 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 882 { 883 gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]); 884 } 885 886 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 887 { 888 gen_helper_store_pcr(tcg_env, cpu_gpr[gprn]); 889 } 890 891 /* DPDES */ 892 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 893 { 894 if (!gen_serialize_core_lpar(ctx)) { 895 return; 896 } 897 898 gen_helper_load_dpdes(cpu_gpr[gprn], tcg_env); 899 } 900 901 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 902 { 903 if (!gen_serialize_core_lpar(ctx)) { 904 return; 905 } 906 907 gen_helper_store_dpdes(tcg_env, cpu_gpr[gprn]); 908 } 909 #endif 910 #endif 911 912 /* PowerPC 40x specific registers */ 913 #if !defined(CONFIG_USER_ONLY) 914 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 915 { 916 translator_io_start(&ctx->base); 917 gen_helper_load_40x_pit(cpu_gpr[gprn], tcg_env); 918 } 919 920 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 921 { 922 translator_io_start(&ctx->base); 923 gen_helper_store_40x_pit(tcg_env, cpu_gpr[gprn]); 924 } 925 926 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 927 { 928 translator_io_start(&ctx->base); 929 gen_store_spr(sprn, cpu_gpr[gprn]); 930 gen_helper_store_40x_dbcr0(tcg_env, cpu_gpr[gprn]); 931 /* We must stop translation as we may have rebooted */ 932 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 933 } 934 935 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 936 { 937 translator_io_start(&ctx->base); 938 gen_helper_store_40x_sler(tcg_env, cpu_gpr[gprn]); 939 } 940 941 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 942 { 943 translator_io_start(&ctx->base); 944 gen_helper_store_40x_tcr(tcg_env, cpu_gpr[gprn]); 945 } 946 947 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 948 { 949 translator_io_start(&ctx->base); 950 gen_helper_store_40x_tsr(tcg_env, cpu_gpr[gprn]); 951 } 952 953 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 954 { 955 TCGv t0 = tcg_temp_new(); 956 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 957 gen_helper_store_40x_pid(tcg_env, t0); 958 } 959 960 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 961 { 962 translator_io_start(&ctx->base); 963 gen_helper_store_booke_tcr(tcg_env, cpu_gpr[gprn]); 964 } 965 966 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 967 { 968 translator_io_start(&ctx->base); 969 gen_helper_store_booke_tsr(tcg_env, cpu_gpr[gprn]); 970 } 971 #endif 972 973 /* PIR */ 974 #if !defined(CONFIG_USER_ONLY) 975 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 976 { 977 TCGv t0 = tcg_temp_new(); 978 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 979 gen_store_spr(SPR_PIR, t0); 980 } 981 #endif 982 983 /* SPE specific registers */ 984 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 985 { 986 TCGv_i32 t0 = tcg_temp_new_i32(); 987 tcg_gen_ld_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); 988 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 989 } 990 991 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 992 { 993 TCGv_i32 t0 = tcg_temp_new_i32(); 994 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 995 tcg_gen_st_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); 996 } 997 998 #if !defined(CONFIG_USER_ONLY) 999 /* Callback used to write the exception vector base */ 1000 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 1001 { 1002 TCGv t0 = tcg_temp_new(); 1003 tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivpr_mask)); 1004 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 1005 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); 1006 gen_store_spr(sprn, t0); 1007 } 1008 1009 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 1010 { 1011 int sprn_offs; 1012 1013 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 1014 sprn_offs = sprn - SPR_BOOKE_IVOR0; 1015 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 1016 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 1017 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 1018 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 1019 } else { 1020 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 1021 " vector 0x%03x\n", sprn); 1022 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1023 return; 1024 } 1025 1026 TCGv t0 = tcg_temp_new(); 1027 tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivor_mask)); 1028 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 1029 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 1030 gen_store_spr(sprn, t0); 1031 } 1032 #endif 1033 1034 #ifdef TARGET_PPC64 1035 #ifndef CONFIG_USER_ONLY 1036 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 1037 { 1038 TCGv t0 = tcg_temp_new(); 1039 TCGv t1 = tcg_temp_new(); 1040 TCGv t2 = tcg_temp_new(); 1041 1042 /* 1043 * Note, the HV=1 PR=0 case is handled earlier by simply using 1044 * spr_write_generic for HV mode in the SPR table 1045 */ 1046 1047 /* Build insertion mask into t1 based on context */ 1048 if (ctx->pr) { 1049 gen_load_spr(t1, SPR_UAMOR); 1050 } else { 1051 gen_load_spr(t1, SPR_AMOR); 1052 } 1053 1054 /* Mask new bits into t2 */ 1055 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1056 1057 /* Load AMR and clear new bits in t0 */ 1058 gen_load_spr(t0, SPR_AMR); 1059 tcg_gen_andc_tl(t0, t0, t1); 1060 1061 /* Or'in new bits and write it out */ 1062 tcg_gen_or_tl(t0, t0, t2); 1063 gen_store_spr(SPR_AMR, t0); 1064 spr_store_dump_spr(SPR_AMR); 1065 } 1066 1067 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 1068 { 1069 TCGv t0 = tcg_temp_new(); 1070 TCGv t1 = tcg_temp_new(); 1071 TCGv t2 = tcg_temp_new(); 1072 1073 /* 1074 * Note, the HV=1 case is handled earlier by simply using 1075 * spr_write_generic for HV mode in the SPR table 1076 */ 1077 1078 /* Build insertion mask into t1 based on context */ 1079 gen_load_spr(t1, SPR_AMOR); 1080 1081 /* Mask new bits into t2 */ 1082 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1083 1084 /* Load AMR and clear new bits in t0 */ 1085 gen_load_spr(t0, SPR_UAMOR); 1086 tcg_gen_andc_tl(t0, t0, t1); 1087 1088 /* Or'in new bits and write it out */ 1089 tcg_gen_or_tl(t0, t0, t2); 1090 gen_store_spr(SPR_UAMOR, t0); 1091 spr_store_dump_spr(SPR_UAMOR); 1092 } 1093 1094 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1095 { 1096 TCGv t0 = tcg_temp_new(); 1097 TCGv t1 = tcg_temp_new(); 1098 TCGv t2 = tcg_temp_new(); 1099 1100 /* 1101 * Note, the HV=1 case is handled earlier by simply using 1102 * spr_write_generic for HV mode in the SPR table 1103 */ 1104 1105 /* Build insertion mask into t1 based on context */ 1106 gen_load_spr(t1, SPR_AMOR); 1107 1108 /* Mask new bits into t2 */ 1109 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1110 1111 /* Load AMR and clear new bits in t0 */ 1112 gen_load_spr(t0, SPR_IAMR); 1113 tcg_gen_andc_tl(t0, t0, t1); 1114 1115 /* Or'in new bits and write it out */ 1116 tcg_gen_or_tl(t0, t0, t2); 1117 gen_store_spr(SPR_IAMR, t0); 1118 spr_store_dump_spr(SPR_IAMR); 1119 } 1120 #endif 1121 #endif 1122 1123 #ifndef CONFIG_USER_ONLY 1124 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1125 { 1126 gen_helper_fixup_thrm(tcg_env); 1127 gen_load_spr(cpu_gpr[gprn], sprn); 1128 spr_load_dump_spr(sprn); 1129 } 1130 #endif /* !CONFIG_USER_ONLY */ 1131 1132 #if !defined(CONFIG_USER_ONLY) 1133 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1134 { 1135 TCGv t0 = tcg_temp_new(); 1136 1137 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1138 gen_store_spr(sprn, t0); 1139 } 1140 1141 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1142 { 1143 TCGv t0 = tcg_temp_new(); 1144 1145 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1146 gen_store_spr(sprn, t0); 1147 } 1148 1149 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1150 { 1151 TCGv t0 = tcg_temp_new(); 1152 1153 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1154 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1155 gen_store_spr(sprn, t0); 1156 } 1157 1158 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1159 { 1160 gen_helper_booke206_tlbflush(tcg_env, cpu_gpr[gprn]); 1161 } 1162 1163 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1164 { 1165 TCGv_i32 t0 = tcg_constant_i32(sprn); 1166 gen_helper_booke_setpid(tcg_env, t0, cpu_gpr[gprn]); 1167 } 1168 1169 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1170 { 1171 gen_helper_booke_set_eplc(tcg_env, cpu_gpr[gprn]); 1172 } 1173 1174 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1175 { 1176 gen_helper_booke_set_epsc(tcg_env, cpu_gpr[gprn]); 1177 } 1178 1179 #endif 1180 1181 #if !defined(CONFIG_USER_ONLY) 1182 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1183 { 1184 TCGv val = tcg_temp_new(); 1185 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1186 gen_store_spr(SPR_BOOKE_MAS3, val); 1187 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1188 gen_store_spr(SPR_BOOKE_MAS7, val); 1189 } 1190 1191 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1192 { 1193 TCGv mas7 = tcg_temp_new(); 1194 TCGv mas3 = tcg_temp_new(); 1195 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1196 tcg_gen_shli_tl(mas7, mas7, 32); 1197 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1198 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1199 } 1200 1201 #endif 1202 1203 #ifdef TARGET_PPC64 1204 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1205 int bit, int sprn, int cause) 1206 { 1207 TCGv_i32 t1 = tcg_constant_i32(bit); 1208 TCGv_i32 t2 = tcg_constant_i32(sprn); 1209 TCGv_i32 t3 = tcg_constant_i32(cause); 1210 1211 gen_helper_fscr_facility_check(tcg_env, t1, t2, t3); 1212 } 1213 1214 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1215 int bit, int sprn, int cause) 1216 { 1217 TCGv_i32 t1 = tcg_constant_i32(bit); 1218 TCGv_i32 t2 = tcg_constant_i32(sprn); 1219 TCGv_i32 t3 = tcg_constant_i32(cause); 1220 1221 gen_helper_msr_facility_check(tcg_env, t1, t2, t3); 1222 } 1223 1224 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1225 { 1226 TCGv spr_up = tcg_temp_new(); 1227 TCGv spr = tcg_temp_new(); 1228 1229 gen_load_spr(spr, sprn - 1); 1230 tcg_gen_shri_tl(spr_up, spr, 32); 1231 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1232 } 1233 1234 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1235 { 1236 TCGv spr = tcg_temp_new(); 1237 1238 gen_load_spr(spr, sprn - 1); 1239 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1240 gen_store_spr(sprn - 1, spr); 1241 } 1242 1243 #if !defined(CONFIG_USER_ONLY) 1244 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1245 { 1246 TCGv hmer = tcg_temp_new(); 1247 1248 gen_load_spr(hmer, sprn); 1249 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1250 gen_store_spr(sprn, hmer); 1251 spr_store_dump_spr(sprn); 1252 } 1253 1254 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1255 { 1256 /* Reading TFMR can cause it to be updated, so serialize threads here too */ 1257 if (!gen_serialize_core(ctx)) { 1258 return; 1259 } 1260 gen_helper_load_tfmr(cpu_gpr[gprn], tcg_env); 1261 } 1262 1263 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1264 { 1265 if (!gen_serialize_core(ctx)) { 1266 return; 1267 } 1268 gen_helper_store_tfmr(tcg_env, cpu_gpr[gprn]); 1269 } 1270 1271 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1272 { 1273 translator_io_start(&ctx->base); 1274 gen_helper_store_lpcr(tcg_env, cpu_gpr[gprn]); 1275 } 1276 #endif /* !defined(CONFIG_USER_ONLY) */ 1277 1278 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1279 { 1280 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1281 spr_read_generic(ctx, gprn, sprn); 1282 } 1283 1284 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1285 { 1286 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1287 spr_write_generic(ctx, sprn, gprn); 1288 } 1289 1290 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1291 { 1292 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1293 spr_read_generic(ctx, gprn, sprn); 1294 } 1295 1296 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1297 { 1298 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1299 spr_write_generic(ctx, sprn, gprn); 1300 } 1301 1302 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1303 { 1304 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1305 spr_read_prev_upper32(ctx, gprn, sprn); 1306 } 1307 1308 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1309 { 1310 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1311 spr_write_prev_upper32(ctx, sprn, gprn); 1312 } 1313 1314 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1315 { 1316 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1317 spr_read_generic(ctx, gprn, sprn); 1318 } 1319 1320 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1321 { 1322 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1323 spr_write_generic(ctx, sprn, gprn); 1324 } 1325 1326 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1327 { 1328 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1329 spr_read_prev_upper32(ctx, gprn, sprn); 1330 } 1331 1332 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1333 { 1334 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1335 spr_write_prev_upper32(ctx, sprn, gprn); 1336 } 1337 1338 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1339 { 1340 TCGv t0 = tcg_temp_new(); 1341 1342 /* 1343 * Access to the (H)DEXCR in problem state is done using separated 1344 * SPR indexes which are 16 below the SPR indexes which have full 1345 * access to the (H)DEXCR in privileged state. Problem state can 1346 * only read bits 32:63, bits 0:31 return 0. 1347 * 1348 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1349 */ 1350 1351 gen_load_spr(t0, sprn + 16); 1352 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1353 } 1354 #endif 1355 1356 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1357 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1358 1359 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1360 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1361 1362 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1363 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1364 1365 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1366 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1367 1368 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1369 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1370 1371 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1372 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1373 1374 typedef struct opcode_t { 1375 unsigned char opc1, opc2, opc3, opc4; 1376 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1377 unsigned char pad[4]; 1378 #endif 1379 opc_handler_t handler; 1380 const char *oname; 1381 } opcode_t; 1382 1383 static void gen_priv_opc(DisasContext *ctx) 1384 { 1385 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1386 } 1387 1388 /* Helpers for priv. check */ 1389 #define GEN_PRIV(CTX) \ 1390 do { \ 1391 gen_priv_opc(CTX); return; \ 1392 } while (0) 1393 1394 #if defined(CONFIG_USER_ONLY) 1395 #define CHK_HV(CTX) GEN_PRIV(CTX) 1396 #define CHK_SV(CTX) GEN_PRIV(CTX) 1397 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1398 #else 1399 #define CHK_HV(CTX) \ 1400 do { \ 1401 if (unlikely(ctx->pr || !ctx->hv)) {\ 1402 GEN_PRIV(CTX); \ 1403 } \ 1404 } while (0) 1405 #define CHK_SV(CTX) \ 1406 do { \ 1407 if (unlikely(ctx->pr)) { \ 1408 GEN_PRIV(CTX); \ 1409 } \ 1410 } while (0) 1411 #define CHK_HVRM(CTX) \ 1412 do { \ 1413 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1414 GEN_PRIV(CTX); \ 1415 } \ 1416 } while (0) 1417 #endif 1418 1419 #define CHK_NONE(CTX) 1420 1421 /*****************************************************************************/ 1422 /* PowerPC instructions table */ 1423 1424 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1425 { \ 1426 .opc1 = op1, \ 1427 .opc2 = op2, \ 1428 .opc3 = op3, \ 1429 .opc4 = 0xff, \ 1430 .handler = { \ 1431 .inval1 = invl, \ 1432 .type = _typ, \ 1433 .type2 = _typ2, \ 1434 .handler = &gen_##name, \ 1435 }, \ 1436 .oname = stringify(name), \ 1437 } 1438 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1439 { \ 1440 .opc1 = op1, \ 1441 .opc2 = op2, \ 1442 .opc3 = op3, \ 1443 .opc4 = 0xff, \ 1444 .handler = { \ 1445 .inval1 = invl1, \ 1446 .inval2 = invl2, \ 1447 .type = _typ, \ 1448 .type2 = _typ2, \ 1449 .handler = &gen_##name, \ 1450 }, \ 1451 .oname = stringify(name), \ 1452 } 1453 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1454 { \ 1455 .opc1 = op1, \ 1456 .opc2 = op2, \ 1457 .opc3 = op3, \ 1458 .opc4 = 0xff, \ 1459 .handler = { \ 1460 .inval1 = invl, \ 1461 .type = _typ, \ 1462 .type2 = _typ2, \ 1463 .handler = &gen_##name, \ 1464 }, \ 1465 .oname = onam, \ 1466 } 1467 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1468 { \ 1469 .opc1 = op1, \ 1470 .opc2 = op2, \ 1471 .opc3 = op3, \ 1472 .opc4 = op4, \ 1473 .handler = { \ 1474 .inval1 = invl, \ 1475 .type = _typ, \ 1476 .type2 = _typ2, \ 1477 .handler = &gen_##name, \ 1478 }, \ 1479 .oname = stringify(name), \ 1480 } 1481 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1482 { \ 1483 .opc1 = op1, \ 1484 .opc2 = op2, \ 1485 .opc3 = op3, \ 1486 .opc4 = op4, \ 1487 .handler = { \ 1488 .inval1 = invl, \ 1489 .type = _typ, \ 1490 .type2 = _typ2, \ 1491 .handler = &gen_##name, \ 1492 }, \ 1493 .oname = onam, \ 1494 } 1495 1496 /* Invalid instruction */ 1497 static void gen_invalid(DisasContext *ctx) 1498 { 1499 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1500 } 1501 1502 static opc_handler_t invalid_handler = { 1503 .inval1 = 0xFFFFFFFF, 1504 .inval2 = 0xFFFFFFFF, 1505 .type = PPC_NONE, 1506 .type2 = PPC_NONE, 1507 .handler = gen_invalid, 1508 }; 1509 1510 /*** Integer comparison ***/ 1511 1512 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1513 { 1514 TCGv t0 = tcg_temp_new(); 1515 TCGv t1 = tcg_temp_new(); 1516 TCGv_i32 t = tcg_temp_new_i32(); 1517 1518 tcg_gen_movi_tl(t0, CRF_EQ); 1519 tcg_gen_movi_tl(t1, CRF_LT); 1520 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1521 t0, arg0, arg1, t1, t0); 1522 tcg_gen_movi_tl(t1, CRF_GT); 1523 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1524 t0, arg0, arg1, t1, t0); 1525 1526 tcg_gen_trunc_tl_i32(t, t0); 1527 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1528 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1529 } 1530 1531 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1532 { 1533 TCGv t0 = tcg_constant_tl(arg1); 1534 gen_op_cmp(arg0, t0, s, crf); 1535 } 1536 1537 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1538 { 1539 TCGv t0, t1; 1540 t0 = tcg_temp_new(); 1541 t1 = tcg_temp_new(); 1542 if (s) { 1543 tcg_gen_ext32s_tl(t0, arg0); 1544 tcg_gen_ext32s_tl(t1, arg1); 1545 } else { 1546 tcg_gen_ext32u_tl(t0, arg0); 1547 tcg_gen_ext32u_tl(t1, arg1); 1548 } 1549 gen_op_cmp(t0, t1, s, crf); 1550 } 1551 1552 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1553 { 1554 TCGv t0 = tcg_constant_tl(arg1); 1555 gen_op_cmp32(arg0, t0, s, crf); 1556 } 1557 1558 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1559 { 1560 if (NARROW_MODE(ctx)) { 1561 gen_op_cmpi32(reg, 0, 1, 0); 1562 } else { 1563 gen_op_cmpi(reg, 0, 1, 0); 1564 } 1565 } 1566 1567 /* cmprb - range comparison: isupper, isaplha, islower*/ 1568 static void gen_cmprb(DisasContext *ctx) 1569 { 1570 TCGv_i32 src1 = tcg_temp_new_i32(); 1571 TCGv_i32 src2 = tcg_temp_new_i32(); 1572 TCGv_i32 src2lo = tcg_temp_new_i32(); 1573 TCGv_i32 src2hi = tcg_temp_new_i32(); 1574 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1575 1576 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1577 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1578 1579 tcg_gen_andi_i32(src1, src1, 0xFF); 1580 tcg_gen_ext8u_i32(src2lo, src2); 1581 tcg_gen_shri_i32(src2, src2, 8); 1582 tcg_gen_ext8u_i32(src2hi, src2); 1583 1584 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1585 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1586 tcg_gen_and_i32(crf, src2lo, src2hi); 1587 1588 if (ctx->opcode & 0x00200000) { 1589 tcg_gen_shri_i32(src2, src2, 8); 1590 tcg_gen_ext8u_i32(src2lo, src2); 1591 tcg_gen_shri_i32(src2, src2, 8); 1592 tcg_gen_ext8u_i32(src2hi, src2); 1593 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1594 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1595 tcg_gen_and_i32(src2lo, src2lo, src2hi); 1596 tcg_gen_or_i32(crf, crf, src2lo); 1597 } 1598 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1599 } 1600 1601 #if defined(TARGET_PPC64) 1602 /* cmpeqb */ 1603 static void gen_cmpeqb(DisasContext *ctx) 1604 { 1605 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1606 cpu_gpr[rB(ctx->opcode)]); 1607 } 1608 #endif 1609 1610 /* isel (PowerPC 2.03 specification) */ 1611 static void gen_isel(DisasContext *ctx) 1612 { 1613 uint32_t bi = rC(ctx->opcode); 1614 uint32_t mask = 0x08 >> (bi & 0x03); 1615 TCGv t0 = tcg_temp_new(); 1616 TCGv zr; 1617 1618 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1619 tcg_gen_andi_tl(t0, t0, mask); 1620 1621 zr = tcg_constant_tl(0); 1622 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1623 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1624 cpu_gpr[rB(ctx->opcode)]); 1625 } 1626 1627 /* cmpb: PowerPC 2.05 specification */ 1628 static void gen_cmpb(DisasContext *ctx) 1629 { 1630 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1631 cpu_gpr[rB(ctx->opcode)]); 1632 } 1633 1634 /*** Integer arithmetic ***/ 1635 1636 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1637 TCGv arg1, TCGv arg2, int sub) 1638 { 1639 TCGv t0 = tcg_temp_new(); 1640 1641 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1642 tcg_gen_xor_tl(t0, arg1, arg2); 1643 if (sub) { 1644 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1645 } else { 1646 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1647 } 1648 if (NARROW_MODE(ctx)) { 1649 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1650 if (is_isa300(ctx)) { 1651 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1652 } 1653 } else { 1654 if (is_isa300(ctx)) { 1655 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1656 } 1657 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1658 } 1659 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1660 } 1661 1662 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1663 TCGv res, TCGv arg0, TCGv arg1, 1664 TCGv ca32, int sub) 1665 { 1666 TCGv t0; 1667 1668 if (!is_isa300(ctx)) { 1669 return; 1670 } 1671 1672 t0 = tcg_temp_new(); 1673 if (sub) { 1674 tcg_gen_eqv_tl(t0, arg0, arg1); 1675 } else { 1676 tcg_gen_xor_tl(t0, arg0, arg1); 1677 } 1678 tcg_gen_xor_tl(t0, t0, res); 1679 tcg_gen_extract_tl(ca32, t0, 32, 1); 1680 } 1681 1682 /* Common add function */ 1683 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1684 TCGv arg2, TCGv ca, TCGv ca32, 1685 bool add_ca, bool compute_ca, 1686 bool compute_ov, bool compute_rc0) 1687 { 1688 TCGv t0 = ret; 1689 1690 if (compute_ca || compute_ov) { 1691 t0 = tcg_temp_new(); 1692 } 1693 1694 if (compute_ca) { 1695 if (NARROW_MODE(ctx)) { 1696 /* 1697 * Caution: a non-obvious corner case of the spec is that 1698 * we must produce the *entire* 64-bit addition, but 1699 * produce the carry into bit 32. 1700 */ 1701 TCGv t1 = tcg_temp_new(); 1702 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1703 tcg_gen_add_tl(t0, arg1, arg2); 1704 if (add_ca) { 1705 tcg_gen_add_tl(t0, t0, ca); 1706 } 1707 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1708 tcg_gen_extract_tl(ca, ca, 32, 1); 1709 if (is_isa300(ctx)) { 1710 tcg_gen_mov_tl(ca32, ca); 1711 } 1712 } else { 1713 TCGv zero = tcg_constant_tl(0); 1714 if (add_ca) { 1715 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1716 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1717 } else { 1718 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1719 } 1720 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1721 } 1722 } else { 1723 tcg_gen_add_tl(t0, arg1, arg2); 1724 if (add_ca) { 1725 tcg_gen_add_tl(t0, t0, ca); 1726 } 1727 } 1728 1729 if (compute_ov) { 1730 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1731 } 1732 if (unlikely(compute_rc0)) { 1733 gen_set_Rc0(ctx, t0); 1734 } 1735 1736 if (t0 != ret) { 1737 tcg_gen_mov_tl(ret, t0); 1738 } 1739 } 1740 1741 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1742 TCGv arg2, int sign, int compute_ov) 1743 { 1744 TCGv_i32 t0 = tcg_temp_new_i32(); 1745 TCGv_i32 t1 = tcg_temp_new_i32(); 1746 TCGv_i32 t2 = tcg_temp_new_i32(); 1747 TCGv_i32 t3 = tcg_temp_new_i32(); 1748 1749 tcg_gen_trunc_tl_i32(t0, arg1); 1750 tcg_gen_trunc_tl_i32(t1, arg2); 1751 if (sign) { 1752 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1753 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1754 tcg_gen_and_i32(t2, t2, t3); 1755 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1756 tcg_gen_or_i32(t2, t2, t3); 1757 tcg_gen_movi_i32(t3, 0); 1758 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1759 tcg_gen_div_i32(t3, t0, t1); 1760 tcg_gen_extu_i32_tl(ret, t3); 1761 } else { 1762 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1763 tcg_gen_movi_i32(t3, 0); 1764 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1765 tcg_gen_divu_i32(t3, t0, t1); 1766 tcg_gen_extu_i32_tl(ret, t3); 1767 } 1768 if (compute_ov) { 1769 tcg_gen_extu_i32_tl(cpu_ov, t2); 1770 if (is_isa300(ctx)) { 1771 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1772 } 1773 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1774 } 1775 1776 if (unlikely(Rc(ctx->opcode) != 0)) { 1777 gen_set_Rc0(ctx, ret); 1778 } 1779 } 1780 /* Div functions */ 1781 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1782 static void glue(gen_, name)(DisasContext *ctx) \ 1783 { \ 1784 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1785 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1786 sign, compute_ov); \ 1787 } 1788 /* divwu divwu. divwuo divwuo. */ 1789 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1790 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1791 /* divw divw. divwo divwo. */ 1792 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1793 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1794 1795 /* div[wd]eu[o][.] */ 1796 #define GEN_DIVE(name, hlpr, compute_ov) \ 1797 static void gen_##name(DisasContext *ctx) \ 1798 { \ 1799 TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1800 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], tcg_env, \ 1801 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1802 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1803 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1804 } \ 1805 } 1806 1807 GEN_DIVE(divweu, divweu, 0); 1808 GEN_DIVE(divweuo, divweu, 1); 1809 GEN_DIVE(divwe, divwe, 0); 1810 GEN_DIVE(divweo, divwe, 1); 1811 1812 #if defined(TARGET_PPC64) 1813 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1814 TCGv arg2, int sign, int compute_ov) 1815 { 1816 TCGv_i64 t0 = tcg_temp_new_i64(); 1817 TCGv_i64 t1 = tcg_temp_new_i64(); 1818 TCGv_i64 t2 = tcg_temp_new_i64(); 1819 TCGv_i64 t3 = tcg_temp_new_i64(); 1820 1821 tcg_gen_mov_i64(t0, arg1); 1822 tcg_gen_mov_i64(t1, arg2); 1823 if (sign) { 1824 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1825 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1826 tcg_gen_and_i64(t2, t2, t3); 1827 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1828 tcg_gen_or_i64(t2, t2, t3); 1829 tcg_gen_movi_i64(t3, 0); 1830 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1831 tcg_gen_div_i64(ret, t0, t1); 1832 } else { 1833 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1834 tcg_gen_movi_i64(t3, 0); 1835 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1836 tcg_gen_divu_i64(ret, t0, t1); 1837 } 1838 if (compute_ov) { 1839 tcg_gen_mov_tl(cpu_ov, t2); 1840 if (is_isa300(ctx)) { 1841 tcg_gen_mov_tl(cpu_ov32, t2); 1842 } 1843 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1844 } 1845 1846 if (unlikely(Rc(ctx->opcode) != 0)) { 1847 gen_set_Rc0(ctx, ret); 1848 } 1849 } 1850 1851 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1852 static void glue(gen_, name)(DisasContext *ctx) \ 1853 { \ 1854 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1855 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1856 sign, compute_ov); \ 1857 } 1858 /* divdu divdu. divduo divduo. */ 1859 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1860 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1861 /* divd divd. divdo divdo. */ 1862 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1863 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1864 1865 GEN_DIVE(divdeu, divdeu, 0); 1866 GEN_DIVE(divdeuo, divdeu, 1); 1867 GEN_DIVE(divde, divde, 0); 1868 GEN_DIVE(divdeo, divde, 1); 1869 #endif 1870 1871 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1872 TCGv arg2, int sign) 1873 { 1874 TCGv_i32 t0 = tcg_temp_new_i32(); 1875 TCGv_i32 t1 = tcg_temp_new_i32(); 1876 1877 tcg_gen_trunc_tl_i32(t0, arg1); 1878 tcg_gen_trunc_tl_i32(t1, arg2); 1879 if (sign) { 1880 TCGv_i32 t2 = tcg_temp_new_i32(); 1881 TCGv_i32 t3 = tcg_temp_new_i32(); 1882 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1883 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1884 tcg_gen_and_i32(t2, t2, t3); 1885 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1886 tcg_gen_or_i32(t2, t2, t3); 1887 tcg_gen_movi_i32(t3, 0); 1888 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1889 tcg_gen_rem_i32(t3, t0, t1); 1890 tcg_gen_ext_i32_tl(ret, t3); 1891 } else { 1892 TCGv_i32 t2 = tcg_constant_i32(1); 1893 TCGv_i32 t3 = tcg_constant_i32(0); 1894 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1895 tcg_gen_remu_i32(t0, t0, t1); 1896 tcg_gen_extu_i32_tl(ret, t0); 1897 } 1898 } 1899 1900 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1901 static void glue(gen_, name)(DisasContext *ctx) \ 1902 { \ 1903 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1904 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1905 sign); \ 1906 } 1907 1908 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1909 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1910 1911 #if defined(TARGET_PPC64) 1912 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1913 TCGv arg2, int sign) 1914 { 1915 TCGv_i64 t0 = tcg_temp_new_i64(); 1916 TCGv_i64 t1 = tcg_temp_new_i64(); 1917 1918 tcg_gen_mov_i64(t0, arg1); 1919 tcg_gen_mov_i64(t1, arg2); 1920 if (sign) { 1921 TCGv_i64 t2 = tcg_temp_new_i64(); 1922 TCGv_i64 t3 = tcg_temp_new_i64(); 1923 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1924 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1925 tcg_gen_and_i64(t2, t2, t3); 1926 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1927 tcg_gen_or_i64(t2, t2, t3); 1928 tcg_gen_movi_i64(t3, 0); 1929 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1930 tcg_gen_rem_i64(ret, t0, t1); 1931 } else { 1932 TCGv_i64 t2 = tcg_constant_i64(1); 1933 TCGv_i64 t3 = tcg_constant_i64(0); 1934 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1935 tcg_gen_remu_i64(ret, t0, t1); 1936 } 1937 } 1938 1939 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1940 static void glue(gen_, name)(DisasContext *ctx) \ 1941 { \ 1942 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1943 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1944 sign); \ 1945 } 1946 1947 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1948 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1949 #endif 1950 1951 /* mulhw mulhw. */ 1952 static void gen_mulhw(DisasContext *ctx) 1953 { 1954 TCGv_i32 t0 = tcg_temp_new_i32(); 1955 TCGv_i32 t1 = tcg_temp_new_i32(); 1956 1957 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1958 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1959 tcg_gen_muls2_i32(t0, t1, t0, t1); 1960 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1961 if (unlikely(Rc(ctx->opcode) != 0)) { 1962 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1963 } 1964 } 1965 1966 /* mulhwu mulhwu. */ 1967 static void gen_mulhwu(DisasContext *ctx) 1968 { 1969 TCGv_i32 t0 = tcg_temp_new_i32(); 1970 TCGv_i32 t1 = tcg_temp_new_i32(); 1971 1972 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1973 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1974 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1975 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1976 if (unlikely(Rc(ctx->opcode) != 0)) { 1977 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1978 } 1979 } 1980 1981 /* mullw mullw. */ 1982 static void gen_mullw(DisasContext *ctx) 1983 { 1984 #if defined(TARGET_PPC64) 1985 TCGv_i64 t0, t1; 1986 t0 = tcg_temp_new_i64(); 1987 t1 = tcg_temp_new_i64(); 1988 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1989 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1990 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1991 #else 1992 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1993 cpu_gpr[rB(ctx->opcode)]); 1994 #endif 1995 if (unlikely(Rc(ctx->opcode) != 0)) { 1996 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1997 } 1998 } 1999 2000 /* mullwo mullwo. */ 2001 static void gen_mullwo(DisasContext *ctx) 2002 { 2003 TCGv_i32 t0 = tcg_temp_new_i32(); 2004 TCGv_i32 t1 = tcg_temp_new_i32(); 2005 2006 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2007 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2008 tcg_gen_muls2_i32(t0, t1, t0, t1); 2009 #if defined(TARGET_PPC64) 2010 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2011 #else 2012 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2013 #endif 2014 2015 tcg_gen_sari_i32(t0, t0, 31); 2016 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2017 tcg_gen_extu_i32_tl(cpu_ov, t0); 2018 if (is_isa300(ctx)) { 2019 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2020 } 2021 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2022 2023 if (unlikely(Rc(ctx->opcode) != 0)) { 2024 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2025 } 2026 } 2027 2028 /* mulli */ 2029 static void gen_mulli(DisasContext *ctx) 2030 { 2031 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2032 SIMM(ctx->opcode)); 2033 } 2034 2035 #if defined(TARGET_PPC64) 2036 /* mulhd mulhd. */ 2037 static void gen_mulhd(DisasContext *ctx) 2038 { 2039 TCGv lo = tcg_temp_new(); 2040 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2041 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2042 if (unlikely(Rc(ctx->opcode) != 0)) { 2043 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2044 } 2045 } 2046 2047 /* mulhdu mulhdu. */ 2048 static void gen_mulhdu(DisasContext *ctx) 2049 { 2050 TCGv lo = tcg_temp_new(); 2051 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2052 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2053 if (unlikely(Rc(ctx->opcode) != 0)) { 2054 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2055 } 2056 } 2057 2058 /* mulld mulld. */ 2059 static void gen_mulld(DisasContext *ctx) 2060 { 2061 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2062 cpu_gpr[rB(ctx->opcode)]); 2063 if (unlikely(Rc(ctx->opcode) != 0)) { 2064 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2065 } 2066 } 2067 2068 /* mulldo mulldo. */ 2069 static void gen_mulldo(DisasContext *ctx) 2070 { 2071 TCGv_i64 t0 = tcg_temp_new_i64(); 2072 TCGv_i64 t1 = tcg_temp_new_i64(); 2073 2074 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2075 cpu_gpr[rB(ctx->opcode)]); 2076 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2077 2078 tcg_gen_sari_i64(t0, t0, 63); 2079 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 2080 if (is_isa300(ctx)) { 2081 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2082 } 2083 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2084 2085 if (unlikely(Rc(ctx->opcode) != 0)) { 2086 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2087 } 2088 } 2089 #endif 2090 2091 /* Common subf function */ 2092 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2093 TCGv arg2, bool add_ca, bool compute_ca, 2094 bool compute_ov, bool compute_rc0) 2095 { 2096 TCGv t0 = ret; 2097 2098 if (compute_ca || compute_ov) { 2099 t0 = tcg_temp_new(); 2100 } 2101 2102 if (compute_ca) { 2103 /* dest = ~arg1 + arg2 [+ ca]. */ 2104 if (NARROW_MODE(ctx)) { 2105 /* 2106 * Caution: a non-obvious corner case of the spec is that 2107 * we must produce the *entire* 64-bit addition, but 2108 * produce the carry into bit 32. 2109 */ 2110 TCGv inv1 = tcg_temp_new(); 2111 TCGv t1 = tcg_temp_new(); 2112 tcg_gen_not_tl(inv1, arg1); 2113 if (add_ca) { 2114 tcg_gen_add_tl(t0, arg2, cpu_ca); 2115 } else { 2116 tcg_gen_addi_tl(t0, arg2, 1); 2117 } 2118 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2119 tcg_gen_add_tl(t0, t0, inv1); 2120 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2121 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 2122 if (is_isa300(ctx)) { 2123 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2124 } 2125 } else if (add_ca) { 2126 TCGv zero, inv1 = tcg_temp_new(); 2127 tcg_gen_not_tl(inv1, arg1); 2128 zero = tcg_constant_tl(0); 2129 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2130 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 2131 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2132 } else { 2133 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2134 tcg_gen_sub_tl(t0, arg2, arg1); 2135 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2136 } 2137 } else if (add_ca) { 2138 /* 2139 * Since we're ignoring carry-out, we can simplify the 2140 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2141 */ 2142 tcg_gen_sub_tl(t0, arg2, arg1); 2143 tcg_gen_add_tl(t0, t0, cpu_ca); 2144 tcg_gen_subi_tl(t0, t0, 1); 2145 } else { 2146 tcg_gen_sub_tl(t0, arg2, arg1); 2147 } 2148 2149 if (compute_ov) { 2150 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2151 } 2152 if (unlikely(compute_rc0)) { 2153 gen_set_Rc0(ctx, t0); 2154 } 2155 2156 if (t0 != ret) { 2157 tcg_gen_mov_tl(ret, t0); 2158 } 2159 } 2160 2161 /* neg neg. nego nego. */ 2162 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2163 { 2164 TCGv zero = tcg_constant_tl(0); 2165 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2166 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2167 } 2168 2169 static void gen_neg(DisasContext *ctx) 2170 { 2171 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2172 if (unlikely(Rc(ctx->opcode))) { 2173 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2174 } 2175 } 2176 2177 static void gen_nego(DisasContext *ctx) 2178 { 2179 gen_op_arith_neg(ctx, 1); 2180 } 2181 2182 /*** Integer logical ***/ 2183 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2184 static void glue(gen_, name)(DisasContext *ctx) \ 2185 { \ 2186 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2187 cpu_gpr[rB(ctx->opcode)]); \ 2188 if (unlikely(Rc(ctx->opcode) != 0)) \ 2189 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2190 } 2191 2192 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2193 static void glue(gen_, name)(DisasContext *ctx) \ 2194 { \ 2195 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2196 if (unlikely(Rc(ctx->opcode) != 0)) \ 2197 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2198 } 2199 2200 /* and & and. */ 2201 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2202 /* andc & andc. */ 2203 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2204 2205 /* andi. */ 2206 static void gen_andi_(DisasContext *ctx) 2207 { 2208 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2209 UIMM(ctx->opcode)); 2210 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2211 } 2212 2213 /* andis. */ 2214 static void gen_andis_(DisasContext *ctx) 2215 { 2216 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2217 UIMM(ctx->opcode) << 16); 2218 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2219 } 2220 2221 /* cntlzw */ 2222 static void gen_cntlzw(DisasContext *ctx) 2223 { 2224 TCGv_i32 t = tcg_temp_new_i32(); 2225 2226 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2227 tcg_gen_clzi_i32(t, t, 32); 2228 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2229 2230 if (unlikely(Rc(ctx->opcode) != 0)) { 2231 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2232 } 2233 } 2234 2235 /* cnttzw */ 2236 static void gen_cnttzw(DisasContext *ctx) 2237 { 2238 TCGv_i32 t = tcg_temp_new_i32(); 2239 2240 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2241 tcg_gen_ctzi_i32(t, t, 32); 2242 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2243 2244 if (unlikely(Rc(ctx->opcode) != 0)) { 2245 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2246 } 2247 } 2248 2249 /* eqv & eqv. */ 2250 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2251 /* extsb & extsb. */ 2252 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2253 /* extsh & extsh. */ 2254 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2255 /* nand & nand. */ 2256 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2257 /* nor & nor. */ 2258 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2259 2260 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2261 static void gen_pause(DisasContext *ctx) 2262 { 2263 TCGv_i32 t0 = tcg_constant_i32(0); 2264 tcg_gen_st_i32(t0, tcg_env, 2265 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2266 2267 /* Stop translation, this gives other CPUs a chance to run */ 2268 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2269 } 2270 #endif /* defined(TARGET_PPC64) */ 2271 2272 /* or & or. */ 2273 static void gen_or(DisasContext *ctx) 2274 { 2275 int rs, ra, rb; 2276 2277 rs = rS(ctx->opcode); 2278 ra = rA(ctx->opcode); 2279 rb = rB(ctx->opcode); 2280 /* Optimisation for mr. ri case */ 2281 if (rs != ra || rs != rb) { 2282 if (rs != rb) { 2283 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2284 } else { 2285 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2286 } 2287 if (unlikely(Rc(ctx->opcode) != 0)) { 2288 gen_set_Rc0(ctx, cpu_gpr[ra]); 2289 } 2290 } else if (unlikely(Rc(ctx->opcode) != 0)) { 2291 gen_set_Rc0(ctx, cpu_gpr[rs]); 2292 #if defined(TARGET_PPC64) 2293 } else if (rs != 0) { /* 0 is nop */ 2294 int prio = 0; 2295 2296 switch (rs) { 2297 case 1: 2298 /* Set process priority to low */ 2299 prio = 2; 2300 break; 2301 case 6: 2302 /* Set process priority to medium-low */ 2303 prio = 3; 2304 break; 2305 case 2: 2306 /* Set process priority to normal */ 2307 prio = 4; 2308 break; 2309 #if !defined(CONFIG_USER_ONLY) 2310 case 31: 2311 if (!ctx->pr) { 2312 /* Set process priority to very low */ 2313 prio = 1; 2314 } 2315 break; 2316 case 5: 2317 if (!ctx->pr) { 2318 /* Set process priority to medium-hight */ 2319 prio = 5; 2320 } 2321 break; 2322 case 3: 2323 if (!ctx->pr) { 2324 /* Set process priority to high */ 2325 prio = 6; 2326 } 2327 break; 2328 case 7: 2329 if (ctx->hv && !ctx->pr) { 2330 /* Set process priority to very high */ 2331 prio = 7; 2332 } 2333 break; 2334 #endif 2335 default: 2336 break; 2337 } 2338 if (prio) { 2339 TCGv t0 = tcg_temp_new(); 2340 gen_load_spr(t0, SPR_PPR); 2341 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2342 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2343 gen_store_spr(SPR_PPR, t0); 2344 } 2345 #if !defined(CONFIG_USER_ONLY) 2346 /* 2347 * Pause out of TCG otherwise spin loops with smt_low eat too 2348 * much CPU and the kernel hangs. This applies to all 2349 * encodings other than no-op, e.g., miso(rs=26), yield(27), 2350 * mdoio(29), mdoom(30), and all currently undefined. 2351 */ 2352 gen_pause(ctx); 2353 #endif 2354 #endif 2355 } 2356 } 2357 /* orc & orc. */ 2358 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2359 2360 /* xor & xor. */ 2361 static void gen_xor(DisasContext *ctx) 2362 { 2363 /* Optimisation for "set to zero" case */ 2364 if (rS(ctx->opcode) != rB(ctx->opcode)) { 2365 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2366 cpu_gpr[rB(ctx->opcode)]); 2367 } else { 2368 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2369 } 2370 if (unlikely(Rc(ctx->opcode) != 0)) { 2371 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2372 } 2373 } 2374 2375 /* ori */ 2376 static void gen_ori(DisasContext *ctx) 2377 { 2378 target_ulong uimm = UIMM(ctx->opcode); 2379 2380 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2381 return; 2382 } 2383 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2384 } 2385 2386 /* oris */ 2387 static void gen_oris(DisasContext *ctx) 2388 { 2389 target_ulong uimm = UIMM(ctx->opcode); 2390 2391 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2392 /* NOP */ 2393 return; 2394 } 2395 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2396 uimm << 16); 2397 } 2398 2399 /* xori */ 2400 static void gen_xori(DisasContext *ctx) 2401 { 2402 target_ulong uimm = UIMM(ctx->opcode); 2403 2404 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2405 /* NOP */ 2406 return; 2407 } 2408 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2409 } 2410 2411 /* xoris */ 2412 static void gen_xoris(DisasContext *ctx) 2413 { 2414 target_ulong uimm = UIMM(ctx->opcode); 2415 2416 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2417 /* NOP */ 2418 return; 2419 } 2420 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2421 uimm << 16); 2422 } 2423 2424 /* popcntb : PowerPC 2.03 specification */ 2425 static void gen_popcntb(DisasContext *ctx) 2426 { 2427 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2428 } 2429 2430 static void gen_popcntw(DisasContext *ctx) 2431 { 2432 #if defined(TARGET_PPC64) 2433 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2434 #else 2435 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2436 #endif 2437 } 2438 2439 #if defined(TARGET_PPC64) 2440 /* popcntd: PowerPC 2.06 specification */ 2441 static void gen_popcntd(DisasContext *ctx) 2442 { 2443 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2444 } 2445 #endif 2446 2447 /* prtyw: PowerPC 2.05 specification */ 2448 static void gen_prtyw(DisasContext *ctx) 2449 { 2450 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2451 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2452 TCGv t0 = tcg_temp_new(); 2453 tcg_gen_shri_tl(t0, rs, 16); 2454 tcg_gen_xor_tl(ra, rs, t0); 2455 tcg_gen_shri_tl(t0, ra, 8); 2456 tcg_gen_xor_tl(ra, ra, t0); 2457 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2458 } 2459 2460 #if defined(TARGET_PPC64) 2461 /* prtyd: PowerPC 2.05 specification */ 2462 static void gen_prtyd(DisasContext *ctx) 2463 { 2464 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2465 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2466 TCGv t0 = tcg_temp_new(); 2467 tcg_gen_shri_tl(t0, rs, 32); 2468 tcg_gen_xor_tl(ra, rs, t0); 2469 tcg_gen_shri_tl(t0, ra, 16); 2470 tcg_gen_xor_tl(ra, ra, t0); 2471 tcg_gen_shri_tl(t0, ra, 8); 2472 tcg_gen_xor_tl(ra, ra, t0); 2473 tcg_gen_andi_tl(ra, ra, 1); 2474 } 2475 #endif 2476 2477 #if defined(TARGET_PPC64) 2478 /* bpermd */ 2479 static void gen_bpermd(DisasContext *ctx) 2480 { 2481 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2482 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2483 } 2484 #endif 2485 2486 #if defined(TARGET_PPC64) 2487 /* extsw & extsw. */ 2488 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2489 2490 /* cntlzd */ 2491 static void gen_cntlzd(DisasContext *ctx) 2492 { 2493 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2494 if (unlikely(Rc(ctx->opcode) != 0)) { 2495 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2496 } 2497 } 2498 2499 /* cnttzd */ 2500 static void gen_cnttzd(DisasContext *ctx) 2501 { 2502 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2503 if (unlikely(Rc(ctx->opcode) != 0)) { 2504 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2505 } 2506 } 2507 2508 /* darn */ 2509 static void gen_darn(DisasContext *ctx) 2510 { 2511 int l = L(ctx->opcode); 2512 2513 if (l > 2) { 2514 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 2515 } else { 2516 translator_io_start(&ctx->base); 2517 if (l == 0) { 2518 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 2519 } else { 2520 /* Return 64-bit random for both CRN and RRN */ 2521 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 2522 } 2523 } 2524 } 2525 #endif 2526 2527 /*** Integer rotate ***/ 2528 2529 /* rlwimi & rlwimi. */ 2530 static void gen_rlwimi(DisasContext *ctx) 2531 { 2532 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2533 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2534 uint32_t sh = SH(ctx->opcode); 2535 uint32_t mb = MB(ctx->opcode); 2536 uint32_t me = ME(ctx->opcode); 2537 2538 if (sh == (31 - me) && mb <= me) { 2539 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2540 } else { 2541 target_ulong mask; 2542 bool mask_in_32b = true; 2543 TCGv t1; 2544 2545 #if defined(TARGET_PPC64) 2546 mb += 32; 2547 me += 32; 2548 #endif 2549 mask = MASK(mb, me); 2550 2551 #if defined(TARGET_PPC64) 2552 if (mask > 0xffffffffu) { 2553 mask_in_32b = false; 2554 } 2555 #endif 2556 t1 = tcg_temp_new(); 2557 if (mask_in_32b) { 2558 TCGv_i32 t0 = tcg_temp_new_i32(); 2559 tcg_gen_trunc_tl_i32(t0, t_rs); 2560 tcg_gen_rotli_i32(t0, t0, sh); 2561 tcg_gen_extu_i32_tl(t1, t0); 2562 } else { 2563 #if defined(TARGET_PPC64) 2564 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2565 tcg_gen_rotli_i64(t1, t1, sh); 2566 #else 2567 g_assert_not_reached(); 2568 #endif 2569 } 2570 2571 tcg_gen_andi_tl(t1, t1, mask); 2572 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2573 tcg_gen_or_tl(t_ra, t_ra, t1); 2574 } 2575 if (unlikely(Rc(ctx->opcode) != 0)) { 2576 gen_set_Rc0(ctx, t_ra); 2577 } 2578 } 2579 2580 /* rlwinm & rlwinm. */ 2581 static void gen_rlwinm(DisasContext *ctx) 2582 { 2583 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2584 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2585 int sh = SH(ctx->opcode); 2586 int mb = MB(ctx->opcode); 2587 int me = ME(ctx->opcode); 2588 int len = me - mb + 1; 2589 int rsh = (32 - sh) & 31; 2590 2591 if (sh != 0 && len > 0 && me == (31 - sh)) { 2592 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2593 } else if (me == 31 && rsh + len <= 32) { 2594 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2595 } else { 2596 target_ulong mask; 2597 bool mask_in_32b = true; 2598 #if defined(TARGET_PPC64) 2599 mb += 32; 2600 me += 32; 2601 #endif 2602 mask = MASK(mb, me); 2603 #if defined(TARGET_PPC64) 2604 if (mask > 0xffffffffu) { 2605 mask_in_32b = false; 2606 } 2607 #endif 2608 if (mask_in_32b) { 2609 if (sh == 0) { 2610 tcg_gen_andi_tl(t_ra, t_rs, mask); 2611 } else { 2612 TCGv_i32 t0 = tcg_temp_new_i32(); 2613 tcg_gen_trunc_tl_i32(t0, t_rs); 2614 tcg_gen_rotli_i32(t0, t0, sh); 2615 tcg_gen_andi_i32(t0, t0, mask); 2616 tcg_gen_extu_i32_tl(t_ra, t0); 2617 } 2618 } else { 2619 #if defined(TARGET_PPC64) 2620 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2621 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2622 tcg_gen_andi_i64(t_ra, t_ra, mask); 2623 #else 2624 g_assert_not_reached(); 2625 #endif 2626 } 2627 } 2628 if (unlikely(Rc(ctx->opcode) != 0)) { 2629 gen_set_Rc0(ctx, t_ra); 2630 } 2631 } 2632 2633 /* rlwnm & rlwnm. */ 2634 static void gen_rlwnm(DisasContext *ctx) 2635 { 2636 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2637 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2638 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2639 uint32_t mb = MB(ctx->opcode); 2640 uint32_t me = ME(ctx->opcode); 2641 target_ulong mask; 2642 bool mask_in_32b = true; 2643 2644 #if defined(TARGET_PPC64) 2645 mb += 32; 2646 me += 32; 2647 #endif 2648 mask = MASK(mb, me); 2649 2650 #if defined(TARGET_PPC64) 2651 if (mask > 0xffffffffu) { 2652 mask_in_32b = false; 2653 } 2654 #endif 2655 if (mask_in_32b) { 2656 TCGv_i32 t0 = tcg_temp_new_i32(); 2657 TCGv_i32 t1 = tcg_temp_new_i32(); 2658 tcg_gen_trunc_tl_i32(t0, t_rb); 2659 tcg_gen_trunc_tl_i32(t1, t_rs); 2660 tcg_gen_andi_i32(t0, t0, 0x1f); 2661 tcg_gen_rotl_i32(t1, t1, t0); 2662 tcg_gen_extu_i32_tl(t_ra, t1); 2663 } else { 2664 #if defined(TARGET_PPC64) 2665 TCGv_i64 t0 = tcg_temp_new_i64(); 2666 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2667 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2668 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2669 #else 2670 g_assert_not_reached(); 2671 #endif 2672 } 2673 2674 tcg_gen_andi_tl(t_ra, t_ra, mask); 2675 2676 if (unlikely(Rc(ctx->opcode) != 0)) { 2677 gen_set_Rc0(ctx, t_ra); 2678 } 2679 } 2680 2681 #if defined(TARGET_PPC64) 2682 #define GEN_PPC64_R2(name, opc1, opc2) \ 2683 static void glue(gen_, name##0)(DisasContext *ctx) \ 2684 { \ 2685 gen_##name(ctx, 0); \ 2686 } \ 2687 \ 2688 static void glue(gen_, name##1)(DisasContext *ctx) \ 2689 { \ 2690 gen_##name(ctx, 1); \ 2691 } 2692 #define GEN_PPC64_R4(name, opc1, opc2) \ 2693 static void glue(gen_, name##0)(DisasContext *ctx) \ 2694 { \ 2695 gen_##name(ctx, 0, 0); \ 2696 } \ 2697 \ 2698 static void glue(gen_, name##1)(DisasContext *ctx) \ 2699 { \ 2700 gen_##name(ctx, 0, 1); \ 2701 } \ 2702 \ 2703 static void glue(gen_, name##2)(DisasContext *ctx) \ 2704 { \ 2705 gen_##name(ctx, 1, 0); \ 2706 } \ 2707 \ 2708 static void glue(gen_, name##3)(DisasContext *ctx) \ 2709 { \ 2710 gen_##name(ctx, 1, 1); \ 2711 } 2712 2713 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2714 { 2715 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2716 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2717 int len = me - mb + 1; 2718 int rsh = (64 - sh) & 63; 2719 2720 if (sh != 0 && len > 0 && me == (63 - sh)) { 2721 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2722 } else if (me == 63 && rsh + len <= 64) { 2723 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2724 } else { 2725 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2726 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2727 } 2728 if (unlikely(Rc(ctx->opcode) != 0)) { 2729 gen_set_Rc0(ctx, t_ra); 2730 } 2731 } 2732 2733 /* rldicl - rldicl. */ 2734 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2735 { 2736 uint32_t sh, mb; 2737 2738 sh = SH(ctx->opcode) | (shn << 5); 2739 mb = MB(ctx->opcode) | (mbn << 5); 2740 gen_rldinm(ctx, mb, 63, sh); 2741 } 2742 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2743 2744 /* rldicr - rldicr. */ 2745 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2746 { 2747 uint32_t sh, me; 2748 2749 sh = SH(ctx->opcode) | (shn << 5); 2750 me = MB(ctx->opcode) | (men << 5); 2751 gen_rldinm(ctx, 0, me, sh); 2752 } 2753 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2754 2755 /* rldic - rldic. */ 2756 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2757 { 2758 uint32_t sh, mb; 2759 2760 sh = SH(ctx->opcode) | (shn << 5); 2761 mb = MB(ctx->opcode) | (mbn << 5); 2762 gen_rldinm(ctx, mb, 63 - sh, sh); 2763 } 2764 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2765 2766 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2767 { 2768 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2769 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2770 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2771 TCGv t0; 2772 2773 t0 = tcg_temp_new(); 2774 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2775 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2776 2777 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2778 if (unlikely(Rc(ctx->opcode) != 0)) { 2779 gen_set_Rc0(ctx, t_ra); 2780 } 2781 } 2782 2783 /* rldcl - rldcl. */ 2784 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2785 { 2786 uint32_t mb; 2787 2788 mb = MB(ctx->opcode) | (mbn << 5); 2789 gen_rldnm(ctx, mb, 63); 2790 } 2791 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2792 2793 /* rldcr - rldcr. */ 2794 static inline void gen_rldcr(DisasContext *ctx, int men) 2795 { 2796 uint32_t me; 2797 2798 me = MB(ctx->opcode) | (men << 5); 2799 gen_rldnm(ctx, 0, me); 2800 } 2801 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2802 2803 /* rldimi - rldimi. */ 2804 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2805 { 2806 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2807 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2808 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2809 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2810 uint32_t me = 63 - sh; 2811 2812 if (mb <= me) { 2813 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2814 } else { 2815 target_ulong mask = MASK(mb, me); 2816 TCGv t1 = tcg_temp_new(); 2817 2818 tcg_gen_rotli_tl(t1, t_rs, sh); 2819 tcg_gen_andi_tl(t1, t1, mask); 2820 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2821 tcg_gen_or_tl(t_ra, t_ra, t1); 2822 } 2823 if (unlikely(Rc(ctx->opcode) != 0)) { 2824 gen_set_Rc0(ctx, t_ra); 2825 } 2826 } 2827 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2828 #endif 2829 2830 /*** Integer shift ***/ 2831 2832 /* slw & slw. */ 2833 static void gen_slw(DisasContext *ctx) 2834 { 2835 TCGv t0, t1; 2836 2837 t0 = tcg_temp_new(); 2838 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2839 #if defined(TARGET_PPC64) 2840 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2841 tcg_gen_sari_tl(t0, t0, 0x3f); 2842 #else 2843 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2844 tcg_gen_sari_tl(t0, t0, 0x1f); 2845 #endif 2846 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2847 t1 = tcg_temp_new(); 2848 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2849 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2850 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2851 if (unlikely(Rc(ctx->opcode) != 0)) { 2852 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2853 } 2854 } 2855 2856 /* sraw & sraw. */ 2857 static void gen_sraw(DisasContext *ctx) 2858 { 2859 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env, 2860 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2861 if (unlikely(Rc(ctx->opcode) != 0)) { 2862 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2863 } 2864 } 2865 2866 /* srawi & srawi. */ 2867 static void gen_srawi(DisasContext *ctx) 2868 { 2869 int sh = SH(ctx->opcode); 2870 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2871 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2872 if (sh == 0) { 2873 tcg_gen_ext32s_tl(dst, src); 2874 tcg_gen_movi_tl(cpu_ca, 0); 2875 if (is_isa300(ctx)) { 2876 tcg_gen_movi_tl(cpu_ca32, 0); 2877 } 2878 } else { 2879 TCGv t0; 2880 tcg_gen_ext32s_tl(dst, src); 2881 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2882 t0 = tcg_temp_new(); 2883 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2884 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2885 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2886 if (is_isa300(ctx)) { 2887 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2888 } 2889 tcg_gen_sari_tl(dst, dst, sh); 2890 } 2891 if (unlikely(Rc(ctx->opcode) != 0)) { 2892 gen_set_Rc0(ctx, dst); 2893 } 2894 } 2895 2896 /* srw & srw. */ 2897 static void gen_srw(DisasContext *ctx) 2898 { 2899 TCGv t0, t1; 2900 2901 t0 = tcg_temp_new(); 2902 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2903 #if defined(TARGET_PPC64) 2904 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2905 tcg_gen_sari_tl(t0, t0, 0x3f); 2906 #else 2907 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2908 tcg_gen_sari_tl(t0, t0, 0x1f); 2909 #endif 2910 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2911 tcg_gen_ext32u_tl(t0, t0); 2912 t1 = tcg_temp_new(); 2913 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2914 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2915 if (unlikely(Rc(ctx->opcode) != 0)) { 2916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2917 } 2918 } 2919 2920 #if defined(TARGET_PPC64) 2921 /* sld & sld. */ 2922 static void gen_sld(DisasContext *ctx) 2923 { 2924 TCGv t0, t1; 2925 2926 t0 = tcg_temp_new(); 2927 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2928 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2929 tcg_gen_sari_tl(t0, t0, 0x3f); 2930 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2931 t1 = tcg_temp_new(); 2932 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2933 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2934 if (unlikely(Rc(ctx->opcode) != 0)) { 2935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2936 } 2937 } 2938 2939 /* srad & srad. */ 2940 static void gen_srad(DisasContext *ctx) 2941 { 2942 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env, 2943 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2944 if (unlikely(Rc(ctx->opcode) != 0)) { 2945 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2946 } 2947 } 2948 /* sradi & sradi. */ 2949 static inline void gen_sradi(DisasContext *ctx, int n) 2950 { 2951 int sh = SH(ctx->opcode) + (n << 5); 2952 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2953 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2954 if (sh == 0) { 2955 tcg_gen_mov_tl(dst, src); 2956 tcg_gen_movi_tl(cpu_ca, 0); 2957 if (is_isa300(ctx)) { 2958 tcg_gen_movi_tl(cpu_ca32, 0); 2959 } 2960 } else { 2961 TCGv t0; 2962 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2963 t0 = tcg_temp_new(); 2964 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2965 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2966 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2967 if (is_isa300(ctx)) { 2968 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2969 } 2970 tcg_gen_sari_tl(dst, src, sh); 2971 } 2972 if (unlikely(Rc(ctx->opcode) != 0)) { 2973 gen_set_Rc0(ctx, dst); 2974 } 2975 } 2976 2977 static void gen_sradi0(DisasContext *ctx) 2978 { 2979 gen_sradi(ctx, 0); 2980 } 2981 2982 static void gen_sradi1(DisasContext *ctx) 2983 { 2984 gen_sradi(ctx, 1); 2985 } 2986 2987 /* extswsli & extswsli. */ 2988 static inline void gen_extswsli(DisasContext *ctx, int n) 2989 { 2990 int sh = SH(ctx->opcode) + (n << 5); 2991 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2992 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2993 2994 tcg_gen_ext32s_tl(dst, src); 2995 tcg_gen_shli_tl(dst, dst, sh); 2996 if (unlikely(Rc(ctx->opcode) != 0)) { 2997 gen_set_Rc0(ctx, dst); 2998 } 2999 } 3000 3001 static void gen_extswsli0(DisasContext *ctx) 3002 { 3003 gen_extswsli(ctx, 0); 3004 } 3005 3006 static void gen_extswsli1(DisasContext *ctx) 3007 { 3008 gen_extswsli(ctx, 1); 3009 } 3010 3011 /* srd & srd. */ 3012 static void gen_srd(DisasContext *ctx) 3013 { 3014 TCGv t0, t1; 3015 3016 t0 = tcg_temp_new(); 3017 /* AND rS with a mask that is 0 when rB >= 0x40 */ 3018 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3019 tcg_gen_sari_tl(t0, t0, 0x3f); 3020 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3021 t1 = tcg_temp_new(); 3022 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3023 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3024 if (unlikely(Rc(ctx->opcode) != 0)) { 3025 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3026 } 3027 } 3028 #endif 3029 3030 /*** Addressing modes ***/ 3031 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3032 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3033 target_long maskl) 3034 { 3035 target_long simm = SIMM(ctx->opcode); 3036 3037 simm &= ~maskl; 3038 if (rA(ctx->opcode) == 0) { 3039 if (NARROW_MODE(ctx)) { 3040 simm = (uint32_t)simm; 3041 } 3042 tcg_gen_movi_tl(EA, simm); 3043 } else if (likely(simm != 0)) { 3044 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3045 if (NARROW_MODE(ctx)) { 3046 tcg_gen_ext32u_tl(EA, EA); 3047 } 3048 } else { 3049 if (NARROW_MODE(ctx)) { 3050 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3051 } else { 3052 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3053 } 3054 } 3055 } 3056 3057 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3058 { 3059 if (rA(ctx->opcode) == 0) { 3060 if (NARROW_MODE(ctx)) { 3061 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3062 } else { 3063 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3064 } 3065 } else { 3066 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3067 if (NARROW_MODE(ctx)) { 3068 tcg_gen_ext32u_tl(EA, EA); 3069 } 3070 } 3071 } 3072 3073 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3074 { 3075 if (rA(ctx->opcode) == 0) { 3076 tcg_gen_movi_tl(EA, 0); 3077 } else if (NARROW_MODE(ctx)) { 3078 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3079 } else { 3080 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3081 } 3082 } 3083 3084 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3085 target_long val) 3086 { 3087 tcg_gen_addi_tl(ret, arg1, val); 3088 if (NARROW_MODE(ctx)) { 3089 tcg_gen_ext32u_tl(ret, ret); 3090 } 3091 } 3092 3093 static inline void gen_align_no_le(DisasContext *ctx) 3094 { 3095 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3096 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3097 } 3098 3099 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3100 { 3101 TCGv ea = tcg_temp_new(); 3102 if (ra) { 3103 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3104 } else { 3105 tcg_gen_mov_tl(ea, displ); 3106 } 3107 if (NARROW_MODE(ctx)) { 3108 tcg_gen_ext32u_tl(ea, ea); 3109 } 3110 return ea; 3111 } 3112 3113 /*** Integer load ***/ 3114 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3115 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3116 3117 #define GEN_QEMU_LOAD_TL(ldop, op) \ 3118 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3119 TCGv val, \ 3120 TCGv addr) \ 3121 { \ 3122 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3123 } 3124 3125 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3126 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3127 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3128 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3129 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3130 3131 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3132 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3133 3134 #define GEN_QEMU_LOAD_64(ldop, op) \ 3135 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3136 TCGv_i64 val, \ 3137 TCGv addr) \ 3138 { \ 3139 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3140 } 3141 3142 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3143 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3144 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3145 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3146 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3147 3148 #if defined(TARGET_PPC64) 3149 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3150 #endif 3151 3152 #define GEN_QEMU_STORE_TL(stop, op) \ 3153 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3154 TCGv val, \ 3155 TCGv addr) \ 3156 { \ 3157 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3158 } 3159 3160 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3161 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3162 #endif 3163 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3164 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3165 3166 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3167 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3168 3169 #define GEN_QEMU_STORE_64(stop, op) \ 3170 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3171 TCGv_i64 val, \ 3172 TCGv addr) \ 3173 { \ 3174 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3175 } 3176 3177 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3178 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3179 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3180 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3181 3182 #if defined(TARGET_PPC64) 3183 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3184 #endif 3185 3186 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3187 static void glue(gen_, name##x)(DisasContext *ctx) \ 3188 { \ 3189 TCGv EA; \ 3190 chk(ctx); \ 3191 gen_set_access_type(ctx, ACCESS_INT); \ 3192 EA = tcg_temp_new(); \ 3193 gen_addr_reg_index(ctx, EA); \ 3194 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3195 } 3196 3197 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3198 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3199 3200 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3201 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3202 3203 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 3204 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3205 { \ 3206 TCGv EA; \ 3207 CHK_SV(ctx); \ 3208 gen_set_access_type(ctx, ACCESS_INT); \ 3209 EA = tcg_temp_new(); \ 3210 gen_addr_reg_index(ctx, EA); \ 3211 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 3212 } 3213 3214 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 3215 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 3216 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 3217 #if defined(TARGET_PPC64) 3218 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 3219 #endif 3220 3221 #if defined(TARGET_PPC64) 3222 /* CI load/store variants */ 3223 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3224 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3225 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3226 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3227 #endif 3228 3229 /*** Integer store ***/ 3230 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3231 static void glue(gen_, name##x)(DisasContext *ctx) \ 3232 { \ 3233 TCGv EA; \ 3234 chk(ctx); \ 3235 gen_set_access_type(ctx, ACCESS_INT); \ 3236 EA = tcg_temp_new(); \ 3237 gen_addr_reg_index(ctx, EA); \ 3238 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3239 } 3240 #define GEN_STX(name, stop, opc2, opc3, type) \ 3241 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3242 3243 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3244 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3245 3246 #define GEN_STEPX(name, stop, opc2, opc3) \ 3247 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3248 { \ 3249 TCGv EA; \ 3250 CHK_SV(ctx); \ 3251 gen_set_access_type(ctx, ACCESS_INT); \ 3252 EA = tcg_temp_new(); \ 3253 gen_addr_reg_index(ctx, EA); \ 3254 tcg_gen_qemu_st_tl( \ 3255 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 3256 } 3257 3258 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 3259 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 3260 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 3261 #if defined(TARGET_PPC64) 3262 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 3263 #endif 3264 3265 #if defined(TARGET_PPC64) 3266 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3267 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3268 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3269 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3270 #endif 3271 /*** Integer load and store with byte reverse ***/ 3272 3273 /* lhbrx */ 3274 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3275 3276 /* lwbrx */ 3277 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3278 3279 #if defined(TARGET_PPC64) 3280 /* ldbrx */ 3281 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3282 /* stdbrx */ 3283 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3284 #endif /* TARGET_PPC64 */ 3285 3286 /* sthbrx */ 3287 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3288 /* stwbrx */ 3289 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3290 3291 /*** Integer load and store multiple ***/ 3292 3293 /* lmw */ 3294 static void gen_lmw(DisasContext *ctx) 3295 { 3296 TCGv t0; 3297 TCGv_i32 t1; 3298 3299 if (ctx->le_mode) { 3300 gen_align_no_le(ctx); 3301 return; 3302 } 3303 gen_set_access_type(ctx, ACCESS_INT); 3304 t0 = tcg_temp_new(); 3305 t1 = tcg_constant_i32(rD(ctx->opcode)); 3306 gen_addr_imm_index(ctx, t0, 0); 3307 gen_helper_lmw(tcg_env, t0, t1); 3308 } 3309 3310 /* stmw */ 3311 static void gen_stmw(DisasContext *ctx) 3312 { 3313 TCGv t0; 3314 TCGv_i32 t1; 3315 3316 if (ctx->le_mode) { 3317 gen_align_no_le(ctx); 3318 return; 3319 } 3320 gen_set_access_type(ctx, ACCESS_INT); 3321 t0 = tcg_temp_new(); 3322 t1 = tcg_constant_i32(rS(ctx->opcode)); 3323 gen_addr_imm_index(ctx, t0, 0); 3324 gen_helper_stmw(tcg_env, t0, t1); 3325 } 3326 3327 /*** Integer load and store strings ***/ 3328 3329 /* lswi */ 3330 /* 3331 * PowerPC32 specification says we must generate an exception if rA is 3332 * in the range of registers to be loaded. In an other hand, IBM says 3333 * this is valid, but rA won't be loaded. For now, I'll follow the 3334 * spec... 3335 */ 3336 static void gen_lswi(DisasContext *ctx) 3337 { 3338 TCGv t0; 3339 TCGv_i32 t1, t2; 3340 int nb = NB(ctx->opcode); 3341 int start = rD(ctx->opcode); 3342 int ra = rA(ctx->opcode); 3343 int nr; 3344 3345 if (ctx->le_mode) { 3346 gen_align_no_le(ctx); 3347 return; 3348 } 3349 if (nb == 0) { 3350 nb = 32; 3351 } 3352 nr = DIV_ROUND_UP(nb, 4); 3353 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3354 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3355 return; 3356 } 3357 gen_set_access_type(ctx, ACCESS_INT); 3358 t0 = tcg_temp_new(); 3359 gen_addr_register(ctx, t0); 3360 t1 = tcg_constant_i32(nb); 3361 t2 = tcg_constant_i32(start); 3362 gen_helper_lsw(tcg_env, t0, t1, t2); 3363 } 3364 3365 /* lswx */ 3366 static void gen_lswx(DisasContext *ctx) 3367 { 3368 TCGv t0; 3369 TCGv_i32 t1, t2, t3; 3370 3371 if (ctx->le_mode) { 3372 gen_align_no_le(ctx); 3373 return; 3374 } 3375 gen_set_access_type(ctx, ACCESS_INT); 3376 t0 = tcg_temp_new(); 3377 gen_addr_reg_index(ctx, t0); 3378 t1 = tcg_constant_i32(rD(ctx->opcode)); 3379 t2 = tcg_constant_i32(rA(ctx->opcode)); 3380 t3 = tcg_constant_i32(rB(ctx->opcode)); 3381 gen_helper_lswx(tcg_env, t0, t1, t2, t3); 3382 } 3383 3384 /* stswi */ 3385 static void gen_stswi(DisasContext *ctx) 3386 { 3387 TCGv t0; 3388 TCGv_i32 t1, t2; 3389 int nb = NB(ctx->opcode); 3390 3391 if (ctx->le_mode) { 3392 gen_align_no_le(ctx); 3393 return; 3394 } 3395 gen_set_access_type(ctx, ACCESS_INT); 3396 t0 = tcg_temp_new(); 3397 gen_addr_register(ctx, t0); 3398 if (nb == 0) { 3399 nb = 32; 3400 } 3401 t1 = tcg_constant_i32(nb); 3402 t2 = tcg_constant_i32(rS(ctx->opcode)); 3403 gen_helper_stsw(tcg_env, t0, t1, t2); 3404 } 3405 3406 /* stswx */ 3407 static void gen_stswx(DisasContext *ctx) 3408 { 3409 TCGv t0; 3410 TCGv_i32 t1, t2; 3411 3412 if (ctx->le_mode) { 3413 gen_align_no_le(ctx); 3414 return; 3415 } 3416 gen_set_access_type(ctx, ACCESS_INT); 3417 t0 = tcg_temp_new(); 3418 gen_addr_reg_index(ctx, t0); 3419 t1 = tcg_temp_new_i32(); 3420 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3421 tcg_gen_andi_i32(t1, t1, 0x7F); 3422 t2 = tcg_constant_i32(rS(ctx->opcode)); 3423 gen_helper_stsw(tcg_env, t0, t1, t2); 3424 } 3425 3426 /*** Memory synchronisation ***/ 3427 /* eieio */ 3428 static void gen_eieio(DisasContext *ctx) 3429 { 3430 TCGBar bar = TCG_MO_ALL; 3431 3432 /* 3433 * eieio has complex semanitcs. It provides memory ordering between 3434 * operations in the set: 3435 * - loads from CI memory. 3436 * - stores to CI memory. 3437 * - stores to WT memory. 3438 * 3439 * It separately also orders memory for operations in the set: 3440 * - stores to cacheble memory. 3441 * 3442 * It also serializes instructions: 3443 * - dcbt and dcbst. 3444 * 3445 * It separately serializes: 3446 * - tlbie and tlbsync. 3447 * 3448 * And separately serializes: 3449 * - slbieg, slbiag, and slbsync. 3450 * 3451 * The end result is that CI memory ordering requires TCG_MO_ALL 3452 * and it is not possible to special-case more relaxed ordering for 3453 * cacheable accesses. TCG_BAR_SC is required to provide this 3454 * serialization. 3455 */ 3456 3457 /* 3458 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3459 * tell the CPU it is a store-forwarding barrier. 3460 */ 3461 if (ctx->opcode & 0x2000000) { 3462 /* 3463 * ISA says that "Reserved fields in instructions are ignored 3464 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3465 * as this is not an instruction software should be using, 3466 * complain to the user. 3467 */ 3468 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3469 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3470 TARGET_FMT_lx "\n", ctx->cia); 3471 } else { 3472 bar = TCG_MO_ST_LD; 3473 } 3474 } 3475 3476 tcg_gen_mb(bar | TCG_BAR_SC); 3477 } 3478 3479 #if !defined(CONFIG_USER_ONLY) 3480 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3481 { 3482 TCGv_i32 t; 3483 TCGLabel *l; 3484 3485 if (!ctx->lazy_tlb_flush) { 3486 return; 3487 } 3488 l = gen_new_label(); 3489 t = tcg_temp_new_i32(); 3490 tcg_gen_ld_i32(t, tcg_env, offsetof(CPUPPCState, tlb_need_flush)); 3491 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3492 if (global) { 3493 gen_helper_check_tlb_flush_global(tcg_env); 3494 } else { 3495 gen_helper_check_tlb_flush_local(tcg_env); 3496 } 3497 gen_set_label(l); 3498 } 3499 #else 3500 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3501 #endif 3502 3503 /* isync */ 3504 static void gen_isync(DisasContext *ctx) 3505 { 3506 /* 3507 * We need to check for a pending TLB flush. This can only happen in 3508 * kernel mode however so check MSR_PR 3509 */ 3510 if (!ctx->pr) { 3511 gen_check_tlb_flush(ctx, false); 3512 } 3513 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3514 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3515 } 3516 3517 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3518 3519 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3520 { 3521 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3522 TCGv t0 = tcg_temp_new(); 3523 3524 gen_set_access_type(ctx, ACCESS_RES); 3525 gen_addr_reg_index(ctx, t0); 3526 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3527 tcg_gen_mov_tl(cpu_reserve, t0); 3528 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 3529 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3530 } 3531 3532 #define LARX(name, memop) \ 3533 static void gen_##name(DisasContext *ctx) \ 3534 { \ 3535 gen_load_locked(ctx, memop); \ 3536 } 3537 3538 /* lwarx */ 3539 LARX(lbarx, DEF_MEMOP(MO_UB)) 3540 LARX(lharx, DEF_MEMOP(MO_UW)) 3541 LARX(lwarx, DEF_MEMOP(MO_UL)) 3542 3543 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3544 TCGv EA, TCGCond cond, int addend) 3545 { 3546 TCGv t = tcg_temp_new(); 3547 TCGv t2 = tcg_temp_new(); 3548 TCGv u = tcg_temp_new(); 3549 3550 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3551 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3552 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3553 tcg_gen_addi_tl(u, t, addend); 3554 3555 /* E.g. for fetch and increment bounded... */ 3556 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3557 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3558 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3559 3560 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3561 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3562 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3563 } 3564 3565 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3566 { 3567 uint32_t gpr_FC = FC(ctx->opcode); 3568 TCGv EA = tcg_temp_new(); 3569 int rt = rD(ctx->opcode); 3570 bool need_serial; 3571 TCGv src, dst; 3572 3573 gen_addr_register(ctx, EA); 3574 dst = cpu_gpr[rt]; 3575 src = cpu_gpr[(rt + 1) & 31]; 3576 3577 need_serial = false; 3578 memop |= MO_ALIGN; 3579 switch (gpr_FC) { 3580 case 0: /* Fetch and add */ 3581 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3582 break; 3583 case 1: /* Fetch and xor */ 3584 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3585 break; 3586 case 2: /* Fetch and or */ 3587 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3588 break; 3589 case 3: /* Fetch and 'and' */ 3590 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3591 break; 3592 case 4: /* Fetch and max unsigned */ 3593 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3594 break; 3595 case 5: /* Fetch and max signed */ 3596 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3597 break; 3598 case 6: /* Fetch and min unsigned */ 3599 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3600 break; 3601 case 7: /* Fetch and min signed */ 3602 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3603 break; 3604 case 8: /* Swap */ 3605 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3606 break; 3607 3608 case 16: /* Compare and swap not equal */ 3609 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3610 need_serial = true; 3611 } else { 3612 TCGv t0 = tcg_temp_new(); 3613 TCGv t1 = tcg_temp_new(); 3614 3615 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3616 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3617 tcg_gen_mov_tl(t1, src); 3618 } else { 3619 tcg_gen_ext32u_tl(t1, src); 3620 } 3621 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3622 cpu_gpr[(rt + 2) & 31], t0); 3623 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3624 tcg_gen_mov_tl(dst, t0); 3625 } 3626 break; 3627 3628 case 24: /* Fetch and increment bounded */ 3629 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3630 need_serial = true; 3631 } else { 3632 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3633 } 3634 break; 3635 case 25: /* Fetch and increment equal */ 3636 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3637 need_serial = true; 3638 } else { 3639 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3640 } 3641 break; 3642 case 28: /* Fetch and decrement bounded */ 3643 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3644 need_serial = true; 3645 } else { 3646 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3647 } 3648 break; 3649 3650 default: 3651 /* invoke data storage error handler */ 3652 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3653 } 3654 3655 if (need_serial) { 3656 /* Restart with exclusive lock. */ 3657 gen_helper_exit_atomic(tcg_env); 3658 ctx->base.is_jmp = DISAS_NORETURN; 3659 } 3660 } 3661 3662 static void gen_lwat(DisasContext *ctx) 3663 { 3664 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3665 } 3666 3667 #ifdef TARGET_PPC64 3668 static void gen_ldat(DisasContext *ctx) 3669 { 3670 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3671 } 3672 #endif 3673 3674 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3675 { 3676 uint32_t gpr_FC = FC(ctx->opcode); 3677 TCGv EA = tcg_temp_new(); 3678 TCGv src, discard; 3679 3680 gen_addr_register(ctx, EA); 3681 src = cpu_gpr[rD(ctx->opcode)]; 3682 discard = tcg_temp_new(); 3683 3684 memop |= MO_ALIGN; 3685 switch (gpr_FC) { 3686 case 0: /* add and Store */ 3687 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3688 break; 3689 case 1: /* xor and Store */ 3690 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3691 break; 3692 case 2: /* Or and Store */ 3693 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3694 break; 3695 case 3: /* 'and' and Store */ 3696 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3697 break; 3698 case 4: /* Store max unsigned */ 3699 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3700 break; 3701 case 5: /* Store max signed */ 3702 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3703 break; 3704 case 6: /* Store min unsigned */ 3705 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3706 break; 3707 case 7: /* Store min signed */ 3708 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3709 break; 3710 case 24: /* Store twin */ 3711 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3712 /* Restart with exclusive lock. */ 3713 gen_helper_exit_atomic(tcg_env); 3714 ctx->base.is_jmp = DISAS_NORETURN; 3715 } else { 3716 TCGv t = tcg_temp_new(); 3717 TCGv t2 = tcg_temp_new(); 3718 TCGv s = tcg_temp_new(); 3719 TCGv s2 = tcg_temp_new(); 3720 TCGv ea_plus_s = tcg_temp_new(); 3721 3722 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3723 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3724 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3725 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3726 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3727 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3728 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3729 } 3730 break; 3731 default: 3732 /* invoke data storage error handler */ 3733 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3734 } 3735 } 3736 3737 static void gen_stwat(DisasContext *ctx) 3738 { 3739 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3740 } 3741 3742 #ifdef TARGET_PPC64 3743 static void gen_stdat(DisasContext *ctx) 3744 { 3745 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3746 } 3747 #endif 3748 3749 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3750 { 3751 TCGLabel *lfail; 3752 TCGv EA; 3753 TCGv cr0; 3754 TCGv t0; 3755 int rs = rS(ctx->opcode); 3756 3757 lfail = gen_new_label(); 3758 EA = tcg_temp_new(); 3759 cr0 = tcg_temp_new(); 3760 t0 = tcg_temp_new(); 3761 3762 tcg_gen_mov_tl(cr0, cpu_so); 3763 gen_set_access_type(ctx, ACCESS_RES); 3764 gen_addr_reg_index(ctx, EA); 3765 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3766 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 3767 3768 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3769 cpu_gpr[rs], ctx->mem_idx, 3770 DEF_MEMOP(memop) | MO_ALIGN); 3771 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3772 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3773 tcg_gen_or_tl(cr0, cr0, t0); 3774 3775 gen_set_label(lfail); 3776 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3777 tcg_gen_movi_tl(cpu_reserve, -1); 3778 } 3779 3780 #define STCX(name, memop) \ 3781 static void gen_##name(DisasContext *ctx) \ 3782 { \ 3783 gen_conditional_store(ctx, memop); \ 3784 } 3785 3786 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3787 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3788 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3789 3790 #if defined(TARGET_PPC64) 3791 /* ldarx */ 3792 LARX(ldarx, DEF_MEMOP(MO_UQ)) 3793 /* stdcx. */ 3794 STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3795 3796 /* lqarx */ 3797 static void gen_lqarx(DisasContext *ctx) 3798 { 3799 int rd = rD(ctx->opcode); 3800 TCGv EA, hi, lo; 3801 TCGv_i128 t16; 3802 3803 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3804 (rd == rB(ctx->opcode)))) { 3805 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3806 return; 3807 } 3808 3809 gen_set_access_type(ctx, ACCESS_RES); 3810 EA = tcg_temp_new(); 3811 gen_addr_reg_index(ctx, EA); 3812 3813 /* Note that the low part is always in RD+1, even in LE mode. */ 3814 lo = cpu_gpr[rd + 1]; 3815 hi = cpu_gpr[rd]; 3816 3817 t16 = tcg_temp_new_i128(); 3818 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3819 tcg_gen_extr_i128_i64(lo, hi, t16); 3820 3821 tcg_gen_mov_tl(cpu_reserve, EA); 3822 tcg_gen_movi_tl(cpu_reserve_length, 16); 3823 tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val)); 3824 tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2)); 3825 } 3826 3827 /* stqcx. */ 3828 static void gen_stqcx_(DisasContext *ctx) 3829 { 3830 TCGLabel *lfail; 3831 TCGv EA, t0, t1; 3832 TCGv cr0; 3833 TCGv_i128 cmp, val; 3834 int rs = rS(ctx->opcode); 3835 3836 if (unlikely(rs & 1)) { 3837 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3838 return; 3839 } 3840 3841 lfail = gen_new_label(); 3842 EA = tcg_temp_new(); 3843 cr0 = tcg_temp_new(); 3844 3845 tcg_gen_mov_tl(cr0, cpu_so); 3846 gen_set_access_type(ctx, ACCESS_RES); 3847 gen_addr_reg_index(ctx, EA); 3848 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3849 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 3850 3851 cmp = tcg_temp_new_i128(); 3852 val = tcg_temp_new_i128(); 3853 3854 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3855 3856 /* Note that the low part is always in RS+1, even in LE mode. */ 3857 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3858 3859 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3860 DEF_MEMOP(MO_128 | MO_ALIGN)); 3861 3862 t0 = tcg_temp_new(); 3863 t1 = tcg_temp_new(); 3864 tcg_gen_extr_i128_i64(t1, t0, val); 3865 3866 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3867 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3868 tcg_gen_or_tl(t0, t0, t1); 3869 3870 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3871 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3872 tcg_gen_or_tl(cr0, cr0, t0); 3873 3874 gen_set_label(lfail); 3875 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3876 tcg_gen_movi_tl(cpu_reserve, -1); 3877 } 3878 #endif /* defined(TARGET_PPC64) */ 3879 3880 /* sync */ 3881 static void gen_sync(DisasContext *ctx) 3882 { 3883 TCGBar bar = TCG_MO_ALL; 3884 uint32_t l = (ctx->opcode >> 21) & 3; 3885 3886 if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 3887 bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 3888 } 3889 3890 /* 3891 * We may need to check for a pending TLB flush. 3892 * 3893 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3894 * 3895 * Additionally, this can only happen in kernel mode however so 3896 * check MSR_PR as well. 3897 */ 3898 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3899 gen_check_tlb_flush(ctx, true); 3900 } 3901 3902 tcg_gen_mb(bar | TCG_BAR_SC); 3903 } 3904 3905 /* wait */ 3906 static void gen_wait(DisasContext *ctx) 3907 { 3908 uint32_t wc; 3909 3910 if (ctx->insns_flags & PPC_WAIT) { 3911 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3912 3913 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3914 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3915 wc = WC(ctx->opcode); 3916 } else { 3917 wc = 0; 3918 } 3919 3920 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3921 /* v3.0 defines a new 'wait' encoding. */ 3922 wc = WC(ctx->opcode); 3923 if (ctx->insns_flags2 & PPC2_ISA310) { 3924 uint32_t pl = PL(ctx->opcode); 3925 3926 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3927 if (wc == 3) { 3928 gen_invalid(ctx); 3929 return; 3930 } 3931 3932 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3933 if (pl > 0 && wc != 2) { 3934 gen_invalid(ctx); 3935 return; 3936 } 3937 3938 } else { /* ISA300 */ 3939 /* WC 1-3 are reserved */ 3940 if (wc > 0) { 3941 gen_invalid(ctx); 3942 return; 3943 } 3944 } 3945 3946 } else { 3947 warn_report("wait instruction decoded with wrong ISA flags."); 3948 gen_invalid(ctx); 3949 return; 3950 } 3951 3952 /* 3953 * wait without WC field or with WC=0 waits for an exception / interrupt 3954 * to occur. 3955 */ 3956 if (wc == 0) { 3957 TCGv_i32 t0 = tcg_constant_i32(1); 3958 tcg_gen_st_i32(t0, tcg_env, 3959 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3960 /* Stop translation, as the CPU is supposed to sleep from now */ 3961 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3962 } 3963 3964 /* 3965 * Other wait types must not just wait until an exception occurs because 3966 * ignoring their other wake-up conditions could cause a hang. 3967 * 3968 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3969 * no-ops. 3970 * 3971 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 3972 * 3973 * wc=2 waits for an implementation-specific condition, such could be 3974 * always true, so it can be implemented as a no-op. 3975 * 3976 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 3977 * 3978 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 3979 * Reservation-loss may have implementation-specific conditions, so it 3980 * can be implemented as a no-op. 3981 * 3982 * wc=2 waits for an exception or an amount of time to pass. This 3983 * amount is implementation-specific so it can be implemented as a 3984 * no-op. 3985 * 3986 * ISA v3.1 allows for execution to resume "in the rare case of 3987 * an implementation-dependent event", so in any case software must 3988 * not depend on the architected resumption condition to become 3989 * true, so no-op implementations should be architecturally correct 3990 * (if suboptimal). 3991 */ 3992 } 3993 3994 #if defined(TARGET_PPC64) 3995 static void gen_doze(DisasContext *ctx) 3996 { 3997 #if defined(CONFIG_USER_ONLY) 3998 GEN_PRIV(ctx); 3999 #else 4000 TCGv_i32 t; 4001 4002 CHK_HV(ctx); 4003 translator_io_start(&ctx->base); 4004 t = tcg_constant_i32(PPC_PM_DOZE); 4005 gen_helper_pminsn(tcg_env, t); 4006 /* Stop translation, as the CPU is supposed to sleep from now */ 4007 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4008 #endif /* defined(CONFIG_USER_ONLY) */ 4009 } 4010 4011 static void gen_nap(DisasContext *ctx) 4012 { 4013 #if defined(CONFIG_USER_ONLY) 4014 GEN_PRIV(ctx); 4015 #else 4016 TCGv_i32 t; 4017 4018 CHK_HV(ctx); 4019 translator_io_start(&ctx->base); 4020 t = tcg_constant_i32(PPC_PM_NAP); 4021 gen_helper_pminsn(tcg_env, t); 4022 /* Stop translation, as the CPU is supposed to sleep from now */ 4023 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4024 #endif /* defined(CONFIG_USER_ONLY) */ 4025 } 4026 4027 static void gen_stop(DisasContext *ctx) 4028 { 4029 #if defined(CONFIG_USER_ONLY) 4030 GEN_PRIV(ctx); 4031 #else 4032 TCGv_i32 t; 4033 4034 CHK_HV(ctx); 4035 translator_io_start(&ctx->base); 4036 t = tcg_constant_i32(PPC_PM_STOP); 4037 gen_helper_pminsn(tcg_env, t); 4038 /* Stop translation, as the CPU is supposed to sleep from now */ 4039 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4040 #endif /* defined(CONFIG_USER_ONLY) */ 4041 } 4042 4043 static void gen_sleep(DisasContext *ctx) 4044 { 4045 #if defined(CONFIG_USER_ONLY) 4046 GEN_PRIV(ctx); 4047 #else 4048 TCGv_i32 t; 4049 4050 CHK_HV(ctx); 4051 translator_io_start(&ctx->base); 4052 t = tcg_constant_i32(PPC_PM_SLEEP); 4053 gen_helper_pminsn(tcg_env, t); 4054 /* Stop translation, as the CPU is supposed to sleep from now */ 4055 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4056 #endif /* defined(CONFIG_USER_ONLY) */ 4057 } 4058 4059 static void gen_rvwinkle(DisasContext *ctx) 4060 { 4061 #if defined(CONFIG_USER_ONLY) 4062 GEN_PRIV(ctx); 4063 #else 4064 TCGv_i32 t; 4065 4066 CHK_HV(ctx); 4067 translator_io_start(&ctx->base); 4068 t = tcg_constant_i32(PPC_PM_RVWINKLE); 4069 gen_helper_pminsn(tcg_env, t); 4070 /* Stop translation, as the CPU is supposed to sleep from now */ 4071 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4072 #endif /* defined(CONFIG_USER_ONLY) */ 4073 } 4074 #endif /* #if defined(TARGET_PPC64) */ 4075 4076 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4077 { 4078 #if defined(TARGET_PPC64) 4079 if (ctx->has_cfar) { 4080 tcg_gen_movi_tl(cpu_cfar, nip); 4081 } 4082 #endif 4083 } 4084 4085 #if defined(TARGET_PPC64) 4086 static void pmu_count_insns(DisasContext *ctx) 4087 { 4088 /* 4089 * Do not bother calling the helper if the PMU isn't counting 4090 * instructions. 4091 */ 4092 if (!ctx->pmu_insn_cnt) { 4093 return; 4094 } 4095 4096 #if !defined(CONFIG_USER_ONLY) 4097 TCGLabel *l; 4098 TCGv t0; 4099 4100 /* 4101 * The PMU insns_inc() helper stops the internal PMU timer if a 4102 * counter overflows happens. In that case, if the guest is 4103 * running with icount and we do not handle it beforehand, 4104 * the helper can trigger a 'bad icount read'. 4105 */ 4106 translator_io_start(&ctx->base); 4107 4108 /* Avoid helper calls when only PMC5-6 are enabled. */ 4109 if (!ctx->pmc_other) { 4110 l = gen_new_label(); 4111 t0 = tcg_temp_new(); 4112 4113 gen_load_spr(t0, SPR_POWER_PMC5); 4114 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4115 gen_store_spr(SPR_POWER_PMC5, t0); 4116 /* Check for overflow, if it's enabled */ 4117 if (ctx->mmcr0_pmcjce) { 4118 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4119 gen_helper_handle_pmc5_overflow(tcg_env); 4120 } 4121 4122 gen_set_label(l); 4123 } else { 4124 gen_helper_insns_inc(tcg_env, tcg_constant_i32(ctx->base.num_insns)); 4125 } 4126 #else 4127 /* 4128 * User mode can read (but not write) PMC5 and start/stop 4129 * the PMU via MMCR0_FC. In this case just increment 4130 * PMC5 with base.num_insns. 4131 */ 4132 TCGv t0 = tcg_temp_new(); 4133 4134 gen_load_spr(t0, SPR_POWER_PMC5); 4135 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4136 gen_store_spr(SPR_POWER_PMC5, t0); 4137 #endif /* #if !defined(CONFIG_USER_ONLY) */ 4138 } 4139 #else 4140 static void pmu_count_insns(DisasContext *ctx) 4141 { 4142 return; 4143 } 4144 #endif /* #if defined(TARGET_PPC64) */ 4145 4146 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4147 { 4148 if (unlikely(ctx->singlestep_enabled)) { 4149 return false; 4150 } 4151 return translator_use_goto_tb(&ctx->base, dest); 4152 } 4153 4154 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 4155 { 4156 if (unlikely(ctx->singlestep_enabled)) { 4157 gen_debug_exception(ctx, false); 4158 } else { 4159 /* 4160 * tcg_gen_lookup_and_goto_ptr will exit the TB if 4161 * CF_NO_GOTO_PTR is set. Count insns now. 4162 */ 4163 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 4164 pmu_count_insns(ctx); 4165 } 4166 4167 tcg_gen_lookup_and_goto_ptr(); 4168 } 4169 } 4170 4171 /*** Branch ***/ 4172 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4173 { 4174 if (NARROW_MODE(ctx)) { 4175 dest = (uint32_t) dest; 4176 } 4177 if (use_goto_tb(ctx, dest)) { 4178 pmu_count_insns(ctx); 4179 tcg_gen_goto_tb(n); 4180 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4181 tcg_gen_exit_tb(ctx->base.tb, n); 4182 } else { 4183 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4184 gen_lookup_and_goto_ptr(ctx); 4185 } 4186 } 4187 4188 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4189 { 4190 if (NARROW_MODE(ctx)) { 4191 nip = (uint32_t)nip; 4192 } 4193 tcg_gen_movi_tl(cpu_lr, nip); 4194 } 4195 4196 /* b ba bl bla */ 4197 static void gen_b(DisasContext *ctx) 4198 { 4199 target_ulong li, target; 4200 4201 /* sign extend LI */ 4202 li = LI(ctx->opcode); 4203 li = (li ^ 0x02000000) - 0x02000000; 4204 if (likely(AA(ctx->opcode) == 0)) { 4205 target = ctx->cia + li; 4206 } else { 4207 target = li; 4208 } 4209 if (LK(ctx->opcode)) { 4210 gen_setlr(ctx, ctx->base.pc_next); 4211 } 4212 gen_update_cfar(ctx, ctx->cia); 4213 gen_goto_tb(ctx, 0, target); 4214 ctx->base.is_jmp = DISAS_NORETURN; 4215 } 4216 4217 #define BCOND_IM 0 4218 #define BCOND_LR 1 4219 #define BCOND_CTR 2 4220 #define BCOND_TAR 3 4221 4222 static void gen_bcond(DisasContext *ctx, int type) 4223 { 4224 uint32_t bo = BO(ctx->opcode); 4225 TCGLabel *l1; 4226 TCGv target; 4227 4228 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4229 target = tcg_temp_new(); 4230 if (type == BCOND_CTR) { 4231 tcg_gen_mov_tl(target, cpu_ctr); 4232 } else if (type == BCOND_TAR) { 4233 gen_load_spr(target, SPR_TAR); 4234 } else { 4235 tcg_gen_mov_tl(target, cpu_lr); 4236 } 4237 } else { 4238 target = NULL; 4239 } 4240 if (LK(ctx->opcode)) { 4241 gen_setlr(ctx, ctx->base.pc_next); 4242 } 4243 l1 = gen_new_label(); 4244 if ((bo & 0x4) == 0) { 4245 /* Decrement and test CTR */ 4246 TCGv temp = tcg_temp_new(); 4247 4248 if (type == BCOND_CTR) { 4249 /* 4250 * All ISAs up to v3 describe this form of bcctr as invalid but 4251 * some processors, ie. 64-bit server processors compliant with 4252 * arch 2.x, do implement a "test and decrement" logic instead, 4253 * as described in their respective UMs. This logic involves CTR 4254 * to act as both the branch target and a counter, which makes 4255 * it basically useless and thus never used in real code. 4256 * 4257 * This form was hence chosen to trigger extra micro-architectural 4258 * side-effect on real HW needed for the Spectre v2 workaround. 4259 * It is up to guests that implement such workaround, ie. linux, to 4260 * use this form in a way it just triggers the side-effect without 4261 * doing anything else harmful. 4262 */ 4263 if (unlikely(!is_book3s_arch2x(ctx))) { 4264 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4265 return; 4266 } 4267 4268 if (NARROW_MODE(ctx)) { 4269 tcg_gen_ext32u_tl(temp, cpu_ctr); 4270 } else { 4271 tcg_gen_mov_tl(temp, cpu_ctr); 4272 } 4273 if (bo & 0x2) { 4274 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4275 } else { 4276 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4277 } 4278 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4279 } else { 4280 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4281 if (NARROW_MODE(ctx)) { 4282 tcg_gen_ext32u_tl(temp, cpu_ctr); 4283 } else { 4284 tcg_gen_mov_tl(temp, cpu_ctr); 4285 } 4286 if (bo & 0x2) { 4287 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4288 } else { 4289 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4290 } 4291 } 4292 } 4293 if ((bo & 0x10) == 0) { 4294 /* Test CR */ 4295 uint32_t bi = BI(ctx->opcode); 4296 uint32_t mask = 0x08 >> (bi & 0x03); 4297 TCGv_i32 temp = tcg_temp_new_i32(); 4298 4299 if (bo & 0x8) { 4300 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4301 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4302 } else { 4303 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4304 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4305 } 4306 } 4307 gen_update_cfar(ctx, ctx->cia); 4308 if (type == BCOND_IM) { 4309 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4310 if (likely(AA(ctx->opcode) == 0)) { 4311 gen_goto_tb(ctx, 0, ctx->cia + li); 4312 } else { 4313 gen_goto_tb(ctx, 0, li); 4314 } 4315 } else { 4316 if (NARROW_MODE(ctx)) { 4317 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4318 } else { 4319 tcg_gen_andi_tl(cpu_nip, target, ~3); 4320 } 4321 gen_lookup_and_goto_ptr(ctx); 4322 } 4323 if ((bo & 0x14) != 0x14) { 4324 /* fallthrough case */ 4325 gen_set_label(l1); 4326 gen_goto_tb(ctx, 1, ctx->base.pc_next); 4327 } 4328 ctx->base.is_jmp = DISAS_NORETURN; 4329 } 4330 4331 static void gen_bc(DisasContext *ctx) 4332 { 4333 gen_bcond(ctx, BCOND_IM); 4334 } 4335 4336 static void gen_bcctr(DisasContext *ctx) 4337 { 4338 gen_bcond(ctx, BCOND_CTR); 4339 } 4340 4341 static void gen_bclr(DisasContext *ctx) 4342 { 4343 gen_bcond(ctx, BCOND_LR); 4344 } 4345 4346 static void gen_bctar(DisasContext *ctx) 4347 { 4348 gen_bcond(ctx, BCOND_TAR); 4349 } 4350 4351 /*** Condition register logical ***/ 4352 #define GEN_CRLOGIC(name, tcg_op, opc) \ 4353 static void glue(gen_, name)(DisasContext *ctx) \ 4354 { \ 4355 uint8_t bitmask; \ 4356 int sh; \ 4357 TCGv_i32 t0, t1; \ 4358 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4359 t0 = tcg_temp_new_i32(); \ 4360 if (sh > 0) \ 4361 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4362 else if (sh < 0) \ 4363 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4364 else \ 4365 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4366 t1 = tcg_temp_new_i32(); \ 4367 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4368 if (sh > 0) \ 4369 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4370 else if (sh < 0) \ 4371 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4372 else \ 4373 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4374 tcg_op(t0, t0, t1); \ 4375 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4376 tcg_gen_andi_i32(t0, t0, bitmask); \ 4377 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4378 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4379 } 4380 4381 /* crand */ 4382 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4383 /* crandc */ 4384 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4385 /* creqv */ 4386 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4387 /* crnand */ 4388 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4389 /* crnor */ 4390 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4391 /* cror */ 4392 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4393 /* crorc */ 4394 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4395 /* crxor */ 4396 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4397 4398 /* mcrf */ 4399 static void gen_mcrf(DisasContext *ctx) 4400 { 4401 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4402 } 4403 4404 /*** System linkage ***/ 4405 4406 /* rfi (supervisor only) */ 4407 static void gen_rfi(DisasContext *ctx) 4408 { 4409 #if defined(CONFIG_USER_ONLY) 4410 GEN_PRIV(ctx); 4411 #else 4412 /* 4413 * This instruction doesn't exist anymore on 64-bit server 4414 * processors compliant with arch 2.x 4415 */ 4416 if (is_book3s_arch2x(ctx)) { 4417 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4418 return; 4419 } 4420 /* Restore CPU state */ 4421 CHK_SV(ctx); 4422 translator_io_start(&ctx->base); 4423 gen_update_cfar(ctx, ctx->cia); 4424 gen_helper_rfi(tcg_env); 4425 ctx->base.is_jmp = DISAS_EXIT; 4426 #endif 4427 } 4428 4429 #if defined(TARGET_PPC64) 4430 static void gen_rfid(DisasContext *ctx) 4431 { 4432 #if defined(CONFIG_USER_ONLY) 4433 GEN_PRIV(ctx); 4434 #else 4435 /* Restore CPU state */ 4436 CHK_SV(ctx); 4437 translator_io_start(&ctx->base); 4438 gen_update_cfar(ctx, ctx->cia); 4439 gen_helper_rfid(tcg_env); 4440 ctx->base.is_jmp = DISAS_EXIT; 4441 #endif 4442 } 4443 4444 #if !defined(CONFIG_USER_ONLY) 4445 static void gen_rfscv(DisasContext *ctx) 4446 { 4447 #if defined(CONFIG_USER_ONLY) 4448 GEN_PRIV(ctx); 4449 #else 4450 /* Restore CPU state */ 4451 CHK_SV(ctx); 4452 translator_io_start(&ctx->base); 4453 gen_update_cfar(ctx, ctx->cia); 4454 gen_helper_rfscv(tcg_env); 4455 ctx->base.is_jmp = DISAS_EXIT; 4456 #endif 4457 } 4458 #endif 4459 4460 static void gen_hrfid(DisasContext *ctx) 4461 { 4462 #if defined(CONFIG_USER_ONLY) 4463 GEN_PRIV(ctx); 4464 #else 4465 /* Restore CPU state */ 4466 CHK_HV(ctx); 4467 translator_io_start(&ctx->base); 4468 gen_helper_hrfid(tcg_env); 4469 ctx->base.is_jmp = DISAS_EXIT; 4470 #endif 4471 } 4472 #endif 4473 4474 /* sc */ 4475 #if defined(CONFIG_USER_ONLY) 4476 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4477 #else 4478 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4479 #endif 4480 static void gen_sc(DisasContext *ctx) 4481 { 4482 uint32_t lev; 4483 4484 /* 4485 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4486 * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4487 * for Ultravisor which TCG does not support, so just ignore the top 6. 4488 */ 4489 lev = (ctx->opcode >> 5) & 0x1; 4490 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4491 } 4492 4493 #if defined(TARGET_PPC64) 4494 #if !defined(CONFIG_USER_ONLY) 4495 static void gen_scv(DisasContext *ctx) 4496 { 4497 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 4498 4499 /* Set the PC back to the faulting instruction. */ 4500 gen_update_nip(ctx, ctx->cia); 4501 gen_helper_scv(tcg_env, tcg_constant_i32(lev)); 4502 4503 ctx->base.is_jmp = DISAS_NORETURN; 4504 } 4505 #endif 4506 #endif 4507 4508 /*** Trap ***/ 4509 4510 /* Check for unconditional traps (always or never) */ 4511 static bool check_unconditional_trap(DisasContext *ctx) 4512 { 4513 /* Trap never */ 4514 if (TO(ctx->opcode) == 0) { 4515 return true; 4516 } 4517 /* Trap always */ 4518 if (TO(ctx->opcode) == 31) { 4519 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4520 return true; 4521 } 4522 return false; 4523 } 4524 4525 /* tw */ 4526 static void gen_tw(DisasContext *ctx) 4527 { 4528 TCGv_i32 t0; 4529 4530 if (check_unconditional_trap(ctx)) { 4531 return; 4532 } 4533 t0 = tcg_constant_i32(TO(ctx->opcode)); 4534 gen_helper_tw(tcg_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4535 t0); 4536 } 4537 4538 /* twi */ 4539 static void gen_twi(DisasContext *ctx) 4540 { 4541 TCGv t0; 4542 TCGv_i32 t1; 4543 4544 if (check_unconditional_trap(ctx)) { 4545 return; 4546 } 4547 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4548 t1 = tcg_constant_i32(TO(ctx->opcode)); 4549 gen_helper_tw(tcg_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4550 } 4551 4552 #if defined(TARGET_PPC64) 4553 /* td */ 4554 static void gen_td(DisasContext *ctx) 4555 { 4556 TCGv_i32 t0; 4557 4558 if (check_unconditional_trap(ctx)) { 4559 return; 4560 } 4561 t0 = tcg_constant_i32(TO(ctx->opcode)); 4562 gen_helper_td(tcg_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4563 t0); 4564 } 4565 4566 /* tdi */ 4567 static void gen_tdi(DisasContext *ctx) 4568 { 4569 TCGv t0; 4570 TCGv_i32 t1; 4571 4572 if (check_unconditional_trap(ctx)) { 4573 return; 4574 } 4575 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4576 t1 = tcg_constant_i32(TO(ctx->opcode)); 4577 gen_helper_td(tcg_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4578 } 4579 #endif 4580 4581 /*** Processor control ***/ 4582 4583 /* mcrxr */ 4584 static void gen_mcrxr(DisasContext *ctx) 4585 { 4586 TCGv_i32 t0 = tcg_temp_new_i32(); 4587 TCGv_i32 t1 = tcg_temp_new_i32(); 4588 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4589 4590 tcg_gen_trunc_tl_i32(t0, cpu_so); 4591 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4592 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4593 tcg_gen_shli_i32(t0, t0, 3); 4594 tcg_gen_shli_i32(t1, t1, 2); 4595 tcg_gen_shli_i32(dst, dst, 1); 4596 tcg_gen_or_i32(dst, dst, t0); 4597 tcg_gen_or_i32(dst, dst, t1); 4598 4599 tcg_gen_movi_tl(cpu_so, 0); 4600 tcg_gen_movi_tl(cpu_ov, 0); 4601 tcg_gen_movi_tl(cpu_ca, 0); 4602 } 4603 4604 #ifdef TARGET_PPC64 4605 /* mcrxrx */ 4606 static void gen_mcrxrx(DisasContext *ctx) 4607 { 4608 TCGv t0 = tcg_temp_new(); 4609 TCGv t1 = tcg_temp_new(); 4610 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4611 4612 /* copy OV and OV32 */ 4613 tcg_gen_shli_tl(t0, cpu_ov, 1); 4614 tcg_gen_or_tl(t0, t0, cpu_ov32); 4615 tcg_gen_shli_tl(t0, t0, 2); 4616 /* copy CA and CA32 */ 4617 tcg_gen_shli_tl(t1, cpu_ca, 1); 4618 tcg_gen_or_tl(t1, t1, cpu_ca32); 4619 tcg_gen_or_tl(t0, t0, t1); 4620 tcg_gen_trunc_tl_i32(dst, t0); 4621 } 4622 #endif 4623 4624 /* mfcr mfocrf */ 4625 static void gen_mfcr(DisasContext *ctx) 4626 { 4627 uint32_t crm, crn; 4628 4629 if (likely(ctx->opcode & 0x00100000)) { 4630 crm = CRM(ctx->opcode); 4631 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4632 crn = ctz32(crm); 4633 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4634 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4635 cpu_gpr[rD(ctx->opcode)], crn * 4); 4636 } 4637 } else { 4638 TCGv_i32 t0 = tcg_temp_new_i32(); 4639 tcg_gen_mov_i32(t0, cpu_crf[0]); 4640 tcg_gen_shli_i32(t0, t0, 4); 4641 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4642 tcg_gen_shli_i32(t0, t0, 4); 4643 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4644 tcg_gen_shli_i32(t0, t0, 4); 4645 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4646 tcg_gen_shli_i32(t0, t0, 4); 4647 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4648 tcg_gen_shli_i32(t0, t0, 4); 4649 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4650 tcg_gen_shli_i32(t0, t0, 4); 4651 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4652 tcg_gen_shli_i32(t0, t0, 4); 4653 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4654 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4655 } 4656 } 4657 4658 /* mfmsr */ 4659 static void gen_mfmsr(DisasContext *ctx) 4660 { 4661 CHK_SV(ctx); 4662 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4663 } 4664 4665 /* mfspr */ 4666 static inline void gen_op_mfspr(DisasContext *ctx) 4667 { 4668 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4669 uint32_t sprn = SPR(ctx->opcode); 4670 4671 #if defined(CONFIG_USER_ONLY) 4672 read_cb = ctx->spr_cb[sprn].uea_read; 4673 #else 4674 if (ctx->pr) { 4675 read_cb = ctx->spr_cb[sprn].uea_read; 4676 } else if (ctx->hv) { 4677 read_cb = ctx->spr_cb[sprn].hea_read; 4678 } else { 4679 read_cb = ctx->spr_cb[sprn].oea_read; 4680 } 4681 #endif 4682 if (likely(read_cb != NULL)) { 4683 if (likely(read_cb != SPR_NOACCESS)) { 4684 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4685 } else { 4686 /* Privilege exception */ 4687 /* 4688 * This is a hack to avoid warnings when running Linux: 4689 * this OS breaks the PowerPC virtualisation model, 4690 * allowing userland application to read the PVR 4691 */ 4692 if (sprn != SPR_PVR) { 4693 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4694 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4695 ctx->cia); 4696 } 4697 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4698 } 4699 } else { 4700 /* ISA 2.07 defines these as no-ops */ 4701 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4702 (sprn >= 808 && sprn <= 811)) { 4703 /* This is a nop */ 4704 return; 4705 } 4706 /* Not defined */ 4707 qemu_log_mask(LOG_GUEST_ERROR, 4708 "Trying to read invalid spr %d (0x%03x) at " 4709 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4710 4711 /* 4712 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4713 * generate a priv, a hv emu or a no-op 4714 */ 4715 if (sprn & 0x10) { 4716 if (ctx->pr) { 4717 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4718 } 4719 } else { 4720 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4721 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4722 } 4723 } 4724 } 4725 } 4726 4727 static void gen_mfspr(DisasContext *ctx) 4728 { 4729 gen_op_mfspr(ctx); 4730 } 4731 4732 /* mftb */ 4733 static void gen_mftb(DisasContext *ctx) 4734 { 4735 gen_op_mfspr(ctx); 4736 } 4737 4738 /* mtcrf mtocrf*/ 4739 static void gen_mtcrf(DisasContext *ctx) 4740 { 4741 uint32_t crm, crn; 4742 4743 crm = CRM(ctx->opcode); 4744 if (likely((ctx->opcode & 0x00100000))) { 4745 if (crm && ((crm & (crm - 1)) == 0)) { 4746 TCGv_i32 temp = tcg_temp_new_i32(); 4747 crn = ctz32(crm); 4748 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4749 tcg_gen_shri_i32(temp, temp, crn * 4); 4750 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4751 } 4752 } else { 4753 TCGv_i32 temp = tcg_temp_new_i32(); 4754 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4755 for (crn = 0 ; crn < 8 ; crn++) { 4756 if (crm & (1 << crn)) { 4757 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4758 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4759 } 4760 } 4761 } 4762 } 4763 4764 /* mtmsr */ 4765 #if defined(TARGET_PPC64) 4766 static void gen_mtmsrd(DisasContext *ctx) 4767 { 4768 if (unlikely(!is_book3s_arch2x(ctx))) { 4769 gen_invalid(ctx); 4770 return; 4771 } 4772 4773 CHK_SV(ctx); 4774 4775 #if !defined(CONFIG_USER_ONLY) 4776 TCGv t0, t1; 4777 target_ulong mask; 4778 4779 t0 = tcg_temp_new(); 4780 t1 = tcg_temp_new(); 4781 4782 translator_io_start(&ctx->base); 4783 4784 if (ctx->opcode & 0x00010000) { 4785 /* L=1 form only updates EE and RI */ 4786 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4787 } else { 4788 /* mtmsrd does not alter HV, S, ME, or LE */ 4789 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4790 (1ULL << MSR_HV)); 4791 /* 4792 * XXX: we need to update nip before the store if we enter 4793 * power saving mode, we will exit the loop directly from 4794 * ppc_store_msr 4795 */ 4796 gen_update_nip(ctx, ctx->base.pc_next); 4797 } 4798 4799 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4800 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4801 tcg_gen_or_tl(t0, t0, t1); 4802 4803 gen_helper_store_msr(tcg_env, t0); 4804 4805 /* Must stop the translation as machine state (may have) changed */ 4806 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4807 #endif /* !defined(CONFIG_USER_ONLY) */ 4808 } 4809 #endif /* defined(TARGET_PPC64) */ 4810 4811 static void gen_mtmsr(DisasContext *ctx) 4812 { 4813 CHK_SV(ctx); 4814 4815 #if !defined(CONFIG_USER_ONLY) 4816 TCGv t0, t1; 4817 target_ulong mask = 0xFFFFFFFF; 4818 4819 t0 = tcg_temp_new(); 4820 t1 = tcg_temp_new(); 4821 4822 translator_io_start(&ctx->base); 4823 if (ctx->opcode & 0x00010000) { 4824 /* L=1 form only updates EE and RI */ 4825 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4826 } else { 4827 /* mtmsr does not alter S, ME, or LE */ 4828 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4829 4830 /* 4831 * XXX: we need to update nip before the store if we enter 4832 * power saving mode, we will exit the loop directly from 4833 * ppc_store_msr 4834 */ 4835 gen_update_nip(ctx, ctx->base.pc_next); 4836 } 4837 4838 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4839 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4840 tcg_gen_or_tl(t0, t0, t1); 4841 4842 gen_helper_store_msr(tcg_env, t0); 4843 4844 /* Must stop the translation as machine state (may have) changed */ 4845 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4846 #endif 4847 } 4848 4849 /* mtspr */ 4850 static void gen_mtspr(DisasContext *ctx) 4851 { 4852 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4853 uint32_t sprn = SPR(ctx->opcode); 4854 4855 #if defined(CONFIG_USER_ONLY) 4856 write_cb = ctx->spr_cb[sprn].uea_write; 4857 #else 4858 if (ctx->pr) { 4859 write_cb = ctx->spr_cb[sprn].uea_write; 4860 } else if (ctx->hv) { 4861 write_cb = ctx->spr_cb[sprn].hea_write; 4862 } else { 4863 write_cb = ctx->spr_cb[sprn].oea_write; 4864 } 4865 #endif 4866 if (likely(write_cb != NULL)) { 4867 if (likely(write_cb != SPR_NOACCESS)) { 4868 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4869 } else { 4870 /* Privilege exception */ 4871 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4872 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4873 ctx->cia); 4874 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4875 } 4876 } else { 4877 /* ISA 2.07 defines these as no-ops */ 4878 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4879 (sprn >= 808 && sprn <= 811)) { 4880 /* This is a nop */ 4881 return; 4882 } 4883 4884 /* Not defined */ 4885 qemu_log_mask(LOG_GUEST_ERROR, 4886 "Trying to write invalid spr %d (0x%03x) at " 4887 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4888 4889 4890 /* 4891 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4892 * generate a priv, a hv emu or a no-op 4893 */ 4894 if (sprn & 0x10) { 4895 if (ctx->pr) { 4896 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4897 } 4898 } else { 4899 if (ctx->pr || sprn == 0) { 4900 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4901 } 4902 } 4903 } 4904 } 4905 4906 #if defined(TARGET_PPC64) 4907 /* setb */ 4908 static void gen_setb(DisasContext *ctx) 4909 { 4910 TCGv_i32 t0 = tcg_temp_new_i32(); 4911 TCGv_i32 t8 = tcg_constant_i32(8); 4912 TCGv_i32 tm1 = tcg_constant_i32(-1); 4913 int crf = crfS(ctx->opcode); 4914 4915 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4916 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4917 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4918 } 4919 #endif 4920 4921 /*** Cache management ***/ 4922 4923 /* dcbf */ 4924 static void gen_dcbf(DisasContext *ctx) 4925 { 4926 /* XXX: specification says this is treated as a load by the MMU */ 4927 TCGv t0; 4928 gen_set_access_type(ctx, ACCESS_CACHE); 4929 t0 = tcg_temp_new(); 4930 gen_addr_reg_index(ctx, t0); 4931 gen_qemu_ld8u(ctx, t0, t0); 4932 } 4933 4934 /* dcbfep (external PID dcbf) */ 4935 static void gen_dcbfep(DisasContext *ctx) 4936 { 4937 /* XXX: specification says this is treated as a load by the MMU */ 4938 TCGv t0; 4939 CHK_SV(ctx); 4940 gen_set_access_type(ctx, ACCESS_CACHE); 4941 t0 = tcg_temp_new(); 4942 gen_addr_reg_index(ctx, t0); 4943 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4944 } 4945 4946 /* dcbi (Supervisor only) */ 4947 static void gen_dcbi(DisasContext *ctx) 4948 { 4949 #if defined(CONFIG_USER_ONLY) 4950 GEN_PRIV(ctx); 4951 #else 4952 TCGv EA, val; 4953 4954 CHK_SV(ctx); 4955 EA = tcg_temp_new(); 4956 gen_set_access_type(ctx, ACCESS_CACHE); 4957 gen_addr_reg_index(ctx, EA); 4958 val = tcg_temp_new(); 4959 /* XXX: specification says this should be treated as a store by the MMU */ 4960 gen_qemu_ld8u(ctx, val, EA); 4961 gen_qemu_st8(ctx, val, EA); 4962 #endif /* defined(CONFIG_USER_ONLY) */ 4963 } 4964 4965 /* dcdst */ 4966 static void gen_dcbst(DisasContext *ctx) 4967 { 4968 /* XXX: specification say this is treated as a load by the MMU */ 4969 TCGv t0; 4970 gen_set_access_type(ctx, ACCESS_CACHE); 4971 t0 = tcg_temp_new(); 4972 gen_addr_reg_index(ctx, t0); 4973 gen_qemu_ld8u(ctx, t0, t0); 4974 } 4975 4976 /* dcbstep (dcbstep External PID version) */ 4977 static void gen_dcbstep(DisasContext *ctx) 4978 { 4979 /* XXX: specification say this is treated as a load by the MMU */ 4980 TCGv t0; 4981 gen_set_access_type(ctx, ACCESS_CACHE); 4982 t0 = tcg_temp_new(); 4983 gen_addr_reg_index(ctx, t0); 4984 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4985 } 4986 4987 /* dcbt */ 4988 static void gen_dcbt(DisasContext *ctx) 4989 { 4990 /* 4991 * interpreted as no-op 4992 * XXX: specification say this is treated as a load by the MMU but 4993 * does not generate any exception 4994 */ 4995 } 4996 4997 /* dcbtep */ 4998 static void gen_dcbtep(DisasContext *ctx) 4999 { 5000 /* 5001 * interpreted as no-op 5002 * XXX: specification say this is treated as a load by the MMU but 5003 * does not generate any exception 5004 */ 5005 } 5006 5007 /* dcbtst */ 5008 static void gen_dcbtst(DisasContext *ctx) 5009 { 5010 /* 5011 * interpreted as no-op 5012 * XXX: specification say this is treated as a load by the MMU but 5013 * does not generate any exception 5014 */ 5015 } 5016 5017 /* dcbtstep */ 5018 static void gen_dcbtstep(DisasContext *ctx) 5019 { 5020 /* 5021 * interpreted as no-op 5022 * XXX: specification say this is treated as a load by the MMU but 5023 * does not generate any exception 5024 */ 5025 } 5026 5027 /* dcbtls */ 5028 static void gen_dcbtls(DisasContext *ctx) 5029 { 5030 /* Always fails locking the cache */ 5031 TCGv t0 = tcg_temp_new(); 5032 gen_load_spr(t0, SPR_Exxx_L1CSR0); 5033 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5034 gen_store_spr(SPR_Exxx_L1CSR0, t0); 5035 } 5036 5037 /* dcblc */ 5038 static void gen_dcblc(DisasContext *ctx) 5039 { 5040 /* 5041 * interpreted as no-op 5042 */ 5043 } 5044 5045 /* dcbz */ 5046 static void gen_dcbz(DisasContext *ctx) 5047 { 5048 TCGv tcgv_addr; 5049 TCGv_i32 tcgv_op; 5050 5051 gen_set_access_type(ctx, ACCESS_CACHE); 5052 tcgv_addr = tcg_temp_new(); 5053 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5054 gen_addr_reg_index(ctx, tcgv_addr); 5055 gen_helper_dcbz(tcg_env, tcgv_addr, tcgv_op); 5056 } 5057 5058 /* dcbzep */ 5059 static void gen_dcbzep(DisasContext *ctx) 5060 { 5061 TCGv tcgv_addr; 5062 TCGv_i32 tcgv_op; 5063 5064 gen_set_access_type(ctx, ACCESS_CACHE); 5065 tcgv_addr = tcg_temp_new(); 5066 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5067 gen_addr_reg_index(ctx, tcgv_addr); 5068 gen_helper_dcbzep(tcg_env, tcgv_addr, tcgv_op); 5069 } 5070 5071 /* dst / dstt */ 5072 static void gen_dst(DisasContext *ctx) 5073 { 5074 if (rA(ctx->opcode) == 0) { 5075 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5076 } else { 5077 /* interpreted as no-op */ 5078 } 5079 } 5080 5081 /* dstst /dststt */ 5082 static void gen_dstst(DisasContext *ctx) 5083 { 5084 if (rA(ctx->opcode) == 0) { 5085 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5086 } else { 5087 /* interpreted as no-op */ 5088 } 5089 5090 } 5091 5092 /* dss / dssall */ 5093 static void gen_dss(DisasContext *ctx) 5094 { 5095 /* interpreted as no-op */ 5096 } 5097 5098 /* icbi */ 5099 static void gen_icbi(DisasContext *ctx) 5100 { 5101 TCGv t0; 5102 gen_set_access_type(ctx, ACCESS_CACHE); 5103 t0 = tcg_temp_new(); 5104 gen_addr_reg_index(ctx, t0); 5105 gen_helper_icbi(tcg_env, t0); 5106 } 5107 5108 /* icbiep */ 5109 static void gen_icbiep(DisasContext *ctx) 5110 { 5111 TCGv t0; 5112 gen_set_access_type(ctx, ACCESS_CACHE); 5113 t0 = tcg_temp_new(); 5114 gen_addr_reg_index(ctx, t0); 5115 gen_helper_icbiep(tcg_env, t0); 5116 } 5117 5118 /* Optional: */ 5119 /* dcba */ 5120 static void gen_dcba(DisasContext *ctx) 5121 { 5122 /* 5123 * interpreted as no-op 5124 * XXX: specification say this is treated as a store by the MMU 5125 * but does not generate any exception 5126 */ 5127 } 5128 5129 /*** Segment register manipulation ***/ 5130 /* Supervisor only: */ 5131 5132 /* mfsr */ 5133 static void gen_mfsr(DisasContext *ctx) 5134 { 5135 #if defined(CONFIG_USER_ONLY) 5136 GEN_PRIV(ctx); 5137 #else 5138 TCGv t0; 5139 5140 CHK_SV(ctx); 5141 t0 = tcg_constant_tl(SR(ctx->opcode)); 5142 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5143 #endif /* defined(CONFIG_USER_ONLY) */ 5144 } 5145 5146 /* mfsrin */ 5147 static void gen_mfsrin(DisasContext *ctx) 5148 { 5149 #if defined(CONFIG_USER_ONLY) 5150 GEN_PRIV(ctx); 5151 #else 5152 TCGv t0; 5153 5154 CHK_SV(ctx); 5155 t0 = tcg_temp_new(); 5156 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5157 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5158 #endif /* defined(CONFIG_USER_ONLY) */ 5159 } 5160 5161 /* mtsr */ 5162 static void gen_mtsr(DisasContext *ctx) 5163 { 5164 #if defined(CONFIG_USER_ONLY) 5165 GEN_PRIV(ctx); 5166 #else 5167 TCGv t0; 5168 5169 CHK_SV(ctx); 5170 t0 = tcg_constant_tl(SR(ctx->opcode)); 5171 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 5172 #endif /* defined(CONFIG_USER_ONLY) */ 5173 } 5174 5175 /* mtsrin */ 5176 static void gen_mtsrin(DisasContext *ctx) 5177 { 5178 #if defined(CONFIG_USER_ONLY) 5179 GEN_PRIV(ctx); 5180 #else 5181 TCGv t0; 5182 CHK_SV(ctx); 5183 5184 t0 = tcg_temp_new(); 5185 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5186 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rD(ctx->opcode)]); 5187 #endif /* defined(CONFIG_USER_ONLY) */ 5188 } 5189 5190 #if defined(TARGET_PPC64) 5191 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5192 5193 /* mfsr */ 5194 static void gen_mfsr_64b(DisasContext *ctx) 5195 { 5196 #if defined(CONFIG_USER_ONLY) 5197 GEN_PRIV(ctx); 5198 #else 5199 TCGv t0; 5200 5201 CHK_SV(ctx); 5202 t0 = tcg_constant_tl(SR(ctx->opcode)); 5203 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5204 #endif /* defined(CONFIG_USER_ONLY) */ 5205 } 5206 5207 /* mfsrin */ 5208 static void gen_mfsrin_64b(DisasContext *ctx) 5209 { 5210 #if defined(CONFIG_USER_ONLY) 5211 GEN_PRIV(ctx); 5212 #else 5213 TCGv t0; 5214 5215 CHK_SV(ctx); 5216 t0 = tcg_temp_new(); 5217 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5218 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5219 #endif /* defined(CONFIG_USER_ONLY) */ 5220 } 5221 5222 /* mtsr */ 5223 static void gen_mtsr_64b(DisasContext *ctx) 5224 { 5225 #if defined(CONFIG_USER_ONLY) 5226 GEN_PRIV(ctx); 5227 #else 5228 TCGv t0; 5229 5230 CHK_SV(ctx); 5231 t0 = tcg_constant_tl(SR(ctx->opcode)); 5232 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 5233 #endif /* defined(CONFIG_USER_ONLY) */ 5234 } 5235 5236 /* mtsrin */ 5237 static void gen_mtsrin_64b(DisasContext *ctx) 5238 { 5239 #if defined(CONFIG_USER_ONLY) 5240 GEN_PRIV(ctx); 5241 #else 5242 TCGv t0; 5243 5244 CHK_SV(ctx); 5245 t0 = tcg_temp_new(); 5246 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5247 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 5248 #endif /* defined(CONFIG_USER_ONLY) */ 5249 } 5250 5251 #endif /* defined(TARGET_PPC64) */ 5252 5253 /*** Lookaside buffer management ***/ 5254 /* Optional & supervisor only: */ 5255 5256 /* tlbia */ 5257 static void gen_tlbia(DisasContext *ctx) 5258 { 5259 #if defined(CONFIG_USER_ONLY) 5260 GEN_PRIV(ctx); 5261 #else 5262 CHK_HV(ctx); 5263 5264 gen_helper_tlbia(tcg_env); 5265 #endif /* defined(CONFIG_USER_ONLY) */ 5266 } 5267 5268 /* tlbsync */ 5269 static void gen_tlbsync(DisasContext *ctx) 5270 { 5271 #if defined(CONFIG_USER_ONLY) 5272 GEN_PRIV(ctx); 5273 #else 5274 5275 if (ctx->gtse) { 5276 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 5277 } else { 5278 CHK_HV(ctx); /* Else hypervisor privileged */ 5279 } 5280 5281 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5282 if (ctx->insns_flags & PPC_BOOKE) { 5283 gen_check_tlb_flush(ctx, true); 5284 } 5285 #endif /* defined(CONFIG_USER_ONLY) */ 5286 } 5287 5288 /*** External control ***/ 5289 /* Optional: */ 5290 5291 /* eciwx */ 5292 static void gen_eciwx(DisasContext *ctx) 5293 { 5294 TCGv t0; 5295 /* Should check EAR[E] ! */ 5296 gen_set_access_type(ctx, ACCESS_EXT); 5297 t0 = tcg_temp_new(); 5298 gen_addr_reg_index(ctx, t0); 5299 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5300 DEF_MEMOP(MO_UL | MO_ALIGN)); 5301 } 5302 5303 /* ecowx */ 5304 static void gen_ecowx(DisasContext *ctx) 5305 { 5306 TCGv t0; 5307 /* Should check EAR[E] ! */ 5308 gen_set_access_type(ctx, ACCESS_EXT); 5309 t0 = tcg_temp_new(); 5310 gen_addr_reg_index(ctx, t0); 5311 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5312 DEF_MEMOP(MO_UL | MO_ALIGN)); 5313 } 5314 5315 /* 602 - 603 - G2 TLB management */ 5316 5317 /* tlbld */ 5318 static void gen_tlbld_6xx(DisasContext *ctx) 5319 { 5320 #if defined(CONFIG_USER_ONLY) 5321 GEN_PRIV(ctx); 5322 #else 5323 CHK_SV(ctx); 5324 gen_helper_6xx_tlbd(tcg_env, cpu_gpr[rB(ctx->opcode)]); 5325 #endif /* defined(CONFIG_USER_ONLY) */ 5326 } 5327 5328 /* tlbli */ 5329 static void gen_tlbli_6xx(DisasContext *ctx) 5330 { 5331 #if defined(CONFIG_USER_ONLY) 5332 GEN_PRIV(ctx); 5333 #else 5334 CHK_SV(ctx); 5335 gen_helper_6xx_tlbi(tcg_env, cpu_gpr[rB(ctx->opcode)]); 5336 #endif /* defined(CONFIG_USER_ONLY) */ 5337 } 5338 5339 /* BookE specific instructions */ 5340 5341 /* XXX: not implemented on 440 ? */ 5342 static void gen_mfapidi(DisasContext *ctx) 5343 { 5344 /* XXX: TODO */ 5345 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5346 } 5347 5348 /* XXX: not implemented on 440 ? */ 5349 static void gen_tlbiva(DisasContext *ctx) 5350 { 5351 #if defined(CONFIG_USER_ONLY) 5352 GEN_PRIV(ctx); 5353 #else 5354 TCGv t0; 5355 5356 CHK_SV(ctx); 5357 t0 = tcg_temp_new(); 5358 gen_addr_reg_index(ctx, t0); 5359 gen_helper_tlbiva(tcg_env, cpu_gpr[rB(ctx->opcode)]); 5360 #endif /* defined(CONFIG_USER_ONLY) */ 5361 } 5362 5363 /* All 405 MAC instructions are translated here */ 5364 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5365 int ra, int rb, int rt, int Rc) 5366 { 5367 TCGv t0, t1; 5368 5369 t0 = tcg_temp_new(); 5370 t1 = tcg_temp_new(); 5371 5372 switch (opc3 & 0x0D) { 5373 case 0x05: 5374 /* macchw - macchw. - macchwo - macchwo. */ 5375 /* macchws - macchws. - macchwso - macchwso. */ 5376 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5377 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5378 /* mulchw - mulchw. */ 5379 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5380 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5381 tcg_gen_ext16s_tl(t1, t1); 5382 break; 5383 case 0x04: 5384 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5385 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5386 /* mulchwu - mulchwu. */ 5387 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5388 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5389 tcg_gen_ext16u_tl(t1, t1); 5390 break; 5391 case 0x01: 5392 /* machhw - machhw. - machhwo - machhwo. */ 5393 /* machhws - machhws. - machhwso - machhwso. */ 5394 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5395 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5396 /* mulhhw - mulhhw. */ 5397 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5398 tcg_gen_ext16s_tl(t0, t0); 5399 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5400 tcg_gen_ext16s_tl(t1, t1); 5401 break; 5402 case 0x00: 5403 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5404 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5405 /* mulhhwu - mulhhwu. */ 5406 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5407 tcg_gen_ext16u_tl(t0, t0); 5408 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5409 tcg_gen_ext16u_tl(t1, t1); 5410 break; 5411 case 0x0D: 5412 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5413 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5414 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5415 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5416 /* mullhw - mullhw. */ 5417 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5418 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5419 break; 5420 case 0x0C: 5421 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5422 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5423 /* mullhwu - mullhwu. */ 5424 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5425 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5426 break; 5427 } 5428 if (opc2 & 0x04) { 5429 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5430 tcg_gen_mul_tl(t1, t0, t1); 5431 if (opc2 & 0x02) { 5432 /* nmultiply-and-accumulate (0x0E) */ 5433 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5434 } else { 5435 /* multiply-and-accumulate (0x0C) */ 5436 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5437 } 5438 5439 if (opc3 & 0x12) { 5440 /* Check overflow and/or saturate */ 5441 TCGLabel *l1 = gen_new_label(); 5442 5443 if (opc3 & 0x10) { 5444 /* Start with XER OV disabled, the most likely case */ 5445 tcg_gen_movi_tl(cpu_ov, 0); 5446 } 5447 if (opc3 & 0x01) { 5448 /* Signed */ 5449 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5450 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5451 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5452 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5453 if (opc3 & 0x02) { 5454 /* Saturate */ 5455 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5456 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5457 } 5458 } else { 5459 /* Unsigned */ 5460 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5461 if (opc3 & 0x02) { 5462 /* Saturate */ 5463 tcg_gen_movi_tl(t0, UINT32_MAX); 5464 } 5465 } 5466 if (opc3 & 0x10) { 5467 /* Check overflow */ 5468 tcg_gen_movi_tl(cpu_ov, 1); 5469 tcg_gen_movi_tl(cpu_so, 1); 5470 } 5471 gen_set_label(l1); 5472 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5473 } 5474 } else { 5475 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5476 } 5477 if (unlikely(Rc) != 0) { 5478 /* Update Rc0 */ 5479 gen_set_Rc0(ctx, cpu_gpr[rt]); 5480 } 5481 } 5482 5483 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5484 static void glue(gen_, name)(DisasContext *ctx) \ 5485 { \ 5486 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5487 rD(ctx->opcode), Rc(ctx->opcode)); \ 5488 } 5489 5490 /* macchw - macchw. */ 5491 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5492 /* macchwo - macchwo. */ 5493 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5494 /* macchws - macchws. */ 5495 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5496 /* macchwso - macchwso. */ 5497 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5498 /* macchwsu - macchwsu. */ 5499 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5500 /* macchwsuo - macchwsuo. */ 5501 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5502 /* macchwu - macchwu. */ 5503 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5504 /* macchwuo - macchwuo. */ 5505 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5506 /* machhw - machhw. */ 5507 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5508 /* machhwo - machhwo. */ 5509 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5510 /* machhws - machhws. */ 5511 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5512 /* machhwso - machhwso. */ 5513 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5514 /* machhwsu - machhwsu. */ 5515 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5516 /* machhwsuo - machhwsuo. */ 5517 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5518 /* machhwu - machhwu. */ 5519 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5520 /* machhwuo - machhwuo. */ 5521 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5522 /* maclhw - maclhw. */ 5523 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5524 /* maclhwo - maclhwo. */ 5525 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5526 /* maclhws - maclhws. */ 5527 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5528 /* maclhwso - maclhwso. */ 5529 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5530 /* maclhwu - maclhwu. */ 5531 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5532 /* maclhwuo - maclhwuo. */ 5533 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5534 /* maclhwsu - maclhwsu. */ 5535 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5536 /* maclhwsuo - maclhwsuo. */ 5537 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5538 /* nmacchw - nmacchw. */ 5539 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5540 /* nmacchwo - nmacchwo. */ 5541 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5542 /* nmacchws - nmacchws. */ 5543 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5544 /* nmacchwso - nmacchwso. */ 5545 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5546 /* nmachhw - nmachhw. */ 5547 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5548 /* nmachhwo - nmachhwo. */ 5549 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5550 /* nmachhws - nmachhws. */ 5551 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5552 /* nmachhwso - nmachhwso. */ 5553 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5554 /* nmaclhw - nmaclhw. */ 5555 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5556 /* nmaclhwo - nmaclhwo. */ 5557 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5558 /* nmaclhws - nmaclhws. */ 5559 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5560 /* nmaclhwso - nmaclhwso. */ 5561 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5562 5563 /* mulchw - mulchw. */ 5564 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5565 /* mulchwu - mulchwu. */ 5566 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5567 /* mulhhw - mulhhw. */ 5568 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5569 /* mulhhwu - mulhhwu. */ 5570 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5571 /* mullhw - mullhw. */ 5572 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5573 /* mullhwu - mullhwu. */ 5574 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5575 5576 /* mfdcr */ 5577 static void gen_mfdcr(DisasContext *ctx) 5578 { 5579 #if defined(CONFIG_USER_ONLY) 5580 GEN_PRIV(ctx); 5581 #else 5582 TCGv dcrn; 5583 5584 CHK_SV(ctx); 5585 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5586 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, dcrn); 5587 #endif /* defined(CONFIG_USER_ONLY) */ 5588 } 5589 5590 /* mtdcr */ 5591 static void gen_mtdcr(DisasContext *ctx) 5592 { 5593 #if defined(CONFIG_USER_ONLY) 5594 GEN_PRIV(ctx); 5595 #else 5596 TCGv dcrn; 5597 5598 CHK_SV(ctx); 5599 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5600 gen_helper_store_dcr(tcg_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5601 #endif /* defined(CONFIG_USER_ONLY) */ 5602 } 5603 5604 /* mfdcrx */ 5605 /* XXX: not implemented on 440 ? */ 5606 static void gen_mfdcrx(DisasContext *ctx) 5607 { 5608 #if defined(CONFIG_USER_ONLY) 5609 GEN_PRIV(ctx); 5610 #else 5611 CHK_SV(ctx); 5612 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, 5613 cpu_gpr[rA(ctx->opcode)]); 5614 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5615 #endif /* defined(CONFIG_USER_ONLY) */ 5616 } 5617 5618 /* mtdcrx */ 5619 /* XXX: not implemented on 440 ? */ 5620 static void gen_mtdcrx(DisasContext *ctx) 5621 { 5622 #if defined(CONFIG_USER_ONLY) 5623 GEN_PRIV(ctx); 5624 #else 5625 CHK_SV(ctx); 5626 gen_helper_store_dcr(tcg_env, cpu_gpr[rA(ctx->opcode)], 5627 cpu_gpr[rS(ctx->opcode)]); 5628 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5629 #endif /* defined(CONFIG_USER_ONLY) */ 5630 } 5631 5632 /* dccci */ 5633 static void gen_dccci(DisasContext *ctx) 5634 { 5635 CHK_SV(ctx); 5636 /* interpreted as no-op */ 5637 } 5638 5639 /* dcread */ 5640 static void gen_dcread(DisasContext *ctx) 5641 { 5642 #if defined(CONFIG_USER_ONLY) 5643 GEN_PRIV(ctx); 5644 #else 5645 TCGv EA, val; 5646 5647 CHK_SV(ctx); 5648 gen_set_access_type(ctx, ACCESS_CACHE); 5649 EA = tcg_temp_new(); 5650 gen_addr_reg_index(ctx, EA); 5651 val = tcg_temp_new(); 5652 gen_qemu_ld32u(ctx, val, EA); 5653 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5654 #endif /* defined(CONFIG_USER_ONLY) */ 5655 } 5656 5657 /* icbt */ 5658 static void gen_icbt_40x(DisasContext *ctx) 5659 { 5660 /* 5661 * interpreted as no-op 5662 * XXX: specification say this is treated as a load by the MMU but 5663 * does not generate any exception 5664 */ 5665 } 5666 5667 /* iccci */ 5668 static void gen_iccci(DisasContext *ctx) 5669 { 5670 CHK_SV(ctx); 5671 /* interpreted as no-op */ 5672 } 5673 5674 /* icread */ 5675 static void gen_icread(DisasContext *ctx) 5676 { 5677 CHK_SV(ctx); 5678 /* interpreted as no-op */ 5679 } 5680 5681 /* rfci (supervisor only) */ 5682 static void gen_rfci_40x(DisasContext *ctx) 5683 { 5684 #if defined(CONFIG_USER_ONLY) 5685 GEN_PRIV(ctx); 5686 #else 5687 CHK_SV(ctx); 5688 /* Restore CPU state */ 5689 gen_helper_40x_rfci(tcg_env); 5690 ctx->base.is_jmp = DISAS_EXIT; 5691 #endif /* defined(CONFIG_USER_ONLY) */ 5692 } 5693 5694 static void gen_rfci(DisasContext *ctx) 5695 { 5696 #if defined(CONFIG_USER_ONLY) 5697 GEN_PRIV(ctx); 5698 #else 5699 CHK_SV(ctx); 5700 /* Restore CPU state */ 5701 gen_helper_rfci(tcg_env); 5702 ctx->base.is_jmp = DISAS_EXIT; 5703 #endif /* defined(CONFIG_USER_ONLY) */ 5704 } 5705 5706 /* BookE specific */ 5707 5708 /* XXX: not implemented on 440 ? */ 5709 static void gen_rfdi(DisasContext *ctx) 5710 { 5711 #if defined(CONFIG_USER_ONLY) 5712 GEN_PRIV(ctx); 5713 #else 5714 CHK_SV(ctx); 5715 /* Restore CPU state */ 5716 gen_helper_rfdi(tcg_env); 5717 ctx->base.is_jmp = DISAS_EXIT; 5718 #endif /* defined(CONFIG_USER_ONLY) */ 5719 } 5720 5721 /* XXX: not implemented on 440 ? */ 5722 static void gen_rfmci(DisasContext *ctx) 5723 { 5724 #if defined(CONFIG_USER_ONLY) 5725 GEN_PRIV(ctx); 5726 #else 5727 CHK_SV(ctx); 5728 /* Restore CPU state */ 5729 gen_helper_rfmci(tcg_env); 5730 ctx->base.is_jmp = DISAS_EXIT; 5731 #endif /* defined(CONFIG_USER_ONLY) */ 5732 } 5733 5734 /* TLB management - PowerPC 405 implementation */ 5735 5736 /* tlbre */ 5737 static void gen_tlbre_40x(DisasContext *ctx) 5738 { 5739 #if defined(CONFIG_USER_ONLY) 5740 GEN_PRIV(ctx); 5741 #else 5742 CHK_SV(ctx); 5743 switch (rB(ctx->opcode)) { 5744 case 0: 5745 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], tcg_env, 5746 cpu_gpr[rA(ctx->opcode)]); 5747 break; 5748 case 1: 5749 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], tcg_env, 5750 cpu_gpr[rA(ctx->opcode)]); 5751 break; 5752 default: 5753 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5754 break; 5755 } 5756 #endif /* defined(CONFIG_USER_ONLY) */ 5757 } 5758 5759 /* tlbsx - tlbsx. */ 5760 static void gen_tlbsx_40x(DisasContext *ctx) 5761 { 5762 #if defined(CONFIG_USER_ONLY) 5763 GEN_PRIV(ctx); 5764 #else 5765 TCGv t0; 5766 5767 CHK_SV(ctx); 5768 t0 = tcg_temp_new(); 5769 gen_addr_reg_index(ctx, t0); 5770 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5771 if (Rc(ctx->opcode)) { 5772 TCGLabel *l1 = gen_new_label(); 5773 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5774 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5775 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5776 gen_set_label(l1); 5777 } 5778 #endif /* defined(CONFIG_USER_ONLY) */ 5779 } 5780 5781 /* tlbwe */ 5782 static void gen_tlbwe_40x(DisasContext *ctx) 5783 { 5784 #if defined(CONFIG_USER_ONLY) 5785 GEN_PRIV(ctx); 5786 #else 5787 CHK_SV(ctx); 5788 5789 switch (rB(ctx->opcode)) { 5790 case 0: 5791 gen_helper_4xx_tlbwe_hi(tcg_env, cpu_gpr[rA(ctx->opcode)], 5792 cpu_gpr[rS(ctx->opcode)]); 5793 break; 5794 case 1: 5795 gen_helper_4xx_tlbwe_lo(tcg_env, cpu_gpr[rA(ctx->opcode)], 5796 cpu_gpr[rS(ctx->opcode)]); 5797 break; 5798 default: 5799 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5800 break; 5801 } 5802 #endif /* defined(CONFIG_USER_ONLY) */ 5803 } 5804 5805 /* TLB management - PowerPC 440 implementation */ 5806 5807 /* tlbre */ 5808 static void gen_tlbre_440(DisasContext *ctx) 5809 { 5810 #if defined(CONFIG_USER_ONLY) 5811 GEN_PRIV(ctx); 5812 #else 5813 CHK_SV(ctx); 5814 5815 switch (rB(ctx->opcode)) { 5816 case 0: 5817 case 1: 5818 case 2: 5819 { 5820 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5821 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], tcg_env, 5822 t0, cpu_gpr[rA(ctx->opcode)]); 5823 } 5824 break; 5825 default: 5826 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5827 break; 5828 } 5829 #endif /* defined(CONFIG_USER_ONLY) */ 5830 } 5831 5832 /* tlbsx - tlbsx. */ 5833 static void gen_tlbsx_440(DisasContext *ctx) 5834 { 5835 #if defined(CONFIG_USER_ONLY) 5836 GEN_PRIV(ctx); 5837 #else 5838 TCGv t0; 5839 5840 CHK_SV(ctx); 5841 t0 = tcg_temp_new(); 5842 gen_addr_reg_index(ctx, t0); 5843 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5844 if (Rc(ctx->opcode)) { 5845 TCGLabel *l1 = gen_new_label(); 5846 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5847 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5848 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5849 gen_set_label(l1); 5850 } 5851 #endif /* defined(CONFIG_USER_ONLY) */ 5852 } 5853 5854 /* tlbwe */ 5855 static void gen_tlbwe_440(DisasContext *ctx) 5856 { 5857 #if defined(CONFIG_USER_ONLY) 5858 GEN_PRIV(ctx); 5859 #else 5860 CHK_SV(ctx); 5861 switch (rB(ctx->opcode)) { 5862 case 0: 5863 case 1: 5864 case 2: 5865 { 5866 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5867 gen_helper_440_tlbwe(tcg_env, t0, cpu_gpr[rA(ctx->opcode)], 5868 cpu_gpr[rS(ctx->opcode)]); 5869 } 5870 break; 5871 default: 5872 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5873 break; 5874 } 5875 #endif /* defined(CONFIG_USER_ONLY) */ 5876 } 5877 5878 /* TLB management - PowerPC BookE 2.06 implementation */ 5879 5880 /* tlbre */ 5881 static void gen_tlbre_booke206(DisasContext *ctx) 5882 { 5883 #if defined(CONFIG_USER_ONLY) 5884 GEN_PRIV(ctx); 5885 #else 5886 CHK_SV(ctx); 5887 gen_helper_booke206_tlbre(tcg_env); 5888 #endif /* defined(CONFIG_USER_ONLY) */ 5889 } 5890 5891 /* tlbsx - tlbsx. */ 5892 static void gen_tlbsx_booke206(DisasContext *ctx) 5893 { 5894 #if defined(CONFIG_USER_ONLY) 5895 GEN_PRIV(ctx); 5896 #else 5897 TCGv t0; 5898 5899 CHK_SV(ctx); 5900 if (rA(ctx->opcode)) { 5901 t0 = tcg_temp_new(); 5902 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5903 } else { 5904 t0 = cpu_gpr[rB(ctx->opcode)]; 5905 } 5906 gen_helper_booke206_tlbsx(tcg_env, t0); 5907 #endif /* defined(CONFIG_USER_ONLY) */ 5908 } 5909 5910 /* tlbwe */ 5911 static void gen_tlbwe_booke206(DisasContext *ctx) 5912 { 5913 #if defined(CONFIG_USER_ONLY) 5914 GEN_PRIV(ctx); 5915 #else 5916 CHK_SV(ctx); 5917 gen_helper_booke206_tlbwe(tcg_env); 5918 #endif /* defined(CONFIG_USER_ONLY) */ 5919 } 5920 5921 static void gen_tlbivax_booke206(DisasContext *ctx) 5922 { 5923 #if defined(CONFIG_USER_ONLY) 5924 GEN_PRIV(ctx); 5925 #else 5926 TCGv t0; 5927 5928 CHK_SV(ctx); 5929 t0 = tcg_temp_new(); 5930 gen_addr_reg_index(ctx, t0); 5931 gen_helper_booke206_tlbivax(tcg_env, t0); 5932 #endif /* defined(CONFIG_USER_ONLY) */ 5933 } 5934 5935 static void gen_tlbilx_booke206(DisasContext *ctx) 5936 { 5937 #if defined(CONFIG_USER_ONLY) 5938 GEN_PRIV(ctx); 5939 #else 5940 TCGv t0; 5941 5942 CHK_SV(ctx); 5943 t0 = tcg_temp_new(); 5944 gen_addr_reg_index(ctx, t0); 5945 5946 switch ((ctx->opcode >> 21) & 0x3) { 5947 case 0: 5948 gen_helper_booke206_tlbilx0(tcg_env, t0); 5949 break; 5950 case 1: 5951 gen_helper_booke206_tlbilx1(tcg_env, t0); 5952 break; 5953 case 3: 5954 gen_helper_booke206_tlbilx3(tcg_env, t0); 5955 break; 5956 default: 5957 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5958 break; 5959 } 5960 #endif /* defined(CONFIG_USER_ONLY) */ 5961 } 5962 5963 /* wrtee */ 5964 static void gen_wrtee(DisasContext *ctx) 5965 { 5966 #if defined(CONFIG_USER_ONLY) 5967 GEN_PRIV(ctx); 5968 #else 5969 TCGv t0; 5970 5971 CHK_SV(ctx); 5972 t0 = tcg_temp_new(); 5973 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5974 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5975 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 5976 gen_ppc_maybe_interrupt(ctx); 5977 /* 5978 * Stop translation to have a chance to raise an exception if we 5979 * just set msr_ee to 1 5980 */ 5981 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5982 #endif /* defined(CONFIG_USER_ONLY) */ 5983 } 5984 5985 /* wrteei */ 5986 static void gen_wrteei(DisasContext *ctx) 5987 { 5988 #if defined(CONFIG_USER_ONLY) 5989 GEN_PRIV(ctx); 5990 #else 5991 CHK_SV(ctx); 5992 if (ctx->opcode & 0x00008000) { 5993 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 5994 gen_ppc_maybe_interrupt(ctx); 5995 /* Stop translation to have a chance to raise an exception */ 5996 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5997 } else { 5998 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5999 } 6000 #endif /* defined(CONFIG_USER_ONLY) */ 6001 } 6002 6003 /* PowerPC 440 specific instructions */ 6004 6005 /* dlmzb */ 6006 static void gen_dlmzb(DisasContext *ctx) 6007 { 6008 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6009 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], tcg_env, 6010 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6011 } 6012 6013 /* mbar replaces eieio on 440 */ 6014 static void gen_mbar(DisasContext *ctx) 6015 { 6016 /* interpreted as no-op */ 6017 } 6018 6019 /* msync replaces sync on 440 */ 6020 static void gen_msync_4xx(DisasContext *ctx) 6021 { 6022 /* Only e500 seems to treat reserved bits as invalid */ 6023 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 6024 (ctx->opcode & 0x03FFF801)) { 6025 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6026 } 6027 /* otherwise interpreted as no-op */ 6028 } 6029 6030 /* icbt */ 6031 static void gen_icbt_440(DisasContext *ctx) 6032 { 6033 /* 6034 * interpreted as no-op 6035 * XXX: specification say this is treated as a load by the MMU but 6036 * does not generate any exception 6037 */ 6038 } 6039 6040 #if defined(TARGET_PPC64) 6041 static void gen_maddld(DisasContext *ctx) 6042 { 6043 TCGv_i64 t1 = tcg_temp_new_i64(); 6044 6045 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6046 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6047 } 6048 6049 /* maddhd maddhdu */ 6050 static void gen_maddhd_maddhdu(DisasContext *ctx) 6051 { 6052 TCGv_i64 lo = tcg_temp_new_i64(); 6053 TCGv_i64 hi = tcg_temp_new_i64(); 6054 TCGv_i64 t1 = tcg_temp_new_i64(); 6055 6056 if (Rc(ctx->opcode)) { 6057 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6058 cpu_gpr[rB(ctx->opcode)]); 6059 tcg_gen_movi_i64(t1, 0); 6060 } else { 6061 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6062 cpu_gpr[rB(ctx->opcode)]); 6063 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6064 } 6065 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6066 cpu_gpr[rC(ctx->opcode)], t1); 6067 } 6068 #endif /* defined(TARGET_PPC64) */ 6069 6070 static void gen_tbegin(DisasContext *ctx) 6071 { 6072 if (unlikely(!ctx->tm_enabled)) { 6073 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6074 return; 6075 } 6076 gen_helper_tbegin(tcg_env); 6077 } 6078 6079 #define GEN_TM_NOOP(name) \ 6080 static inline void gen_##name(DisasContext *ctx) \ 6081 { \ 6082 if (unlikely(!ctx->tm_enabled)) { \ 6083 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6084 return; \ 6085 } \ 6086 /* \ 6087 * Because tbegin always fails in QEMU, these user \ 6088 * space instructions all have a simple implementation: \ 6089 * \ 6090 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6091 * = 0b0 || 0b00 || 0b0 \ 6092 */ \ 6093 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6094 } 6095 6096 GEN_TM_NOOP(tend); 6097 GEN_TM_NOOP(tabort); 6098 GEN_TM_NOOP(tabortwc); 6099 GEN_TM_NOOP(tabortwci); 6100 GEN_TM_NOOP(tabortdc); 6101 GEN_TM_NOOP(tabortdci); 6102 GEN_TM_NOOP(tsr); 6103 6104 static inline void gen_cp_abort(DisasContext *ctx) 6105 { 6106 /* Do Nothing */ 6107 } 6108 6109 #define GEN_CP_PASTE_NOOP(name) \ 6110 static inline void gen_##name(DisasContext *ctx) \ 6111 { \ 6112 /* \ 6113 * Generate invalid exception until we have an \ 6114 * implementation of the copy paste facility \ 6115 */ \ 6116 gen_invalid(ctx); \ 6117 } 6118 6119 GEN_CP_PASTE_NOOP(copy) 6120 GEN_CP_PASTE_NOOP(paste) 6121 6122 static void gen_tcheck(DisasContext *ctx) 6123 { 6124 if (unlikely(!ctx->tm_enabled)) { 6125 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6126 return; 6127 } 6128 /* 6129 * Because tbegin always fails, the tcheck implementation is 6130 * simple: 6131 * 6132 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6133 * = 0b1 || 0b00 || 0b0 6134 */ 6135 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6136 } 6137 6138 #if defined(CONFIG_USER_ONLY) 6139 #define GEN_TM_PRIV_NOOP(name) \ 6140 static inline void gen_##name(DisasContext *ctx) \ 6141 { \ 6142 gen_priv_opc(ctx); \ 6143 } 6144 6145 #else 6146 6147 #define GEN_TM_PRIV_NOOP(name) \ 6148 static inline void gen_##name(DisasContext *ctx) \ 6149 { \ 6150 CHK_SV(ctx); \ 6151 if (unlikely(!ctx->tm_enabled)) { \ 6152 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6153 return; \ 6154 } \ 6155 /* \ 6156 * Because tbegin always fails, the implementation is \ 6157 * simple: \ 6158 * \ 6159 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6160 * = 0b0 || 0b00 | 0b0 \ 6161 */ \ 6162 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6163 } 6164 6165 #endif 6166 6167 GEN_TM_PRIV_NOOP(treclaim); 6168 GEN_TM_PRIV_NOOP(trechkpt); 6169 6170 static inline void get_fpr(TCGv_i64 dst, int regno) 6171 { 6172 tcg_gen_ld_i64(dst, tcg_env, fpr_offset(regno)); 6173 } 6174 6175 static inline void set_fpr(int regno, TCGv_i64 src) 6176 { 6177 tcg_gen_st_i64(src, tcg_env, fpr_offset(regno)); 6178 /* 6179 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 6180 * corresponding to the target FPR was undefined. However, 6181 * most (if not all) real hardware were setting the result to 0. 6182 * Starting at ISA v3.1, the result for doubleword 1 is now defined 6183 * to be 0. 6184 */ 6185 tcg_gen_st_i64(tcg_constant_i64(0), tcg_env, vsr64_offset(regno, false)); 6186 } 6187 6188 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6189 { 6190 tcg_gen_ld_i64(dst, tcg_env, avr64_offset(regno, high)); 6191 } 6192 6193 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6194 { 6195 tcg_gen_st_i64(src, tcg_env, avr64_offset(regno, high)); 6196 } 6197 6198 /* 6199 * Helpers for decodetree used by !function for decoding arguments. 6200 */ 6201 static int times_2(DisasContext *ctx, int x) 6202 { 6203 return x * 2; 6204 } 6205 6206 static int times_4(DisasContext *ctx, int x) 6207 { 6208 return x * 4; 6209 } 6210 6211 static int times_16(DisasContext *ctx, int x) 6212 { 6213 return x * 16; 6214 } 6215 6216 static int64_t dw_compose_ea(DisasContext *ctx, int x) 6217 { 6218 return deposit64(0xfffffffffffffe00, 3, 6, x); 6219 } 6220 6221 /* 6222 * Helpers for trans_* functions to check for specific insns flags. 6223 * Use token pasting to ensure that we use the proper flag with the 6224 * proper variable. 6225 */ 6226 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6227 do { \ 6228 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6229 return false; \ 6230 } \ 6231 } while (0) 6232 6233 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6234 do { \ 6235 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6236 return false; \ 6237 } \ 6238 } while (0) 6239 6240 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6241 #if TARGET_LONG_BITS == 32 6242 # define REQUIRE_64BIT(CTX) return false 6243 #else 6244 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6245 #endif 6246 6247 #define REQUIRE_VECTOR(CTX) \ 6248 do { \ 6249 if (unlikely(!(CTX)->altivec_enabled)) { \ 6250 gen_exception((CTX), POWERPC_EXCP_VPU); \ 6251 return true; \ 6252 } \ 6253 } while (0) 6254 6255 #define REQUIRE_VSX(CTX) \ 6256 do { \ 6257 if (unlikely(!(CTX)->vsx_enabled)) { \ 6258 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 6259 return true; \ 6260 } \ 6261 } while (0) 6262 6263 #define REQUIRE_FPU(ctx) \ 6264 do { \ 6265 if (unlikely(!(ctx)->fpu_enabled)) { \ 6266 gen_exception((ctx), POWERPC_EXCP_FPU); \ 6267 return true; \ 6268 } \ 6269 } while (0) 6270 6271 #if !defined(CONFIG_USER_ONLY) 6272 #define REQUIRE_SV(CTX) \ 6273 do { \ 6274 if (unlikely((CTX)->pr)) { \ 6275 gen_priv_opc(CTX); \ 6276 return true; \ 6277 } \ 6278 } while (0) 6279 6280 #define REQUIRE_HV(CTX) \ 6281 do { \ 6282 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6283 gen_priv_opc(CTX); \ 6284 return true; \ 6285 } \ 6286 } while (0) 6287 #else 6288 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6289 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6290 #endif 6291 6292 /* 6293 * Helpers for implementing sets of trans_* functions. 6294 * Defer the implementation of NAME to FUNC, with optional extra arguments. 6295 */ 6296 #define TRANS(NAME, FUNC, ...) \ 6297 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6298 { return FUNC(ctx, a, __VA_ARGS__); } 6299 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 6300 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6301 { \ 6302 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 6303 return FUNC(ctx, a, __VA_ARGS__); \ 6304 } 6305 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6306 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6307 { \ 6308 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6309 return FUNC(ctx, a, __VA_ARGS__); \ 6310 } 6311 6312 #define TRANS64(NAME, FUNC, ...) \ 6313 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6314 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 6315 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6316 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6317 { \ 6318 REQUIRE_64BIT(ctx); \ 6319 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6320 return FUNC(ctx, a, __VA_ARGS__); \ 6321 } 6322 6323 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6324 6325 6326 #include "decode-insn32.c.inc" 6327 #include "decode-insn64.c.inc" 6328 #include "power8-pmu-regs.c.inc" 6329 6330 /* 6331 * Incorporate CIA into the constant when R=1. 6332 * Validate that when R=1, RA=0. 6333 */ 6334 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6335 { 6336 d->rt = a->rt; 6337 d->ra = a->ra; 6338 d->si = a->si; 6339 if (a->r) { 6340 if (unlikely(a->ra != 0)) { 6341 gen_invalid(ctx); 6342 return false; 6343 } 6344 d->si += ctx->cia; 6345 } 6346 return true; 6347 } 6348 6349 #include "translate/fixedpoint-impl.c.inc" 6350 6351 #include "translate/fp-impl.c.inc" 6352 6353 #include "translate/vmx-impl.c.inc" 6354 6355 #include "translate/vsx-impl.c.inc" 6356 6357 #include "translate/dfp-impl.c.inc" 6358 6359 #include "translate/spe-impl.c.inc" 6360 6361 #include "translate/branch-impl.c.inc" 6362 6363 #include "translate/processor-ctrl-impl.c.inc" 6364 6365 #include "translate/storage-ctrl-impl.c.inc" 6366 6367 /* Handles lfdp */ 6368 static void gen_dform39(DisasContext *ctx) 6369 { 6370 if ((ctx->opcode & 0x3) == 0) { 6371 if (ctx->insns_flags2 & PPC2_ISA205) { 6372 return gen_lfdp(ctx); 6373 } 6374 } 6375 return gen_invalid(ctx); 6376 } 6377 6378 /* Handles stfdp */ 6379 static void gen_dform3D(DisasContext *ctx) 6380 { 6381 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 6382 /* stfdp */ 6383 if (ctx->insns_flags2 & PPC2_ISA205) { 6384 return gen_stfdp(ctx); 6385 } 6386 } 6387 return gen_invalid(ctx); 6388 } 6389 6390 #if defined(TARGET_PPC64) 6391 /* brd */ 6392 static void gen_brd(DisasContext *ctx) 6393 { 6394 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6395 } 6396 6397 /* brw */ 6398 static void gen_brw(DisasContext *ctx) 6399 { 6400 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6401 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 6402 6403 } 6404 6405 /* brh */ 6406 static void gen_brh(DisasContext *ctx) 6407 { 6408 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 6409 TCGv_i64 t1 = tcg_temp_new_i64(); 6410 TCGv_i64 t2 = tcg_temp_new_i64(); 6411 6412 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6413 tcg_gen_and_i64(t2, t1, mask); 6414 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 6415 tcg_gen_shli_i64(t1, t1, 8); 6416 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 6417 } 6418 #endif 6419 6420 static opcode_t opcodes[] = { 6421 #if defined(TARGET_PPC64) 6422 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 6423 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 6424 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 6425 #endif 6426 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6427 #if defined(TARGET_PPC64) 6428 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6429 #endif 6430 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6431 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6432 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6433 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6434 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6435 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6436 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6437 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6438 #if defined(TARGET_PPC64) 6439 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6440 #endif 6441 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6442 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6443 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6444 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6445 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6446 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6447 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6448 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6449 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6450 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6451 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6452 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6453 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6454 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6455 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6456 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6457 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6458 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6459 #if defined(TARGET_PPC64) 6460 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6461 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6462 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6463 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6464 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6465 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6466 #endif 6467 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6468 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6469 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6470 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6471 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6472 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6473 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6474 #if defined(TARGET_PPC64) 6475 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6476 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6477 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6478 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6479 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6480 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6481 PPC_NONE, PPC2_ISA300), 6482 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6483 PPC_NONE, PPC2_ISA300), 6484 #endif 6485 /* handles lfdp, lxsd, lxssp */ 6486 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6487 /* handles stfdp, stxsd, stxssp */ 6488 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6489 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6490 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6491 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6492 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6493 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6494 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6495 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6496 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6497 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6498 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6499 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6500 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6501 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6502 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6503 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6504 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6505 #if defined(TARGET_PPC64) 6506 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6507 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6508 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6509 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6510 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6511 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6512 #endif 6513 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6514 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 6515 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 6516 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6517 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6518 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6519 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6520 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6521 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6522 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6523 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6524 #if defined(TARGET_PPC64) 6525 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6526 #if !defined(CONFIG_USER_ONLY) 6527 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6528 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6529 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6530 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 6531 #endif 6532 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6533 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6534 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6535 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6536 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6537 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6538 #endif 6539 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6540 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 6541 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6542 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6543 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6544 #if defined(TARGET_PPC64) 6545 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6546 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6547 #endif 6548 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6549 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6550 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6551 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6552 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6553 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6554 #if defined(TARGET_PPC64) 6555 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6556 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6557 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6558 #endif 6559 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6560 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6561 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6562 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6563 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6564 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6565 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6566 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6567 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6568 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6569 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6570 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6571 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6572 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6573 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6574 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6575 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6576 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6577 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6578 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6579 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6580 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6581 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6582 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6583 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6584 #if defined(TARGET_PPC64) 6585 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6586 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6587 PPC_SEGMENT_64B), 6588 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6589 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6590 PPC_SEGMENT_64B), 6591 #endif 6592 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6593 /* 6594 * XXX Those instructions will need to be handled differently for 6595 * different ISA versions 6596 */ 6597 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6598 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6599 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6600 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6601 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6602 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6603 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6604 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6605 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6606 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6607 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6608 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6609 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6610 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6611 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6612 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6613 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6614 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6615 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6616 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6617 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6618 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6619 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6620 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6621 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6622 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6623 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6624 PPC_NONE, PPC2_BOOKE206), 6625 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6626 PPC_NONE, PPC2_BOOKE206), 6627 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6628 PPC_NONE, PPC2_BOOKE206), 6629 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6630 PPC_NONE, PPC2_BOOKE206), 6631 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6632 PPC_NONE, PPC2_BOOKE206), 6633 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6634 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6635 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6636 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6637 PPC_BOOKE, PPC2_BOOKE206), 6638 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6639 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6640 PPC_BOOKE, PPC2_BOOKE206), 6641 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 6642 PPC_440_SPEC), 6643 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6644 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6645 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6646 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6647 #if defined(TARGET_PPC64) 6648 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6649 PPC2_ISA300), 6650 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6651 #endif 6652 6653 #undef GEN_INT_ARITH_DIVW 6654 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6655 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6656 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6657 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6658 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6659 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6660 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6661 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6662 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6663 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6664 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6665 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6666 6667 #if defined(TARGET_PPC64) 6668 #undef GEN_INT_ARITH_DIVD 6669 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6670 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6671 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6672 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6673 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6674 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6675 6676 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6677 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6678 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6679 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6680 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6681 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6682 6683 #undef GEN_INT_ARITH_MUL_HELPER 6684 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6685 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6686 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6687 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6688 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6689 #endif 6690 6691 #undef GEN_LOGICAL1 6692 #undef GEN_LOGICAL2 6693 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6694 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6695 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6696 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6697 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6698 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6699 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6700 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6701 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6702 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6703 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6704 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6705 #if defined(TARGET_PPC64) 6706 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6707 #endif 6708 6709 #if defined(TARGET_PPC64) 6710 #undef GEN_PPC64_R2 6711 #undef GEN_PPC64_R4 6712 #define GEN_PPC64_R2(name, opc1, opc2) \ 6713 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6714 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6715 PPC_64B) 6716 #define GEN_PPC64_R4(name, opc1, opc2) \ 6717 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6718 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6719 PPC_64B), \ 6720 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6721 PPC_64B), \ 6722 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6723 PPC_64B) 6724 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6725 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6726 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6727 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6728 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6729 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6730 #endif 6731 6732 #undef GEN_LDX_E 6733 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6734 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6735 6736 #if defined(TARGET_PPC64) 6737 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6738 6739 /* HV/P7 and later only */ 6740 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6741 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6742 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6743 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6744 #endif 6745 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6746 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6747 6748 /* External PID based load */ 6749 #undef GEN_LDEPX 6750 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6751 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6752 0x00000001, PPC_NONE, PPC2_BOOKE206), 6753 6754 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6755 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6756 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6757 #if defined(TARGET_PPC64) 6758 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6759 #endif 6760 6761 #undef GEN_STX_E 6762 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6763 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6764 6765 #if defined(TARGET_PPC64) 6766 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6767 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6768 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6769 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6770 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6771 #endif 6772 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6773 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6774 6775 #undef GEN_STEPX 6776 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6777 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6778 0x00000001, PPC_NONE, PPC2_BOOKE206), 6779 6780 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6781 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6782 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6783 #if defined(TARGET_PPC64) 6784 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6785 #endif 6786 6787 #undef GEN_CRLOGIC 6788 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6789 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6790 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6791 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6792 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6793 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6794 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6795 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6796 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6797 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6798 6799 #undef GEN_MAC_HANDLER 6800 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6801 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6802 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6803 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6804 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6805 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6806 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6807 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6808 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6809 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6810 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6811 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6812 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6813 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6814 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6815 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6816 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6817 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6818 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6819 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6820 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6821 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6822 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6823 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6824 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6825 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6826 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6827 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6828 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6829 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6830 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6831 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6832 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6833 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6834 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6835 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6836 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6837 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6838 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6839 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6840 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6841 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6842 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6843 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6844 6845 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6846 PPC_NONE, PPC2_TM), 6847 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6848 PPC_NONE, PPC2_TM), 6849 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6850 PPC_NONE, PPC2_TM), 6851 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6852 PPC_NONE, PPC2_TM), 6853 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6854 PPC_NONE, PPC2_TM), 6855 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6856 PPC_NONE, PPC2_TM), 6857 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6858 PPC_NONE, PPC2_TM), 6859 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6860 PPC_NONE, PPC2_TM), 6861 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6862 PPC_NONE, PPC2_TM), 6863 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6864 PPC_NONE, PPC2_TM), 6865 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6866 PPC_NONE, PPC2_TM), 6867 6868 #include "translate/fp-ops.c.inc" 6869 6870 #include "translate/vmx-ops.c.inc" 6871 6872 #include "translate/vsx-ops.c.inc" 6873 6874 #include "translate/spe-ops.c.inc" 6875 }; 6876 6877 /*****************************************************************************/ 6878 /* Opcode types */ 6879 enum { 6880 PPC_DIRECT = 0, /* Opcode routine */ 6881 PPC_INDIRECT = 1, /* Indirect opcode table */ 6882 }; 6883 6884 #define PPC_OPCODE_MASK 0x3 6885 6886 static inline int is_indirect_opcode(void *handler) 6887 { 6888 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6889 } 6890 6891 static inline opc_handler_t **ind_table(void *handler) 6892 { 6893 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6894 } 6895 6896 /* Instruction table creation */ 6897 /* Opcodes tables creation */ 6898 static void fill_new_table(opc_handler_t **table, int len) 6899 { 6900 int i; 6901 6902 for (i = 0; i < len; i++) { 6903 table[i] = &invalid_handler; 6904 } 6905 } 6906 6907 static int create_new_table(opc_handler_t **table, unsigned char idx) 6908 { 6909 opc_handler_t **tmp; 6910 6911 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6912 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6913 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6914 6915 return 0; 6916 } 6917 6918 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6919 opc_handler_t *handler) 6920 { 6921 if (table[idx] != &invalid_handler) { 6922 return -1; 6923 } 6924 table[idx] = handler; 6925 6926 return 0; 6927 } 6928 6929 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6930 unsigned char idx, opc_handler_t *handler) 6931 { 6932 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 6933 printf("*** ERROR: opcode %02x already assigned in main " 6934 "opcode table\n", idx); 6935 return -1; 6936 } 6937 6938 return 0; 6939 } 6940 6941 static int register_ind_in_table(opc_handler_t **table, 6942 unsigned char idx1, unsigned char idx2, 6943 opc_handler_t *handler) 6944 { 6945 if (table[idx1] == &invalid_handler) { 6946 if (create_new_table(table, idx1) < 0) { 6947 printf("*** ERROR: unable to create indirect table " 6948 "idx=%02x\n", idx1); 6949 return -1; 6950 } 6951 } else { 6952 if (!is_indirect_opcode(table[idx1])) { 6953 printf("*** ERROR: idx %02x already assigned to a direct " 6954 "opcode\n", idx1); 6955 return -1; 6956 } 6957 } 6958 if (handler != NULL && 6959 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 6960 printf("*** ERROR: opcode %02x already assigned in " 6961 "opcode table %02x\n", idx2, idx1); 6962 return -1; 6963 } 6964 6965 return 0; 6966 } 6967 6968 static int register_ind_insn(opc_handler_t **ppc_opcodes, 6969 unsigned char idx1, unsigned char idx2, 6970 opc_handler_t *handler) 6971 { 6972 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 6973 } 6974 6975 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 6976 unsigned char idx1, unsigned char idx2, 6977 unsigned char idx3, opc_handler_t *handler) 6978 { 6979 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6980 printf("*** ERROR: unable to join indirect table idx " 6981 "[%02x-%02x]\n", idx1, idx2); 6982 return -1; 6983 } 6984 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 6985 handler) < 0) { 6986 printf("*** ERROR: unable to insert opcode " 6987 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6988 return -1; 6989 } 6990 6991 return 0; 6992 } 6993 6994 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 6995 unsigned char idx1, unsigned char idx2, 6996 unsigned char idx3, unsigned char idx4, 6997 opc_handler_t *handler) 6998 { 6999 opc_handler_t **table; 7000 7001 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7002 printf("*** ERROR: unable to join indirect table idx " 7003 "[%02x-%02x]\n", idx1, idx2); 7004 return -1; 7005 } 7006 table = ind_table(ppc_opcodes[idx1]); 7007 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 7008 printf("*** ERROR: unable to join 2nd-level indirect table idx " 7009 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7010 return -1; 7011 } 7012 table = ind_table(table[idx2]); 7013 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 7014 printf("*** ERROR: unable to insert opcode " 7015 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 7016 return -1; 7017 } 7018 return 0; 7019 } 7020 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 7021 { 7022 if (insn->opc2 != 0xFF) { 7023 if (insn->opc3 != 0xFF) { 7024 if (insn->opc4 != 0xFF) { 7025 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7026 insn->opc3, insn->opc4, 7027 &insn->handler) < 0) { 7028 return -1; 7029 } 7030 } else { 7031 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7032 insn->opc3, &insn->handler) < 0) { 7033 return -1; 7034 } 7035 } 7036 } else { 7037 if (register_ind_insn(ppc_opcodes, insn->opc1, 7038 insn->opc2, &insn->handler) < 0) { 7039 return -1; 7040 } 7041 } 7042 } else { 7043 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 7044 return -1; 7045 } 7046 } 7047 7048 return 0; 7049 } 7050 7051 static int test_opcode_table(opc_handler_t **table, int len) 7052 { 7053 int i, count, tmp; 7054 7055 for (i = 0, count = 0; i < len; i++) { 7056 /* Consistency fixup */ 7057 if (table[i] == NULL) { 7058 table[i] = &invalid_handler; 7059 } 7060 if (table[i] != &invalid_handler) { 7061 if (is_indirect_opcode(table[i])) { 7062 tmp = test_opcode_table(ind_table(table[i]), 7063 PPC_CPU_INDIRECT_OPCODES_LEN); 7064 if (tmp == 0) { 7065 g_free(table[i]); 7066 table[i] = &invalid_handler; 7067 } else { 7068 count++; 7069 } 7070 } else { 7071 count++; 7072 } 7073 } 7074 } 7075 7076 return count; 7077 } 7078 7079 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 7080 { 7081 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 7082 printf("*** WARNING: no opcode defined !\n"); 7083 } 7084 } 7085 7086 /*****************************************************************************/ 7087 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 7088 { 7089 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7090 opcode_t *opc; 7091 7092 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 7093 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 7094 if (((opc->handler.type & pcc->insns_flags) != 0) || 7095 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 7096 if (register_insn(cpu->opcodes, opc) < 0) { 7097 error_setg(errp, "ERROR initializing PowerPC instruction " 7098 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 7099 opc->opc3); 7100 return; 7101 } 7102 } 7103 } 7104 fix_opcode_tables(cpu->opcodes); 7105 fflush(stdout); 7106 fflush(stderr); 7107 } 7108 7109 void destroy_ppc_opcodes(PowerPCCPU *cpu) 7110 { 7111 opc_handler_t **table, **table_2; 7112 int i, j, k; 7113 7114 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 7115 if (cpu->opcodes[i] == &invalid_handler) { 7116 continue; 7117 } 7118 if (is_indirect_opcode(cpu->opcodes[i])) { 7119 table = ind_table(cpu->opcodes[i]); 7120 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 7121 if (table[j] == &invalid_handler) { 7122 continue; 7123 } 7124 if (is_indirect_opcode(table[j])) { 7125 table_2 = ind_table(table[j]); 7126 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 7127 if (table_2[k] != &invalid_handler && 7128 is_indirect_opcode(table_2[k])) { 7129 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 7130 ~PPC_INDIRECT)); 7131 } 7132 } 7133 g_free((opc_handler_t *)((uintptr_t)table[j] & 7134 ~PPC_INDIRECT)); 7135 } 7136 } 7137 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 7138 ~PPC_INDIRECT)); 7139 } 7140 } 7141 } 7142 7143 int ppc_fixup_cpu(PowerPCCPU *cpu) 7144 { 7145 CPUPPCState *env = &cpu->env; 7146 7147 /* 7148 * TCG doesn't (yet) emulate some groups of instructions that are 7149 * implemented on some otherwise supported CPUs (e.g. VSX and 7150 * decimal floating point instructions on POWER7). We remove 7151 * unsupported instruction groups from the cpu state's instruction 7152 * masks and hope the guest can cope. For at least the pseries 7153 * machine, the unavailability of these instructions can be 7154 * advertised to the guest via the device tree. 7155 */ 7156 if ((env->insns_flags & ~PPC_TCG_INSNS) 7157 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 7158 warn_report("Disabling some instructions which are not " 7159 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 7160 env->insns_flags & ~PPC_TCG_INSNS, 7161 env->insns_flags2 & ~PPC_TCG_INSNS2); 7162 } 7163 env->insns_flags &= PPC_TCG_INSNS; 7164 env->insns_flags2 &= PPC_TCG_INSNS2; 7165 return 0; 7166 } 7167 7168 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7169 { 7170 opc_handler_t **table, *handler; 7171 uint32_t inval; 7172 7173 ctx->opcode = insn; 7174 7175 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7176 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7177 ctx->le_mode ? "little" : "big"); 7178 7179 table = cpu->opcodes; 7180 handler = table[opc1(insn)]; 7181 if (is_indirect_opcode(handler)) { 7182 table = ind_table(handler); 7183 handler = table[opc2(insn)]; 7184 if (is_indirect_opcode(handler)) { 7185 table = ind_table(handler); 7186 handler = table[opc3(insn)]; 7187 if (is_indirect_opcode(handler)) { 7188 table = ind_table(handler); 7189 handler = table[opc4(insn)]; 7190 } 7191 } 7192 } 7193 7194 /* Is opcode *REALLY* valid ? */ 7195 if (unlikely(handler->handler == &gen_invalid)) { 7196 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7197 "%02x - %02x - %02x - %02x (%08x) " 7198 TARGET_FMT_lx "\n", 7199 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7200 insn, ctx->cia); 7201 return false; 7202 } 7203 7204 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7205 && Rc(insn))) { 7206 inval = handler->inval2; 7207 } else { 7208 inval = handler->inval1; 7209 } 7210 7211 if (unlikely((insn & inval) != 0)) { 7212 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7213 "%02x - %02x - %02x - %02x (%08x) " 7214 TARGET_FMT_lx "\n", insn & inval, 7215 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7216 insn, ctx->cia); 7217 return false; 7218 } 7219 7220 handler->handler(ctx); 7221 return true; 7222 } 7223 7224 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7225 { 7226 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7227 CPUPPCState *env = cpu_env(cs); 7228 uint32_t hflags = ctx->base.tb->flags; 7229 7230 ctx->spr_cb = env->spr_cb; 7231 ctx->pr = (hflags >> HFLAGS_PR) & 1; 7232 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 7233 ctx->dr = (hflags >> HFLAGS_DR) & 1; 7234 ctx->hv = (hflags >> HFLAGS_HV) & 1; 7235 ctx->insns_flags = env->insns_flags; 7236 ctx->insns_flags2 = env->insns_flags2; 7237 ctx->access_type = -1; 7238 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 7239 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7240 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7241 ctx->flags = env->flags; 7242 #if defined(TARGET_PPC64) 7243 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7244 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7245 #endif 7246 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7247 || env->mmu_model & POWERPC_MMU_64; 7248 7249 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 7250 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 7251 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 7252 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 7253 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7254 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 7255 ctx->hr = (hflags >> HFLAGS_HR) & 1; 7256 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7257 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 7258 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 7259 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 7260 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 7261 7262 ctx->singlestep_enabled = 0; 7263 if ((hflags >> HFLAGS_SE) & 1) { 7264 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7265 ctx->base.max_insns = 1; 7266 } 7267 if ((hflags >> HFLAGS_BE) & 1) { 7268 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7269 } 7270 } 7271 7272 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7273 { 7274 } 7275 7276 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7277 { 7278 tcg_gen_insn_start(dcbase->pc_next); 7279 } 7280 7281 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 7282 { 7283 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 7284 return opc1(insn) == 1; 7285 } 7286 7287 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7288 { 7289 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7290 PowerPCCPU *cpu = POWERPC_CPU(cs); 7291 CPUPPCState *env = cpu_env(cs); 7292 target_ulong pc; 7293 uint32_t insn; 7294 bool ok; 7295 7296 LOG_DISAS("----------------\n"); 7297 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7298 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7299 7300 ctx->cia = pc = ctx->base.pc_next; 7301 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 7302 ctx->base.pc_next = pc += 4; 7303 7304 if (!is_prefix_insn(ctx, insn)) { 7305 ok = (decode_insn32(ctx, insn) || 7306 decode_legacy(cpu, ctx, insn)); 7307 } else if ((pc & 63) == 0) { 7308 /* 7309 * Power v3.1, section 1.9 Exceptions: 7310 * attempt to execute a prefixed instruction that crosses a 7311 * 64-byte address boundary (system alignment error). 7312 */ 7313 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 7314 ok = true; 7315 } else { 7316 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 7317 need_byteswap(ctx)); 7318 ctx->base.pc_next = pc += 4; 7319 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 7320 } 7321 if (!ok) { 7322 gen_invalid(ctx); 7323 } 7324 7325 /* End the TB when crossing a page boundary. */ 7326 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 7327 ctx->base.is_jmp = DISAS_TOO_MANY; 7328 } 7329 } 7330 7331 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7332 { 7333 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7334 DisasJumpType is_jmp = ctx->base.is_jmp; 7335 target_ulong nip = ctx->base.pc_next; 7336 7337 if (is_jmp == DISAS_NORETURN) { 7338 /* We have already exited the TB. */ 7339 return; 7340 } 7341 7342 /* Honor single stepping. */ 7343 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { 7344 bool rfi_type = false; 7345 7346 switch (is_jmp) { 7347 case DISAS_TOO_MANY: 7348 case DISAS_EXIT_UPDATE: 7349 case DISAS_CHAIN_UPDATE: 7350 gen_update_nip(ctx, nip); 7351 break; 7352 case DISAS_EXIT: 7353 case DISAS_CHAIN: 7354 /* 7355 * This is a heuristic, to put it kindly. The rfi class of 7356 * instructions are among the few outside branches that change 7357 * NIP without taking an interrupt. Single step trace interrupts 7358 * do not fire on completion of these instructions. 7359 */ 7360 rfi_type = true; 7361 break; 7362 default: 7363 g_assert_not_reached(); 7364 } 7365 7366 gen_debug_exception(ctx, rfi_type); 7367 return; 7368 } 7369 7370 switch (is_jmp) { 7371 case DISAS_TOO_MANY: 7372 if (use_goto_tb(ctx, nip)) { 7373 pmu_count_insns(ctx); 7374 tcg_gen_goto_tb(0); 7375 gen_update_nip(ctx, nip); 7376 tcg_gen_exit_tb(ctx->base.tb, 0); 7377 break; 7378 } 7379 /* fall through */ 7380 case DISAS_CHAIN_UPDATE: 7381 gen_update_nip(ctx, nip); 7382 /* fall through */ 7383 case DISAS_CHAIN: 7384 /* 7385 * tcg_gen_lookup_and_goto_ptr will exit the TB if 7386 * CF_NO_GOTO_PTR is set. Count insns now. 7387 */ 7388 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 7389 pmu_count_insns(ctx); 7390 } 7391 7392 tcg_gen_lookup_and_goto_ptr(); 7393 break; 7394 7395 case DISAS_EXIT_UPDATE: 7396 gen_update_nip(ctx, nip); 7397 /* fall through */ 7398 case DISAS_EXIT: 7399 pmu_count_insns(ctx); 7400 tcg_gen_exit_tb(NULL, 0); 7401 break; 7402 7403 default: 7404 g_assert_not_reached(); 7405 } 7406 } 7407 7408 static void ppc_tr_disas_log(const DisasContextBase *dcbase, 7409 CPUState *cs, FILE *logfile) 7410 { 7411 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 7412 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7413 } 7414 7415 static const TranslatorOps ppc_tr_ops = { 7416 .init_disas_context = ppc_tr_init_disas_context, 7417 .tb_start = ppc_tr_tb_start, 7418 .insn_start = ppc_tr_insn_start, 7419 .translate_insn = ppc_tr_translate_insn, 7420 .tb_stop = ppc_tr_tb_stop, 7421 .disas_log = ppc_tr_disas_log, 7422 }; 7423 7424 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7425 vaddr pc, void *host_pc) 7426 { 7427 DisasContext ctx; 7428 7429 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7430 } 7431