xref: /openbmc/qemu/target/ppc/translate.c (revision e8d1e0cd)
1 /*
2  *  PowerPC emulation for qemu: main translation routines.
3  *
4  *  Copyright (c) 2003-2007 Jocelyn Mayer
5  *  Copyright (C) 2011 Freescale Semiconductor, Inc.
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2.1 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg/tcg-op.h"
27 #include "tcg/tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "qemu/main-loop.h"
30 #include "exec/cpu_ldst.h"
31 
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34 
35 #include "exec/translator.h"
36 #include "exec/log.h"
37 #include "qemu/atomic128.h"
38 #include "spr_common.h"
39 #include "power8-pmu.h"
40 
41 #include "qemu/qemu-print.h"
42 #include "qapi/error.h"
43 
44 #define CPU_SINGLE_STEP 0x1
45 #define CPU_BRANCH_STEP 0x2
46 
47 /* Include definitions for instructions classes and implementations flags */
48 /* #define PPC_DEBUG_DISAS */
49 
50 #ifdef PPC_DEBUG_DISAS
51 #  define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
52 #else
53 #  define LOG_DISAS(...) do { } while (0)
54 #endif
55 /*****************************************************************************/
56 /* Code translation helpers                                                  */
57 
58 /* global register indexes */
59 static char cpu_reg_names[10 * 3 + 22 * 4   /* GPR */
60                           + 10 * 4 + 22 * 5 /* SPE GPRh */
61                           + 8 * 5           /* CRF */];
62 static TCGv cpu_gpr[32];
63 static TCGv cpu_gprh[32];
64 static TCGv_i32 cpu_crf[8];
65 static TCGv cpu_nip;
66 static TCGv cpu_msr;
67 static TCGv cpu_ctr;
68 static TCGv cpu_lr;
69 #if defined(TARGET_PPC64)
70 static TCGv cpu_cfar;
71 #endif
72 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
73 static TCGv cpu_reserve;
74 static TCGv cpu_reserve_val;
75 static TCGv cpu_reserve_val2;
76 static TCGv cpu_fpscr;
77 static TCGv_i32 cpu_access_type;
78 
79 #include "exec/gen-icount.h"
80 
81 void ppc_translate_init(void)
82 {
83     int i;
84     char *p;
85     size_t cpu_reg_names_size;
86 
87     p = cpu_reg_names;
88     cpu_reg_names_size = sizeof(cpu_reg_names);
89 
90     for (i = 0; i < 8; i++) {
91         snprintf(p, cpu_reg_names_size, "crf%d", i);
92         cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
93                                             offsetof(CPUPPCState, crf[i]), p);
94         p += 5;
95         cpu_reg_names_size -= 5;
96     }
97 
98     for (i = 0; i < 32; i++) {
99         snprintf(p, cpu_reg_names_size, "r%d", i);
100         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
101                                         offsetof(CPUPPCState, gpr[i]), p);
102         p += (i < 10) ? 3 : 4;
103         cpu_reg_names_size -= (i < 10) ? 3 : 4;
104         snprintf(p, cpu_reg_names_size, "r%dH", i);
105         cpu_gprh[i] = tcg_global_mem_new(cpu_env,
106                                          offsetof(CPUPPCState, gprh[i]), p);
107         p += (i < 10) ? 4 : 5;
108         cpu_reg_names_size -= (i < 10) ? 4 : 5;
109     }
110 
111     cpu_nip = tcg_global_mem_new(cpu_env,
112                                  offsetof(CPUPPCState, nip), "nip");
113 
114     cpu_msr = tcg_global_mem_new(cpu_env,
115                                  offsetof(CPUPPCState, msr), "msr");
116 
117     cpu_ctr = tcg_global_mem_new(cpu_env,
118                                  offsetof(CPUPPCState, ctr), "ctr");
119 
120     cpu_lr = tcg_global_mem_new(cpu_env,
121                                 offsetof(CPUPPCState, lr), "lr");
122 
123 #if defined(TARGET_PPC64)
124     cpu_cfar = tcg_global_mem_new(cpu_env,
125                                   offsetof(CPUPPCState, cfar), "cfar");
126 #endif
127 
128     cpu_xer = tcg_global_mem_new(cpu_env,
129                                  offsetof(CPUPPCState, xer), "xer");
130     cpu_so = tcg_global_mem_new(cpu_env,
131                                 offsetof(CPUPPCState, so), "SO");
132     cpu_ov = tcg_global_mem_new(cpu_env,
133                                 offsetof(CPUPPCState, ov), "OV");
134     cpu_ca = tcg_global_mem_new(cpu_env,
135                                 offsetof(CPUPPCState, ca), "CA");
136     cpu_ov32 = tcg_global_mem_new(cpu_env,
137                                   offsetof(CPUPPCState, ov32), "OV32");
138     cpu_ca32 = tcg_global_mem_new(cpu_env,
139                                   offsetof(CPUPPCState, ca32), "CA32");
140 
141     cpu_reserve = tcg_global_mem_new(cpu_env,
142                                      offsetof(CPUPPCState, reserve_addr),
143                                      "reserve_addr");
144     cpu_reserve_val = tcg_global_mem_new(cpu_env,
145                                          offsetof(CPUPPCState, reserve_val),
146                                          "reserve_val");
147     cpu_reserve_val2 = tcg_global_mem_new(cpu_env,
148                                           offsetof(CPUPPCState, reserve_val2),
149                                           "reserve_val2");
150 
151     cpu_fpscr = tcg_global_mem_new(cpu_env,
152                                    offsetof(CPUPPCState, fpscr), "fpscr");
153 
154     cpu_access_type = tcg_global_mem_new_i32(cpu_env,
155                                              offsetof(CPUPPCState, access_type),
156                                              "access_type");
157 }
158 
159 /* internal defines */
160 struct DisasContext {
161     DisasContextBase base;
162     target_ulong cia;  /* current instruction address */
163     uint32_t opcode;
164     /* Routine used to access memory */
165     bool pr, hv, dr, le_mode;
166     bool lazy_tlb_flush;
167     bool need_access_type;
168     int mem_idx;
169     int access_type;
170     /* Translation flags */
171     MemOp default_tcg_memop_mask;
172 #if defined(TARGET_PPC64)
173     bool sf_mode;
174     bool has_cfar;
175 #endif
176     bool fpu_enabled;
177     bool altivec_enabled;
178     bool vsx_enabled;
179     bool spe_enabled;
180     bool tm_enabled;
181     bool gtse;
182     bool hr;
183     bool mmcr0_pmcc0;
184     bool mmcr0_pmcc1;
185     bool mmcr0_pmcjce;
186     bool pmc_other;
187     bool pmu_insn_cnt;
188     ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
189     int singlestep_enabled;
190     uint32_t flags;
191     uint64_t insns_flags;
192     uint64_t insns_flags2;
193 };
194 
195 #define DISAS_EXIT         DISAS_TARGET_0  /* exit to main loop, pc updated */
196 #define DISAS_EXIT_UPDATE  DISAS_TARGET_1  /* exit to main loop, pc stale */
197 #define DISAS_CHAIN        DISAS_TARGET_2  /* lookup next tb, pc updated */
198 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3  /* lookup next tb, pc stale */
199 
200 /* Return true iff byteswap is needed in a scalar memop */
201 static inline bool need_byteswap(const DisasContext *ctx)
202 {
203 #if TARGET_BIG_ENDIAN
204      return ctx->le_mode;
205 #else
206      return !ctx->le_mode;
207 #endif
208 }
209 
210 /* True when active word size < size of target_long.  */
211 #ifdef TARGET_PPC64
212 # define NARROW_MODE(C)  (!(C)->sf_mode)
213 #else
214 # define NARROW_MODE(C)  0
215 #endif
216 
217 struct opc_handler_t {
218     /* invalid bits for instruction 1 (Rc(opcode) == 0) */
219     uint32_t inval1;
220     /* invalid bits for instruction 2 (Rc(opcode) == 1) */
221     uint32_t inval2;
222     /* instruction type */
223     uint64_t type;
224     /* extended instruction type */
225     uint64_t type2;
226     /* handler */
227     void (*handler)(DisasContext *ctx);
228 };
229 
230 /* SPR load/store helpers */
231 static inline void gen_load_spr(TCGv t, int reg)
232 {
233     tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
234 }
235 
236 static inline void gen_store_spr(int reg, TCGv t)
237 {
238     tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
239 }
240 
241 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
242 {
243     if (ctx->need_access_type && ctx->access_type != access_type) {
244         tcg_gen_movi_i32(cpu_access_type, access_type);
245         ctx->access_type = access_type;
246     }
247 }
248 
249 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
250 {
251     if (NARROW_MODE(ctx)) {
252         nip = (uint32_t)nip;
253     }
254     tcg_gen_movi_tl(cpu_nip, nip);
255 }
256 
257 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
258 {
259     TCGv_i32 t0, t1;
260 
261     /*
262      * These are all synchronous exceptions, we set the PC back to the
263      * faulting instruction
264      */
265     gen_update_nip(ctx, ctx->cia);
266     t0 = tcg_constant_i32(excp);
267     t1 = tcg_constant_i32(error);
268     gen_helper_raise_exception_err(cpu_env, t0, t1);
269     ctx->base.is_jmp = DISAS_NORETURN;
270 }
271 
272 static void gen_exception(DisasContext *ctx, uint32_t excp)
273 {
274     TCGv_i32 t0;
275 
276     /*
277      * These are all synchronous exceptions, we set the PC back to the
278      * faulting instruction
279      */
280     gen_update_nip(ctx, ctx->cia);
281     t0 = tcg_constant_i32(excp);
282     gen_helper_raise_exception(cpu_env, t0);
283     ctx->base.is_jmp = DISAS_NORETURN;
284 }
285 
286 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
287                               target_ulong nip)
288 {
289     TCGv_i32 t0;
290 
291     gen_update_nip(ctx, nip);
292     t0 = tcg_constant_i32(excp);
293     gen_helper_raise_exception(cpu_env, t0);
294     ctx->base.is_jmp = DISAS_NORETURN;
295 }
296 
297 static void gen_icount_io_start(DisasContext *ctx)
298 {
299     if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
300         gen_io_start();
301         /*
302          * An I/O instruction must be last in the TB.
303          * Chain to the next TB, and let the code from gen_tb_start
304          * decide if we need to return to the main loop.
305          * Doing this first also allows this value to be overridden.
306          */
307         ctx->base.is_jmp = DISAS_TOO_MANY;
308     }
309 }
310 
311 #if !defined(CONFIG_USER_ONLY)
312 static void gen_ppc_maybe_interrupt(DisasContext *ctx)
313 {
314     gen_icount_io_start(ctx);
315     gen_helper_ppc_maybe_interrupt(cpu_env);
316 }
317 #endif
318 
319 /*
320  * Tells the caller what is the appropriate exception to generate and prepares
321  * SPR registers for this exception.
322  *
323  * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
324  * POWERPC_EXCP_DEBUG (on BookE).
325  */
326 static uint32_t gen_prep_dbgex(DisasContext *ctx)
327 {
328     if (ctx->flags & POWERPC_FLAG_DE) {
329         target_ulong dbsr = 0;
330         if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
331             dbsr = DBCR0_ICMP;
332         } else {
333             /* Must have been branch */
334             dbsr = DBCR0_BRT;
335         }
336         TCGv t0 = tcg_temp_new();
337         gen_load_spr(t0, SPR_BOOKE_DBSR);
338         tcg_gen_ori_tl(t0, t0, dbsr);
339         gen_store_spr(SPR_BOOKE_DBSR, t0);
340         return POWERPC_EXCP_DEBUG;
341     } else {
342         return POWERPC_EXCP_TRACE;
343     }
344 }
345 
346 static void gen_debug_exception(DisasContext *ctx)
347 {
348     gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
349     ctx->base.is_jmp = DISAS_NORETURN;
350 }
351 
352 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
353 {
354     /* Will be converted to program check if needed */
355     gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
356 }
357 
358 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
359 {
360     gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
361 }
362 
363 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
364 {
365     /* Will be converted to program check if needed */
366     gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
367 }
368 
369 /*****************************************************************************/
370 /* SPR READ/WRITE CALLBACKS */
371 
372 void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
373 {
374 #if 0
375     sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
376     printf("ERROR: try to access SPR %d !\n", sprn);
377 #endif
378 }
379 
380 /* #define PPC_DUMP_SPR_ACCESSES */
381 
382 /*
383  * Generic callbacks:
384  * do nothing but store/retrieve spr value
385  */
386 static void spr_load_dump_spr(int sprn)
387 {
388 #ifdef PPC_DUMP_SPR_ACCESSES
389     TCGv_i32 t0 = tcg_constant_i32(sprn);
390     gen_helper_load_dump_spr(cpu_env, t0);
391 #endif
392 }
393 
394 void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
395 {
396     gen_load_spr(cpu_gpr[gprn], sprn);
397     spr_load_dump_spr(sprn);
398 }
399 
400 static void spr_store_dump_spr(int sprn)
401 {
402 #ifdef PPC_DUMP_SPR_ACCESSES
403     TCGv_i32 t0 = tcg_constant_i32(sprn);
404     gen_helper_store_dump_spr(cpu_env, t0);
405 #endif
406 }
407 
408 void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
409 {
410     gen_store_spr(sprn, cpu_gpr[gprn]);
411     spr_store_dump_spr(sprn);
412 }
413 
414 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
415 {
416     spr_write_generic(ctx, sprn, gprn);
417 
418     /*
419      * SPR_CTRL writes must force a new translation block,
420      * allowing the PMU to calculate the run latch events with
421      * more accuracy.
422      */
423     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
424 }
425 
426 #if !defined(CONFIG_USER_ONLY)
427 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
428 {
429 #ifdef TARGET_PPC64
430     TCGv t0 = tcg_temp_new();
431     tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
432     gen_store_spr(sprn, t0);
433     spr_store_dump_spr(sprn);
434 #else
435     spr_write_generic(ctx, sprn, gprn);
436 #endif
437 }
438 
439 void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
440 {
441     TCGv t0 = tcg_temp_new();
442     TCGv t1 = tcg_temp_new();
443     gen_load_spr(t0, sprn);
444     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
445     tcg_gen_and_tl(t0, t0, t1);
446     gen_store_spr(sprn, t0);
447 }
448 
449 void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
450 {
451 }
452 
453 #endif
454 
455 /* SPR common to all PowerPC */
456 /* XER */
457 void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
458 {
459     TCGv dst = cpu_gpr[gprn];
460     TCGv t0 = tcg_temp_new();
461     TCGv t1 = tcg_temp_new();
462     TCGv t2 = tcg_temp_new();
463     tcg_gen_mov_tl(dst, cpu_xer);
464     tcg_gen_shli_tl(t0, cpu_so, XER_SO);
465     tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
466     tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
467     tcg_gen_or_tl(t0, t0, t1);
468     tcg_gen_or_tl(dst, dst, t2);
469     tcg_gen_or_tl(dst, dst, t0);
470     if (is_isa300(ctx)) {
471         tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
472         tcg_gen_or_tl(dst, dst, t0);
473         tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
474         tcg_gen_or_tl(dst, dst, t0);
475     }
476 }
477 
478 void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
479 {
480     TCGv src = cpu_gpr[gprn];
481     /* Write all flags, while reading back check for isa300 */
482     tcg_gen_andi_tl(cpu_xer, src,
483                     ~((1u << XER_SO) |
484                       (1u << XER_OV) | (1u << XER_OV32) |
485                       (1u << XER_CA) | (1u << XER_CA32)));
486     tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
487     tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
488     tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
489     tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
490     tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
491 }
492 
493 /* LR */
494 void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
495 {
496     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
497 }
498 
499 void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
500 {
501     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
502 }
503 
504 /* CFAR */
505 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
506 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
507 {
508     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
509 }
510 
511 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
512 {
513     tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
514 }
515 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
516 
517 /* CTR */
518 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
519 {
520     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
521 }
522 
523 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
524 {
525     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
526 }
527 
528 /* User read access to SPR */
529 /* USPRx */
530 /* UMMCRx */
531 /* UPMCx */
532 /* USIA */
533 /* UDECR */
534 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
535 {
536     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
537 }
538 
539 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
540 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
541 {
542     gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
543 }
544 #endif
545 
546 /* SPR common to all non-embedded PowerPC */
547 /* DECR */
548 #if !defined(CONFIG_USER_ONLY)
549 void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
550 {
551     gen_icount_io_start(ctx);
552     gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
553 }
554 
555 void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
556 {
557     gen_icount_io_start(ctx);
558     gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
559 }
560 #endif
561 
562 /* SPR common to all non-embedded PowerPC, except 601 */
563 /* Time base */
564 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
565 {
566     gen_icount_io_start(ctx);
567     gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
568 }
569 
570 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
571 {
572     gen_icount_io_start(ctx);
573     gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
574 }
575 
576 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
577 {
578     gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
579 }
580 
581 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
582 {
583     gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
584 }
585 
586 #if !defined(CONFIG_USER_ONLY)
587 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
588 {
589     gen_icount_io_start(ctx);
590     gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
591 }
592 
593 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
594 {
595     gen_icount_io_start(ctx);
596     gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
597 }
598 
599 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
600 {
601     gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
602 }
603 
604 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
605 {
606     gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
607 }
608 
609 #if defined(TARGET_PPC64)
610 void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
611 {
612     gen_icount_io_start(ctx);
613     gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
614 }
615 
616 void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
617 {
618     gen_icount_io_start(ctx);
619     gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
620 }
621 
622 /* HDECR */
623 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
624 {
625     gen_icount_io_start(ctx);
626     gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
627 }
628 
629 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
630 {
631     gen_icount_io_start(ctx);
632     gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
633 }
634 
635 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
636 {
637     gen_icount_io_start(ctx);
638     gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
639 }
640 
641 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
642 {
643     gen_icount_io_start(ctx);
644     gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
645 }
646 
647 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
648 {
649     gen_icount_io_start(ctx);
650     gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
651 }
652 
653 #endif
654 #endif
655 
656 #if !defined(CONFIG_USER_ONLY)
657 /* IBAT0U...IBAT0U */
658 /* IBAT0L...IBAT7L */
659 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
660 {
661     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
662                   offsetof(CPUPPCState,
663                            IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
664 }
665 
666 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
667 {
668     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
669                   offsetof(CPUPPCState,
670                            IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
671 }
672 
673 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
674 {
675     TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2);
676     gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
677 }
678 
679 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
680 {
681     TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4);
682     gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
683 }
684 
685 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
686 {
687     TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2);
688     gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
689 }
690 
691 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
692 {
693     TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4);
694     gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
695 }
696 
697 /* DBAT0U...DBAT7U */
698 /* DBAT0L...DBAT7L */
699 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
700 {
701     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
702                   offsetof(CPUPPCState,
703                            DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
704 }
705 
706 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
707 {
708     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
709                   offsetof(CPUPPCState,
710                            DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
711 }
712 
713 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
714 {
715     TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2);
716     gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
717 }
718 
719 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
720 {
721     TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4);
722     gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
723 }
724 
725 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
726 {
727     TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2);
728     gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
729 }
730 
731 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
732 {
733     TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4);
734     gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
735 }
736 
737 /* SDR1 */
738 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
739 {
740     gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
741 }
742 
743 #if defined(TARGET_PPC64)
744 /* 64 bits PowerPC specific SPRs */
745 /* PIDR */
746 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
747 {
748     gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
749 }
750 
751 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
752 {
753     gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
754 }
755 
756 void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
757 {
758     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
759 }
760 
761 void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
762 {
763     TCGv t0 = tcg_temp_new();
764     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
765     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
766 }
767 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
768 {
769     gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
770 }
771 
772 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
773 {
774     gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
775 }
776 
777 /* DPDES */
778 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
779 {
780     gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
781 }
782 
783 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
784 {
785     gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
786 }
787 #endif
788 #endif
789 
790 /* PowerPC 40x specific registers */
791 #if !defined(CONFIG_USER_ONLY)
792 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
793 {
794     gen_icount_io_start(ctx);
795     gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
796 }
797 
798 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
799 {
800     gen_icount_io_start(ctx);
801     gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
802 }
803 
804 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
805 {
806     gen_icount_io_start(ctx);
807     gen_store_spr(sprn, cpu_gpr[gprn]);
808     gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
809     /* We must stop translation as we may have rebooted */
810     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
811 }
812 
813 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
814 {
815     gen_icount_io_start(ctx);
816     gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
817 }
818 
819 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
820 {
821     gen_icount_io_start(ctx);
822     gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]);
823 }
824 
825 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn)
826 {
827     gen_icount_io_start(ctx);
828     gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]);
829 }
830 
831 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
832 {
833     TCGv t0 = tcg_temp_new();
834     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF);
835     gen_helper_store_40x_pid(cpu_env, t0);
836 }
837 
838 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
839 {
840     gen_icount_io_start(ctx);
841     gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
842 }
843 
844 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
845 {
846     gen_icount_io_start(ctx);
847     gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
848 }
849 #endif
850 
851 /* PIR */
852 #if !defined(CONFIG_USER_ONLY)
853 void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
854 {
855     TCGv t0 = tcg_temp_new();
856     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
857     gen_store_spr(SPR_PIR, t0);
858 }
859 #endif
860 
861 /* SPE specific registers */
862 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
863 {
864     TCGv_i32 t0 = tcg_temp_new_i32();
865     tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
866     tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
867 }
868 
869 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
870 {
871     TCGv_i32 t0 = tcg_temp_new_i32();
872     tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
873     tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
874 }
875 
876 #if !defined(CONFIG_USER_ONLY)
877 /* Callback used to write the exception vector base */
878 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
879 {
880     TCGv t0 = tcg_temp_new();
881     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
882     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
883     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
884     gen_store_spr(sprn, t0);
885 }
886 
887 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
888 {
889     int sprn_offs;
890 
891     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
892         sprn_offs = sprn - SPR_BOOKE_IVOR0;
893     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
894         sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
895     } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
896         sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
897     } else {
898         qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception"
899                       " vector 0x%03x\n", sprn);
900         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
901         return;
902     }
903 
904     TCGv t0 = tcg_temp_new();
905     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
906     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
907     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
908     gen_store_spr(sprn, t0);
909 }
910 #endif
911 
912 #ifdef TARGET_PPC64
913 #ifndef CONFIG_USER_ONLY
914 void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
915 {
916     TCGv t0 = tcg_temp_new();
917     TCGv t1 = tcg_temp_new();
918     TCGv t2 = tcg_temp_new();
919 
920     /*
921      * Note, the HV=1 PR=0 case is handled earlier by simply using
922      * spr_write_generic for HV mode in the SPR table
923      */
924 
925     /* Build insertion mask into t1 based on context */
926     if (ctx->pr) {
927         gen_load_spr(t1, SPR_UAMOR);
928     } else {
929         gen_load_spr(t1, SPR_AMOR);
930     }
931 
932     /* Mask new bits into t2 */
933     tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
934 
935     /* Load AMR and clear new bits in t0 */
936     gen_load_spr(t0, SPR_AMR);
937     tcg_gen_andc_tl(t0, t0, t1);
938 
939     /* Or'in new bits and write it out */
940     tcg_gen_or_tl(t0, t0, t2);
941     gen_store_spr(SPR_AMR, t0);
942     spr_store_dump_spr(SPR_AMR);
943 }
944 
945 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
946 {
947     TCGv t0 = tcg_temp_new();
948     TCGv t1 = tcg_temp_new();
949     TCGv t2 = tcg_temp_new();
950 
951     /*
952      * Note, the HV=1 case is handled earlier by simply using
953      * spr_write_generic for HV mode in the SPR table
954      */
955 
956     /* Build insertion mask into t1 based on context */
957     gen_load_spr(t1, SPR_AMOR);
958 
959     /* Mask new bits into t2 */
960     tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
961 
962     /* Load AMR and clear new bits in t0 */
963     gen_load_spr(t0, SPR_UAMOR);
964     tcg_gen_andc_tl(t0, t0, t1);
965 
966     /* Or'in new bits and write it out */
967     tcg_gen_or_tl(t0, t0, t2);
968     gen_store_spr(SPR_UAMOR, t0);
969     spr_store_dump_spr(SPR_UAMOR);
970 }
971 
972 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
973 {
974     TCGv t0 = tcg_temp_new();
975     TCGv t1 = tcg_temp_new();
976     TCGv t2 = tcg_temp_new();
977 
978     /*
979      * Note, the HV=1 case is handled earlier by simply using
980      * spr_write_generic for HV mode in the SPR table
981      */
982 
983     /* Build insertion mask into t1 based on context */
984     gen_load_spr(t1, SPR_AMOR);
985 
986     /* Mask new bits into t2 */
987     tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
988 
989     /* Load AMR and clear new bits in t0 */
990     gen_load_spr(t0, SPR_IAMR);
991     tcg_gen_andc_tl(t0, t0, t1);
992 
993     /* Or'in new bits and write it out */
994     tcg_gen_or_tl(t0, t0, t2);
995     gen_store_spr(SPR_IAMR, t0);
996     spr_store_dump_spr(SPR_IAMR);
997 }
998 #endif
999 #endif
1000 
1001 #ifndef CONFIG_USER_ONLY
1002 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1003 {
1004     gen_helper_fixup_thrm(cpu_env);
1005     gen_load_spr(cpu_gpr[gprn], sprn);
1006     spr_load_dump_spr(sprn);
1007 }
1008 #endif /* !CONFIG_USER_ONLY */
1009 
1010 #if !defined(CONFIG_USER_ONLY)
1011 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1012 {
1013     TCGv t0 = tcg_temp_new();
1014 
1015     tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1016     gen_store_spr(sprn, t0);
1017 }
1018 
1019 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1020 {
1021     TCGv t0 = tcg_temp_new();
1022 
1023     tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1024     gen_store_spr(sprn, t0);
1025 }
1026 
1027 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
1028 {
1029     TCGv t0 = tcg_temp_new();
1030 
1031     tcg_gen_andi_tl(t0, cpu_gpr[gprn],
1032                     ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
1033     gen_store_spr(sprn, t0);
1034 }
1035 
1036 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1037 {
1038     gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1039 }
1040 
1041 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1042 {
1043     TCGv_i32 t0 = tcg_constant_i32(sprn);
1044     gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1045 }
1046 
1047 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1048 {
1049     gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1050 }
1051 
1052 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1053 {
1054     gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1055 }
1056 
1057 #endif
1058 
1059 #if !defined(CONFIG_USER_ONLY)
1060 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
1061 {
1062     TCGv val = tcg_temp_new();
1063     tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
1064     gen_store_spr(SPR_BOOKE_MAS3, val);
1065     tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
1066     gen_store_spr(SPR_BOOKE_MAS7, val);
1067 }
1068 
1069 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
1070 {
1071     TCGv mas7 = tcg_temp_new();
1072     TCGv mas3 = tcg_temp_new();
1073     gen_load_spr(mas7, SPR_BOOKE_MAS7);
1074     tcg_gen_shli_tl(mas7, mas7, 32);
1075     gen_load_spr(mas3, SPR_BOOKE_MAS3);
1076     tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
1077 }
1078 
1079 #endif
1080 
1081 #ifdef TARGET_PPC64
1082 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
1083                                     int bit, int sprn, int cause)
1084 {
1085     TCGv_i32 t1 = tcg_constant_i32(bit);
1086     TCGv_i32 t2 = tcg_constant_i32(sprn);
1087     TCGv_i32 t3 = tcg_constant_i32(cause);
1088 
1089     gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
1090 }
1091 
1092 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
1093                                    int bit, int sprn, int cause)
1094 {
1095     TCGv_i32 t1 = tcg_constant_i32(bit);
1096     TCGv_i32 t2 = tcg_constant_i32(sprn);
1097     TCGv_i32 t3 = tcg_constant_i32(cause);
1098 
1099     gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
1100 }
1101 
1102 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
1103 {
1104     TCGv spr_up = tcg_temp_new();
1105     TCGv spr = tcg_temp_new();
1106 
1107     gen_load_spr(spr, sprn - 1);
1108     tcg_gen_shri_tl(spr_up, spr, 32);
1109     tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
1110 }
1111 
1112 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
1113 {
1114     TCGv spr = tcg_temp_new();
1115 
1116     gen_load_spr(spr, sprn - 1);
1117     tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
1118     gen_store_spr(sprn - 1, spr);
1119 }
1120 
1121 #if !defined(CONFIG_USER_ONLY)
1122 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
1123 {
1124     TCGv hmer = tcg_temp_new();
1125 
1126     gen_load_spr(hmer, sprn);
1127     tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
1128     gen_store_spr(sprn, hmer);
1129     spr_store_dump_spr(sprn);
1130 }
1131 
1132 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
1133 {
1134     gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
1135 }
1136 #endif /* !defined(CONFIG_USER_ONLY) */
1137 
1138 void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
1139 {
1140     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1141     spr_read_generic(ctx, gprn, sprn);
1142 }
1143 
1144 void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
1145 {
1146     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1147     spr_write_generic(ctx, sprn, gprn);
1148 }
1149 
1150 void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
1151 {
1152     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1153     spr_read_generic(ctx, gprn, sprn);
1154 }
1155 
1156 void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
1157 {
1158     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1159     spr_write_generic(ctx, sprn, gprn);
1160 }
1161 
1162 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
1163 {
1164     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1165     spr_read_prev_upper32(ctx, gprn, sprn);
1166 }
1167 
1168 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
1169 {
1170     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1171     spr_write_prev_upper32(ctx, sprn, gprn);
1172 }
1173 
1174 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
1175 {
1176     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1177     spr_read_generic(ctx, gprn, sprn);
1178 }
1179 
1180 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
1181 {
1182     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1183     spr_write_generic(ctx, sprn, gprn);
1184 }
1185 
1186 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
1187 {
1188     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1189     spr_read_prev_upper32(ctx, gprn, sprn);
1190 }
1191 
1192 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
1193 {
1194     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1195     spr_write_prev_upper32(ctx, sprn, gprn);
1196 }
1197 
1198 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn)
1199 {
1200     TCGv t0 = tcg_temp_new();
1201 
1202     /*
1203      * Access to the (H)DEXCR in problem state is done using separated
1204      * SPR indexes which are 16 below the SPR indexes which have full
1205      * access to the (H)DEXCR in privileged state. Problem state can
1206      * only read bits 32:63, bits 0:31 return 0.
1207      *
1208      * See section 9.3.1-9.3.2 of PowerISA v3.1B
1209      */
1210 
1211     gen_load_spr(t0, sprn + 16);
1212     tcg_gen_ext32u_tl(cpu_gpr[gprn], t0);
1213 }
1214 #endif
1215 
1216 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
1217 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1218 
1219 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2)             \
1220 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
1221 
1222 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
1223 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1224 
1225 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2)      \
1226 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
1227 
1228 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2)     \
1229 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
1230 
1231 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
1232 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
1233 
1234 typedef struct opcode_t {
1235     unsigned char opc1, opc2, opc3, opc4;
1236 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
1237     unsigned char pad[4];
1238 #endif
1239     opc_handler_t handler;
1240     const char *oname;
1241 } opcode_t;
1242 
1243 static void gen_priv_opc(DisasContext *ctx)
1244 {
1245     gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
1246 }
1247 
1248 /* Helpers for priv. check */
1249 #define GEN_PRIV(CTX)              \
1250     do {                           \
1251         gen_priv_opc(CTX); return; \
1252     } while (0)
1253 
1254 #if defined(CONFIG_USER_ONLY)
1255 #define CHK_HV(CTX) GEN_PRIV(CTX)
1256 #define CHK_SV(CTX) GEN_PRIV(CTX)
1257 #define CHK_HVRM(CTX) GEN_PRIV(CTX)
1258 #else
1259 #define CHK_HV(CTX)                         \
1260     do {                                    \
1261         if (unlikely(ctx->pr || !ctx->hv)) {\
1262             GEN_PRIV(CTX);                  \
1263         }                                   \
1264     } while (0)
1265 #define CHK_SV(CTX)              \
1266     do {                         \
1267         if (unlikely(ctx->pr)) { \
1268             GEN_PRIV(CTX);       \
1269         }                        \
1270     } while (0)
1271 #define CHK_HVRM(CTX)                                   \
1272     do {                                                \
1273         if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
1274             GEN_PRIV(CTX);                              \
1275         }                                               \
1276     } while (0)
1277 #endif
1278 
1279 #define CHK_NONE(CTX)
1280 
1281 /*****************************************************************************/
1282 /* PowerPC instructions table                                                */
1283 
1284 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)                    \
1285 {                                                                             \
1286     .opc1 = op1,                                                              \
1287     .opc2 = op2,                                                              \
1288     .opc3 = op3,                                                              \
1289     .opc4 = 0xff,                                                             \
1290     .handler = {                                                              \
1291         .inval1  = invl,                                                      \
1292         .type = _typ,                                                         \
1293         .type2 = _typ2,                                                       \
1294         .handler = &gen_##name,                                               \
1295     },                                                                        \
1296     .oname = stringify(name),                                                 \
1297 }
1298 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2)       \
1299 {                                                                             \
1300     .opc1 = op1,                                                              \
1301     .opc2 = op2,                                                              \
1302     .opc3 = op3,                                                              \
1303     .opc4 = 0xff,                                                             \
1304     .handler = {                                                              \
1305         .inval1  = invl1,                                                     \
1306         .inval2  = invl2,                                                     \
1307         .type = _typ,                                                         \
1308         .type2 = _typ2,                                                       \
1309         .handler = &gen_##name,                                               \
1310     },                                                                        \
1311     .oname = stringify(name),                                                 \
1312 }
1313 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2)             \
1314 {                                                                             \
1315     .opc1 = op1,                                                              \
1316     .opc2 = op2,                                                              \
1317     .opc3 = op3,                                                              \
1318     .opc4 = 0xff,                                                             \
1319     .handler = {                                                              \
1320         .inval1  = invl,                                                      \
1321         .type = _typ,                                                         \
1322         .type2 = _typ2,                                                       \
1323         .handler = &gen_##name,                                               \
1324     },                                                                        \
1325     .oname = onam,                                                            \
1326 }
1327 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2)              \
1328 {                                                                             \
1329     .opc1 = op1,                                                              \
1330     .opc2 = op2,                                                              \
1331     .opc3 = op3,                                                              \
1332     .opc4 = op4,                                                              \
1333     .handler = {                                                              \
1334         .inval1  = invl,                                                      \
1335         .type = _typ,                                                         \
1336         .type2 = _typ2,                                                       \
1337         .handler = &gen_##name,                                               \
1338     },                                                                        \
1339     .oname = stringify(name),                                                 \
1340 }
1341 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2)        \
1342 {                                                                             \
1343     .opc1 = op1,                                                              \
1344     .opc2 = op2,                                                              \
1345     .opc3 = op3,                                                              \
1346     .opc4 = op4,                                                              \
1347     .handler = {                                                              \
1348         .inval1  = invl,                                                      \
1349         .type = _typ,                                                         \
1350         .type2 = _typ2,                                                       \
1351         .handler = &gen_##name,                                               \
1352     },                                                                        \
1353     .oname = onam,                                                            \
1354 }
1355 
1356 /* Invalid instruction */
1357 static void gen_invalid(DisasContext *ctx)
1358 {
1359     gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
1360 }
1361 
1362 static opc_handler_t invalid_handler = {
1363     .inval1  = 0xFFFFFFFF,
1364     .inval2  = 0xFFFFFFFF,
1365     .type    = PPC_NONE,
1366     .type2   = PPC_NONE,
1367     .handler = gen_invalid,
1368 };
1369 
1370 /***                           Integer comparison                          ***/
1371 
1372 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
1373 {
1374     TCGv t0 = tcg_temp_new();
1375     TCGv t1 = tcg_temp_new();
1376     TCGv_i32 t = tcg_temp_new_i32();
1377 
1378     tcg_gen_movi_tl(t0, CRF_EQ);
1379     tcg_gen_movi_tl(t1, CRF_LT);
1380     tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU),
1381                        t0, arg0, arg1, t1, t0);
1382     tcg_gen_movi_tl(t1, CRF_GT);
1383     tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU),
1384                        t0, arg0, arg1, t1, t0);
1385 
1386     tcg_gen_trunc_tl_i32(t, t0);
1387     tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
1388     tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
1389 }
1390 
1391 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
1392 {
1393     TCGv t0 = tcg_constant_tl(arg1);
1394     gen_op_cmp(arg0, t0, s, crf);
1395 }
1396 
1397 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
1398 {
1399     TCGv t0, t1;
1400     t0 = tcg_temp_new();
1401     t1 = tcg_temp_new();
1402     if (s) {
1403         tcg_gen_ext32s_tl(t0, arg0);
1404         tcg_gen_ext32s_tl(t1, arg1);
1405     } else {
1406         tcg_gen_ext32u_tl(t0, arg0);
1407         tcg_gen_ext32u_tl(t1, arg1);
1408     }
1409     gen_op_cmp(t0, t1, s, crf);
1410 }
1411 
1412 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
1413 {
1414     TCGv t0 = tcg_constant_tl(arg1);
1415     gen_op_cmp32(arg0, t0, s, crf);
1416 }
1417 
1418 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
1419 {
1420     if (NARROW_MODE(ctx)) {
1421         gen_op_cmpi32(reg, 0, 1, 0);
1422     } else {
1423         gen_op_cmpi(reg, 0, 1, 0);
1424     }
1425 }
1426 
1427 /* cmprb - range comparison: isupper, isaplha, islower*/
1428 static void gen_cmprb(DisasContext *ctx)
1429 {
1430     TCGv_i32 src1 = tcg_temp_new_i32();
1431     TCGv_i32 src2 = tcg_temp_new_i32();
1432     TCGv_i32 src2lo = tcg_temp_new_i32();
1433     TCGv_i32 src2hi = tcg_temp_new_i32();
1434     TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
1435 
1436     tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
1437     tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
1438 
1439     tcg_gen_andi_i32(src1, src1, 0xFF);
1440     tcg_gen_ext8u_i32(src2lo, src2);
1441     tcg_gen_shri_i32(src2, src2, 8);
1442     tcg_gen_ext8u_i32(src2hi, src2);
1443 
1444     tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1445     tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1446     tcg_gen_and_i32(crf, src2lo, src2hi);
1447 
1448     if (ctx->opcode & 0x00200000) {
1449         tcg_gen_shri_i32(src2, src2, 8);
1450         tcg_gen_ext8u_i32(src2lo, src2);
1451         tcg_gen_shri_i32(src2, src2, 8);
1452         tcg_gen_ext8u_i32(src2hi, src2);
1453         tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1454         tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1455         tcg_gen_and_i32(src2lo, src2lo, src2hi);
1456         tcg_gen_or_i32(crf, crf, src2lo);
1457     }
1458     tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
1459 }
1460 
1461 #if defined(TARGET_PPC64)
1462 /* cmpeqb */
1463 static void gen_cmpeqb(DisasContext *ctx)
1464 {
1465     gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1466                       cpu_gpr[rB(ctx->opcode)]);
1467 }
1468 #endif
1469 
1470 /* isel (PowerPC 2.03 specification) */
1471 static void gen_isel(DisasContext *ctx)
1472 {
1473     uint32_t bi = rC(ctx->opcode);
1474     uint32_t mask = 0x08 >> (bi & 0x03);
1475     TCGv t0 = tcg_temp_new();
1476     TCGv zr;
1477 
1478     tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
1479     tcg_gen_andi_tl(t0, t0, mask);
1480 
1481     zr = tcg_constant_tl(0);
1482     tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
1483                        rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
1484                        cpu_gpr[rB(ctx->opcode)]);
1485 }
1486 
1487 /* cmpb: PowerPC 2.05 specification */
1488 static void gen_cmpb(DisasContext *ctx)
1489 {
1490     gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1491                     cpu_gpr[rB(ctx->opcode)]);
1492 }
1493 
1494 /***                           Integer arithmetic                          ***/
1495 
1496 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
1497                                            TCGv arg1, TCGv arg2, int sub)
1498 {
1499     TCGv t0 = tcg_temp_new();
1500 
1501     tcg_gen_xor_tl(cpu_ov, arg0, arg2);
1502     tcg_gen_xor_tl(t0, arg1, arg2);
1503     if (sub) {
1504         tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
1505     } else {
1506         tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
1507     }
1508     if (NARROW_MODE(ctx)) {
1509         tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
1510         if (is_isa300(ctx)) {
1511             tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1512         }
1513     } else {
1514         if (is_isa300(ctx)) {
1515             tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
1516         }
1517         tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
1518     }
1519     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1520 }
1521 
1522 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
1523                                              TCGv res, TCGv arg0, TCGv arg1,
1524                                              TCGv ca32, int sub)
1525 {
1526     TCGv t0;
1527 
1528     if (!is_isa300(ctx)) {
1529         return;
1530     }
1531 
1532     t0 = tcg_temp_new();
1533     if (sub) {
1534         tcg_gen_eqv_tl(t0, arg0, arg1);
1535     } else {
1536         tcg_gen_xor_tl(t0, arg0, arg1);
1537     }
1538     tcg_gen_xor_tl(t0, t0, res);
1539     tcg_gen_extract_tl(ca32, t0, 32, 1);
1540 }
1541 
1542 /* Common add function */
1543 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
1544                                     TCGv arg2, TCGv ca, TCGv ca32,
1545                                     bool add_ca, bool compute_ca,
1546                                     bool compute_ov, bool compute_rc0)
1547 {
1548     TCGv t0 = ret;
1549 
1550     if (compute_ca || compute_ov) {
1551         t0 = tcg_temp_new();
1552     }
1553 
1554     if (compute_ca) {
1555         if (NARROW_MODE(ctx)) {
1556             /*
1557              * Caution: a non-obvious corner case of the spec is that
1558              * we must produce the *entire* 64-bit addition, but
1559              * produce the carry into bit 32.
1560              */
1561             TCGv t1 = tcg_temp_new();
1562             tcg_gen_xor_tl(t1, arg1, arg2);        /* add without carry */
1563             tcg_gen_add_tl(t0, arg1, arg2);
1564             if (add_ca) {
1565                 tcg_gen_add_tl(t0, t0, ca);
1566             }
1567             tcg_gen_xor_tl(ca, t0, t1);        /* bits changed w/ carry */
1568             tcg_gen_extract_tl(ca, ca, 32, 1);
1569             if (is_isa300(ctx)) {
1570                 tcg_gen_mov_tl(ca32, ca);
1571             }
1572         } else {
1573             TCGv zero = tcg_constant_tl(0);
1574             if (add_ca) {
1575                 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
1576                 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
1577             } else {
1578                 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
1579             }
1580             gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
1581         }
1582     } else {
1583         tcg_gen_add_tl(t0, arg1, arg2);
1584         if (add_ca) {
1585             tcg_gen_add_tl(t0, t0, ca);
1586         }
1587     }
1588 
1589     if (compute_ov) {
1590         gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
1591     }
1592     if (unlikely(compute_rc0)) {
1593         gen_set_Rc0(ctx, t0);
1594     }
1595 
1596     if (t0 != ret) {
1597         tcg_gen_mov_tl(ret, t0);
1598     }
1599 }
1600 /* Add functions with two operands */
1601 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov)     \
1602 static void glue(gen_, name)(DisasContext *ctx)                               \
1603 {                                                                             \
1604     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
1605                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
1606                      ca, glue(ca, 32),                                        \
1607                      add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \
1608 }
1609 /* Add functions with one operand and one immediate */
1610 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca,                    \
1611                                 add_ca, compute_ca, compute_ov)               \
1612 static void glue(gen_, name)(DisasContext *ctx)                               \
1613 {                                                                             \
1614     TCGv t0 = tcg_constant_tl(const_val);                                     \
1615     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
1616                      cpu_gpr[rA(ctx->opcode)], t0,                            \
1617                      ca, glue(ca, 32),                                        \
1618                      add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \
1619 }
1620 
1621 /* add  add.  addo  addo. */
1622 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
1623 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
1624 /* addc  addc.  addco  addco. */
1625 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
1626 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
1627 /* adde  adde.  addeo  addeo. */
1628 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
1629 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
1630 /* addme  addme.  addmeo  addmeo.  */
1631 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
1632 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
1633 /* addex */
1634 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
1635 /* addze  addze.  addzeo  addzeo.*/
1636 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
1637 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
1638 /* addic  addic.*/
1639 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1640 {
1641     TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
1642     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1643                      c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
1644 }
1645 
1646 static void gen_addic(DisasContext *ctx)
1647 {
1648     gen_op_addic(ctx, 0);
1649 }
1650 
1651 static void gen_addic_(DisasContext *ctx)
1652 {
1653     gen_op_addic(ctx, 1);
1654 }
1655 
1656 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1657                                      TCGv arg2, int sign, int compute_ov)
1658 {
1659     TCGv_i32 t0 = tcg_temp_new_i32();
1660     TCGv_i32 t1 = tcg_temp_new_i32();
1661     TCGv_i32 t2 = tcg_temp_new_i32();
1662     TCGv_i32 t3 = tcg_temp_new_i32();
1663 
1664     tcg_gen_trunc_tl_i32(t0, arg1);
1665     tcg_gen_trunc_tl_i32(t1, arg2);
1666     if (sign) {
1667         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1668         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1669         tcg_gen_and_i32(t2, t2, t3);
1670         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1671         tcg_gen_or_i32(t2, t2, t3);
1672         tcg_gen_movi_i32(t3, 0);
1673         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1674         tcg_gen_div_i32(t3, t0, t1);
1675         tcg_gen_extu_i32_tl(ret, t3);
1676     } else {
1677         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1678         tcg_gen_movi_i32(t3, 0);
1679         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1680         tcg_gen_divu_i32(t3, t0, t1);
1681         tcg_gen_extu_i32_tl(ret, t3);
1682     }
1683     if (compute_ov) {
1684         tcg_gen_extu_i32_tl(cpu_ov, t2);
1685         if (is_isa300(ctx)) {
1686             tcg_gen_extu_i32_tl(cpu_ov32, t2);
1687         }
1688         tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1689     }
1690 
1691     if (unlikely(Rc(ctx->opcode) != 0)) {
1692         gen_set_Rc0(ctx, ret);
1693     }
1694 }
1695 /* Div functions */
1696 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
1697 static void glue(gen_, name)(DisasContext *ctx)                               \
1698 {                                                                             \
1699     gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1700                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
1701                      sign, compute_ov);                                       \
1702 }
1703 /* divwu  divwu.  divwuo  divwuo.   */
1704 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1705 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1706 /* divw  divw.  divwo  divwo.   */
1707 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1708 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1709 
1710 /* div[wd]eu[o][.] */
1711 #define GEN_DIVE(name, hlpr, compute_ov)                                      \
1712 static void gen_##name(DisasContext *ctx)                                     \
1713 {                                                                             \
1714     TCGv_i32 t0 = tcg_constant_i32(compute_ov);                               \
1715     gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env,                      \
1716                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1717     if (unlikely(Rc(ctx->opcode) != 0)) {                                     \
1718         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);                           \
1719     }                                                                         \
1720 }
1721 
1722 GEN_DIVE(divweu, divweu, 0);
1723 GEN_DIVE(divweuo, divweu, 1);
1724 GEN_DIVE(divwe, divwe, 0);
1725 GEN_DIVE(divweo, divwe, 1);
1726 
1727 #if defined(TARGET_PPC64)
1728 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1729                                      TCGv arg2, int sign, int compute_ov)
1730 {
1731     TCGv_i64 t0 = tcg_temp_new_i64();
1732     TCGv_i64 t1 = tcg_temp_new_i64();
1733     TCGv_i64 t2 = tcg_temp_new_i64();
1734     TCGv_i64 t3 = tcg_temp_new_i64();
1735 
1736     tcg_gen_mov_i64(t0, arg1);
1737     tcg_gen_mov_i64(t1, arg2);
1738     if (sign) {
1739         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1740         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1741         tcg_gen_and_i64(t2, t2, t3);
1742         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1743         tcg_gen_or_i64(t2, t2, t3);
1744         tcg_gen_movi_i64(t3, 0);
1745         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1746         tcg_gen_div_i64(ret, t0, t1);
1747     } else {
1748         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1749         tcg_gen_movi_i64(t3, 0);
1750         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1751         tcg_gen_divu_i64(ret, t0, t1);
1752     }
1753     if (compute_ov) {
1754         tcg_gen_mov_tl(cpu_ov, t2);
1755         if (is_isa300(ctx)) {
1756             tcg_gen_mov_tl(cpu_ov32, t2);
1757         }
1758         tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1759     }
1760 
1761     if (unlikely(Rc(ctx->opcode) != 0)) {
1762         gen_set_Rc0(ctx, ret);
1763     }
1764 }
1765 
1766 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
1767 static void glue(gen_, name)(DisasContext *ctx)                               \
1768 {                                                                             \
1769     gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1770                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1771                       sign, compute_ov);                                      \
1772 }
1773 /* divdu  divdu.  divduo  divduo.   */
1774 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1775 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1776 /* divd  divd.  divdo  divdo.   */
1777 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1778 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1779 
1780 GEN_DIVE(divdeu, divdeu, 0);
1781 GEN_DIVE(divdeuo, divdeu, 1);
1782 GEN_DIVE(divde, divde, 0);
1783 GEN_DIVE(divdeo, divde, 1);
1784 #endif
1785 
1786 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1787                                      TCGv arg2, int sign)
1788 {
1789     TCGv_i32 t0 = tcg_temp_new_i32();
1790     TCGv_i32 t1 = tcg_temp_new_i32();
1791 
1792     tcg_gen_trunc_tl_i32(t0, arg1);
1793     tcg_gen_trunc_tl_i32(t1, arg2);
1794     if (sign) {
1795         TCGv_i32 t2 = tcg_temp_new_i32();
1796         TCGv_i32 t3 = tcg_temp_new_i32();
1797         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1798         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1799         tcg_gen_and_i32(t2, t2, t3);
1800         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1801         tcg_gen_or_i32(t2, t2, t3);
1802         tcg_gen_movi_i32(t3, 0);
1803         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1804         tcg_gen_rem_i32(t3, t0, t1);
1805         tcg_gen_ext_i32_tl(ret, t3);
1806     } else {
1807         TCGv_i32 t2 = tcg_constant_i32(1);
1808         TCGv_i32 t3 = tcg_constant_i32(0);
1809         tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1810         tcg_gen_remu_i32(t3, t0, t1);
1811         tcg_gen_extu_i32_tl(ret, t3);
1812     }
1813 }
1814 
1815 #define GEN_INT_ARITH_MODW(name, opc3, sign)                                \
1816 static void glue(gen_, name)(DisasContext *ctx)                             \
1817 {                                                                           \
1818     gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)],                        \
1819                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],   \
1820                       sign);                                                \
1821 }
1822 
1823 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1824 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1825 
1826 #if defined(TARGET_PPC64)
1827 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1828                                      TCGv arg2, int sign)
1829 {
1830     TCGv_i64 t0 = tcg_temp_new_i64();
1831     TCGv_i64 t1 = tcg_temp_new_i64();
1832 
1833     tcg_gen_mov_i64(t0, arg1);
1834     tcg_gen_mov_i64(t1, arg2);
1835     if (sign) {
1836         TCGv_i64 t2 = tcg_temp_new_i64();
1837         TCGv_i64 t3 = tcg_temp_new_i64();
1838         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1839         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1840         tcg_gen_and_i64(t2, t2, t3);
1841         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1842         tcg_gen_or_i64(t2, t2, t3);
1843         tcg_gen_movi_i64(t3, 0);
1844         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1845         tcg_gen_rem_i64(ret, t0, t1);
1846     } else {
1847         TCGv_i64 t2 = tcg_constant_i64(1);
1848         TCGv_i64 t3 = tcg_constant_i64(0);
1849         tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1850         tcg_gen_remu_i64(ret, t0, t1);
1851     }
1852 }
1853 
1854 #define GEN_INT_ARITH_MODD(name, opc3, sign)                            \
1855 static void glue(gen_, name)(DisasContext *ctx)                           \
1856 {                                                                         \
1857   gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)],                        \
1858                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],   \
1859                     sign);                                                \
1860 }
1861 
1862 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1863 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1864 #endif
1865 
1866 /* mulhw  mulhw. */
1867 static void gen_mulhw(DisasContext *ctx)
1868 {
1869     TCGv_i32 t0 = tcg_temp_new_i32();
1870     TCGv_i32 t1 = tcg_temp_new_i32();
1871 
1872     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1873     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1874     tcg_gen_muls2_i32(t0, t1, t0, t1);
1875     tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1876     if (unlikely(Rc(ctx->opcode) != 0)) {
1877         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1878     }
1879 }
1880 
1881 /* mulhwu  mulhwu.  */
1882 static void gen_mulhwu(DisasContext *ctx)
1883 {
1884     TCGv_i32 t0 = tcg_temp_new_i32();
1885     TCGv_i32 t1 = tcg_temp_new_i32();
1886 
1887     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1888     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1889     tcg_gen_mulu2_i32(t0, t1, t0, t1);
1890     tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1891     if (unlikely(Rc(ctx->opcode) != 0)) {
1892         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1893     }
1894 }
1895 
1896 /* mullw  mullw. */
1897 static void gen_mullw(DisasContext *ctx)
1898 {
1899 #if defined(TARGET_PPC64)
1900     TCGv_i64 t0, t1;
1901     t0 = tcg_temp_new_i64();
1902     t1 = tcg_temp_new_i64();
1903     tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1904     tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1905     tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1906 #else
1907     tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1908                     cpu_gpr[rB(ctx->opcode)]);
1909 #endif
1910     if (unlikely(Rc(ctx->opcode) != 0)) {
1911         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1912     }
1913 }
1914 
1915 /* mullwo  mullwo. */
1916 static void gen_mullwo(DisasContext *ctx)
1917 {
1918     TCGv_i32 t0 = tcg_temp_new_i32();
1919     TCGv_i32 t1 = tcg_temp_new_i32();
1920 
1921     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1922     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1923     tcg_gen_muls2_i32(t0, t1, t0, t1);
1924 #if defined(TARGET_PPC64)
1925     tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1926 #else
1927     tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1928 #endif
1929 
1930     tcg_gen_sari_i32(t0, t0, 31);
1931     tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1932     tcg_gen_extu_i32_tl(cpu_ov, t0);
1933     if (is_isa300(ctx)) {
1934         tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1935     }
1936     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1937 
1938     if (unlikely(Rc(ctx->opcode) != 0)) {
1939         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1940     }
1941 }
1942 
1943 /* mulli */
1944 static void gen_mulli(DisasContext *ctx)
1945 {
1946     tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1947                     SIMM(ctx->opcode));
1948 }
1949 
1950 #if defined(TARGET_PPC64)
1951 /* mulhd  mulhd. */
1952 static void gen_mulhd(DisasContext *ctx)
1953 {
1954     TCGv lo = tcg_temp_new();
1955     tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1956                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1957     if (unlikely(Rc(ctx->opcode) != 0)) {
1958         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1959     }
1960 }
1961 
1962 /* mulhdu  mulhdu. */
1963 static void gen_mulhdu(DisasContext *ctx)
1964 {
1965     TCGv lo = tcg_temp_new();
1966     tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1967                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1968     if (unlikely(Rc(ctx->opcode) != 0)) {
1969         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1970     }
1971 }
1972 
1973 /* mulld  mulld. */
1974 static void gen_mulld(DisasContext *ctx)
1975 {
1976     tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1977                    cpu_gpr[rB(ctx->opcode)]);
1978     if (unlikely(Rc(ctx->opcode) != 0)) {
1979         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1980     }
1981 }
1982 
1983 /* mulldo  mulldo. */
1984 static void gen_mulldo(DisasContext *ctx)
1985 {
1986     TCGv_i64 t0 = tcg_temp_new_i64();
1987     TCGv_i64 t1 = tcg_temp_new_i64();
1988 
1989     tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1990                       cpu_gpr[rB(ctx->opcode)]);
1991     tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1992 
1993     tcg_gen_sari_i64(t0, t0, 63);
1994     tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1995     if (is_isa300(ctx)) {
1996         tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1997     }
1998     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1999 
2000     if (unlikely(Rc(ctx->opcode) != 0)) {
2001         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2002     }
2003 }
2004 #endif
2005 
2006 /* Common subf function */
2007 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
2008                                      TCGv arg2, bool add_ca, bool compute_ca,
2009                                      bool compute_ov, bool compute_rc0)
2010 {
2011     TCGv t0 = ret;
2012 
2013     if (compute_ca || compute_ov) {
2014         t0 = tcg_temp_new();
2015     }
2016 
2017     if (compute_ca) {
2018         /* dest = ~arg1 + arg2 [+ ca].  */
2019         if (NARROW_MODE(ctx)) {
2020             /*
2021              * Caution: a non-obvious corner case of the spec is that
2022              * we must produce the *entire* 64-bit addition, but
2023              * produce the carry into bit 32.
2024              */
2025             TCGv inv1 = tcg_temp_new();
2026             TCGv t1 = tcg_temp_new();
2027             tcg_gen_not_tl(inv1, arg1);
2028             if (add_ca) {
2029                 tcg_gen_add_tl(t0, arg2, cpu_ca);
2030             } else {
2031                 tcg_gen_addi_tl(t0, arg2, 1);
2032             }
2033             tcg_gen_xor_tl(t1, arg2, inv1);         /* add without carry */
2034             tcg_gen_add_tl(t0, t0, inv1);
2035             tcg_gen_xor_tl(cpu_ca, t0, t1);         /* bits changes w/ carry */
2036             tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
2037             if (is_isa300(ctx)) {
2038                 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2039             }
2040         } else if (add_ca) {
2041             TCGv zero, inv1 = tcg_temp_new();
2042             tcg_gen_not_tl(inv1, arg1);
2043             zero = tcg_constant_tl(0);
2044             tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
2045             tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
2046             gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
2047         } else {
2048             tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
2049             tcg_gen_sub_tl(t0, arg2, arg1);
2050             gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1);
2051         }
2052     } else if (add_ca) {
2053         /*
2054          * Since we're ignoring carry-out, we can simplify the
2055          * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
2056          */
2057         tcg_gen_sub_tl(t0, arg2, arg1);
2058         tcg_gen_add_tl(t0, t0, cpu_ca);
2059         tcg_gen_subi_tl(t0, t0, 1);
2060     } else {
2061         tcg_gen_sub_tl(t0, arg2, arg1);
2062     }
2063 
2064     if (compute_ov) {
2065         gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
2066     }
2067     if (unlikely(compute_rc0)) {
2068         gen_set_Rc0(ctx, t0);
2069     }
2070 
2071     if (t0 != ret) {
2072         tcg_gen_mov_tl(ret, t0);
2073     }
2074 }
2075 /* Sub functions with Two operands functions */
2076 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
2077 static void glue(gen_, name)(DisasContext *ctx)                               \
2078 {                                                                             \
2079     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
2080                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
2081                       add_ca, compute_ca, compute_ov, Rc(ctx->opcode));       \
2082 }
2083 /* Sub functions with one operand and one immediate */
2084 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
2085                                 add_ca, compute_ca, compute_ov)               \
2086 static void glue(gen_, name)(DisasContext *ctx)                               \
2087 {                                                                             \
2088     TCGv t0 = tcg_constant_tl(const_val);                                     \
2089     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
2090                       cpu_gpr[rA(ctx->opcode)], t0,                           \
2091                       add_ca, compute_ca, compute_ov, Rc(ctx->opcode));       \
2092 }
2093 /* subf  subf.  subfo  subfo. */
2094 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
2095 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
2096 /* subfc  subfc.  subfco  subfco. */
2097 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
2098 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
2099 /* subfe  subfe.  subfeo  subfo. */
2100 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
2101 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
2102 /* subfme  subfme.  subfmeo  subfmeo.  */
2103 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
2104 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
2105 /* subfze  subfze.  subfzeo  subfzeo.*/
2106 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
2107 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
2108 
2109 /* subfic */
2110 static void gen_subfic(DisasContext *ctx)
2111 {
2112     TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
2113     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2114                       c, 0, 1, 0, 0);
2115 }
2116 
2117 /* neg neg. nego nego. */
2118 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
2119 {
2120     TCGv zero = tcg_constant_tl(0);
2121     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2122                       zero, 0, 0, compute_ov, Rc(ctx->opcode));
2123 }
2124 
2125 static void gen_neg(DisasContext *ctx)
2126 {
2127     tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2128     if (unlikely(Rc(ctx->opcode))) {
2129         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2130     }
2131 }
2132 
2133 static void gen_nego(DisasContext *ctx)
2134 {
2135     gen_op_arith_neg(ctx, 1);
2136 }
2137 
2138 /***                            Integer logical                            ***/
2139 #define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
2140 static void glue(gen_, name)(DisasContext *ctx)                               \
2141 {                                                                             \
2142     tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],                \
2143        cpu_gpr[rB(ctx->opcode)]);                                             \
2144     if (unlikely(Rc(ctx->opcode) != 0))                                       \
2145         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
2146 }
2147 
2148 #define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
2149 static void glue(gen_, name)(DisasContext *ctx)                               \
2150 {                                                                             \
2151     tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);               \
2152     if (unlikely(Rc(ctx->opcode) != 0))                                       \
2153         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
2154 }
2155 
2156 /* and & and. */
2157 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
2158 /* andc & andc. */
2159 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
2160 
2161 /* andi. */
2162 static void gen_andi_(DisasContext *ctx)
2163 {
2164     tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2165                     UIMM(ctx->opcode));
2166     gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2167 }
2168 
2169 /* andis. */
2170 static void gen_andis_(DisasContext *ctx)
2171 {
2172     tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2173                     UIMM(ctx->opcode) << 16);
2174     gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2175 }
2176 
2177 /* cntlzw */
2178 static void gen_cntlzw(DisasContext *ctx)
2179 {
2180     TCGv_i32 t = tcg_temp_new_i32();
2181 
2182     tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2183     tcg_gen_clzi_i32(t, t, 32);
2184     tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2185 
2186     if (unlikely(Rc(ctx->opcode) != 0)) {
2187         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2188     }
2189 }
2190 
2191 /* cnttzw */
2192 static void gen_cnttzw(DisasContext *ctx)
2193 {
2194     TCGv_i32 t = tcg_temp_new_i32();
2195 
2196     tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2197     tcg_gen_ctzi_i32(t, t, 32);
2198     tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2199 
2200     if (unlikely(Rc(ctx->opcode) != 0)) {
2201         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2202     }
2203 }
2204 
2205 /* eqv & eqv. */
2206 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
2207 /* extsb & extsb. */
2208 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
2209 /* extsh & extsh. */
2210 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
2211 /* nand & nand. */
2212 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
2213 /* nor & nor. */
2214 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
2215 
2216 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2217 static void gen_pause(DisasContext *ctx)
2218 {
2219     TCGv_i32 t0 = tcg_constant_i32(0);
2220     tcg_gen_st_i32(t0, cpu_env,
2221                    -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
2222 
2223     /* Stop translation, this gives other CPUs a chance to run */
2224     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
2225 }
2226 #endif /* defined(TARGET_PPC64) */
2227 
2228 /* or & or. */
2229 static void gen_or(DisasContext *ctx)
2230 {
2231     int rs, ra, rb;
2232 
2233     rs = rS(ctx->opcode);
2234     ra = rA(ctx->opcode);
2235     rb = rB(ctx->opcode);
2236     /* Optimisation for mr. ri case */
2237     if (rs != ra || rs != rb) {
2238         if (rs != rb) {
2239             tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
2240         } else {
2241             tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
2242         }
2243         if (unlikely(Rc(ctx->opcode) != 0)) {
2244             gen_set_Rc0(ctx, cpu_gpr[ra]);
2245         }
2246     } else if (unlikely(Rc(ctx->opcode) != 0)) {
2247         gen_set_Rc0(ctx, cpu_gpr[rs]);
2248 #if defined(TARGET_PPC64)
2249     } else if (rs != 0) { /* 0 is nop */
2250         int prio = 0;
2251 
2252         switch (rs) {
2253         case 1:
2254             /* Set process priority to low */
2255             prio = 2;
2256             break;
2257         case 6:
2258             /* Set process priority to medium-low */
2259             prio = 3;
2260             break;
2261         case 2:
2262             /* Set process priority to normal */
2263             prio = 4;
2264             break;
2265 #if !defined(CONFIG_USER_ONLY)
2266         case 31:
2267             if (!ctx->pr) {
2268                 /* Set process priority to very low */
2269                 prio = 1;
2270             }
2271             break;
2272         case 5:
2273             if (!ctx->pr) {
2274                 /* Set process priority to medium-hight */
2275                 prio = 5;
2276             }
2277             break;
2278         case 3:
2279             if (!ctx->pr) {
2280                 /* Set process priority to high */
2281                 prio = 6;
2282             }
2283             break;
2284         case 7:
2285             if (ctx->hv && !ctx->pr) {
2286                 /* Set process priority to very high */
2287                 prio = 7;
2288             }
2289             break;
2290 #endif
2291         default:
2292             break;
2293         }
2294         if (prio) {
2295             TCGv t0 = tcg_temp_new();
2296             gen_load_spr(t0, SPR_PPR);
2297             tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
2298             tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
2299             gen_store_spr(SPR_PPR, t0);
2300         }
2301 #if !defined(CONFIG_USER_ONLY)
2302         /*
2303          * Pause out of TCG otherwise spin loops with smt_low eat too
2304          * much CPU and the kernel hangs.  This applies to all
2305          * encodings other than no-op, e.g., miso(rs=26), yield(27),
2306          * mdoio(29), mdoom(30), and all currently undefined.
2307          */
2308         gen_pause(ctx);
2309 #endif
2310 #endif
2311     }
2312 }
2313 /* orc & orc. */
2314 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
2315 
2316 /* xor & xor. */
2317 static void gen_xor(DisasContext *ctx)
2318 {
2319     /* Optimisation for "set to zero" case */
2320     if (rS(ctx->opcode) != rB(ctx->opcode)) {
2321         tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2322                        cpu_gpr[rB(ctx->opcode)]);
2323     } else {
2324         tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2325     }
2326     if (unlikely(Rc(ctx->opcode) != 0)) {
2327         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2328     }
2329 }
2330 
2331 /* ori */
2332 static void gen_ori(DisasContext *ctx)
2333 {
2334     target_ulong uimm = UIMM(ctx->opcode);
2335 
2336     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2337         return;
2338     }
2339     tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2340 }
2341 
2342 /* oris */
2343 static void gen_oris(DisasContext *ctx)
2344 {
2345     target_ulong uimm = UIMM(ctx->opcode);
2346 
2347     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2348         /* NOP */
2349         return;
2350     }
2351     tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2352                    uimm << 16);
2353 }
2354 
2355 /* xori */
2356 static void gen_xori(DisasContext *ctx)
2357 {
2358     target_ulong uimm = UIMM(ctx->opcode);
2359 
2360     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2361         /* NOP */
2362         return;
2363     }
2364     tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2365 }
2366 
2367 /* xoris */
2368 static void gen_xoris(DisasContext *ctx)
2369 {
2370     target_ulong uimm = UIMM(ctx->opcode);
2371 
2372     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2373         /* NOP */
2374         return;
2375     }
2376     tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2377                     uimm << 16);
2378 }
2379 
2380 /* popcntb : PowerPC 2.03 specification */
2381 static void gen_popcntb(DisasContext *ctx)
2382 {
2383     gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2384 }
2385 
2386 static void gen_popcntw(DisasContext *ctx)
2387 {
2388 #if defined(TARGET_PPC64)
2389     gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2390 #else
2391     tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2392 #endif
2393 }
2394 
2395 #if defined(TARGET_PPC64)
2396 /* popcntd: PowerPC 2.06 specification */
2397 static void gen_popcntd(DisasContext *ctx)
2398 {
2399     tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2400 }
2401 #endif
2402 
2403 /* prtyw: PowerPC 2.05 specification */
2404 static void gen_prtyw(DisasContext *ctx)
2405 {
2406     TCGv ra = cpu_gpr[rA(ctx->opcode)];
2407     TCGv rs = cpu_gpr[rS(ctx->opcode)];
2408     TCGv t0 = tcg_temp_new();
2409     tcg_gen_shri_tl(t0, rs, 16);
2410     tcg_gen_xor_tl(ra, rs, t0);
2411     tcg_gen_shri_tl(t0, ra, 8);
2412     tcg_gen_xor_tl(ra, ra, t0);
2413     tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
2414 }
2415 
2416 #if defined(TARGET_PPC64)
2417 /* prtyd: PowerPC 2.05 specification */
2418 static void gen_prtyd(DisasContext *ctx)
2419 {
2420     TCGv ra = cpu_gpr[rA(ctx->opcode)];
2421     TCGv rs = cpu_gpr[rS(ctx->opcode)];
2422     TCGv t0 = tcg_temp_new();
2423     tcg_gen_shri_tl(t0, rs, 32);
2424     tcg_gen_xor_tl(ra, rs, t0);
2425     tcg_gen_shri_tl(t0, ra, 16);
2426     tcg_gen_xor_tl(ra, ra, t0);
2427     tcg_gen_shri_tl(t0, ra, 8);
2428     tcg_gen_xor_tl(ra, ra, t0);
2429     tcg_gen_andi_tl(ra, ra, 1);
2430 }
2431 #endif
2432 
2433 #if defined(TARGET_PPC64)
2434 /* bpermd */
2435 static void gen_bpermd(DisasContext *ctx)
2436 {
2437     gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
2438                       cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2439 }
2440 #endif
2441 
2442 #if defined(TARGET_PPC64)
2443 /* extsw & extsw. */
2444 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
2445 
2446 /* cntlzd */
2447 static void gen_cntlzd(DisasContext *ctx)
2448 {
2449     tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2450     if (unlikely(Rc(ctx->opcode) != 0)) {
2451         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2452     }
2453 }
2454 
2455 /* cnttzd */
2456 static void gen_cnttzd(DisasContext *ctx)
2457 {
2458     tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2459     if (unlikely(Rc(ctx->opcode) != 0)) {
2460         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2461     }
2462 }
2463 
2464 /* darn */
2465 static void gen_darn(DisasContext *ctx)
2466 {
2467     int l = L(ctx->opcode);
2468 
2469     if (l > 2) {
2470         tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
2471     } else {
2472         gen_icount_io_start(ctx);
2473         if (l == 0) {
2474             gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
2475         } else {
2476             /* Return 64-bit random for both CRN and RRN */
2477             gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
2478         }
2479     }
2480 }
2481 #endif
2482 
2483 /***                             Integer rotate                            ***/
2484 
2485 /* rlwimi & rlwimi. */
2486 static void gen_rlwimi(DisasContext *ctx)
2487 {
2488     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2489     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2490     uint32_t sh = SH(ctx->opcode);
2491     uint32_t mb = MB(ctx->opcode);
2492     uint32_t me = ME(ctx->opcode);
2493 
2494     if (sh == (31 - me) && mb <= me) {
2495         tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2496     } else {
2497         target_ulong mask;
2498         bool mask_in_32b = true;
2499         TCGv t1;
2500 
2501 #if defined(TARGET_PPC64)
2502         mb += 32;
2503         me += 32;
2504 #endif
2505         mask = MASK(mb, me);
2506 
2507 #if defined(TARGET_PPC64)
2508         if (mask > 0xffffffffu) {
2509             mask_in_32b = false;
2510         }
2511 #endif
2512         t1 = tcg_temp_new();
2513         if (mask_in_32b) {
2514             TCGv_i32 t0 = tcg_temp_new_i32();
2515             tcg_gen_trunc_tl_i32(t0, t_rs);
2516             tcg_gen_rotli_i32(t0, t0, sh);
2517             tcg_gen_extu_i32_tl(t1, t0);
2518         } else {
2519 #if defined(TARGET_PPC64)
2520             tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
2521             tcg_gen_rotli_i64(t1, t1, sh);
2522 #else
2523             g_assert_not_reached();
2524 #endif
2525         }
2526 
2527         tcg_gen_andi_tl(t1, t1, mask);
2528         tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2529         tcg_gen_or_tl(t_ra, t_ra, t1);
2530     }
2531     if (unlikely(Rc(ctx->opcode) != 0)) {
2532         gen_set_Rc0(ctx, t_ra);
2533     }
2534 }
2535 
2536 /* rlwinm & rlwinm. */
2537 static void gen_rlwinm(DisasContext *ctx)
2538 {
2539     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2540     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2541     int sh = SH(ctx->opcode);
2542     int mb = MB(ctx->opcode);
2543     int me = ME(ctx->opcode);
2544     int len = me - mb + 1;
2545     int rsh = (32 - sh) & 31;
2546 
2547     if (sh != 0 && len > 0 && me == (31 - sh)) {
2548         tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2549     } else if (me == 31 && rsh + len <= 32) {
2550         tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2551     } else {
2552         target_ulong mask;
2553         bool mask_in_32b = true;
2554 #if defined(TARGET_PPC64)
2555         mb += 32;
2556         me += 32;
2557 #endif
2558         mask = MASK(mb, me);
2559 #if defined(TARGET_PPC64)
2560         if (mask > 0xffffffffu) {
2561             mask_in_32b = false;
2562         }
2563 #endif
2564         if (mask_in_32b) {
2565             if (sh == 0) {
2566                 tcg_gen_andi_tl(t_ra, t_rs, mask);
2567             } else {
2568                 TCGv_i32 t0 = tcg_temp_new_i32();
2569                 tcg_gen_trunc_tl_i32(t0, t_rs);
2570                 tcg_gen_rotli_i32(t0, t0, sh);
2571                 tcg_gen_andi_i32(t0, t0, mask);
2572                 tcg_gen_extu_i32_tl(t_ra, t0);
2573             }
2574         } else {
2575 #if defined(TARGET_PPC64)
2576             tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2577             tcg_gen_rotli_i64(t_ra, t_ra, sh);
2578             tcg_gen_andi_i64(t_ra, t_ra, mask);
2579 #else
2580             g_assert_not_reached();
2581 #endif
2582         }
2583     }
2584     if (unlikely(Rc(ctx->opcode) != 0)) {
2585         gen_set_Rc0(ctx, t_ra);
2586     }
2587 }
2588 
2589 /* rlwnm & rlwnm. */
2590 static void gen_rlwnm(DisasContext *ctx)
2591 {
2592     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2593     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2594     TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2595     uint32_t mb = MB(ctx->opcode);
2596     uint32_t me = ME(ctx->opcode);
2597     target_ulong mask;
2598     bool mask_in_32b = true;
2599 
2600 #if defined(TARGET_PPC64)
2601     mb += 32;
2602     me += 32;
2603 #endif
2604     mask = MASK(mb, me);
2605 
2606 #if defined(TARGET_PPC64)
2607     if (mask > 0xffffffffu) {
2608         mask_in_32b = false;
2609     }
2610 #endif
2611     if (mask_in_32b) {
2612         TCGv_i32 t0 = tcg_temp_new_i32();
2613         TCGv_i32 t1 = tcg_temp_new_i32();
2614         tcg_gen_trunc_tl_i32(t0, t_rb);
2615         tcg_gen_trunc_tl_i32(t1, t_rs);
2616         tcg_gen_andi_i32(t0, t0, 0x1f);
2617         tcg_gen_rotl_i32(t1, t1, t0);
2618         tcg_gen_extu_i32_tl(t_ra, t1);
2619     } else {
2620 #if defined(TARGET_PPC64)
2621         TCGv_i64 t0 = tcg_temp_new_i64();
2622         tcg_gen_andi_i64(t0, t_rb, 0x1f);
2623         tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2624         tcg_gen_rotl_i64(t_ra, t_ra, t0);
2625 #else
2626         g_assert_not_reached();
2627 #endif
2628     }
2629 
2630     tcg_gen_andi_tl(t_ra, t_ra, mask);
2631 
2632     if (unlikely(Rc(ctx->opcode) != 0)) {
2633         gen_set_Rc0(ctx, t_ra);
2634     }
2635 }
2636 
2637 #if defined(TARGET_PPC64)
2638 #define GEN_PPC64_R2(name, opc1, opc2)                                        \
2639 static void glue(gen_, name##0)(DisasContext *ctx)                            \
2640 {                                                                             \
2641     gen_##name(ctx, 0);                                                       \
2642 }                                                                             \
2643                                                                               \
2644 static void glue(gen_, name##1)(DisasContext *ctx)                            \
2645 {                                                                             \
2646     gen_##name(ctx, 1);                                                       \
2647 }
2648 #define GEN_PPC64_R4(name, opc1, opc2)                                        \
2649 static void glue(gen_, name##0)(DisasContext *ctx)                            \
2650 {                                                                             \
2651     gen_##name(ctx, 0, 0);                                                    \
2652 }                                                                             \
2653                                                                               \
2654 static void glue(gen_, name##1)(DisasContext *ctx)                            \
2655 {                                                                             \
2656     gen_##name(ctx, 0, 1);                                                    \
2657 }                                                                             \
2658                                                                               \
2659 static void glue(gen_, name##2)(DisasContext *ctx)                            \
2660 {                                                                             \
2661     gen_##name(ctx, 1, 0);                                                    \
2662 }                                                                             \
2663                                                                               \
2664 static void glue(gen_, name##3)(DisasContext *ctx)                            \
2665 {                                                                             \
2666     gen_##name(ctx, 1, 1);                                                    \
2667 }
2668 
2669 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2670 {
2671     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2672     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2673     int len = me - mb + 1;
2674     int rsh = (64 - sh) & 63;
2675 
2676     if (sh != 0 && len > 0 && me == (63 - sh)) {
2677         tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2678     } else if (me == 63 && rsh + len <= 64) {
2679         tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2680     } else {
2681         tcg_gen_rotli_tl(t_ra, t_rs, sh);
2682         tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2683     }
2684     if (unlikely(Rc(ctx->opcode) != 0)) {
2685         gen_set_Rc0(ctx, t_ra);
2686     }
2687 }
2688 
2689 /* rldicl - rldicl. */
2690 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2691 {
2692     uint32_t sh, mb;
2693 
2694     sh = SH(ctx->opcode) | (shn << 5);
2695     mb = MB(ctx->opcode) | (mbn << 5);
2696     gen_rldinm(ctx, mb, 63, sh);
2697 }
2698 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2699 
2700 /* rldicr - rldicr. */
2701 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2702 {
2703     uint32_t sh, me;
2704 
2705     sh = SH(ctx->opcode) | (shn << 5);
2706     me = MB(ctx->opcode) | (men << 5);
2707     gen_rldinm(ctx, 0, me, sh);
2708 }
2709 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2710 
2711 /* rldic - rldic. */
2712 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2713 {
2714     uint32_t sh, mb;
2715 
2716     sh = SH(ctx->opcode) | (shn << 5);
2717     mb = MB(ctx->opcode) | (mbn << 5);
2718     gen_rldinm(ctx, mb, 63 - sh, sh);
2719 }
2720 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2721 
2722 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2723 {
2724     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2725     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2726     TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2727     TCGv t0;
2728 
2729     t0 = tcg_temp_new();
2730     tcg_gen_andi_tl(t0, t_rb, 0x3f);
2731     tcg_gen_rotl_tl(t_ra, t_rs, t0);
2732 
2733     tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2734     if (unlikely(Rc(ctx->opcode) != 0)) {
2735         gen_set_Rc0(ctx, t_ra);
2736     }
2737 }
2738 
2739 /* rldcl - rldcl. */
2740 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2741 {
2742     uint32_t mb;
2743 
2744     mb = MB(ctx->opcode) | (mbn << 5);
2745     gen_rldnm(ctx, mb, 63);
2746 }
2747 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2748 
2749 /* rldcr - rldcr. */
2750 static inline void gen_rldcr(DisasContext *ctx, int men)
2751 {
2752     uint32_t me;
2753 
2754     me = MB(ctx->opcode) | (men << 5);
2755     gen_rldnm(ctx, 0, me);
2756 }
2757 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2758 
2759 /* rldimi - rldimi. */
2760 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2761 {
2762     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2763     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2764     uint32_t sh = SH(ctx->opcode) | (shn << 5);
2765     uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2766     uint32_t me = 63 - sh;
2767 
2768     if (mb <= me) {
2769         tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2770     } else {
2771         target_ulong mask = MASK(mb, me);
2772         TCGv t1 = tcg_temp_new();
2773 
2774         tcg_gen_rotli_tl(t1, t_rs, sh);
2775         tcg_gen_andi_tl(t1, t1, mask);
2776         tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2777         tcg_gen_or_tl(t_ra, t_ra, t1);
2778     }
2779     if (unlikely(Rc(ctx->opcode) != 0)) {
2780         gen_set_Rc0(ctx, t_ra);
2781     }
2782 }
2783 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2784 #endif
2785 
2786 /***                             Integer shift                             ***/
2787 
2788 /* slw & slw. */
2789 static void gen_slw(DisasContext *ctx)
2790 {
2791     TCGv t0, t1;
2792 
2793     t0 = tcg_temp_new();
2794     /* AND rS with a mask that is 0 when rB >= 0x20 */
2795 #if defined(TARGET_PPC64)
2796     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2797     tcg_gen_sari_tl(t0, t0, 0x3f);
2798 #else
2799     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2800     tcg_gen_sari_tl(t0, t0, 0x1f);
2801 #endif
2802     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2803     t1 = tcg_temp_new();
2804     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2805     tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2806     tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2807     if (unlikely(Rc(ctx->opcode) != 0)) {
2808         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2809     }
2810 }
2811 
2812 /* sraw & sraw. */
2813 static void gen_sraw(DisasContext *ctx)
2814 {
2815     gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2816                     cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2817     if (unlikely(Rc(ctx->opcode) != 0)) {
2818         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2819     }
2820 }
2821 
2822 /* srawi & srawi. */
2823 static void gen_srawi(DisasContext *ctx)
2824 {
2825     int sh = SH(ctx->opcode);
2826     TCGv dst = cpu_gpr[rA(ctx->opcode)];
2827     TCGv src = cpu_gpr[rS(ctx->opcode)];
2828     if (sh == 0) {
2829         tcg_gen_ext32s_tl(dst, src);
2830         tcg_gen_movi_tl(cpu_ca, 0);
2831         if (is_isa300(ctx)) {
2832             tcg_gen_movi_tl(cpu_ca32, 0);
2833         }
2834     } else {
2835         TCGv t0;
2836         tcg_gen_ext32s_tl(dst, src);
2837         tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2838         t0 = tcg_temp_new();
2839         tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2840         tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2841         tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2842         if (is_isa300(ctx)) {
2843             tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2844         }
2845         tcg_gen_sari_tl(dst, dst, sh);
2846     }
2847     if (unlikely(Rc(ctx->opcode) != 0)) {
2848         gen_set_Rc0(ctx, dst);
2849     }
2850 }
2851 
2852 /* srw & srw. */
2853 static void gen_srw(DisasContext *ctx)
2854 {
2855     TCGv t0, t1;
2856 
2857     t0 = tcg_temp_new();
2858     /* AND rS with a mask that is 0 when rB >= 0x20 */
2859 #if defined(TARGET_PPC64)
2860     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2861     tcg_gen_sari_tl(t0, t0, 0x3f);
2862 #else
2863     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2864     tcg_gen_sari_tl(t0, t0, 0x1f);
2865 #endif
2866     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2867     tcg_gen_ext32u_tl(t0, t0);
2868     t1 = tcg_temp_new();
2869     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2870     tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2871     if (unlikely(Rc(ctx->opcode) != 0)) {
2872         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2873     }
2874 }
2875 
2876 #if defined(TARGET_PPC64)
2877 /* sld & sld. */
2878 static void gen_sld(DisasContext *ctx)
2879 {
2880     TCGv t0, t1;
2881 
2882     t0 = tcg_temp_new();
2883     /* AND rS with a mask that is 0 when rB >= 0x40 */
2884     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2885     tcg_gen_sari_tl(t0, t0, 0x3f);
2886     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2887     t1 = tcg_temp_new();
2888     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2889     tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2890     if (unlikely(Rc(ctx->opcode) != 0)) {
2891         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2892     }
2893 }
2894 
2895 /* srad & srad. */
2896 static void gen_srad(DisasContext *ctx)
2897 {
2898     gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2899                     cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2900     if (unlikely(Rc(ctx->opcode) != 0)) {
2901         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2902     }
2903 }
2904 /* sradi & sradi. */
2905 static inline void gen_sradi(DisasContext *ctx, int n)
2906 {
2907     int sh = SH(ctx->opcode) + (n << 5);
2908     TCGv dst = cpu_gpr[rA(ctx->opcode)];
2909     TCGv src = cpu_gpr[rS(ctx->opcode)];
2910     if (sh == 0) {
2911         tcg_gen_mov_tl(dst, src);
2912         tcg_gen_movi_tl(cpu_ca, 0);
2913         if (is_isa300(ctx)) {
2914             tcg_gen_movi_tl(cpu_ca32, 0);
2915         }
2916     } else {
2917         TCGv t0;
2918         tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2919         t0 = tcg_temp_new();
2920         tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2921         tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2922         tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2923         if (is_isa300(ctx)) {
2924             tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2925         }
2926         tcg_gen_sari_tl(dst, src, sh);
2927     }
2928     if (unlikely(Rc(ctx->opcode) != 0)) {
2929         gen_set_Rc0(ctx, dst);
2930     }
2931 }
2932 
2933 static void gen_sradi0(DisasContext *ctx)
2934 {
2935     gen_sradi(ctx, 0);
2936 }
2937 
2938 static void gen_sradi1(DisasContext *ctx)
2939 {
2940     gen_sradi(ctx, 1);
2941 }
2942 
2943 /* extswsli & extswsli. */
2944 static inline void gen_extswsli(DisasContext *ctx, int n)
2945 {
2946     int sh = SH(ctx->opcode) + (n << 5);
2947     TCGv dst = cpu_gpr[rA(ctx->opcode)];
2948     TCGv src = cpu_gpr[rS(ctx->opcode)];
2949 
2950     tcg_gen_ext32s_tl(dst, src);
2951     tcg_gen_shli_tl(dst, dst, sh);
2952     if (unlikely(Rc(ctx->opcode) != 0)) {
2953         gen_set_Rc0(ctx, dst);
2954     }
2955 }
2956 
2957 static void gen_extswsli0(DisasContext *ctx)
2958 {
2959     gen_extswsli(ctx, 0);
2960 }
2961 
2962 static void gen_extswsli1(DisasContext *ctx)
2963 {
2964     gen_extswsli(ctx, 1);
2965 }
2966 
2967 /* srd & srd. */
2968 static void gen_srd(DisasContext *ctx)
2969 {
2970     TCGv t0, t1;
2971 
2972     t0 = tcg_temp_new();
2973     /* AND rS with a mask that is 0 when rB >= 0x40 */
2974     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2975     tcg_gen_sari_tl(t0, t0, 0x3f);
2976     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2977     t1 = tcg_temp_new();
2978     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2979     tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2980     if (unlikely(Rc(ctx->opcode) != 0)) {
2981         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2982     }
2983 }
2984 #endif
2985 
2986 /***                           Addressing modes                            ***/
2987 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2988 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2989                                       target_long maskl)
2990 {
2991     target_long simm = SIMM(ctx->opcode);
2992 
2993     simm &= ~maskl;
2994     if (rA(ctx->opcode) == 0) {
2995         if (NARROW_MODE(ctx)) {
2996             simm = (uint32_t)simm;
2997         }
2998         tcg_gen_movi_tl(EA, simm);
2999     } else if (likely(simm != 0)) {
3000         tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
3001         if (NARROW_MODE(ctx)) {
3002             tcg_gen_ext32u_tl(EA, EA);
3003         }
3004     } else {
3005         if (NARROW_MODE(ctx)) {
3006             tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3007         } else {
3008             tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3009         }
3010     }
3011 }
3012 
3013 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
3014 {
3015     if (rA(ctx->opcode) == 0) {
3016         if (NARROW_MODE(ctx)) {
3017             tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3018         } else {
3019             tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3020         }
3021     } else {
3022         tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3023         if (NARROW_MODE(ctx)) {
3024             tcg_gen_ext32u_tl(EA, EA);
3025         }
3026     }
3027 }
3028 
3029 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
3030 {
3031     if (rA(ctx->opcode) == 0) {
3032         tcg_gen_movi_tl(EA, 0);
3033     } else if (NARROW_MODE(ctx)) {
3034         tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3035     } else {
3036         tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3037     }
3038 }
3039 
3040 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
3041                                 target_long val)
3042 {
3043     tcg_gen_addi_tl(ret, arg1, val);
3044     if (NARROW_MODE(ctx)) {
3045         tcg_gen_ext32u_tl(ret, ret);
3046     }
3047 }
3048 
3049 static inline void gen_align_no_le(DisasContext *ctx)
3050 {
3051     gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
3052                       (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
3053 }
3054 
3055 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ)
3056 {
3057     TCGv ea = tcg_temp_new();
3058     if (ra) {
3059         tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
3060     } else {
3061         tcg_gen_mov_tl(ea, displ);
3062     }
3063     if (NARROW_MODE(ctx)) {
3064         tcg_gen_ext32u_tl(ea, ea);
3065     }
3066     return ea;
3067 }
3068 
3069 /***                             Integer load                              ***/
3070 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
3071 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
3072 
3073 #define GEN_QEMU_LOAD_TL(ldop, op)                                      \
3074 static void glue(gen_qemu_, ldop)(DisasContext *ctx,                    \
3075                                   TCGv val,                             \
3076                                   TCGv addr)                            \
3077 {                                                                       \
3078     tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op);                    \
3079 }
3080 
3081 GEN_QEMU_LOAD_TL(ld8u,  DEF_MEMOP(MO_UB))
3082 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
3083 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
3084 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
3085 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
3086 
3087 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
3088 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
3089 
3090 #define GEN_QEMU_LOAD_64(ldop, op)                                  \
3091 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx,    \
3092                                              TCGv_i64 val,          \
3093                                              TCGv addr)             \
3094 {                                                                   \
3095     tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op);               \
3096 }
3097 
3098 GEN_QEMU_LOAD_64(ld8u,  DEF_MEMOP(MO_UB))
3099 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
3100 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
3101 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
3102 GEN_QEMU_LOAD_64(ld64,  DEF_MEMOP(MO_UQ))
3103 
3104 #if defined(TARGET_PPC64)
3105 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ))
3106 #endif
3107 
3108 #define GEN_QEMU_STORE_TL(stop, op)                                     \
3109 static void glue(gen_qemu_, stop)(DisasContext *ctx,                    \
3110                                   TCGv val,                             \
3111                                   TCGv addr)                            \
3112 {                                                                       \
3113     tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op);                    \
3114 }
3115 
3116 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
3117 GEN_QEMU_STORE_TL(st8,  DEF_MEMOP(MO_UB))
3118 #endif
3119 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
3120 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
3121 
3122 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
3123 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
3124 
3125 #define GEN_QEMU_STORE_64(stop, op)                               \
3126 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx,  \
3127                                               TCGv_i64 val,       \
3128                                               TCGv addr)          \
3129 {                                                                 \
3130     tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op);             \
3131 }
3132 
3133 GEN_QEMU_STORE_64(st8,  DEF_MEMOP(MO_UB))
3134 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
3135 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
3136 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ))
3137 
3138 #if defined(TARGET_PPC64)
3139 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))
3140 #endif
3141 
3142 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk)                   \
3143 static void glue(gen_, name##x)(DisasContext *ctx)                            \
3144 {                                                                             \
3145     TCGv EA;                                                                  \
3146     chk(ctx);                                                                 \
3147     gen_set_access_type(ctx, ACCESS_INT);                                     \
3148     EA = tcg_temp_new();                                                      \
3149     gen_addr_reg_index(ctx, EA);                                              \
3150     gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
3151 }
3152 
3153 #define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
3154     GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3155 
3156 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type)                            \
3157     GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3158 
3159 #define GEN_LDEPX(name, ldop, opc2, opc3)                                     \
3160 static void glue(gen_, name##epx)(DisasContext *ctx)                          \
3161 {                                                                             \
3162     TCGv EA;                                                                  \
3163     CHK_SV(ctx);                                                              \
3164     gen_set_access_type(ctx, ACCESS_INT);                                     \
3165     EA = tcg_temp_new();                                                      \
3166     gen_addr_reg_index(ctx, EA);                                              \
3167     tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
3168 }
3169 
3170 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
3171 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
3172 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
3173 #if defined(TARGET_PPC64)
3174 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)
3175 #endif
3176 
3177 #if defined(TARGET_PPC64)
3178 /* CI load/store variants */
3179 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
3180 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
3181 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
3182 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
3183 #endif
3184 
3185 /***                              Integer store                            ***/
3186 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk)                   \
3187 static void glue(gen_, name##x)(DisasContext *ctx)                            \
3188 {                                                                             \
3189     TCGv EA;                                                                  \
3190     chk(ctx);                                                                 \
3191     gen_set_access_type(ctx, ACCESS_INT);                                     \
3192     EA = tcg_temp_new();                                                      \
3193     gen_addr_reg_index(ctx, EA);                                              \
3194     gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
3195 }
3196 #define GEN_STX(name, stop, opc2, opc3, type)                                 \
3197     GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3198 
3199 #define GEN_STX_HVRM(name, stop, opc2, opc3, type)                            \
3200     GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3201 
3202 #define GEN_STEPX(name, stop, opc2, opc3)                                     \
3203 static void glue(gen_, name##epx)(DisasContext *ctx)                          \
3204 {                                                                             \
3205     TCGv EA;                                                                  \
3206     CHK_SV(ctx);                                                              \
3207     gen_set_access_type(ctx, ACCESS_INT);                                     \
3208     EA = tcg_temp_new();                                                      \
3209     gen_addr_reg_index(ctx, EA);                                              \
3210     tcg_gen_qemu_st_tl(                                                       \
3211         cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop);              \
3212 }
3213 
3214 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
3215 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
3216 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
3217 #if defined(TARGET_PPC64)
3218 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04)
3219 #endif
3220 
3221 #if defined(TARGET_PPC64)
3222 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
3223 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
3224 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
3225 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
3226 #endif
3227 /***                Integer load and store with byte reverse               ***/
3228 
3229 /* lhbrx */
3230 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3231 
3232 /* lwbrx */
3233 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3234 
3235 #if defined(TARGET_PPC64)
3236 /* ldbrx */
3237 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
3238 /* stdbrx */
3239 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
3240 #endif  /* TARGET_PPC64 */
3241 
3242 /* sthbrx */
3243 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3244 /* stwbrx */
3245 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3246 
3247 /***                    Integer load and store multiple                    ***/
3248 
3249 /* lmw */
3250 static void gen_lmw(DisasContext *ctx)
3251 {
3252     TCGv t0;
3253     TCGv_i32 t1;
3254 
3255     if (ctx->le_mode) {
3256         gen_align_no_le(ctx);
3257         return;
3258     }
3259     gen_set_access_type(ctx, ACCESS_INT);
3260     t0 = tcg_temp_new();
3261     t1 = tcg_constant_i32(rD(ctx->opcode));
3262     gen_addr_imm_index(ctx, t0, 0);
3263     gen_helper_lmw(cpu_env, t0, t1);
3264 }
3265 
3266 /* stmw */
3267 static void gen_stmw(DisasContext *ctx)
3268 {
3269     TCGv t0;
3270     TCGv_i32 t1;
3271 
3272     if (ctx->le_mode) {
3273         gen_align_no_le(ctx);
3274         return;
3275     }
3276     gen_set_access_type(ctx, ACCESS_INT);
3277     t0 = tcg_temp_new();
3278     t1 = tcg_constant_i32(rS(ctx->opcode));
3279     gen_addr_imm_index(ctx, t0, 0);
3280     gen_helper_stmw(cpu_env, t0, t1);
3281 }
3282 
3283 /***                    Integer load and store strings                     ***/
3284 
3285 /* lswi */
3286 /*
3287  * PowerPC32 specification says we must generate an exception if rA is
3288  * in the range of registers to be loaded.  In an other hand, IBM says
3289  * this is valid, but rA won't be loaded.  For now, I'll follow the
3290  * spec...
3291  */
3292 static void gen_lswi(DisasContext *ctx)
3293 {
3294     TCGv t0;
3295     TCGv_i32 t1, t2;
3296     int nb = NB(ctx->opcode);
3297     int start = rD(ctx->opcode);
3298     int ra = rA(ctx->opcode);
3299     int nr;
3300 
3301     if (ctx->le_mode) {
3302         gen_align_no_le(ctx);
3303         return;
3304     }
3305     if (nb == 0) {
3306         nb = 32;
3307     }
3308     nr = DIV_ROUND_UP(nb, 4);
3309     if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3310         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3311         return;
3312     }
3313     gen_set_access_type(ctx, ACCESS_INT);
3314     t0 = tcg_temp_new();
3315     gen_addr_register(ctx, t0);
3316     t1 = tcg_constant_i32(nb);
3317     t2 = tcg_constant_i32(start);
3318     gen_helper_lsw(cpu_env, t0, t1, t2);
3319 }
3320 
3321 /* lswx */
3322 static void gen_lswx(DisasContext *ctx)
3323 {
3324     TCGv t0;
3325     TCGv_i32 t1, t2, t3;
3326 
3327     if (ctx->le_mode) {
3328         gen_align_no_le(ctx);
3329         return;
3330     }
3331     gen_set_access_type(ctx, ACCESS_INT);
3332     t0 = tcg_temp_new();
3333     gen_addr_reg_index(ctx, t0);
3334     t1 = tcg_constant_i32(rD(ctx->opcode));
3335     t2 = tcg_constant_i32(rA(ctx->opcode));
3336     t3 = tcg_constant_i32(rB(ctx->opcode));
3337     gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3338 }
3339 
3340 /* stswi */
3341 static void gen_stswi(DisasContext *ctx)
3342 {
3343     TCGv t0;
3344     TCGv_i32 t1, t2;
3345     int nb = NB(ctx->opcode);
3346 
3347     if (ctx->le_mode) {
3348         gen_align_no_le(ctx);
3349         return;
3350     }
3351     gen_set_access_type(ctx, ACCESS_INT);
3352     t0 = tcg_temp_new();
3353     gen_addr_register(ctx, t0);
3354     if (nb == 0) {
3355         nb = 32;
3356     }
3357     t1 = tcg_constant_i32(nb);
3358     t2 = tcg_constant_i32(rS(ctx->opcode));
3359     gen_helper_stsw(cpu_env, t0, t1, t2);
3360 }
3361 
3362 /* stswx */
3363 static void gen_stswx(DisasContext *ctx)
3364 {
3365     TCGv t0;
3366     TCGv_i32 t1, t2;
3367 
3368     if (ctx->le_mode) {
3369         gen_align_no_le(ctx);
3370         return;
3371     }
3372     gen_set_access_type(ctx, ACCESS_INT);
3373     t0 = tcg_temp_new();
3374     gen_addr_reg_index(ctx, t0);
3375     t1 = tcg_temp_new_i32();
3376     tcg_gen_trunc_tl_i32(t1, cpu_xer);
3377     tcg_gen_andi_i32(t1, t1, 0x7F);
3378     t2 = tcg_constant_i32(rS(ctx->opcode));
3379     gen_helper_stsw(cpu_env, t0, t1, t2);
3380 }
3381 
3382 /***                        Memory synchronisation                         ***/
3383 /* eieio */
3384 static void gen_eieio(DisasContext *ctx)
3385 {
3386     TCGBar bar = TCG_MO_ALL;
3387 
3388     /*
3389      * eieio has complex semanitcs. It provides memory ordering between
3390      * operations in the set:
3391      * - loads from CI memory.
3392      * - stores to CI memory.
3393      * - stores to WT memory.
3394      *
3395      * It separately also orders memory for operations in the set:
3396      * - stores to cacheble memory.
3397      *
3398      * It also serializes instructions:
3399      * - dcbt and dcbst.
3400      *
3401      * It separately serializes:
3402      * - tlbie and tlbsync.
3403      *
3404      * And separately serializes:
3405      * - slbieg, slbiag, and slbsync.
3406      *
3407      * The end result is that CI memory ordering requires TCG_MO_ALL
3408      * and it is not possible to special-case more relaxed ordering for
3409      * cacheable accesses. TCG_BAR_SC is required to provide this
3410      * serialization.
3411      */
3412 
3413     /*
3414      * POWER9 has a eieio instruction variant using bit 6 as a hint to
3415      * tell the CPU it is a store-forwarding barrier.
3416      */
3417     if (ctx->opcode & 0x2000000) {
3418         /*
3419          * ISA says that "Reserved fields in instructions are ignored
3420          * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3421          * as this is not an instruction software should be using,
3422          * complain to the user.
3423          */
3424         if (!(ctx->insns_flags2 & PPC2_ISA300)) {
3425             qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
3426                           TARGET_FMT_lx "\n", ctx->cia);
3427         } else {
3428             bar = TCG_MO_ST_LD;
3429         }
3430     }
3431 
3432     tcg_gen_mb(bar | TCG_BAR_SC);
3433 }
3434 
3435 #if !defined(CONFIG_USER_ONLY)
3436 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
3437 {
3438     TCGv_i32 t;
3439     TCGLabel *l;
3440 
3441     if (!ctx->lazy_tlb_flush) {
3442         return;
3443     }
3444     l = gen_new_label();
3445     t = tcg_temp_new_i32();
3446     tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3447     tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3448     if (global) {
3449         gen_helper_check_tlb_flush_global(cpu_env);
3450     } else {
3451         gen_helper_check_tlb_flush_local(cpu_env);
3452     }
3453     gen_set_label(l);
3454 }
3455 #else
3456 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3457 #endif
3458 
3459 /* isync */
3460 static void gen_isync(DisasContext *ctx)
3461 {
3462     /*
3463      * We need to check for a pending TLB flush. This can only happen in
3464      * kernel mode however so check MSR_PR
3465      */
3466     if (!ctx->pr) {
3467         gen_check_tlb_flush(ctx, false);
3468     }
3469     tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3470     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
3471 }
3472 
3473 #define MEMOP_GET_SIZE(x)  (1 << ((x) & MO_SIZE))
3474 
3475 static void gen_load_locked(DisasContext *ctx, MemOp memop)
3476 {
3477     TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3478     TCGv t0 = tcg_temp_new();
3479 
3480     gen_set_access_type(ctx, ACCESS_RES);
3481     gen_addr_reg_index(ctx, t0);
3482     tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3483     tcg_gen_mov_tl(cpu_reserve, t0);
3484     tcg_gen_mov_tl(cpu_reserve_val, gpr);
3485     tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
3486 }
3487 
3488 #define LARX(name, memop)                  \
3489 static void gen_##name(DisasContext *ctx)  \
3490 {                                          \
3491     gen_load_locked(ctx, memop);           \
3492 }
3493 
3494 /* lwarx */
3495 LARX(lbarx, DEF_MEMOP(MO_UB))
3496 LARX(lharx, DEF_MEMOP(MO_UW))
3497 LARX(lwarx, DEF_MEMOP(MO_UL))
3498 
3499 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
3500                                       TCGv EA, TCGCond cond, int addend)
3501 {
3502     TCGv t = tcg_temp_new();
3503     TCGv t2 = tcg_temp_new();
3504     TCGv u = tcg_temp_new();
3505 
3506     tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3507     tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
3508     tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
3509     tcg_gen_addi_tl(u, t, addend);
3510 
3511     /* E.g. for fetch and increment bounded... */
3512     /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3513     tcg_gen_movcond_tl(cond, u, t, t2, u, t);
3514     tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
3515 
3516     /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3517     tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
3518     tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
3519 }
3520 
3521 static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
3522 {
3523     uint32_t gpr_FC = FC(ctx->opcode);
3524     TCGv EA = tcg_temp_new();
3525     int rt = rD(ctx->opcode);
3526     bool need_serial;
3527     TCGv src, dst;
3528 
3529     gen_addr_register(ctx, EA);
3530     dst = cpu_gpr[rt];
3531     src = cpu_gpr[(rt + 1) & 31];
3532 
3533     need_serial = false;
3534     memop |= MO_ALIGN;
3535     switch (gpr_FC) {
3536     case 0: /* Fetch and add */
3537         tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
3538         break;
3539     case 1: /* Fetch and xor */
3540         tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
3541         break;
3542     case 2: /* Fetch and or */
3543         tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
3544         break;
3545     case 3: /* Fetch and 'and' */
3546         tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
3547         break;
3548     case 4:  /* Fetch and max unsigned */
3549         tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
3550         break;
3551     case 5:  /* Fetch and max signed */
3552         tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
3553         break;
3554     case 6:  /* Fetch and min unsigned */
3555         tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
3556         break;
3557     case 7:  /* Fetch and min signed */
3558         tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
3559         break;
3560     case 8: /* Swap */
3561         tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
3562         break;
3563 
3564     case 16: /* Compare and swap not equal */
3565         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3566             need_serial = true;
3567         } else {
3568             TCGv t0 = tcg_temp_new();
3569             TCGv t1 = tcg_temp_new();
3570 
3571             tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
3572             if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
3573                 tcg_gen_mov_tl(t1, src);
3574             } else {
3575                 tcg_gen_ext32u_tl(t1, src);
3576             }
3577             tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
3578                                cpu_gpr[(rt + 2) & 31], t0);
3579             tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
3580             tcg_gen_mov_tl(dst, t0);
3581         }
3582         break;
3583 
3584     case 24: /* Fetch and increment bounded */
3585         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3586             need_serial = true;
3587         } else {
3588             gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
3589         }
3590         break;
3591     case 25: /* Fetch and increment equal */
3592         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3593             need_serial = true;
3594         } else {
3595             gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
3596         }
3597         break;
3598     case 28: /* Fetch and decrement bounded */
3599         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3600             need_serial = true;
3601         } else {
3602             gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
3603         }
3604         break;
3605 
3606     default:
3607         /* invoke data storage error handler */
3608         gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3609     }
3610 
3611     if (need_serial) {
3612         /* Restart with exclusive lock.  */
3613         gen_helper_exit_atomic(cpu_env);
3614         ctx->base.is_jmp = DISAS_NORETURN;
3615     }
3616 }
3617 
3618 static void gen_lwat(DisasContext *ctx)
3619 {
3620     gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
3621 }
3622 
3623 #ifdef TARGET_PPC64
3624 static void gen_ldat(DisasContext *ctx)
3625 {
3626     gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ));
3627 }
3628 #endif
3629 
3630 static void gen_st_atomic(DisasContext *ctx, MemOp memop)
3631 {
3632     uint32_t gpr_FC = FC(ctx->opcode);
3633     TCGv EA = tcg_temp_new();
3634     TCGv src, discard;
3635 
3636     gen_addr_register(ctx, EA);
3637     src = cpu_gpr[rD(ctx->opcode)];
3638     discard = tcg_temp_new();
3639 
3640     memop |= MO_ALIGN;
3641     switch (gpr_FC) {
3642     case 0: /* add and Store */
3643         tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3644         break;
3645     case 1: /* xor and Store */
3646         tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3647         break;
3648     case 2: /* Or and Store */
3649         tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3650         break;
3651     case 3: /* 'and' and Store */
3652         tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3653         break;
3654     case 4:  /* Store max unsigned */
3655         tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3656         break;
3657     case 5:  /* Store max signed */
3658         tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3659         break;
3660     case 6:  /* Store min unsigned */
3661         tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3662         break;
3663     case 7:  /* Store min signed */
3664         tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3665         break;
3666     case 24: /* Store twin  */
3667         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3668             /* Restart with exclusive lock.  */
3669             gen_helper_exit_atomic(cpu_env);
3670             ctx->base.is_jmp = DISAS_NORETURN;
3671         } else {
3672             TCGv t = tcg_temp_new();
3673             TCGv t2 = tcg_temp_new();
3674             TCGv s = tcg_temp_new();
3675             TCGv s2 = tcg_temp_new();
3676             TCGv ea_plus_s = tcg_temp_new();
3677 
3678             tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3679             tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
3680             tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
3681             tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
3682             tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
3683             tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
3684             tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
3685         }
3686         break;
3687     default:
3688         /* invoke data storage error handler */
3689         gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3690     }
3691 }
3692 
3693 static void gen_stwat(DisasContext *ctx)
3694 {
3695     gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
3696 }
3697 
3698 #ifdef TARGET_PPC64
3699 static void gen_stdat(DisasContext *ctx)
3700 {
3701     gen_st_atomic(ctx, DEF_MEMOP(MO_UQ));
3702 }
3703 #endif
3704 
3705 static void gen_conditional_store(DisasContext *ctx, MemOp memop)
3706 {
3707     TCGLabel *l1 = gen_new_label();
3708     TCGLabel *l2 = gen_new_label();
3709     TCGv t0 = tcg_temp_new();
3710     int reg = rS(ctx->opcode);
3711 
3712     gen_set_access_type(ctx, ACCESS_RES);
3713     gen_addr_reg_index(ctx, t0);
3714     tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3715 
3716     t0 = tcg_temp_new();
3717     tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3718                               cpu_gpr[reg], ctx->mem_idx,
3719                               DEF_MEMOP(memop) | MO_ALIGN);
3720     tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3721     tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3722     tcg_gen_or_tl(t0, t0, cpu_so);
3723     tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3724     tcg_gen_br(l2);
3725 
3726     gen_set_label(l1);
3727 
3728     /*
3729      * Address mismatch implies failure.  But we still need to provide
3730      * the memory barrier semantics of the instruction.
3731      */
3732     tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3733     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3734 
3735     gen_set_label(l2);
3736     tcg_gen_movi_tl(cpu_reserve, -1);
3737 }
3738 
3739 #define STCX(name, memop)                  \
3740 static void gen_##name(DisasContext *ctx)  \
3741 {                                          \
3742     gen_conditional_store(ctx, memop);     \
3743 }
3744 
3745 STCX(stbcx_, DEF_MEMOP(MO_UB))
3746 STCX(sthcx_, DEF_MEMOP(MO_UW))
3747 STCX(stwcx_, DEF_MEMOP(MO_UL))
3748 
3749 #if defined(TARGET_PPC64)
3750 /* ldarx */
3751 LARX(ldarx, DEF_MEMOP(MO_UQ))
3752 /* stdcx. */
3753 STCX(stdcx_, DEF_MEMOP(MO_UQ))
3754 
3755 /* lqarx */
3756 static void gen_lqarx(DisasContext *ctx)
3757 {
3758     int rd = rD(ctx->opcode);
3759     TCGv EA, hi, lo;
3760 
3761     if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3762                  (rd == rB(ctx->opcode)))) {
3763         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3764         return;
3765     }
3766 
3767     gen_set_access_type(ctx, ACCESS_RES);
3768     EA = tcg_temp_new();
3769     gen_addr_reg_index(ctx, EA);
3770 
3771     /* Note that the low part is always in RD+1, even in LE mode.  */
3772     lo = cpu_gpr[rd + 1];
3773     hi = cpu_gpr[rd];
3774 
3775     if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3776         if (HAVE_ATOMIC128) {
3777             TCGv_i32 oi = tcg_temp_new_i32();
3778             if (ctx->le_mode) {
3779                 tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN,
3780                                                     ctx->mem_idx));
3781                 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3782             } else {
3783                 tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN,
3784                                                     ctx->mem_idx));
3785                 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3786             }
3787             tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
3788         } else {
3789             /* Restart with exclusive lock.  */
3790             gen_helper_exit_atomic(cpu_env);
3791             ctx->base.is_jmp = DISAS_NORETURN;
3792             return;
3793         }
3794     } else if (ctx->le_mode) {
3795         tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEUQ | MO_ALIGN_16);
3796         tcg_gen_mov_tl(cpu_reserve, EA);
3797         gen_addr_add(ctx, EA, EA, 8);
3798         tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEUQ);
3799     } else {
3800         tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEUQ | MO_ALIGN_16);
3801         tcg_gen_mov_tl(cpu_reserve, EA);
3802         gen_addr_add(ctx, EA, EA, 8);
3803         tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEUQ);
3804     }
3805 
3806     tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
3807     tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
3808 }
3809 
3810 /* stqcx. */
3811 static void gen_stqcx_(DisasContext *ctx)
3812 {
3813     TCGLabel *lab_fail, *lab_over;
3814     int rs = rS(ctx->opcode);
3815     TCGv EA, t0, t1;
3816     TCGv_i128 cmp, val;
3817 
3818     if (unlikely(rs & 1)) {
3819         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3820         return;
3821     }
3822 
3823     lab_fail = gen_new_label();
3824     lab_over = gen_new_label();
3825 
3826     gen_set_access_type(ctx, ACCESS_RES);
3827     EA = tcg_temp_new();
3828     gen_addr_reg_index(ctx, EA);
3829 
3830     tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
3831 
3832     cmp = tcg_temp_new_i128();
3833     val = tcg_temp_new_i128();
3834 
3835     tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val);
3836 
3837     /* Note that the low part is always in RS+1, even in LE mode.  */
3838     tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]);
3839 
3840     tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx,
3841                                 DEF_MEMOP(MO_128 | MO_ALIGN));
3842 
3843     t0 = tcg_temp_new();
3844     t1 = tcg_temp_new();
3845     tcg_gen_extr_i128_i64(t1, t0, val);
3846 
3847     tcg_gen_xor_tl(t1, t1, cpu_reserve_val2);
3848     tcg_gen_xor_tl(t0, t0, cpu_reserve_val);
3849     tcg_gen_or_tl(t0, t0, t1);
3850 
3851     tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0);
3852     tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3853     tcg_gen_or_tl(t0, t0, cpu_so);
3854     tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3855 
3856     tcg_gen_br(lab_over);
3857     gen_set_label(lab_fail);
3858 
3859     /*
3860      * Address mismatch implies failure.  But we still need to provide
3861      * the memory barrier semantics of the instruction.
3862      */
3863     tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3864     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3865 
3866     gen_set_label(lab_over);
3867     tcg_gen_movi_tl(cpu_reserve, -1);
3868 }
3869 #endif /* defined(TARGET_PPC64) */
3870 
3871 /* sync */
3872 static void gen_sync(DisasContext *ctx)
3873 {
3874     TCGBar bar = TCG_MO_ALL;
3875     uint32_t l = (ctx->opcode >> 21) & 3;
3876 
3877     if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) {
3878         bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST;
3879     }
3880 
3881     /*
3882      * We may need to check for a pending TLB flush.
3883      *
3884      * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3885      *
3886      * Additionally, this can only happen in kernel mode however so
3887      * check MSR_PR as well.
3888      */
3889     if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3890         gen_check_tlb_flush(ctx, true);
3891     }
3892 
3893     tcg_gen_mb(bar | TCG_BAR_SC);
3894 }
3895 
3896 /* wait */
3897 static void gen_wait(DisasContext *ctx)
3898 {
3899     uint32_t wc;
3900 
3901     if (ctx->insns_flags & PPC_WAIT) {
3902         /* v2.03-v2.07 define an older incompatible 'wait' encoding. */
3903 
3904         if (ctx->insns_flags2 & PPC2_PM_ISA206) {
3905             /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */
3906             wc = WC(ctx->opcode);
3907         } else {
3908             wc = 0;
3909         }
3910 
3911     } else if (ctx->insns_flags2 & PPC2_ISA300) {
3912         /* v3.0 defines a new 'wait' encoding. */
3913         wc = WC(ctx->opcode);
3914         if (ctx->insns_flags2 & PPC2_ISA310) {
3915             uint32_t pl = PL(ctx->opcode);
3916 
3917             /* WC 1,2 may be treated as no-op. WC 3 is reserved. */
3918             if (wc == 3) {
3919                 gen_invalid(ctx);
3920                 return;
3921             }
3922 
3923             /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */
3924             if (pl > 0 && wc != 2) {
3925                 gen_invalid(ctx);
3926                 return;
3927             }
3928 
3929         } else { /* ISA300 */
3930             /* WC 1-3 are reserved */
3931             if (wc > 0) {
3932                 gen_invalid(ctx);
3933                 return;
3934             }
3935         }
3936 
3937     } else {
3938         warn_report("wait instruction decoded with wrong ISA flags.");
3939         gen_invalid(ctx);
3940         return;
3941     }
3942 
3943     /*
3944      * wait without WC field or with WC=0 waits for an exception / interrupt
3945      * to occur.
3946      */
3947     if (wc == 0) {
3948         TCGv_i32 t0 = tcg_constant_i32(1);
3949         tcg_gen_st_i32(t0, cpu_env,
3950                        -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3951         /* Stop translation, as the CPU is supposed to sleep from now */
3952         gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3953     }
3954 
3955     /*
3956      * Other wait types must not just wait until an exception occurs because
3957      * ignoring their other wake-up conditions could cause a hang.
3958      *
3959      * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as
3960      * no-ops.
3961      *
3962      * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op.
3963      *
3964      * wc=2 waits for an implementation-specific condition, such could be
3965      * always true, so it can be implemented as a no-op.
3966      *
3967      * For v3.1, wc=1,2 are architected but may be implemented as no-ops.
3968      *
3969      * wc=1 (waitrsv) waits for an exception or a reservation to be lost.
3970      * Reservation-loss may have implementation-specific conditions, so it
3971      * can be implemented as a no-op.
3972      *
3973      * wc=2 waits for an exception or an amount of time to pass. This
3974      * amount is implementation-specific so it can be implemented as a
3975      * no-op.
3976      *
3977      * ISA v3.1 allows for execution to resume "in the rare case of
3978      * an implementation-dependent event", so in any case software must
3979      * not depend on the architected resumption condition to become
3980      * true, so no-op implementations should be architecturally correct
3981      * (if suboptimal).
3982      */
3983 }
3984 
3985 #if defined(TARGET_PPC64)
3986 static void gen_doze(DisasContext *ctx)
3987 {
3988 #if defined(CONFIG_USER_ONLY)
3989     GEN_PRIV(ctx);
3990 #else
3991     TCGv_i32 t;
3992 
3993     CHK_HV(ctx);
3994     t = tcg_constant_i32(PPC_PM_DOZE);
3995     gen_helper_pminsn(cpu_env, t);
3996     /* Stop translation, as the CPU is supposed to sleep from now */
3997     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3998 #endif /* defined(CONFIG_USER_ONLY) */
3999 }
4000 
4001 static void gen_nap(DisasContext *ctx)
4002 {
4003 #if defined(CONFIG_USER_ONLY)
4004     GEN_PRIV(ctx);
4005 #else
4006     TCGv_i32 t;
4007 
4008     CHK_HV(ctx);
4009     t = tcg_constant_i32(PPC_PM_NAP);
4010     gen_helper_pminsn(cpu_env, t);
4011     /* Stop translation, as the CPU is supposed to sleep from now */
4012     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4013 #endif /* defined(CONFIG_USER_ONLY) */
4014 }
4015 
4016 static void gen_stop(DisasContext *ctx)
4017 {
4018 #if defined(CONFIG_USER_ONLY)
4019     GEN_PRIV(ctx);
4020 #else
4021     TCGv_i32 t;
4022 
4023     CHK_HV(ctx);
4024     t = tcg_constant_i32(PPC_PM_STOP);
4025     gen_helper_pminsn(cpu_env, t);
4026     /* Stop translation, as the CPU is supposed to sleep from now */
4027     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4028 #endif /* defined(CONFIG_USER_ONLY) */
4029 }
4030 
4031 static void gen_sleep(DisasContext *ctx)
4032 {
4033 #if defined(CONFIG_USER_ONLY)
4034     GEN_PRIV(ctx);
4035 #else
4036     TCGv_i32 t;
4037 
4038     CHK_HV(ctx);
4039     t = tcg_constant_i32(PPC_PM_SLEEP);
4040     gen_helper_pminsn(cpu_env, t);
4041     /* Stop translation, as the CPU is supposed to sleep from now */
4042     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4043 #endif /* defined(CONFIG_USER_ONLY) */
4044 }
4045 
4046 static void gen_rvwinkle(DisasContext *ctx)
4047 {
4048 #if defined(CONFIG_USER_ONLY)
4049     GEN_PRIV(ctx);
4050 #else
4051     TCGv_i32 t;
4052 
4053     CHK_HV(ctx);
4054     t = tcg_constant_i32(PPC_PM_RVWINKLE);
4055     gen_helper_pminsn(cpu_env, t);
4056     /* Stop translation, as the CPU is supposed to sleep from now */
4057     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4058 #endif /* defined(CONFIG_USER_ONLY) */
4059 }
4060 #endif /* #if defined(TARGET_PPC64) */
4061 
4062 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
4063 {
4064 #if defined(TARGET_PPC64)
4065     if (ctx->has_cfar) {
4066         tcg_gen_movi_tl(cpu_cfar, nip);
4067     }
4068 #endif
4069 }
4070 
4071 #if defined(TARGET_PPC64)
4072 static void pmu_count_insns(DisasContext *ctx)
4073 {
4074     /*
4075      * Do not bother calling the helper if the PMU isn't counting
4076      * instructions.
4077      */
4078     if (!ctx->pmu_insn_cnt) {
4079         return;
4080     }
4081 
4082  #if !defined(CONFIG_USER_ONLY)
4083     TCGLabel *l;
4084     TCGv t0;
4085 
4086     /*
4087      * The PMU insns_inc() helper stops the internal PMU timer if a
4088      * counter overflows happens. In that case, if the guest is
4089      * running with icount and we do not handle it beforehand,
4090      * the helper can trigger a 'bad icount read'.
4091      */
4092     gen_icount_io_start(ctx);
4093 
4094     /* Avoid helper calls when only PMC5-6 are enabled. */
4095     if (!ctx->pmc_other) {
4096         l = gen_new_label();
4097         t0 = tcg_temp_new();
4098 
4099         gen_load_spr(t0, SPR_POWER_PMC5);
4100         tcg_gen_addi_tl(t0, t0, ctx->base.num_insns);
4101         gen_store_spr(SPR_POWER_PMC5, t0);
4102         /* Check for overflow, if it's enabled */
4103         if (ctx->mmcr0_pmcjce) {
4104             tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l);
4105             gen_helper_handle_pmc5_overflow(cpu_env);
4106         }
4107 
4108         gen_set_label(l);
4109     } else {
4110         gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns));
4111     }
4112   #else
4113     /*
4114      * User mode can read (but not write) PMC5 and start/stop
4115      * the PMU via MMCR0_FC. In this case just increment
4116      * PMC5 with base.num_insns.
4117      */
4118     TCGv t0 = tcg_temp_new();
4119 
4120     gen_load_spr(t0, SPR_POWER_PMC5);
4121     tcg_gen_addi_tl(t0, t0, ctx->base.num_insns);
4122     gen_store_spr(SPR_POWER_PMC5, t0);
4123   #endif /* #if !defined(CONFIG_USER_ONLY) */
4124 }
4125 #else
4126 static void pmu_count_insns(DisasContext *ctx)
4127 {
4128     return;
4129 }
4130 #endif /* #if defined(TARGET_PPC64) */
4131 
4132 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
4133 {
4134     return translator_use_goto_tb(&ctx->base, dest);
4135 }
4136 
4137 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
4138 {
4139     if (unlikely(ctx->singlestep_enabled)) {
4140         gen_debug_exception(ctx);
4141     } else {
4142         /*
4143          * tcg_gen_lookup_and_goto_ptr will exit the TB if
4144          * CF_NO_GOTO_PTR is set. Count insns now.
4145          */
4146         if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
4147             pmu_count_insns(ctx);
4148         }
4149 
4150         tcg_gen_lookup_and_goto_ptr();
4151     }
4152 }
4153 
4154 /***                                Branch                                 ***/
4155 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4156 {
4157     if (NARROW_MODE(ctx)) {
4158         dest = (uint32_t) dest;
4159     }
4160     if (use_goto_tb(ctx, dest)) {
4161         pmu_count_insns(ctx);
4162         tcg_gen_goto_tb(n);
4163         tcg_gen_movi_tl(cpu_nip, dest & ~3);
4164         tcg_gen_exit_tb(ctx->base.tb, n);
4165     } else {
4166         tcg_gen_movi_tl(cpu_nip, dest & ~3);
4167         gen_lookup_and_goto_ptr(ctx);
4168     }
4169 }
4170 
4171 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
4172 {
4173     if (NARROW_MODE(ctx)) {
4174         nip = (uint32_t)nip;
4175     }
4176     tcg_gen_movi_tl(cpu_lr, nip);
4177 }
4178 
4179 /* b ba bl bla */
4180 static void gen_b(DisasContext *ctx)
4181 {
4182     target_ulong li, target;
4183 
4184     /* sign extend LI */
4185     li = LI(ctx->opcode);
4186     li = (li ^ 0x02000000) - 0x02000000;
4187     if (likely(AA(ctx->opcode) == 0)) {
4188         target = ctx->cia + li;
4189     } else {
4190         target = li;
4191     }
4192     if (LK(ctx->opcode)) {
4193         gen_setlr(ctx, ctx->base.pc_next);
4194     }
4195     gen_update_cfar(ctx, ctx->cia);
4196     gen_goto_tb(ctx, 0, target);
4197     ctx->base.is_jmp = DISAS_NORETURN;
4198 }
4199 
4200 #define BCOND_IM  0
4201 #define BCOND_LR  1
4202 #define BCOND_CTR 2
4203 #define BCOND_TAR 3
4204 
4205 static void gen_bcond(DisasContext *ctx, int type)
4206 {
4207     uint32_t bo = BO(ctx->opcode);
4208     TCGLabel *l1;
4209     TCGv target;
4210 
4211     if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4212         target = tcg_temp_new();
4213         if (type == BCOND_CTR) {
4214             tcg_gen_mov_tl(target, cpu_ctr);
4215         } else if (type == BCOND_TAR) {
4216             gen_load_spr(target, SPR_TAR);
4217         } else {
4218             tcg_gen_mov_tl(target, cpu_lr);
4219         }
4220     } else {
4221         target = NULL;
4222     }
4223     if (LK(ctx->opcode)) {
4224         gen_setlr(ctx, ctx->base.pc_next);
4225     }
4226     l1 = gen_new_label();
4227     if ((bo & 0x4) == 0) {
4228         /* Decrement and test CTR */
4229         TCGv temp = tcg_temp_new();
4230 
4231         if (type == BCOND_CTR) {
4232             /*
4233              * All ISAs up to v3 describe this form of bcctr as invalid but
4234              * some processors, ie. 64-bit server processors compliant with
4235              * arch 2.x, do implement a "test and decrement" logic instead,
4236              * as described in their respective UMs. This logic involves CTR
4237              * to act as both the branch target and a counter, which makes
4238              * it basically useless and thus never used in real code.
4239              *
4240              * This form was hence chosen to trigger extra micro-architectural
4241              * side-effect on real HW needed for the Spectre v2 workaround.
4242              * It is up to guests that implement such workaround, ie. linux, to
4243              * use this form in a way it just triggers the side-effect without
4244              * doing anything else harmful.
4245              */
4246             if (unlikely(!is_book3s_arch2x(ctx))) {
4247                 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4248                 return;
4249             }
4250 
4251             if (NARROW_MODE(ctx)) {
4252                 tcg_gen_ext32u_tl(temp, cpu_ctr);
4253             } else {
4254                 tcg_gen_mov_tl(temp, cpu_ctr);
4255             }
4256             if (bo & 0x2) {
4257                 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4258             } else {
4259                 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4260             }
4261             tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4262         } else {
4263             tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4264             if (NARROW_MODE(ctx)) {
4265                 tcg_gen_ext32u_tl(temp, cpu_ctr);
4266             } else {
4267                 tcg_gen_mov_tl(temp, cpu_ctr);
4268             }
4269             if (bo & 0x2) {
4270                 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4271             } else {
4272                 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4273             }
4274         }
4275     }
4276     if ((bo & 0x10) == 0) {
4277         /* Test CR */
4278         uint32_t bi = BI(ctx->opcode);
4279         uint32_t mask = 0x08 >> (bi & 0x03);
4280         TCGv_i32 temp = tcg_temp_new_i32();
4281 
4282         if (bo & 0x8) {
4283             tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4284             tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4285         } else {
4286             tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4287             tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4288         }
4289     }
4290     gen_update_cfar(ctx, ctx->cia);
4291     if (type == BCOND_IM) {
4292         target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4293         if (likely(AA(ctx->opcode) == 0)) {
4294             gen_goto_tb(ctx, 0, ctx->cia + li);
4295         } else {
4296             gen_goto_tb(ctx, 0, li);
4297         }
4298     } else {
4299         if (NARROW_MODE(ctx)) {
4300             tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4301         } else {
4302             tcg_gen_andi_tl(cpu_nip, target, ~3);
4303         }
4304         gen_lookup_and_goto_ptr(ctx);
4305     }
4306     if ((bo & 0x14) != 0x14) {
4307         /* fallthrough case */
4308         gen_set_label(l1);
4309         gen_goto_tb(ctx, 1, ctx->base.pc_next);
4310     }
4311     ctx->base.is_jmp = DISAS_NORETURN;
4312 }
4313 
4314 static void gen_bc(DisasContext *ctx)
4315 {
4316     gen_bcond(ctx, BCOND_IM);
4317 }
4318 
4319 static void gen_bcctr(DisasContext *ctx)
4320 {
4321     gen_bcond(ctx, BCOND_CTR);
4322 }
4323 
4324 static void gen_bclr(DisasContext *ctx)
4325 {
4326     gen_bcond(ctx, BCOND_LR);
4327 }
4328 
4329 static void gen_bctar(DisasContext *ctx)
4330 {
4331     gen_bcond(ctx, BCOND_TAR);
4332 }
4333 
4334 /***                      Condition register logical                       ***/
4335 #define GEN_CRLOGIC(name, tcg_op, opc)                                        \
4336 static void glue(gen_, name)(DisasContext *ctx)                               \
4337 {                                                                             \
4338     uint8_t bitmask;                                                          \
4339     int sh;                                                                   \
4340     TCGv_i32 t0, t1;                                                          \
4341     sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
4342     t0 = tcg_temp_new_i32();                                                  \
4343     if (sh > 0)                                                               \
4344         tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh);            \
4345     else if (sh < 0)                                                          \
4346         tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh);           \
4347     else                                                                      \
4348         tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]);                 \
4349     t1 = tcg_temp_new_i32();                                                  \
4350     sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
4351     if (sh > 0)                                                               \
4352         tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh);            \
4353     else if (sh < 0)                                                          \
4354         tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh);           \
4355     else                                                                      \
4356         tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]);                 \
4357     tcg_op(t0, t0, t1);                                                       \
4358     bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03);                             \
4359     tcg_gen_andi_i32(t0, t0, bitmask);                                        \
4360     tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);          \
4361     tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);                  \
4362 }
4363 
4364 /* crand */
4365 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4366 /* crandc */
4367 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4368 /* creqv */
4369 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4370 /* crnand */
4371 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4372 /* crnor */
4373 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4374 /* cror */
4375 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4376 /* crorc */
4377 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4378 /* crxor */
4379 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4380 
4381 /* mcrf */
4382 static void gen_mcrf(DisasContext *ctx)
4383 {
4384     tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4385 }
4386 
4387 /***                           System linkage                              ***/
4388 
4389 /* rfi (supervisor only) */
4390 static void gen_rfi(DisasContext *ctx)
4391 {
4392 #if defined(CONFIG_USER_ONLY)
4393     GEN_PRIV(ctx);
4394 #else
4395     /*
4396      * This instruction doesn't exist anymore on 64-bit server
4397      * processors compliant with arch 2.x
4398      */
4399     if (is_book3s_arch2x(ctx)) {
4400         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4401         return;
4402     }
4403     /* Restore CPU state */
4404     CHK_SV(ctx);
4405     gen_icount_io_start(ctx);
4406     gen_update_cfar(ctx, ctx->cia);
4407     gen_helper_rfi(cpu_env);
4408     ctx->base.is_jmp = DISAS_EXIT;
4409 #endif
4410 }
4411 
4412 #if defined(TARGET_PPC64)
4413 static void gen_rfid(DisasContext *ctx)
4414 {
4415 #if defined(CONFIG_USER_ONLY)
4416     GEN_PRIV(ctx);
4417 #else
4418     /* Restore CPU state */
4419     CHK_SV(ctx);
4420     gen_icount_io_start(ctx);
4421     gen_update_cfar(ctx, ctx->cia);
4422     gen_helper_rfid(cpu_env);
4423     ctx->base.is_jmp = DISAS_EXIT;
4424 #endif
4425 }
4426 
4427 #if !defined(CONFIG_USER_ONLY)
4428 static void gen_rfscv(DisasContext *ctx)
4429 {
4430 #if defined(CONFIG_USER_ONLY)
4431     GEN_PRIV(ctx);
4432 #else
4433     /* Restore CPU state */
4434     CHK_SV(ctx);
4435     gen_icount_io_start(ctx);
4436     gen_update_cfar(ctx, ctx->cia);
4437     gen_helper_rfscv(cpu_env);
4438     ctx->base.is_jmp = DISAS_EXIT;
4439 #endif
4440 }
4441 #endif
4442 
4443 static void gen_hrfid(DisasContext *ctx)
4444 {
4445 #if defined(CONFIG_USER_ONLY)
4446     GEN_PRIV(ctx);
4447 #else
4448     /* Restore CPU state */
4449     CHK_HV(ctx);
4450     gen_helper_hrfid(cpu_env);
4451     ctx->base.is_jmp = DISAS_EXIT;
4452 #endif
4453 }
4454 #endif
4455 
4456 /* sc */
4457 #if defined(CONFIG_USER_ONLY)
4458 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4459 #else
4460 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4461 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED
4462 #endif
4463 static void gen_sc(DisasContext *ctx)
4464 {
4465     uint32_t lev;
4466 
4467     lev = (ctx->opcode >> 5) & 0x7F;
4468     gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4469 }
4470 
4471 #if defined(TARGET_PPC64)
4472 #if !defined(CONFIG_USER_ONLY)
4473 static void gen_scv(DisasContext *ctx)
4474 {
4475     uint32_t lev = (ctx->opcode >> 5) & 0x7F;
4476 
4477     /* Set the PC back to the faulting instruction. */
4478     gen_update_nip(ctx, ctx->cia);
4479     gen_helper_scv(cpu_env, tcg_constant_i32(lev));
4480 
4481     ctx->base.is_jmp = DISAS_NORETURN;
4482 }
4483 #endif
4484 #endif
4485 
4486 /***                                Trap                                   ***/
4487 
4488 /* Check for unconditional traps (always or never) */
4489 static bool check_unconditional_trap(DisasContext *ctx)
4490 {
4491     /* Trap never */
4492     if (TO(ctx->opcode) == 0) {
4493         return true;
4494     }
4495     /* Trap always */
4496     if (TO(ctx->opcode) == 31) {
4497         gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
4498         return true;
4499     }
4500     return false;
4501 }
4502 
4503 /* tw */
4504 static void gen_tw(DisasContext *ctx)
4505 {
4506     TCGv_i32 t0;
4507 
4508     if (check_unconditional_trap(ctx)) {
4509         return;
4510     }
4511     t0 = tcg_constant_i32(TO(ctx->opcode));
4512     gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4513                   t0);
4514 }
4515 
4516 /* twi */
4517 static void gen_twi(DisasContext *ctx)
4518 {
4519     TCGv t0;
4520     TCGv_i32 t1;
4521 
4522     if (check_unconditional_trap(ctx)) {
4523         return;
4524     }
4525     t0 = tcg_constant_tl(SIMM(ctx->opcode));
4526     t1 = tcg_constant_i32(TO(ctx->opcode));
4527     gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4528 }
4529 
4530 #if defined(TARGET_PPC64)
4531 /* td */
4532 static void gen_td(DisasContext *ctx)
4533 {
4534     TCGv_i32 t0;
4535 
4536     if (check_unconditional_trap(ctx)) {
4537         return;
4538     }
4539     t0 = tcg_constant_i32(TO(ctx->opcode));
4540     gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4541                   t0);
4542 }
4543 
4544 /* tdi */
4545 static void gen_tdi(DisasContext *ctx)
4546 {
4547     TCGv t0;
4548     TCGv_i32 t1;
4549 
4550     if (check_unconditional_trap(ctx)) {
4551         return;
4552     }
4553     t0 = tcg_constant_tl(SIMM(ctx->opcode));
4554     t1 = tcg_constant_i32(TO(ctx->opcode));
4555     gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4556 }
4557 #endif
4558 
4559 /***                          Processor control                            ***/
4560 
4561 /* mcrxr */
4562 static void gen_mcrxr(DisasContext *ctx)
4563 {
4564     TCGv_i32 t0 = tcg_temp_new_i32();
4565     TCGv_i32 t1 = tcg_temp_new_i32();
4566     TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4567 
4568     tcg_gen_trunc_tl_i32(t0, cpu_so);
4569     tcg_gen_trunc_tl_i32(t1, cpu_ov);
4570     tcg_gen_trunc_tl_i32(dst, cpu_ca);
4571     tcg_gen_shli_i32(t0, t0, 3);
4572     tcg_gen_shli_i32(t1, t1, 2);
4573     tcg_gen_shli_i32(dst, dst, 1);
4574     tcg_gen_or_i32(dst, dst, t0);
4575     tcg_gen_or_i32(dst, dst, t1);
4576 
4577     tcg_gen_movi_tl(cpu_so, 0);
4578     tcg_gen_movi_tl(cpu_ov, 0);
4579     tcg_gen_movi_tl(cpu_ca, 0);
4580 }
4581 
4582 #ifdef TARGET_PPC64
4583 /* mcrxrx */
4584 static void gen_mcrxrx(DisasContext *ctx)
4585 {
4586     TCGv t0 = tcg_temp_new();
4587     TCGv t1 = tcg_temp_new();
4588     TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4589 
4590     /* copy OV and OV32 */
4591     tcg_gen_shli_tl(t0, cpu_ov, 1);
4592     tcg_gen_or_tl(t0, t0, cpu_ov32);
4593     tcg_gen_shli_tl(t0, t0, 2);
4594     /* copy CA and CA32 */
4595     tcg_gen_shli_tl(t1, cpu_ca, 1);
4596     tcg_gen_or_tl(t1, t1, cpu_ca32);
4597     tcg_gen_or_tl(t0, t0, t1);
4598     tcg_gen_trunc_tl_i32(dst, t0);
4599 }
4600 #endif
4601 
4602 /* mfcr mfocrf */
4603 static void gen_mfcr(DisasContext *ctx)
4604 {
4605     uint32_t crm, crn;
4606 
4607     if (likely(ctx->opcode & 0x00100000)) {
4608         crm = CRM(ctx->opcode);
4609         if (likely(crm && ((crm & (crm - 1)) == 0))) {
4610             crn = ctz32(crm);
4611             tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4612             tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4613                             cpu_gpr[rD(ctx->opcode)], crn * 4);
4614         }
4615     } else {
4616         TCGv_i32 t0 = tcg_temp_new_i32();
4617         tcg_gen_mov_i32(t0, cpu_crf[0]);
4618         tcg_gen_shli_i32(t0, t0, 4);
4619         tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4620         tcg_gen_shli_i32(t0, t0, 4);
4621         tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4622         tcg_gen_shli_i32(t0, t0, 4);
4623         tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4624         tcg_gen_shli_i32(t0, t0, 4);
4625         tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4626         tcg_gen_shli_i32(t0, t0, 4);
4627         tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4628         tcg_gen_shli_i32(t0, t0, 4);
4629         tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4630         tcg_gen_shli_i32(t0, t0, 4);
4631         tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4632         tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4633     }
4634 }
4635 
4636 /* mfmsr */
4637 static void gen_mfmsr(DisasContext *ctx)
4638 {
4639     CHK_SV(ctx);
4640     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4641 }
4642 
4643 /* mfspr */
4644 static inline void gen_op_mfspr(DisasContext *ctx)
4645 {
4646     void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4647     uint32_t sprn = SPR(ctx->opcode);
4648 
4649 #if defined(CONFIG_USER_ONLY)
4650     read_cb = ctx->spr_cb[sprn].uea_read;
4651 #else
4652     if (ctx->pr) {
4653         read_cb = ctx->spr_cb[sprn].uea_read;
4654     } else if (ctx->hv) {
4655         read_cb = ctx->spr_cb[sprn].hea_read;
4656     } else {
4657         read_cb = ctx->spr_cb[sprn].oea_read;
4658     }
4659 #endif
4660     if (likely(read_cb != NULL)) {
4661         if (likely(read_cb != SPR_NOACCESS)) {
4662             (*read_cb)(ctx, rD(ctx->opcode), sprn);
4663         } else {
4664             /* Privilege exception */
4665             /*
4666              * This is a hack to avoid warnings when running Linux:
4667              * this OS breaks the PowerPC virtualisation model,
4668              * allowing userland application to read the PVR
4669              */
4670             if (sprn != SPR_PVR) {
4671                 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
4672                               "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4673                               ctx->cia);
4674             }
4675             gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4676         }
4677     } else {
4678         /* ISA 2.07 defines these as no-ops */
4679         if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4680             (sprn >= 808 && sprn <= 811)) {
4681             /* This is a nop */
4682             return;
4683         }
4684         /* Not defined */
4685         qemu_log_mask(LOG_GUEST_ERROR,
4686                       "Trying to read invalid spr %d (0x%03x) at "
4687                       TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
4688 
4689         /*
4690          * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4691          * generate a priv, a hv emu or a no-op
4692          */
4693         if (sprn & 0x10) {
4694             if (ctx->pr) {
4695                 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4696             }
4697         } else {
4698             if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4699                 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4700             }
4701         }
4702     }
4703 }
4704 
4705 static void gen_mfspr(DisasContext *ctx)
4706 {
4707     gen_op_mfspr(ctx);
4708 }
4709 
4710 /* mftb */
4711 static void gen_mftb(DisasContext *ctx)
4712 {
4713     gen_op_mfspr(ctx);
4714 }
4715 
4716 /* mtcrf mtocrf*/
4717 static void gen_mtcrf(DisasContext *ctx)
4718 {
4719     uint32_t crm, crn;
4720 
4721     crm = CRM(ctx->opcode);
4722     if (likely((ctx->opcode & 0x00100000))) {
4723         if (crm && ((crm & (crm - 1)) == 0)) {
4724             TCGv_i32 temp = tcg_temp_new_i32();
4725             crn = ctz32(crm);
4726             tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4727             tcg_gen_shri_i32(temp, temp, crn * 4);
4728             tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4729         }
4730     } else {
4731         TCGv_i32 temp = tcg_temp_new_i32();
4732         tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4733         for (crn = 0 ; crn < 8 ; crn++) {
4734             if (crm & (1 << crn)) {
4735                     tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4736                     tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4737             }
4738         }
4739     }
4740 }
4741 
4742 /* mtmsr */
4743 #if defined(TARGET_PPC64)
4744 static void gen_mtmsrd(DisasContext *ctx)
4745 {
4746     if (unlikely(!is_book3s_arch2x(ctx))) {
4747         gen_invalid(ctx);
4748         return;
4749     }
4750 
4751     CHK_SV(ctx);
4752 
4753 #if !defined(CONFIG_USER_ONLY)
4754     TCGv t0, t1;
4755     target_ulong mask;
4756 
4757     t0 = tcg_temp_new();
4758     t1 = tcg_temp_new();
4759 
4760     gen_icount_io_start(ctx);
4761 
4762     if (ctx->opcode & 0x00010000) {
4763         /* L=1 form only updates EE and RI */
4764         mask = (1ULL << MSR_RI) | (1ULL << MSR_EE);
4765     } else {
4766         /* mtmsrd does not alter HV, S, ME, or LE */
4767         mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) |
4768                  (1ULL << MSR_HV));
4769         /*
4770          * XXX: we need to update nip before the store if we enter
4771          *      power saving mode, we will exit the loop directly from
4772          *      ppc_store_msr
4773          */
4774         gen_update_nip(ctx, ctx->base.pc_next);
4775     }
4776 
4777     tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
4778     tcg_gen_andi_tl(t1, cpu_msr, ~mask);
4779     tcg_gen_or_tl(t0, t0, t1);
4780 
4781     gen_helper_store_msr(cpu_env, t0);
4782 
4783     /* Must stop the translation as machine state (may have) changed */
4784     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
4785 #endif /* !defined(CONFIG_USER_ONLY) */
4786 }
4787 #endif /* defined(TARGET_PPC64) */
4788 
4789 static void gen_mtmsr(DisasContext *ctx)
4790 {
4791     CHK_SV(ctx);
4792 
4793 #if !defined(CONFIG_USER_ONLY)
4794     TCGv t0, t1;
4795     target_ulong mask = 0xFFFFFFFF;
4796 
4797     t0 = tcg_temp_new();
4798     t1 = tcg_temp_new();
4799 
4800     gen_icount_io_start(ctx);
4801     if (ctx->opcode & 0x00010000) {
4802         /* L=1 form only updates EE and RI */
4803         mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE);
4804     } else {
4805         /* mtmsr does not alter S, ME, or LE */
4806         mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S));
4807 
4808         /*
4809          * XXX: we need to update nip before the store if we enter
4810          *      power saving mode, we will exit the loop directly from
4811          *      ppc_store_msr
4812          */
4813         gen_update_nip(ctx, ctx->base.pc_next);
4814     }
4815 
4816     tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
4817     tcg_gen_andi_tl(t1, cpu_msr, ~mask);
4818     tcg_gen_or_tl(t0, t0, t1);
4819 
4820     gen_helper_store_msr(cpu_env, t0);
4821 
4822     /* Must stop the translation as machine state (may have) changed */
4823     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
4824 #endif
4825 }
4826 
4827 /* mtspr */
4828 static void gen_mtspr(DisasContext *ctx)
4829 {
4830     void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4831     uint32_t sprn = SPR(ctx->opcode);
4832 
4833 #if defined(CONFIG_USER_ONLY)
4834     write_cb = ctx->spr_cb[sprn].uea_write;
4835 #else
4836     if (ctx->pr) {
4837         write_cb = ctx->spr_cb[sprn].uea_write;
4838     } else if (ctx->hv) {
4839         write_cb = ctx->spr_cb[sprn].hea_write;
4840     } else {
4841         write_cb = ctx->spr_cb[sprn].oea_write;
4842     }
4843 #endif
4844     if (likely(write_cb != NULL)) {
4845         if (likely(write_cb != SPR_NOACCESS)) {
4846             (*write_cb)(ctx, sprn, rS(ctx->opcode));
4847         } else {
4848             /* Privilege exception */
4849             qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4850                           "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4851                           ctx->cia);
4852             gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4853         }
4854     } else {
4855         /* ISA 2.07 defines these as no-ops */
4856         if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4857             (sprn >= 808 && sprn <= 811)) {
4858             /* This is a nop */
4859             return;
4860         }
4861 
4862         /* Not defined */
4863         qemu_log_mask(LOG_GUEST_ERROR,
4864                       "Trying to write invalid spr %d (0x%03x) at "
4865                       TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
4866 
4867 
4868         /*
4869          * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4870          * generate a priv, a hv emu or a no-op
4871          */
4872         if (sprn & 0x10) {
4873             if (ctx->pr) {
4874                 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4875             }
4876         } else {
4877             if (ctx->pr || sprn == 0) {
4878                 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4879             }
4880         }
4881     }
4882 }
4883 
4884 #if defined(TARGET_PPC64)
4885 /* setb */
4886 static void gen_setb(DisasContext *ctx)
4887 {
4888     TCGv_i32 t0 = tcg_temp_new_i32();
4889     TCGv_i32 t8 = tcg_constant_i32(8);
4890     TCGv_i32 tm1 = tcg_constant_i32(-1);
4891     int crf = crfS(ctx->opcode);
4892 
4893     tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4894     tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4895     tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4896 }
4897 #endif
4898 
4899 /***                         Cache management                              ***/
4900 
4901 /* dcbf */
4902 static void gen_dcbf(DisasContext *ctx)
4903 {
4904     /* XXX: specification says this is treated as a load by the MMU */
4905     TCGv t0;
4906     gen_set_access_type(ctx, ACCESS_CACHE);
4907     t0 = tcg_temp_new();
4908     gen_addr_reg_index(ctx, t0);
4909     gen_qemu_ld8u(ctx, t0, t0);
4910 }
4911 
4912 /* dcbfep (external PID dcbf) */
4913 static void gen_dcbfep(DisasContext *ctx)
4914 {
4915     /* XXX: specification says this is treated as a load by the MMU */
4916     TCGv t0;
4917     CHK_SV(ctx);
4918     gen_set_access_type(ctx, ACCESS_CACHE);
4919     t0 = tcg_temp_new();
4920     gen_addr_reg_index(ctx, t0);
4921     tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4922 }
4923 
4924 /* dcbi (Supervisor only) */
4925 static void gen_dcbi(DisasContext *ctx)
4926 {
4927 #if defined(CONFIG_USER_ONLY)
4928     GEN_PRIV(ctx);
4929 #else
4930     TCGv EA, val;
4931 
4932     CHK_SV(ctx);
4933     EA = tcg_temp_new();
4934     gen_set_access_type(ctx, ACCESS_CACHE);
4935     gen_addr_reg_index(ctx, EA);
4936     val = tcg_temp_new();
4937     /* XXX: specification says this should be treated as a store by the MMU */
4938     gen_qemu_ld8u(ctx, val, EA);
4939     gen_qemu_st8(ctx, val, EA);
4940 #endif /* defined(CONFIG_USER_ONLY) */
4941 }
4942 
4943 /* dcdst */
4944 static void gen_dcbst(DisasContext *ctx)
4945 {
4946     /* XXX: specification say this is treated as a load by the MMU */
4947     TCGv t0;
4948     gen_set_access_type(ctx, ACCESS_CACHE);
4949     t0 = tcg_temp_new();
4950     gen_addr_reg_index(ctx, t0);
4951     gen_qemu_ld8u(ctx, t0, t0);
4952 }
4953 
4954 /* dcbstep (dcbstep External PID version) */
4955 static void gen_dcbstep(DisasContext *ctx)
4956 {
4957     /* XXX: specification say this is treated as a load by the MMU */
4958     TCGv t0;
4959     gen_set_access_type(ctx, ACCESS_CACHE);
4960     t0 = tcg_temp_new();
4961     gen_addr_reg_index(ctx, t0);
4962     tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4963 }
4964 
4965 /* dcbt */
4966 static void gen_dcbt(DisasContext *ctx)
4967 {
4968     /*
4969      * interpreted as no-op
4970      * XXX: specification say this is treated as a load by the MMU but
4971      *      does not generate any exception
4972      */
4973 }
4974 
4975 /* dcbtep */
4976 static void gen_dcbtep(DisasContext *ctx)
4977 {
4978     /*
4979      * interpreted as no-op
4980      * XXX: specification say this is treated as a load by the MMU but
4981      *      does not generate any exception
4982      */
4983 }
4984 
4985 /* dcbtst */
4986 static void gen_dcbtst(DisasContext *ctx)
4987 {
4988     /*
4989      * interpreted as no-op
4990      * XXX: specification say this is treated as a load by the MMU but
4991      *      does not generate any exception
4992      */
4993 }
4994 
4995 /* dcbtstep */
4996 static void gen_dcbtstep(DisasContext *ctx)
4997 {
4998     /*
4999      * interpreted as no-op
5000      * XXX: specification say this is treated as a load by the MMU but
5001      *      does not generate any exception
5002      */
5003 }
5004 
5005 /* dcbtls */
5006 static void gen_dcbtls(DisasContext *ctx)
5007 {
5008     /* Always fails locking the cache */
5009     TCGv t0 = tcg_temp_new();
5010     gen_load_spr(t0, SPR_Exxx_L1CSR0);
5011     tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
5012     gen_store_spr(SPR_Exxx_L1CSR0, t0);
5013 }
5014 
5015 /* dcblc */
5016 static void gen_dcblc(DisasContext *ctx)
5017 {
5018     /*
5019      * interpreted as no-op
5020      */
5021 }
5022 
5023 /* dcbz */
5024 static void gen_dcbz(DisasContext *ctx)
5025 {
5026     TCGv tcgv_addr;
5027     TCGv_i32 tcgv_op;
5028 
5029     gen_set_access_type(ctx, ACCESS_CACHE);
5030     tcgv_addr = tcg_temp_new();
5031     tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
5032     gen_addr_reg_index(ctx, tcgv_addr);
5033     gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
5034 }
5035 
5036 /* dcbzep */
5037 static void gen_dcbzep(DisasContext *ctx)
5038 {
5039     TCGv tcgv_addr;
5040     TCGv_i32 tcgv_op;
5041 
5042     gen_set_access_type(ctx, ACCESS_CACHE);
5043     tcgv_addr = tcg_temp_new();
5044     tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
5045     gen_addr_reg_index(ctx, tcgv_addr);
5046     gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
5047 }
5048 
5049 /* dst / dstt */
5050 static void gen_dst(DisasContext *ctx)
5051 {
5052     if (rA(ctx->opcode) == 0) {
5053         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5054     } else {
5055         /* interpreted as no-op */
5056     }
5057 }
5058 
5059 /* dstst /dststt */
5060 static void gen_dstst(DisasContext *ctx)
5061 {
5062     if (rA(ctx->opcode) == 0) {
5063         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5064     } else {
5065         /* interpreted as no-op */
5066     }
5067 
5068 }
5069 
5070 /* dss / dssall */
5071 static void gen_dss(DisasContext *ctx)
5072 {
5073     /* interpreted as no-op */
5074 }
5075 
5076 /* icbi */
5077 static void gen_icbi(DisasContext *ctx)
5078 {
5079     TCGv t0;
5080     gen_set_access_type(ctx, ACCESS_CACHE);
5081     t0 = tcg_temp_new();
5082     gen_addr_reg_index(ctx, t0);
5083     gen_helper_icbi(cpu_env, t0);
5084 }
5085 
5086 /* icbiep */
5087 static void gen_icbiep(DisasContext *ctx)
5088 {
5089     TCGv t0;
5090     gen_set_access_type(ctx, ACCESS_CACHE);
5091     t0 = tcg_temp_new();
5092     gen_addr_reg_index(ctx, t0);
5093     gen_helper_icbiep(cpu_env, t0);
5094 }
5095 
5096 /* Optional: */
5097 /* dcba */
5098 static void gen_dcba(DisasContext *ctx)
5099 {
5100     /*
5101      * interpreted as no-op
5102      * XXX: specification say this is treated as a store by the MMU
5103      *      but does not generate any exception
5104      */
5105 }
5106 
5107 /***                    Segment register manipulation                      ***/
5108 /* Supervisor only: */
5109 
5110 /* mfsr */
5111 static void gen_mfsr(DisasContext *ctx)
5112 {
5113 #if defined(CONFIG_USER_ONLY)
5114     GEN_PRIV(ctx);
5115 #else
5116     TCGv t0;
5117 
5118     CHK_SV(ctx);
5119     t0 = tcg_constant_tl(SR(ctx->opcode));
5120     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5121 #endif /* defined(CONFIG_USER_ONLY) */
5122 }
5123 
5124 /* mfsrin */
5125 static void gen_mfsrin(DisasContext *ctx)
5126 {
5127 #if defined(CONFIG_USER_ONLY)
5128     GEN_PRIV(ctx);
5129 #else
5130     TCGv t0;
5131 
5132     CHK_SV(ctx);
5133     t0 = tcg_temp_new();
5134     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5135     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5136 #endif /* defined(CONFIG_USER_ONLY) */
5137 }
5138 
5139 /* mtsr */
5140 static void gen_mtsr(DisasContext *ctx)
5141 {
5142 #if defined(CONFIG_USER_ONLY)
5143     GEN_PRIV(ctx);
5144 #else
5145     TCGv t0;
5146 
5147     CHK_SV(ctx);
5148     t0 = tcg_constant_tl(SR(ctx->opcode));
5149     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5150 #endif /* defined(CONFIG_USER_ONLY) */
5151 }
5152 
5153 /* mtsrin */
5154 static void gen_mtsrin(DisasContext *ctx)
5155 {
5156 #if defined(CONFIG_USER_ONLY)
5157     GEN_PRIV(ctx);
5158 #else
5159     TCGv t0;
5160     CHK_SV(ctx);
5161 
5162     t0 = tcg_temp_new();
5163     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5164     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
5165 #endif /* defined(CONFIG_USER_ONLY) */
5166 }
5167 
5168 #if defined(TARGET_PPC64)
5169 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
5170 
5171 /* mfsr */
5172 static void gen_mfsr_64b(DisasContext *ctx)
5173 {
5174 #if defined(CONFIG_USER_ONLY)
5175     GEN_PRIV(ctx);
5176 #else
5177     TCGv t0;
5178 
5179     CHK_SV(ctx);
5180     t0 = tcg_constant_tl(SR(ctx->opcode));
5181     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5182 #endif /* defined(CONFIG_USER_ONLY) */
5183 }
5184 
5185 /* mfsrin */
5186 static void gen_mfsrin_64b(DisasContext *ctx)
5187 {
5188 #if defined(CONFIG_USER_ONLY)
5189     GEN_PRIV(ctx);
5190 #else
5191     TCGv t0;
5192 
5193     CHK_SV(ctx);
5194     t0 = tcg_temp_new();
5195     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5196     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5197 #endif /* defined(CONFIG_USER_ONLY) */
5198 }
5199 
5200 /* mtsr */
5201 static void gen_mtsr_64b(DisasContext *ctx)
5202 {
5203 #if defined(CONFIG_USER_ONLY)
5204     GEN_PRIV(ctx);
5205 #else
5206     TCGv t0;
5207 
5208     CHK_SV(ctx);
5209     t0 = tcg_constant_tl(SR(ctx->opcode));
5210     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5211 #endif /* defined(CONFIG_USER_ONLY) */
5212 }
5213 
5214 /* mtsrin */
5215 static void gen_mtsrin_64b(DisasContext *ctx)
5216 {
5217 #if defined(CONFIG_USER_ONLY)
5218     GEN_PRIV(ctx);
5219 #else
5220     TCGv t0;
5221 
5222     CHK_SV(ctx);
5223     t0 = tcg_temp_new();
5224     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5225     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5226 #endif /* defined(CONFIG_USER_ONLY) */
5227 }
5228 
5229 #endif /* defined(TARGET_PPC64) */
5230 
5231 /***                      Lookaside buffer management                      ***/
5232 /* Optional & supervisor only: */
5233 
5234 /* tlbia */
5235 static void gen_tlbia(DisasContext *ctx)
5236 {
5237 #if defined(CONFIG_USER_ONLY)
5238     GEN_PRIV(ctx);
5239 #else
5240     CHK_HV(ctx);
5241 
5242     gen_helper_tlbia(cpu_env);
5243 #endif  /* defined(CONFIG_USER_ONLY) */
5244 }
5245 
5246 /* tlbsync */
5247 static void gen_tlbsync(DisasContext *ctx)
5248 {
5249 #if defined(CONFIG_USER_ONLY)
5250     GEN_PRIV(ctx);
5251 #else
5252 
5253     if (ctx->gtse) {
5254         CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */
5255     } else {
5256         CHK_HV(ctx); /* Else hypervisor privileged */
5257     }
5258 
5259     /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
5260     if (ctx->insns_flags & PPC_BOOKE) {
5261         gen_check_tlb_flush(ctx, true);
5262     }
5263 #endif /* defined(CONFIG_USER_ONLY) */
5264 }
5265 
5266 /***                              External control                         ***/
5267 /* Optional: */
5268 
5269 /* eciwx */
5270 static void gen_eciwx(DisasContext *ctx)
5271 {
5272     TCGv t0;
5273     /* Should check EAR[E] ! */
5274     gen_set_access_type(ctx, ACCESS_EXT);
5275     t0 = tcg_temp_new();
5276     gen_addr_reg_index(ctx, t0);
5277     tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5278                        DEF_MEMOP(MO_UL | MO_ALIGN));
5279 }
5280 
5281 /* ecowx */
5282 static void gen_ecowx(DisasContext *ctx)
5283 {
5284     TCGv t0;
5285     /* Should check EAR[E] ! */
5286     gen_set_access_type(ctx, ACCESS_EXT);
5287     t0 = tcg_temp_new();
5288     gen_addr_reg_index(ctx, t0);
5289     tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5290                        DEF_MEMOP(MO_UL | MO_ALIGN));
5291 }
5292 
5293 /* 602 - 603 - G2 TLB management */
5294 
5295 /* tlbld */
5296 static void gen_tlbld_6xx(DisasContext *ctx)
5297 {
5298 #if defined(CONFIG_USER_ONLY)
5299     GEN_PRIV(ctx);
5300 #else
5301     CHK_SV(ctx);
5302     gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5303 #endif /* defined(CONFIG_USER_ONLY) */
5304 }
5305 
5306 /* tlbli */
5307 static void gen_tlbli_6xx(DisasContext *ctx)
5308 {
5309 #if defined(CONFIG_USER_ONLY)
5310     GEN_PRIV(ctx);
5311 #else
5312     CHK_SV(ctx);
5313     gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5314 #endif /* defined(CONFIG_USER_ONLY) */
5315 }
5316 
5317 /* BookE specific instructions */
5318 
5319 /* XXX: not implemented on 440 ? */
5320 static void gen_mfapidi(DisasContext *ctx)
5321 {
5322     /* XXX: TODO */
5323     gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5324 }
5325 
5326 /* XXX: not implemented on 440 ? */
5327 static void gen_tlbiva(DisasContext *ctx)
5328 {
5329 #if defined(CONFIG_USER_ONLY)
5330     GEN_PRIV(ctx);
5331 #else
5332     TCGv t0;
5333 
5334     CHK_SV(ctx);
5335     t0 = tcg_temp_new();
5336     gen_addr_reg_index(ctx, t0);
5337     gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5338 #endif /* defined(CONFIG_USER_ONLY) */
5339 }
5340 
5341 /* All 405 MAC instructions are translated here */
5342 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5343                                         int ra, int rb, int rt, int Rc)
5344 {
5345     TCGv t0, t1;
5346 
5347     t0 = tcg_temp_new();
5348     t1 = tcg_temp_new();
5349 
5350     switch (opc3 & 0x0D) {
5351     case 0x05:
5352         /* macchw    - macchw.    - macchwo   - macchwo.   */
5353         /* macchws   - macchws.   - macchwso  - macchwso.  */
5354         /* nmacchw   - nmacchw.   - nmacchwo  - nmacchwo.  */
5355         /* nmacchws  - nmacchws.  - nmacchwso - nmacchwso. */
5356         /* mulchw - mulchw. */
5357         tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5358         tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5359         tcg_gen_ext16s_tl(t1, t1);
5360         break;
5361     case 0x04:
5362         /* macchwu   - macchwu.   - macchwuo  - macchwuo.  */
5363         /* macchwsu  - macchwsu.  - macchwsuo - macchwsuo. */
5364         /* mulchwu - mulchwu. */
5365         tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5366         tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5367         tcg_gen_ext16u_tl(t1, t1);
5368         break;
5369     case 0x01:
5370         /* machhw    - machhw.    - machhwo   - machhwo.   */
5371         /* machhws   - machhws.   - machhwso  - machhwso.  */
5372         /* nmachhw   - nmachhw.   - nmachhwo  - nmachhwo.  */
5373         /* nmachhws  - nmachhws.  - nmachhwso - nmachhwso. */
5374         /* mulhhw - mulhhw. */
5375         tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5376         tcg_gen_ext16s_tl(t0, t0);
5377         tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5378         tcg_gen_ext16s_tl(t1, t1);
5379         break;
5380     case 0x00:
5381         /* machhwu   - machhwu.   - machhwuo  - machhwuo.  */
5382         /* machhwsu  - machhwsu.  - machhwsuo - machhwsuo. */
5383         /* mulhhwu - mulhhwu. */
5384         tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5385         tcg_gen_ext16u_tl(t0, t0);
5386         tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5387         tcg_gen_ext16u_tl(t1, t1);
5388         break;
5389     case 0x0D:
5390         /* maclhw    - maclhw.    - maclhwo   - maclhwo.   */
5391         /* maclhws   - maclhws.   - maclhwso  - maclhwso.  */
5392         /* nmaclhw   - nmaclhw.   - nmaclhwo  - nmaclhwo.  */
5393         /* nmaclhws  - nmaclhws.  - nmaclhwso - nmaclhwso. */
5394         /* mullhw - mullhw. */
5395         tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5396         tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5397         break;
5398     case 0x0C:
5399         /* maclhwu   - maclhwu.   - maclhwuo  - maclhwuo.  */
5400         /* maclhwsu  - maclhwsu.  - maclhwsuo - maclhwsuo. */
5401         /* mullhwu - mullhwu. */
5402         tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5403         tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5404         break;
5405     }
5406     if (opc2 & 0x04) {
5407         /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5408         tcg_gen_mul_tl(t1, t0, t1);
5409         if (opc2 & 0x02) {
5410             /* nmultiply-and-accumulate (0x0E) */
5411             tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5412         } else {
5413             /* multiply-and-accumulate (0x0C) */
5414             tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5415         }
5416 
5417         if (opc3 & 0x12) {
5418             /* Check overflow and/or saturate */
5419             TCGLabel *l1 = gen_new_label();
5420 
5421             if (opc3 & 0x10) {
5422                 /* Start with XER OV disabled, the most likely case */
5423                 tcg_gen_movi_tl(cpu_ov, 0);
5424             }
5425             if (opc3 & 0x01) {
5426                 /* Signed */
5427                 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5428                 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5429                 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5430                 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5431                 if (opc3 & 0x02) {
5432                     /* Saturate */
5433                     tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5434                     tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5435                 }
5436             } else {
5437                 /* Unsigned */
5438                 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5439                 if (opc3 & 0x02) {
5440                     /* Saturate */
5441                     tcg_gen_movi_tl(t0, UINT32_MAX);
5442                 }
5443             }
5444             if (opc3 & 0x10) {
5445                 /* Check overflow */
5446                 tcg_gen_movi_tl(cpu_ov, 1);
5447                 tcg_gen_movi_tl(cpu_so, 1);
5448             }
5449             gen_set_label(l1);
5450             tcg_gen_mov_tl(cpu_gpr[rt], t0);
5451         }
5452     } else {
5453         tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5454     }
5455     if (unlikely(Rc) != 0) {
5456         /* Update Rc0 */
5457         gen_set_Rc0(ctx, cpu_gpr[rt]);
5458     }
5459 }
5460 
5461 #define GEN_MAC_HANDLER(name, opc2, opc3)                                     \
5462 static void glue(gen_, name)(DisasContext *ctx)                               \
5463 {                                                                             \
5464     gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode),   \
5465                          rD(ctx->opcode), Rc(ctx->opcode));                   \
5466 }
5467 
5468 /* macchw    - macchw.    */
5469 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5470 /* macchwo   - macchwo.   */
5471 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5472 /* macchws   - macchws.   */
5473 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5474 /* macchwso  - macchwso.  */
5475 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5476 /* macchwsu  - macchwsu.  */
5477 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5478 /* macchwsuo - macchwsuo. */
5479 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5480 /* macchwu   - macchwu.   */
5481 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5482 /* macchwuo  - macchwuo.  */
5483 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5484 /* machhw    - machhw.    */
5485 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5486 /* machhwo   - machhwo.   */
5487 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5488 /* machhws   - machhws.   */
5489 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5490 /* machhwso  - machhwso.  */
5491 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5492 /* machhwsu  - machhwsu.  */
5493 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5494 /* machhwsuo - machhwsuo. */
5495 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5496 /* machhwu   - machhwu.   */
5497 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5498 /* machhwuo  - machhwuo.  */
5499 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5500 /* maclhw    - maclhw.    */
5501 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5502 /* maclhwo   - maclhwo.   */
5503 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5504 /* maclhws   - maclhws.   */
5505 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5506 /* maclhwso  - maclhwso.  */
5507 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5508 /* maclhwu   - maclhwu.   */
5509 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5510 /* maclhwuo  - maclhwuo.  */
5511 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5512 /* maclhwsu  - maclhwsu.  */
5513 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5514 /* maclhwsuo - maclhwsuo. */
5515 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5516 /* nmacchw   - nmacchw.   */
5517 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5518 /* nmacchwo  - nmacchwo.  */
5519 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5520 /* nmacchws  - nmacchws.  */
5521 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5522 /* nmacchwso - nmacchwso. */
5523 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5524 /* nmachhw   - nmachhw.   */
5525 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5526 /* nmachhwo  - nmachhwo.  */
5527 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5528 /* nmachhws  - nmachhws.  */
5529 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5530 /* nmachhwso - nmachhwso. */
5531 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5532 /* nmaclhw   - nmaclhw.   */
5533 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5534 /* nmaclhwo  - nmaclhwo.  */
5535 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5536 /* nmaclhws  - nmaclhws.  */
5537 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5538 /* nmaclhwso - nmaclhwso. */
5539 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5540 
5541 /* mulchw  - mulchw.  */
5542 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5543 /* mulchwu - mulchwu. */
5544 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5545 /* mulhhw  - mulhhw.  */
5546 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5547 /* mulhhwu - mulhhwu. */
5548 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5549 /* mullhw  - mullhw.  */
5550 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5551 /* mullhwu - mullhwu. */
5552 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5553 
5554 /* mfdcr */
5555 static void gen_mfdcr(DisasContext *ctx)
5556 {
5557 #if defined(CONFIG_USER_ONLY)
5558     GEN_PRIV(ctx);
5559 #else
5560     TCGv dcrn;
5561 
5562     CHK_SV(ctx);
5563     dcrn = tcg_constant_tl(SPR(ctx->opcode));
5564     gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5565 #endif /* defined(CONFIG_USER_ONLY) */
5566 }
5567 
5568 /* mtdcr */
5569 static void gen_mtdcr(DisasContext *ctx)
5570 {
5571 #if defined(CONFIG_USER_ONLY)
5572     GEN_PRIV(ctx);
5573 #else
5574     TCGv dcrn;
5575 
5576     CHK_SV(ctx);
5577     dcrn = tcg_constant_tl(SPR(ctx->opcode));
5578     gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5579 #endif /* defined(CONFIG_USER_ONLY) */
5580 }
5581 
5582 /* mfdcrx */
5583 /* XXX: not implemented on 440 ? */
5584 static void gen_mfdcrx(DisasContext *ctx)
5585 {
5586 #if defined(CONFIG_USER_ONLY)
5587     GEN_PRIV(ctx);
5588 #else
5589     CHK_SV(ctx);
5590     gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5591                         cpu_gpr[rA(ctx->opcode)]);
5592     /* Note: Rc update flag set leads to undefined state of Rc0 */
5593 #endif /* defined(CONFIG_USER_ONLY) */
5594 }
5595 
5596 /* mtdcrx */
5597 /* XXX: not implemented on 440 ? */
5598 static void gen_mtdcrx(DisasContext *ctx)
5599 {
5600 #if defined(CONFIG_USER_ONLY)
5601     GEN_PRIV(ctx);
5602 #else
5603     CHK_SV(ctx);
5604     gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5605                          cpu_gpr[rS(ctx->opcode)]);
5606     /* Note: Rc update flag set leads to undefined state of Rc0 */
5607 #endif /* defined(CONFIG_USER_ONLY) */
5608 }
5609 
5610 /* dccci */
5611 static void gen_dccci(DisasContext *ctx)
5612 {
5613     CHK_SV(ctx);
5614     /* interpreted as no-op */
5615 }
5616 
5617 /* dcread */
5618 static void gen_dcread(DisasContext *ctx)
5619 {
5620 #if defined(CONFIG_USER_ONLY)
5621     GEN_PRIV(ctx);
5622 #else
5623     TCGv EA, val;
5624 
5625     CHK_SV(ctx);
5626     gen_set_access_type(ctx, ACCESS_CACHE);
5627     EA = tcg_temp_new();
5628     gen_addr_reg_index(ctx, EA);
5629     val = tcg_temp_new();
5630     gen_qemu_ld32u(ctx, val, EA);
5631     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5632 #endif /* defined(CONFIG_USER_ONLY) */
5633 }
5634 
5635 /* icbt */
5636 static void gen_icbt_40x(DisasContext *ctx)
5637 {
5638     /*
5639      * interpreted as no-op
5640      * XXX: specification say this is treated as a load by the MMU but
5641      *      does not generate any exception
5642      */
5643 }
5644 
5645 /* iccci */
5646 static void gen_iccci(DisasContext *ctx)
5647 {
5648     CHK_SV(ctx);
5649     /* interpreted as no-op */
5650 }
5651 
5652 /* icread */
5653 static void gen_icread(DisasContext *ctx)
5654 {
5655     CHK_SV(ctx);
5656     /* interpreted as no-op */
5657 }
5658 
5659 /* rfci (supervisor only) */
5660 static void gen_rfci_40x(DisasContext *ctx)
5661 {
5662 #if defined(CONFIG_USER_ONLY)
5663     GEN_PRIV(ctx);
5664 #else
5665     CHK_SV(ctx);
5666     /* Restore CPU state */
5667     gen_helper_40x_rfci(cpu_env);
5668     ctx->base.is_jmp = DISAS_EXIT;
5669 #endif /* defined(CONFIG_USER_ONLY) */
5670 }
5671 
5672 static void gen_rfci(DisasContext *ctx)
5673 {
5674 #if defined(CONFIG_USER_ONLY)
5675     GEN_PRIV(ctx);
5676 #else
5677     CHK_SV(ctx);
5678     /* Restore CPU state */
5679     gen_helper_rfci(cpu_env);
5680     ctx->base.is_jmp = DISAS_EXIT;
5681 #endif /* defined(CONFIG_USER_ONLY) */
5682 }
5683 
5684 /* BookE specific */
5685 
5686 /* XXX: not implemented on 440 ? */
5687 static void gen_rfdi(DisasContext *ctx)
5688 {
5689 #if defined(CONFIG_USER_ONLY)
5690     GEN_PRIV(ctx);
5691 #else
5692     CHK_SV(ctx);
5693     /* Restore CPU state */
5694     gen_helper_rfdi(cpu_env);
5695     ctx->base.is_jmp = DISAS_EXIT;
5696 #endif /* defined(CONFIG_USER_ONLY) */
5697 }
5698 
5699 /* XXX: not implemented on 440 ? */
5700 static void gen_rfmci(DisasContext *ctx)
5701 {
5702 #if defined(CONFIG_USER_ONLY)
5703     GEN_PRIV(ctx);
5704 #else
5705     CHK_SV(ctx);
5706     /* Restore CPU state */
5707     gen_helper_rfmci(cpu_env);
5708     ctx->base.is_jmp = DISAS_EXIT;
5709 #endif /* defined(CONFIG_USER_ONLY) */
5710 }
5711 
5712 /* TLB management - PowerPC 405 implementation */
5713 
5714 /* tlbre */
5715 static void gen_tlbre_40x(DisasContext *ctx)
5716 {
5717 #if defined(CONFIG_USER_ONLY)
5718     GEN_PRIV(ctx);
5719 #else
5720     CHK_SV(ctx);
5721     switch (rB(ctx->opcode)) {
5722     case 0:
5723         gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5724                                 cpu_gpr[rA(ctx->opcode)]);
5725         break;
5726     case 1:
5727         gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5728                                 cpu_gpr[rA(ctx->opcode)]);
5729         break;
5730     default:
5731         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5732         break;
5733     }
5734 #endif /* defined(CONFIG_USER_ONLY) */
5735 }
5736 
5737 /* tlbsx - tlbsx. */
5738 static void gen_tlbsx_40x(DisasContext *ctx)
5739 {
5740 #if defined(CONFIG_USER_ONLY)
5741     GEN_PRIV(ctx);
5742 #else
5743     TCGv t0;
5744 
5745     CHK_SV(ctx);
5746     t0 = tcg_temp_new();
5747     gen_addr_reg_index(ctx, t0);
5748     gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5749     if (Rc(ctx->opcode)) {
5750         TCGLabel *l1 = gen_new_label();
5751         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5752         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5753         tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5754         gen_set_label(l1);
5755     }
5756 #endif /* defined(CONFIG_USER_ONLY) */
5757 }
5758 
5759 /* tlbwe */
5760 static void gen_tlbwe_40x(DisasContext *ctx)
5761 {
5762 #if defined(CONFIG_USER_ONLY)
5763     GEN_PRIV(ctx);
5764 #else
5765     CHK_SV(ctx);
5766 
5767     switch (rB(ctx->opcode)) {
5768     case 0:
5769         gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5770                                 cpu_gpr[rS(ctx->opcode)]);
5771         break;
5772     case 1:
5773         gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5774                                 cpu_gpr[rS(ctx->opcode)]);
5775         break;
5776     default:
5777         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5778         break;
5779     }
5780 #endif /* defined(CONFIG_USER_ONLY) */
5781 }
5782 
5783 /* TLB management - PowerPC 440 implementation */
5784 
5785 /* tlbre */
5786 static void gen_tlbre_440(DisasContext *ctx)
5787 {
5788 #if defined(CONFIG_USER_ONLY)
5789     GEN_PRIV(ctx);
5790 #else
5791     CHK_SV(ctx);
5792 
5793     switch (rB(ctx->opcode)) {
5794     case 0:
5795     case 1:
5796     case 2:
5797         {
5798             TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
5799             gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5800                                  t0, cpu_gpr[rA(ctx->opcode)]);
5801         }
5802         break;
5803     default:
5804         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5805         break;
5806     }
5807 #endif /* defined(CONFIG_USER_ONLY) */
5808 }
5809 
5810 /* tlbsx - tlbsx. */
5811 static void gen_tlbsx_440(DisasContext *ctx)
5812 {
5813 #if defined(CONFIG_USER_ONLY)
5814     GEN_PRIV(ctx);
5815 #else
5816     TCGv t0;
5817 
5818     CHK_SV(ctx);
5819     t0 = tcg_temp_new();
5820     gen_addr_reg_index(ctx, t0);
5821     gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5822     if (Rc(ctx->opcode)) {
5823         TCGLabel *l1 = gen_new_label();
5824         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5825         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5826         tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5827         gen_set_label(l1);
5828     }
5829 #endif /* defined(CONFIG_USER_ONLY) */
5830 }
5831 
5832 /* tlbwe */
5833 static void gen_tlbwe_440(DisasContext *ctx)
5834 {
5835 #if defined(CONFIG_USER_ONLY)
5836     GEN_PRIV(ctx);
5837 #else
5838     CHK_SV(ctx);
5839     switch (rB(ctx->opcode)) {
5840     case 0:
5841     case 1:
5842     case 2:
5843         {
5844             TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
5845             gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5846                                  cpu_gpr[rS(ctx->opcode)]);
5847         }
5848         break;
5849     default:
5850         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5851         break;
5852     }
5853 #endif /* defined(CONFIG_USER_ONLY) */
5854 }
5855 
5856 /* TLB management - PowerPC BookE 2.06 implementation */
5857 
5858 /* tlbre */
5859 static void gen_tlbre_booke206(DisasContext *ctx)
5860 {
5861  #if defined(CONFIG_USER_ONLY)
5862     GEN_PRIV(ctx);
5863 #else
5864    CHK_SV(ctx);
5865     gen_helper_booke206_tlbre(cpu_env);
5866 #endif /* defined(CONFIG_USER_ONLY) */
5867 }
5868 
5869 /* tlbsx - tlbsx. */
5870 static void gen_tlbsx_booke206(DisasContext *ctx)
5871 {
5872 #if defined(CONFIG_USER_ONLY)
5873     GEN_PRIV(ctx);
5874 #else
5875     TCGv t0;
5876 
5877     CHK_SV(ctx);
5878     if (rA(ctx->opcode)) {
5879         t0 = tcg_temp_new();
5880         tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5881     } else {
5882         t0 = cpu_gpr[rB(ctx->opcode)];
5883     }
5884     gen_helper_booke206_tlbsx(cpu_env, t0);
5885 #endif /* defined(CONFIG_USER_ONLY) */
5886 }
5887 
5888 /* tlbwe */
5889 static void gen_tlbwe_booke206(DisasContext *ctx)
5890 {
5891 #if defined(CONFIG_USER_ONLY)
5892     GEN_PRIV(ctx);
5893 #else
5894     CHK_SV(ctx);
5895     gen_helper_booke206_tlbwe(cpu_env);
5896 #endif /* defined(CONFIG_USER_ONLY) */
5897 }
5898 
5899 static void gen_tlbivax_booke206(DisasContext *ctx)
5900 {
5901 #if defined(CONFIG_USER_ONLY)
5902     GEN_PRIV(ctx);
5903 #else
5904     TCGv t0;
5905 
5906     CHK_SV(ctx);
5907     t0 = tcg_temp_new();
5908     gen_addr_reg_index(ctx, t0);
5909     gen_helper_booke206_tlbivax(cpu_env, t0);
5910 #endif /* defined(CONFIG_USER_ONLY) */
5911 }
5912 
5913 static void gen_tlbilx_booke206(DisasContext *ctx)
5914 {
5915 #if defined(CONFIG_USER_ONLY)
5916     GEN_PRIV(ctx);
5917 #else
5918     TCGv t0;
5919 
5920     CHK_SV(ctx);
5921     t0 = tcg_temp_new();
5922     gen_addr_reg_index(ctx, t0);
5923 
5924     switch ((ctx->opcode >> 21) & 0x3) {
5925     case 0:
5926         gen_helper_booke206_tlbilx0(cpu_env, t0);
5927         break;
5928     case 1:
5929         gen_helper_booke206_tlbilx1(cpu_env, t0);
5930         break;
5931     case 3:
5932         gen_helper_booke206_tlbilx3(cpu_env, t0);
5933         break;
5934     default:
5935         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5936         break;
5937     }
5938 #endif /* defined(CONFIG_USER_ONLY) */
5939 }
5940 
5941 /* wrtee */
5942 static void gen_wrtee(DisasContext *ctx)
5943 {
5944 #if defined(CONFIG_USER_ONLY)
5945     GEN_PRIV(ctx);
5946 #else
5947     TCGv t0;
5948 
5949     CHK_SV(ctx);
5950     t0 = tcg_temp_new();
5951     tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5952     tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5953     tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5954     gen_ppc_maybe_interrupt(ctx);
5955     /*
5956      * Stop translation to have a chance to raise an exception if we
5957      * just set msr_ee to 1
5958      */
5959     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
5960 #endif /* defined(CONFIG_USER_ONLY) */
5961 }
5962 
5963 /* wrteei */
5964 static void gen_wrteei(DisasContext *ctx)
5965 {
5966 #if defined(CONFIG_USER_ONLY)
5967     GEN_PRIV(ctx);
5968 #else
5969     CHK_SV(ctx);
5970     if (ctx->opcode & 0x00008000) {
5971         tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5972         gen_ppc_maybe_interrupt(ctx);
5973         /* Stop translation to have a chance to raise an exception */
5974         ctx->base.is_jmp = DISAS_EXIT_UPDATE;
5975     } else {
5976         tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5977     }
5978 #endif /* defined(CONFIG_USER_ONLY) */
5979 }
5980 
5981 /* PowerPC 440 specific instructions */
5982 
5983 /* dlmzb */
5984 static void gen_dlmzb(DisasContext *ctx)
5985 {
5986     TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode));
5987     gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
5988                      cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
5989 }
5990 
5991 /* mbar replaces eieio on 440 */
5992 static void gen_mbar(DisasContext *ctx)
5993 {
5994     /* interpreted as no-op */
5995 }
5996 
5997 /* msync replaces sync on 440 */
5998 static void gen_msync_4xx(DisasContext *ctx)
5999 {
6000     /* Only e500 seems to treat reserved bits as invalid */
6001     if ((ctx->insns_flags2 & PPC2_BOOKE206) &&
6002         (ctx->opcode & 0x03FFF801)) {
6003         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6004     }
6005     /* otherwise interpreted as no-op */
6006 }
6007 
6008 /* icbt */
6009 static void gen_icbt_440(DisasContext *ctx)
6010 {
6011     /*
6012      * interpreted as no-op
6013      * XXX: specification say this is treated as a load by the MMU but
6014      *      does not generate any exception
6015      */
6016 }
6017 
6018 #if defined(TARGET_PPC64)
6019 static void gen_maddld(DisasContext *ctx)
6020 {
6021     TCGv_i64 t1 = tcg_temp_new_i64();
6022 
6023     tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6024     tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6025 }
6026 
6027 /* maddhd maddhdu */
6028 static void gen_maddhd_maddhdu(DisasContext *ctx)
6029 {
6030     TCGv_i64 lo = tcg_temp_new_i64();
6031     TCGv_i64 hi = tcg_temp_new_i64();
6032     TCGv_i64 t1 = tcg_temp_new_i64();
6033 
6034     if (Rc(ctx->opcode)) {
6035         tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6036                           cpu_gpr[rB(ctx->opcode)]);
6037         tcg_gen_movi_i64(t1, 0);
6038     } else {
6039         tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6040                           cpu_gpr[rB(ctx->opcode)]);
6041         tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6042     }
6043     tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6044                      cpu_gpr[rC(ctx->opcode)], t1);
6045 }
6046 #endif /* defined(TARGET_PPC64) */
6047 
6048 static void gen_tbegin(DisasContext *ctx)
6049 {
6050     if (unlikely(!ctx->tm_enabled)) {
6051         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6052         return;
6053     }
6054     gen_helper_tbegin(cpu_env);
6055 }
6056 
6057 #define GEN_TM_NOOP(name)                                      \
6058 static inline void gen_##name(DisasContext *ctx)               \
6059 {                                                              \
6060     if (unlikely(!ctx->tm_enabled)) {                          \
6061         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);   \
6062         return;                                                \
6063     }                                                          \
6064     /*                                                         \
6065      * Because tbegin always fails in QEMU, these user         \
6066      * space instructions all have a simple implementation:    \
6067      *                                                         \
6068      *     CR[0] = 0b0 || MSR[TS] || 0b0                       \
6069      *           = 0b0 || 0b00    || 0b0                       \
6070      */                                                        \
6071     tcg_gen_movi_i32(cpu_crf[0], 0);                           \
6072 }
6073 
6074 GEN_TM_NOOP(tend);
6075 GEN_TM_NOOP(tabort);
6076 GEN_TM_NOOP(tabortwc);
6077 GEN_TM_NOOP(tabortwci);
6078 GEN_TM_NOOP(tabortdc);
6079 GEN_TM_NOOP(tabortdci);
6080 GEN_TM_NOOP(tsr);
6081 
6082 static inline void gen_cp_abort(DisasContext *ctx)
6083 {
6084     /* Do Nothing */
6085 }
6086 
6087 #define GEN_CP_PASTE_NOOP(name)                           \
6088 static inline void gen_##name(DisasContext *ctx)          \
6089 {                                                         \
6090     /*                                                    \
6091      * Generate invalid exception until we have an        \
6092      * implementation of the copy paste facility          \
6093      */                                                   \
6094     gen_invalid(ctx);                                     \
6095 }
6096 
6097 GEN_CP_PASTE_NOOP(copy)
6098 GEN_CP_PASTE_NOOP(paste)
6099 
6100 static void gen_tcheck(DisasContext *ctx)
6101 {
6102     if (unlikely(!ctx->tm_enabled)) {
6103         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6104         return;
6105     }
6106     /*
6107      * Because tbegin always fails, the tcheck implementation is
6108      * simple:
6109      *
6110      * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6111      *         = 0b1 || 0b00 || 0b0
6112      */
6113     tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6114 }
6115 
6116 #if defined(CONFIG_USER_ONLY)
6117 #define GEN_TM_PRIV_NOOP(name)                                 \
6118 static inline void gen_##name(DisasContext *ctx)               \
6119 {                                                              \
6120     gen_priv_opc(ctx);                                         \
6121 }
6122 
6123 #else
6124 
6125 #define GEN_TM_PRIV_NOOP(name)                                 \
6126 static inline void gen_##name(DisasContext *ctx)               \
6127 {                                                              \
6128     CHK_SV(ctx);                                               \
6129     if (unlikely(!ctx->tm_enabled)) {                          \
6130         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);   \
6131         return;                                                \
6132     }                                                          \
6133     /*                                                         \
6134      * Because tbegin always fails, the implementation is      \
6135      * simple:                                                 \
6136      *                                                         \
6137      *   CR[0] = 0b0 || MSR[TS] || 0b0                         \
6138      *         = 0b0 || 0b00 | 0b0                             \
6139      */                                                        \
6140     tcg_gen_movi_i32(cpu_crf[0], 0);                           \
6141 }
6142 
6143 #endif
6144 
6145 GEN_TM_PRIV_NOOP(treclaim);
6146 GEN_TM_PRIV_NOOP(trechkpt);
6147 
6148 static inline void get_fpr(TCGv_i64 dst, int regno)
6149 {
6150     tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
6151 }
6152 
6153 static inline void set_fpr(int regno, TCGv_i64 src)
6154 {
6155     tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
6156     /*
6157      * Before PowerISA v3.1 the result of doubleword 1 of the VSR
6158      * corresponding to the target FPR was undefined. However,
6159      * most (if not all) real hardware were setting the result to 0.
6160      * Starting at ISA v3.1, the result for doubleword 1 is now defined
6161      * to be 0.
6162      */
6163     tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false));
6164 }
6165 
6166 static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
6167 {
6168     tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high));
6169 }
6170 
6171 static inline void set_avr64(int regno, TCGv_i64 src, bool high)
6172 {
6173     tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
6174 }
6175 
6176 /*
6177  * Helpers for decodetree used by !function for decoding arguments.
6178  */
6179 static int times_2(DisasContext *ctx, int x)
6180 {
6181     return x * 2;
6182 }
6183 
6184 static int times_4(DisasContext *ctx, int x)
6185 {
6186     return x * 4;
6187 }
6188 
6189 static int times_16(DisasContext *ctx, int x)
6190 {
6191     return x * 16;
6192 }
6193 
6194 static int64_t dw_compose_ea(DisasContext *ctx, int x)
6195 {
6196     return deposit64(0xfffffffffffffe00, 3, 6, x);
6197 }
6198 
6199 /*
6200  * Helpers for trans_* functions to check for specific insns flags.
6201  * Use token pasting to ensure that we use the proper flag with the
6202  * proper variable.
6203  */
6204 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \
6205     do {                                                \
6206         if (((CTX)->insns_flags & PPC_##NAME) == 0) {   \
6207             return false;                               \
6208         }                                               \
6209     } while (0)
6210 
6211 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
6212     do {                                                \
6213         if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
6214             return false;                               \
6215         }                                               \
6216     } while (0)
6217 
6218 /* Then special-case the check for 64-bit so that we elide code for ppc32. */
6219 #if TARGET_LONG_BITS == 32
6220 # define REQUIRE_64BIT(CTX)  return false
6221 #else
6222 # define REQUIRE_64BIT(CTX)  REQUIRE_INSNS_FLAGS(CTX, 64B)
6223 #endif
6224 
6225 #define REQUIRE_VECTOR(CTX)                             \
6226     do {                                                \
6227         if (unlikely(!(CTX)->altivec_enabled)) {        \
6228             gen_exception((CTX), POWERPC_EXCP_VPU);     \
6229             return true;                                \
6230         }                                               \
6231     } while (0)
6232 
6233 #define REQUIRE_VSX(CTX)                                \
6234     do {                                                \
6235         if (unlikely(!(CTX)->vsx_enabled)) {            \
6236             gen_exception((CTX), POWERPC_EXCP_VSXU);    \
6237             return true;                                \
6238         }                                               \
6239     } while (0)
6240 
6241 #define REQUIRE_FPU(ctx)                                \
6242     do {                                                \
6243         if (unlikely(!(ctx)->fpu_enabled)) {            \
6244             gen_exception((ctx), POWERPC_EXCP_FPU);     \
6245             return true;                                \
6246         }                                               \
6247     } while (0)
6248 
6249 #if !defined(CONFIG_USER_ONLY)
6250 #define REQUIRE_SV(CTX)             \
6251     do {                            \
6252         if (unlikely((CTX)->pr)) {  \
6253             gen_priv_opc(CTX);      \
6254             return true;            \
6255         }                           \
6256     } while (0)
6257 
6258 #define REQUIRE_HV(CTX)                             \
6259     do {                                            \
6260         if (unlikely((CTX)->pr || !(CTX)->hv)) {    \
6261             gen_priv_opc(CTX);                      \
6262             return true;                            \
6263         }                                           \
6264     } while (0)
6265 #else
6266 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
6267 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
6268 #endif
6269 
6270 /*
6271  * Helpers for implementing sets of trans_* functions.
6272  * Defer the implementation of NAME to FUNC, with optional extra arguments.
6273  */
6274 #define TRANS(NAME, FUNC, ...) \
6275     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6276     { return FUNC(ctx, a, __VA_ARGS__); }
6277 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \
6278     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6279     {                                                          \
6280         REQUIRE_INSNS_FLAGS(ctx, FLAGS);                       \
6281         return FUNC(ctx, a, __VA_ARGS__);                      \
6282     }
6283 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \
6284     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6285     {                                                          \
6286         REQUIRE_INSNS_FLAGS2(ctx, FLAGS2);                     \
6287         return FUNC(ctx, a, __VA_ARGS__);                      \
6288     }
6289 
6290 #define TRANS64(NAME, FUNC, ...) \
6291     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6292     { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
6293 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \
6294     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6295     {                                                          \
6296         REQUIRE_64BIT(ctx);                                    \
6297         REQUIRE_INSNS_FLAGS2(ctx, FLAGS2);                     \
6298         return FUNC(ctx, a, __VA_ARGS__);                      \
6299     }
6300 
6301 /* TODO: More TRANS* helpers for extra insn_flags checks. */
6302 
6303 
6304 #include "decode-insn32.c.inc"
6305 #include "decode-insn64.c.inc"
6306 #include "power8-pmu-regs.c.inc"
6307 
6308 /*
6309  * Incorporate CIA into the constant when R=1.
6310  * Validate that when R=1, RA=0.
6311  */
6312 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
6313 {
6314     d->rt = a->rt;
6315     d->ra = a->ra;
6316     d->si = a->si;
6317     if (a->r) {
6318         if (unlikely(a->ra != 0)) {
6319             gen_invalid(ctx);
6320             return false;
6321         }
6322         d->si += ctx->cia;
6323     }
6324     return true;
6325 }
6326 
6327 #include "translate/fixedpoint-impl.c.inc"
6328 
6329 #include "translate/fp-impl.c.inc"
6330 
6331 #include "translate/vmx-impl.c.inc"
6332 
6333 #include "translate/vsx-impl.c.inc"
6334 
6335 #include "translate/dfp-impl.c.inc"
6336 
6337 #include "translate/spe-impl.c.inc"
6338 
6339 #include "translate/branch-impl.c.inc"
6340 
6341 #include "translate/processor-ctrl-impl.c.inc"
6342 
6343 #include "translate/storage-ctrl-impl.c.inc"
6344 
6345 /* Handles lfdp */
6346 static void gen_dform39(DisasContext *ctx)
6347 {
6348     if ((ctx->opcode & 0x3) == 0) {
6349         if (ctx->insns_flags2 & PPC2_ISA205) {
6350             return gen_lfdp(ctx);
6351         }
6352     }
6353     return gen_invalid(ctx);
6354 }
6355 
6356 /* Handles stfdp */
6357 static void gen_dform3D(DisasContext *ctx)
6358 {
6359     if ((ctx->opcode & 3) == 0) { /* DS-FORM */
6360         /* stfdp */
6361         if (ctx->insns_flags2 & PPC2_ISA205) {
6362             return gen_stfdp(ctx);
6363         }
6364     }
6365     return gen_invalid(ctx);
6366 }
6367 
6368 #if defined(TARGET_PPC64)
6369 /* brd */
6370 static void gen_brd(DisasContext *ctx)
6371 {
6372     tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6373 }
6374 
6375 /* brw */
6376 static void gen_brw(DisasContext *ctx)
6377 {
6378     tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6379     tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
6380 
6381 }
6382 
6383 /* brh */
6384 static void gen_brh(DisasContext *ctx)
6385 {
6386     TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull);
6387     TCGv_i64 t1 = tcg_temp_new_i64();
6388     TCGv_i64 t2 = tcg_temp_new_i64();
6389 
6390     tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
6391     tcg_gen_and_i64(t2, t1, mask);
6392     tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask);
6393     tcg_gen_shli_i64(t1, t1, 8);
6394     tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
6395 }
6396 #endif
6397 
6398 static opcode_t opcodes[] = {
6399 #if defined(TARGET_PPC64)
6400 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
6401 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
6402 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
6403 #endif
6404 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6405 #if defined(TARGET_PPC64)
6406 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6407 #endif
6408 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6409 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6410 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6411 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6412 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6413 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6414 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6415 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6416 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6417 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6418 #if defined(TARGET_PPC64)
6419 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6420 #endif
6421 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6422 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6423 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6424 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6425 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6426 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6427 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6428 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6429 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6430 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6431 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6432 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6433 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6434 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6435 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6436 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6437 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6438 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6439 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6440 #if defined(TARGET_PPC64)
6441 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6442 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6443 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6444 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6445 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6446 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6447 #endif
6448 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6449 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6450 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6451 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6452 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6453 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6454 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6455 #if defined(TARGET_PPC64)
6456 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6457 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6458 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6459 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6460 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6461 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6462                PPC_NONE, PPC2_ISA300),
6463 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6464                PPC_NONE, PPC2_ISA300),
6465 #endif
6466 /* handles lfdp, lxsd, lxssp */
6467 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6468 /* handles stfdp, stxsd, stxssp */
6469 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6470 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6471 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6472 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6473 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6474 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6475 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6476 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
6477 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6478 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6479 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6480 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6481 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6482 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6483 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6484 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6485 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6486 #if defined(TARGET_PPC64)
6487 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6488 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6489 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6490 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6491 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6492 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6493 #endif
6494 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6495 /* ISA v3.0 changed the extended opcode from 62 to 30 */
6496 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT),
6497 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300),
6498 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6499 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6500 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6501 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6502 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6503 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6504 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6505 #if defined(TARGET_PPC64)
6506 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6507 #if !defined(CONFIG_USER_ONLY)
6508 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
6509 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
6510 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
6511 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300),
6512 #endif
6513 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6514 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6515 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6516 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6517 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6518 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6519 #endif
6520 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
6521 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
6522 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
6523 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6524 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6525 #if defined(TARGET_PPC64)
6526 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6527 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6528 #endif
6529 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6530 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6531 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6532 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6533 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6534 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6535 #if defined(TARGET_PPC64)
6536 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6537 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6538 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6539 #endif
6540 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6541 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6542 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6543 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
6544 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6545 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6546 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
6547 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6548 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
6549 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6550 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
6551 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6552 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6553 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6554 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
6555 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6556 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
6557 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6558 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6559 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
6560 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6561 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6562 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6563 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6564 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6565 #if defined(TARGET_PPC64)
6566 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6567 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6568              PPC_SEGMENT_64B),
6569 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6570 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6571              PPC_SEGMENT_64B),
6572 #endif
6573 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6574 /*
6575  * XXX Those instructions will need to be handled differently for
6576  * different ISA versions
6577  */
6578 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6579 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6580 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6581 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6582 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6583 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6584 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6585 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6586 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6587 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6588 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6589 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6590 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6591 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6592 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6593 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6594 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6595 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6596 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6597 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6598 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6599 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6600 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6601 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6602 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6603 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6604 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6605                PPC_NONE, PPC2_BOOKE206),
6606 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6607                PPC_NONE, PPC2_BOOKE206),
6608 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6609                PPC_NONE, PPC2_BOOKE206),
6610 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6611                PPC_NONE, PPC2_BOOKE206),
6612 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6613                PPC_NONE, PPC2_BOOKE206),
6614 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6615 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6616 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6617 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6618               PPC_BOOKE, PPC2_BOOKE206),
6619 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE),
6620 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6621                PPC_BOOKE, PPC2_BOOKE206),
6622 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
6623              PPC_440_SPEC),
6624 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6625 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6626 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6627 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6628 #if defined(TARGET_PPC64)
6629 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6630               PPC2_ISA300),
6631 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6632 #endif
6633 
6634 #undef GEN_INT_ARITH_ADD
6635 #undef GEN_INT_ARITH_ADD_CONST
6636 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
6637 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6638 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \
6639                                 add_ca, compute_ca, compute_ov)               \
6640 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6641 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6642 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6643 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6644 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6645 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6646 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6647 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6648 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6649 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
6650 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6651 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6652 
6653 #undef GEN_INT_ARITH_DIVW
6654 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
6655 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6656 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6657 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6658 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6659 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6660 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6661 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6662 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6663 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6664 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6665 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6666 
6667 #if defined(TARGET_PPC64)
6668 #undef GEN_INT_ARITH_DIVD
6669 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
6670 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6671 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6672 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6673 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6674 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6675 
6676 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6677 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6678 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6679 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6680 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6681 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6682 
6683 #undef GEN_INT_ARITH_MUL_HELPER
6684 #define GEN_INT_ARITH_MUL_HELPER(name, opc3)                                  \
6685 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6686 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6687 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6688 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6689 #endif
6690 
6691 #undef GEN_INT_ARITH_SUBF
6692 #undef GEN_INT_ARITH_SUBF_CONST
6693 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
6694 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6695 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
6696                                 add_ca, compute_ca, compute_ov)               \
6697 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6698 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6699 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6700 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6701 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6702 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6703 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6704 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6705 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6706 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6707 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6708 
6709 #undef GEN_LOGICAL1
6710 #undef GEN_LOGICAL2
6711 #define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
6712 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6713 #define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
6714 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6715 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6716 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6717 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6718 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6719 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6720 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6721 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6722 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6723 #if defined(TARGET_PPC64)
6724 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6725 #endif
6726 
6727 #if defined(TARGET_PPC64)
6728 #undef GEN_PPC64_R2
6729 #undef GEN_PPC64_R4
6730 #define GEN_PPC64_R2(name, opc1, opc2)                                        \
6731 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6732 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
6733              PPC_64B)
6734 #define GEN_PPC64_R4(name, opc1, opc2)                                        \
6735 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6736 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
6737              PPC_64B),                                                        \
6738 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
6739              PPC_64B),                                                        \
6740 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
6741              PPC_64B)
6742 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6743 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6744 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6745 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6746 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6747 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6748 #endif
6749 
6750 #undef GEN_LDX_E
6751 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk)                   \
6752 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6753 
6754 #if defined(TARGET_PPC64)
6755 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6756 
6757 /* HV/P7 and later only */
6758 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6759 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6760 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6761 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6762 #endif
6763 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6764 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6765 
6766 /* External PID based load */
6767 #undef GEN_LDEPX
6768 #define GEN_LDEPX(name, ldop, opc2, opc3)                                     \
6769 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3,                                    \
6770               0x00000001, PPC_NONE, PPC2_BOOKE206),
6771 
6772 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
6773 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
6774 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
6775 #if defined(TARGET_PPC64)
6776 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)
6777 #endif
6778 
6779 #undef GEN_STX_E
6780 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk)                   \
6781 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
6782 
6783 #if defined(TARGET_PPC64)
6784 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6785 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6786 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6787 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6788 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6789 #endif
6790 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6791 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6792 
6793 #undef GEN_STEPX
6794 #define GEN_STEPX(name, ldop, opc2, opc3)                                     \
6795 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3,                                    \
6796               0x00000001, PPC_NONE, PPC2_BOOKE206),
6797 
6798 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
6799 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
6800 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
6801 #if defined(TARGET_PPC64)
6802 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04)
6803 #endif
6804 
6805 #undef GEN_CRLOGIC
6806 #define GEN_CRLOGIC(name, tcg_op, opc)                                        \
6807 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6808 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6809 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6810 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6811 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6812 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6813 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6814 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6815 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6816 
6817 #undef GEN_MAC_HANDLER
6818 #define GEN_MAC_HANDLER(name, opc2, opc3)                                     \
6819 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6820 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6821 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6822 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6823 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6824 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6825 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6826 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6827 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6828 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6829 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6830 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6831 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6832 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6833 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6834 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6835 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6836 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6837 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6838 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6839 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6840 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6841 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6842 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6843 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6844 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6845 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6846 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6847 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6848 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6849 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6850 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6851 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6852 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6853 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6854 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6855 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6856 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6857 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6858 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6859 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6860 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6861 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6862 
6863 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6864                PPC_NONE, PPC2_TM),
6865 GEN_HANDLER2_E(tend,   "tend",   0x1F, 0x0E, 0x15, 0x01FFF800, \
6866                PPC_NONE, PPC2_TM),
6867 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6868                PPC_NONE, PPC2_TM),
6869 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6870                PPC_NONE, PPC2_TM),
6871 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6872                PPC_NONE, PPC2_TM),
6873 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6874                PPC_NONE, PPC2_TM),
6875 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6876                PPC_NONE, PPC2_TM),
6877 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6878                PPC_NONE, PPC2_TM),
6879 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6880                PPC_NONE, PPC2_TM),
6881 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6882                PPC_NONE, PPC2_TM),
6883 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6884                PPC_NONE, PPC2_TM),
6885 
6886 #include "translate/fp-ops.c.inc"
6887 
6888 #include "translate/vmx-ops.c.inc"
6889 
6890 #include "translate/vsx-ops.c.inc"
6891 
6892 #include "translate/spe-ops.c.inc"
6893 };
6894 
6895 /*****************************************************************************/
6896 /* Opcode types */
6897 enum {
6898     PPC_DIRECT   = 0, /* Opcode routine        */
6899     PPC_INDIRECT = 1, /* Indirect opcode table */
6900 };
6901 
6902 #define PPC_OPCODE_MASK 0x3
6903 
6904 static inline int is_indirect_opcode(void *handler)
6905 {
6906     return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
6907 }
6908 
6909 static inline opc_handler_t **ind_table(void *handler)
6910 {
6911     return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
6912 }
6913 
6914 /* Instruction table creation */
6915 /* Opcodes tables creation */
6916 static void fill_new_table(opc_handler_t **table, int len)
6917 {
6918     int i;
6919 
6920     for (i = 0; i < len; i++) {
6921         table[i] = &invalid_handler;
6922     }
6923 }
6924 
6925 static int create_new_table(opc_handler_t **table, unsigned char idx)
6926 {
6927     opc_handler_t **tmp;
6928 
6929     tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
6930     fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
6931     table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
6932 
6933     return 0;
6934 }
6935 
6936 static int insert_in_table(opc_handler_t **table, unsigned char idx,
6937                             opc_handler_t *handler)
6938 {
6939     if (table[idx] != &invalid_handler) {
6940         return -1;
6941     }
6942     table[idx] = handler;
6943 
6944     return 0;
6945 }
6946 
6947 static int register_direct_insn(opc_handler_t **ppc_opcodes,
6948                                 unsigned char idx, opc_handler_t *handler)
6949 {
6950     if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
6951         printf("*** ERROR: opcode %02x already assigned in main "
6952                "opcode table\n", idx);
6953         return -1;
6954     }
6955 
6956     return 0;
6957 }
6958 
6959 static int register_ind_in_table(opc_handler_t **table,
6960                                  unsigned char idx1, unsigned char idx2,
6961                                  opc_handler_t *handler)
6962 {
6963     if (table[idx1] == &invalid_handler) {
6964         if (create_new_table(table, idx1) < 0) {
6965             printf("*** ERROR: unable to create indirect table "
6966                    "idx=%02x\n", idx1);
6967             return -1;
6968         }
6969     } else {
6970         if (!is_indirect_opcode(table[idx1])) {
6971             printf("*** ERROR: idx %02x already assigned to a direct "
6972                    "opcode\n", idx1);
6973             return -1;
6974         }
6975     }
6976     if (handler != NULL &&
6977         insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
6978         printf("*** ERROR: opcode %02x already assigned in "
6979                "opcode table %02x\n", idx2, idx1);
6980         return -1;
6981     }
6982 
6983     return 0;
6984 }
6985 
6986 static int register_ind_insn(opc_handler_t **ppc_opcodes,
6987                              unsigned char idx1, unsigned char idx2,
6988                              opc_handler_t *handler)
6989 {
6990     return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
6991 }
6992 
6993 static int register_dblind_insn(opc_handler_t **ppc_opcodes,
6994                                 unsigned char idx1, unsigned char idx2,
6995                                 unsigned char idx3, opc_handler_t *handler)
6996 {
6997     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
6998         printf("*** ERROR: unable to join indirect table idx "
6999                "[%02x-%02x]\n", idx1, idx2);
7000         return -1;
7001     }
7002     if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7003                               handler) < 0) {
7004         printf("*** ERROR: unable to insert opcode "
7005                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7006         return -1;
7007     }
7008 
7009     return 0;
7010 }
7011 
7012 static int register_trplind_insn(opc_handler_t **ppc_opcodes,
7013                                  unsigned char idx1, unsigned char idx2,
7014                                  unsigned char idx3, unsigned char idx4,
7015                                  opc_handler_t *handler)
7016 {
7017     opc_handler_t **table;
7018 
7019     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7020         printf("*** ERROR: unable to join indirect table idx "
7021                "[%02x-%02x]\n", idx1, idx2);
7022         return -1;
7023     }
7024     table = ind_table(ppc_opcodes[idx1]);
7025     if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
7026         printf("*** ERROR: unable to join 2nd-level indirect table idx "
7027                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7028         return -1;
7029     }
7030     table = ind_table(table[idx2]);
7031     if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
7032         printf("*** ERROR: unable to insert opcode "
7033                "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
7034         return -1;
7035     }
7036     return 0;
7037 }
7038 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
7039 {
7040     if (insn->opc2 != 0xFF) {
7041         if (insn->opc3 != 0xFF) {
7042             if (insn->opc4 != 0xFF) {
7043                 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7044                                           insn->opc3, insn->opc4,
7045                                           &insn->handler) < 0) {
7046                     return -1;
7047                 }
7048             } else {
7049                 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7050                                          insn->opc3, &insn->handler) < 0) {
7051                     return -1;
7052                 }
7053             }
7054         } else {
7055             if (register_ind_insn(ppc_opcodes, insn->opc1,
7056                                   insn->opc2, &insn->handler) < 0) {
7057                 return -1;
7058             }
7059         }
7060     } else {
7061         if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
7062             return -1;
7063         }
7064     }
7065 
7066     return 0;
7067 }
7068 
7069 static int test_opcode_table(opc_handler_t **table, int len)
7070 {
7071     int i, count, tmp;
7072 
7073     for (i = 0, count = 0; i < len; i++) {
7074         /* Consistency fixup */
7075         if (table[i] == NULL) {
7076             table[i] = &invalid_handler;
7077         }
7078         if (table[i] != &invalid_handler) {
7079             if (is_indirect_opcode(table[i])) {
7080                 tmp = test_opcode_table(ind_table(table[i]),
7081                     PPC_CPU_INDIRECT_OPCODES_LEN);
7082                 if (tmp == 0) {
7083                     free(table[i]);
7084                     table[i] = &invalid_handler;
7085                 } else {
7086                     count++;
7087                 }
7088             } else {
7089                 count++;
7090             }
7091         }
7092     }
7093 
7094     return count;
7095 }
7096 
7097 static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
7098 {
7099     if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
7100         printf("*** WARNING: no opcode defined !\n");
7101     }
7102 }
7103 
7104 /*****************************************************************************/
7105 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
7106 {
7107     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7108     opcode_t *opc;
7109 
7110     fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN);
7111     for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
7112         if (((opc->handler.type & pcc->insns_flags) != 0) ||
7113             ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
7114             if (register_insn(cpu->opcodes, opc) < 0) {
7115                 error_setg(errp, "ERROR initializing PowerPC instruction "
7116                            "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
7117                            opc->opc3);
7118                 return;
7119             }
7120         }
7121     }
7122     fix_opcode_tables(cpu->opcodes);
7123     fflush(stdout);
7124     fflush(stderr);
7125 }
7126 
7127 void destroy_ppc_opcodes(PowerPCCPU *cpu)
7128 {
7129     opc_handler_t **table, **table_2;
7130     int i, j, k;
7131 
7132     for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
7133         if (cpu->opcodes[i] == &invalid_handler) {
7134             continue;
7135         }
7136         if (is_indirect_opcode(cpu->opcodes[i])) {
7137             table = ind_table(cpu->opcodes[i]);
7138             for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
7139                 if (table[j] == &invalid_handler) {
7140                     continue;
7141                 }
7142                 if (is_indirect_opcode(table[j])) {
7143                     table_2 = ind_table(table[j]);
7144                     for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
7145                         if (table_2[k] != &invalid_handler &&
7146                             is_indirect_opcode(table_2[k])) {
7147                             g_free((opc_handler_t *)((uintptr_t)table_2[k] &
7148                                                      ~PPC_INDIRECT));
7149                         }
7150                     }
7151                     g_free((opc_handler_t *)((uintptr_t)table[j] &
7152                                              ~PPC_INDIRECT));
7153                 }
7154             }
7155             g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
7156                 ~PPC_INDIRECT));
7157         }
7158     }
7159 }
7160 
7161 int ppc_fixup_cpu(PowerPCCPU *cpu)
7162 {
7163     CPUPPCState *env = &cpu->env;
7164 
7165     /*
7166      * TCG doesn't (yet) emulate some groups of instructions that are
7167      * implemented on some otherwise supported CPUs (e.g. VSX and
7168      * decimal floating point instructions on POWER7).  We remove
7169      * unsupported instruction groups from the cpu state's instruction
7170      * masks and hope the guest can cope.  For at least the pseries
7171      * machine, the unavailability of these instructions can be
7172      * advertised to the guest via the device tree.
7173      */
7174     if ((env->insns_flags & ~PPC_TCG_INSNS)
7175         || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
7176         warn_report("Disabling some instructions which are not "
7177                     "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
7178                     env->insns_flags & ~PPC_TCG_INSNS,
7179                     env->insns_flags2 & ~PPC_TCG_INSNS2);
7180     }
7181     env->insns_flags &= PPC_TCG_INSNS;
7182     env->insns_flags2 &= PPC_TCG_INSNS2;
7183     return 0;
7184 }
7185 
7186 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn)
7187 {
7188     opc_handler_t **table, *handler;
7189     uint32_t inval;
7190 
7191     ctx->opcode = insn;
7192 
7193     LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7194               insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn),
7195               ctx->le_mode ? "little" : "big");
7196 
7197     table = cpu->opcodes;
7198     handler = table[opc1(insn)];
7199     if (is_indirect_opcode(handler)) {
7200         table = ind_table(handler);
7201         handler = table[opc2(insn)];
7202         if (is_indirect_opcode(handler)) {
7203             table = ind_table(handler);
7204             handler = table[opc3(insn)];
7205             if (is_indirect_opcode(handler)) {
7206                 table = ind_table(handler);
7207                 handler = table[opc4(insn)];
7208             }
7209         }
7210     }
7211 
7212     /* Is opcode *REALLY* valid ? */
7213     if (unlikely(handler->handler == &gen_invalid)) {
7214         qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7215                       "%02x - %02x - %02x - %02x (%08x) "
7216                       TARGET_FMT_lx "\n",
7217                       opc1(insn), opc2(insn), opc3(insn), opc4(insn),
7218                       insn, ctx->cia);
7219         return false;
7220     }
7221 
7222     if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
7223                  && Rc(insn))) {
7224         inval = handler->inval2;
7225     } else {
7226         inval = handler->inval1;
7227     }
7228 
7229     if (unlikely((insn & inval) != 0)) {
7230         qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7231                       "%02x - %02x - %02x - %02x (%08x) "
7232                       TARGET_FMT_lx "\n", insn & inval,
7233                       opc1(insn), opc2(insn), opc3(insn), opc4(insn),
7234                       insn, ctx->cia);
7235         return false;
7236     }
7237 
7238     handler->handler(ctx);
7239     return true;
7240 }
7241 
7242 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7243 {
7244     DisasContext *ctx = container_of(dcbase, DisasContext, base);
7245     CPUPPCState *env = cs->env_ptr;
7246     uint32_t hflags = ctx->base.tb->flags;
7247 
7248     ctx->spr_cb = env->spr_cb;
7249     ctx->pr = (hflags >> HFLAGS_PR) & 1;
7250     ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
7251     ctx->dr = (hflags >> HFLAGS_DR) & 1;
7252     ctx->hv = (hflags >> HFLAGS_HV) & 1;
7253     ctx->insns_flags = env->insns_flags;
7254     ctx->insns_flags2 = env->insns_flags2;
7255     ctx->access_type = -1;
7256     ctx->need_access_type = !mmu_is_64bit(env->mmu_model);
7257     ctx->le_mode = (hflags >> HFLAGS_LE) & 1;
7258     ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
7259     ctx->flags = env->flags;
7260 #if defined(TARGET_PPC64)
7261     ctx->sf_mode = (hflags >> HFLAGS_64) & 1;
7262     ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7263 #endif
7264     ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
7265         || env->mmu_model & POWERPC_MMU_64;
7266 
7267     ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1;
7268     ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1;
7269     ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
7270     ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
7271     ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
7272     ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
7273     ctx->hr = (hflags >> HFLAGS_HR) & 1;
7274     ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1;
7275     ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1;
7276     ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1;
7277     ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1;
7278     ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1;
7279 
7280     ctx->singlestep_enabled = 0;
7281     if ((hflags >> HFLAGS_SE) & 1) {
7282         ctx->singlestep_enabled |= CPU_SINGLE_STEP;
7283         ctx->base.max_insns = 1;
7284     }
7285     if ((hflags >> HFLAGS_BE) & 1) {
7286         ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7287     }
7288 }
7289 
7290 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
7291 {
7292 }
7293 
7294 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
7295 {
7296     tcg_gen_insn_start(dcbase->pc_next);
7297 }
7298 
7299 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
7300 {
7301     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
7302     return opc1(insn) == 1;
7303 }
7304 
7305 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
7306 {
7307     DisasContext *ctx = container_of(dcbase, DisasContext, base);
7308     PowerPCCPU *cpu = POWERPC_CPU(cs);
7309     CPUPPCState *env = cs->env_ptr;
7310     target_ulong pc;
7311     uint32_t insn;
7312     bool ok;
7313 
7314     LOG_DISAS("----------------\n");
7315     LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7316               ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
7317 
7318     ctx->cia = pc = ctx->base.pc_next;
7319     insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
7320     ctx->base.pc_next = pc += 4;
7321 
7322     if (!is_prefix_insn(ctx, insn)) {
7323         ok = (decode_insn32(ctx, insn) ||
7324               decode_legacy(cpu, ctx, insn));
7325     } else if ((pc & 63) == 0) {
7326         /*
7327          * Power v3.1, section 1.9 Exceptions:
7328          * attempt to execute a prefixed instruction that crosses a
7329          * 64-byte address boundary (system alignment error).
7330          */
7331         gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
7332         ok = true;
7333     } else {
7334         uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
7335                                              need_byteswap(ctx));
7336         ctx->base.pc_next = pc += 4;
7337         ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
7338     }
7339     if (!ok) {
7340         gen_invalid(ctx);
7341     }
7342 
7343     /* End the TB when crossing a page boundary. */
7344     if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) {
7345         ctx->base.is_jmp = DISAS_TOO_MANY;
7346     }
7347 }
7348 
7349 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
7350 {
7351     DisasContext *ctx = container_of(dcbase, DisasContext, base);
7352     DisasJumpType is_jmp = ctx->base.is_jmp;
7353     target_ulong nip = ctx->base.pc_next;
7354 
7355     if (is_jmp == DISAS_NORETURN) {
7356         /* We have already exited the TB. */
7357         return;
7358     }
7359 
7360     /* Honor single stepping. */
7361     if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)
7362         && (nip <= 0x100 || nip > 0xf00)) {
7363         switch (is_jmp) {
7364         case DISAS_TOO_MANY:
7365         case DISAS_EXIT_UPDATE:
7366         case DISAS_CHAIN_UPDATE:
7367             gen_update_nip(ctx, nip);
7368             break;
7369         case DISAS_EXIT:
7370         case DISAS_CHAIN:
7371             break;
7372         default:
7373             g_assert_not_reached();
7374         }
7375 
7376         gen_debug_exception(ctx);
7377         return;
7378     }
7379 
7380     switch (is_jmp) {
7381     case DISAS_TOO_MANY:
7382         if (use_goto_tb(ctx, nip)) {
7383             pmu_count_insns(ctx);
7384             tcg_gen_goto_tb(0);
7385             gen_update_nip(ctx, nip);
7386             tcg_gen_exit_tb(ctx->base.tb, 0);
7387             break;
7388         }
7389         /* fall through */
7390     case DISAS_CHAIN_UPDATE:
7391         gen_update_nip(ctx, nip);
7392         /* fall through */
7393     case DISAS_CHAIN:
7394         /*
7395          * tcg_gen_lookup_and_goto_ptr will exit the TB if
7396          * CF_NO_GOTO_PTR is set. Count insns now.
7397          */
7398         if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
7399             pmu_count_insns(ctx);
7400         }
7401 
7402         tcg_gen_lookup_and_goto_ptr();
7403         break;
7404 
7405     case DISAS_EXIT_UPDATE:
7406         gen_update_nip(ctx, nip);
7407         /* fall through */
7408     case DISAS_EXIT:
7409         pmu_count_insns(ctx);
7410         tcg_gen_exit_tb(NULL, 0);
7411         break;
7412 
7413     default:
7414         g_assert_not_reached();
7415     }
7416 }
7417 
7418 static void ppc_tr_disas_log(const DisasContextBase *dcbase,
7419                              CPUState *cs, FILE *logfile)
7420 {
7421     fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
7422     target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size);
7423 }
7424 
7425 static const TranslatorOps ppc_tr_ops = {
7426     .init_disas_context = ppc_tr_init_disas_context,
7427     .tb_start           = ppc_tr_tb_start,
7428     .insn_start         = ppc_tr_insn_start,
7429     .translate_insn     = ppc_tr_translate_insn,
7430     .tb_stop            = ppc_tr_tb_stop,
7431     .disas_log          = ppc_tr_disas_log,
7432 };
7433 
7434 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
7435                            target_ulong pc, void *host_pc)
7436 {
7437     DisasContext ctx;
7438 
7439     translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base);
7440 }
7441