xref: /openbmc/qemu/target/ppc/translate.c (revision beb1a917)
1 /*
2  *  PowerPC emulation for qemu: main translation routines.
3  *
4  *  Copyright (c) 2003-2007 Jocelyn Mayer
5  *  Copyright (C) 2011 Freescale Semiconductor, Inc.
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2.1 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg/tcg-op.h"
27 #include "tcg/tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "qemu/main-loop.h"
30 #include "exec/cpu_ldst.h"
31 
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34 
35 #include "exec/translator.h"
36 #include "exec/log.h"
37 #include "qemu/atomic128.h"
38 #include "spr_common.h"
39 #include "power8-pmu.h"
40 
41 #include "qemu/qemu-print.h"
42 #include "qapi/error.h"
43 
44 #define HELPER_H "helper.h"
45 #include "exec/helper-info.c.inc"
46 #undef  HELPER_H
47 
48 #define CPU_SINGLE_STEP 0x1
49 #define CPU_BRANCH_STEP 0x2
50 
51 /* Include definitions for instructions classes and implementations flags */
52 /* #define PPC_DEBUG_DISAS */
53 
54 #ifdef PPC_DEBUG_DISAS
55 #  define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
56 #else
57 #  define LOG_DISAS(...) do { } while (0)
58 #endif
59 /*****************************************************************************/
60 /* Code translation helpers                                                  */
61 
62 /* global register indexes */
63 static char cpu_reg_names[10 * 3 + 22 * 4   /* GPR */
64                           + 10 * 4 + 22 * 5 /* SPE GPRh */
65                           + 8 * 5           /* CRF */];
66 static TCGv cpu_gpr[32];
67 static TCGv cpu_gprh[32];
68 static TCGv_i32 cpu_crf[8];
69 static TCGv cpu_nip;
70 static TCGv cpu_msr;
71 static TCGv cpu_ctr;
72 static TCGv cpu_lr;
73 #if defined(TARGET_PPC64)
74 static TCGv cpu_cfar;
75 #endif
76 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
77 static TCGv cpu_reserve;
78 static TCGv cpu_reserve_length;
79 static TCGv cpu_reserve_val;
80 static TCGv cpu_reserve_val2;
81 static TCGv cpu_fpscr;
82 static TCGv_i32 cpu_access_type;
83 
84 void ppc_translate_init(void)
85 {
86     int i;
87     char *p;
88     size_t cpu_reg_names_size;
89 
90     p = cpu_reg_names;
91     cpu_reg_names_size = sizeof(cpu_reg_names);
92 
93     for (i = 0; i < 8; i++) {
94         snprintf(p, cpu_reg_names_size, "crf%d", i);
95         cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
96                                             offsetof(CPUPPCState, crf[i]), p);
97         p += 5;
98         cpu_reg_names_size -= 5;
99     }
100 
101     for (i = 0; i < 32; i++) {
102         snprintf(p, cpu_reg_names_size, "r%d", i);
103         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
104                                         offsetof(CPUPPCState, gpr[i]), p);
105         p += (i < 10) ? 3 : 4;
106         cpu_reg_names_size -= (i < 10) ? 3 : 4;
107         snprintf(p, cpu_reg_names_size, "r%dH", i);
108         cpu_gprh[i] = tcg_global_mem_new(cpu_env,
109                                          offsetof(CPUPPCState, gprh[i]), p);
110         p += (i < 10) ? 4 : 5;
111         cpu_reg_names_size -= (i < 10) ? 4 : 5;
112     }
113 
114     cpu_nip = tcg_global_mem_new(cpu_env,
115                                  offsetof(CPUPPCState, nip), "nip");
116 
117     cpu_msr = tcg_global_mem_new(cpu_env,
118                                  offsetof(CPUPPCState, msr), "msr");
119 
120     cpu_ctr = tcg_global_mem_new(cpu_env,
121                                  offsetof(CPUPPCState, ctr), "ctr");
122 
123     cpu_lr = tcg_global_mem_new(cpu_env,
124                                 offsetof(CPUPPCState, lr), "lr");
125 
126 #if defined(TARGET_PPC64)
127     cpu_cfar = tcg_global_mem_new(cpu_env,
128                                   offsetof(CPUPPCState, cfar), "cfar");
129 #endif
130 
131     cpu_xer = tcg_global_mem_new(cpu_env,
132                                  offsetof(CPUPPCState, xer), "xer");
133     cpu_so = tcg_global_mem_new(cpu_env,
134                                 offsetof(CPUPPCState, so), "SO");
135     cpu_ov = tcg_global_mem_new(cpu_env,
136                                 offsetof(CPUPPCState, ov), "OV");
137     cpu_ca = tcg_global_mem_new(cpu_env,
138                                 offsetof(CPUPPCState, ca), "CA");
139     cpu_ov32 = tcg_global_mem_new(cpu_env,
140                                   offsetof(CPUPPCState, ov32), "OV32");
141     cpu_ca32 = tcg_global_mem_new(cpu_env,
142                                   offsetof(CPUPPCState, ca32), "CA32");
143 
144     cpu_reserve = tcg_global_mem_new(cpu_env,
145                                      offsetof(CPUPPCState, reserve_addr),
146                                      "reserve_addr");
147     cpu_reserve_length = tcg_global_mem_new(cpu_env,
148                                             offsetof(CPUPPCState,
149                                                      reserve_length),
150                                             "reserve_length");
151     cpu_reserve_val = tcg_global_mem_new(cpu_env,
152                                          offsetof(CPUPPCState, reserve_val),
153                                          "reserve_val");
154     cpu_reserve_val2 = tcg_global_mem_new(cpu_env,
155                                           offsetof(CPUPPCState, reserve_val2),
156                                           "reserve_val2");
157 
158     cpu_fpscr = tcg_global_mem_new(cpu_env,
159                                    offsetof(CPUPPCState, fpscr), "fpscr");
160 
161     cpu_access_type = tcg_global_mem_new_i32(cpu_env,
162                                              offsetof(CPUPPCState, access_type),
163                                              "access_type");
164 }
165 
166 /* internal defines */
167 struct DisasContext {
168     DisasContextBase base;
169     target_ulong cia;  /* current instruction address */
170     uint32_t opcode;
171     /* Routine used to access memory */
172     bool pr, hv, dr, le_mode;
173     bool lazy_tlb_flush;
174     bool need_access_type;
175     int mem_idx;
176     int access_type;
177     /* Translation flags */
178     MemOp default_tcg_memop_mask;
179 #if defined(TARGET_PPC64)
180     bool sf_mode;
181     bool has_cfar;
182 #endif
183     bool fpu_enabled;
184     bool altivec_enabled;
185     bool vsx_enabled;
186     bool spe_enabled;
187     bool tm_enabled;
188     bool gtse;
189     bool hr;
190     bool mmcr0_pmcc0;
191     bool mmcr0_pmcc1;
192     bool mmcr0_pmcjce;
193     bool pmc_other;
194     bool pmu_insn_cnt;
195     ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
196     int singlestep_enabled;
197     uint32_t flags;
198     uint64_t insns_flags;
199     uint64_t insns_flags2;
200 };
201 
202 #define DISAS_EXIT         DISAS_TARGET_0  /* exit to main loop, pc updated */
203 #define DISAS_EXIT_UPDATE  DISAS_TARGET_1  /* exit to main loop, pc stale */
204 #define DISAS_CHAIN        DISAS_TARGET_2  /* lookup next tb, pc updated */
205 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3  /* lookup next tb, pc stale */
206 
207 /* Return true iff byteswap is needed in a scalar memop */
208 static inline bool need_byteswap(const DisasContext *ctx)
209 {
210 #if TARGET_BIG_ENDIAN
211      return ctx->le_mode;
212 #else
213      return !ctx->le_mode;
214 #endif
215 }
216 
217 /* True when active word size < size of target_long.  */
218 #ifdef TARGET_PPC64
219 # define NARROW_MODE(C)  (!(C)->sf_mode)
220 #else
221 # define NARROW_MODE(C)  0
222 #endif
223 
224 struct opc_handler_t {
225     /* invalid bits for instruction 1 (Rc(opcode) == 0) */
226     uint32_t inval1;
227     /* invalid bits for instruction 2 (Rc(opcode) == 1) */
228     uint32_t inval2;
229     /* instruction type */
230     uint64_t type;
231     /* extended instruction type */
232     uint64_t type2;
233     /* handler */
234     void (*handler)(DisasContext *ctx);
235 };
236 
237 static inline bool gen_serialize(DisasContext *ctx)
238 {
239     if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
240         /* Restart with exclusive lock.  */
241         gen_helper_exit_atomic(cpu_env);
242         ctx->base.is_jmp = DISAS_NORETURN;
243         return false;
244     }
245     return true;
246 }
247 
248 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
249 static inline bool gen_serialize_core_lpar(DisasContext *ctx)
250 {
251     if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) {
252         return gen_serialize(ctx);
253     }
254 
255     return true;
256 }
257 #endif
258 
259 /* SPR load/store helpers */
260 static inline void gen_load_spr(TCGv t, int reg)
261 {
262     tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
263 }
264 
265 static inline void gen_store_spr(int reg, TCGv t)
266 {
267     tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
268 }
269 
270 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
271 {
272     if (ctx->need_access_type && ctx->access_type != access_type) {
273         tcg_gen_movi_i32(cpu_access_type, access_type);
274         ctx->access_type = access_type;
275     }
276 }
277 
278 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
279 {
280     if (NARROW_MODE(ctx)) {
281         nip = (uint32_t)nip;
282     }
283     tcg_gen_movi_tl(cpu_nip, nip);
284 }
285 
286 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
287 {
288     TCGv_i32 t0, t1;
289 
290     /*
291      * These are all synchronous exceptions, we set the PC back to the
292      * faulting instruction
293      */
294     gen_update_nip(ctx, ctx->cia);
295     t0 = tcg_constant_i32(excp);
296     t1 = tcg_constant_i32(error);
297     gen_helper_raise_exception_err(cpu_env, t0, t1);
298     ctx->base.is_jmp = DISAS_NORETURN;
299 }
300 
301 static void gen_exception(DisasContext *ctx, uint32_t excp)
302 {
303     TCGv_i32 t0;
304 
305     /*
306      * These are all synchronous exceptions, we set the PC back to the
307      * faulting instruction
308      */
309     gen_update_nip(ctx, ctx->cia);
310     t0 = tcg_constant_i32(excp);
311     gen_helper_raise_exception(cpu_env, t0);
312     ctx->base.is_jmp = DISAS_NORETURN;
313 }
314 
315 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
316                               target_ulong nip)
317 {
318     TCGv_i32 t0;
319 
320     gen_update_nip(ctx, nip);
321     t0 = tcg_constant_i32(excp);
322     gen_helper_raise_exception(cpu_env, t0);
323     ctx->base.is_jmp = DISAS_NORETURN;
324 }
325 
326 #if !defined(CONFIG_USER_ONLY)
327 static void gen_ppc_maybe_interrupt(DisasContext *ctx)
328 {
329     translator_io_start(&ctx->base);
330     gen_helper_ppc_maybe_interrupt(cpu_env);
331 }
332 #endif
333 
334 /*
335  * Tells the caller what is the appropriate exception to generate and prepares
336  * SPR registers for this exception.
337  *
338  * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
339  * POWERPC_EXCP_DEBUG (on BookE).
340  */
341 static uint32_t gen_prep_dbgex(DisasContext *ctx)
342 {
343     if (ctx->flags & POWERPC_FLAG_DE) {
344         target_ulong dbsr = 0;
345         if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
346             dbsr = DBCR0_ICMP;
347         } else {
348             /* Must have been branch */
349             dbsr = DBCR0_BRT;
350         }
351         TCGv t0 = tcg_temp_new();
352         gen_load_spr(t0, SPR_BOOKE_DBSR);
353         tcg_gen_ori_tl(t0, t0, dbsr);
354         gen_store_spr(SPR_BOOKE_DBSR, t0);
355         return POWERPC_EXCP_DEBUG;
356     } else {
357         return POWERPC_EXCP_TRACE;
358     }
359 }
360 
361 static void gen_debug_exception(DisasContext *ctx)
362 {
363     gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
364     ctx->base.is_jmp = DISAS_NORETURN;
365 }
366 
367 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
368 {
369     /* Will be converted to program check if needed */
370     gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
371 }
372 
373 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
374 {
375     gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
376 }
377 
378 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
379 {
380     /* Will be converted to program check if needed */
381     gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
382 }
383 
384 /*****************************************************************************/
385 /* SPR READ/WRITE CALLBACKS */
386 
387 void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
388 {
389 #if 0
390     sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
391     printf("ERROR: try to access SPR %d !\n", sprn);
392 #endif
393 }
394 
395 /* #define PPC_DUMP_SPR_ACCESSES */
396 
397 /*
398  * Generic callbacks:
399  * do nothing but store/retrieve spr value
400  */
401 static void spr_load_dump_spr(int sprn)
402 {
403 #ifdef PPC_DUMP_SPR_ACCESSES
404     TCGv_i32 t0 = tcg_constant_i32(sprn);
405     gen_helper_load_dump_spr(cpu_env, t0);
406 #endif
407 }
408 
409 void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
410 {
411     gen_load_spr(cpu_gpr[gprn], sprn);
412     spr_load_dump_spr(sprn);
413 }
414 
415 static void spr_store_dump_spr(int sprn)
416 {
417 #ifdef PPC_DUMP_SPR_ACCESSES
418     TCGv_i32 t0 = tcg_constant_i32(sprn);
419     gen_helper_store_dump_spr(cpu_env, t0);
420 #endif
421 }
422 
423 void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
424 {
425     gen_store_spr(sprn, cpu_gpr[gprn]);
426     spr_store_dump_spr(sprn);
427 }
428 
429 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
430 {
431 #ifdef TARGET_PPC64
432     TCGv t0 = tcg_temp_new();
433     tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
434     gen_store_spr(sprn, t0);
435     spr_store_dump_spr(sprn);
436 #else
437     spr_write_generic(ctx, sprn, gprn);
438 #endif
439 }
440 
441 void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn)
442 {
443     if (!(ctx->flags & POWERPC_FLAG_SMT)) {
444         spr_write_generic(ctx, sprn, gprn);
445         return;
446     }
447 
448     if (!gen_serialize(ctx)) {
449         return;
450     }
451 
452     gen_helper_spr_core_write_generic(cpu_env, tcg_constant_i32(sprn),
453                                       cpu_gpr[gprn]);
454     spr_store_dump_spr(sprn);
455 }
456 
457 static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn)
458 {
459     /* This does not implement >1 thread */
460     TCGv t0 = tcg_temp_new();
461     TCGv t1 = tcg_temp_new();
462     tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */
463     tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */
464     tcg_gen_or_tl(t1, t1, t0);
465     gen_store_spr(sprn, t1);
466 }
467 
468 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
469 {
470     if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) {
471         /* CTRL behaves as 1-thread in LPAR-per-thread mode */
472         spr_write_CTRL_ST(ctx, sprn, gprn);
473         goto out;
474     }
475 
476     if (!gen_serialize(ctx)) {
477         return;
478     }
479 
480     gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn),
481                               cpu_gpr[gprn]);
482 out:
483     spr_store_dump_spr(sprn);
484 
485     /*
486      * SPR_CTRL writes must force a new translation block,
487      * allowing the PMU to calculate the run latch events with
488      * more accuracy.
489      */
490     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
491 }
492 
493 #if !defined(CONFIG_USER_ONLY)
494 void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
495 {
496     TCGv t0 = tcg_temp_new();
497     TCGv t1 = tcg_temp_new();
498     gen_load_spr(t0, sprn);
499     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
500     tcg_gen_and_tl(t0, t0, t1);
501     gen_store_spr(sprn, t0);
502 }
503 
504 void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
505 {
506 }
507 
508 #endif
509 
510 /* SPR common to all PowerPC */
511 /* XER */
512 void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
513 {
514     TCGv dst = cpu_gpr[gprn];
515     TCGv t0 = tcg_temp_new();
516     TCGv t1 = tcg_temp_new();
517     TCGv t2 = tcg_temp_new();
518     tcg_gen_mov_tl(dst, cpu_xer);
519     tcg_gen_shli_tl(t0, cpu_so, XER_SO);
520     tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
521     tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
522     tcg_gen_or_tl(t0, t0, t1);
523     tcg_gen_or_tl(dst, dst, t2);
524     tcg_gen_or_tl(dst, dst, t0);
525     if (is_isa300(ctx)) {
526         tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
527         tcg_gen_or_tl(dst, dst, t0);
528         tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
529         tcg_gen_or_tl(dst, dst, t0);
530     }
531 }
532 
533 void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
534 {
535     TCGv src = cpu_gpr[gprn];
536     /* Write all flags, while reading back check for isa300 */
537     tcg_gen_andi_tl(cpu_xer, src,
538                     ~((1u << XER_SO) |
539                       (1u << XER_OV) | (1u << XER_OV32) |
540                       (1u << XER_CA) | (1u << XER_CA32)));
541     tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
542     tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
543     tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
544     tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
545     tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
546 }
547 
548 /* LR */
549 void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
550 {
551     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
552 }
553 
554 void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
555 {
556     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
557 }
558 
559 /* CFAR */
560 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
561 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
562 {
563     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
564 }
565 
566 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
567 {
568     tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
569 }
570 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
571 
572 /* CTR */
573 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
574 {
575     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
576 }
577 
578 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
579 {
580     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
581 }
582 
583 /* User read access to SPR */
584 /* USPRx */
585 /* UMMCRx */
586 /* UPMCx */
587 /* USIA */
588 /* UDECR */
589 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
590 {
591     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
592 }
593 
594 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
595 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
596 {
597     gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
598 }
599 #endif
600 
601 /* SPR common to all non-embedded PowerPC */
602 /* DECR */
603 #if !defined(CONFIG_USER_ONLY)
604 void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
605 {
606     translator_io_start(&ctx->base);
607     gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
608 }
609 
610 void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
611 {
612     translator_io_start(&ctx->base);
613     gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
614 }
615 #endif
616 
617 /* SPR common to all non-embedded PowerPC, except 601 */
618 /* Time base */
619 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
620 {
621     translator_io_start(&ctx->base);
622     gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
623 }
624 
625 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
626 {
627     translator_io_start(&ctx->base);
628     gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
629 }
630 
631 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
632 {
633     gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
634 }
635 
636 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
637 {
638     gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
639 }
640 
641 #if !defined(CONFIG_USER_ONLY)
642 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
643 {
644     translator_io_start(&ctx->base);
645     gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
646 }
647 
648 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
649 {
650     translator_io_start(&ctx->base);
651     gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
652 }
653 
654 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
655 {
656     gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
657 }
658 
659 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
660 {
661     gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
662 }
663 
664 #if defined(TARGET_PPC64)
665 void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
666 {
667     translator_io_start(&ctx->base);
668     gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
669 }
670 
671 void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
672 {
673     translator_io_start(&ctx->base);
674     gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
675 }
676 
677 /* HDECR */
678 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
679 {
680     translator_io_start(&ctx->base);
681     gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
682 }
683 
684 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
685 {
686     translator_io_start(&ctx->base);
687     gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
688 }
689 
690 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
691 {
692     translator_io_start(&ctx->base);
693     gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
694 }
695 
696 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
697 {
698     translator_io_start(&ctx->base);
699     gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
700 }
701 
702 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
703 {
704     translator_io_start(&ctx->base);
705     gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
706 }
707 
708 #endif
709 #endif
710 
711 #if !defined(CONFIG_USER_ONLY)
712 /* IBAT0U...IBAT0U */
713 /* IBAT0L...IBAT7L */
714 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
715 {
716     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
717                   offsetof(CPUPPCState,
718                            IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
719 }
720 
721 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
722 {
723     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
724                   offsetof(CPUPPCState,
725                            IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
726 }
727 
728 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
729 {
730     TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2);
731     gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
732 }
733 
734 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
735 {
736     TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4);
737     gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
738 }
739 
740 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
741 {
742     TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2);
743     gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
744 }
745 
746 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
747 {
748     TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4);
749     gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
750 }
751 
752 /* DBAT0U...DBAT7U */
753 /* DBAT0L...DBAT7L */
754 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
755 {
756     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
757                   offsetof(CPUPPCState,
758                            DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
759 }
760 
761 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
762 {
763     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
764                   offsetof(CPUPPCState,
765                            DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
766 }
767 
768 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
769 {
770     TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2);
771     gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
772 }
773 
774 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
775 {
776     TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4);
777     gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
778 }
779 
780 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
781 {
782     TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2);
783     gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
784 }
785 
786 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
787 {
788     TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4);
789     gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
790 }
791 
792 /* SDR1 */
793 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
794 {
795     gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
796 }
797 
798 #if defined(TARGET_PPC64)
799 /* 64 bits PowerPC specific SPRs */
800 /* PIDR */
801 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
802 {
803     gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
804 }
805 
806 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
807 {
808     gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
809 }
810 
811 void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
812 {
813     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
814 }
815 
816 void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
817 {
818     TCGv t0 = tcg_temp_new();
819     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
820     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
821 }
822 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
823 {
824     gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
825 }
826 
827 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
828 {
829     gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
830 }
831 
832 /* DPDES */
833 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
834 {
835     if (!gen_serialize_core_lpar(ctx)) {
836         return;
837     }
838 
839     gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
840 }
841 
842 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
843 {
844     if (!gen_serialize_core_lpar(ctx)) {
845         return;
846     }
847 
848     gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
849 }
850 #endif
851 #endif
852 
853 /* PowerPC 40x specific registers */
854 #if !defined(CONFIG_USER_ONLY)
855 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
856 {
857     translator_io_start(&ctx->base);
858     gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
859 }
860 
861 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
862 {
863     translator_io_start(&ctx->base);
864     gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
865 }
866 
867 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
868 {
869     translator_io_start(&ctx->base);
870     gen_store_spr(sprn, cpu_gpr[gprn]);
871     gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
872     /* We must stop translation as we may have rebooted */
873     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
874 }
875 
876 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
877 {
878     translator_io_start(&ctx->base);
879     gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
880 }
881 
882 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
883 {
884     translator_io_start(&ctx->base);
885     gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]);
886 }
887 
888 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn)
889 {
890     translator_io_start(&ctx->base);
891     gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]);
892 }
893 
894 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
895 {
896     TCGv t0 = tcg_temp_new();
897     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF);
898     gen_helper_store_40x_pid(cpu_env, t0);
899 }
900 
901 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
902 {
903     translator_io_start(&ctx->base);
904     gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
905 }
906 
907 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
908 {
909     translator_io_start(&ctx->base);
910     gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
911 }
912 #endif
913 
914 /* PIR */
915 #if !defined(CONFIG_USER_ONLY)
916 void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
917 {
918     TCGv t0 = tcg_temp_new();
919     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
920     gen_store_spr(SPR_PIR, t0);
921 }
922 #endif
923 
924 /* SPE specific registers */
925 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
926 {
927     TCGv_i32 t0 = tcg_temp_new_i32();
928     tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
929     tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
930 }
931 
932 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
933 {
934     TCGv_i32 t0 = tcg_temp_new_i32();
935     tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
936     tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
937 }
938 
939 #if !defined(CONFIG_USER_ONLY)
940 /* Callback used to write the exception vector base */
941 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
942 {
943     TCGv t0 = tcg_temp_new();
944     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
945     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
946     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
947     gen_store_spr(sprn, t0);
948 }
949 
950 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
951 {
952     int sprn_offs;
953 
954     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
955         sprn_offs = sprn - SPR_BOOKE_IVOR0;
956     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
957         sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
958     } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
959         sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
960     } else {
961         qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception"
962                       " vector 0x%03x\n", sprn);
963         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
964         return;
965     }
966 
967     TCGv t0 = tcg_temp_new();
968     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
969     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
970     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
971     gen_store_spr(sprn, t0);
972 }
973 #endif
974 
975 #ifdef TARGET_PPC64
976 #ifndef CONFIG_USER_ONLY
977 void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
978 {
979     TCGv t0 = tcg_temp_new();
980     TCGv t1 = tcg_temp_new();
981     TCGv t2 = tcg_temp_new();
982 
983     /*
984      * Note, the HV=1 PR=0 case is handled earlier by simply using
985      * spr_write_generic for HV mode in the SPR table
986      */
987 
988     /* Build insertion mask into t1 based on context */
989     if (ctx->pr) {
990         gen_load_spr(t1, SPR_UAMOR);
991     } else {
992         gen_load_spr(t1, SPR_AMOR);
993     }
994 
995     /* Mask new bits into t2 */
996     tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
997 
998     /* Load AMR and clear new bits in t0 */
999     gen_load_spr(t0, SPR_AMR);
1000     tcg_gen_andc_tl(t0, t0, t1);
1001 
1002     /* Or'in new bits and write it out */
1003     tcg_gen_or_tl(t0, t0, t2);
1004     gen_store_spr(SPR_AMR, t0);
1005     spr_store_dump_spr(SPR_AMR);
1006 }
1007 
1008 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1009 {
1010     TCGv t0 = tcg_temp_new();
1011     TCGv t1 = tcg_temp_new();
1012     TCGv t2 = tcg_temp_new();
1013 
1014     /*
1015      * Note, the HV=1 case is handled earlier by simply using
1016      * spr_write_generic for HV mode in the SPR table
1017      */
1018 
1019     /* Build insertion mask into t1 based on context */
1020     gen_load_spr(t1, SPR_AMOR);
1021 
1022     /* Mask new bits into t2 */
1023     tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1024 
1025     /* Load AMR and clear new bits in t0 */
1026     gen_load_spr(t0, SPR_UAMOR);
1027     tcg_gen_andc_tl(t0, t0, t1);
1028 
1029     /* Or'in new bits and write it out */
1030     tcg_gen_or_tl(t0, t0, t2);
1031     gen_store_spr(SPR_UAMOR, t0);
1032     spr_store_dump_spr(SPR_UAMOR);
1033 }
1034 
1035 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1036 {
1037     TCGv t0 = tcg_temp_new();
1038     TCGv t1 = tcg_temp_new();
1039     TCGv t2 = tcg_temp_new();
1040 
1041     /*
1042      * Note, the HV=1 case is handled earlier by simply using
1043      * spr_write_generic for HV mode in the SPR table
1044      */
1045 
1046     /* Build insertion mask into t1 based on context */
1047     gen_load_spr(t1, SPR_AMOR);
1048 
1049     /* Mask new bits into t2 */
1050     tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1051 
1052     /* Load AMR and clear new bits in t0 */
1053     gen_load_spr(t0, SPR_IAMR);
1054     tcg_gen_andc_tl(t0, t0, t1);
1055 
1056     /* Or'in new bits and write it out */
1057     tcg_gen_or_tl(t0, t0, t2);
1058     gen_store_spr(SPR_IAMR, t0);
1059     spr_store_dump_spr(SPR_IAMR);
1060 }
1061 #endif
1062 #endif
1063 
1064 #ifndef CONFIG_USER_ONLY
1065 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1066 {
1067     gen_helper_fixup_thrm(cpu_env);
1068     gen_load_spr(cpu_gpr[gprn], sprn);
1069     spr_load_dump_spr(sprn);
1070 }
1071 #endif /* !CONFIG_USER_ONLY */
1072 
1073 #if !defined(CONFIG_USER_ONLY)
1074 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1075 {
1076     TCGv t0 = tcg_temp_new();
1077 
1078     tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1079     gen_store_spr(sprn, t0);
1080 }
1081 
1082 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1083 {
1084     TCGv t0 = tcg_temp_new();
1085 
1086     tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1087     gen_store_spr(sprn, t0);
1088 }
1089 
1090 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
1091 {
1092     TCGv t0 = tcg_temp_new();
1093 
1094     tcg_gen_andi_tl(t0, cpu_gpr[gprn],
1095                     ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
1096     gen_store_spr(sprn, t0);
1097 }
1098 
1099 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1100 {
1101     gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1102 }
1103 
1104 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1105 {
1106     TCGv_i32 t0 = tcg_constant_i32(sprn);
1107     gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1108 }
1109 
1110 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1111 {
1112     gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1113 }
1114 
1115 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1116 {
1117     gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1118 }
1119 
1120 #endif
1121 
1122 #if !defined(CONFIG_USER_ONLY)
1123 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
1124 {
1125     TCGv val = tcg_temp_new();
1126     tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
1127     gen_store_spr(SPR_BOOKE_MAS3, val);
1128     tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
1129     gen_store_spr(SPR_BOOKE_MAS7, val);
1130 }
1131 
1132 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
1133 {
1134     TCGv mas7 = tcg_temp_new();
1135     TCGv mas3 = tcg_temp_new();
1136     gen_load_spr(mas7, SPR_BOOKE_MAS7);
1137     tcg_gen_shli_tl(mas7, mas7, 32);
1138     gen_load_spr(mas3, SPR_BOOKE_MAS3);
1139     tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
1140 }
1141 
1142 #endif
1143 
1144 #ifdef TARGET_PPC64
1145 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
1146                                     int bit, int sprn, int cause)
1147 {
1148     TCGv_i32 t1 = tcg_constant_i32(bit);
1149     TCGv_i32 t2 = tcg_constant_i32(sprn);
1150     TCGv_i32 t3 = tcg_constant_i32(cause);
1151 
1152     gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
1153 }
1154 
1155 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
1156                                    int bit, int sprn, int cause)
1157 {
1158     TCGv_i32 t1 = tcg_constant_i32(bit);
1159     TCGv_i32 t2 = tcg_constant_i32(sprn);
1160     TCGv_i32 t3 = tcg_constant_i32(cause);
1161 
1162     gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
1163 }
1164 
1165 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
1166 {
1167     TCGv spr_up = tcg_temp_new();
1168     TCGv spr = tcg_temp_new();
1169 
1170     gen_load_spr(spr, sprn - 1);
1171     tcg_gen_shri_tl(spr_up, spr, 32);
1172     tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
1173 }
1174 
1175 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
1176 {
1177     TCGv spr = tcg_temp_new();
1178 
1179     gen_load_spr(spr, sprn - 1);
1180     tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
1181     gen_store_spr(sprn - 1, spr);
1182 }
1183 
1184 #if !defined(CONFIG_USER_ONLY)
1185 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
1186 {
1187     TCGv hmer = tcg_temp_new();
1188 
1189     gen_load_spr(hmer, sprn);
1190     tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
1191     gen_store_spr(sprn, hmer);
1192     spr_store_dump_spr(sprn);
1193 }
1194 
1195 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn)
1196 {
1197     gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env);
1198 }
1199 
1200 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn)
1201 {
1202     gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]);
1203 }
1204 
1205 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
1206 {
1207     translator_io_start(&ctx->base);
1208     gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
1209 }
1210 #endif /* !defined(CONFIG_USER_ONLY) */
1211 
1212 void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
1213 {
1214     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1215     spr_read_generic(ctx, gprn, sprn);
1216 }
1217 
1218 void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
1219 {
1220     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1221     spr_write_generic(ctx, sprn, gprn);
1222 }
1223 
1224 void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
1225 {
1226     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1227     spr_read_generic(ctx, gprn, sprn);
1228 }
1229 
1230 void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
1231 {
1232     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1233     spr_write_generic(ctx, sprn, gprn);
1234 }
1235 
1236 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
1237 {
1238     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1239     spr_read_prev_upper32(ctx, gprn, sprn);
1240 }
1241 
1242 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
1243 {
1244     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1245     spr_write_prev_upper32(ctx, sprn, gprn);
1246 }
1247 
1248 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
1249 {
1250     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1251     spr_read_generic(ctx, gprn, sprn);
1252 }
1253 
1254 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
1255 {
1256     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1257     spr_write_generic(ctx, sprn, gprn);
1258 }
1259 
1260 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
1261 {
1262     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1263     spr_read_prev_upper32(ctx, gprn, sprn);
1264 }
1265 
1266 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
1267 {
1268     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1269     spr_write_prev_upper32(ctx, sprn, gprn);
1270 }
1271 
1272 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn)
1273 {
1274     TCGv t0 = tcg_temp_new();
1275 
1276     /*
1277      * Access to the (H)DEXCR in problem state is done using separated
1278      * SPR indexes which are 16 below the SPR indexes which have full
1279      * access to the (H)DEXCR in privileged state. Problem state can
1280      * only read bits 32:63, bits 0:31 return 0.
1281      *
1282      * See section 9.3.1-9.3.2 of PowerISA v3.1B
1283      */
1284 
1285     gen_load_spr(t0, sprn + 16);
1286     tcg_gen_ext32u_tl(cpu_gpr[gprn], t0);
1287 }
1288 #endif
1289 
1290 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
1291 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1292 
1293 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2)             \
1294 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
1295 
1296 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
1297 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1298 
1299 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2)      \
1300 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
1301 
1302 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2)     \
1303 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
1304 
1305 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
1306 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
1307 
1308 typedef struct opcode_t {
1309     unsigned char opc1, opc2, opc3, opc4;
1310 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
1311     unsigned char pad[4];
1312 #endif
1313     opc_handler_t handler;
1314     const char *oname;
1315 } opcode_t;
1316 
1317 static void gen_priv_opc(DisasContext *ctx)
1318 {
1319     gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
1320 }
1321 
1322 /* Helpers for priv. check */
1323 #define GEN_PRIV(CTX)              \
1324     do {                           \
1325         gen_priv_opc(CTX); return; \
1326     } while (0)
1327 
1328 #if defined(CONFIG_USER_ONLY)
1329 #define CHK_HV(CTX) GEN_PRIV(CTX)
1330 #define CHK_SV(CTX) GEN_PRIV(CTX)
1331 #define CHK_HVRM(CTX) GEN_PRIV(CTX)
1332 #else
1333 #define CHK_HV(CTX)                         \
1334     do {                                    \
1335         if (unlikely(ctx->pr || !ctx->hv)) {\
1336             GEN_PRIV(CTX);                  \
1337         }                                   \
1338     } while (0)
1339 #define CHK_SV(CTX)              \
1340     do {                         \
1341         if (unlikely(ctx->pr)) { \
1342             GEN_PRIV(CTX);       \
1343         }                        \
1344     } while (0)
1345 #define CHK_HVRM(CTX)                                   \
1346     do {                                                \
1347         if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
1348             GEN_PRIV(CTX);                              \
1349         }                                               \
1350     } while (0)
1351 #endif
1352 
1353 #define CHK_NONE(CTX)
1354 
1355 /*****************************************************************************/
1356 /* PowerPC instructions table                                                */
1357 
1358 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)                    \
1359 {                                                                             \
1360     .opc1 = op1,                                                              \
1361     .opc2 = op2,                                                              \
1362     .opc3 = op3,                                                              \
1363     .opc4 = 0xff,                                                             \
1364     .handler = {                                                              \
1365         .inval1  = invl,                                                      \
1366         .type = _typ,                                                         \
1367         .type2 = _typ2,                                                       \
1368         .handler = &gen_##name,                                               \
1369     },                                                                        \
1370     .oname = stringify(name),                                                 \
1371 }
1372 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2)       \
1373 {                                                                             \
1374     .opc1 = op1,                                                              \
1375     .opc2 = op2,                                                              \
1376     .opc3 = op3,                                                              \
1377     .opc4 = 0xff,                                                             \
1378     .handler = {                                                              \
1379         .inval1  = invl1,                                                     \
1380         .inval2  = invl2,                                                     \
1381         .type = _typ,                                                         \
1382         .type2 = _typ2,                                                       \
1383         .handler = &gen_##name,                                               \
1384     },                                                                        \
1385     .oname = stringify(name),                                                 \
1386 }
1387 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2)             \
1388 {                                                                             \
1389     .opc1 = op1,                                                              \
1390     .opc2 = op2,                                                              \
1391     .opc3 = op3,                                                              \
1392     .opc4 = 0xff,                                                             \
1393     .handler = {                                                              \
1394         .inval1  = invl,                                                      \
1395         .type = _typ,                                                         \
1396         .type2 = _typ2,                                                       \
1397         .handler = &gen_##name,                                               \
1398     },                                                                        \
1399     .oname = onam,                                                            \
1400 }
1401 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2)              \
1402 {                                                                             \
1403     .opc1 = op1,                                                              \
1404     .opc2 = op2,                                                              \
1405     .opc3 = op3,                                                              \
1406     .opc4 = op4,                                                              \
1407     .handler = {                                                              \
1408         .inval1  = invl,                                                      \
1409         .type = _typ,                                                         \
1410         .type2 = _typ2,                                                       \
1411         .handler = &gen_##name,                                               \
1412     },                                                                        \
1413     .oname = stringify(name),                                                 \
1414 }
1415 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2)        \
1416 {                                                                             \
1417     .opc1 = op1,                                                              \
1418     .opc2 = op2,                                                              \
1419     .opc3 = op3,                                                              \
1420     .opc4 = op4,                                                              \
1421     .handler = {                                                              \
1422         .inval1  = invl,                                                      \
1423         .type = _typ,                                                         \
1424         .type2 = _typ2,                                                       \
1425         .handler = &gen_##name,                                               \
1426     },                                                                        \
1427     .oname = onam,                                                            \
1428 }
1429 
1430 /* Invalid instruction */
1431 static void gen_invalid(DisasContext *ctx)
1432 {
1433     gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
1434 }
1435 
1436 static opc_handler_t invalid_handler = {
1437     .inval1  = 0xFFFFFFFF,
1438     .inval2  = 0xFFFFFFFF,
1439     .type    = PPC_NONE,
1440     .type2   = PPC_NONE,
1441     .handler = gen_invalid,
1442 };
1443 
1444 /***                           Integer comparison                          ***/
1445 
1446 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
1447 {
1448     TCGv t0 = tcg_temp_new();
1449     TCGv t1 = tcg_temp_new();
1450     TCGv_i32 t = tcg_temp_new_i32();
1451 
1452     tcg_gen_movi_tl(t0, CRF_EQ);
1453     tcg_gen_movi_tl(t1, CRF_LT);
1454     tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU),
1455                        t0, arg0, arg1, t1, t0);
1456     tcg_gen_movi_tl(t1, CRF_GT);
1457     tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU),
1458                        t0, arg0, arg1, t1, t0);
1459 
1460     tcg_gen_trunc_tl_i32(t, t0);
1461     tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
1462     tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
1463 }
1464 
1465 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
1466 {
1467     TCGv t0 = tcg_constant_tl(arg1);
1468     gen_op_cmp(arg0, t0, s, crf);
1469 }
1470 
1471 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
1472 {
1473     TCGv t0, t1;
1474     t0 = tcg_temp_new();
1475     t1 = tcg_temp_new();
1476     if (s) {
1477         tcg_gen_ext32s_tl(t0, arg0);
1478         tcg_gen_ext32s_tl(t1, arg1);
1479     } else {
1480         tcg_gen_ext32u_tl(t0, arg0);
1481         tcg_gen_ext32u_tl(t1, arg1);
1482     }
1483     gen_op_cmp(t0, t1, s, crf);
1484 }
1485 
1486 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
1487 {
1488     TCGv t0 = tcg_constant_tl(arg1);
1489     gen_op_cmp32(arg0, t0, s, crf);
1490 }
1491 
1492 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
1493 {
1494     if (NARROW_MODE(ctx)) {
1495         gen_op_cmpi32(reg, 0, 1, 0);
1496     } else {
1497         gen_op_cmpi(reg, 0, 1, 0);
1498     }
1499 }
1500 
1501 /* cmprb - range comparison: isupper, isaplha, islower*/
1502 static void gen_cmprb(DisasContext *ctx)
1503 {
1504     TCGv_i32 src1 = tcg_temp_new_i32();
1505     TCGv_i32 src2 = tcg_temp_new_i32();
1506     TCGv_i32 src2lo = tcg_temp_new_i32();
1507     TCGv_i32 src2hi = tcg_temp_new_i32();
1508     TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
1509 
1510     tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
1511     tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
1512 
1513     tcg_gen_andi_i32(src1, src1, 0xFF);
1514     tcg_gen_ext8u_i32(src2lo, src2);
1515     tcg_gen_shri_i32(src2, src2, 8);
1516     tcg_gen_ext8u_i32(src2hi, src2);
1517 
1518     tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1519     tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1520     tcg_gen_and_i32(crf, src2lo, src2hi);
1521 
1522     if (ctx->opcode & 0x00200000) {
1523         tcg_gen_shri_i32(src2, src2, 8);
1524         tcg_gen_ext8u_i32(src2lo, src2);
1525         tcg_gen_shri_i32(src2, src2, 8);
1526         tcg_gen_ext8u_i32(src2hi, src2);
1527         tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1528         tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1529         tcg_gen_and_i32(src2lo, src2lo, src2hi);
1530         tcg_gen_or_i32(crf, crf, src2lo);
1531     }
1532     tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
1533 }
1534 
1535 #if defined(TARGET_PPC64)
1536 /* cmpeqb */
1537 static void gen_cmpeqb(DisasContext *ctx)
1538 {
1539     gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1540                       cpu_gpr[rB(ctx->opcode)]);
1541 }
1542 #endif
1543 
1544 /* isel (PowerPC 2.03 specification) */
1545 static void gen_isel(DisasContext *ctx)
1546 {
1547     uint32_t bi = rC(ctx->opcode);
1548     uint32_t mask = 0x08 >> (bi & 0x03);
1549     TCGv t0 = tcg_temp_new();
1550     TCGv zr;
1551 
1552     tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
1553     tcg_gen_andi_tl(t0, t0, mask);
1554 
1555     zr = tcg_constant_tl(0);
1556     tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
1557                        rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
1558                        cpu_gpr[rB(ctx->opcode)]);
1559 }
1560 
1561 /* cmpb: PowerPC 2.05 specification */
1562 static void gen_cmpb(DisasContext *ctx)
1563 {
1564     gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1565                     cpu_gpr[rB(ctx->opcode)]);
1566 }
1567 
1568 /***                           Integer arithmetic                          ***/
1569 
1570 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
1571                                            TCGv arg1, TCGv arg2, int sub)
1572 {
1573     TCGv t0 = tcg_temp_new();
1574 
1575     tcg_gen_xor_tl(cpu_ov, arg0, arg2);
1576     tcg_gen_xor_tl(t0, arg1, arg2);
1577     if (sub) {
1578         tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
1579     } else {
1580         tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
1581     }
1582     if (NARROW_MODE(ctx)) {
1583         tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
1584         if (is_isa300(ctx)) {
1585             tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1586         }
1587     } else {
1588         if (is_isa300(ctx)) {
1589             tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
1590         }
1591         tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
1592     }
1593     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1594 }
1595 
1596 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
1597                                              TCGv res, TCGv arg0, TCGv arg1,
1598                                              TCGv ca32, int sub)
1599 {
1600     TCGv t0;
1601 
1602     if (!is_isa300(ctx)) {
1603         return;
1604     }
1605 
1606     t0 = tcg_temp_new();
1607     if (sub) {
1608         tcg_gen_eqv_tl(t0, arg0, arg1);
1609     } else {
1610         tcg_gen_xor_tl(t0, arg0, arg1);
1611     }
1612     tcg_gen_xor_tl(t0, t0, res);
1613     tcg_gen_extract_tl(ca32, t0, 32, 1);
1614 }
1615 
1616 /* Common add function */
1617 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
1618                                     TCGv arg2, TCGv ca, TCGv ca32,
1619                                     bool add_ca, bool compute_ca,
1620                                     bool compute_ov, bool compute_rc0)
1621 {
1622     TCGv t0 = ret;
1623 
1624     if (compute_ca || compute_ov) {
1625         t0 = tcg_temp_new();
1626     }
1627 
1628     if (compute_ca) {
1629         if (NARROW_MODE(ctx)) {
1630             /*
1631              * Caution: a non-obvious corner case of the spec is that
1632              * we must produce the *entire* 64-bit addition, but
1633              * produce the carry into bit 32.
1634              */
1635             TCGv t1 = tcg_temp_new();
1636             tcg_gen_xor_tl(t1, arg1, arg2);        /* add without carry */
1637             tcg_gen_add_tl(t0, arg1, arg2);
1638             if (add_ca) {
1639                 tcg_gen_add_tl(t0, t0, ca);
1640             }
1641             tcg_gen_xor_tl(ca, t0, t1);        /* bits changed w/ carry */
1642             tcg_gen_extract_tl(ca, ca, 32, 1);
1643             if (is_isa300(ctx)) {
1644                 tcg_gen_mov_tl(ca32, ca);
1645             }
1646         } else {
1647             TCGv zero = tcg_constant_tl(0);
1648             if (add_ca) {
1649                 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
1650                 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
1651             } else {
1652                 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
1653             }
1654             gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
1655         }
1656     } else {
1657         tcg_gen_add_tl(t0, arg1, arg2);
1658         if (add_ca) {
1659             tcg_gen_add_tl(t0, t0, ca);
1660         }
1661     }
1662 
1663     if (compute_ov) {
1664         gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
1665     }
1666     if (unlikely(compute_rc0)) {
1667         gen_set_Rc0(ctx, t0);
1668     }
1669 
1670     if (t0 != ret) {
1671         tcg_gen_mov_tl(ret, t0);
1672     }
1673 }
1674 /* Add functions with two operands */
1675 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov)     \
1676 static void glue(gen_, name)(DisasContext *ctx)                               \
1677 {                                                                             \
1678     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
1679                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
1680                      ca, glue(ca, 32),                                        \
1681                      add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \
1682 }
1683 /* Add functions with one operand and one immediate */
1684 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca,                    \
1685                                 add_ca, compute_ca, compute_ov)               \
1686 static void glue(gen_, name)(DisasContext *ctx)                               \
1687 {                                                                             \
1688     TCGv t0 = tcg_constant_tl(const_val);                                     \
1689     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
1690                      cpu_gpr[rA(ctx->opcode)], t0,                            \
1691                      ca, glue(ca, 32),                                        \
1692                      add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \
1693 }
1694 
1695 /* add  add.  addo  addo. */
1696 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
1697 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
1698 /* addc  addc.  addco  addco. */
1699 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
1700 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
1701 /* adde  adde.  addeo  addeo. */
1702 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
1703 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
1704 /* addme  addme.  addmeo  addmeo.  */
1705 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
1706 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
1707 /* addex */
1708 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
1709 /* addze  addze.  addzeo  addzeo.*/
1710 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
1711 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
1712 /* addic  addic.*/
1713 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1714 {
1715     TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
1716     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1717                      c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
1718 }
1719 
1720 static void gen_addic(DisasContext *ctx)
1721 {
1722     gen_op_addic(ctx, 0);
1723 }
1724 
1725 static void gen_addic_(DisasContext *ctx)
1726 {
1727     gen_op_addic(ctx, 1);
1728 }
1729 
1730 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1731                                      TCGv arg2, int sign, int compute_ov)
1732 {
1733     TCGv_i32 t0 = tcg_temp_new_i32();
1734     TCGv_i32 t1 = tcg_temp_new_i32();
1735     TCGv_i32 t2 = tcg_temp_new_i32();
1736     TCGv_i32 t3 = tcg_temp_new_i32();
1737 
1738     tcg_gen_trunc_tl_i32(t0, arg1);
1739     tcg_gen_trunc_tl_i32(t1, arg2);
1740     if (sign) {
1741         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1742         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1743         tcg_gen_and_i32(t2, t2, t3);
1744         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1745         tcg_gen_or_i32(t2, t2, t3);
1746         tcg_gen_movi_i32(t3, 0);
1747         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1748         tcg_gen_div_i32(t3, t0, t1);
1749         tcg_gen_extu_i32_tl(ret, t3);
1750     } else {
1751         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1752         tcg_gen_movi_i32(t3, 0);
1753         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1754         tcg_gen_divu_i32(t3, t0, t1);
1755         tcg_gen_extu_i32_tl(ret, t3);
1756     }
1757     if (compute_ov) {
1758         tcg_gen_extu_i32_tl(cpu_ov, t2);
1759         if (is_isa300(ctx)) {
1760             tcg_gen_extu_i32_tl(cpu_ov32, t2);
1761         }
1762         tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1763     }
1764 
1765     if (unlikely(Rc(ctx->opcode) != 0)) {
1766         gen_set_Rc0(ctx, ret);
1767     }
1768 }
1769 /* Div functions */
1770 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
1771 static void glue(gen_, name)(DisasContext *ctx)                               \
1772 {                                                                             \
1773     gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1774                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
1775                      sign, compute_ov);                                       \
1776 }
1777 /* divwu  divwu.  divwuo  divwuo.   */
1778 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1779 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1780 /* divw  divw.  divwo  divwo.   */
1781 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1782 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1783 
1784 /* div[wd]eu[o][.] */
1785 #define GEN_DIVE(name, hlpr, compute_ov)                                      \
1786 static void gen_##name(DisasContext *ctx)                                     \
1787 {                                                                             \
1788     TCGv_i32 t0 = tcg_constant_i32(compute_ov);                               \
1789     gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env,                      \
1790                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1791     if (unlikely(Rc(ctx->opcode) != 0)) {                                     \
1792         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);                           \
1793     }                                                                         \
1794 }
1795 
1796 GEN_DIVE(divweu, divweu, 0);
1797 GEN_DIVE(divweuo, divweu, 1);
1798 GEN_DIVE(divwe, divwe, 0);
1799 GEN_DIVE(divweo, divwe, 1);
1800 
1801 #if defined(TARGET_PPC64)
1802 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1803                                      TCGv arg2, int sign, int compute_ov)
1804 {
1805     TCGv_i64 t0 = tcg_temp_new_i64();
1806     TCGv_i64 t1 = tcg_temp_new_i64();
1807     TCGv_i64 t2 = tcg_temp_new_i64();
1808     TCGv_i64 t3 = tcg_temp_new_i64();
1809 
1810     tcg_gen_mov_i64(t0, arg1);
1811     tcg_gen_mov_i64(t1, arg2);
1812     if (sign) {
1813         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1814         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1815         tcg_gen_and_i64(t2, t2, t3);
1816         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1817         tcg_gen_or_i64(t2, t2, t3);
1818         tcg_gen_movi_i64(t3, 0);
1819         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1820         tcg_gen_div_i64(ret, t0, t1);
1821     } else {
1822         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1823         tcg_gen_movi_i64(t3, 0);
1824         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1825         tcg_gen_divu_i64(ret, t0, t1);
1826     }
1827     if (compute_ov) {
1828         tcg_gen_mov_tl(cpu_ov, t2);
1829         if (is_isa300(ctx)) {
1830             tcg_gen_mov_tl(cpu_ov32, t2);
1831         }
1832         tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1833     }
1834 
1835     if (unlikely(Rc(ctx->opcode) != 0)) {
1836         gen_set_Rc0(ctx, ret);
1837     }
1838 }
1839 
1840 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
1841 static void glue(gen_, name)(DisasContext *ctx)                               \
1842 {                                                                             \
1843     gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1844                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1845                       sign, compute_ov);                                      \
1846 }
1847 /* divdu  divdu.  divduo  divduo.   */
1848 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1849 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1850 /* divd  divd.  divdo  divdo.   */
1851 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1852 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1853 
1854 GEN_DIVE(divdeu, divdeu, 0);
1855 GEN_DIVE(divdeuo, divdeu, 1);
1856 GEN_DIVE(divde, divde, 0);
1857 GEN_DIVE(divdeo, divde, 1);
1858 #endif
1859 
1860 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1861                                      TCGv arg2, int sign)
1862 {
1863     TCGv_i32 t0 = tcg_temp_new_i32();
1864     TCGv_i32 t1 = tcg_temp_new_i32();
1865 
1866     tcg_gen_trunc_tl_i32(t0, arg1);
1867     tcg_gen_trunc_tl_i32(t1, arg2);
1868     if (sign) {
1869         TCGv_i32 t2 = tcg_temp_new_i32();
1870         TCGv_i32 t3 = tcg_temp_new_i32();
1871         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1872         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1873         tcg_gen_and_i32(t2, t2, t3);
1874         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1875         tcg_gen_or_i32(t2, t2, t3);
1876         tcg_gen_movi_i32(t3, 0);
1877         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1878         tcg_gen_rem_i32(t3, t0, t1);
1879         tcg_gen_ext_i32_tl(ret, t3);
1880     } else {
1881         TCGv_i32 t2 = tcg_constant_i32(1);
1882         TCGv_i32 t3 = tcg_constant_i32(0);
1883         tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1884         tcg_gen_remu_i32(t0, t0, t1);
1885         tcg_gen_extu_i32_tl(ret, t0);
1886     }
1887 }
1888 
1889 #define GEN_INT_ARITH_MODW(name, opc3, sign)                                \
1890 static void glue(gen_, name)(DisasContext *ctx)                             \
1891 {                                                                           \
1892     gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)],                        \
1893                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],   \
1894                       sign);                                                \
1895 }
1896 
1897 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1898 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1899 
1900 #if defined(TARGET_PPC64)
1901 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1902                                      TCGv arg2, int sign)
1903 {
1904     TCGv_i64 t0 = tcg_temp_new_i64();
1905     TCGv_i64 t1 = tcg_temp_new_i64();
1906 
1907     tcg_gen_mov_i64(t0, arg1);
1908     tcg_gen_mov_i64(t1, arg2);
1909     if (sign) {
1910         TCGv_i64 t2 = tcg_temp_new_i64();
1911         TCGv_i64 t3 = tcg_temp_new_i64();
1912         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1913         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1914         tcg_gen_and_i64(t2, t2, t3);
1915         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1916         tcg_gen_or_i64(t2, t2, t3);
1917         tcg_gen_movi_i64(t3, 0);
1918         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1919         tcg_gen_rem_i64(ret, t0, t1);
1920     } else {
1921         TCGv_i64 t2 = tcg_constant_i64(1);
1922         TCGv_i64 t3 = tcg_constant_i64(0);
1923         tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1924         tcg_gen_remu_i64(ret, t0, t1);
1925     }
1926 }
1927 
1928 #define GEN_INT_ARITH_MODD(name, opc3, sign)                            \
1929 static void glue(gen_, name)(DisasContext *ctx)                           \
1930 {                                                                         \
1931   gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)],                        \
1932                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],   \
1933                     sign);                                                \
1934 }
1935 
1936 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1937 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1938 #endif
1939 
1940 /* mulhw  mulhw. */
1941 static void gen_mulhw(DisasContext *ctx)
1942 {
1943     TCGv_i32 t0 = tcg_temp_new_i32();
1944     TCGv_i32 t1 = tcg_temp_new_i32();
1945 
1946     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1947     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1948     tcg_gen_muls2_i32(t0, t1, t0, t1);
1949     tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1950     if (unlikely(Rc(ctx->opcode) != 0)) {
1951         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1952     }
1953 }
1954 
1955 /* mulhwu  mulhwu.  */
1956 static void gen_mulhwu(DisasContext *ctx)
1957 {
1958     TCGv_i32 t0 = tcg_temp_new_i32();
1959     TCGv_i32 t1 = tcg_temp_new_i32();
1960 
1961     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1962     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1963     tcg_gen_mulu2_i32(t0, t1, t0, t1);
1964     tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1965     if (unlikely(Rc(ctx->opcode) != 0)) {
1966         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1967     }
1968 }
1969 
1970 /* mullw  mullw. */
1971 static void gen_mullw(DisasContext *ctx)
1972 {
1973 #if defined(TARGET_PPC64)
1974     TCGv_i64 t0, t1;
1975     t0 = tcg_temp_new_i64();
1976     t1 = tcg_temp_new_i64();
1977     tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1978     tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1979     tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1980 #else
1981     tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1982                     cpu_gpr[rB(ctx->opcode)]);
1983 #endif
1984     if (unlikely(Rc(ctx->opcode) != 0)) {
1985         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1986     }
1987 }
1988 
1989 /* mullwo  mullwo. */
1990 static void gen_mullwo(DisasContext *ctx)
1991 {
1992     TCGv_i32 t0 = tcg_temp_new_i32();
1993     TCGv_i32 t1 = tcg_temp_new_i32();
1994 
1995     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1996     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1997     tcg_gen_muls2_i32(t0, t1, t0, t1);
1998 #if defined(TARGET_PPC64)
1999     tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
2000 #else
2001     tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
2002 #endif
2003 
2004     tcg_gen_sari_i32(t0, t0, 31);
2005     tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
2006     tcg_gen_extu_i32_tl(cpu_ov, t0);
2007     if (is_isa300(ctx)) {
2008         tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2009     }
2010     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2011 
2012     if (unlikely(Rc(ctx->opcode) != 0)) {
2013         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2014     }
2015 }
2016 
2017 /* mulli */
2018 static void gen_mulli(DisasContext *ctx)
2019 {
2020     tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2021                     SIMM(ctx->opcode));
2022 }
2023 
2024 #if defined(TARGET_PPC64)
2025 /* mulhd  mulhd. */
2026 static void gen_mulhd(DisasContext *ctx)
2027 {
2028     TCGv lo = tcg_temp_new();
2029     tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2030                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2031     if (unlikely(Rc(ctx->opcode) != 0)) {
2032         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2033     }
2034 }
2035 
2036 /* mulhdu  mulhdu. */
2037 static void gen_mulhdu(DisasContext *ctx)
2038 {
2039     TCGv lo = tcg_temp_new();
2040     tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2041                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2042     if (unlikely(Rc(ctx->opcode) != 0)) {
2043         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2044     }
2045 }
2046 
2047 /* mulld  mulld. */
2048 static void gen_mulld(DisasContext *ctx)
2049 {
2050     tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2051                    cpu_gpr[rB(ctx->opcode)]);
2052     if (unlikely(Rc(ctx->opcode) != 0)) {
2053         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2054     }
2055 }
2056 
2057 /* mulldo  mulldo. */
2058 static void gen_mulldo(DisasContext *ctx)
2059 {
2060     TCGv_i64 t0 = tcg_temp_new_i64();
2061     TCGv_i64 t1 = tcg_temp_new_i64();
2062 
2063     tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
2064                       cpu_gpr[rB(ctx->opcode)]);
2065     tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
2066 
2067     tcg_gen_sari_i64(t0, t0, 63);
2068     tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
2069     if (is_isa300(ctx)) {
2070         tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2071     }
2072     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2073 
2074     if (unlikely(Rc(ctx->opcode) != 0)) {
2075         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2076     }
2077 }
2078 #endif
2079 
2080 /* Common subf function */
2081 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
2082                                      TCGv arg2, bool add_ca, bool compute_ca,
2083                                      bool compute_ov, bool compute_rc0)
2084 {
2085     TCGv t0 = ret;
2086 
2087     if (compute_ca || compute_ov) {
2088         t0 = tcg_temp_new();
2089     }
2090 
2091     if (compute_ca) {
2092         /* dest = ~arg1 + arg2 [+ ca].  */
2093         if (NARROW_MODE(ctx)) {
2094             /*
2095              * Caution: a non-obvious corner case of the spec is that
2096              * we must produce the *entire* 64-bit addition, but
2097              * produce the carry into bit 32.
2098              */
2099             TCGv inv1 = tcg_temp_new();
2100             TCGv t1 = tcg_temp_new();
2101             tcg_gen_not_tl(inv1, arg1);
2102             if (add_ca) {
2103                 tcg_gen_add_tl(t0, arg2, cpu_ca);
2104             } else {
2105                 tcg_gen_addi_tl(t0, arg2, 1);
2106             }
2107             tcg_gen_xor_tl(t1, arg2, inv1);         /* add without carry */
2108             tcg_gen_add_tl(t0, t0, inv1);
2109             tcg_gen_xor_tl(cpu_ca, t0, t1);         /* bits changes w/ carry */
2110             tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
2111             if (is_isa300(ctx)) {
2112                 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2113             }
2114         } else if (add_ca) {
2115             TCGv zero, inv1 = tcg_temp_new();
2116             tcg_gen_not_tl(inv1, arg1);
2117             zero = tcg_constant_tl(0);
2118             tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
2119             tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
2120             gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
2121         } else {
2122             tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
2123             tcg_gen_sub_tl(t0, arg2, arg1);
2124             gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1);
2125         }
2126     } else if (add_ca) {
2127         /*
2128          * Since we're ignoring carry-out, we can simplify the
2129          * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
2130          */
2131         tcg_gen_sub_tl(t0, arg2, arg1);
2132         tcg_gen_add_tl(t0, t0, cpu_ca);
2133         tcg_gen_subi_tl(t0, t0, 1);
2134     } else {
2135         tcg_gen_sub_tl(t0, arg2, arg1);
2136     }
2137 
2138     if (compute_ov) {
2139         gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
2140     }
2141     if (unlikely(compute_rc0)) {
2142         gen_set_Rc0(ctx, t0);
2143     }
2144 
2145     if (t0 != ret) {
2146         tcg_gen_mov_tl(ret, t0);
2147     }
2148 }
2149 /* Sub functions with Two operands functions */
2150 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
2151 static void glue(gen_, name)(DisasContext *ctx)                               \
2152 {                                                                             \
2153     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
2154                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
2155                       add_ca, compute_ca, compute_ov, Rc(ctx->opcode));       \
2156 }
2157 /* Sub functions with one operand and one immediate */
2158 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
2159                                 add_ca, compute_ca, compute_ov)               \
2160 static void glue(gen_, name)(DisasContext *ctx)                               \
2161 {                                                                             \
2162     TCGv t0 = tcg_constant_tl(const_val);                                     \
2163     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
2164                       cpu_gpr[rA(ctx->opcode)], t0,                           \
2165                       add_ca, compute_ca, compute_ov, Rc(ctx->opcode));       \
2166 }
2167 /* subf  subf.  subfo  subfo. */
2168 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
2169 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
2170 /* subfc  subfc.  subfco  subfco. */
2171 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
2172 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
2173 /* subfe  subfe.  subfeo  subfo. */
2174 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
2175 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
2176 /* subfme  subfme.  subfmeo  subfmeo.  */
2177 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
2178 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
2179 /* subfze  subfze.  subfzeo  subfzeo.*/
2180 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
2181 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
2182 
2183 /* subfic */
2184 static void gen_subfic(DisasContext *ctx)
2185 {
2186     TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
2187     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2188                       c, 0, 1, 0, 0);
2189 }
2190 
2191 /* neg neg. nego nego. */
2192 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
2193 {
2194     TCGv zero = tcg_constant_tl(0);
2195     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2196                       zero, 0, 0, compute_ov, Rc(ctx->opcode));
2197 }
2198 
2199 static void gen_neg(DisasContext *ctx)
2200 {
2201     tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2202     if (unlikely(Rc(ctx->opcode))) {
2203         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2204     }
2205 }
2206 
2207 static void gen_nego(DisasContext *ctx)
2208 {
2209     gen_op_arith_neg(ctx, 1);
2210 }
2211 
2212 /***                            Integer logical                            ***/
2213 #define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
2214 static void glue(gen_, name)(DisasContext *ctx)                               \
2215 {                                                                             \
2216     tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],                \
2217        cpu_gpr[rB(ctx->opcode)]);                                             \
2218     if (unlikely(Rc(ctx->opcode) != 0))                                       \
2219         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
2220 }
2221 
2222 #define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
2223 static void glue(gen_, name)(DisasContext *ctx)                               \
2224 {                                                                             \
2225     tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);               \
2226     if (unlikely(Rc(ctx->opcode) != 0))                                       \
2227         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
2228 }
2229 
2230 /* and & and. */
2231 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
2232 /* andc & andc. */
2233 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
2234 
2235 /* andi. */
2236 static void gen_andi_(DisasContext *ctx)
2237 {
2238     tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2239                     UIMM(ctx->opcode));
2240     gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2241 }
2242 
2243 /* andis. */
2244 static void gen_andis_(DisasContext *ctx)
2245 {
2246     tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2247                     UIMM(ctx->opcode) << 16);
2248     gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2249 }
2250 
2251 /* cntlzw */
2252 static void gen_cntlzw(DisasContext *ctx)
2253 {
2254     TCGv_i32 t = tcg_temp_new_i32();
2255 
2256     tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2257     tcg_gen_clzi_i32(t, t, 32);
2258     tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2259 
2260     if (unlikely(Rc(ctx->opcode) != 0)) {
2261         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2262     }
2263 }
2264 
2265 /* cnttzw */
2266 static void gen_cnttzw(DisasContext *ctx)
2267 {
2268     TCGv_i32 t = tcg_temp_new_i32();
2269 
2270     tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2271     tcg_gen_ctzi_i32(t, t, 32);
2272     tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2273 
2274     if (unlikely(Rc(ctx->opcode) != 0)) {
2275         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2276     }
2277 }
2278 
2279 /* eqv & eqv. */
2280 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
2281 /* extsb & extsb. */
2282 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
2283 /* extsh & extsh. */
2284 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
2285 /* nand & nand. */
2286 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
2287 /* nor & nor. */
2288 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
2289 
2290 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2291 static void gen_pause(DisasContext *ctx)
2292 {
2293     TCGv_i32 t0 = tcg_constant_i32(0);
2294     tcg_gen_st_i32(t0, cpu_env,
2295                    -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
2296 
2297     /* Stop translation, this gives other CPUs a chance to run */
2298     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
2299 }
2300 #endif /* defined(TARGET_PPC64) */
2301 
2302 /* or & or. */
2303 static void gen_or(DisasContext *ctx)
2304 {
2305     int rs, ra, rb;
2306 
2307     rs = rS(ctx->opcode);
2308     ra = rA(ctx->opcode);
2309     rb = rB(ctx->opcode);
2310     /* Optimisation for mr. ri case */
2311     if (rs != ra || rs != rb) {
2312         if (rs != rb) {
2313             tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
2314         } else {
2315             tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
2316         }
2317         if (unlikely(Rc(ctx->opcode) != 0)) {
2318             gen_set_Rc0(ctx, cpu_gpr[ra]);
2319         }
2320     } else if (unlikely(Rc(ctx->opcode) != 0)) {
2321         gen_set_Rc0(ctx, cpu_gpr[rs]);
2322 #if defined(TARGET_PPC64)
2323     } else if (rs != 0) { /* 0 is nop */
2324         int prio = 0;
2325 
2326         switch (rs) {
2327         case 1:
2328             /* Set process priority to low */
2329             prio = 2;
2330             break;
2331         case 6:
2332             /* Set process priority to medium-low */
2333             prio = 3;
2334             break;
2335         case 2:
2336             /* Set process priority to normal */
2337             prio = 4;
2338             break;
2339 #if !defined(CONFIG_USER_ONLY)
2340         case 31:
2341             if (!ctx->pr) {
2342                 /* Set process priority to very low */
2343                 prio = 1;
2344             }
2345             break;
2346         case 5:
2347             if (!ctx->pr) {
2348                 /* Set process priority to medium-hight */
2349                 prio = 5;
2350             }
2351             break;
2352         case 3:
2353             if (!ctx->pr) {
2354                 /* Set process priority to high */
2355                 prio = 6;
2356             }
2357             break;
2358         case 7:
2359             if (ctx->hv && !ctx->pr) {
2360                 /* Set process priority to very high */
2361                 prio = 7;
2362             }
2363             break;
2364 #endif
2365         default:
2366             break;
2367         }
2368         if (prio) {
2369             TCGv t0 = tcg_temp_new();
2370             gen_load_spr(t0, SPR_PPR);
2371             tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
2372             tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
2373             gen_store_spr(SPR_PPR, t0);
2374         }
2375 #if !defined(CONFIG_USER_ONLY)
2376         /*
2377          * Pause out of TCG otherwise spin loops with smt_low eat too
2378          * much CPU and the kernel hangs.  This applies to all
2379          * encodings other than no-op, e.g., miso(rs=26), yield(27),
2380          * mdoio(29), mdoom(30), and all currently undefined.
2381          */
2382         gen_pause(ctx);
2383 #endif
2384 #endif
2385     }
2386 }
2387 /* orc & orc. */
2388 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
2389 
2390 /* xor & xor. */
2391 static void gen_xor(DisasContext *ctx)
2392 {
2393     /* Optimisation for "set to zero" case */
2394     if (rS(ctx->opcode) != rB(ctx->opcode)) {
2395         tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2396                        cpu_gpr[rB(ctx->opcode)]);
2397     } else {
2398         tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2399     }
2400     if (unlikely(Rc(ctx->opcode) != 0)) {
2401         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2402     }
2403 }
2404 
2405 /* ori */
2406 static void gen_ori(DisasContext *ctx)
2407 {
2408     target_ulong uimm = UIMM(ctx->opcode);
2409 
2410     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2411         return;
2412     }
2413     tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2414 }
2415 
2416 /* oris */
2417 static void gen_oris(DisasContext *ctx)
2418 {
2419     target_ulong uimm = UIMM(ctx->opcode);
2420 
2421     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2422         /* NOP */
2423         return;
2424     }
2425     tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2426                    uimm << 16);
2427 }
2428 
2429 /* xori */
2430 static void gen_xori(DisasContext *ctx)
2431 {
2432     target_ulong uimm = UIMM(ctx->opcode);
2433 
2434     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2435         /* NOP */
2436         return;
2437     }
2438     tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2439 }
2440 
2441 /* xoris */
2442 static void gen_xoris(DisasContext *ctx)
2443 {
2444     target_ulong uimm = UIMM(ctx->opcode);
2445 
2446     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2447         /* NOP */
2448         return;
2449     }
2450     tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2451                     uimm << 16);
2452 }
2453 
2454 /* popcntb : PowerPC 2.03 specification */
2455 static void gen_popcntb(DisasContext *ctx)
2456 {
2457     gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2458 }
2459 
2460 static void gen_popcntw(DisasContext *ctx)
2461 {
2462 #if defined(TARGET_PPC64)
2463     gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2464 #else
2465     tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2466 #endif
2467 }
2468 
2469 #if defined(TARGET_PPC64)
2470 /* popcntd: PowerPC 2.06 specification */
2471 static void gen_popcntd(DisasContext *ctx)
2472 {
2473     tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2474 }
2475 #endif
2476 
2477 /* prtyw: PowerPC 2.05 specification */
2478 static void gen_prtyw(DisasContext *ctx)
2479 {
2480     TCGv ra = cpu_gpr[rA(ctx->opcode)];
2481     TCGv rs = cpu_gpr[rS(ctx->opcode)];
2482     TCGv t0 = tcg_temp_new();
2483     tcg_gen_shri_tl(t0, rs, 16);
2484     tcg_gen_xor_tl(ra, rs, t0);
2485     tcg_gen_shri_tl(t0, ra, 8);
2486     tcg_gen_xor_tl(ra, ra, t0);
2487     tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
2488 }
2489 
2490 #if defined(TARGET_PPC64)
2491 /* prtyd: PowerPC 2.05 specification */
2492 static void gen_prtyd(DisasContext *ctx)
2493 {
2494     TCGv ra = cpu_gpr[rA(ctx->opcode)];
2495     TCGv rs = cpu_gpr[rS(ctx->opcode)];
2496     TCGv t0 = tcg_temp_new();
2497     tcg_gen_shri_tl(t0, rs, 32);
2498     tcg_gen_xor_tl(ra, rs, t0);
2499     tcg_gen_shri_tl(t0, ra, 16);
2500     tcg_gen_xor_tl(ra, ra, t0);
2501     tcg_gen_shri_tl(t0, ra, 8);
2502     tcg_gen_xor_tl(ra, ra, t0);
2503     tcg_gen_andi_tl(ra, ra, 1);
2504 }
2505 #endif
2506 
2507 #if defined(TARGET_PPC64)
2508 /* bpermd */
2509 static void gen_bpermd(DisasContext *ctx)
2510 {
2511     gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
2512                       cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2513 }
2514 #endif
2515 
2516 #if defined(TARGET_PPC64)
2517 /* extsw & extsw. */
2518 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
2519 
2520 /* cntlzd */
2521 static void gen_cntlzd(DisasContext *ctx)
2522 {
2523     tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2524     if (unlikely(Rc(ctx->opcode) != 0)) {
2525         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2526     }
2527 }
2528 
2529 /* cnttzd */
2530 static void gen_cnttzd(DisasContext *ctx)
2531 {
2532     tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2533     if (unlikely(Rc(ctx->opcode) != 0)) {
2534         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2535     }
2536 }
2537 
2538 /* darn */
2539 static void gen_darn(DisasContext *ctx)
2540 {
2541     int l = L(ctx->opcode);
2542 
2543     if (l > 2) {
2544         tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
2545     } else {
2546         translator_io_start(&ctx->base);
2547         if (l == 0) {
2548             gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
2549         } else {
2550             /* Return 64-bit random for both CRN and RRN */
2551             gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
2552         }
2553     }
2554 }
2555 #endif
2556 
2557 /***                             Integer rotate                            ***/
2558 
2559 /* rlwimi & rlwimi. */
2560 static void gen_rlwimi(DisasContext *ctx)
2561 {
2562     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2563     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2564     uint32_t sh = SH(ctx->opcode);
2565     uint32_t mb = MB(ctx->opcode);
2566     uint32_t me = ME(ctx->opcode);
2567 
2568     if (sh == (31 - me) && mb <= me) {
2569         tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2570     } else {
2571         target_ulong mask;
2572         bool mask_in_32b = true;
2573         TCGv t1;
2574 
2575 #if defined(TARGET_PPC64)
2576         mb += 32;
2577         me += 32;
2578 #endif
2579         mask = MASK(mb, me);
2580 
2581 #if defined(TARGET_PPC64)
2582         if (mask > 0xffffffffu) {
2583             mask_in_32b = false;
2584         }
2585 #endif
2586         t1 = tcg_temp_new();
2587         if (mask_in_32b) {
2588             TCGv_i32 t0 = tcg_temp_new_i32();
2589             tcg_gen_trunc_tl_i32(t0, t_rs);
2590             tcg_gen_rotli_i32(t0, t0, sh);
2591             tcg_gen_extu_i32_tl(t1, t0);
2592         } else {
2593 #if defined(TARGET_PPC64)
2594             tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
2595             tcg_gen_rotli_i64(t1, t1, sh);
2596 #else
2597             g_assert_not_reached();
2598 #endif
2599         }
2600 
2601         tcg_gen_andi_tl(t1, t1, mask);
2602         tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2603         tcg_gen_or_tl(t_ra, t_ra, t1);
2604     }
2605     if (unlikely(Rc(ctx->opcode) != 0)) {
2606         gen_set_Rc0(ctx, t_ra);
2607     }
2608 }
2609 
2610 /* rlwinm & rlwinm. */
2611 static void gen_rlwinm(DisasContext *ctx)
2612 {
2613     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2614     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2615     int sh = SH(ctx->opcode);
2616     int mb = MB(ctx->opcode);
2617     int me = ME(ctx->opcode);
2618     int len = me - mb + 1;
2619     int rsh = (32 - sh) & 31;
2620 
2621     if (sh != 0 && len > 0 && me == (31 - sh)) {
2622         tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2623     } else if (me == 31 && rsh + len <= 32) {
2624         tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2625     } else {
2626         target_ulong mask;
2627         bool mask_in_32b = true;
2628 #if defined(TARGET_PPC64)
2629         mb += 32;
2630         me += 32;
2631 #endif
2632         mask = MASK(mb, me);
2633 #if defined(TARGET_PPC64)
2634         if (mask > 0xffffffffu) {
2635             mask_in_32b = false;
2636         }
2637 #endif
2638         if (mask_in_32b) {
2639             if (sh == 0) {
2640                 tcg_gen_andi_tl(t_ra, t_rs, mask);
2641             } else {
2642                 TCGv_i32 t0 = tcg_temp_new_i32();
2643                 tcg_gen_trunc_tl_i32(t0, t_rs);
2644                 tcg_gen_rotli_i32(t0, t0, sh);
2645                 tcg_gen_andi_i32(t0, t0, mask);
2646                 tcg_gen_extu_i32_tl(t_ra, t0);
2647             }
2648         } else {
2649 #if defined(TARGET_PPC64)
2650             tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2651             tcg_gen_rotli_i64(t_ra, t_ra, sh);
2652             tcg_gen_andi_i64(t_ra, t_ra, mask);
2653 #else
2654             g_assert_not_reached();
2655 #endif
2656         }
2657     }
2658     if (unlikely(Rc(ctx->opcode) != 0)) {
2659         gen_set_Rc0(ctx, t_ra);
2660     }
2661 }
2662 
2663 /* rlwnm & rlwnm. */
2664 static void gen_rlwnm(DisasContext *ctx)
2665 {
2666     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2667     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2668     TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2669     uint32_t mb = MB(ctx->opcode);
2670     uint32_t me = ME(ctx->opcode);
2671     target_ulong mask;
2672     bool mask_in_32b = true;
2673 
2674 #if defined(TARGET_PPC64)
2675     mb += 32;
2676     me += 32;
2677 #endif
2678     mask = MASK(mb, me);
2679 
2680 #if defined(TARGET_PPC64)
2681     if (mask > 0xffffffffu) {
2682         mask_in_32b = false;
2683     }
2684 #endif
2685     if (mask_in_32b) {
2686         TCGv_i32 t0 = tcg_temp_new_i32();
2687         TCGv_i32 t1 = tcg_temp_new_i32();
2688         tcg_gen_trunc_tl_i32(t0, t_rb);
2689         tcg_gen_trunc_tl_i32(t1, t_rs);
2690         tcg_gen_andi_i32(t0, t0, 0x1f);
2691         tcg_gen_rotl_i32(t1, t1, t0);
2692         tcg_gen_extu_i32_tl(t_ra, t1);
2693     } else {
2694 #if defined(TARGET_PPC64)
2695         TCGv_i64 t0 = tcg_temp_new_i64();
2696         tcg_gen_andi_i64(t0, t_rb, 0x1f);
2697         tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2698         tcg_gen_rotl_i64(t_ra, t_ra, t0);
2699 #else
2700         g_assert_not_reached();
2701 #endif
2702     }
2703 
2704     tcg_gen_andi_tl(t_ra, t_ra, mask);
2705 
2706     if (unlikely(Rc(ctx->opcode) != 0)) {
2707         gen_set_Rc0(ctx, t_ra);
2708     }
2709 }
2710 
2711 #if defined(TARGET_PPC64)
2712 #define GEN_PPC64_R2(name, opc1, opc2)                                        \
2713 static void glue(gen_, name##0)(DisasContext *ctx)                            \
2714 {                                                                             \
2715     gen_##name(ctx, 0);                                                       \
2716 }                                                                             \
2717                                                                               \
2718 static void glue(gen_, name##1)(DisasContext *ctx)                            \
2719 {                                                                             \
2720     gen_##name(ctx, 1);                                                       \
2721 }
2722 #define GEN_PPC64_R4(name, opc1, opc2)                                        \
2723 static void glue(gen_, name##0)(DisasContext *ctx)                            \
2724 {                                                                             \
2725     gen_##name(ctx, 0, 0);                                                    \
2726 }                                                                             \
2727                                                                               \
2728 static void glue(gen_, name##1)(DisasContext *ctx)                            \
2729 {                                                                             \
2730     gen_##name(ctx, 0, 1);                                                    \
2731 }                                                                             \
2732                                                                               \
2733 static void glue(gen_, name##2)(DisasContext *ctx)                            \
2734 {                                                                             \
2735     gen_##name(ctx, 1, 0);                                                    \
2736 }                                                                             \
2737                                                                               \
2738 static void glue(gen_, name##3)(DisasContext *ctx)                            \
2739 {                                                                             \
2740     gen_##name(ctx, 1, 1);                                                    \
2741 }
2742 
2743 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2744 {
2745     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2746     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2747     int len = me - mb + 1;
2748     int rsh = (64 - sh) & 63;
2749 
2750     if (sh != 0 && len > 0 && me == (63 - sh)) {
2751         tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2752     } else if (me == 63 && rsh + len <= 64) {
2753         tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2754     } else {
2755         tcg_gen_rotli_tl(t_ra, t_rs, sh);
2756         tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2757     }
2758     if (unlikely(Rc(ctx->opcode) != 0)) {
2759         gen_set_Rc0(ctx, t_ra);
2760     }
2761 }
2762 
2763 /* rldicl - rldicl. */
2764 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2765 {
2766     uint32_t sh, mb;
2767 
2768     sh = SH(ctx->opcode) | (shn << 5);
2769     mb = MB(ctx->opcode) | (mbn << 5);
2770     gen_rldinm(ctx, mb, 63, sh);
2771 }
2772 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2773 
2774 /* rldicr - rldicr. */
2775 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2776 {
2777     uint32_t sh, me;
2778 
2779     sh = SH(ctx->opcode) | (shn << 5);
2780     me = MB(ctx->opcode) | (men << 5);
2781     gen_rldinm(ctx, 0, me, sh);
2782 }
2783 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2784 
2785 /* rldic - rldic. */
2786 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2787 {
2788     uint32_t sh, mb;
2789 
2790     sh = SH(ctx->opcode) | (shn << 5);
2791     mb = MB(ctx->opcode) | (mbn << 5);
2792     gen_rldinm(ctx, mb, 63 - sh, sh);
2793 }
2794 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2795 
2796 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2797 {
2798     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2799     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2800     TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2801     TCGv t0;
2802 
2803     t0 = tcg_temp_new();
2804     tcg_gen_andi_tl(t0, t_rb, 0x3f);
2805     tcg_gen_rotl_tl(t_ra, t_rs, t0);
2806 
2807     tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2808     if (unlikely(Rc(ctx->opcode) != 0)) {
2809         gen_set_Rc0(ctx, t_ra);
2810     }
2811 }
2812 
2813 /* rldcl - rldcl. */
2814 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2815 {
2816     uint32_t mb;
2817 
2818     mb = MB(ctx->opcode) | (mbn << 5);
2819     gen_rldnm(ctx, mb, 63);
2820 }
2821 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2822 
2823 /* rldcr - rldcr. */
2824 static inline void gen_rldcr(DisasContext *ctx, int men)
2825 {
2826     uint32_t me;
2827 
2828     me = MB(ctx->opcode) | (men << 5);
2829     gen_rldnm(ctx, 0, me);
2830 }
2831 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2832 
2833 /* rldimi - rldimi. */
2834 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2835 {
2836     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2837     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2838     uint32_t sh = SH(ctx->opcode) | (shn << 5);
2839     uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2840     uint32_t me = 63 - sh;
2841 
2842     if (mb <= me) {
2843         tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2844     } else {
2845         target_ulong mask = MASK(mb, me);
2846         TCGv t1 = tcg_temp_new();
2847 
2848         tcg_gen_rotli_tl(t1, t_rs, sh);
2849         tcg_gen_andi_tl(t1, t1, mask);
2850         tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2851         tcg_gen_or_tl(t_ra, t_ra, t1);
2852     }
2853     if (unlikely(Rc(ctx->opcode) != 0)) {
2854         gen_set_Rc0(ctx, t_ra);
2855     }
2856 }
2857 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2858 #endif
2859 
2860 /***                             Integer shift                             ***/
2861 
2862 /* slw & slw. */
2863 static void gen_slw(DisasContext *ctx)
2864 {
2865     TCGv t0, t1;
2866 
2867     t0 = tcg_temp_new();
2868     /* AND rS with a mask that is 0 when rB >= 0x20 */
2869 #if defined(TARGET_PPC64)
2870     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2871     tcg_gen_sari_tl(t0, t0, 0x3f);
2872 #else
2873     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2874     tcg_gen_sari_tl(t0, t0, 0x1f);
2875 #endif
2876     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2877     t1 = tcg_temp_new();
2878     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2879     tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2880     tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2881     if (unlikely(Rc(ctx->opcode) != 0)) {
2882         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2883     }
2884 }
2885 
2886 /* sraw & sraw. */
2887 static void gen_sraw(DisasContext *ctx)
2888 {
2889     gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2890                     cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2891     if (unlikely(Rc(ctx->opcode) != 0)) {
2892         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2893     }
2894 }
2895 
2896 /* srawi & srawi. */
2897 static void gen_srawi(DisasContext *ctx)
2898 {
2899     int sh = SH(ctx->opcode);
2900     TCGv dst = cpu_gpr[rA(ctx->opcode)];
2901     TCGv src = cpu_gpr[rS(ctx->opcode)];
2902     if (sh == 0) {
2903         tcg_gen_ext32s_tl(dst, src);
2904         tcg_gen_movi_tl(cpu_ca, 0);
2905         if (is_isa300(ctx)) {
2906             tcg_gen_movi_tl(cpu_ca32, 0);
2907         }
2908     } else {
2909         TCGv t0;
2910         tcg_gen_ext32s_tl(dst, src);
2911         tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2912         t0 = tcg_temp_new();
2913         tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2914         tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2915         tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2916         if (is_isa300(ctx)) {
2917             tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2918         }
2919         tcg_gen_sari_tl(dst, dst, sh);
2920     }
2921     if (unlikely(Rc(ctx->opcode) != 0)) {
2922         gen_set_Rc0(ctx, dst);
2923     }
2924 }
2925 
2926 /* srw & srw. */
2927 static void gen_srw(DisasContext *ctx)
2928 {
2929     TCGv t0, t1;
2930 
2931     t0 = tcg_temp_new();
2932     /* AND rS with a mask that is 0 when rB >= 0x20 */
2933 #if defined(TARGET_PPC64)
2934     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2935     tcg_gen_sari_tl(t0, t0, 0x3f);
2936 #else
2937     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2938     tcg_gen_sari_tl(t0, t0, 0x1f);
2939 #endif
2940     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2941     tcg_gen_ext32u_tl(t0, t0);
2942     t1 = tcg_temp_new();
2943     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2944     tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2945     if (unlikely(Rc(ctx->opcode) != 0)) {
2946         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2947     }
2948 }
2949 
2950 #if defined(TARGET_PPC64)
2951 /* sld & sld. */
2952 static void gen_sld(DisasContext *ctx)
2953 {
2954     TCGv t0, t1;
2955 
2956     t0 = tcg_temp_new();
2957     /* AND rS with a mask that is 0 when rB >= 0x40 */
2958     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2959     tcg_gen_sari_tl(t0, t0, 0x3f);
2960     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2961     t1 = tcg_temp_new();
2962     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2963     tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2964     if (unlikely(Rc(ctx->opcode) != 0)) {
2965         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2966     }
2967 }
2968 
2969 /* srad & srad. */
2970 static void gen_srad(DisasContext *ctx)
2971 {
2972     gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2973                     cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2974     if (unlikely(Rc(ctx->opcode) != 0)) {
2975         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2976     }
2977 }
2978 /* sradi & sradi. */
2979 static inline void gen_sradi(DisasContext *ctx, int n)
2980 {
2981     int sh = SH(ctx->opcode) + (n << 5);
2982     TCGv dst = cpu_gpr[rA(ctx->opcode)];
2983     TCGv src = cpu_gpr[rS(ctx->opcode)];
2984     if (sh == 0) {
2985         tcg_gen_mov_tl(dst, src);
2986         tcg_gen_movi_tl(cpu_ca, 0);
2987         if (is_isa300(ctx)) {
2988             tcg_gen_movi_tl(cpu_ca32, 0);
2989         }
2990     } else {
2991         TCGv t0;
2992         tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2993         t0 = tcg_temp_new();
2994         tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2995         tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2996         tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2997         if (is_isa300(ctx)) {
2998             tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2999         }
3000         tcg_gen_sari_tl(dst, src, sh);
3001     }
3002     if (unlikely(Rc(ctx->opcode) != 0)) {
3003         gen_set_Rc0(ctx, dst);
3004     }
3005 }
3006 
3007 static void gen_sradi0(DisasContext *ctx)
3008 {
3009     gen_sradi(ctx, 0);
3010 }
3011 
3012 static void gen_sradi1(DisasContext *ctx)
3013 {
3014     gen_sradi(ctx, 1);
3015 }
3016 
3017 /* extswsli & extswsli. */
3018 static inline void gen_extswsli(DisasContext *ctx, int n)
3019 {
3020     int sh = SH(ctx->opcode) + (n << 5);
3021     TCGv dst = cpu_gpr[rA(ctx->opcode)];
3022     TCGv src = cpu_gpr[rS(ctx->opcode)];
3023 
3024     tcg_gen_ext32s_tl(dst, src);
3025     tcg_gen_shli_tl(dst, dst, sh);
3026     if (unlikely(Rc(ctx->opcode) != 0)) {
3027         gen_set_Rc0(ctx, dst);
3028     }
3029 }
3030 
3031 static void gen_extswsli0(DisasContext *ctx)
3032 {
3033     gen_extswsli(ctx, 0);
3034 }
3035 
3036 static void gen_extswsli1(DisasContext *ctx)
3037 {
3038     gen_extswsli(ctx, 1);
3039 }
3040 
3041 /* srd & srd. */
3042 static void gen_srd(DisasContext *ctx)
3043 {
3044     TCGv t0, t1;
3045 
3046     t0 = tcg_temp_new();
3047     /* AND rS with a mask that is 0 when rB >= 0x40 */
3048     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
3049     tcg_gen_sari_tl(t0, t0, 0x3f);
3050     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3051     t1 = tcg_temp_new();
3052     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
3053     tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3054     if (unlikely(Rc(ctx->opcode) != 0)) {
3055         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3056     }
3057 }
3058 #endif
3059 
3060 /***                           Addressing modes                            ***/
3061 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
3062 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
3063                                       target_long maskl)
3064 {
3065     target_long simm = SIMM(ctx->opcode);
3066 
3067     simm &= ~maskl;
3068     if (rA(ctx->opcode) == 0) {
3069         if (NARROW_MODE(ctx)) {
3070             simm = (uint32_t)simm;
3071         }
3072         tcg_gen_movi_tl(EA, simm);
3073     } else if (likely(simm != 0)) {
3074         tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
3075         if (NARROW_MODE(ctx)) {
3076             tcg_gen_ext32u_tl(EA, EA);
3077         }
3078     } else {
3079         if (NARROW_MODE(ctx)) {
3080             tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3081         } else {
3082             tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3083         }
3084     }
3085 }
3086 
3087 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
3088 {
3089     if (rA(ctx->opcode) == 0) {
3090         if (NARROW_MODE(ctx)) {
3091             tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3092         } else {
3093             tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3094         }
3095     } else {
3096         tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3097         if (NARROW_MODE(ctx)) {
3098             tcg_gen_ext32u_tl(EA, EA);
3099         }
3100     }
3101 }
3102 
3103 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
3104 {
3105     if (rA(ctx->opcode) == 0) {
3106         tcg_gen_movi_tl(EA, 0);
3107     } else if (NARROW_MODE(ctx)) {
3108         tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3109     } else {
3110         tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3111     }
3112 }
3113 
3114 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
3115                                 target_long val)
3116 {
3117     tcg_gen_addi_tl(ret, arg1, val);
3118     if (NARROW_MODE(ctx)) {
3119         tcg_gen_ext32u_tl(ret, ret);
3120     }
3121 }
3122 
3123 static inline void gen_align_no_le(DisasContext *ctx)
3124 {
3125     gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
3126                       (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
3127 }
3128 
3129 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ)
3130 {
3131     TCGv ea = tcg_temp_new();
3132     if (ra) {
3133         tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
3134     } else {
3135         tcg_gen_mov_tl(ea, displ);
3136     }
3137     if (NARROW_MODE(ctx)) {
3138         tcg_gen_ext32u_tl(ea, ea);
3139     }
3140     return ea;
3141 }
3142 
3143 /***                             Integer load                              ***/
3144 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
3145 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
3146 
3147 #define GEN_QEMU_LOAD_TL(ldop, op)                                      \
3148 static void glue(gen_qemu_, ldop)(DisasContext *ctx,                    \
3149                                   TCGv val,                             \
3150                                   TCGv addr)                            \
3151 {                                                                       \
3152     tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op);                    \
3153 }
3154 
3155 GEN_QEMU_LOAD_TL(ld8u,  DEF_MEMOP(MO_UB))
3156 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
3157 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
3158 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
3159 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
3160 
3161 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
3162 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
3163 
3164 #define GEN_QEMU_LOAD_64(ldop, op)                                  \
3165 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx,    \
3166                                              TCGv_i64 val,          \
3167                                              TCGv addr)             \
3168 {                                                                   \
3169     tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op);               \
3170 }
3171 
3172 GEN_QEMU_LOAD_64(ld8u,  DEF_MEMOP(MO_UB))
3173 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
3174 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
3175 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
3176 GEN_QEMU_LOAD_64(ld64,  DEF_MEMOP(MO_UQ))
3177 
3178 #if defined(TARGET_PPC64)
3179 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ))
3180 #endif
3181 
3182 #define GEN_QEMU_STORE_TL(stop, op)                                     \
3183 static void glue(gen_qemu_, stop)(DisasContext *ctx,                    \
3184                                   TCGv val,                             \
3185                                   TCGv addr)                            \
3186 {                                                                       \
3187     tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op);                    \
3188 }
3189 
3190 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
3191 GEN_QEMU_STORE_TL(st8,  DEF_MEMOP(MO_UB))
3192 #endif
3193 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
3194 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
3195 
3196 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
3197 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
3198 
3199 #define GEN_QEMU_STORE_64(stop, op)                               \
3200 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx,  \
3201                                               TCGv_i64 val,       \
3202                                               TCGv addr)          \
3203 {                                                                 \
3204     tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op);             \
3205 }
3206 
3207 GEN_QEMU_STORE_64(st8,  DEF_MEMOP(MO_UB))
3208 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
3209 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
3210 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ))
3211 
3212 #if defined(TARGET_PPC64)
3213 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))
3214 #endif
3215 
3216 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk)                   \
3217 static void glue(gen_, name##x)(DisasContext *ctx)                            \
3218 {                                                                             \
3219     TCGv EA;                                                                  \
3220     chk(ctx);                                                                 \
3221     gen_set_access_type(ctx, ACCESS_INT);                                     \
3222     EA = tcg_temp_new();                                                      \
3223     gen_addr_reg_index(ctx, EA);                                              \
3224     gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
3225 }
3226 
3227 #define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
3228     GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3229 
3230 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type)                            \
3231     GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3232 
3233 #define GEN_LDEPX(name, ldop, opc2, opc3)                                     \
3234 static void glue(gen_, name##epx)(DisasContext *ctx)                          \
3235 {                                                                             \
3236     TCGv EA;                                                                  \
3237     CHK_SV(ctx);                                                              \
3238     gen_set_access_type(ctx, ACCESS_INT);                                     \
3239     EA = tcg_temp_new();                                                      \
3240     gen_addr_reg_index(ctx, EA);                                              \
3241     tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
3242 }
3243 
3244 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
3245 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
3246 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
3247 #if defined(TARGET_PPC64)
3248 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)
3249 #endif
3250 
3251 #if defined(TARGET_PPC64)
3252 /* CI load/store variants */
3253 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
3254 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
3255 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
3256 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
3257 #endif
3258 
3259 /***                              Integer store                            ***/
3260 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk)                   \
3261 static void glue(gen_, name##x)(DisasContext *ctx)                            \
3262 {                                                                             \
3263     TCGv EA;                                                                  \
3264     chk(ctx);                                                                 \
3265     gen_set_access_type(ctx, ACCESS_INT);                                     \
3266     EA = tcg_temp_new();                                                      \
3267     gen_addr_reg_index(ctx, EA);                                              \
3268     gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
3269 }
3270 #define GEN_STX(name, stop, opc2, opc3, type)                                 \
3271     GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3272 
3273 #define GEN_STX_HVRM(name, stop, opc2, opc3, type)                            \
3274     GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3275 
3276 #define GEN_STEPX(name, stop, opc2, opc3)                                     \
3277 static void glue(gen_, name##epx)(DisasContext *ctx)                          \
3278 {                                                                             \
3279     TCGv EA;                                                                  \
3280     CHK_SV(ctx);                                                              \
3281     gen_set_access_type(ctx, ACCESS_INT);                                     \
3282     EA = tcg_temp_new();                                                      \
3283     gen_addr_reg_index(ctx, EA);                                              \
3284     tcg_gen_qemu_st_tl(                                                       \
3285         cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop);              \
3286 }
3287 
3288 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
3289 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
3290 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
3291 #if defined(TARGET_PPC64)
3292 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04)
3293 #endif
3294 
3295 #if defined(TARGET_PPC64)
3296 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
3297 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
3298 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
3299 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
3300 #endif
3301 /***                Integer load and store with byte reverse               ***/
3302 
3303 /* lhbrx */
3304 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3305 
3306 /* lwbrx */
3307 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3308 
3309 #if defined(TARGET_PPC64)
3310 /* ldbrx */
3311 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
3312 /* stdbrx */
3313 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
3314 #endif  /* TARGET_PPC64 */
3315 
3316 /* sthbrx */
3317 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3318 /* stwbrx */
3319 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3320 
3321 /***                    Integer load and store multiple                    ***/
3322 
3323 /* lmw */
3324 static void gen_lmw(DisasContext *ctx)
3325 {
3326     TCGv t0;
3327     TCGv_i32 t1;
3328 
3329     if (ctx->le_mode) {
3330         gen_align_no_le(ctx);
3331         return;
3332     }
3333     gen_set_access_type(ctx, ACCESS_INT);
3334     t0 = tcg_temp_new();
3335     t1 = tcg_constant_i32(rD(ctx->opcode));
3336     gen_addr_imm_index(ctx, t0, 0);
3337     gen_helper_lmw(cpu_env, t0, t1);
3338 }
3339 
3340 /* stmw */
3341 static void gen_stmw(DisasContext *ctx)
3342 {
3343     TCGv t0;
3344     TCGv_i32 t1;
3345 
3346     if (ctx->le_mode) {
3347         gen_align_no_le(ctx);
3348         return;
3349     }
3350     gen_set_access_type(ctx, ACCESS_INT);
3351     t0 = tcg_temp_new();
3352     t1 = tcg_constant_i32(rS(ctx->opcode));
3353     gen_addr_imm_index(ctx, t0, 0);
3354     gen_helper_stmw(cpu_env, t0, t1);
3355 }
3356 
3357 /***                    Integer load and store strings                     ***/
3358 
3359 /* lswi */
3360 /*
3361  * PowerPC32 specification says we must generate an exception if rA is
3362  * in the range of registers to be loaded.  In an other hand, IBM says
3363  * this is valid, but rA won't be loaded.  For now, I'll follow the
3364  * spec...
3365  */
3366 static void gen_lswi(DisasContext *ctx)
3367 {
3368     TCGv t0;
3369     TCGv_i32 t1, t2;
3370     int nb = NB(ctx->opcode);
3371     int start = rD(ctx->opcode);
3372     int ra = rA(ctx->opcode);
3373     int nr;
3374 
3375     if (ctx->le_mode) {
3376         gen_align_no_le(ctx);
3377         return;
3378     }
3379     if (nb == 0) {
3380         nb = 32;
3381     }
3382     nr = DIV_ROUND_UP(nb, 4);
3383     if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3384         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3385         return;
3386     }
3387     gen_set_access_type(ctx, ACCESS_INT);
3388     t0 = tcg_temp_new();
3389     gen_addr_register(ctx, t0);
3390     t1 = tcg_constant_i32(nb);
3391     t2 = tcg_constant_i32(start);
3392     gen_helper_lsw(cpu_env, t0, t1, t2);
3393 }
3394 
3395 /* lswx */
3396 static void gen_lswx(DisasContext *ctx)
3397 {
3398     TCGv t0;
3399     TCGv_i32 t1, t2, t3;
3400 
3401     if (ctx->le_mode) {
3402         gen_align_no_le(ctx);
3403         return;
3404     }
3405     gen_set_access_type(ctx, ACCESS_INT);
3406     t0 = tcg_temp_new();
3407     gen_addr_reg_index(ctx, t0);
3408     t1 = tcg_constant_i32(rD(ctx->opcode));
3409     t2 = tcg_constant_i32(rA(ctx->opcode));
3410     t3 = tcg_constant_i32(rB(ctx->opcode));
3411     gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3412 }
3413 
3414 /* stswi */
3415 static void gen_stswi(DisasContext *ctx)
3416 {
3417     TCGv t0;
3418     TCGv_i32 t1, t2;
3419     int nb = NB(ctx->opcode);
3420 
3421     if (ctx->le_mode) {
3422         gen_align_no_le(ctx);
3423         return;
3424     }
3425     gen_set_access_type(ctx, ACCESS_INT);
3426     t0 = tcg_temp_new();
3427     gen_addr_register(ctx, t0);
3428     if (nb == 0) {
3429         nb = 32;
3430     }
3431     t1 = tcg_constant_i32(nb);
3432     t2 = tcg_constant_i32(rS(ctx->opcode));
3433     gen_helper_stsw(cpu_env, t0, t1, t2);
3434 }
3435 
3436 /* stswx */
3437 static void gen_stswx(DisasContext *ctx)
3438 {
3439     TCGv t0;
3440     TCGv_i32 t1, t2;
3441 
3442     if (ctx->le_mode) {
3443         gen_align_no_le(ctx);
3444         return;
3445     }
3446     gen_set_access_type(ctx, ACCESS_INT);
3447     t0 = tcg_temp_new();
3448     gen_addr_reg_index(ctx, t0);
3449     t1 = tcg_temp_new_i32();
3450     tcg_gen_trunc_tl_i32(t1, cpu_xer);
3451     tcg_gen_andi_i32(t1, t1, 0x7F);
3452     t2 = tcg_constant_i32(rS(ctx->opcode));
3453     gen_helper_stsw(cpu_env, t0, t1, t2);
3454 }
3455 
3456 /***                        Memory synchronisation                         ***/
3457 /* eieio */
3458 static void gen_eieio(DisasContext *ctx)
3459 {
3460     TCGBar bar = TCG_MO_ALL;
3461 
3462     /*
3463      * eieio has complex semanitcs. It provides memory ordering between
3464      * operations in the set:
3465      * - loads from CI memory.
3466      * - stores to CI memory.
3467      * - stores to WT memory.
3468      *
3469      * It separately also orders memory for operations in the set:
3470      * - stores to cacheble memory.
3471      *
3472      * It also serializes instructions:
3473      * - dcbt and dcbst.
3474      *
3475      * It separately serializes:
3476      * - tlbie and tlbsync.
3477      *
3478      * And separately serializes:
3479      * - slbieg, slbiag, and slbsync.
3480      *
3481      * The end result is that CI memory ordering requires TCG_MO_ALL
3482      * and it is not possible to special-case more relaxed ordering for
3483      * cacheable accesses. TCG_BAR_SC is required to provide this
3484      * serialization.
3485      */
3486 
3487     /*
3488      * POWER9 has a eieio instruction variant using bit 6 as a hint to
3489      * tell the CPU it is a store-forwarding barrier.
3490      */
3491     if (ctx->opcode & 0x2000000) {
3492         /*
3493          * ISA says that "Reserved fields in instructions are ignored
3494          * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3495          * as this is not an instruction software should be using,
3496          * complain to the user.
3497          */
3498         if (!(ctx->insns_flags2 & PPC2_ISA300)) {
3499             qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
3500                           TARGET_FMT_lx "\n", ctx->cia);
3501         } else {
3502             bar = TCG_MO_ST_LD;
3503         }
3504     }
3505 
3506     tcg_gen_mb(bar | TCG_BAR_SC);
3507 }
3508 
3509 #if !defined(CONFIG_USER_ONLY)
3510 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
3511 {
3512     TCGv_i32 t;
3513     TCGLabel *l;
3514 
3515     if (!ctx->lazy_tlb_flush) {
3516         return;
3517     }
3518     l = gen_new_label();
3519     t = tcg_temp_new_i32();
3520     tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3521     tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3522     if (global) {
3523         gen_helper_check_tlb_flush_global(cpu_env);
3524     } else {
3525         gen_helper_check_tlb_flush_local(cpu_env);
3526     }
3527     gen_set_label(l);
3528 }
3529 #else
3530 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3531 #endif
3532 
3533 /* isync */
3534 static void gen_isync(DisasContext *ctx)
3535 {
3536     /*
3537      * We need to check for a pending TLB flush. This can only happen in
3538      * kernel mode however so check MSR_PR
3539      */
3540     if (!ctx->pr) {
3541         gen_check_tlb_flush(ctx, false);
3542     }
3543     tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3544     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
3545 }
3546 
3547 #define MEMOP_GET_SIZE(x)  (1 << ((x) & MO_SIZE))
3548 
3549 static void gen_load_locked(DisasContext *ctx, MemOp memop)
3550 {
3551     TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3552     TCGv t0 = tcg_temp_new();
3553 
3554     gen_set_access_type(ctx, ACCESS_RES);
3555     gen_addr_reg_index(ctx, t0);
3556     tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3557     tcg_gen_mov_tl(cpu_reserve, t0);
3558     tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop));
3559     tcg_gen_mov_tl(cpu_reserve_val, gpr);
3560 }
3561 
3562 #define LARX(name, memop)                  \
3563 static void gen_##name(DisasContext *ctx)  \
3564 {                                          \
3565     gen_load_locked(ctx, memop);           \
3566 }
3567 
3568 /* lwarx */
3569 LARX(lbarx, DEF_MEMOP(MO_UB))
3570 LARX(lharx, DEF_MEMOP(MO_UW))
3571 LARX(lwarx, DEF_MEMOP(MO_UL))
3572 
3573 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
3574                                       TCGv EA, TCGCond cond, int addend)
3575 {
3576     TCGv t = tcg_temp_new();
3577     TCGv t2 = tcg_temp_new();
3578     TCGv u = tcg_temp_new();
3579 
3580     tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3581     tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
3582     tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
3583     tcg_gen_addi_tl(u, t, addend);
3584 
3585     /* E.g. for fetch and increment bounded... */
3586     /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3587     tcg_gen_movcond_tl(cond, u, t, t2, u, t);
3588     tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
3589 
3590     /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3591     tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
3592     tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
3593 }
3594 
3595 static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
3596 {
3597     uint32_t gpr_FC = FC(ctx->opcode);
3598     TCGv EA = tcg_temp_new();
3599     int rt = rD(ctx->opcode);
3600     bool need_serial;
3601     TCGv src, dst;
3602 
3603     gen_addr_register(ctx, EA);
3604     dst = cpu_gpr[rt];
3605     src = cpu_gpr[(rt + 1) & 31];
3606 
3607     need_serial = false;
3608     memop |= MO_ALIGN;
3609     switch (gpr_FC) {
3610     case 0: /* Fetch and add */
3611         tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
3612         break;
3613     case 1: /* Fetch and xor */
3614         tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
3615         break;
3616     case 2: /* Fetch and or */
3617         tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
3618         break;
3619     case 3: /* Fetch and 'and' */
3620         tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
3621         break;
3622     case 4:  /* Fetch and max unsigned */
3623         tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
3624         break;
3625     case 5:  /* Fetch and max signed */
3626         tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
3627         break;
3628     case 6:  /* Fetch and min unsigned */
3629         tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
3630         break;
3631     case 7:  /* Fetch and min signed */
3632         tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
3633         break;
3634     case 8: /* Swap */
3635         tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
3636         break;
3637 
3638     case 16: /* Compare and swap not equal */
3639         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3640             need_serial = true;
3641         } else {
3642             TCGv t0 = tcg_temp_new();
3643             TCGv t1 = tcg_temp_new();
3644 
3645             tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
3646             if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
3647                 tcg_gen_mov_tl(t1, src);
3648             } else {
3649                 tcg_gen_ext32u_tl(t1, src);
3650             }
3651             tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
3652                                cpu_gpr[(rt + 2) & 31], t0);
3653             tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
3654             tcg_gen_mov_tl(dst, t0);
3655         }
3656         break;
3657 
3658     case 24: /* Fetch and increment bounded */
3659         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3660             need_serial = true;
3661         } else {
3662             gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
3663         }
3664         break;
3665     case 25: /* Fetch and increment equal */
3666         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3667             need_serial = true;
3668         } else {
3669             gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
3670         }
3671         break;
3672     case 28: /* Fetch and decrement bounded */
3673         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3674             need_serial = true;
3675         } else {
3676             gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
3677         }
3678         break;
3679 
3680     default:
3681         /* invoke data storage error handler */
3682         gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3683     }
3684 
3685     if (need_serial) {
3686         /* Restart with exclusive lock.  */
3687         gen_helper_exit_atomic(cpu_env);
3688         ctx->base.is_jmp = DISAS_NORETURN;
3689     }
3690 }
3691 
3692 static void gen_lwat(DisasContext *ctx)
3693 {
3694     gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
3695 }
3696 
3697 #ifdef TARGET_PPC64
3698 static void gen_ldat(DisasContext *ctx)
3699 {
3700     gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ));
3701 }
3702 #endif
3703 
3704 static void gen_st_atomic(DisasContext *ctx, MemOp memop)
3705 {
3706     uint32_t gpr_FC = FC(ctx->opcode);
3707     TCGv EA = tcg_temp_new();
3708     TCGv src, discard;
3709 
3710     gen_addr_register(ctx, EA);
3711     src = cpu_gpr[rD(ctx->opcode)];
3712     discard = tcg_temp_new();
3713 
3714     memop |= MO_ALIGN;
3715     switch (gpr_FC) {
3716     case 0: /* add and Store */
3717         tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3718         break;
3719     case 1: /* xor and Store */
3720         tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3721         break;
3722     case 2: /* Or and Store */
3723         tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3724         break;
3725     case 3: /* 'and' and Store */
3726         tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3727         break;
3728     case 4:  /* Store max unsigned */
3729         tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3730         break;
3731     case 5:  /* Store max signed */
3732         tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3733         break;
3734     case 6:  /* Store min unsigned */
3735         tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3736         break;
3737     case 7:  /* Store min signed */
3738         tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3739         break;
3740     case 24: /* Store twin  */
3741         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3742             /* Restart with exclusive lock.  */
3743             gen_helper_exit_atomic(cpu_env);
3744             ctx->base.is_jmp = DISAS_NORETURN;
3745         } else {
3746             TCGv t = tcg_temp_new();
3747             TCGv t2 = tcg_temp_new();
3748             TCGv s = tcg_temp_new();
3749             TCGv s2 = tcg_temp_new();
3750             TCGv ea_plus_s = tcg_temp_new();
3751 
3752             tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3753             tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
3754             tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
3755             tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
3756             tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
3757             tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
3758             tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
3759         }
3760         break;
3761     default:
3762         /* invoke data storage error handler */
3763         gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3764     }
3765 }
3766 
3767 static void gen_stwat(DisasContext *ctx)
3768 {
3769     gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
3770 }
3771 
3772 #ifdef TARGET_PPC64
3773 static void gen_stdat(DisasContext *ctx)
3774 {
3775     gen_st_atomic(ctx, DEF_MEMOP(MO_UQ));
3776 }
3777 #endif
3778 
3779 static void gen_conditional_store(DisasContext *ctx, MemOp memop)
3780 {
3781     TCGLabel *lfail;
3782     TCGv EA;
3783     TCGv cr0;
3784     TCGv t0;
3785     int rs = rS(ctx->opcode);
3786 
3787     lfail = gen_new_label();
3788     EA = tcg_temp_new();
3789     cr0 = tcg_temp_new();
3790     t0 = tcg_temp_new();
3791 
3792     tcg_gen_mov_tl(cr0, cpu_so);
3793     gen_set_access_type(ctx, ACCESS_RES);
3794     gen_addr_reg_index(ctx, EA);
3795     tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail);
3796     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail);
3797 
3798     tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3799                               cpu_gpr[rs], ctx->mem_idx,
3800                               DEF_MEMOP(memop) | MO_ALIGN);
3801     tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3802     tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3803     tcg_gen_or_tl(cr0, cr0, t0);
3804 
3805     gen_set_label(lfail);
3806     tcg_gen_trunc_tl_i32(cpu_crf[0], cr0);
3807     tcg_gen_movi_tl(cpu_reserve, -1);
3808 }
3809 
3810 #define STCX(name, memop)                  \
3811 static void gen_##name(DisasContext *ctx)  \
3812 {                                          \
3813     gen_conditional_store(ctx, memop);     \
3814 }
3815 
3816 STCX(stbcx_, DEF_MEMOP(MO_UB))
3817 STCX(sthcx_, DEF_MEMOP(MO_UW))
3818 STCX(stwcx_, DEF_MEMOP(MO_UL))
3819 
3820 #if defined(TARGET_PPC64)
3821 /* ldarx */
3822 LARX(ldarx, DEF_MEMOP(MO_UQ))
3823 /* stdcx. */
3824 STCX(stdcx_, DEF_MEMOP(MO_UQ))
3825 
3826 /* lqarx */
3827 static void gen_lqarx(DisasContext *ctx)
3828 {
3829     int rd = rD(ctx->opcode);
3830     TCGv EA, hi, lo;
3831     TCGv_i128 t16;
3832 
3833     if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3834                  (rd == rB(ctx->opcode)))) {
3835         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3836         return;
3837     }
3838 
3839     gen_set_access_type(ctx, ACCESS_RES);
3840     EA = tcg_temp_new();
3841     gen_addr_reg_index(ctx, EA);
3842 
3843     /* Note that the low part is always in RD+1, even in LE mode.  */
3844     lo = cpu_gpr[rd + 1];
3845     hi = cpu_gpr[rd];
3846 
3847     t16 = tcg_temp_new_i128();
3848     tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN));
3849     tcg_gen_extr_i128_i64(lo, hi, t16);
3850 
3851     tcg_gen_mov_tl(cpu_reserve, EA);
3852     tcg_gen_movi_tl(cpu_reserve_length, 16);
3853     tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
3854     tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
3855 }
3856 
3857 /* stqcx. */
3858 static void gen_stqcx_(DisasContext *ctx)
3859 {
3860     TCGLabel *lfail;
3861     TCGv EA, t0, t1;
3862     TCGv cr0;
3863     TCGv_i128 cmp, val;
3864     int rs = rS(ctx->opcode);
3865 
3866     if (unlikely(rs & 1)) {
3867         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3868         return;
3869     }
3870 
3871     lfail = gen_new_label();
3872     EA = tcg_temp_new();
3873     cr0 = tcg_temp_new();
3874 
3875     tcg_gen_mov_tl(cr0, cpu_so);
3876     gen_set_access_type(ctx, ACCESS_RES);
3877     gen_addr_reg_index(ctx, EA);
3878     tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail);
3879     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail);
3880 
3881     cmp = tcg_temp_new_i128();
3882     val = tcg_temp_new_i128();
3883 
3884     tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val);
3885 
3886     /* Note that the low part is always in RS+1, even in LE mode.  */
3887     tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]);
3888 
3889     tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx,
3890                                 DEF_MEMOP(MO_128 | MO_ALIGN));
3891 
3892     t0 = tcg_temp_new();
3893     t1 = tcg_temp_new();
3894     tcg_gen_extr_i128_i64(t1, t0, val);
3895 
3896     tcg_gen_xor_tl(t1, t1, cpu_reserve_val2);
3897     tcg_gen_xor_tl(t0, t0, cpu_reserve_val);
3898     tcg_gen_or_tl(t0, t0, t1);
3899 
3900     tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0);
3901     tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3902     tcg_gen_or_tl(cr0, cr0, t0);
3903 
3904     gen_set_label(lfail);
3905     tcg_gen_trunc_tl_i32(cpu_crf[0], cr0);
3906     tcg_gen_movi_tl(cpu_reserve, -1);
3907 }
3908 #endif /* defined(TARGET_PPC64) */
3909 
3910 /* sync */
3911 static void gen_sync(DisasContext *ctx)
3912 {
3913     TCGBar bar = TCG_MO_ALL;
3914     uint32_t l = (ctx->opcode >> 21) & 3;
3915 
3916     if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) {
3917         bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST;
3918     }
3919 
3920     /*
3921      * We may need to check for a pending TLB flush.
3922      *
3923      * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3924      *
3925      * Additionally, this can only happen in kernel mode however so
3926      * check MSR_PR as well.
3927      */
3928     if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3929         gen_check_tlb_flush(ctx, true);
3930     }
3931 
3932     tcg_gen_mb(bar | TCG_BAR_SC);
3933 }
3934 
3935 /* wait */
3936 static void gen_wait(DisasContext *ctx)
3937 {
3938     uint32_t wc;
3939 
3940     if (ctx->insns_flags & PPC_WAIT) {
3941         /* v2.03-v2.07 define an older incompatible 'wait' encoding. */
3942 
3943         if (ctx->insns_flags2 & PPC2_PM_ISA206) {
3944             /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */
3945             wc = WC(ctx->opcode);
3946         } else {
3947             wc = 0;
3948         }
3949 
3950     } else if (ctx->insns_flags2 & PPC2_ISA300) {
3951         /* v3.0 defines a new 'wait' encoding. */
3952         wc = WC(ctx->opcode);
3953         if (ctx->insns_flags2 & PPC2_ISA310) {
3954             uint32_t pl = PL(ctx->opcode);
3955 
3956             /* WC 1,2 may be treated as no-op. WC 3 is reserved. */
3957             if (wc == 3) {
3958                 gen_invalid(ctx);
3959                 return;
3960             }
3961 
3962             /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */
3963             if (pl > 0 && wc != 2) {
3964                 gen_invalid(ctx);
3965                 return;
3966             }
3967 
3968         } else { /* ISA300 */
3969             /* WC 1-3 are reserved */
3970             if (wc > 0) {
3971                 gen_invalid(ctx);
3972                 return;
3973             }
3974         }
3975 
3976     } else {
3977         warn_report("wait instruction decoded with wrong ISA flags.");
3978         gen_invalid(ctx);
3979         return;
3980     }
3981 
3982     /*
3983      * wait without WC field or with WC=0 waits for an exception / interrupt
3984      * to occur.
3985      */
3986     if (wc == 0) {
3987         TCGv_i32 t0 = tcg_constant_i32(1);
3988         tcg_gen_st_i32(t0, cpu_env,
3989                        -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3990         /* Stop translation, as the CPU is supposed to sleep from now */
3991         gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3992     }
3993 
3994     /*
3995      * Other wait types must not just wait until an exception occurs because
3996      * ignoring their other wake-up conditions could cause a hang.
3997      *
3998      * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as
3999      * no-ops.
4000      *
4001      * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op.
4002      *
4003      * wc=2 waits for an implementation-specific condition, such could be
4004      * always true, so it can be implemented as a no-op.
4005      *
4006      * For v3.1, wc=1,2 are architected but may be implemented as no-ops.
4007      *
4008      * wc=1 (waitrsv) waits for an exception or a reservation to be lost.
4009      * Reservation-loss may have implementation-specific conditions, so it
4010      * can be implemented as a no-op.
4011      *
4012      * wc=2 waits for an exception or an amount of time to pass. This
4013      * amount is implementation-specific so it can be implemented as a
4014      * no-op.
4015      *
4016      * ISA v3.1 allows for execution to resume "in the rare case of
4017      * an implementation-dependent event", so in any case software must
4018      * not depend on the architected resumption condition to become
4019      * true, so no-op implementations should be architecturally correct
4020      * (if suboptimal).
4021      */
4022 }
4023 
4024 #if defined(TARGET_PPC64)
4025 static void gen_doze(DisasContext *ctx)
4026 {
4027 #if defined(CONFIG_USER_ONLY)
4028     GEN_PRIV(ctx);
4029 #else
4030     TCGv_i32 t;
4031 
4032     CHK_HV(ctx);
4033     translator_io_start(&ctx->base);
4034     t = tcg_constant_i32(PPC_PM_DOZE);
4035     gen_helper_pminsn(cpu_env, t);
4036     /* Stop translation, as the CPU is supposed to sleep from now */
4037     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4038 #endif /* defined(CONFIG_USER_ONLY) */
4039 }
4040 
4041 static void gen_nap(DisasContext *ctx)
4042 {
4043 #if defined(CONFIG_USER_ONLY)
4044     GEN_PRIV(ctx);
4045 #else
4046     TCGv_i32 t;
4047 
4048     CHK_HV(ctx);
4049     translator_io_start(&ctx->base);
4050     t = tcg_constant_i32(PPC_PM_NAP);
4051     gen_helper_pminsn(cpu_env, t);
4052     /* Stop translation, as the CPU is supposed to sleep from now */
4053     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4054 #endif /* defined(CONFIG_USER_ONLY) */
4055 }
4056 
4057 static void gen_stop(DisasContext *ctx)
4058 {
4059 #if defined(CONFIG_USER_ONLY)
4060     GEN_PRIV(ctx);
4061 #else
4062     TCGv_i32 t;
4063 
4064     CHK_HV(ctx);
4065     translator_io_start(&ctx->base);
4066     t = tcg_constant_i32(PPC_PM_STOP);
4067     gen_helper_pminsn(cpu_env, t);
4068     /* Stop translation, as the CPU is supposed to sleep from now */
4069     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4070 #endif /* defined(CONFIG_USER_ONLY) */
4071 }
4072 
4073 static void gen_sleep(DisasContext *ctx)
4074 {
4075 #if defined(CONFIG_USER_ONLY)
4076     GEN_PRIV(ctx);
4077 #else
4078     TCGv_i32 t;
4079 
4080     CHK_HV(ctx);
4081     translator_io_start(&ctx->base);
4082     t = tcg_constant_i32(PPC_PM_SLEEP);
4083     gen_helper_pminsn(cpu_env, t);
4084     /* Stop translation, as the CPU is supposed to sleep from now */
4085     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4086 #endif /* defined(CONFIG_USER_ONLY) */
4087 }
4088 
4089 static void gen_rvwinkle(DisasContext *ctx)
4090 {
4091 #if defined(CONFIG_USER_ONLY)
4092     GEN_PRIV(ctx);
4093 #else
4094     TCGv_i32 t;
4095 
4096     CHK_HV(ctx);
4097     translator_io_start(&ctx->base);
4098     t = tcg_constant_i32(PPC_PM_RVWINKLE);
4099     gen_helper_pminsn(cpu_env, t);
4100     /* Stop translation, as the CPU is supposed to sleep from now */
4101     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4102 #endif /* defined(CONFIG_USER_ONLY) */
4103 }
4104 #endif /* #if defined(TARGET_PPC64) */
4105 
4106 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
4107 {
4108 #if defined(TARGET_PPC64)
4109     if (ctx->has_cfar) {
4110         tcg_gen_movi_tl(cpu_cfar, nip);
4111     }
4112 #endif
4113 }
4114 
4115 #if defined(TARGET_PPC64)
4116 static void pmu_count_insns(DisasContext *ctx)
4117 {
4118     /*
4119      * Do not bother calling the helper if the PMU isn't counting
4120      * instructions.
4121      */
4122     if (!ctx->pmu_insn_cnt) {
4123         return;
4124     }
4125 
4126  #if !defined(CONFIG_USER_ONLY)
4127     TCGLabel *l;
4128     TCGv t0;
4129 
4130     /*
4131      * The PMU insns_inc() helper stops the internal PMU timer if a
4132      * counter overflows happens. In that case, if the guest is
4133      * running with icount and we do not handle it beforehand,
4134      * the helper can trigger a 'bad icount read'.
4135      */
4136     translator_io_start(&ctx->base);
4137 
4138     /* Avoid helper calls when only PMC5-6 are enabled. */
4139     if (!ctx->pmc_other) {
4140         l = gen_new_label();
4141         t0 = tcg_temp_new();
4142 
4143         gen_load_spr(t0, SPR_POWER_PMC5);
4144         tcg_gen_addi_tl(t0, t0, ctx->base.num_insns);
4145         gen_store_spr(SPR_POWER_PMC5, t0);
4146         /* Check for overflow, if it's enabled */
4147         if (ctx->mmcr0_pmcjce) {
4148             tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l);
4149             gen_helper_handle_pmc5_overflow(cpu_env);
4150         }
4151 
4152         gen_set_label(l);
4153     } else {
4154         gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns));
4155     }
4156   #else
4157     /*
4158      * User mode can read (but not write) PMC5 and start/stop
4159      * the PMU via MMCR0_FC. In this case just increment
4160      * PMC5 with base.num_insns.
4161      */
4162     TCGv t0 = tcg_temp_new();
4163 
4164     gen_load_spr(t0, SPR_POWER_PMC5);
4165     tcg_gen_addi_tl(t0, t0, ctx->base.num_insns);
4166     gen_store_spr(SPR_POWER_PMC5, t0);
4167   #endif /* #if !defined(CONFIG_USER_ONLY) */
4168 }
4169 #else
4170 static void pmu_count_insns(DisasContext *ctx)
4171 {
4172     return;
4173 }
4174 #endif /* #if defined(TARGET_PPC64) */
4175 
4176 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
4177 {
4178     if (unlikely(ctx->singlestep_enabled)) {
4179         return false;
4180     }
4181     return translator_use_goto_tb(&ctx->base, dest);
4182 }
4183 
4184 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
4185 {
4186     if (unlikely(ctx->singlestep_enabled)) {
4187         gen_debug_exception(ctx);
4188     } else {
4189         /*
4190          * tcg_gen_lookup_and_goto_ptr will exit the TB if
4191          * CF_NO_GOTO_PTR is set. Count insns now.
4192          */
4193         if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
4194             pmu_count_insns(ctx);
4195         }
4196 
4197         tcg_gen_lookup_and_goto_ptr();
4198     }
4199 }
4200 
4201 /***                                Branch                                 ***/
4202 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4203 {
4204     if (NARROW_MODE(ctx)) {
4205         dest = (uint32_t) dest;
4206     }
4207     if (use_goto_tb(ctx, dest)) {
4208         pmu_count_insns(ctx);
4209         tcg_gen_goto_tb(n);
4210         tcg_gen_movi_tl(cpu_nip, dest & ~3);
4211         tcg_gen_exit_tb(ctx->base.tb, n);
4212     } else {
4213         tcg_gen_movi_tl(cpu_nip, dest & ~3);
4214         gen_lookup_and_goto_ptr(ctx);
4215     }
4216 }
4217 
4218 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
4219 {
4220     if (NARROW_MODE(ctx)) {
4221         nip = (uint32_t)nip;
4222     }
4223     tcg_gen_movi_tl(cpu_lr, nip);
4224 }
4225 
4226 /* b ba bl bla */
4227 static void gen_b(DisasContext *ctx)
4228 {
4229     target_ulong li, target;
4230 
4231     /* sign extend LI */
4232     li = LI(ctx->opcode);
4233     li = (li ^ 0x02000000) - 0x02000000;
4234     if (likely(AA(ctx->opcode) == 0)) {
4235         target = ctx->cia + li;
4236     } else {
4237         target = li;
4238     }
4239     if (LK(ctx->opcode)) {
4240         gen_setlr(ctx, ctx->base.pc_next);
4241     }
4242     gen_update_cfar(ctx, ctx->cia);
4243     gen_goto_tb(ctx, 0, target);
4244     ctx->base.is_jmp = DISAS_NORETURN;
4245 }
4246 
4247 #define BCOND_IM  0
4248 #define BCOND_LR  1
4249 #define BCOND_CTR 2
4250 #define BCOND_TAR 3
4251 
4252 static void gen_bcond(DisasContext *ctx, int type)
4253 {
4254     uint32_t bo = BO(ctx->opcode);
4255     TCGLabel *l1;
4256     TCGv target;
4257 
4258     if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4259         target = tcg_temp_new();
4260         if (type == BCOND_CTR) {
4261             tcg_gen_mov_tl(target, cpu_ctr);
4262         } else if (type == BCOND_TAR) {
4263             gen_load_spr(target, SPR_TAR);
4264         } else {
4265             tcg_gen_mov_tl(target, cpu_lr);
4266         }
4267     } else {
4268         target = NULL;
4269     }
4270     if (LK(ctx->opcode)) {
4271         gen_setlr(ctx, ctx->base.pc_next);
4272     }
4273     l1 = gen_new_label();
4274     if ((bo & 0x4) == 0) {
4275         /* Decrement and test CTR */
4276         TCGv temp = tcg_temp_new();
4277 
4278         if (type == BCOND_CTR) {
4279             /*
4280              * All ISAs up to v3 describe this form of bcctr as invalid but
4281              * some processors, ie. 64-bit server processors compliant with
4282              * arch 2.x, do implement a "test and decrement" logic instead,
4283              * as described in their respective UMs. This logic involves CTR
4284              * to act as both the branch target and a counter, which makes
4285              * it basically useless and thus never used in real code.
4286              *
4287              * This form was hence chosen to trigger extra micro-architectural
4288              * side-effect on real HW needed for the Spectre v2 workaround.
4289              * It is up to guests that implement such workaround, ie. linux, to
4290              * use this form in a way it just triggers the side-effect without
4291              * doing anything else harmful.
4292              */
4293             if (unlikely(!is_book3s_arch2x(ctx))) {
4294                 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4295                 return;
4296             }
4297 
4298             if (NARROW_MODE(ctx)) {
4299                 tcg_gen_ext32u_tl(temp, cpu_ctr);
4300             } else {
4301                 tcg_gen_mov_tl(temp, cpu_ctr);
4302             }
4303             if (bo & 0x2) {
4304                 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4305             } else {
4306                 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4307             }
4308             tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4309         } else {
4310             tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4311             if (NARROW_MODE(ctx)) {
4312                 tcg_gen_ext32u_tl(temp, cpu_ctr);
4313             } else {
4314                 tcg_gen_mov_tl(temp, cpu_ctr);
4315             }
4316             if (bo & 0x2) {
4317                 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4318             } else {
4319                 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4320             }
4321         }
4322     }
4323     if ((bo & 0x10) == 0) {
4324         /* Test CR */
4325         uint32_t bi = BI(ctx->opcode);
4326         uint32_t mask = 0x08 >> (bi & 0x03);
4327         TCGv_i32 temp = tcg_temp_new_i32();
4328 
4329         if (bo & 0x8) {
4330             tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4331             tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4332         } else {
4333             tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4334             tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4335         }
4336     }
4337     gen_update_cfar(ctx, ctx->cia);
4338     if (type == BCOND_IM) {
4339         target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4340         if (likely(AA(ctx->opcode) == 0)) {
4341             gen_goto_tb(ctx, 0, ctx->cia + li);
4342         } else {
4343             gen_goto_tb(ctx, 0, li);
4344         }
4345     } else {
4346         if (NARROW_MODE(ctx)) {
4347             tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4348         } else {
4349             tcg_gen_andi_tl(cpu_nip, target, ~3);
4350         }
4351         gen_lookup_and_goto_ptr(ctx);
4352     }
4353     if ((bo & 0x14) != 0x14) {
4354         /* fallthrough case */
4355         gen_set_label(l1);
4356         gen_goto_tb(ctx, 1, ctx->base.pc_next);
4357     }
4358     ctx->base.is_jmp = DISAS_NORETURN;
4359 }
4360 
4361 static void gen_bc(DisasContext *ctx)
4362 {
4363     gen_bcond(ctx, BCOND_IM);
4364 }
4365 
4366 static void gen_bcctr(DisasContext *ctx)
4367 {
4368     gen_bcond(ctx, BCOND_CTR);
4369 }
4370 
4371 static void gen_bclr(DisasContext *ctx)
4372 {
4373     gen_bcond(ctx, BCOND_LR);
4374 }
4375 
4376 static void gen_bctar(DisasContext *ctx)
4377 {
4378     gen_bcond(ctx, BCOND_TAR);
4379 }
4380 
4381 /***                      Condition register logical                       ***/
4382 #define GEN_CRLOGIC(name, tcg_op, opc)                                        \
4383 static void glue(gen_, name)(DisasContext *ctx)                               \
4384 {                                                                             \
4385     uint8_t bitmask;                                                          \
4386     int sh;                                                                   \
4387     TCGv_i32 t0, t1;                                                          \
4388     sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
4389     t0 = tcg_temp_new_i32();                                                  \
4390     if (sh > 0)                                                               \
4391         tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh);            \
4392     else if (sh < 0)                                                          \
4393         tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh);           \
4394     else                                                                      \
4395         tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]);                 \
4396     t1 = tcg_temp_new_i32();                                                  \
4397     sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
4398     if (sh > 0)                                                               \
4399         tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh);            \
4400     else if (sh < 0)                                                          \
4401         tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh);           \
4402     else                                                                      \
4403         tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]);                 \
4404     tcg_op(t0, t0, t1);                                                       \
4405     bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03);                             \
4406     tcg_gen_andi_i32(t0, t0, bitmask);                                        \
4407     tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);          \
4408     tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);                  \
4409 }
4410 
4411 /* crand */
4412 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4413 /* crandc */
4414 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4415 /* creqv */
4416 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4417 /* crnand */
4418 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4419 /* crnor */
4420 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4421 /* cror */
4422 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4423 /* crorc */
4424 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4425 /* crxor */
4426 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4427 
4428 /* mcrf */
4429 static void gen_mcrf(DisasContext *ctx)
4430 {
4431     tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4432 }
4433 
4434 /***                           System linkage                              ***/
4435 
4436 /* rfi (supervisor only) */
4437 static void gen_rfi(DisasContext *ctx)
4438 {
4439 #if defined(CONFIG_USER_ONLY)
4440     GEN_PRIV(ctx);
4441 #else
4442     /*
4443      * This instruction doesn't exist anymore on 64-bit server
4444      * processors compliant with arch 2.x
4445      */
4446     if (is_book3s_arch2x(ctx)) {
4447         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4448         return;
4449     }
4450     /* Restore CPU state */
4451     CHK_SV(ctx);
4452     translator_io_start(&ctx->base);
4453     gen_update_cfar(ctx, ctx->cia);
4454     gen_helper_rfi(cpu_env);
4455     ctx->base.is_jmp = DISAS_EXIT;
4456 #endif
4457 }
4458 
4459 #if defined(TARGET_PPC64)
4460 static void gen_rfid(DisasContext *ctx)
4461 {
4462 #if defined(CONFIG_USER_ONLY)
4463     GEN_PRIV(ctx);
4464 #else
4465     /* Restore CPU state */
4466     CHK_SV(ctx);
4467     translator_io_start(&ctx->base);
4468     gen_update_cfar(ctx, ctx->cia);
4469     gen_helper_rfid(cpu_env);
4470     ctx->base.is_jmp = DISAS_EXIT;
4471 #endif
4472 }
4473 
4474 #if !defined(CONFIG_USER_ONLY)
4475 static void gen_rfscv(DisasContext *ctx)
4476 {
4477 #if defined(CONFIG_USER_ONLY)
4478     GEN_PRIV(ctx);
4479 #else
4480     /* Restore CPU state */
4481     CHK_SV(ctx);
4482     translator_io_start(&ctx->base);
4483     gen_update_cfar(ctx, ctx->cia);
4484     gen_helper_rfscv(cpu_env);
4485     ctx->base.is_jmp = DISAS_EXIT;
4486 #endif
4487 }
4488 #endif
4489 
4490 static void gen_hrfid(DisasContext *ctx)
4491 {
4492 #if defined(CONFIG_USER_ONLY)
4493     GEN_PRIV(ctx);
4494 #else
4495     /* Restore CPU state */
4496     CHK_HV(ctx);
4497     translator_io_start(&ctx->base);
4498     gen_helper_hrfid(cpu_env);
4499     ctx->base.is_jmp = DISAS_EXIT;
4500 #endif
4501 }
4502 #endif
4503 
4504 /* sc */
4505 #if defined(CONFIG_USER_ONLY)
4506 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4507 #else
4508 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4509 #endif
4510 static void gen_sc(DisasContext *ctx)
4511 {
4512     uint32_t lev;
4513 
4514     /*
4515      * LEV is a 7-bit field, but the top 6 bits are treated as a reserved
4516      * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is
4517      * for Ultravisor which TCG does not support, so just ignore the top 6.
4518      */
4519     lev = (ctx->opcode >> 5) & 0x1;
4520     gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4521 }
4522 
4523 #if defined(TARGET_PPC64)
4524 #if !defined(CONFIG_USER_ONLY)
4525 static void gen_scv(DisasContext *ctx)
4526 {
4527     uint32_t lev = (ctx->opcode >> 5) & 0x7F;
4528 
4529     /* Set the PC back to the faulting instruction. */
4530     gen_update_nip(ctx, ctx->cia);
4531     gen_helper_scv(cpu_env, tcg_constant_i32(lev));
4532 
4533     ctx->base.is_jmp = DISAS_NORETURN;
4534 }
4535 #endif
4536 #endif
4537 
4538 /***                                Trap                                   ***/
4539 
4540 /* Check for unconditional traps (always or never) */
4541 static bool check_unconditional_trap(DisasContext *ctx)
4542 {
4543     /* Trap never */
4544     if (TO(ctx->opcode) == 0) {
4545         return true;
4546     }
4547     /* Trap always */
4548     if (TO(ctx->opcode) == 31) {
4549         gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
4550         return true;
4551     }
4552     return false;
4553 }
4554 
4555 /* tw */
4556 static void gen_tw(DisasContext *ctx)
4557 {
4558     TCGv_i32 t0;
4559 
4560     if (check_unconditional_trap(ctx)) {
4561         return;
4562     }
4563     t0 = tcg_constant_i32(TO(ctx->opcode));
4564     gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4565                   t0);
4566 }
4567 
4568 /* twi */
4569 static void gen_twi(DisasContext *ctx)
4570 {
4571     TCGv t0;
4572     TCGv_i32 t1;
4573 
4574     if (check_unconditional_trap(ctx)) {
4575         return;
4576     }
4577     t0 = tcg_constant_tl(SIMM(ctx->opcode));
4578     t1 = tcg_constant_i32(TO(ctx->opcode));
4579     gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4580 }
4581 
4582 #if defined(TARGET_PPC64)
4583 /* td */
4584 static void gen_td(DisasContext *ctx)
4585 {
4586     TCGv_i32 t0;
4587 
4588     if (check_unconditional_trap(ctx)) {
4589         return;
4590     }
4591     t0 = tcg_constant_i32(TO(ctx->opcode));
4592     gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4593                   t0);
4594 }
4595 
4596 /* tdi */
4597 static void gen_tdi(DisasContext *ctx)
4598 {
4599     TCGv t0;
4600     TCGv_i32 t1;
4601 
4602     if (check_unconditional_trap(ctx)) {
4603         return;
4604     }
4605     t0 = tcg_constant_tl(SIMM(ctx->opcode));
4606     t1 = tcg_constant_i32(TO(ctx->opcode));
4607     gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4608 }
4609 #endif
4610 
4611 /***                          Processor control                            ***/
4612 
4613 /* mcrxr */
4614 static void gen_mcrxr(DisasContext *ctx)
4615 {
4616     TCGv_i32 t0 = tcg_temp_new_i32();
4617     TCGv_i32 t1 = tcg_temp_new_i32();
4618     TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4619 
4620     tcg_gen_trunc_tl_i32(t0, cpu_so);
4621     tcg_gen_trunc_tl_i32(t1, cpu_ov);
4622     tcg_gen_trunc_tl_i32(dst, cpu_ca);
4623     tcg_gen_shli_i32(t0, t0, 3);
4624     tcg_gen_shli_i32(t1, t1, 2);
4625     tcg_gen_shli_i32(dst, dst, 1);
4626     tcg_gen_or_i32(dst, dst, t0);
4627     tcg_gen_or_i32(dst, dst, t1);
4628 
4629     tcg_gen_movi_tl(cpu_so, 0);
4630     tcg_gen_movi_tl(cpu_ov, 0);
4631     tcg_gen_movi_tl(cpu_ca, 0);
4632 }
4633 
4634 #ifdef TARGET_PPC64
4635 /* mcrxrx */
4636 static void gen_mcrxrx(DisasContext *ctx)
4637 {
4638     TCGv t0 = tcg_temp_new();
4639     TCGv t1 = tcg_temp_new();
4640     TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4641 
4642     /* copy OV and OV32 */
4643     tcg_gen_shli_tl(t0, cpu_ov, 1);
4644     tcg_gen_or_tl(t0, t0, cpu_ov32);
4645     tcg_gen_shli_tl(t0, t0, 2);
4646     /* copy CA and CA32 */
4647     tcg_gen_shli_tl(t1, cpu_ca, 1);
4648     tcg_gen_or_tl(t1, t1, cpu_ca32);
4649     tcg_gen_or_tl(t0, t0, t1);
4650     tcg_gen_trunc_tl_i32(dst, t0);
4651 }
4652 #endif
4653 
4654 /* mfcr mfocrf */
4655 static void gen_mfcr(DisasContext *ctx)
4656 {
4657     uint32_t crm, crn;
4658 
4659     if (likely(ctx->opcode & 0x00100000)) {
4660         crm = CRM(ctx->opcode);
4661         if (likely(crm && ((crm & (crm - 1)) == 0))) {
4662             crn = ctz32(crm);
4663             tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4664             tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4665                             cpu_gpr[rD(ctx->opcode)], crn * 4);
4666         }
4667     } else {
4668         TCGv_i32 t0 = tcg_temp_new_i32();
4669         tcg_gen_mov_i32(t0, cpu_crf[0]);
4670         tcg_gen_shli_i32(t0, t0, 4);
4671         tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4672         tcg_gen_shli_i32(t0, t0, 4);
4673         tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4674         tcg_gen_shli_i32(t0, t0, 4);
4675         tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4676         tcg_gen_shli_i32(t0, t0, 4);
4677         tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4678         tcg_gen_shli_i32(t0, t0, 4);
4679         tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4680         tcg_gen_shli_i32(t0, t0, 4);
4681         tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4682         tcg_gen_shli_i32(t0, t0, 4);
4683         tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4684         tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4685     }
4686 }
4687 
4688 /* mfmsr */
4689 static void gen_mfmsr(DisasContext *ctx)
4690 {
4691     CHK_SV(ctx);
4692     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4693 }
4694 
4695 /* mfspr */
4696 static inline void gen_op_mfspr(DisasContext *ctx)
4697 {
4698     void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4699     uint32_t sprn = SPR(ctx->opcode);
4700 
4701 #if defined(CONFIG_USER_ONLY)
4702     read_cb = ctx->spr_cb[sprn].uea_read;
4703 #else
4704     if (ctx->pr) {
4705         read_cb = ctx->spr_cb[sprn].uea_read;
4706     } else if (ctx->hv) {
4707         read_cb = ctx->spr_cb[sprn].hea_read;
4708     } else {
4709         read_cb = ctx->spr_cb[sprn].oea_read;
4710     }
4711 #endif
4712     if (likely(read_cb != NULL)) {
4713         if (likely(read_cb != SPR_NOACCESS)) {
4714             (*read_cb)(ctx, rD(ctx->opcode), sprn);
4715         } else {
4716             /* Privilege exception */
4717             /*
4718              * This is a hack to avoid warnings when running Linux:
4719              * this OS breaks the PowerPC virtualisation model,
4720              * allowing userland application to read the PVR
4721              */
4722             if (sprn != SPR_PVR) {
4723                 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
4724                               "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4725                               ctx->cia);
4726             }
4727             gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4728         }
4729     } else {
4730         /* ISA 2.07 defines these as no-ops */
4731         if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4732             (sprn >= 808 && sprn <= 811)) {
4733             /* This is a nop */
4734             return;
4735         }
4736         /* Not defined */
4737         qemu_log_mask(LOG_GUEST_ERROR,
4738                       "Trying to read invalid spr %d (0x%03x) at "
4739                       TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
4740 
4741         /*
4742          * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4743          * generate a priv, a hv emu or a no-op
4744          */
4745         if (sprn & 0x10) {
4746             if (ctx->pr) {
4747                 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4748             }
4749         } else {
4750             if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4751                 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4752             }
4753         }
4754     }
4755 }
4756 
4757 static void gen_mfspr(DisasContext *ctx)
4758 {
4759     gen_op_mfspr(ctx);
4760 }
4761 
4762 /* mftb */
4763 static void gen_mftb(DisasContext *ctx)
4764 {
4765     gen_op_mfspr(ctx);
4766 }
4767 
4768 /* mtcrf mtocrf*/
4769 static void gen_mtcrf(DisasContext *ctx)
4770 {
4771     uint32_t crm, crn;
4772 
4773     crm = CRM(ctx->opcode);
4774     if (likely((ctx->opcode & 0x00100000))) {
4775         if (crm && ((crm & (crm - 1)) == 0)) {
4776             TCGv_i32 temp = tcg_temp_new_i32();
4777             crn = ctz32(crm);
4778             tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4779             tcg_gen_shri_i32(temp, temp, crn * 4);
4780             tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4781         }
4782     } else {
4783         TCGv_i32 temp = tcg_temp_new_i32();
4784         tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4785         for (crn = 0 ; crn < 8 ; crn++) {
4786             if (crm & (1 << crn)) {
4787                     tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4788                     tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4789             }
4790         }
4791     }
4792 }
4793 
4794 /* mtmsr */
4795 #if defined(TARGET_PPC64)
4796 static void gen_mtmsrd(DisasContext *ctx)
4797 {
4798     if (unlikely(!is_book3s_arch2x(ctx))) {
4799         gen_invalid(ctx);
4800         return;
4801     }
4802 
4803     CHK_SV(ctx);
4804 
4805 #if !defined(CONFIG_USER_ONLY)
4806     TCGv t0, t1;
4807     target_ulong mask;
4808 
4809     t0 = tcg_temp_new();
4810     t1 = tcg_temp_new();
4811 
4812     translator_io_start(&ctx->base);
4813 
4814     if (ctx->opcode & 0x00010000) {
4815         /* L=1 form only updates EE and RI */
4816         mask = (1ULL << MSR_RI) | (1ULL << MSR_EE);
4817     } else {
4818         /* mtmsrd does not alter HV, S, ME, or LE */
4819         mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) |
4820                  (1ULL << MSR_HV));
4821         /*
4822          * XXX: we need to update nip before the store if we enter
4823          *      power saving mode, we will exit the loop directly from
4824          *      ppc_store_msr
4825          */
4826         gen_update_nip(ctx, ctx->base.pc_next);
4827     }
4828 
4829     tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
4830     tcg_gen_andi_tl(t1, cpu_msr, ~mask);
4831     tcg_gen_or_tl(t0, t0, t1);
4832 
4833     gen_helper_store_msr(cpu_env, t0);
4834 
4835     /* Must stop the translation as machine state (may have) changed */
4836     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
4837 #endif /* !defined(CONFIG_USER_ONLY) */
4838 }
4839 #endif /* defined(TARGET_PPC64) */
4840 
4841 static void gen_mtmsr(DisasContext *ctx)
4842 {
4843     CHK_SV(ctx);
4844 
4845 #if !defined(CONFIG_USER_ONLY)
4846     TCGv t0, t1;
4847     target_ulong mask = 0xFFFFFFFF;
4848 
4849     t0 = tcg_temp_new();
4850     t1 = tcg_temp_new();
4851 
4852     translator_io_start(&ctx->base);
4853     if (ctx->opcode & 0x00010000) {
4854         /* L=1 form only updates EE and RI */
4855         mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE);
4856     } else {
4857         /* mtmsr does not alter S, ME, or LE */
4858         mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S));
4859 
4860         /*
4861          * XXX: we need to update nip before the store if we enter
4862          *      power saving mode, we will exit the loop directly from
4863          *      ppc_store_msr
4864          */
4865         gen_update_nip(ctx, ctx->base.pc_next);
4866     }
4867 
4868     tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
4869     tcg_gen_andi_tl(t1, cpu_msr, ~mask);
4870     tcg_gen_or_tl(t0, t0, t1);
4871 
4872     gen_helper_store_msr(cpu_env, t0);
4873 
4874     /* Must stop the translation as machine state (may have) changed */
4875     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
4876 #endif
4877 }
4878 
4879 /* mtspr */
4880 static void gen_mtspr(DisasContext *ctx)
4881 {
4882     void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4883     uint32_t sprn = SPR(ctx->opcode);
4884 
4885 #if defined(CONFIG_USER_ONLY)
4886     write_cb = ctx->spr_cb[sprn].uea_write;
4887 #else
4888     if (ctx->pr) {
4889         write_cb = ctx->spr_cb[sprn].uea_write;
4890     } else if (ctx->hv) {
4891         write_cb = ctx->spr_cb[sprn].hea_write;
4892     } else {
4893         write_cb = ctx->spr_cb[sprn].oea_write;
4894     }
4895 #endif
4896     if (likely(write_cb != NULL)) {
4897         if (likely(write_cb != SPR_NOACCESS)) {
4898             (*write_cb)(ctx, sprn, rS(ctx->opcode));
4899         } else {
4900             /* Privilege exception */
4901             qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4902                           "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4903                           ctx->cia);
4904             gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4905         }
4906     } else {
4907         /* ISA 2.07 defines these as no-ops */
4908         if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4909             (sprn >= 808 && sprn <= 811)) {
4910             /* This is a nop */
4911             return;
4912         }
4913 
4914         /* Not defined */
4915         qemu_log_mask(LOG_GUEST_ERROR,
4916                       "Trying to write invalid spr %d (0x%03x) at "
4917                       TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
4918 
4919 
4920         /*
4921          * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4922          * generate a priv, a hv emu or a no-op
4923          */
4924         if (sprn & 0x10) {
4925             if (ctx->pr) {
4926                 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4927             }
4928         } else {
4929             if (ctx->pr || sprn == 0) {
4930                 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4931             }
4932         }
4933     }
4934 }
4935 
4936 #if defined(TARGET_PPC64)
4937 /* setb */
4938 static void gen_setb(DisasContext *ctx)
4939 {
4940     TCGv_i32 t0 = tcg_temp_new_i32();
4941     TCGv_i32 t8 = tcg_constant_i32(8);
4942     TCGv_i32 tm1 = tcg_constant_i32(-1);
4943     int crf = crfS(ctx->opcode);
4944 
4945     tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4946     tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4947     tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4948 }
4949 #endif
4950 
4951 /***                         Cache management                              ***/
4952 
4953 /* dcbf */
4954 static void gen_dcbf(DisasContext *ctx)
4955 {
4956     /* XXX: specification says this is treated as a load by the MMU */
4957     TCGv t0;
4958     gen_set_access_type(ctx, ACCESS_CACHE);
4959     t0 = tcg_temp_new();
4960     gen_addr_reg_index(ctx, t0);
4961     gen_qemu_ld8u(ctx, t0, t0);
4962 }
4963 
4964 /* dcbfep (external PID dcbf) */
4965 static void gen_dcbfep(DisasContext *ctx)
4966 {
4967     /* XXX: specification says this is treated as a load by the MMU */
4968     TCGv t0;
4969     CHK_SV(ctx);
4970     gen_set_access_type(ctx, ACCESS_CACHE);
4971     t0 = tcg_temp_new();
4972     gen_addr_reg_index(ctx, t0);
4973     tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4974 }
4975 
4976 /* dcbi (Supervisor only) */
4977 static void gen_dcbi(DisasContext *ctx)
4978 {
4979 #if defined(CONFIG_USER_ONLY)
4980     GEN_PRIV(ctx);
4981 #else
4982     TCGv EA, val;
4983 
4984     CHK_SV(ctx);
4985     EA = tcg_temp_new();
4986     gen_set_access_type(ctx, ACCESS_CACHE);
4987     gen_addr_reg_index(ctx, EA);
4988     val = tcg_temp_new();
4989     /* XXX: specification says this should be treated as a store by the MMU */
4990     gen_qemu_ld8u(ctx, val, EA);
4991     gen_qemu_st8(ctx, val, EA);
4992 #endif /* defined(CONFIG_USER_ONLY) */
4993 }
4994 
4995 /* dcdst */
4996 static void gen_dcbst(DisasContext *ctx)
4997 {
4998     /* XXX: specification say this is treated as a load by the MMU */
4999     TCGv t0;
5000     gen_set_access_type(ctx, ACCESS_CACHE);
5001     t0 = tcg_temp_new();
5002     gen_addr_reg_index(ctx, t0);
5003     gen_qemu_ld8u(ctx, t0, t0);
5004 }
5005 
5006 /* dcbstep (dcbstep External PID version) */
5007 static void gen_dcbstep(DisasContext *ctx)
5008 {
5009     /* XXX: specification say this is treated as a load by the MMU */
5010     TCGv t0;
5011     gen_set_access_type(ctx, ACCESS_CACHE);
5012     t0 = tcg_temp_new();
5013     gen_addr_reg_index(ctx, t0);
5014     tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
5015 }
5016 
5017 /* dcbt */
5018 static void gen_dcbt(DisasContext *ctx)
5019 {
5020     /*
5021      * interpreted as no-op
5022      * XXX: specification say this is treated as a load by the MMU but
5023      *      does not generate any exception
5024      */
5025 }
5026 
5027 /* dcbtep */
5028 static void gen_dcbtep(DisasContext *ctx)
5029 {
5030     /*
5031      * interpreted as no-op
5032      * XXX: specification say this is treated as a load by the MMU but
5033      *      does not generate any exception
5034      */
5035 }
5036 
5037 /* dcbtst */
5038 static void gen_dcbtst(DisasContext *ctx)
5039 {
5040     /*
5041      * interpreted as no-op
5042      * XXX: specification say this is treated as a load by the MMU but
5043      *      does not generate any exception
5044      */
5045 }
5046 
5047 /* dcbtstep */
5048 static void gen_dcbtstep(DisasContext *ctx)
5049 {
5050     /*
5051      * interpreted as no-op
5052      * XXX: specification say this is treated as a load by the MMU but
5053      *      does not generate any exception
5054      */
5055 }
5056 
5057 /* dcbtls */
5058 static void gen_dcbtls(DisasContext *ctx)
5059 {
5060     /* Always fails locking the cache */
5061     TCGv t0 = tcg_temp_new();
5062     gen_load_spr(t0, SPR_Exxx_L1CSR0);
5063     tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
5064     gen_store_spr(SPR_Exxx_L1CSR0, t0);
5065 }
5066 
5067 /* dcblc */
5068 static void gen_dcblc(DisasContext *ctx)
5069 {
5070     /*
5071      * interpreted as no-op
5072      */
5073 }
5074 
5075 /* dcbz */
5076 static void gen_dcbz(DisasContext *ctx)
5077 {
5078     TCGv tcgv_addr;
5079     TCGv_i32 tcgv_op;
5080 
5081     gen_set_access_type(ctx, ACCESS_CACHE);
5082     tcgv_addr = tcg_temp_new();
5083     tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
5084     gen_addr_reg_index(ctx, tcgv_addr);
5085     gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
5086 }
5087 
5088 /* dcbzep */
5089 static void gen_dcbzep(DisasContext *ctx)
5090 {
5091     TCGv tcgv_addr;
5092     TCGv_i32 tcgv_op;
5093 
5094     gen_set_access_type(ctx, ACCESS_CACHE);
5095     tcgv_addr = tcg_temp_new();
5096     tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
5097     gen_addr_reg_index(ctx, tcgv_addr);
5098     gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
5099 }
5100 
5101 /* dst / dstt */
5102 static void gen_dst(DisasContext *ctx)
5103 {
5104     if (rA(ctx->opcode) == 0) {
5105         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5106     } else {
5107         /* interpreted as no-op */
5108     }
5109 }
5110 
5111 /* dstst /dststt */
5112 static void gen_dstst(DisasContext *ctx)
5113 {
5114     if (rA(ctx->opcode) == 0) {
5115         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5116     } else {
5117         /* interpreted as no-op */
5118     }
5119 
5120 }
5121 
5122 /* dss / dssall */
5123 static void gen_dss(DisasContext *ctx)
5124 {
5125     /* interpreted as no-op */
5126 }
5127 
5128 /* icbi */
5129 static void gen_icbi(DisasContext *ctx)
5130 {
5131     TCGv t0;
5132     gen_set_access_type(ctx, ACCESS_CACHE);
5133     t0 = tcg_temp_new();
5134     gen_addr_reg_index(ctx, t0);
5135     gen_helper_icbi(cpu_env, t0);
5136 }
5137 
5138 /* icbiep */
5139 static void gen_icbiep(DisasContext *ctx)
5140 {
5141     TCGv t0;
5142     gen_set_access_type(ctx, ACCESS_CACHE);
5143     t0 = tcg_temp_new();
5144     gen_addr_reg_index(ctx, t0);
5145     gen_helper_icbiep(cpu_env, t0);
5146 }
5147 
5148 /* Optional: */
5149 /* dcba */
5150 static void gen_dcba(DisasContext *ctx)
5151 {
5152     /*
5153      * interpreted as no-op
5154      * XXX: specification say this is treated as a store by the MMU
5155      *      but does not generate any exception
5156      */
5157 }
5158 
5159 /***                    Segment register manipulation                      ***/
5160 /* Supervisor only: */
5161 
5162 /* mfsr */
5163 static void gen_mfsr(DisasContext *ctx)
5164 {
5165 #if defined(CONFIG_USER_ONLY)
5166     GEN_PRIV(ctx);
5167 #else
5168     TCGv t0;
5169 
5170     CHK_SV(ctx);
5171     t0 = tcg_constant_tl(SR(ctx->opcode));
5172     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5173 #endif /* defined(CONFIG_USER_ONLY) */
5174 }
5175 
5176 /* mfsrin */
5177 static void gen_mfsrin(DisasContext *ctx)
5178 {
5179 #if defined(CONFIG_USER_ONLY)
5180     GEN_PRIV(ctx);
5181 #else
5182     TCGv t0;
5183 
5184     CHK_SV(ctx);
5185     t0 = tcg_temp_new();
5186     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5187     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5188 #endif /* defined(CONFIG_USER_ONLY) */
5189 }
5190 
5191 /* mtsr */
5192 static void gen_mtsr(DisasContext *ctx)
5193 {
5194 #if defined(CONFIG_USER_ONLY)
5195     GEN_PRIV(ctx);
5196 #else
5197     TCGv t0;
5198 
5199     CHK_SV(ctx);
5200     t0 = tcg_constant_tl(SR(ctx->opcode));
5201     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5202 #endif /* defined(CONFIG_USER_ONLY) */
5203 }
5204 
5205 /* mtsrin */
5206 static void gen_mtsrin(DisasContext *ctx)
5207 {
5208 #if defined(CONFIG_USER_ONLY)
5209     GEN_PRIV(ctx);
5210 #else
5211     TCGv t0;
5212     CHK_SV(ctx);
5213 
5214     t0 = tcg_temp_new();
5215     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5216     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
5217 #endif /* defined(CONFIG_USER_ONLY) */
5218 }
5219 
5220 #if defined(TARGET_PPC64)
5221 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
5222 
5223 /* mfsr */
5224 static void gen_mfsr_64b(DisasContext *ctx)
5225 {
5226 #if defined(CONFIG_USER_ONLY)
5227     GEN_PRIV(ctx);
5228 #else
5229     TCGv t0;
5230 
5231     CHK_SV(ctx);
5232     t0 = tcg_constant_tl(SR(ctx->opcode));
5233     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5234 #endif /* defined(CONFIG_USER_ONLY) */
5235 }
5236 
5237 /* mfsrin */
5238 static void gen_mfsrin_64b(DisasContext *ctx)
5239 {
5240 #if defined(CONFIG_USER_ONLY)
5241     GEN_PRIV(ctx);
5242 #else
5243     TCGv t0;
5244 
5245     CHK_SV(ctx);
5246     t0 = tcg_temp_new();
5247     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5248     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5249 #endif /* defined(CONFIG_USER_ONLY) */
5250 }
5251 
5252 /* mtsr */
5253 static void gen_mtsr_64b(DisasContext *ctx)
5254 {
5255 #if defined(CONFIG_USER_ONLY)
5256     GEN_PRIV(ctx);
5257 #else
5258     TCGv t0;
5259 
5260     CHK_SV(ctx);
5261     t0 = tcg_constant_tl(SR(ctx->opcode));
5262     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5263 #endif /* defined(CONFIG_USER_ONLY) */
5264 }
5265 
5266 /* mtsrin */
5267 static void gen_mtsrin_64b(DisasContext *ctx)
5268 {
5269 #if defined(CONFIG_USER_ONLY)
5270     GEN_PRIV(ctx);
5271 #else
5272     TCGv t0;
5273 
5274     CHK_SV(ctx);
5275     t0 = tcg_temp_new();
5276     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5277     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5278 #endif /* defined(CONFIG_USER_ONLY) */
5279 }
5280 
5281 #endif /* defined(TARGET_PPC64) */
5282 
5283 /***                      Lookaside buffer management                      ***/
5284 /* Optional & supervisor only: */
5285 
5286 /* tlbia */
5287 static void gen_tlbia(DisasContext *ctx)
5288 {
5289 #if defined(CONFIG_USER_ONLY)
5290     GEN_PRIV(ctx);
5291 #else
5292     CHK_HV(ctx);
5293 
5294     gen_helper_tlbia(cpu_env);
5295 #endif  /* defined(CONFIG_USER_ONLY) */
5296 }
5297 
5298 /* tlbsync */
5299 static void gen_tlbsync(DisasContext *ctx)
5300 {
5301 #if defined(CONFIG_USER_ONLY)
5302     GEN_PRIV(ctx);
5303 #else
5304 
5305     if (ctx->gtse) {
5306         CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */
5307     } else {
5308         CHK_HV(ctx); /* Else hypervisor privileged */
5309     }
5310 
5311     /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
5312     if (ctx->insns_flags & PPC_BOOKE) {
5313         gen_check_tlb_flush(ctx, true);
5314     }
5315 #endif /* defined(CONFIG_USER_ONLY) */
5316 }
5317 
5318 /***                              External control                         ***/
5319 /* Optional: */
5320 
5321 /* eciwx */
5322 static void gen_eciwx(DisasContext *ctx)
5323 {
5324     TCGv t0;
5325     /* Should check EAR[E] ! */
5326     gen_set_access_type(ctx, ACCESS_EXT);
5327     t0 = tcg_temp_new();
5328     gen_addr_reg_index(ctx, t0);
5329     tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5330                        DEF_MEMOP(MO_UL | MO_ALIGN));
5331 }
5332 
5333 /* ecowx */
5334 static void gen_ecowx(DisasContext *ctx)
5335 {
5336     TCGv t0;
5337     /* Should check EAR[E] ! */
5338     gen_set_access_type(ctx, ACCESS_EXT);
5339     t0 = tcg_temp_new();
5340     gen_addr_reg_index(ctx, t0);
5341     tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5342                        DEF_MEMOP(MO_UL | MO_ALIGN));
5343 }
5344 
5345 /* 602 - 603 - G2 TLB management */
5346 
5347 /* tlbld */
5348 static void gen_tlbld_6xx(DisasContext *ctx)
5349 {
5350 #if defined(CONFIG_USER_ONLY)
5351     GEN_PRIV(ctx);
5352 #else
5353     CHK_SV(ctx);
5354     gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5355 #endif /* defined(CONFIG_USER_ONLY) */
5356 }
5357 
5358 /* tlbli */
5359 static void gen_tlbli_6xx(DisasContext *ctx)
5360 {
5361 #if defined(CONFIG_USER_ONLY)
5362     GEN_PRIV(ctx);
5363 #else
5364     CHK_SV(ctx);
5365     gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5366 #endif /* defined(CONFIG_USER_ONLY) */
5367 }
5368 
5369 /* BookE specific instructions */
5370 
5371 /* XXX: not implemented on 440 ? */
5372 static void gen_mfapidi(DisasContext *ctx)
5373 {
5374     /* XXX: TODO */
5375     gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5376 }
5377 
5378 /* XXX: not implemented on 440 ? */
5379 static void gen_tlbiva(DisasContext *ctx)
5380 {
5381 #if defined(CONFIG_USER_ONLY)
5382     GEN_PRIV(ctx);
5383 #else
5384     TCGv t0;
5385 
5386     CHK_SV(ctx);
5387     t0 = tcg_temp_new();
5388     gen_addr_reg_index(ctx, t0);
5389     gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5390 #endif /* defined(CONFIG_USER_ONLY) */
5391 }
5392 
5393 /* All 405 MAC instructions are translated here */
5394 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5395                                         int ra, int rb, int rt, int Rc)
5396 {
5397     TCGv t0, t1;
5398 
5399     t0 = tcg_temp_new();
5400     t1 = tcg_temp_new();
5401 
5402     switch (opc3 & 0x0D) {
5403     case 0x05:
5404         /* macchw    - macchw.    - macchwo   - macchwo.   */
5405         /* macchws   - macchws.   - macchwso  - macchwso.  */
5406         /* nmacchw   - nmacchw.   - nmacchwo  - nmacchwo.  */
5407         /* nmacchws  - nmacchws.  - nmacchwso - nmacchwso. */
5408         /* mulchw - mulchw. */
5409         tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5410         tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5411         tcg_gen_ext16s_tl(t1, t1);
5412         break;
5413     case 0x04:
5414         /* macchwu   - macchwu.   - macchwuo  - macchwuo.  */
5415         /* macchwsu  - macchwsu.  - macchwsuo - macchwsuo. */
5416         /* mulchwu - mulchwu. */
5417         tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5418         tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5419         tcg_gen_ext16u_tl(t1, t1);
5420         break;
5421     case 0x01:
5422         /* machhw    - machhw.    - machhwo   - machhwo.   */
5423         /* machhws   - machhws.   - machhwso  - machhwso.  */
5424         /* nmachhw   - nmachhw.   - nmachhwo  - nmachhwo.  */
5425         /* nmachhws  - nmachhws.  - nmachhwso - nmachhwso. */
5426         /* mulhhw - mulhhw. */
5427         tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5428         tcg_gen_ext16s_tl(t0, t0);
5429         tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5430         tcg_gen_ext16s_tl(t1, t1);
5431         break;
5432     case 0x00:
5433         /* machhwu   - machhwu.   - machhwuo  - machhwuo.  */
5434         /* machhwsu  - machhwsu.  - machhwsuo - machhwsuo. */
5435         /* mulhhwu - mulhhwu. */
5436         tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5437         tcg_gen_ext16u_tl(t0, t0);
5438         tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5439         tcg_gen_ext16u_tl(t1, t1);
5440         break;
5441     case 0x0D:
5442         /* maclhw    - maclhw.    - maclhwo   - maclhwo.   */
5443         /* maclhws   - maclhws.   - maclhwso  - maclhwso.  */
5444         /* nmaclhw   - nmaclhw.   - nmaclhwo  - nmaclhwo.  */
5445         /* nmaclhws  - nmaclhws.  - nmaclhwso - nmaclhwso. */
5446         /* mullhw - mullhw. */
5447         tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5448         tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5449         break;
5450     case 0x0C:
5451         /* maclhwu   - maclhwu.   - maclhwuo  - maclhwuo.  */
5452         /* maclhwsu  - maclhwsu.  - maclhwsuo - maclhwsuo. */
5453         /* mullhwu - mullhwu. */
5454         tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5455         tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5456         break;
5457     }
5458     if (opc2 & 0x04) {
5459         /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5460         tcg_gen_mul_tl(t1, t0, t1);
5461         if (opc2 & 0x02) {
5462             /* nmultiply-and-accumulate (0x0E) */
5463             tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5464         } else {
5465             /* multiply-and-accumulate (0x0C) */
5466             tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5467         }
5468 
5469         if (opc3 & 0x12) {
5470             /* Check overflow and/or saturate */
5471             TCGLabel *l1 = gen_new_label();
5472 
5473             if (opc3 & 0x10) {
5474                 /* Start with XER OV disabled, the most likely case */
5475                 tcg_gen_movi_tl(cpu_ov, 0);
5476             }
5477             if (opc3 & 0x01) {
5478                 /* Signed */
5479                 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5480                 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5481                 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5482                 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5483                 if (opc3 & 0x02) {
5484                     /* Saturate */
5485                     tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5486                     tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5487                 }
5488             } else {
5489                 /* Unsigned */
5490                 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5491                 if (opc3 & 0x02) {
5492                     /* Saturate */
5493                     tcg_gen_movi_tl(t0, UINT32_MAX);
5494                 }
5495             }
5496             if (opc3 & 0x10) {
5497                 /* Check overflow */
5498                 tcg_gen_movi_tl(cpu_ov, 1);
5499                 tcg_gen_movi_tl(cpu_so, 1);
5500             }
5501             gen_set_label(l1);
5502             tcg_gen_mov_tl(cpu_gpr[rt], t0);
5503         }
5504     } else {
5505         tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5506     }
5507     if (unlikely(Rc) != 0) {
5508         /* Update Rc0 */
5509         gen_set_Rc0(ctx, cpu_gpr[rt]);
5510     }
5511 }
5512 
5513 #define GEN_MAC_HANDLER(name, opc2, opc3)                                     \
5514 static void glue(gen_, name)(DisasContext *ctx)                               \
5515 {                                                                             \
5516     gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode),   \
5517                          rD(ctx->opcode), Rc(ctx->opcode));                   \
5518 }
5519 
5520 /* macchw    - macchw.    */
5521 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5522 /* macchwo   - macchwo.   */
5523 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5524 /* macchws   - macchws.   */
5525 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5526 /* macchwso  - macchwso.  */
5527 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5528 /* macchwsu  - macchwsu.  */
5529 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5530 /* macchwsuo - macchwsuo. */
5531 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5532 /* macchwu   - macchwu.   */
5533 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5534 /* macchwuo  - macchwuo.  */
5535 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5536 /* machhw    - machhw.    */
5537 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5538 /* machhwo   - machhwo.   */
5539 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5540 /* machhws   - machhws.   */
5541 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5542 /* machhwso  - machhwso.  */
5543 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5544 /* machhwsu  - machhwsu.  */
5545 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5546 /* machhwsuo - machhwsuo. */
5547 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5548 /* machhwu   - machhwu.   */
5549 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5550 /* machhwuo  - machhwuo.  */
5551 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5552 /* maclhw    - maclhw.    */
5553 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5554 /* maclhwo   - maclhwo.   */
5555 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5556 /* maclhws   - maclhws.   */
5557 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5558 /* maclhwso  - maclhwso.  */
5559 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5560 /* maclhwu   - maclhwu.   */
5561 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5562 /* maclhwuo  - maclhwuo.  */
5563 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5564 /* maclhwsu  - maclhwsu.  */
5565 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5566 /* maclhwsuo - maclhwsuo. */
5567 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5568 /* nmacchw   - nmacchw.   */
5569 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5570 /* nmacchwo  - nmacchwo.  */
5571 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5572 /* nmacchws  - nmacchws.  */
5573 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5574 /* nmacchwso - nmacchwso. */
5575 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5576 /* nmachhw   - nmachhw.   */
5577 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5578 /* nmachhwo  - nmachhwo.  */
5579 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5580 /* nmachhws  - nmachhws.  */
5581 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5582 /* nmachhwso - nmachhwso. */
5583 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5584 /* nmaclhw   - nmaclhw.   */
5585 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5586 /* nmaclhwo  - nmaclhwo.  */
5587 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5588 /* nmaclhws  - nmaclhws.  */
5589 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5590 /* nmaclhwso - nmaclhwso. */
5591 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5592 
5593 /* mulchw  - mulchw.  */
5594 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5595 /* mulchwu - mulchwu. */
5596 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5597 /* mulhhw  - mulhhw.  */
5598 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5599 /* mulhhwu - mulhhwu. */
5600 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5601 /* mullhw  - mullhw.  */
5602 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5603 /* mullhwu - mullhwu. */
5604 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5605 
5606 /* mfdcr */
5607 static void gen_mfdcr(DisasContext *ctx)
5608 {
5609 #if defined(CONFIG_USER_ONLY)
5610     GEN_PRIV(ctx);
5611 #else
5612     TCGv dcrn;
5613 
5614     CHK_SV(ctx);
5615     dcrn = tcg_constant_tl(SPR(ctx->opcode));
5616     gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5617 #endif /* defined(CONFIG_USER_ONLY) */
5618 }
5619 
5620 /* mtdcr */
5621 static void gen_mtdcr(DisasContext *ctx)
5622 {
5623 #if defined(CONFIG_USER_ONLY)
5624     GEN_PRIV(ctx);
5625 #else
5626     TCGv dcrn;
5627 
5628     CHK_SV(ctx);
5629     dcrn = tcg_constant_tl(SPR(ctx->opcode));
5630     gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5631 #endif /* defined(CONFIG_USER_ONLY) */
5632 }
5633 
5634 /* mfdcrx */
5635 /* XXX: not implemented on 440 ? */
5636 static void gen_mfdcrx(DisasContext *ctx)
5637 {
5638 #if defined(CONFIG_USER_ONLY)
5639     GEN_PRIV(ctx);
5640 #else
5641     CHK_SV(ctx);
5642     gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5643                         cpu_gpr[rA(ctx->opcode)]);
5644     /* Note: Rc update flag set leads to undefined state of Rc0 */
5645 #endif /* defined(CONFIG_USER_ONLY) */
5646 }
5647 
5648 /* mtdcrx */
5649 /* XXX: not implemented on 440 ? */
5650 static void gen_mtdcrx(DisasContext *ctx)
5651 {
5652 #if defined(CONFIG_USER_ONLY)
5653     GEN_PRIV(ctx);
5654 #else
5655     CHK_SV(ctx);
5656     gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5657                          cpu_gpr[rS(ctx->opcode)]);
5658     /* Note: Rc update flag set leads to undefined state of Rc0 */
5659 #endif /* defined(CONFIG_USER_ONLY) */
5660 }
5661 
5662 /* dccci */
5663 static void gen_dccci(DisasContext *ctx)
5664 {
5665     CHK_SV(ctx);
5666     /* interpreted as no-op */
5667 }
5668 
5669 /* dcread */
5670 static void gen_dcread(DisasContext *ctx)
5671 {
5672 #if defined(CONFIG_USER_ONLY)
5673     GEN_PRIV(ctx);
5674 #else
5675     TCGv EA, val;
5676 
5677     CHK_SV(ctx);
5678     gen_set_access_type(ctx, ACCESS_CACHE);
5679     EA = tcg_temp_new();
5680     gen_addr_reg_index(ctx, EA);
5681     val = tcg_temp_new();
5682     gen_qemu_ld32u(ctx, val, EA);
5683     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5684 #endif /* defined(CONFIG_USER_ONLY) */
5685 }
5686 
5687 /* icbt */
5688 static void gen_icbt_40x(DisasContext *ctx)
5689 {
5690     /*
5691      * interpreted as no-op
5692      * XXX: specification say this is treated as a load by the MMU but
5693      *      does not generate any exception
5694      */
5695 }
5696 
5697 /* iccci */
5698 static void gen_iccci(DisasContext *ctx)
5699 {
5700     CHK_SV(ctx);
5701     /* interpreted as no-op */
5702 }
5703 
5704 /* icread */
5705 static void gen_icread(DisasContext *ctx)
5706 {
5707     CHK_SV(ctx);
5708     /* interpreted as no-op */
5709 }
5710 
5711 /* rfci (supervisor only) */
5712 static void gen_rfci_40x(DisasContext *ctx)
5713 {
5714 #if defined(CONFIG_USER_ONLY)
5715     GEN_PRIV(ctx);
5716 #else
5717     CHK_SV(ctx);
5718     /* Restore CPU state */
5719     gen_helper_40x_rfci(cpu_env);
5720     ctx->base.is_jmp = DISAS_EXIT;
5721 #endif /* defined(CONFIG_USER_ONLY) */
5722 }
5723 
5724 static void gen_rfci(DisasContext *ctx)
5725 {
5726 #if defined(CONFIG_USER_ONLY)
5727     GEN_PRIV(ctx);
5728 #else
5729     CHK_SV(ctx);
5730     /* Restore CPU state */
5731     gen_helper_rfci(cpu_env);
5732     ctx->base.is_jmp = DISAS_EXIT;
5733 #endif /* defined(CONFIG_USER_ONLY) */
5734 }
5735 
5736 /* BookE specific */
5737 
5738 /* XXX: not implemented on 440 ? */
5739 static void gen_rfdi(DisasContext *ctx)
5740 {
5741 #if defined(CONFIG_USER_ONLY)
5742     GEN_PRIV(ctx);
5743 #else
5744     CHK_SV(ctx);
5745     /* Restore CPU state */
5746     gen_helper_rfdi(cpu_env);
5747     ctx->base.is_jmp = DISAS_EXIT;
5748 #endif /* defined(CONFIG_USER_ONLY) */
5749 }
5750 
5751 /* XXX: not implemented on 440 ? */
5752 static void gen_rfmci(DisasContext *ctx)
5753 {
5754 #if defined(CONFIG_USER_ONLY)
5755     GEN_PRIV(ctx);
5756 #else
5757     CHK_SV(ctx);
5758     /* Restore CPU state */
5759     gen_helper_rfmci(cpu_env);
5760     ctx->base.is_jmp = DISAS_EXIT;
5761 #endif /* defined(CONFIG_USER_ONLY) */
5762 }
5763 
5764 /* TLB management - PowerPC 405 implementation */
5765 
5766 /* tlbre */
5767 static void gen_tlbre_40x(DisasContext *ctx)
5768 {
5769 #if defined(CONFIG_USER_ONLY)
5770     GEN_PRIV(ctx);
5771 #else
5772     CHK_SV(ctx);
5773     switch (rB(ctx->opcode)) {
5774     case 0:
5775         gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5776                                 cpu_gpr[rA(ctx->opcode)]);
5777         break;
5778     case 1:
5779         gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5780                                 cpu_gpr[rA(ctx->opcode)]);
5781         break;
5782     default:
5783         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5784         break;
5785     }
5786 #endif /* defined(CONFIG_USER_ONLY) */
5787 }
5788 
5789 /* tlbsx - tlbsx. */
5790 static void gen_tlbsx_40x(DisasContext *ctx)
5791 {
5792 #if defined(CONFIG_USER_ONLY)
5793     GEN_PRIV(ctx);
5794 #else
5795     TCGv t0;
5796 
5797     CHK_SV(ctx);
5798     t0 = tcg_temp_new();
5799     gen_addr_reg_index(ctx, t0);
5800     gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5801     if (Rc(ctx->opcode)) {
5802         TCGLabel *l1 = gen_new_label();
5803         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5804         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5805         tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5806         gen_set_label(l1);
5807     }
5808 #endif /* defined(CONFIG_USER_ONLY) */
5809 }
5810 
5811 /* tlbwe */
5812 static void gen_tlbwe_40x(DisasContext *ctx)
5813 {
5814 #if defined(CONFIG_USER_ONLY)
5815     GEN_PRIV(ctx);
5816 #else
5817     CHK_SV(ctx);
5818 
5819     switch (rB(ctx->opcode)) {
5820     case 0:
5821         gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5822                                 cpu_gpr[rS(ctx->opcode)]);
5823         break;
5824     case 1:
5825         gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5826                                 cpu_gpr[rS(ctx->opcode)]);
5827         break;
5828     default:
5829         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5830         break;
5831     }
5832 #endif /* defined(CONFIG_USER_ONLY) */
5833 }
5834 
5835 /* TLB management - PowerPC 440 implementation */
5836 
5837 /* tlbre */
5838 static void gen_tlbre_440(DisasContext *ctx)
5839 {
5840 #if defined(CONFIG_USER_ONLY)
5841     GEN_PRIV(ctx);
5842 #else
5843     CHK_SV(ctx);
5844 
5845     switch (rB(ctx->opcode)) {
5846     case 0:
5847     case 1:
5848     case 2:
5849         {
5850             TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
5851             gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5852                                  t0, cpu_gpr[rA(ctx->opcode)]);
5853         }
5854         break;
5855     default:
5856         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5857         break;
5858     }
5859 #endif /* defined(CONFIG_USER_ONLY) */
5860 }
5861 
5862 /* tlbsx - tlbsx. */
5863 static void gen_tlbsx_440(DisasContext *ctx)
5864 {
5865 #if defined(CONFIG_USER_ONLY)
5866     GEN_PRIV(ctx);
5867 #else
5868     TCGv t0;
5869 
5870     CHK_SV(ctx);
5871     t0 = tcg_temp_new();
5872     gen_addr_reg_index(ctx, t0);
5873     gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5874     if (Rc(ctx->opcode)) {
5875         TCGLabel *l1 = gen_new_label();
5876         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5877         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5878         tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5879         gen_set_label(l1);
5880     }
5881 #endif /* defined(CONFIG_USER_ONLY) */
5882 }
5883 
5884 /* tlbwe */
5885 static void gen_tlbwe_440(DisasContext *ctx)
5886 {
5887 #if defined(CONFIG_USER_ONLY)
5888     GEN_PRIV(ctx);
5889 #else
5890     CHK_SV(ctx);
5891     switch (rB(ctx->opcode)) {
5892     case 0:
5893     case 1:
5894     case 2:
5895         {
5896             TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
5897             gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5898                                  cpu_gpr[rS(ctx->opcode)]);
5899         }
5900         break;
5901     default:
5902         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5903         break;
5904     }
5905 #endif /* defined(CONFIG_USER_ONLY) */
5906 }
5907 
5908 /* TLB management - PowerPC BookE 2.06 implementation */
5909 
5910 /* tlbre */
5911 static void gen_tlbre_booke206(DisasContext *ctx)
5912 {
5913  #if defined(CONFIG_USER_ONLY)
5914     GEN_PRIV(ctx);
5915 #else
5916    CHK_SV(ctx);
5917     gen_helper_booke206_tlbre(cpu_env);
5918 #endif /* defined(CONFIG_USER_ONLY) */
5919 }
5920 
5921 /* tlbsx - tlbsx. */
5922 static void gen_tlbsx_booke206(DisasContext *ctx)
5923 {
5924 #if defined(CONFIG_USER_ONLY)
5925     GEN_PRIV(ctx);
5926 #else
5927     TCGv t0;
5928 
5929     CHK_SV(ctx);
5930     if (rA(ctx->opcode)) {
5931         t0 = tcg_temp_new();
5932         tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5933     } else {
5934         t0 = cpu_gpr[rB(ctx->opcode)];
5935     }
5936     gen_helper_booke206_tlbsx(cpu_env, t0);
5937 #endif /* defined(CONFIG_USER_ONLY) */
5938 }
5939 
5940 /* tlbwe */
5941 static void gen_tlbwe_booke206(DisasContext *ctx)
5942 {
5943 #if defined(CONFIG_USER_ONLY)
5944     GEN_PRIV(ctx);
5945 #else
5946     CHK_SV(ctx);
5947     gen_helper_booke206_tlbwe(cpu_env);
5948 #endif /* defined(CONFIG_USER_ONLY) */
5949 }
5950 
5951 static void gen_tlbivax_booke206(DisasContext *ctx)
5952 {
5953 #if defined(CONFIG_USER_ONLY)
5954     GEN_PRIV(ctx);
5955 #else
5956     TCGv t0;
5957 
5958     CHK_SV(ctx);
5959     t0 = tcg_temp_new();
5960     gen_addr_reg_index(ctx, t0);
5961     gen_helper_booke206_tlbivax(cpu_env, t0);
5962 #endif /* defined(CONFIG_USER_ONLY) */
5963 }
5964 
5965 static void gen_tlbilx_booke206(DisasContext *ctx)
5966 {
5967 #if defined(CONFIG_USER_ONLY)
5968     GEN_PRIV(ctx);
5969 #else
5970     TCGv t0;
5971 
5972     CHK_SV(ctx);
5973     t0 = tcg_temp_new();
5974     gen_addr_reg_index(ctx, t0);
5975 
5976     switch ((ctx->opcode >> 21) & 0x3) {
5977     case 0:
5978         gen_helper_booke206_tlbilx0(cpu_env, t0);
5979         break;
5980     case 1:
5981         gen_helper_booke206_tlbilx1(cpu_env, t0);
5982         break;
5983     case 3:
5984         gen_helper_booke206_tlbilx3(cpu_env, t0);
5985         break;
5986     default:
5987         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5988         break;
5989     }
5990 #endif /* defined(CONFIG_USER_ONLY) */
5991 }
5992 
5993 /* wrtee */
5994 static void gen_wrtee(DisasContext *ctx)
5995 {
5996 #if defined(CONFIG_USER_ONLY)
5997     GEN_PRIV(ctx);
5998 #else
5999     TCGv t0;
6000 
6001     CHK_SV(ctx);
6002     t0 = tcg_temp_new();
6003     tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6004     tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6005     tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6006     gen_ppc_maybe_interrupt(ctx);
6007     /*
6008      * Stop translation to have a chance to raise an exception if we
6009      * just set msr_ee to 1
6010      */
6011     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
6012 #endif /* defined(CONFIG_USER_ONLY) */
6013 }
6014 
6015 /* wrteei */
6016 static void gen_wrteei(DisasContext *ctx)
6017 {
6018 #if defined(CONFIG_USER_ONLY)
6019     GEN_PRIV(ctx);
6020 #else
6021     CHK_SV(ctx);
6022     if (ctx->opcode & 0x00008000) {
6023         tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6024         gen_ppc_maybe_interrupt(ctx);
6025         /* Stop translation to have a chance to raise an exception */
6026         ctx->base.is_jmp = DISAS_EXIT_UPDATE;
6027     } else {
6028         tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6029     }
6030 #endif /* defined(CONFIG_USER_ONLY) */
6031 }
6032 
6033 /* PowerPC 440 specific instructions */
6034 
6035 /* dlmzb */
6036 static void gen_dlmzb(DisasContext *ctx)
6037 {
6038     TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode));
6039     gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6040                      cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6041 }
6042 
6043 /* mbar replaces eieio on 440 */
6044 static void gen_mbar(DisasContext *ctx)
6045 {
6046     /* interpreted as no-op */
6047 }
6048 
6049 /* msync replaces sync on 440 */
6050 static void gen_msync_4xx(DisasContext *ctx)
6051 {
6052     /* Only e500 seems to treat reserved bits as invalid */
6053     if ((ctx->insns_flags2 & PPC2_BOOKE206) &&
6054         (ctx->opcode & 0x03FFF801)) {
6055         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6056     }
6057     /* otherwise interpreted as no-op */
6058 }
6059 
6060 /* icbt */
6061 static void gen_icbt_440(DisasContext *ctx)
6062 {
6063     /*
6064      * interpreted as no-op
6065      * XXX: specification say this is treated as a load by the MMU but
6066      *      does not generate any exception
6067      */
6068 }
6069 
6070 #if defined(TARGET_PPC64)
6071 static void gen_maddld(DisasContext *ctx)
6072 {
6073     TCGv_i64 t1 = tcg_temp_new_i64();
6074 
6075     tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6076     tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6077 }
6078 
6079 /* maddhd maddhdu */
6080 static void gen_maddhd_maddhdu(DisasContext *ctx)
6081 {
6082     TCGv_i64 lo = tcg_temp_new_i64();
6083     TCGv_i64 hi = tcg_temp_new_i64();
6084     TCGv_i64 t1 = tcg_temp_new_i64();
6085 
6086     if (Rc(ctx->opcode)) {
6087         tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6088                           cpu_gpr[rB(ctx->opcode)]);
6089         tcg_gen_movi_i64(t1, 0);
6090     } else {
6091         tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6092                           cpu_gpr[rB(ctx->opcode)]);
6093         tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6094     }
6095     tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6096                      cpu_gpr[rC(ctx->opcode)], t1);
6097 }
6098 #endif /* defined(TARGET_PPC64) */
6099 
6100 static void gen_tbegin(DisasContext *ctx)
6101 {
6102     if (unlikely(!ctx->tm_enabled)) {
6103         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6104         return;
6105     }
6106     gen_helper_tbegin(cpu_env);
6107 }
6108 
6109 #define GEN_TM_NOOP(name)                                      \
6110 static inline void gen_##name(DisasContext *ctx)               \
6111 {                                                              \
6112     if (unlikely(!ctx->tm_enabled)) {                          \
6113         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);   \
6114         return;                                                \
6115     }                                                          \
6116     /*                                                         \
6117      * Because tbegin always fails in QEMU, these user         \
6118      * space instructions all have a simple implementation:    \
6119      *                                                         \
6120      *     CR[0] = 0b0 || MSR[TS] || 0b0                       \
6121      *           = 0b0 || 0b00    || 0b0                       \
6122      */                                                        \
6123     tcg_gen_movi_i32(cpu_crf[0], 0);                           \
6124 }
6125 
6126 GEN_TM_NOOP(tend);
6127 GEN_TM_NOOP(tabort);
6128 GEN_TM_NOOP(tabortwc);
6129 GEN_TM_NOOP(tabortwci);
6130 GEN_TM_NOOP(tabortdc);
6131 GEN_TM_NOOP(tabortdci);
6132 GEN_TM_NOOP(tsr);
6133 
6134 static inline void gen_cp_abort(DisasContext *ctx)
6135 {
6136     /* Do Nothing */
6137 }
6138 
6139 #define GEN_CP_PASTE_NOOP(name)                           \
6140 static inline void gen_##name(DisasContext *ctx)          \
6141 {                                                         \
6142     /*                                                    \
6143      * Generate invalid exception until we have an        \
6144      * implementation of the copy paste facility          \
6145      */                                                   \
6146     gen_invalid(ctx);                                     \
6147 }
6148 
6149 GEN_CP_PASTE_NOOP(copy)
6150 GEN_CP_PASTE_NOOP(paste)
6151 
6152 static void gen_tcheck(DisasContext *ctx)
6153 {
6154     if (unlikely(!ctx->tm_enabled)) {
6155         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6156         return;
6157     }
6158     /*
6159      * Because tbegin always fails, the tcheck implementation is
6160      * simple:
6161      *
6162      * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6163      *         = 0b1 || 0b00 || 0b0
6164      */
6165     tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6166 }
6167 
6168 #if defined(CONFIG_USER_ONLY)
6169 #define GEN_TM_PRIV_NOOP(name)                                 \
6170 static inline void gen_##name(DisasContext *ctx)               \
6171 {                                                              \
6172     gen_priv_opc(ctx);                                         \
6173 }
6174 
6175 #else
6176 
6177 #define GEN_TM_PRIV_NOOP(name)                                 \
6178 static inline void gen_##name(DisasContext *ctx)               \
6179 {                                                              \
6180     CHK_SV(ctx);                                               \
6181     if (unlikely(!ctx->tm_enabled)) {                          \
6182         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);   \
6183         return;                                                \
6184     }                                                          \
6185     /*                                                         \
6186      * Because tbegin always fails, the implementation is      \
6187      * simple:                                                 \
6188      *                                                         \
6189      *   CR[0] = 0b0 || MSR[TS] || 0b0                         \
6190      *         = 0b0 || 0b00 | 0b0                             \
6191      */                                                        \
6192     tcg_gen_movi_i32(cpu_crf[0], 0);                           \
6193 }
6194 
6195 #endif
6196 
6197 GEN_TM_PRIV_NOOP(treclaim);
6198 GEN_TM_PRIV_NOOP(trechkpt);
6199 
6200 static inline void get_fpr(TCGv_i64 dst, int regno)
6201 {
6202     tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
6203 }
6204 
6205 static inline void set_fpr(int regno, TCGv_i64 src)
6206 {
6207     tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
6208     /*
6209      * Before PowerISA v3.1 the result of doubleword 1 of the VSR
6210      * corresponding to the target FPR was undefined. However,
6211      * most (if not all) real hardware were setting the result to 0.
6212      * Starting at ISA v3.1, the result for doubleword 1 is now defined
6213      * to be 0.
6214      */
6215     tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false));
6216 }
6217 
6218 static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
6219 {
6220     tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high));
6221 }
6222 
6223 static inline void set_avr64(int regno, TCGv_i64 src, bool high)
6224 {
6225     tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
6226 }
6227 
6228 /*
6229  * Helpers for decodetree used by !function for decoding arguments.
6230  */
6231 static int times_2(DisasContext *ctx, int x)
6232 {
6233     return x * 2;
6234 }
6235 
6236 static int times_4(DisasContext *ctx, int x)
6237 {
6238     return x * 4;
6239 }
6240 
6241 static int times_16(DisasContext *ctx, int x)
6242 {
6243     return x * 16;
6244 }
6245 
6246 static int64_t dw_compose_ea(DisasContext *ctx, int x)
6247 {
6248     return deposit64(0xfffffffffffffe00, 3, 6, x);
6249 }
6250 
6251 /*
6252  * Helpers for trans_* functions to check for specific insns flags.
6253  * Use token pasting to ensure that we use the proper flag with the
6254  * proper variable.
6255  */
6256 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \
6257     do {                                                \
6258         if (((CTX)->insns_flags & PPC_##NAME) == 0) {   \
6259             return false;                               \
6260         }                                               \
6261     } while (0)
6262 
6263 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
6264     do {                                                \
6265         if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
6266             return false;                               \
6267         }                                               \
6268     } while (0)
6269 
6270 /* Then special-case the check for 64-bit so that we elide code for ppc32. */
6271 #if TARGET_LONG_BITS == 32
6272 # define REQUIRE_64BIT(CTX)  return false
6273 #else
6274 # define REQUIRE_64BIT(CTX)  REQUIRE_INSNS_FLAGS(CTX, 64B)
6275 #endif
6276 
6277 #define REQUIRE_VECTOR(CTX)                             \
6278     do {                                                \
6279         if (unlikely(!(CTX)->altivec_enabled)) {        \
6280             gen_exception((CTX), POWERPC_EXCP_VPU);     \
6281             return true;                                \
6282         }                                               \
6283     } while (0)
6284 
6285 #define REQUIRE_VSX(CTX)                                \
6286     do {                                                \
6287         if (unlikely(!(CTX)->vsx_enabled)) {            \
6288             gen_exception((CTX), POWERPC_EXCP_VSXU);    \
6289             return true;                                \
6290         }                                               \
6291     } while (0)
6292 
6293 #define REQUIRE_FPU(ctx)                                \
6294     do {                                                \
6295         if (unlikely(!(ctx)->fpu_enabled)) {            \
6296             gen_exception((ctx), POWERPC_EXCP_FPU);     \
6297             return true;                                \
6298         }                                               \
6299     } while (0)
6300 
6301 #if !defined(CONFIG_USER_ONLY)
6302 #define REQUIRE_SV(CTX)             \
6303     do {                            \
6304         if (unlikely((CTX)->pr)) {  \
6305             gen_priv_opc(CTX);      \
6306             return true;            \
6307         }                           \
6308     } while (0)
6309 
6310 #define REQUIRE_HV(CTX)                             \
6311     do {                                            \
6312         if (unlikely((CTX)->pr || !(CTX)->hv)) {    \
6313             gen_priv_opc(CTX);                      \
6314             return true;                            \
6315         }                                           \
6316     } while (0)
6317 #else
6318 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
6319 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
6320 #endif
6321 
6322 /*
6323  * Helpers for implementing sets of trans_* functions.
6324  * Defer the implementation of NAME to FUNC, with optional extra arguments.
6325  */
6326 #define TRANS(NAME, FUNC, ...) \
6327     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6328     { return FUNC(ctx, a, __VA_ARGS__); }
6329 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \
6330     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6331     {                                                          \
6332         REQUIRE_INSNS_FLAGS(ctx, FLAGS);                       \
6333         return FUNC(ctx, a, __VA_ARGS__);                      \
6334     }
6335 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \
6336     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6337     {                                                          \
6338         REQUIRE_INSNS_FLAGS2(ctx, FLAGS2);                     \
6339         return FUNC(ctx, a, __VA_ARGS__);                      \
6340     }
6341 
6342 #define TRANS64(NAME, FUNC, ...) \
6343     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6344     { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
6345 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \
6346     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6347     {                                                          \
6348         REQUIRE_64BIT(ctx);                                    \
6349         REQUIRE_INSNS_FLAGS2(ctx, FLAGS2);                     \
6350         return FUNC(ctx, a, __VA_ARGS__);                      \
6351     }
6352 
6353 /* TODO: More TRANS* helpers for extra insn_flags checks. */
6354 
6355 
6356 #include "decode-insn32.c.inc"
6357 #include "decode-insn64.c.inc"
6358 #include "power8-pmu-regs.c.inc"
6359 
6360 /*
6361  * Incorporate CIA into the constant when R=1.
6362  * Validate that when R=1, RA=0.
6363  */
6364 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
6365 {
6366     d->rt = a->rt;
6367     d->ra = a->ra;
6368     d->si = a->si;
6369     if (a->r) {
6370         if (unlikely(a->ra != 0)) {
6371             gen_invalid(ctx);
6372             return false;
6373         }
6374         d->si += ctx->cia;
6375     }
6376     return true;
6377 }
6378 
6379 #include "translate/fixedpoint-impl.c.inc"
6380 
6381 #include "translate/fp-impl.c.inc"
6382 
6383 #include "translate/vmx-impl.c.inc"
6384 
6385 #include "translate/vsx-impl.c.inc"
6386 
6387 #include "translate/dfp-impl.c.inc"
6388 
6389 #include "translate/spe-impl.c.inc"
6390 
6391 #include "translate/branch-impl.c.inc"
6392 
6393 #include "translate/processor-ctrl-impl.c.inc"
6394 
6395 #include "translate/storage-ctrl-impl.c.inc"
6396 
6397 /* Handles lfdp */
6398 static void gen_dform39(DisasContext *ctx)
6399 {
6400     if ((ctx->opcode & 0x3) == 0) {
6401         if (ctx->insns_flags2 & PPC2_ISA205) {
6402             return gen_lfdp(ctx);
6403         }
6404     }
6405     return gen_invalid(ctx);
6406 }
6407 
6408 /* Handles stfdp */
6409 static void gen_dform3D(DisasContext *ctx)
6410 {
6411     if ((ctx->opcode & 3) == 0) { /* DS-FORM */
6412         /* stfdp */
6413         if (ctx->insns_flags2 & PPC2_ISA205) {
6414             return gen_stfdp(ctx);
6415         }
6416     }
6417     return gen_invalid(ctx);
6418 }
6419 
6420 #if defined(TARGET_PPC64)
6421 /* brd */
6422 static void gen_brd(DisasContext *ctx)
6423 {
6424     tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6425 }
6426 
6427 /* brw */
6428 static void gen_brw(DisasContext *ctx)
6429 {
6430     tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6431     tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
6432 
6433 }
6434 
6435 /* brh */
6436 static void gen_brh(DisasContext *ctx)
6437 {
6438     TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull);
6439     TCGv_i64 t1 = tcg_temp_new_i64();
6440     TCGv_i64 t2 = tcg_temp_new_i64();
6441 
6442     tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
6443     tcg_gen_and_i64(t2, t1, mask);
6444     tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask);
6445     tcg_gen_shli_i64(t1, t1, 8);
6446     tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
6447 }
6448 #endif
6449 
6450 static opcode_t opcodes[] = {
6451 #if defined(TARGET_PPC64)
6452 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
6453 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
6454 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
6455 #endif
6456 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6457 #if defined(TARGET_PPC64)
6458 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6459 #endif
6460 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6461 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6462 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6463 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6464 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6465 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6466 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6467 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6468 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6469 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6470 #if defined(TARGET_PPC64)
6471 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6472 #endif
6473 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6474 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6475 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6476 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6477 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6478 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6479 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6480 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6481 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6482 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6483 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6484 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6485 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6486 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6487 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6488 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6489 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6490 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6491 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6492 #if defined(TARGET_PPC64)
6493 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6494 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6495 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6496 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6497 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6498 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6499 #endif
6500 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6501 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6502 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6503 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6504 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6505 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6506 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6507 #if defined(TARGET_PPC64)
6508 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6509 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6510 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6511 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6512 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6513 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6514                PPC_NONE, PPC2_ISA300),
6515 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6516                PPC_NONE, PPC2_ISA300),
6517 #endif
6518 /* handles lfdp, lxsd, lxssp */
6519 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6520 /* handles stfdp, stxsd, stxssp */
6521 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6522 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6523 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6524 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6525 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6526 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6527 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6528 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
6529 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6530 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6531 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6532 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6533 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6534 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6535 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6536 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6537 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6538 #if defined(TARGET_PPC64)
6539 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6540 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6541 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6542 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6543 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6544 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6545 #endif
6546 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6547 /* ISA v3.0 changed the extended opcode from 62 to 30 */
6548 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT),
6549 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300),
6550 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6551 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6552 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6553 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6554 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6555 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6556 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6557 #if defined(TARGET_PPC64)
6558 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6559 #if !defined(CONFIG_USER_ONLY)
6560 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
6561 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
6562 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
6563 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300),
6564 #endif
6565 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6566 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6567 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6568 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6569 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6570 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6571 #endif
6572 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
6573 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
6574 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
6575 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6576 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6577 #if defined(TARGET_PPC64)
6578 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6579 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6580 #endif
6581 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6582 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6583 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6584 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6585 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6586 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6587 #if defined(TARGET_PPC64)
6588 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6589 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6590 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6591 #endif
6592 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6593 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6594 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6595 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
6596 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6597 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6598 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
6599 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6600 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
6601 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6602 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
6603 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6604 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6605 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6606 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
6607 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6608 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
6609 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6610 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6611 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
6612 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6613 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6614 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6615 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6616 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6617 #if defined(TARGET_PPC64)
6618 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6619 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6620              PPC_SEGMENT_64B),
6621 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6622 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6623              PPC_SEGMENT_64B),
6624 #endif
6625 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6626 /*
6627  * XXX Those instructions will need to be handled differently for
6628  * different ISA versions
6629  */
6630 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6631 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6632 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6633 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6634 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6635 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6636 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6637 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6638 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6639 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6640 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6641 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6642 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6643 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6644 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6645 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6646 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6647 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6648 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6649 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6650 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6651 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6652 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6653 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6654 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6655 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6656 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6657                PPC_NONE, PPC2_BOOKE206),
6658 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6659                PPC_NONE, PPC2_BOOKE206),
6660 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6661                PPC_NONE, PPC2_BOOKE206),
6662 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6663                PPC_NONE, PPC2_BOOKE206),
6664 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6665                PPC_NONE, PPC2_BOOKE206),
6666 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6667 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6668 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6669 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6670               PPC_BOOKE, PPC2_BOOKE206),
6671 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE),
6672 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6673                PPC_BOOKE, PPC2_BOOKE206),
6674 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
6675              PPC_440_SPEC),
6676 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6677 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6678 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6679 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6680 #if defined(TARGET_PPC64)
6681 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6682               PPC2_ISA300),
6683 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6684 #endif
6685 
6686 #undef GEN_INT_ARITH_ADD
6687 #undef GEN_INT_ARITH_ADD_CONST
6688 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
6689 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6690 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \
6691                                 add_ca, compute_ca, compute_ov)               \
6692 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6693 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6694 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6695 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6696 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6697 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6698 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6699 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6700 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6701 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
6702 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6703 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6704 
6705 #undef GEN_INT_ARITH_DIVW
6706 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
6707 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6708 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6709 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6710 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6711 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6712 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6713 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6714 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6715 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6716 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6717 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6718 
6719 #if defined(TARGET_PPC64)
6720 #undef GEN_INT_ARITH_DIVD
6721 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
6722 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6723 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6724 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6725 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6726 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6727 
6728 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6729 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6730 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6731 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6732 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6733 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6734 
6735 #undef GEN_INT_ARITH_MUL_HELPER
6736 #define GEN_INT_ARITH_MUL_HELPER(name, opc3)                                  \
6737 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6738 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6739 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6740 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6741 #endif
6742 
6743 #undef GEN_INT_ARITH_SUBF
6744 #undef GEN_INT_ARITH_SUBF_CONST
6745 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
6746 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6747 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
6748                                 add_ca, compute_ca, compute_ov)               \
6749 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6750 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6751 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6752 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6753 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6754 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6755 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6756 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6757 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6758 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6759 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6760 
6761 #undef GEN_LOGICAL1
6762 #undef GEN_LOGICAL2
6763 #define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
6764 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6765 #define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
6766 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6767 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6768 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6769 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6770 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6771 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6772 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6773 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6774 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6775 #if defined(TARGET_PPC64)
6776 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6777 #endif
6778 
6779 #if defined(TARGET_PPC64)
6780 #undef GEN_PPC64_R2
6781 #undef GEN_PPC64_R4
6782 #define GEN_PPC64_R2(name, opc1, opc2)                                        \
6783 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6784 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
6785              PPC_64B)
6786 #define GEN_PPC64_R4(name, opc1, opc2)                                        \
6787 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6788 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
6789              PPC_64B),                                                        \
6790 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
6791              PPC_64B),                                                        \
6792 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
6793              PPC_64B)
6794 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6795 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6796 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6797 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6798 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6799 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6800 #endif
6801 
6802 #undef GEN_LDX_E
6803 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk)                   \
6804 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6805 
6806 #if defined(TARGET_PPC64)
6807 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6808 
6809 /* HV/P7 and later only */
6810 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6811 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6812 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6813 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6814 #endif
6815 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6816 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6817 
6818 /* External PID based load */
6819 #undef GEN_LDEPX
6820 #define GEN_LDEPX(name, ldop, opc2, opc3)                                     \
6821 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3,                                    \
6822               0x00000001, PPC_NONE, PPC2_BOOKE206),
6823 
6824 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
6825 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
6826 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
6827 #if defined(TARGET_PPC64)
6828 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)
6829 #endif
6830 
6831 #undef GEN_STX_E
6832 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk)                   \
6833 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
6834 
6835 #if defined(TARGET_PPC64)
6836 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6837 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6838 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6839 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6840 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6841 #endif
6842 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6843 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6844 
6845 #undef GEN_STEPX
6846 #define GEN_STEPX(name, ldop, opc2, opc3)                                     \
6847 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3,                                    \
6848               0x00000001, PPC_NONE, PPC2_BOOKE206),
6849 
6850 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
6851 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
6852 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
6853 #if defined(TARGET_PPC64)
6854 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04)
6855 #endif
6856 
6857 #undef GEN_CRLOGIC
6858 #define GEN_CRLOGIC(name, tcg_op, opc)                                        \
6859 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6860 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6861 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6862 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6863 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6864 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6865 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6866 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6867 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6868 
6869 #undef GEN_MAC_HANDLER
6870 #define GEN_MAC_HANDLER(name, opc2, opc3)                                     \
6871 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6872 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6873 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6874 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6875 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6876 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6877 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6878 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6879 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6880 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6881 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6882 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6883 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6884 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6885 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6886 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6887 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6888 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6889 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6890 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6891 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6892 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6893 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6894 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6895 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6896 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6897 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6898 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6899 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6900 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6901 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6902 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6903 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6904 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6905 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6906 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6907 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6908 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6909 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6910 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6911 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6912 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6913 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6914 
6915 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6916                PPC_NONE, PPC2_TM),
6917 GEN_HANDLER2_E(tend,   "tend",   0x1F, 0x0E, 0x15, 0x01FFF800, \
6918                PPC_NONE, PPC2_TM),
6919 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6920                PPC_NONE, PPC2_TM),
6921 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6922                PPC_NONE, PPC2_TM),
6923 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6924                PPC_NONE, PPC2_TM),
6925 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6926                PPC_NONE, PPC2_TM),
6927 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6928                PPC_NONE, PPC2_TM),
6929 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6930                PPC_NONE, PPC2_TM),
6931 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6932                PPC_NONE, PPC2_TM),
6933 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6934                PPC_NONE, PPC2_TM),
6935 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6936                PPC_NONE, PPC2_TM),
6937 
6938 #include "translate/fp-ops.c.inc"
6939 
6940 #include "translate/vmx-ops.c.inc"
6941 
6942 #include "translate/vsx-ops.c.inc"
6943 
6944 #include "translate/spe-ops.c.inc"
6945 };
6946 
6947 /*****************************************************************************/
6948 /* Opcode types */
6949 enum {
6950     PPC_DIRECT   = 0, /* Opcode routine        */
6951     PPC_INDIRECT = 1, /* Indirect opcode table */
6952 };
6953 
6954 #define PPC_OPCODE_MASK 0x3
6955 
6956 static inline int is_indirect_opcode(void *handler)
6957 {
6958     return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
6959 }
6960 
6961 static inline opc_handler_t **ind_table(void *handler)
6962 {
6963     return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
6964 }
6965 
6966 /* Instruction table creation */
6967 /* Opcodes tables creation */
6968 static void fill_new_table(opc_handler_t **table, int len)
6969 {
6970     int i;
6971 
6972     for (i = 0; i < len; i++) {
6973         table[i] = &invalid_handler;
6974     }
6975 }
6976 
6977 static int create_new_table(opc_handler_t **table, unsigned char idx)
6978 {
6979     opc_handler_t **tmp;
6980 
6981     tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
6982     fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
6983     table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
6984 
6985     return 0;
6986 }
6987 
6988 static int insert_in_table(opc_handler_t **table, unsigned char idx,
6989                             opc_handler_t *handler)
6990 {
6991     if (table[idx] != &invalid_handler) {
6992         return -1;
6993     }
6994     table[idx] = handler;
6995 
6996     return 0;
6997 }
6998 
6999 static int register_direct_insn(opc_handler_t **ppc_opcodes,
7000                                 unsigned char idx, opc_handler_t *handler)
7001 {
7002     if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
7003         printf("*** ERROR: opcode %02x already assigned in main "
7004                "opcode table\n", idx);
7005         return -1;
7006     }
7007 
7008     return 0;
7009 }
7010 
7011 static int register_ind_in_table(opc_handler_t **table,
7012                                  unsigned char idx1, unsigned char idx2,
7013                                  opc_handler_t *handler)
7014 {
7015     if (table[idx1] == &invalid_handler) {
7016         if (create_new_table(table, idx1) < 0) {
7017             printf("*** ERROR: unable to create indirect table "
7018                    "idx=%02x\n", idx1);
7019             return -1;
7020         }
7021     } else {
7022         if (!is_indirect_opcode(table[idx1])) {
7023             printf("*** ERROR: idx %02x already assigned to a direct "
7024                    "opcode\n", idx1);
7025             return -1;
7026         }
7027     }
7028     if (handler != NULL &&
7029         insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
7030         printf("*** ERROR: opcode %02x already assigned in "
7031                "opcode table %02x\n", idx2, idx1);
7032         return -1;
7033     }
7034 
7035     return 0;
7036 }
7037 
7038 static int register_ind_insn(opc_handler_t **ppc_opcodes,
7039                              unsigned char idx1, unsigned char idx2,
7040                              opc_handler_t *handler)
7041 {
7042     return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
7043 }
7044 
7045 static int register_dblind_insn(opc_handler_t **ppc_opcodes,
7046                                 unsigned char idx1, unsigned char idx2,
7047                                 unsigned char idx3, opc_handler_t *handler)
7048 {
7049     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7050         printf("*** ERROR: unable to join indirect table idx "
7051                "[%02x-%02x]\n", idx1, idx2);
7052         return -1;
7053     }
7054     if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7055                               handler) < 0) {
7056         printf("*** ERROR: unable to insert opcode "
7057                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7058         return -1;
7059     }
7060 
7061     return 0;
7062 }
7063 
7064 static int register_trplind_insn(opc_handler_t **ppc_opcodes,
7065                                  unsigned char idx1, unsigned char idx2,
7066                                  unsigned char idx3, unsigned char idx4,
7067                                  opc_handler_t *handler)
7068 {
7069     opc_handler_t **table;
7070 
7071     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7072         printf("*** ERROR: unable to join indirect table idx "
7073                "[%02x-%02x]\n", idx1, idx2);
7074         return -1;
7075     }
7076     table = ind_table(ppc_opcodes[idx1]);
7077     if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
7078         printf("*** ERROR: unable to join 2nd-level indirect table idx "
7079                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7080         return -1;
7081     }
7082     table = ind_table(table[idx2]);
7083     if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
7084         printf("*** ERROR: unable to insert opcode "
7085                "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
7086         return -1;
7087     }
7088     return 0;
7089 }
7090 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
7091 {
7092     if (insn->opc2 != 0xFF) {
7093         if (insn->opc3 != 0xFF) {
7094             if (insn->opc4 != 0xFF) {
7095                 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7096                                           insn->opc3, insn->opc4,
7097                                           &insn->handler) < 0) {
7098                     return -1;
7099                 }
7100             } else {
7101                 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7102                                          insn->opc3, &insn->handler) < 0) {
7103                     return -1;
7104                 }
7105             }
7106         } else {
7107             if (register_ind_insn(ppc_opcodes, insn->opc1,
7108                                   insn->opc2, &insn->handler) < 0) {
7109                 return -1;
7110             }
7111         }
7112     } else {
7113         if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
7114             return -1;
7115         }
7116     }
7117 
7118     return 0;
7119 }
7120 
7121 static int test_opcode_table(opc_handler_t **table, int len)
7122 {
7123     int i, count, tmp;
7124 
7125     for (i = 0, count = 0; i < len; i++) {
7126         /* Consistency fixup */
7127         if (table[i] == NULL) {
7128             table[i] = &invalid_handler;
7129         }
7130         if (table[i] != &invalid_handler) {
7131             if (is_indirect_opcode(table[i])) {
7132                 tmp = test_opcode_table(ind_table(table[i]),
7133                     PPC_CPU_INDIRECT_OPCODES_LEN);
7134                 if (tmp == 0) {
7135                     free(table[i]);
7136                     table[i] = &invalid_handler;
7137                 } else {
7138                     count++;
7139                 }
7140             } else {
7141                 count++;
7142             }
7143         }
7144     }
7145 
7146     return count;
7147 }
7148 
7149 static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
7150 {
7151     if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
7152         printf("*** WARNING: no opcode defined !\n");
7153     }
7154 }
7155 
7156 /*****************************************************************************/
7157 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
7158 {
7159     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7160     opcode_t *opc;
7161 
7162     fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN);
7163     for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
7164         if (((opc->handler.type & pcc->insns_flags) != 0) ||
7165             ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
7166             if (register_insn(cpu->opcodes, opc) < 0) {
7167                 error_setg(errp, "ERROR initializing PowerPC instruction "
7168                            "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
7169                            opc->opc3);
7170                 return;
7171             }
7172         }
7173     }
7174     fix_opcode_tables(cpu->opcodes);
7175     fflush(stdout);
7176     fflush(stderr);
7177 }
7178 
7179 void destroy_ppc_opcodes(PowerPCCPU *cpu)
7180 {
7181     opc_handler_t **table, **table_2;
7182     int i, j, k;
7183 
7184     for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
7185         if (cpu->opcodes[i] == &invalid_handler) {
7186             continue;
7187         }
7188         if (is_indirect_opcode(cpu->opcodes[i])) {
7189             table = ind_table(cpu->opcodes[i]);
7190             for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
7191                 if (table[j] == &invalid_handler) {
7192                     continue;
7193                 }
7194                 if (is_indirect_opcode(table[j])) {
7195                     table_2 = ind_table(table[j]);
7196                     for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
7197                         if (table_2[k] != &invalid_handler &&
7198                             is_indirect_opcode(table_2[k])) {
7199                             g_free((opc_handler_t *)((uintptr_t)table_2[k] &
7200                                                      ~PPC_INDIRECT));
7201                         }
7202                     }
7203                     g_free((opc_handler_t *)((uintptr_t)table[j] &
7204                                              ~PPC_INDIRECT));
7205                 }
7206             }
7207             g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
7208                 ~PPC_INDIRECT));
7209         }
7210     }
7211 }
7212 
7213 int ppc_fixup_cpu(PowerPCCPU *cpu)
7214 {
7215     CPUPPCState *env = &cpu->env;
7216 
7217     /*
7218      * TCG doesn't (yet) emulate some groups of instructions that are
7219      * implemented on some otherwise supported CPUs (e.g. VSX and
7220      * decimal floating point instructions on POWER7).  We remove
7221      * unsupported instruction groups from the cpu state's instruction
7222      * masks and hope the guest can cope.  For at least the pseries
7223      * machine, the unavailability of these instructions can be
7224      * advertised to the guest via the device tree.
7225      */
7226     if ((env->insns_flags & ~PPC_TCG_INSNS)
7227         || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
7228         warn_report("Disabling some instructions which are not "
7229                     "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
7230                     env->insns_flags & ~PPC_TCG_INSNS,
7231                     env->insns_flags2 & ~PPC_TCG_INSNS2);
7232     }
7233     env->insns_flags &= PPC_TCG_INSNS;
7234     env->insns_flags2 &= PPC_TCG_INSNS2;
7235     return 0;
7236 }
7237 
7238 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn)
7239 {
7240     opc_handler_t **table, *handler;
7241     uint32_t inval;
7242 
7243     ctx->opcode = insn;
7244 
7245     LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7246               insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn),
7247               ctx->le_mode ? "little" : "big");
7248 
7249     table = cpu->opcodes;
7250     handler = table[opc1(insn)];
7251     if (is_indirect_opcode(handler)) {
7252         table = ind_table(handler);
7253         handler = table[opc2(insn)];
7254         if (is_indirect_opcode(handler)) {
7255             table = ind_table(handler);
7256             handler = table[opc3(insn)];
7257             if (is_indirect_opcode(handler)) {
7258                 table = ind_table(handler);
7259                 handler = table[opc4(insn)];
7260             }
7261         }
7262     }
7263 
7264     /* Is opcode *REALLY* valid ? */
7265     if (unlikely(handler->handler == &gen_invalid)) {
7266         qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7267                       "%02x - %02x - %02x - %02x (%08x) "
7268                       TARGET_FMT_lx "\n",
7269                       opc1(insn), opc2(insn), opc3(insn), opc4(insn),
7270                       insn, ctx->cia);
7271         return false;
7272     }
7273 
7274     if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
7275                  && Rc(insn))) {
7276         inval = handler->inval2;
7277     } else {
7278         inval = handler->inval1;
7279     }
7280 
7281     if (unlikely((insn & inval) != 0)) {
7282         qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7283                       "%02x - %02x - %02x - %02x (%08x) "
7284                       TARGET_FMT_lx "\n", insn & inval,
7285                       opc1(insn), opc2(insn), opc3(insn), opc4(insn),
7286                       insn, ctx->cia);
7287         return false;
7288     }
7289 
7290     handler->handler(ctx);
7291     return true;
7292 }
7293 
7294 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7295 {
7296     DisasContext *ctx = container_of(dcbase, DisasContext, base);
7297     CPUPPCState *env = cs->env_ptr;
7298     uint32_t hflags = ctx->base.tb->flags;
7299 
7300     ctx->spr_cb = env->spr_cb;
7301     ctx->pr = (hflags >> HFLAGS_PR) & 1;
7302     ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
7303     ctx->dr = (hflags >> HFLAGS_DR) & 1;
7304     ctx->hv = (hflags >> HFLAGS_HV) & 1;
7305     ctx->insns_flags = env->insns_flags;
7306     ctx->insns_flags2 = env->insns_flags2;
7307     ctx->access_type = -1;
7308     ctx->need_access_type = !mmu_is_64bit(env->mmu_model);
7309     ctx->le_mode = (hflags >> HFLAGS_LE) & 1;
7310     ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
7311     ctx->flags = env->flags;
7312 #if defined(TARGET_PPC64)
7313     ctx->sf_mode = (hflags >> HFLAGS_64) & 1;
7314     ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7315 #endif
7316     ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
7317         || env->mmu_model & POWERPC_MMU_64;
7318 
7319     ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1;
7320     ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1;
7321     ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
7322     ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
7323     ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
7324     ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
7325     ctx->hr = (hflags >> HFLAGS_HR) & 1;
7326     ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1;
7327     ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1;
7328     ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1;
7329     ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1;
7330     ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1;
7331 
7332     ctx->singlestep_enabled = 0;
7333     if ((hflags >> HFLAGS_SE) & 1) {
7334         ctx->singlestep_enabled |= CPU_SINGLE_STEP;
7335         ctx->base.max_insns = 1;
7336     }
7337     if ((hflags >> HFLAGS_BE) & 1) {
7338         ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7339     }
7340 }
7341 
7342 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
7343 {
7344 }
7345 
7346 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
7347 {
7348     tcg_gen_insn_start(dcbase->pc_next);
7349 }
7350 
7351 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
7352 {
7353     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
7354     return opc1(insn) == 1;
7355 }
7356 
7357 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
7358 {
7359     DisasContext *ctx = container_of(dcbase, DisasContext, base);
7360     PowerPCCPU *cpu = POWERPC_CPU(cs);
7361     CPUPPCState *env = cs->env_ptr;
7362     target_ulong pc;
7363     uint32_t insn;
7364     bool ok;
7365 
7366     LOG_DISAS("----------------\n");
7367     LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7368               ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
7369 
7370     ctx->cia = pc = ctx->base.pc_next;
7371     insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
7372     ctx->base.pc_next = pc += 4;
7373 
7374     if (!is_prefix_insn(ctx, insn)) {
7375         ok = (decode_insn32(ctx, insn) ||
7376               decode_legacy(cpu, ctx, insn));
7377     } else if ((pc & 63) == 0) {
7378         /*
7379          * Power v3.1, section 1.9 Exceptions:
7380          * attempt to execute a prefixed instruction that crosses a
7381          * 64-byte address boundary (system alignment error).
7382          */
7383         gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
7384         ok = true;
7385     } else {
7386         uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
7387                                              need_byteswap(ctx));
7388         ctx->base.pc_next = pc += 4;
7389         ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
7390     }
7391     if (!ok) {
7392         gen_invalid(ctx);
7393     }
7394 
7395     /* End the TB when crossing a page boundary. */
7396     if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) {
7397         ctx->base.is_jmp = DISAS_TOO_MANY;
7398     }
7399 }
7400 
7401 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
7402 {
7403     DisasContext *ctx = container_of(dcbase, DisasContext, base);
7404     DisasJumpType is_jmp = ctx->base.is_jmp;
7405     target_ulong nip = ctx->base.pc_next;
7406 
7407     if (is_jmp == DISAS_NORETURN) {
7408         /* We have already exited the TB. */
7409         return;
7410     }
7411 
7412     /* Honor single stepping. */
7413     if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)
7414         && (nip <= 0x100 || nip > 0xf00)) {
7415         switch (is_jmp) {
7416         case DISAS_TOO_MANY:
7417         case DISAS_EXIT_UPDATE:
7418         case DISAS_CHAIN_UPDATE:
7419             gen_update_nip(ctx, nip);
7420             break;
7421         case DISAS_EXIT:
7422         case DISAS_CHAIN:
7423             break;
7424         default:
7425             g_assert_not_reached();
7426         }
7427 
7428         gen_debug_exception(ctx);
7429         return;
7430     }
7431 
7432     switch (is_jmp) {
7433     case DISAS_TOO_MANY:
7434         if (use_goto_tb(ctx, nip)) {
7435             pmu_count_insns(ctx);
7436             tcg_gen_goto_tb(0);
7437             gen_update_nip(ctx, nip);
7438             tcg_gen_exit_tb(ctx->base.tb, 0);
7439             break;
7440         }
7441         /* fall through */
7442     case DISAS_CHAIN_UPDATE:
7443         gen_update_nip(ctx, nip);
7444         /* fall through */
7445     case DISAS_CHAIN:
7446         /*
7447          * tcg_gen_lookup_and_goto_ptr will exit the TB if
7448          * CF_NO_GOTO_PTR is set. Count insns now.
7449          */
7450         if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
7451             pmu_count_insns(ctx);
7452         }
7453 
7454         tcg_gen_lookup_and_goto_ptr();
7455         break;
7456 
7457     case DISAS_EXIT_UPDATE:
7458         gen_update_nip(ctx, nip);
7459         /* fall through */
7460     case DISAS_EXIT:
7461         pmu_count_insns(ctx);
7462         tcg_gen_exit_tb(NULL, 0);
7463         break;
7464 
7465     default:
7466         g_assert_not_reached();
7467     }
7468 }
7469 
7470 static void ppc_tr_disas_log(const DisasContextBase *dcbase,
7471                              CPUState *cs, FILE *logfile)
7472 {
7473     fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
7474     target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size);
7475 }
7476 
7477 static const TranslatorOps ppc_tr_ops = {
7478     .init_disas_context = ppc_tr_init_disas_context,
7479     .tb_start           = ppc_tr_tb_start,
7480     .insn_start         = ppc_tr_insn_start,
7481     .translate_insn     = ppc_tr_translate_insn,
7482     .tb_stop            = ppc_tr_tb_stop,
7483     .disas_log          = ppc_tr_disas_log,
7484 };
7485 
7486 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
7487                            target_ulong pc, void *host_pc)
7488 {
7489     DisasContext ctx;
7490 
7491     translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base);
7492 }
7493