1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg-op.h" 27 #include "qemu/host-utils.h" 28 #include "exec/cpu_ldst.h" 29 30 #include "exec/helper-proto.h" 31 #include "exec/helper-gen.h" 32 33 #include "trace-tcg.h" 34 #include "exec/log.h" 35 36 37 #define CPU_SINGLE_STEP 0x1 38 #define CPU_BRANCH_STEP 0x2 39 #define GDBSTUB_SINGLE_STEP 0x4 40 41 /* Include definitions for instructions classes and implementations flags */ 42 //#define PPC_DEBUG_DISAS 43 //#define DO_PPC_STATISTICS 44 45 #ifdef PPC_DEBUG_DISAS 46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 47 #else 48 # define LOG_DISAS(...) do { } while (0) 49 #endif 50 /*****************************************************************************/ 51 /* Code translation helpers */ 52 53 /* global register indexes */ 54 static TCGv_env cpu_env; 55 static char cpu_reg_names[10*3 + 22*4 /* GPR */ 56 + 10*4 + 22*5 /* SPE GPRh */ 57 + 10*4 + 22*5 /* FPR */ 58 + 2*(10*6 + 22*7) /* AVRh, AVRl */ 59 + 10*5 + 22*6 /* VSR */ 60 + 8*5 /* CRF */]; 61 static TCGv cpu_gpr[32]; 62 static TCGv cpu_gprh[32]; 63 static TCGv_i64 cpu_fpr[32]; 64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; 65 static TCGv_i64 cpu_vsr[32]; 66 static TCGv_i32 cpu_crf[8]; 67 static TCGv cpu_nip; 68 static TCGv cpu_msr; 69 static TCGv cpu_ctr; 70 static TCGv cpu_lr; 71 #if defined(TARGET_PPC64) 72 static TCGv cpu_cfar; 73 #endif 74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75 static TCGv cpu_reserve; 76 static TCGv cpu_reserve_val; 77 static TCGv cpu_fpscr; 78 static TCGv_i32 cpu_access_type; 79 80 #include "exec/gen-icount.h" 81 82 void ppc_translate_init(void) 83 { 84 int i; 85 char* p; 86 size_t cpu_reg_names_size; 87 88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 89 tcg_ctx->tcg_env = cpu_env; 90 91 p = cpu_reg_names; 92 cpu_reg_names_size = sizeof(cpu_reg_names); 93 94 for (i = 0; i < 8; i++) { 95 snprintf(p, cpu_reg_names_size, "crf%d", i); 96 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 97 offsetof(CPUPPCState, crf[i]), p); 98 p += 5; 99 cpu_reg_names_size -= 5; 100 } 101 102 for (i = 0; i < 32; i++) { 103 snprintf(p, cpu_reg_names_size, "r%d", i); 104 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 105 offsetof(CPUPPCState, gpr[i]), p); 106 p += (i < 10) ? 3 : 4; 107 cpu_reg_names_size -= (i < 10) ? 3 : 4; 108 snprintf(p, cpu_reg_names_size, "r%dH", i); 109 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 110 offsetof(CPUPPCState, gprh[i]), p); 111 p += (i < 10) ? 4 : 5; 112 cpu_reg_names_size -= (i < 10) ? 4 : 5; 113 114 snprintf(p, cpu_reg_names_size, "fp%d", i); 115 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 116 offsetof(CPUPPCState, fpr[i]), p); 117 p += (i < 10) ? 4 : 5; 118 cpu_reg_names_size -= (i < 10) ? 4 : 5; 119 120 snprintf(p, cpu_reg_names_size, "avr%dH", i); 121 #ifdef HOST_WORDS_BIGENDIAN 122 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 123 offsetof(CPUPPCState, avr[i].u64[0]), p); 124 #else 125 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 126 offsetof(CPUPPCState, avr[i].u64[1]), p); 127 #endif 128 p += (i < 10) ? 6 : 7; 129 cpu_reg_names_size -= (i < 10) ? 6 : 7; 130 131 snprintf(p, cpu_reg_names_size, "avr%dL", i); 132 #ifdef HOST_WORDS_BIGENDIAN 133 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 134 offsetof(CPUPPCState, avr[i].u64[1]), p); 135 #else 136 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 137 offsetof(CPUPPCState, avr[i].u64[0]), p); 138 #endif 139 p += (i < 10) ? 6 : 7; 140 cpu_reg_names_size -= (i < 10) ? 6 : 7; 141 snprintf(p, cpu_reg_names_size, "vsr%d", i); 142 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, 143 offsetof(CPUPPCState, vsr[i]), p); 144 p += (i < 10) ? 5 : 6; 145 cpu_reg_names_size -= (i < 10) ? 5 : 6; 146 } 147 148 cpu_nip = tcg_global_mem_new(cpu_env, 149 offsetof(CPUPPCState, nip), "nip"); 150 151 cpu_msr = tcg_global_mem_new(cpu_env, 152 offsetof(CPUPPCState, msr), "msr"); 153 154 cpu_ctr = tcg_global_mem_new(cpu_env, 155 offsetof(CPUPPCState, ctr), "ctr"); 156 157 cpu_lr = tcg_global_mem_new(cpu_env, 158 offsetof(CPUPPCState, lr), "lr"); 159 160 #if defined(TARGET_PPC64) 161 cpu_cfar = tcg_global_mem_new(cpu_env, 162 offsetof(CPUPPCState, cfar), "cfar"); 163 #endif 164 165 cpu_xer = tcg_global_mem_new(cpu_env, 166 offsetof(CPUPPCState, xer), "xer"); 167 cpu_so = tcg_global_mem_new(cpu_env, 168 offsetof(CPUPPCState, so), "SO"); 169 cpu_ov = tcg_global_mem_new(cpu_env, 170 offsetof(CPUPPCState, ov), "OV"); 171 cpu_ca = tcg_global_mem_new(cpu_env, 172 offsetof(CPUPPCState, ca), "CA"); 173 cpu_ov32 = tcg_global_mem_new(cpu_env, 174 offsetof(CPUPPCState, ov32), "OV32"); 175 cpu_ca32 = tcg_global_mem_new(cpu_env, 176 offsetof(CPUPPCState, ca32), "CA32"); 177 178 cpu_reserve = tcg_global_mem_new(cpu_env, 179 offsetof(CPUPPCState, reserve_addr), 180 "reserve_addr"); 181 cpu_reserve_val = tcg_global_mem_new(cpu_env, 182 offsetof(CPUPPCState, reserve_val), 183 "reserve_val"); 184 185 cpu_fpscr = tcg_global_mem_new(cpu_env, 186 offsetof(CPUPPCState, fpscr), "fpscr"); 187 188 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 189 offsetof(CPUPPCState, access_type), "access_type"); 190 } 191 192 /* internal defines */ 193 struct DisasContext { 194 struct TranslationBlock *tb; 195 target_ulong nip; 196 uint32_t opcode; 197 uint32_t exception; 198 /* Routine used to access memory */ 199 bool pr, hv, dr, le_mode; 200 bool lazy_tlb_flush; 201 bool need_access_type; 202 int mem_idx; 203 int access_type; 204 /* Translation flags */ 205 TCGMemOp default_tcg_memop_mask; 206 #if defined(TARGET_PPC64) 207 bool sf_mode; 208 bool has_cfar; 209 #endif 210 bool fpu_enabled; 211 bool altivec_enabled; 212 bool vsx_enabled; 213 bool spe_enabled; 214 bool tm_enabled; 215 bool gtse; 216 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 217 int singlestep_enabled; 218 uint64_t insns_flags; 219 uint64_t insns_flags2; 220 }; 221 222 /* Return true iff byteswap is needed in a scalar memop */ 223 static inline bool need_byteswap(const DisasContext *ctx) 224 { 225 #if defined(TARGET_WORDS_BIGENDIAN) 226 return ctx->le_mode; 227 #else 228 return !ctx->le_mode; 229 #endif 230 } 231 232 /* True when active word size < size of target_long. */ 233 #ifdef TARGET_PPC64 234 # define NARROW_MODE(C) (!(C)->sf_mode) 235 #else 236 # define NARROW_MODE(C) 0 237 #endif 238 239 struct opc_handler_t { 240 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 241 uint32_t inval1; 242 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 243 uint32_t inval2; 244 /* instruction type */ 245 uint64_t type; 246 /* extended instruction type */ 247 uint64_t type2; 248 /* handler */ 249 void (*handler)(DisasContext *ctx); 250 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 251 const char *oname; 252 #endif 253 #if defined(DO_PPC_STATISTICS) 254 uint64_t count; 255 #endif 256 }; 257 258 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 259 { 260 if (ctx->need_access_type && ctx->access_type != access_type) { 261 tcg_gen_movi_i32(cpu_access_type, access_type); 262 ctx->access_type = access_type; 263 } 264 } 265 266 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 267 { 268 if (NARROW_MODE(ctx)) { 269 nip = (uint32_t)nip; 270 } 271 tcg_gen_movi_tl(cpu_nip, nip); 272 } 273 274 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 275 { 276 TCGv_i32 t0, t1; 277 278 /* These are all synchronous exceptions, we set the PC back to 279 * the faulting instruction 280 */ 281 if (ctx->exception == POWERPC_EXCP_NONE) { 282 gen_update_nip(ctx, ctx->nip - 4); 283 } 284 t0 = tcg_const_i32(excp); 285 t1 = tcg_const_i32(error); 286 gen_helper_raise_exception_err(cpu_env, t0, t1); 287 tcg_temp_free_i32(t0); 288 tcg_temp_free_i32(t1); 289 ctx->exception = (excp); 290 } 291 292 static void gen_exception(DisasContext *ctx, uint32_t excp) 293 { 294 TCGv_i32 t0; 295 296 /* These are all synchronous exceptions, we set the PC back to 297 * the faulting instruction 298 */ 299 if (ctx->exception == POWERPC_EXCP_NONE) { 300 gen_update_nip(ctx, ctx->nip - 4); 301 } 302 t0 = tcg_const_i32(excp); 303 gen_helper_raise_exception(cpu_env, t0); 304 tcg_temp_free_i32(t0); 305 ctx->exception = (excp); 306 } 307 308 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 309 target_ulong nip) 310 { 311 TCGv_i32 t0; 312 313 gen_update_nip(ctx, nip); 314 t0 = tcg_const_i32(excp); 315 gen_helper_raise_exception(cpu_env, t0); 316 tcg_temp_free_i32(t0); 317 ctx->exception = (excp); 318 } 319 320 static void gen_debug_exception(DisasContext *ctx) 321 { 322 TCGv_i32 t0; 323 324 /* These are all synchronous exceptions, we set the PC back to 325 * the faulting instruction 326 */ 327 if ((ctx->exception != POWERPC_EXCP_BRANCH) && 328 (ctx->exception != POWERPC_EXCP_SYNC)) { 329 gen_update_nip(ctx, ctx->nip); 330 } 331 t0 = tcg_const_i32(EXCP_DEBUG); 332 gen_helper_raise_exception(cpu_env, t0); 333 tcg_temp_free_i32(t0); 334 } 335 336 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 337 { 338 /* Will be converted to program check if needed */ 339 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 340 } 341 342 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 343 { 344 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 345 } 346 347 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 348 { 349 /* Will be converted to program check if needed */ 350 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 351 } 352 353 /* Stop translation */ 354 static inline void gen_stop_exception(DisasContext *ctx) 355 { 356 gen_update_nip(ctx, ctx->nip); 357 ctx->exception = POWERPC_EXCP_STOP; 358 } 359 360 #ifndef CONFIG_USER_ONLY 361 /* No need to update nip here, as execution flow will change */ 362 static inline void gen_sync_exception(DisasContext *ctx) 363 { 364 ctx->exception = POWERPC_EXCP_SYNC; 365 } 366 #endif 367 368 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 369 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 370 371 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 372 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 373 374 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 375 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 376 377 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 378 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 379 380 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 381 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 382 383 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 384 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 385 386 typedef struct opcode_t { 387 unsigned char opc1, opc2, opc3, opc4; 388 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 389 unsigned char pad[4]; 390 #endif 391 opc_handler_t handler; 392 const char *oname; 393 } opcode_t; 394 395 /* Helpers for priv. check */ 396 #define GEN_PRIV \ 397 do { \ 398 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 399 } while (0) 400 401 #if defined(CONFIG_USER_ONLY) 402 #define CHK_HV GEN_PRIV 403 #define CHK_SV GEN_PRIV 404 #define CHK_HVRM GEN_PRIV 405 #else 406 #define CHK_HV \ 407 do { \ 408 if (unlikely(ctx->pr || !ctx->hv)) { \ 409 GEN_PRIV; \ 410 } \ 411 } while (0) 412 #define CHK_SV \ 413 do { \ 414 if (unlikely(ctx->pr)) { \ 415 GEN_PRIV; \ 416 } \ 417 } while (0) 418 #define CHK_HVRM \ 419 do { \ 420 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 421 GEN_PRIV; \ 422 } \ 423 } while (0) 424 #endif 425 426 #define CHK_NONE 427 428 /*****************************************************************************/ 429 /* PowerPC instructions table */ 430 431 #if defined(DO_PPC_STATISTICS) 432 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 433 { \ 434 .opc1 = op1, \ 435 .opc2 = op2, \ 436 .opc3 = op3, \ 437 .opc4 = 0xff, \ 438 .handler = { \ 439 .inval1 = invl, \ 440 .type = _typ, \ 441 .type2 = _typ2, \ 442 .handler = &gen_##name, \ 443 .oname = stringify(name), \ 444 }, \ 445 .oname = stringify(name), \ 446 } 447 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 448 { \ 449 .opc1 = op1, \ 450 .opc2 = op2, \ 451 .opc3 = op3, \ 452 .opc4 = 0xff, \ 453 .handler = { \ 454 .inval1 = invl1, \ 455 .inval2 = invl2, \ 456 .type = _typ, \ 457 .type2 = _typ2, \ 458 .handler = &gen_##name, \ 459 .oname = stringify(name), \ 460 }, \ 461 .oname = stringify(name), \ 462 } 463 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 464 { \ 465 .opc1 = op1, \ 466 .opc2 = op2, \ 467 .opc3 = op3, \ 468 .opc4 = 0xff, \ 469 .handler = { \ 470 .inval1 = invl, \ 471 .type = _typ, \ 472 .type2 = _typ2, \ 473 .handler = &gen_##name, \ 474 .oname = onam, \ 475 }, \ 476 .oname = onam, \ 477 } 478 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 479 { \ 480 .opc1 = op1, \ 481 .opc2 = op2, \ 482 .opc3 = op3, \ 483 .opc4 = op4, \ 484 .handler = { \ 485 .inval1 = invl, \ 486 .type = _typ, \ 487 .type2 = _typ2, \ 488 .handler = &gen_##name, \ 489 .oname = stringify(name), \ 490 }, \ 491 .oname = stringify(name), \ 492 } 493 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 494 { \ 495 .opc1 = op1, \ 496 .opc2 = op2, \ 497 .opc3 = op3, \ 498 .opc4 = op4, \ 499 .handler = { \ 500 .inval1 = invl, \ 501 .type = _typ, \ 502 .type2 = _typ2, \ 503 .handler = &gen_##name, \ 504 .oname = onam, \ 505 }, \ 506 .oname = onam, \ 507 } 508 #else 509 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 510 { \ 511 .opc1 = op1, \ 512 .opc2 = op2, \ 513 .opc3 = op3, \ 514 .opc4 = 0xff, \ 515 .handler = { \ 516 .inval1 = invl, \ 517 .type = _typ, \ 518 .type2 = _typ2, \ 519 .handler = &gen_##name, \ 520 }, \ 521 .oname = stringify(name), \ 522 } 523 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 524 { \ 525 .opc1 = op1, \ 526 .opc2 = op2, \ 527 .opc3 = op3, \ 528 .opc4 = 0xff, \ 529 .handler = { \ 530 .inval1 = invl1, \ 531 .inval2 = invl2, \ 532 .type = _typ, \ 533 .type2 = _typ2, \ 534 .handler = &gen_##name, \ 535 }, \ 536 .oname = stringify(name), \ 537 } 538 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 539 { \ 540 .opc1 = op1, \ 541 .opc2 = op2, \ 542 .opc3 = op3, \ 543 .opc4 = 0xff, \ 544 .handler = { \ 545 .inval1 = invl, \ 546 .type = _typ, \ 547 .type2 = _typ2, \ 548 .handler = &gen_##name, \ 549 }, \ 550 .oname = onam, \ 551 } 552 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 553 { \ 554 .opc1 = op1, \ 555 .opc2 = op2, \ 556 .opc3 = op3, \ 557 .opc4 = op4, \ 558 .handler = { \ 559 .inval1 = invl, \ 560 .type = _typ, \ 561 .type2 = _typ2, \ 562 .handler = &gen_##name, \ 563 }, \ 564 .oname = stringify(name), \ 565 } 566 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 567 { \ 568 .opc1 = op1, \ 569 .opc2 = op2, \ 570 .opc3 = op3, \ 571 .opc4 = op4, \ 572 .handler = { \ 573 .inval1 = invl, \ 574 .type = _typ, \ 575 .type2 = _typ2, \ 576 .handler = &gen_##name, \ 577 }, \ 578 .oname = onam, \ 579 } 580 #endif 581 582 /* SPR load/store helpers */ 583 static inline void gen_load_spr(TCGv t, int reg) 584 { 585 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 586 } 587 588 static inline void gen_store_spr(int reg, TCGv t) 589 { 590 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 591 } 592 593 /* Invalid instruction */ 594 static void gen_invalid(DisasContext *ctx) 595 { 596 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 597 } 598 599 static opc_handler_t invalid_handler = { 600 .inval1 = 0xFFFFFFFF, 601 .inval2 = 0xFFFFFFFF, 602 .type = PPC_NONE, 603 .type2 = PPC_NONE, 604 .handler = gen_invalid, 605 }; 606 607 /*** Integer comparison ***/ 608 609 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 610 { 611 TCGv t0 = tcg_temp_new(); 612 TCGv_i32 t1 = tcg_temp_new_i32(); 613 614 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 615 616 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); 617 tcg_gen_trunc_tl_i32(t1, t0); 618 tcg_gen_shli_i32(t1, t1, CRF_LT_BIT); 619 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 620 621 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); 622 tcg_gen_trunc_tl_i32(t1, t0); 623 tcg_gen_shli_i32(t1, t1, CRF_GT_BIT); 624 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 625 626 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); 627 tcg_gen_trunc_tl_i32(t1, t0); 628 tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT); 629 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 630 631 tcg_temp_free(t0); 632 tcg_temp_free_i32(t1); 633 } 634 635 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 636 { 637 TCGv t0 = tcg_const_tl(arg1); 638 gen_op_cmp(arg0, t0, s, crf); 639 tcg_temp_free(t0); 640 } 641 642 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 643 { 644 TCGv t0, t1; 645 t0 = tcg_temp_new(); 646 t1 = tcg_temp_new(); 647 if (s) { 648 tcg_gen_ext32s_tl(t0, arg0); 649 tcg_gen_ext32s_tl(t1, arg1); 650 } else { 651 tcg_gen_ext32u_tl(t0, arg0); 652 tcg_gen_ext32u_tl(t1, arg1); 653 } 654 gen_op_cmp(t0, t1, s, crf); 655 tcg_temp_free(t1); 656 tcg_temp_free(t0); 657 } 658 659 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 660 { 661 TCGv t0 = tcg_const_tl(arg1); 662 gen_op_cmp32(arg0, t0, s, crf); 663 tcg_temp_free(t0); 664 } 665 666 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 667 { 668 if (NARROW_MODE(ctx)) { 669 gen_op_cmpi32(reg, 0, 1, 0); 670 } else { 671 gen_op_cmpi(reg, 0, 1, 0); 672 } 673 } 674 675 /* cmp */ 676 static void gen_cmp(DisasContext *ctx) 677 { 678 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 679 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 680 1, crfD(ctx->opcode)); 681 } else { 682 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 683 1, crfD(ctx->opcode)); 684 } 685 } 686 687 /* cmpi */ 688 static void gen_cmpi(DisasContext *ctx) 689 { 690 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 691 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 692 1, crfD(ctx->opcode)); 693 } else { 694 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 695 1, crfD(ctx->opcode)); 696 } 697 } 698 699 /* cmpl */ 700 static void gen_cmpl(DisasContext *ctx) 701 { 702 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 703 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 704 0, crfD(ctx->opcode)); 705 } else { 706 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 707 0, crfD(ctx->opcode)); 708 } 709 } 710 711 /* cmpli */ 712 static void gen_cmpli(DisasContext *ctx) 713 { 714 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 715 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 716 0, crfD(ctx->opcode)); 717 } else { 718 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 719 0, crfD(ctx->opcode)); 720 } 721 } 722 723 /* cmprb - range comparison: isupper, isaplha, islower*/ 724 static void gen_cmprb(DisasContext *ctx) 725 { 726 TCGv_i32 src1 = tcg_temp_new_i32(); 727 TCGv_i32 src2 = tcg_temp_new_i32(); 728 TCGv_i32 src2lo = tcg_temp_new_i32(); 729 TCGv_i32 src2hi = tcg_temp_new_i32(); 730 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 731 732 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 733 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 734 735 tcg_gen_andi_i32(src1, src1, 0xFF); 736 tcg_gen_ext8u_i32(src2lo, src2); 737 tcg_gen_shri_i32(src2, src2, 8); 738 tcg_gen_ext8u_i32(src2hi, src2); 739 740 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 741 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 742 tcg_gen_and_i32(crf, src2lo, src2hi); 743 744 if (ctx->opcode & 0x00200000) { 745 tcg_gen_shri_i32(src2, src2, 8); 746 tcg_gen_ext8u_i32(src2lo, src2); 747 tcg_gen_shri_i32(src2, src2, 8); 748 tcg_gen_ext8u_i32(src2hi, src2); 749 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 750 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 751 tcg_gen_and_i32(src2lo, src2lo, src2hi); 752 tcg_gen_or_i32(crf, crf, src2lo); 753 } 754 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 755 tcg_temp_free_i32(src1); 756 tcg_temp_free_i32(src2); 757 tcg_temp_free_i32(src2lo); 758 tcg_temp_free_i32(src2hi); 759 } 760 761 #if defined(TARGET_PPC64) 762 /* cmpeqb */ 763 static void gen_cmpeqb(DisasContext *ctx) 764 { 765 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 766 cpu_gpr[rB(ctx->opcode)]); 767 } 768 #endif 769 770 /* isel (PowerPC 2.03 specification) */ 771 static void gen_isel(DisasContext *ctx) 772 { 773 uint32_t bi = rC(ctx->opcode); 774 uint32_t mask = 0x08 >> (bi & 0x03); 775 TCGv t0 = tcg_temp_new(); 776 TCGv zr; 777 778 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 779 tcg_gen_andi_tl(t0, t0, mask); 780 781 zr = tcg_const_tl(0); 782 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 783 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 784 cpu_gpr[rB(ctx->opcode)]); 785 tcg_temp_free(zr); 786 tcg_temp_free(t0); 787 } 788 789 /* cmpb: PowerPC 2.05 specification */ 790 static void gen_cmpb(DisasContext *ctx) 791 { 792 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 793 cpu_gpr[rB(ctx->opcode)]); 794 } 795 796 /*** Integer arithmetic ***/ 797 798 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 799 TCGv arg1, TCGv arg2, int sub) 800 { 801 TCGv t0 = tcg_temp_new(); 802 803 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 804 tcg_gen_xor_tl(t0, arg1, arg2); 805 if (sub) { 806 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 807 } else { 808 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 809 } 810 tcg_temp_free(t0); 811 if (NARROW_MODE(ctx)) { 812 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 813 if (is_isa300(ctx)) { 814 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 815 } 816 } else { 817 if (is_isa300(ctx)) { 818 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 819 } 820 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 821 } 822 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 823 } 824 825 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 826 TCGv res, TCGv arg0, TCGv arg1, 827 int sub) 828 { 829 TCGv t0; 830 831 if (!is_isa300(ctx)) { 832 return; 833 } 834 835 t0 = tcg_temp_new(); 836 if (sub) { 837 tcg_gen_eqv_tl(t0, arg0, arg1); 838 } else { 839 tcg_gen_xor_tl(t0, arg0, arg1); 840 } 841 tcg_gen_xor_tl(t0, t0, res); 842 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1); 843 tcg_temp_free(t0); 844 } 845 846 /* Common add function */ 847 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 848 TCGv arg2, bool add_ca, bool compute_ca, 849 bool compute_ov, bool compute_rc0) 850 { 851 TCGv t0 = ret; 852 853 if (compute_ca || compute_ov) { 854 t0 = tcg_temp_new(); 855 } 856 857 if (compute_ca) { 858 if (NARROW_MODE(ctx)) { 859 /* Caution: a non-obvious corner case of the spec is that we 860 must produce the *entire* 64-bit addition, but produce the 861 carry into bit 32. */ 862 TCGv t1 = tcg_temp_new(); 863 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 864 tcg_gen_add_tl(t0, arg1, arg2); 865 if (add_ca) { 866 tcg_gen_add_tl(t0, t0, cpu_ca); 867 } 868 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ 869 tcg_temp_free(t1); 870 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 871 if (is_isa300(ctx)) { 872 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 873 } 874 } else { 875 TCGv zero = tcg_const_tl(0); 876 if (add_ca) { 877 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); 878 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); 879 } else { 880 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); 881 } 882 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0); 883 tcg_temp_free(zero); 884 } 885 } else { 886 tcg_gen_add_tl(t0, arg1, arg2); 887 if (add_ca) { 888 tcg_gen_add_tl(t0, t0, cpu_ca); 889 } 890 } 891 892 if (compute_ov) { 893 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 894 } 895 if (unlikely(compute_rc0)) { 896 gen_set_Rc0(ctx, t0); 897 } 898 899 if (t0 != ret) { 900 tcg_gen_mov_tl(ret, t0); 901 tcg_temp_free(t0); 902 } 903 } 904 /* Add functions with two operands */ 905 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 906 static void glue(gen_, name)(DisasContext *ctx) \ 907 { \ 908 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 909 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 910 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 911 } 912 /* Add functions with one operand and one immediate */ 913 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 914 add_ca, compute_ca, compute_ov) \ 915 static void glue(gen_, name)(DisasContext *ctx) \ 916 { \ 917 TCGv t0 = tcg_const_tl(const_val); \ 918 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 919 cpu_gpr[rA(ctx->opcode)], t0, \ 920 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 921 tcg_temp_free(t0); \ 922 } 923 924 /* add add. addo addo. */ 925 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 926 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 927 /* addc addc. addco addco. */ 928 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 929 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 930 /* adde adde. addeo addeo. */ 931 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 932 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 933 /* addme addme. addmeo addmeo. */ 934 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 935 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 936 /* addze addze. addzeo addzeo.*/ 937 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 938 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 939 /* addi */ 940 static void gen_addi(DisasContext *ctx) 941 { 942 target_long simm = SIMM(ctx->opcode); 943 944 if (rA(ctx->opcode) == 0) { 945 /* li case */ 946 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 947 } else { 948 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 949 cpu_gpr[rA(ctx->opcode)], simm); 950 } 951 } 952 /* addic addic.*/ 953 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 954 { 955 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 956 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 957 c, 0, 1, 0, compute_rc0); 958 tcg_temp_free(c); 959 } 960 961 static void gen_addic(DisasContext *ctx) 962 { 963 gen_op_addic(ctx, 0); 964 } 965 966 static void gen_addic_(DisasContext *ctx) 967 { 968 gen_op_addic(ctx, 1); 969 } 970 971 /* addis */ 972 static void gen_addis(DisasContext *ctx) 973 { 974 target_long simm = SIMM(ctx->opcode); 975 976 if (rA(ctx->opcode) == 0) { 977 /* lis case */ 978 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 979 } else { 980 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 981 cpu_gpr[rA(ctx->opcode)], simm << 16); 982 } 983 } 984 985 /* addpcis */ 986 static void gen_addpcis(DisasContext *ctx) 987 { 988 target_long d = DX(ctx->opcode); 989 990 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16)); 991 } 992 993 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 994 TCGv arg2, int sign, int compute_ov) 995 { 996 TCGv_i32 t0 = tcg_temp_new_i32(); 997 TCGv_i32 t1 = tcg_temp_new_i32(); 998 TCGv_i32 t2 = tcg_temp_new_i32(); 999 TCGv_i32 t3 = tcg_temp_new_i32(); 1000 1001 tcg_gen_trunc_tl_i32(t0, arg1); 1002 tcg_gen_trunc_tl_i32(t1, arg2); 1003 if (sign) { 1004 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1005 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1006 tcg_gen_and_i32(t2, t2, t3); 1007 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1008 tcg_gen_or_i32(t2, t2, t3); 1009 tcg_gen_movi_i32(t3, 0); 1010 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1011 tcg_gen_div_i32(t3, t0, t1); 1012 tcg_gen_extu_i32_tl(ret, t3); 1013 } else { 1014 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1015 tcg_gen_movi_i32(t3, 0); 1016 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1017 tcg_gen_divu_i32(t3, t0, t1); 1018 tcg_gen_extu_i32_tl(ret, t3); 1019 } 1020 if (compute_ov) { 1021 tcg_gen_extu_i32_tl(cpu_ov, t2); 1022 if (is_isa300(ctx)) { 1023 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1024 } 1025 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1026 } 1027 tcg_temp_free_i32(t0); 1028 tcg_temp_free_i32(t1); 1029 tcg_temp_free_i32(t2); 1030 tcg_temp_free_i32(t3); 1031 1032 if (unlikely(Rc(ctx->opcode) != 0)) 1033 gen_set_Rc0(ctx, ret); 1034 } 1035 /* Div functions */ 1036 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1037 static void glue(gen_, name)(DisasContext *ctx) \ 1038 { \ 1039 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1040 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1041 sign, compute_ov); \ 1042 } 1043 /* divwu divwu. divwuo divwuo. */ 1044 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1045 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1046 /* divw divw. divwo divwo. */ 1047 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1048 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1049 1050 /* div[wd]eu[o][.] */ 1051 #define GEN_DIVE(name, hlpr, compute_ov) \ 1052 static void gen_##name(DisasContext *ctx) \ 1053 { \ 1054 TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1055 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1056 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1057 tcg_temp_free_i32(t0); \ 1058 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1059 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1060 } \ 1061 } 1062 1063 GEN_DIVE(divweu, divweu, 0); 1064 GEN_DIVE(divweuo, divweu, 1); 1065 GEN_DIVE(divwe, divwe, 0); 1066 GEN_DIVE(divweo, divwe, 1); 1067 1068 #if defined(TARGET_PPC64) 1069 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1070 TCGv arg2, int sign, int compute_ov) 1071 { 1072 TCGv_i64 t0 = tcg_temp_new_i64(); 1073 TCGv_i64 t1 = tcg_temp_new_i64(); 1074 TCGv_i64 t2 = tcg_temp_new_i64(); 1075 TCGv_i64 t3 = tcg_temp_new_i64(); 1076 1077 tcg_gen_mov_i64(t0, arg1); 1078 tcg_gen_mov_i64(t1, arg2); 1079 if (sign) { 1080 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1081 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1082 tcg_gen_and_i64(t2, t2, t3); 1083 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1084 tcg_gen_or_i64(t2, t2, t3); 1085 tcg_gen_movi_i64(t3, 0); 1086 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1087 tcg_gen_div_i64(ret, t0, t1); 1088 } else { 1089 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1090 tcg_gen_movi_i64(t3, 0); 1091 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1092 tcg_gen_divu_i64(ret, t0, t1); 1093 } 1094 if (compute_ov) { 1095 tcg_gen_mov_tl(cpu_ov, t2); 1096 if (is_isa300(ctx)) { 1097 tcg_gen_mov_tl(cpu_ov32, t2); 1098 } 1099 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1100 } 1101 tcg_temp_free_i64(t0); 1102 tcg_temp_free_i64(t1); 1103 tcg_temp_free_i64(t2); 1104 tcg_temp_free_i64(t3); 1105 1106 if (unlikely(Rc(ctx->opcode) != 0)) 1107 gen_set_Rc0(ctx, ret); 1108 } 1109 1110 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1111 static void glue(gen_, name)(DisasContext *ctx) \ 1112 { \ 1113 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1114 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1115 sign, compute_ov); \ 1116 } 1117 /* divdu divdu. divduo divduo. */ 1118 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1119 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1120 /* divd divd. divdo divdo. */ 1121 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1122 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1123 1124 GEN_DIVE(divdeu, divdeu, 0); 1125 GEN_DIVE(divdeuo, divdeu, 1); 1126 GEN_DIVE(divde, divde, 0); 1127 GEN_DIVE(divdeo, divde, 1); 1128 #endif 1129 1130 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1131 TCGv arg2, int sign) 1132 { 1133 TCGv_i32 t0 = tcg_temp_new_i32(); 1134 TCGv_i32 t1 = tcg_temp_new_i32(); 1135 1136 tcg_gen_trunc_tl_i32(t0, arg1); 1137 tcg_gen_trunc_tl_i32(t1, arg2); 1138 if (sign) { 1139 TCGv_i32 t2 = tcg_temp_new_i32(); 1140 TCGv_i32 t3 = tcg_temp_new_i32(); 1141 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1142 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1143 tcg_gen_and_i32(t2, t2, t3); 1144 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1145 tcg_gen_or_i32(t2, t2, t3); 1146 tcg_gen_movi_i32(t3, 0); 1147 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1148 tcg_gen_rem_i32(t3, t0, t1); 1149 tcg_gen_ext_i32_tl(ret, t3); 1150 tcg_temp_free_i32(t2); 1151 tcg_temp_free_i32(t3); 1152 } else { 1153 TCGv_i32 t2 = tcg_const_i32(1); 1154 TCGv_i32 t3 = tcg_const_i32(0); 1155 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1156 tcg_gen_remu_i32(t3, t0, t1); 1157 tcg_gen_extu_i32_tl(ret, t3); 1158 tcg_temp_free_i32(t2); 1159 tcg_temp_free_i32(t3); 1160 } 1161 tcg_temp_free_i32(t0); 1162 tcg_temp_free_i32(t1); 1163 } 1164 1165 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1166 static void glue(gen_, name)(DisasContext *ctx) \ 1167 { \ 1168 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1169 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1170 sign); \ 1171 } 1172 1173 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1174 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1175 1176 #if defined(TARGET_PPC64) 1177 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1178 TCGv arg2, int sign) 1179 { 1180 TCGv_i64 t0 = tcg_temp_new_i64(); 1181 TCGv_i64 t1 = tcg_temp_new_i64(); 1182 1183 tcg_gen_mov_i64(t0, arg1); 1184 tcg_gen_mov_i64(t1, arg2); 1185 if (sign) { 1186 TCGv_i64 t2 = tcg_temp_new_i64(); 1187 TCGv_i64 t3 = tcg_temp_new_i64(); 1188 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1189 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1190 tcg_gen_and_i64(t2, t2, t3); 1191 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1192 tcg_gen_or_i64(t2, t2, t3); 1193 tcg_gen_movi_i64(t3, 0); 1194 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1195 tcg_gen_rem_i64(ret, t0, t1); 1196 tcg_temp_free_i64(t2); 1197 tcg_temp_free_i64(t3); 1198 } else { 1199 TCGv_i64 t2 = tcg_const_i64(1); 1200 TCGv_i64 t3 = tcg_const_i64(0); 1201 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1202 tcg_gen_remu_i64(ret, t0, t1); 1203 tcg_temp_free_i64(t2); 1204 tcg_temp_free_i64(t3); 1205 } 1206 tcg_temp_free_i64(t0); 1207 tcg_temp_free_i64(t1); 1208 } 1209 1210 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1211 static void glue(gen_, name)(DisasContext *ctx) \ 1212 { \ 1213 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1214 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1215 sign); \ 1216 } 1217 1218 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1219 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1220 #endif 1221 1222 /* mulhw mulhw. */ 1223 static void gen_mulhw(DisasContext *ctx) 1224 { 1225 TCGv_i32 t0 = tcg_temp_new_i32(); 1226 TCGv_i32 t1 = tcg_temp_new_i32(); 1227 1228 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1229 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1230 tcg_gen_muls2_i32(t0, t1, t0, t1); 1231 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1232 tcg_temp_free_i32(t0); 1233 tcg_temp_free_i32(t1); 1234 if (unlikely(Rc(ctx->opcode) != 0)) 1235 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1236 } 1237 1238 /* mulhwu mulhwu. */ 1239 static void gen_mulhwu(DisasContext *ctx) 1240 { 1241 TCGv_i32 t0 = tcg_temp_new_i32(); 1242 TCGv_i32 t1 = tcg_temp_new_i32(); 1243 1244 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1245 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1246 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1247 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1248 tcg_temp_free_i32(t0); 1249 tcg_temp_free_i32(t1); 1250 if (unlikely(Rc(ctx->opcode) != 0)) 1251 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1252 } 1253 1254 /* mullw mullw. */ 1255 static void gen_mullw(DisasContext *ctx) 1256 { 1257 #if defined(TARGET_PPC64) 1258 TCGv_i64 t0, t1; 1259 t0 = tcg_temp_new_i64(); 1260 t1 = tcg_temp_new_i64(); 1261 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1262 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1263 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1264 tcg_temp_free(t0); 1265 tcg_temp_free(t1); 1266 #else 1267 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1268 cpu_gpr[rB(ctx->opcode)]); 1269 #endif 1270 if (unlikely(Rc(ctx->opcode) != 0)) 1271 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1272 } 1273 1274 /* mullwo mullwo. */ 1275 static void gen_mullwo(DisasContext *ctx) 1276 { 1277 TCGv_i32 t0 = tcg_temp_new_i32(); 1278 TCGv_i32 t1 = tcg_temp_new_i32(); 1279 1280 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1281 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1282 tcg_gen_muls2_i32(t0, t1, t0, t1); 1283 #if defined(TARGET_PPC64) 1284 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1285 #else 1286 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1287 #endif 1288 1289 tcg_gen_sari_i32(t0, t0, 31); 1290 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1291 tcg_gen_extu_i32_tl(cpu_ov, t0); 1292 if (is_isa300(ctx)) { 1293 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1294 } 1295 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1296 1297 tcg_temp_free_i32(t0); 1298 tcg_temp_free_i32(t1); 1299 if (unlikely(Rc(ctx->opcode) != 0)) 1300 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1301 } 1302 1303 /* mulli */ 1304 static void gen_mulli(DisasContext *ctx) 1305 { 1306 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1307 SIMM(ctx->opcode)); 1308 } 1309 1310 #if defined(TARGET_PPC64) 1311 /* mulhd mulhd. */ 1312 static void gen_mulhd(DisasContext *ctx) 1313 { 1314 TCGv lo = tcg_temp_new(); 1315 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1316 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1317 tcg_temp_free(lo); 1318 if (unlikely(Rc(ctx->opcode) != 0)) { 1319 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1320 } 1321 } 1322 1323 /* mulhdu mulhdu. */ 1324 static void gen_mulhdu(DisasContext *ctx) 1325 { 1326 TCGv lo = tcg_temp_new(); 1327 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1328 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1329 tcg_temp_free(lo); 1330 if (unlikely(Rc(ctx->opcode) != 0)) { 1331 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1332 } 1333 } 1334 1335 /* mulld mulld. */ 1336 static void gen_mulld(DisasContext *ctx) 1337 { 1338 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1339 cpu_gpr[rB(ctx->opcode)]); 1340 if (unlikely(Rc(ctx->opcode) != 0)) 1341 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1342 } 1343 1344 /* mulldo mulldo. */ 1345 static void gen_mulldo(DisasContext *ctx) 1346 { 1347 TCGv_i64 t0 = tcg_temp_new_i64(); 1348 TCGv_i64 t1 = tcg_temp_new_i64(); 1349 1350 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1351 cpu_gpr[rB(ctx->opcode)]); 1352 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1353 1354 tcg_gen_sari_i64(t0, t0, 63); 1355 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 1356 if (is_isa300(ctx)) { 1357 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1358 } 1359 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1360 1361 tcg_temp_free_i64(t0); 1362 tcg_temp_free_i64(t1); 1363 1364 if (unlikely(Rc(ctx->opcode) != 0)) { 1365 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1366 } 1367 } 1368 #endif 1369 1370 /* Common subf function */ 1371 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1372 TCGv arg2, bool add_ca, bool compute_ca, 1373 bool compute_ov, bool compute_rc0) 1374 { 1375 TCGv t0 = ret; 1376 1377 if (compute_ca || compute_ov) { 1378 t0 = tcg_temp_new(); 1379 } 1380 1381 if (compute_ca) { 1382 /* dest = ~arg1 + arg2 [+ ca]. */ 1383 if (NARROW_MODE(ctx)) { 1384 /* Caution: a non-obvious corner case of the spec is that we 1385 must produce the *entire* 64-bit addition, but produce the 1386 carry into bit 32. */ 1387 TCGv inv1 = tcg_temp_new(); 1388 TCGv t1 = tcg_temp_new(); 1389 tcg_gen_not_tl(inv1, arg1); 1390 if (add_ca) { 1391 tcg_gen_add_tl(t0, arg2, cpu_ca); 1392 } else { 1393 tcg_gen_addi_tl(t0, arg2, 1); 1394 } 1395 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1396 tcg_gen_add_tl(t0, t0, inv1); 1397 tcg_temp_free(inv1); 1398 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1399 tcg_temp_free(t1); 1400 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 1401 if (is_isa300(ctx)) { 1402 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 1403 } 1404 } else if (add_ca) { 1405 TCGv zero, inv1 = tcg_temp_new(); 1406 tcg_gen_not_tl(inv1, arg1); 1407 zero = tcg_const_tl(0); 1408 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1409 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 1410 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0); 1411 tcg_temp_free(zero); 1412 tcg_temp_free(inv1); 1413 } else { 1414 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1415 tcg_gen_sub_tl(t0, arg2, arg1); 1416 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1); 1417 } 1418 } else if (add_ca) { 1419 /* Since we're ignoring carry-out, we can simplify the 1420 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ 1421 tcg_gen_sub_tl(t0, arg2, arg1); 1422 tcg_gen_add_tl(t0, t0, cpu_ca); 1423 tcg_gen_subi_tl(t0, t0, 1); 1424 } else { 1425 tcg_gen_sub_tl(t0, arg2, arg1); 1426 } 1427 1428 if (compute_ov) { 1429 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1430 } 1431 if (unlikely(compute_rc0)) { 1432 gen_set_Rc0(ctx, t0); 1433 } 1434 1435 if (t0 != ret) { 1436 tcg_gen_mov_tl(ret, t0); 1437 tcg_temp_free(t0); 1438 } 1439 } 1440 /* Sub functions with Two operands functions */ 1441 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1442 static void glue(gen_, name)(DisasContext *ctx) \ 1443 { \ 1444 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1445 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1446 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1447 } 1448 /* Sub functions with one operand and one immediate */ 1449 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1450 add_ca, compute_ca, compute_ov) \ 1451 static void glue(gen_, name)(DisasContext *ctx) \ 1452 { \ 1453 TCGv t0 = tcg_const_tl(const_val); \ 1454 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1455 cpu_gpr[rA(ctx->opcode)], t0, \ 1456 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1457 tcg_temp_free(t0); \ 1458 } 1459 /* subf subf. subfo subfo. */ 1460 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1461 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1462 /* subfc subfc. subfco subfco. */ 1463 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1464 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1465 /* subfe subfe. subfeo subfo. */ 1466 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1467 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1468 /* subfme subfme. subfmeo subfmeo. */ 1469 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1470 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1471 /* subfze subfze. subfzeo subfzeo.*/ 1472 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1473 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1474 1475 /* subfic */ 1476 static void gen_subfic(DisasContext *ctx) 1477 { 1478 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1479 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1480 c, 0, 1, 0, 0); 1481 tcg_temp_free(c); 1482 } 1483 1484 /* neg neg. nego nego. */ 1485 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1486 { 1487 TCGv zero = tcg_const_tl(0); 1488 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1489 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1490 tcg_temp_free(zero); 1491 } 1492 1493 static void gen_neg(DisasContext *ctx) 1494 { 1495 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 1496 if (unlikely(Rc(ctx->opcode))) { 1497 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1498 } 1499 } 1500 1501 static void gen_nego(DisasContext *ctx) 1502 { 1503 gen_op_arith_neg(ctx, 1); 1504 } 1505 1506 /*** Integer logical ***/ 1507 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1508 static void glue(gen_, name)(DisasContext *ctx) \ 1509 { \ 1510 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1511 cpu_gpr[rB(ctx->opcode)]); \ 1512 if (unlikely(Rc(ctx->opcode) != 0)) \ 1513 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1514 } 1515 1516 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1517 static void glue(gen_, name)(DisasContext *ctx) \ 1518 { \ 1519 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1520 if (unlikely(Rc(ctx->opcode) != 0)) \ 1521 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1522 } 1523 1524 /* and & and. */ 1525 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1526 /* andc & andc. */ 1527 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1528 1529 /* andi. */ 1530 static void gen_andi_(DisasContext *ctx) 1531 { 1532 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); 1533 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1534 } 1535 1536 /* andis. */ 1537 static void gen_andis_(DisasContext *ctx) 1538 { 1539 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); 1540 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1541 } 1542 1543 /* cntlzw */ 1544 static void gen_cntlzw(DisasContext *ctx) 1545 { 1546 TCGv_i32 t = tcg_temp_new_i32(); 1547 1548 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1549 tcg_gen_clzi_i32(t, t, 32); 1550 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1551 tcg_temp_free_i32(t); 1552 1553 if (unlikely(Rc(ctx->opcode) != 0)) 1554 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1555 } 1556 1557 /* cnttzw */ 1558 static void gen_cnttzw(DisasContext *ctx) 1559 { 1560 TCGv_i32 t = tcg_temp_new_i32(); 1561 1562 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1563 tcg_gen_ctzi_i32(t, t, 32); 1564 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1565 tcg_temp_free_i32(t); 1566 1567 if (unlikely(Rc(ctx->opcode) != 0)) { 1568 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1569 } 1570 } 1571 1572 /* eqv & eqv. */ 1573 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1574 /* extsb & extsb. */ 1575 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1576 /* extsh & extsh. */ 1577 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1578 /* nand & nand. */ 1579 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1580 /* nor & nor. */ 1581 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1582 1583 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1584 static void gen_pause(DisasContext *ctx) 1585 { 1586 TCGv_i32 t0 = tcg_const_i32(0); 1587 tcg_gen_st_i32(t0, cpu_env, 1588 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1589 tcg_temp_free_i32(t0); 1590 1591 /* Stop translation, this gives other CPUs a chance to run */ 1592 gen_exception_nip(ctx, EXCP_HLT, ctx->nip); 1593 } 1594 #endif /* defined(TARGET_PPC64) */ 1595 1596 /* or & or. */ 1597 static void gen_or(DisasContext *ctx) 1598 { 1599 int rs, ra, rb; 1600 1601 rs = rS(ctx->opcode); 1602 ra = rA(ctx->opcode); 1603 rb = rB(ctx->opcode); 1604 /* Optimisation for mr. ri case */ 1605 if (rs != ra || rs != rb) { 1606 if (rs != rb) 1607 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1608 else 1609 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1610 if (unlikely(Rc(ctx->opcode) != 0)) 1611 gen_set_Rc0(ctx, cpu_gpr[ra]); 1612 } else if (unlikely(Rc(ctx->opcode) != 0)) { 1613 gen_set_Rc0(ctx, cpu_gpr[rs]); 1614 #if defined(TARGET_PPC64) 1615 } else if (rs != 0) { /* 0 is nop */ 1616 int prio = 0; 1617 1618 switch (rs) { 1619 case 1: 1620 /* Set process priority to low */ 1621 prio = 2; 1622 break; 1623 case 6: 1624 /* Set process priority to medium-low */ 1625 prio = 3; 1626 break; 1627 case 2: 1628 /* Set process priority to normal */ 1629 prio = 4; 1630 break; 1631 #if !defined(CONFIG_USER_ONLY) 1632 case 31: 1633 if (!ctx->pr) { 1634 /* Set process priority to very low */ 1635 prio = 1; 1636 } 1637 break; 1638 case 5: 1639 if (!ctx->pr) { 1640 /* Set process priority to medium-hight */ 1641 prio = 5; 1642 } 1643 break; 1644 case 3: 1645 if (!ctx->pr) { 1646 /* Set process priority to high */ 1647 prio = 6; 1648 } 1649 break; 1650 case 7: 1651 if (ctx->hv && !ctx->pr) { 1652 /* Set process priority to very high */ 1653 prio = 7; 1654 } 1655 break; 1656 #endif 1657 default: 1658 break; 1659 } 1660 if (prio) { 1661 TCGv t0 = tcg_temp_new(); 1662 gen_load_spr(t0, SPR_PPR); 1663 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1664 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1665 gen_store_spr(SPR_PPR, t0); 1666 tcg_temp_free(t0); 1667 } 1668 #if !defined(CONFIG_USER_ONLY) 1669 /* Pause out of TCG otherwise spin loops with smt_low eat too much 1670 * CPU and the kernel hangs. This applies to all encodings other 1671 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), 1672 * and all currently undefined. 1673 */ 1674 gen_pause(ctx); 1675 #endif 1676 #endif 1677 } 1678 } 1679 /* orc & orc. */ 1680 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1681 1682 /* xor & xor. */ 1683 static void gen_xor(DisasContext *ctx) 1684 { 1685 /* Optimisation for "set to zero" case */ 1686 if (rS(ctx->opcode) != rB(ctx->opcode)) 1687 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1688 else 1689 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1690 if (unlikely(Rc(ctx->opcode) != 0)) 1691 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1692 } 1693 1694 /* ori */ 1695 static void gen_ori(DisasContext *ctx) 1696 { 1697 target_ulong uimm = UIMM(ctx->opcode); 1698 1699 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1700 return; 1701 } 1702 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1703 } 1704 1705 /* oris */ 1706 static void gen_oris(DisasContext *ctx) 1707 { 1708 target_ulong uimm = UIMM(ctx->opcode); 1709 1710 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1711 /* NOP */ 1712 return; 1713 } 1714 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1715 } 1716 1717 /* xori */ 1718 static void gen_xori(DisasContext *ctx) 1719 { 1720 target_ulong uimm = UIMM(ctx->opcode); 1721 1722 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1723 /* NOP */ 1724 return; 1725 } 1726 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1727 } 1728 1729 /* xoris */ 1730 static void gen_xoris(DisasContext *ctx) 1731 { 1732 target_ulong uimm = UIMM(ctx->opcode); 1733 1734 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1735 /* NOP */ 1736 return; 1737 } 1738 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1739 } 1740 1741 /* popcntb : PowerPC 2.03 specification */ 1742 static void gen_popcntb(DisasContext *ctx) 1743 { 1744 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1745 } 1746 1747 static void gen_popcntw(DisasContext *ctx) 1748 { 1749 #if defined(TARGET_PPC64) 1750 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1751 #else 1752 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1753 #endif 1754 } 1755 1756 #if defined(TARGET_PPC64) 1757 /* popcntd: PowerPC 2.06 specification */ 1758 static void gen_popcntd(DisasContext *ctx) 1759 { 1760 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1761 } 1762 #endif 1763 1764 /* prtyw: PowerPC 2.05 specification */ 1765 static void gen_prtyw(DisasContext *ctx) 1766 { 1767 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1768 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1769 TCGv t0 = tcg_temp_new(); 1770 tcg_gen_shri_tl(t0, rs, 16); 1771 tcg_gen_xor_tl(ra, rs, t0); 1772 tcg_gen_shri_tl(t0, ra, 8); 1773 tcg_gen_xor_tl(ra, ra, t0); 1774 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1775 tcg_temp_free(t0); 1776 } 1777 1778 #if defined(TARGET_PPC64) 1779 /* prtyd: PowerPC 2.05 specification */ 1780 static void gen_prtyd(DisasContext *ctx) 1781 { 1782 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1783 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1784 TCGv t0 = tcg_temp_new(); 1785 tcg_gen_shri_tl(t0, rs, 32); 1786 tcg_gen_xor_tl(ra, rs, t0); 1787 tcg_gen_shri_tl(t0, ra, 16); 1788 tcg_gen_xor_tl(ra, ra, t0); 1789 tcg_gen_shri_tl(t0, ra, 8); 1790 tcg_gen_xor_tl(ra, ra, t0); 1791 tcg_gen_andi_tl(ra, ra, 1); 1792 tcg_temp_free(t0); 1793 } 1794 #endif 1795 1796 #if defined(TARGET_PPC64) 1797 /* bpermd */ 1798 static void gen_bpermd(DisasContext *ctx) 1799 { 1800 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1801 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1802 } 1803 #endif 1804 1805 #if defined(TARGET_PPC64) 1806 /* extsw & extsw. */ 1807 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1808 1809 /* cntlzd */ 1810 static void gen_cntlzd(DisasContext *ctx) 1811 { 1812 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1813 if (unlikely(Rc(ctx->opcode) != 0)) 1814 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1815 } 1816 1817 /* cnttzd */ 1818 static void gen_cnttzd(DisasContext *ctx) 1819 { 1820 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1821 if (unlikely(Rc(ctx->opcode) != 0)) { 1822 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1823 } 1824 } 1825 1826 /* darn */ 1827 static void gen_darn(DisasContext *ctx) 1828 { 1829 int l = L(ctx->opcode); 1830 1831 if (l == 0) { 1832 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1833 } else if (l <= 2) { 1834 /* Return 64-bit random for both CRN and RRN */ 1835 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1836 } else { 1837 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1838 } 1839 } 1840 #endif 1841 1842 /*** Integer rotate ***/ 1843 1844 /* rlwimi & rlwimi. */ 1845 static void gen_rlwimi(DisasContext *ctx) 1846 { 1847 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1848 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1849 uint32_t sh = SH(ctx->opcode); 1850 uint32_t mb = MB(ctx->opcode); 1851 uint32_t me = ME(ctx->opcode); 1852 1853 if (sh == (31-me) && mb <= me) { 1854 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1855 } else { 1856 target_ulong mask; 1857 TCGv t1; 1858 1859 #if defined(TARGET_PPC64) 1860 mb += 32; 1861 me += 32; 1862 #endif 1863 mask = MASK(mb, me); 1864 1865 t1 = tcg_temp_new(); 1866 if (mask <= 0xffffffffu) { 1867 TCGv_i32 t0 = tcg_temp_new_i32(); 1868 tcg_gen_trunc_tl_i32(t0, t_rs); 1869 tcg_gen_rotli_i32(t0, t0, sh); 1870 tcg_gen_extu_i32_tl(t1, t0); 1871 tcg_temp_free_i32(t0); 1872 } else { 1873 #if defined(TARGET_PPC64) 1874 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1875 tcg_gen_rotli_i64(t1, t1, sh); 1876 #else 1877 g_assert_not_reached(); 1878 #endif 1879 } 1880 1881 tcg_gen_andi_tl(t1, t1, mask); 1882 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1883 tcg_gen_or_tl(t_ra, t_ra, t1); 1884 tcg_temp_free(t1); 1885 } 1886 if (unlikely(Rc(ctx->opcode) != 0)) { 1887 gen_set_Rc0(ctx, t_ra); 1888 } 1889 } 1890 1891 /* rlwinm & rlwinm. */ 1892 static void gen_rlwinm(DisasContext *ctx) 1893 { 1894 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1895 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1896 int sh = SH(ctx->opcode); 1897 int mb = MB(ctx->opcode); 1898 int me = ME(ctx->opcode); 1899 int len = me - mb + 1; 1900 int rsh = (32 - sh) & 31; 1901 1902 if (sh != 0 && len > 0 && me == (31 - sh)) { 1903 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 1904 } else if (me == 31 && rsh + len <= 32) { 1905 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1906 } else { 1907 target_ulong mask; 1908 #if defined(TARGET_PPC64) 1909 mb += 32; 1910 me += 32; 1911 #endif 1912 mask = MASK(mb, me); 1913 if (sh == 0) { 1914 tcg_gen_andi_tl(t_ra, t_rs, mask); 1915 } else if (mask <= 0xffffffffu) { 1916 TCGv_i32 t0 = tcg_temp_new_i32(); 1917 tcg_gen_trunc_tl_i32(t0, t_rs); 1918 tcg_gen_rotli_i32(t0, t0, sh); 1919 tcg_gen_andi_i32(t0, t0, mask); 1920 tcg_gen_extu_i32_tl(t_ra, t0); 1921 tcg_temp_free_i32(t0); 1922 } else { 1923 #if defined(TARGET_PPC64) 1924 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1925 tcg_gen_rotli_i64(t_ra, t_ra, sh); 1926 tcg_gen_andi_i64(t_ra, t_ra, mask); 1927 #else 1928 g_assert_not_reached(); 1929 #endif 1930 } 1931 } 1932 if (unlikely(Rc(ctx->opcode) != 0)) { 1933 gen_set_Rc0(ctx, t_ra); 1934 } 1935 } 1936 1937 /* rlwnm & rlwnm. */ 1938 static void gen_rlwnm(DisasContext *ctx) 1939 { 1940 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1941 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1942 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1943 uint32_t mb = MB(ctx->opcode); 1944 uint32_t me = ME(ctx->opcode); 1945 target_ulong mask; 1946 1947 #if defined(TARGET_PPC64) 1948 mb += 32; 1949 me += 32; 1950 #endif 1951 mask = MASK(mb, me); 1952 1953 if (mask <= 0xffffffffu) { 1954 TCGv_i32 t0 = tcg_temp_new_i32(); 1955 TCGv_i32 t1 = tcg_temp_new_i32(); 1956 tcg_gen_trunc_tl_i32(t0, t_rb); 1957 tcg_gen_trunc_tl_i32(t1, t_rs); 1958 tcg_gen_andi_i32(t0, t0, 0x1f); 1959 tcg_gen_rotl_i32(t1, t1, t0); 1960 tcg_gen_extu_i32_tl(t_ra, t1); 1961 tcg_temp_free_i32(t0); 1962 tcg_temp_free_i32(t1); 1963 } else { 1964 #if defined(TARGET_PPC64) 1965 TCGv_i64 t0 = tcg_temp_new_i64(); 1966 tcg_gen_andi_i64(t0, t_rb, 0x1f); 1967 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1968 tcg_gen_rotl_i64(t_ra, t_ra, t0); 1969 tcg_temp_free_i64(t0); 1970 #else 1971 g_assert_not_reached(); 1972 #endif 1973 } 1974 1975 tcg_gen_andi_tl(t_ra, t_ra, mask); 1976 1977 if (unlikely(Rc(ctx->opcode) != 0)) { 1978 gen_set_Rc0(ctx, t_ra); 1979 } 1980 } 1981 1982 #if defined(TARGET_PPC64) 1983 #define GEN_PPC64_R2(name, opc1, opc2) \ 1984 static void glue(gen_, name##0)(DisasContext *ctx) \ 1985 { \ 1986 gen_##name(ctx, 0); \ 1987 } \ 1988 \ 1989 static void glue(gen_, name##1)(DisasContext *ctx) \ 1990 { \ 1991 gen_##name(ctx, 1); \ 1992 } 1993 #define GEN_PPC64_R4(name, opc1, opc2) \ 1994 static void glue(gen_, name##0)(DisasContext *ctx) \ 1995 { \ 1996 gen_##name(ctx, 0, 0); \ 1997 } \ 1998 \ 1999 static void glue(gen_, name##1)(DisasContext *ctx) \ 2000 { \ 2001 gen_##name(ctx, 0, 1); \ 2002 } \ 2003 \ 2004 static void glue(gen_, name##2)(DisasContext *ctx) \ 2005 { \ 2006 gen_##name(ctx, 1, 0); \ 2007 } \ 2008 \ 2009 static void glue(gen_, name##3)(DisasContext *ctx) \ 2010 { \ 2011 gen_##name(ctx, 1, 1); \ 2012 } 2013 2014 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2015 { 2016 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2017 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2018 int len = me - mb + 1; 2019 int rsh = (64 - sh) & 63; 2020 2021 if (sh != 0 && len > 0 && me == (63 - sh)) { 2022 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2023 } else if (me == 63 && rsh + len <= 64) { 2024 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2025 } else { 2026 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2027 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2028 } 2029 if (unlikely(Rc(ctx->opcode) != 0)) { 2030 gen_set_Rc0(ctx, t_ra); 2031 } 2032 } 2033 2034 /* rldicl - rldicl. */ 2035 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2036 { 2037 uint32_t sh, mb; 2038 2039 sh = SH(ctx->opcode) | (shn << 5); 2040 mb = MB(ctx->opcode) | (mbn << 5); 2041 gen_rldinm(ctx, mb, 63, sh); 2042 } 2043 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2044 2045 /* rldicr - rldicr. */ 2046 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2047 { 2048 uint32_t sh, me; 2049 2050 sh = SH(ctx->opcode) | (shn << 5); 2051 me = MB(ctx->opcode) | (men << 5); 2052 gen_rldinm(ctx, 0, me, sh); 2053 } 2054 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2055 2056 /* rldic - rldic. */ 2057 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2058 { 2059 uint32_t sh, mb; 2060 2061 sh = SH(ctx->opcode) | (shn << 5); 2062 mb = MB(ctx->opcode) | (mbn << 5); 2063 gen_rldinm(ctx, mb, 63 - sh, sh); 2064 } 2065 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2066 2067 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2068 { 2069 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2070 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2071 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2072 TCGv t0; 2073 2074 t0 = tcg_temp_new(); 2075 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2076 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2077 tcg_temp_free(t0); 2078 2079 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2080 if (unlikely(Rc(ctx->opcode) != 0)) { 2081 gen_set_Rc0(ctx, t_ra); 2082 } 2083 } 2084 2085 /* rldcl - rldcl. */ 2086 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2087 { 2088 uint32_t mb; 2089 2090 mb = MB(ctx->opcode) | (mbn << 5); 2091 gen_rldnm(ctx, mb, 63); 2092 } 2093 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2094 2095 /* rldcr - rldcr. */ 2096 static inline void gen_rldcr(DisasContext *ctx, int men) 2097 { 2098 uint32_t me; 2099 2100 me = MB(ctx->opcode) | (men << 5); 2101 gen_rldnm(ctx, 0, me); 2102 } 2103 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2104 2105 /* rldimi - rldimi. */ 2106 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2107 { 2108 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2109 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2110 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2111 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2112 uint32_t me = 63 - sh; 2113 2114 if (mb <= me) { 2115 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2116 } else { 2117 target_ulong mask = MASK(mb, me); 2118 TCGv t1 = tcg_temp_new(); 2119 2120 tcg_gen_rotli_tl(t1, t_rs, sh); 2121 tcg_gen_andi_tl(t1, t1, mask); 2122 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2123 tcg_gen_or_tl(t_ra, t_ra, t1); 2124 tcg_temp_free(t1); 2125 } 2126 if (unlikely(Rc(ctx->opcode) != 0)) { 2127 gen_set_Rc0(ctx, t_ra); 2128 } 2129 } 2130 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2131 #endif 2132 2133 /*** Integer shift ***/ 2134 2135 /* slw & slw. */ 2136 static void gen_slw(DisasContext *ctx) 2137 { 2138 TCGv t0, t1; 2139 2140 t0 = tcg_temp_new(); 2141 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2142 #if defined(TARGET_PPC64) 2143 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2144 tcg_gen_sari_tl(t0, t0, 0x3f); 2145 #else 2146 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2147 tcg_gen_sari_tl(t0, t0, 0x1f); 2148 #endif 2149 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2150 t1 = tcg_temp_new(); 2151 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2152 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2153 tcg_temp_free(t1); 2154 tcg_temp_free(t0); 2155 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2156 if (unlikely(Rc(ctx->opcode) != 0)) 2157 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2158 } 2159 2160 /* sraw & sraw. */ 2161 static void gen_sraw(DisasContext *ctx) 2162 { 2163 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2164 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2165 if (unlikely(Rc(ctx->opcode) != 0)) 2166 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2167 } 2168 2169 /* srawi & srawi. */ 2170 static void gen_srawi(DisasContext *ctx) 2171 { 2172 int sh = SH(ctx->opcode); 2173 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2174 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2175 if (sh == 0) { 2176 tcg_gen_ext32s_tl(dst, src); 2177 tcg_gen_movi_tl(cpu_ca, 0); 2178 if (is_isa300(ctx)) { 2179 tcg_gen_movi_tl(cpu_ca32, 0); 2180 } 2181 } else { 2182 TCGv t0; 2183 tcg_gen_ext32s_tl(dst, src); 2184 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2185 t0 = tcg_temp_new(); 2186 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2187 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2188 tcg_temp_free(t0); 2189 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2190 if (is_isa300(ctx)) { 2191 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2192 } 2193 tcg_gen_sari_tl(dst, dst, sh); 2194 } 2195 if (unlikely(Rc(ctx->opcode) != 0)) { 2196 gen_set_Rc0(ctx, dst); 2197 } 2198 } 2199 2200 /* srw & srw. */ 2201 static void gen_srw(DisasContext *ctx) 2202 { 2203 TCGv t0, t1; 2204 2205 t0 = tcg_temp_new(); 2206 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2207 #if defined(TARGET_PPC64) 2208 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2209 tcg_gen_sari_tl(t0, t0, 0x3f); 2210 #else 2211 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2212 tcg_gen_sari_tl(t0, t0, 0x1f); 2213 #endif 2214 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2215 tcg_gen_ext32u_tl(t0, t0); 2216 t1 = tcg_temp_new(); 2217 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2218 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2219 tcg_temp_free(t1); 2220 tcg_temp_free(t0); 2221 if (unlikely(Rc(ctx->opcode) != 0)) 2222 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2223 } 2224 2225 #if defined(TARGET_PPC64) 2226 /* sld & sld. */ 2227 static void gen_sld(DisasContext *ctx) 2228 { 2229 TCGv t0, t1; 2230 2231 t0 = tcg_temp_new(); 2232 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2233 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2234 tcg_gen_sari_tl(t0, t0, 0x3f); 2235 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2236 t1 = tcg_temp_new(); 2237 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2238 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2239 tcg_temp_free(t1); 2240 tcg_temp_free(t0); 2241 if (unlikely(Rc(ctx->opcode) != 0)) 2242 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2243 } 2244 2245 /* srad & srad. */ 2246 static void gen_srad(DisasContext *ctx) 2247 { 2248 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2249 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2250 if (unlikely(Rc(ctx->opcode) != 0)) 2251 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2252 } 2253 /* sradi & sradi. */ 2254 static inline void gen_sradi(DisasContext *ctx, int n) 2255 { 2256 int sh = SH(ctx->opcode) + (n << 5); 2257 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2258 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2259 if (sh == 0) { 2260 tcg_gen_mov_tl(dst, src); 2261 tcg_gen_movi_tl(cpu_ca, 0); 2262 if (is_isa300(ctx)) { 2263 tcg_gen_movi_tl(cpu_ca32, 0); 2264 } 2265 } else { 2266 TCGv t0; 2267 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2268 t0 = tcg_temp_new(); 2269 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2270 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2271 tcg_temp_free(t0); 2272 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2273 if (is_isa300(ctx)) { 2274 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2275 } 2276 tcg_gen_sari_tl(dst, src, sh); 2277 } 2278 if (unlikely(Rc(ctx->opcode) != 0)) { 2279 gen_set_Rc0(ctx, dst); 2280 } 2281 } 2282 2283 static void gen_sradi0(DisasContext *ctx) 2284 { 2285 gen_sradi(ctx, 0); 2286 } 2287 2288 static void gen_sradi1(DisasContext *ctx) 2289 { 2290 gen_sradi(ctx, 1); 2291 } 2292 2293 /* extswsli & extswsli. */ 2294 static inline void gen_extswsli(DisasContext *ctx, int n) 2295 { 2296 int sh = SH(ctx->opcode) + (n << 5); 2297 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2298 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2299 2300 tcg_gen_ext32s_tl(dst, src); 2301 tcg_gen_shli_tl(dst, dst, sh); 2302 if (unlikely(Rc(ctx->opcode) != 0)) { 2303 gen_set_Rc0(ctx, dst); 2304 } 2305 } 2306 2307 static void gen_extswsli0(DisasContext *ctx) 2308 { 2309 gen_extswsli(ctx, 0); 2310 } 2311 2312 static void gen_extswsli1(DisasContext *ctx) 2313 { 2314 gen_extswsli(ctx, 1); 2315 } 2316 2317 /* srd & srd. */ 2318 static void gen_srd(DisasContext *ctx) 2319 { 2320 TCGv t0, t1; 2321 2322 t0 = tcg_temp_new(); 2323 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2324 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2325 tcg_gen_sari_tl(t0, t0, 0x3f); 2326 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2327 t1 = tcg_temp_new(); 2328 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2329 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2330 tcg_temp_free(t1); 2331 tcg_temp_free(t0); 2332 if (unlikely(Rc(ctx->opcode) != 0)) 2333 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2334 } 2335 #endif 2336 2337 /*** Addressing modes ***/ 2338 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2339 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2340 target_long maskl) 2341 { 2342 target_long simm = SIMM(ctx->opcode); 2343 2344 simm &= ~maskl; 2345 if (rA(ctx->opcode) == 0) { 2346 if (NARROW_MODE(ctx)) { 2347 simm = (uint32_t)simm; 2348 } 2349 tcg_gen_movi_tl(EA, simm); 2350 } else if (likely(simm != 0)) { 2351 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2352 if (NARROW_MODE(ctx)) { 2353 tcg_gen_ext32u_tl(EA, EA); 2354 } 2355 } else { 2356 if (NARROW_MODE(ctx)) { 2357 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2358 } else { 2359 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2360 } 2361 } 2362 } 2363 2364 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2365 { 2366 if (rA(ctx->opcode) == 0) { 2367 if (NARROW_MODE(ctx)) { 2368 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2369 } else { 2370 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2371 } 2372 } else { 2373 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2374 if (NARROW_MODE(ctx)) { 2375 tcg_gen_ext32u_tl(EA, EA); 2376 } 2377 } 2378 } 2379 2380 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2381 { 2382 if (rA(ctx->opcode) == 0) { 2383 tcg_gen_movi_tl(EA, 0); 2384 } else if (NARROW_MODE(ctx)) { 2385 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2386 } else { 2387 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2388 } 2389 } 2390 2391 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2392 target_long val) 2393 { 2394 tcg_gen_addi_tl(ret, arg1, val); 2395 if (NARROW_MODE(ctx)) { 2396 tcg_gen_ext32u_tl(ret, ret); 2397 } 2398 } 2399 2400 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) 2401 { 2402 TCGLabel *l1 = gen_new_label(); 2403 TCGv t0 = tcg_temp_new(); 2404 TCGv_i32 t1, t2; 2405 tcg_gen_andi_tl(t0, EA, mask); 2406 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 2407 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); 2408 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); 2409 gen_update_nip(ctx, ctx->nip - 4); 2410 gen_helper_raise_exception_err(cpu_env, t1, t2); 2411 tcg_temp_free_i32(t1); 2412 tcg_temp_free_i32(t2); 2413 gen_set_label(l1); 2414 tcg_temp_free(t0); 2415 } 2416 2417 static inline void gen_align_no_le(DisasContext *ctx) 2418 { 2419 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2420 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2421 } 2422 2423 /*** Integer load ***/ 2424 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2425 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2426 2427 #define GEN_QEMU_LOAD_TL(ldop, op) \ 2428 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2429 TCGv val, \ 2430 TCGv addr) \ 2431 { \ 2432 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2433 } 2434 2435 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2436 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2437 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2438 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2439 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2440 2441 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2442 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2443 2444 #define GEN_QEMU_LOAD_64(ldop, op) \ 2445 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2446 TCGv_i64 val, \ 2447 TCGv addr) \ 2448 { \ 2449 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2450 } 2451 2452 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2453 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2454 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2455 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2456 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2457 2458 #if defined(TARGET_PPC64) 2459 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2460 #endif 2461 2462 #define GEN_QEMU_STORE_TL(stop, op) \ 2463 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2464 TCGv val, \ 2465 TCGv addr) \ 2466 { \ 2467 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2468 } 2469 2470 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2471 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2472 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2473 2474 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2475 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2476 2477 #define GEN_QEMU_STORE_64(stop, op) \ 2478 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2479 TCGv_i64 val, \ 2480 TCGv addr) \ 2481 { \ 2482 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2483 } 2484 2485 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2486 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2487 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2488 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2489 2490 #if defined(TARGET_PPC64) 2491 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2492 #endif 2493 2494 #define GEN_LD(name, ldop, opc, type) \ 2495 static void glue(gen_, name)(DisasContext *ctx) \ 2496 { \ 2497 TCGv EA; \ 2498 gen_set_access_type(ctx, ACCESS_INT); \ 2499 EA = tcg_temp_new(); \ 2500 gen_addr_imm_index(ctx, EA, 0); \ 2501 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2502 tcg_temp_free(EA); \ 2503 } 2504 2505 #define GEN_LDU(name, ldop, opc, type) \ 2506 static void glue(gen_, name##u)(DisasContext *ctx) \ 2507 { \ 2508 TCGv EA; \ 2509 if (unlikely(rA(ctx->opcode) == 0 || \ 2510 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2511 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2512 return; \ 2513 } \ 2514 gen_set_access_type(ctx, ACCESS_INT); \ 2515 EA = tcg_temp_new(); \ 2516 if (type == PPC_64B) \ 2517 gen_addr_imm_index(ctx, EA, 0x03); \ 2518 else \ 2519 gen_addr_imm_index(ctx, EA, 0); \ 2520 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2521 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2522 tcg_temp_free(EA); \ 2523 } 2524 2525 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2526 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2527 { \ 2528 TCGv EA; \ 2529 if (unlikely(rA(ctx->opcode) == 0 || \ 2530 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2531 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2532 return; \ 2533 } \ 2534 gen_set_access_type(ctx, ACCESS_INT); \ 2535 EA = tcg_temp_new(); \ 2536 gen_addr_reg_index(ctx, EA); \ 2537 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2538 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2539 tcg_temp_free(EA); \ 2540 } 2541 2542 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2543 static void glue(gen_, name##x)(DisasContext *ctx) \ 2544 { \ 2545 TCGv EA; \ 2546 chk; \ 2547 gen_set_access_type(ctx, ACCESS_INT); \ 2548 EA = tcg_temp_new(); \ 2549 gen_addr_reg_index(ctx, EA); \ 2550 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2551 tcg_temp_free(EA); \ 2552 } 2553 2554 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2555 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2556 2557 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2558 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2559 2560 #define GEN_LDS(name, ldop, op, type) \ 2561 GEN_LD(name, ldop, op | 0x20, type); \ 2562 GEN_LDU(name, ldop, op | 0x21, type); \ 2563 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2564 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2565 2566 /* lbz lbzu lbzux lbzx */ 2567 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2568 /* lha lhau lhaux lhax */ 2569 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2570 /* lhz lhzu lhzux lhzx */ 2571 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2572 /* lwz lwzu lwzux lwzx */ 2573 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2574 #if defined(TARGET_PPC64) 2575 /* lwaux */ 2576 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2577 /* lwax */ 2578 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2579 /* ldux */ 2580 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2581 /* ldx */ 2582 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2583 2584 /* CI load/store variants */ 2585 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2586 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2587 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2588 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2589 2590 static void gen_ld(DisasContext *ctx) 2591 { 2592 TCGv EA; 2593 if (Rc(ctx->opcode)) { 2594 if (unlikely(rA(ctx->opcode) == 0 || 2595 rA(ctx->opcode) == rD(ctx->opcode))) { 2596 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2597 return; 2598 } 2599 } 2600 gen_set_access_type(ctx, ACCESS_INT); 2601 EA = tcg_temp_new(); 2602 gen_addr_imm_index(ctx, EA, 0x03); 2603 if (ctx->opcode & 0x02) { 2604 /* lwa (lwau is undefined) */ 2605 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2606 } else { 2607 /* ld - ldu */ 2608 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2609 } 2610 if (Rc(ctx->opcode)) 2611 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2612 tcg_temp_free(EA); 2613 } 2614 2615 /* lq */ 2616 static void gen_lq(DisasContext *ctx) 2617 { 2618 int ra, rd; 2619 TCGv EA; 2620 2621 /* lq is a legal user mode instruction starting in ISA 2.07 */ 2622 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2623 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2624 2625 if (!legal_in_user_mode && ctx->pr) { 2626 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2627 return; 2628 } 2629 2630 if (!le_is_supported && ctx->le_mode) { 2631 gen_align_no_le(ctx); 2632 return; 2633 } 2634 ra = rA(ctx->opcode); 2635 rd = rD(ctx->opcode); 2636 if (unlikely((rd & 1) || rd == ra)) { 2637 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2638 return; 2639 } 2640 2641 gen_set_access_type(ctx, ACCESS_INT); 2642 EA = tcg_temp_new(); 2643 gen_addr_imm_index(ctx, EA, 0x0F); 2644 2645 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does 2646 necessary 64-bit byteswap already. */ 2647 if (unlikely(ctx->le_mode)) { 2648 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2649 gen_addr_add(ctx, EA, EA, 8); 2650 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2651 } else { 2652 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2653 gen_addr_add(ctx, EA, EA, 8); 2654 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2655 } 2656 tcg_temp_free(EA); 2657 } 2658 #endif 2659 2660 /*** Integer store ***/ 2661 #define GEN_ST(name, stop, opc, type) \ 2662 static void glue(gen_, name)(DisasContext *ctx) \ 2663 { \ 2664 TCGv EA; \ 2665 gen_set_access_type(ctx, ACCESS_INT); \ 2666 EA = tcg_temp_new(); \ 2667 gen_addr_imm_index(ctx, EA, 0); \ 2668 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2669 tcg_temp_free(EA); \ 2670 } 2671 2672 #define GEN_STU(name, stop, opc, type) \ 2673 static void glue(gen_, stop##u)(DisasContext *ctx) \ 2674 { \ 2675 TCGv EA; \ 2676 if (unlikely(rA(ctx->opcode) == 0)) { \ 2677 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2678 return; \ 2679 } \ 2680 gen_set_access_type(ctx, ACCESS_INT); \ 2681 EA = tcg_temp_new(); \ 2682 if (type == PPC_64B) \ 2683 gen_addr_imm_index(ctx, EA, 0x03); \ 2684 else \ 2685 gen_addr_imm_index(ctx, EA, 0); \ 2686 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2687 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2688 tcg_temp_free(EA); \ 2689 } 2690 2691 #define GEN_STUX(name, stop, opc2, opc3, type) \ 2692 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2693 { \ 2694 TCGv EA; \ 2695 if (unlikely(rA(ctx->opcode) == 0)) { \ 2696 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2697 return; \ 2698 } \ 2699 gen_set_access_type(ctx, ACCESS_INT); \ 2700 EA = tcg_temp_new(); \ 2701 gen_addr_reg_index(ctx, EA); \ 2702 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2703 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2704 tcg_temp_free(EA); \ 2705 } 2706 2707 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2708 static void glue(gen_, name##x)(DisasContext *ctx) \ 2709 { \ 2710 TCGv EA; \ 2711 chk; \ 2712 gen_set_access_type(ctx, ACCESS_INT); \ 2713 EA = tcg_temp_new(); \ 2714 gen_addr_reg_index(ctx, EA); \ 2715 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2716 tcg_temp_free(EA); \ 2717 } 2718 #define GEN_STX(name, stop, opc2, opc3, type) \ 2719 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2720 2721 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2722 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2723 2724 #define GEN_STS(name, stop, op, type) \ 2725 GEN_ST(name, stop, op | 0x20, type); \ 2726 GEN_STU(name, stop, op | 0x21, type); \ 2727 GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2728 GEN_STX(name, stop, 0x17, op | 0x00, type) 2729 2730 /* stb stbu stbux stbx */ 2731 GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2732 /* sth sthu sthux sthx */ 2733 GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2734 /* stw stwu stwux stwx */ 2735 GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2736 #if defined(TARGET_PPC64) 2737 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2738 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2739 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2740 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2741 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2742 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2743 2744 static void gen_std(DisasContext *ctx) 2745 { 2746 int rs; 2747 TCGv EA; 2748 2749 rs = rS(ctx->opcode); 2750 if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2751 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2752 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2753 2754 if (!(ctx->insns_flags & PPC_64BX)) { 2755 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2756 } 2757 2758 if (!legal_in_user_mode && ctx->pr) { 2759 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2760 return; 2761 } 2762 2763 if (!le_is_supported && ctx->le_mode) { 2764 gen_align_no_le(ctx); 2765 return; 2766 } 2767 2768 if (unlikely(rs & 1)) { 2769 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2770 return; 2771 } 2772 gen_set_access_type(ctx, ACCESS_INT); 2773 EA = tcg_temp_new(); 2774 gen_addr_imm_index(ctx, EA, 0x03); 2775 2776 /* We only need to swap high and low halves. gen_qemu_st64_i64 does 2777 necessary 64-bit byteswap already. */ 2778 if (unlikely(ctx->le_mode)) { 2779 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2780 gen_addr_add(ctx, EA, EA, 8); 2781 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2782 } else { 2783 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2784 gen_addr_add(ctx, EA, EA, 8); 2785 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2786 } 2787 tcg_temp_free(EA); 2788 } else { 2789 /* std / stdu*/ 2790 if (Rc(ctx->opcode)) { 2791 if (unlikely(rA(ctx->opcode) == 0)) { 2792 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2793 return; 2794 } 2795 } 2796 gen_set_access_type(ctx, ACCESS_INT); 2797 EA = tcg_temp_new(); 2798 gen_addr_imm_index(ctx, EA, 0x03); 2799 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2800 if (Rc(ctx->opcode)) 2801 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2802 tcg_temp_free(EA); 2803 } 2804 } 2805 #endif 2806 /*** Integer load and store with byte reverse ***/ 2807 2808 /* lhbrx */ 2809 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2810 2811 /* lwbrx */ 2812 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2813 2814 #if defined(TARGET_PPC64) 2815 /* ldbrx */ 2816 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2817 /* stdbrx */ 2818 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2819 #endif /* TARGET_PPC64 */ 2820 2821 /* sthbrx */ 2822 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2823 /* stwbrx */ 2824 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2825 2826 /*** Integer load and store multiple ***/ 2827 2828 /* lmw */ 2829 static void gen_lmw(DisasContext *ctx) 2830 { 2831 TCGv t0; 2832 TCGv_i32 t1; 2833 2834 if (ctx->le_mode) { 2835 gen_align_no_le(ctx); 2836 return; 2837 } 2838 gen_set_access_type(ctx, ACCESS_INT); 2839 t0 = tcg_temp_new(); 2840 t1 = tcg_const_i32(rD(ctx->opcode)); 2841 gen_addr_imm_index(ctx, t0, 0); 2842 gen_helper_lmw(cpu_env, t0, t1); 2843 tcg_temp_free(t0); 2844 tcg_temp_free_i32(t1); 2845 } 2846 2847 /* stmw */ 2848 static void gen_stmw(DisasContext *ctx) 2849 { 2850 TCGv t0; 2851 TCGv_i32 t1; 2852 2853 if (ctx->le_mode) { 2854 gen_align_no_le(ctx); 2855 return; 2856 } 2857 gen_set_access_type(ctx, ACCESS_INT); 2858 t0 = tcg_temp_new(); 2859 t1 = tcg_const_i32(rS(ctx->opcode)); 2860 gen_addr_imm_index(ctx, t0, 0); 2861 gen_helper_stmw(cpu_env, t0, t1); 2862 tcg_temp_free(t0); 2863 tcg_temp_free_i32(t1); 2864 } 2865 2866 /*** Integer load and store strings ***/ 2867 2868 /* lswi */ 2869 /* PowerPC32 specification says we must generate an exception if 2870 * rA is in the range of registers to be loaded. 2871 * In an other hand, IBM says this is valid, but rA won't be loaded. 2872 * For now, I'll follow the spec... 2873 */ 2874 static void gen_lswi(DisasContext *ctx) 2875 { 2876 TCGv t0; 2877 TCGv_i32 t1, t2; 2878 int nb = NB(ctx->opcode); 2879 int start = rD(ctx->opcode); 2880 int ra = rA(ctx->opcode); 2881 int nr; 2882 2883 if (ctx->le_mode) { 2884 gen_align_no_le(ctx); 2885 return; 2886 } 2887 if (nb == 0) 2888 nb = 32; 2889 nr = DIV_ROUND_UP(nb, 4); 2890 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2891 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2892 return; 2893 } 2894 gen_set_access_type(ctx, ACCESS_INT); 2895 t0 = tcg_temp_new(); 2896 gen_addr_register(ctx, t0); 2897 t1 = tcg_const_i32(nb); 2898 t2 = tcg_const_i32(start); 2899 gen_helper_lsw(cpu_env, t0, t1, t2); 2900 tcg_temp_free(t0); 2901 tcg_temp_free_i32(t1); 2902 tcg_temp_free_i32(t2); 2903 } 2904 2905 /* lswx */ 2906 static void gen_lswx(DisasContext *ctx) 2907 { 2908 TCGv t0; 2909 TCGv_i32 t1, t2, t3; 2910 2911 if (ctx->le_mode) { 2912 gen_align_no_le(ctx); 2913 return; 2914 } 2915 gen_set_access_type(ctx, ACCESS_INT); 2916 t0 = tcg_temp_new(); 2917 gen_addr_reg_index(ctx, t0); 2918 t1 = tcg_const_i32(rD(ctx->opcode)); 2919 t2 = tcg_const_i32(rA(ctx->opcode)); 2920 t3 = tcg_const_i32(rB(ctx->opcode)); 2921 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 2922 tcg_temp_free(t0); 2923 tcg_temp_free_i32(t1); 2924 tcg_temp_free_i32(t2); 2925 tcg_temp_free_i32(t3); 2926 } 2927 2928 /* stswi */ 2929 static void gen_stswi(DisasContext *ctx) 2930 { 2931 TCGv t0; 2932 TCGv_i32 t1, t2; 2933 int nb = NB(ctx->opcode); 2934 2935 if (ctx->le_mode) { 2936 gen_align_no_le(ctx); 2937 return; 2938 } 2939 gen_set_access_type(ctx, ACCESS_INT); 2940 t0 = tcg_temp_new(); 2941 gen_addr_register(ctx, t0); 2942 if (nb == 0) 2943 nb = 32; 2944 t1 = tcg_const_i32(nb); 2945 t2 = tcg_const_i32(rS(ctx->opcode)); 2946 gen_helper_stsw(cpu_env, t0, t1, t2); 2947 tcg_temp_free(t0); 2948 tcg_temp_free_i32(t1); 2949 tcg_temp_free_i32(t2); 2950 } 2951 2952 /* stswx */ 2953 static void gen_stswx(DisasContext *ctx) 2954 { 2955 TCGv t0; 2956 TCGv_i32 t1, t2; 2957 2958 if (ctx->le_mode) { 2959 gen_align_no_le(ctx); 2960 return; 2961 } 2962 gen_set_access_type(ctx, ACCESS_INT); 2963 t0 = tcg_temp_new(); 2964 gen_addr_reg_index(ctx, t0); 2965 t1 = tcg_temp_new_i32(); 2966 tcg_gen_trunc_tl_i32(t1, cpu_xer); 2967 tcg_gen_andi_i32(t1, t1, 0x7F); 2968 t2 = tcg_const_i32(rS(ctx->opcode)); 2969 gen_helper_stsw(cpu_env, t0, t1, t2); 2970 tcg_temp_free(t0); 2971 tcg_temp_free_i32(t1); 2972 tcg_temp_free_i32(t2); 2973 } 2974 2975 /*** Memory synchronisation ***/ 2976 /* eieio */ 2977 static void gen_eieio(DisasContext *ctx) 2978 { 2979 tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC); 2980 } 2981 2982 #if !defined(CONFIG_USER_ONLY) 2983 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 2984 { 2985 TCGv_i32 t; 2986 TCGLabel *l; 2987 2988 if (!ctx->lazy_tlb_flush) { 2989 return; 2990 } 2991 l = gen_new_label(); 2992 t = tcg_temp_new_i32(); 2993 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 2994 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 2995 if (global) { 2996 gen_helper_check_tlb_flush_global(cpu_env); 2997 } else { 2998 gen_helper_check_tlb_flush_local(cpu_env); 2999 } 3000 gen_set_label(l); 3001 tcg_temp_free_i32(t); 3002 } 3003 #else 3004 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3005 #endif 3006 3007 /* isync */ 3008 static void gen_isync(DisasContext *ctx) 3009 { 3010 /* 3011 * We need to check for a pending TLB flush. This can only happen in 3012 * kernel mode however so check MSR_PR 3013 */ 3014 if (!ctx->pr) { 3015 gen_check_tlb_flush(ctx, false); 3016 } 3017 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3018 gen_stop_exception(ctx); 3019 } 3020 3021 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3022 3023 #define LARX(name, memop) \ 3024 static void gen_##name(DisasContext *ctx) \ 3025 { \ 3026 TCGv t0; \ 3027 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ 3028 int len = MEMOP_GET_SIZE(memop); \ 3029 gen_set_access_type(ctx, ACCESS_RES); \ 3030 t0 = tcg_temp_local_new(); \ 3031 gen_addr_reg_index(ctx, t0); \ 3032 if ((len) > 1) { \ 3033 gen_check_align(ctx, t0, (len)-1); \ 3034 } \ 3035 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ 3036 tcg_gen_mov_tl(cpu_reserve, t0); \ 3037 tcg_gen_mov_tl(cpu_reserve_val, gpr); \ 3038 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \ 3039 tcg_temp_free(t0); \ 3040 } 3041 3042 /* lwarx */ 3043 LARX(lbarx, DEF_MEMOP(MO_UB)) 3044 LARX(lharx, DEF_MEMOP(MO_UW)) 3045 LARX(lwarx, DEF_MEMOP(MO_UL)) 3046 3047 #define LD_ATOMIC(name, memop, tp, op, eop) \ 3048 static void gen_##name(DisasContext *ctx) \ 3049 { \ 3050 int len = MEMOP_GET_SIZE(memop); \ 3051 uint32_t gpr_FC = FC(ctx->opcode); \ 3052 TCGv EA = tcg_temp_local_new(); \ 3053 TCGv_##tp t0, t1; \ 3054 \ 3055 gen_addr_register(ctx, EA); \ 3056 if (len > 1) { \ 3057 gen_check_align(ctx, EA, len - 1); \ 3058 } \ 3059 t0 = tcg_temp_new_##tp(); \ 3060 t1 = tcg_temp_new_##tp(); \ 3061 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3062 \ 3063 switch (gpr_FC) { \ 3064 case 0: /* Fetch and add */ \ 3065 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3066 break; \ 3067 case 1: /* Fetch and xor */ \ 3068 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3069 break; \ 3070 case 2: /* Fetch and or */ \ 3071 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3072 break; \ 3073 case 3: /* Fetch and 'and' */ \ 3074 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3075 break; \ 3076 case 8: /* Swap */ \ 3077 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3078 break; \ 3079 case 4: /* Fetch and max unsigned */ \ 3080 case 5: /* Fetch and max signed */ \ 3081 case 6: /* Fetch and min unsigned */ \ 3082 case 7: /* Fetch and min signed */ \ 3083 case 16: /* compare and swap not equal */ \ 3084 case 24: /* Fetch and increment bounded */ \ 3085 case 25: /* Fetch and increment equal */ \ 3086 case 28: /* Fetch and decrement bounded */ \ 3087 gen_invalid(ctx); \ 3088 break; \ 3089 default: \ 3090 /* invoke data storage error handler */ \ 3091 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3092 } \ 3093 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \ 3094 tcg_temp_free_##tp(t0); \ 3095 tcg_temp_free_##tp(t1); \ 3096 tcg_temp_free(EA); \ 3097 } 3098 3099 LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl) 3100 #if defined(TARGET_PPC64) 3101 LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64) 3102 #endif 3103 3104 #define ST_ATOMIC(name, memop, tp, op) \ 3105 static void gen_##name(DisasContext *ctx) \ 3106 { \ 3107 int len = MEMOP_GET_SIZE(memop); \ 3108 uint32_t gpr_FC = FC(ctx->opcode); \ 3109 TCGv EA = tcg_temp_local_new(); \ 3110 TCGv_##tp t0, t1; \ 3111 \ 3112 gen_addr_register(ctx, EA); \ 3113 if (len > 1) { \ 3114 gen_check_align(ctx, EA, len - 1); \ 3115 } \ 3116 t0 = tcg_temp_new_##tp(); \ 3117 t1 = tcg_temp_new_##tp(); \ 3118 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3119 \ 3120 switch (gpr_FC) { \ 3121 case 0: /* add and Store */ \ 3122 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3123 break; \ 3124 case 1: /* xor and Store */ \ 3125 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3126 break; \ 3127 case 2: /* Or and Store */ \ 3128 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3129 break; \ 3130 case 3: /* 'and' and Store */ \ 3131 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3132 break; \ 3133 case 4: /* Store max unsigned */ \ 3134 case 5: /* Store max signed */ \ 3135 case 6: /* Store min unsigned */ \ 3136 case 7: /* Store min signed */ \ 3137 case 24: /* Store twin */ \ 3138 gen_invalid(ctx); \ 3139 break; \ 3140 default: \ 3141 /* invoke data storage error handler */ \ 3142 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3143 } \ 3144 tcg_temp_free_##tp(t0); \ 3145 tcg_temp_free_##tp(t1); \ 3146 tcg_temp_free(EA); \ 3147 } 3148 3149 ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) 3150 #if defined(TARGET_PPC64) 3151 ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) 3152 #endif 3153 3154 #if defined(CONFIG_USER_ONLY) 3155 static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3156 int reg, int memop) 3157 { 3158 TCGv t0 = tcg_temp_new(); 3159 3160 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); 3161 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); 3162 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); 3163 tcg_temp_free(t0); 3164 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); 3165 } 3166 #else 3167 static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3168 int reg, int memop) 3169 { 3170 TCGLabel *l1 = gen_new_label(); 3171 TCGLabel *l2 = gen_new_label(); 3172 TCGv t0; 3173 3174 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3175 3176 t0 = tcg_temp_new(); 3177 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3178 cpu_gpr[reg], ctx->mem_idx, 3179 DEF_MEMOP(memop) | MO_ALIGN); 3180 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3181 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3182 tcg_gen_or_tl(t0, t0, cpu_so); 3183 tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3184 tcg_temp_free(t0); 3185 tcg_gen_br(l2); 3186 3187 gen_set_label(l1); 3188 3189 /* Address mismatch implies failure. But we still need to provide the 3190 memory barrier semantics of the instruction. */ 3191 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3192 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3193 3194 gen_set_label(l2); 3195 tcg_gen_movi_tl(cpu_reserve, -1); 3196 } 3197 #endif 3198 3199 #define STCX(name, memop) \ 3200 static void gen_##name(DisasContext *ctx) \ 3201 { \ 3202 TCGv t0; \ 3203 int len = MEMOP_GET_SIZE(memop); \ 3204 gen_set_access_type(ctx, ACCESS_RES); \ 3205 t0 = tcg_temp_local_new(); \ 3206 gen_addr_reg_index(ctx, t0); \ 3207 if (len > 1) { \ 3208 gen_check_align(ctx, t0, (len) - 1); \ 3209 } \ 3210 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ 3211 tcg_temp_free(t0); \ 3212 } 3213 3214 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3215 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3216 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3217 3218 #if defined(TARGET_PPC64) 3219 /* ldarx */ 3220 LARX(ldarx, DEF_MEMOP(MO_Q)) 3221 /* stdcx. */ 3222 STCX(stdcx_, DEF_MEMOP(MO_Q)) 3223 3224 /* lqarx */ 3225 static void gen_lqarx(DisasContext *ctx) 3226 { 3227 TCGv EA; 3228 int rd = rD(ctx->opcode); 3229 TCGv gpr1, gpr2; 3230 3231 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3232 (rd == rB(ctx->opcode)))) { 3233 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3234 return; 3235 } 3236 3237 gen_set_access_type(ctx, ACCESS_RES); 3238 EA = tcg_temp_local_new(); 3239 gen_addr_reg_index(ctx, EA); 3240 gen_check_align(ctx, EA, 15); 3241 if (unlikely(ctx->le_mode)) { 3242 gpr1 = cpu_gpr[rd+1]; 3243 gpr2 = cpu_gpr[rd]; 3244 } else { 3245 gpr1 = cpu_gpr[rd]; 3246 gpr2 = cpu_gpr[rd+1]; 3247 } 3248 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3249 tcg_gen_mov_tl(cpu_reserve, EA); 3250 gen_addr_add(ctx, EA, EA, 8); 3251 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3252 3253 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); 3254 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3255 tcg_temp_free(EA); 3256 } 3257 3258 /* stqcx. */ 3259 static void gen_stqcx_(DisasContext *ctx) 3260 { 3261 TCGv EA; 3262 int reg = rS(ctx->opcode); 3263 int len = 16; 3264 #if !defined(CONFIG_USER_ONLY) 3265 TCGLabel *l1; 3266 TCGv gpr1, gpr2; 3267 #endif 3268 3269 if (unlikely((rD(ctx->opcode) & 1))) { 3270 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3271 return; 3272 } 3273 gen_set_access_type(ctx, ACCESS_RES); 3274 EA = tcg_temp_local_new(); 3275 gen_addr_reg_index(ctx, EA); 3276 if (len > 1) { 3277 gen_check_align(ctx, EA, (len) - 1); 3278 } 3279 3280 #if defined(CONFIG_USER_ONLY) 3281 gen_conditional_store(ctx, EA, reg, 16); 3282 #else 3283 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3284 l1 = gen_new_label(); 3285 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3286 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3287 3288 if (unlikely(ctx->le_mode)) { 3289 gpr1 = cpu_gpr[reg + 1]; 3290 gpr2 = cpu_gpr[reg]; 3291 } else { 3292 gpr1 = cpu_gpr[reg]; 3293 gpr2 = cpu_gpr[reg + 1]; 3294 } 3295 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3296 gen_addr_add(ctx, EA, EA, 8); 3297 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3298 3299 gen_set_label(l1); 3300 tcg_gen_movi_tl(cpu_reserve, -1); 3301 #endif 3302 tcg_temp_free(EA); 3303 } 3304 3305 #endif /* defined(TARGET_PPC64) */ 3306 3307 /* sync */ 3308 static void gen_sync(DisasContext *ctx) 3309 { 3310 uint32_t l = (ctx->opcode >> 21) & 3; 3311 3312 /* 3313 * We may need to check for a pending TLB flush. 3314 * 3315 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3316 * 3317 * Additionally, this can only happen in kernel mode however so 3318 * check MSR_PR as well. 3319 */ 3320 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3321 gen_check_tlb_flush(ctx, true); 3322 } 3323 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3324 } 3325 3326 /* wait */ 3327 static void gen_wait(DisasContext *ctx) 3328 { 3329 TCGv_i32 t0 = tcg_const_i32(1); 3330 tcg_gen_st_i32(t0, cpu_env, 3331 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3332 tcg_temp_free_i32(t0); 3333 /* Stop translation, as the CPU is supposed to sleep from now */ 3334 gen_exception_nip(ctx, EXCP_HLT, ctx->nip); 3335 } 3336 3337 #if defined(TARGET_PPC64) 3338 static void gen_doze(DisasContext *ctx) 3339 { 3340 #if defined(CONFIG_USER_ONLY) 3341 GEN_PRIV; 3342 #else 3343 TCGv_i32 t; 3344 3345 CHK_HV; 3346 t = tcg_const_i32(PPC_PM_DOZE); 3347 gen_helper_pminsn(cpu_env, t); 3348 tcg_temp_free_i32(t); 3349 gen_stop_exception(ctx); 3350 #endif /* defined(CONFIG_USER_ONLY) */ 3351 } 3352 3353 static void gen_nap(DisasContext *ctx) 3354 { 3355 #if defined(CONFIG_USER_ONLY) 3356 GEN_PRIV; 3357 #else 3358 TCGv_i32 t; 3359 3360 CHK_HV; 3361 t = tcg_const_i32(PPC_PM_NAP); 3362 gen_helper_pminsn(cpu_env, t); 3363 tcg_temp_free_i32(t); 3364 gen_stop_exception(ctx); 3365 #endif /* defined(CONFIG_USER_ONLY) */ 3366 } 3367 3368 static void gen_stop(DisasContext *ctx) 3369 { 3370 gen_nap(ctx); 3371 } 3372 3373 static void gen_sleep(DisasContext *ctx) 3374 { 3375 #if defined(CONFIG_USER_ONLY) 3376 GEN_PRIV; 3377 #else 3378 TCGv_i32 t; 3379 3380 CHK_HV; 3381 t = tcg_const_i32(PPC_PM_SLEEP); 3382 gen_helper_pminsn(cpu_env, t); 3383 tcg_temp_free_i32(t); 3384 gen_stop_exception(ctx); 3385 #endif /* defined(CONFIG_USER_ONLY) */ 3386 } 3387 3388 static void gen_rvwinkle(DisasContext *ctx) 3389 { 3390 #if defined(CONFIG_USER_ONLY) 3391 GEN_PRIV; 3392 #else 3393 TCGv_i32 t; 3394 3395 CHK_HV; 3396 t = tcg_const_i32(PPC_PM_RVWINKLE); 3397 gen_helper_pminsn(cpu_env, t); 3398 tcg_temp_free_i32(t); 3399 gen_stop_exception(ctx); 3400 #endif /* defined(CONFIG_USER_ONLY) */ 3401 } 3402 #endif /* #if defined(TARGET_PPC64) */ 3403 3404 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3405 { 3406 #if defined(TARGET_PPC64) 3407 if (ctx->has_cfar) 3408 tcg_gen_movi_tl(cpu_cfar, nip); 3409 #endif 3410 } 3411 3412 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3413 { 3414 if (unlikely(ctx->singlestep_enabled)) { 3415 return false; 3416 } 3417 3418 #ifndef CONFIG_USER_ONLY 3419 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3420 #else 3421 return true; 3422 #endif 3423 } 3424 3425 /*** Branch ***/ 3426 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3427 { 3428 if (NARROW_MODE(ctx)) { 3429 dest = (uint32_t) dest; 3430 } 3431 if (use_goto_tb(ctx, dest)) { 3432 tcg_gen_goto_tb(n); 3433 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3434 tcg_gen_exit_tb((uintptr_t)ctx->tb + n); 3435 } else { 3436 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3437 if (unlikely(ctx->singlestep_enabled)) { 3438 if ((ctx->singlestep_enabled & 3439 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && 3440 (ctx->exception == POWERPC_EXCP_BRANCH || 3441 ctx->exception == POWERPC_EXCP_TRACE)) { 3442 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest); 3443 } 3444 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { 3445 gen_debug_exception(ctx); 3446 } 3447 } 3448 tcg_gen_exit_tb(0); 3449 } 3450 } 3451 3452 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3453 { 3454 if (NARROW_MODE(ctx)) { 3455 nip = (uint32_t)nip; 3456 } 3457 tcg_gen_movi_tl(cpu_lr, nip); 3458 } 3459 3460 /* b ba bl bla */ 3461 static void gen_b(DisasContext *ctx) 3462 { 3463 target_ulong li, target; 3464 3465 ctx->exception = POWERPC_EXCP_BRANCH; 3466 /* sign extend LI */ 3467 li = LI(ctx->opcode); 3468 li = (li ^ 0x02000000) - 0x02000000; 3469 if (likely(AA(ctx->opcode) == 0)) { 3470 target = ctx->nip + li - 4; 3471 } else { 3472 target = li; 3473 } 3474 if (LK(ctx->opcode)) { 3475 gen_setlr(ctx, ctx->nip); 3476 } 3477 gen_update_cfar(ctx, ctx->nip - 4); 3478 gen_goto_tb(ctx, 0, target); 3479 } 3480 3481 #define BCOND_IM 0 3482 #define BCOND_LR 1 3483 #define BCOND_CTR 2 3484 #define BCOND_TAR 3 3485 3486 static inline void gen_bcond(DisasContext *ctx, int type) 3487 { 3488 uint32_t bo = BO(ctx->opcode); 3489 TCGLabel *l1; 3490 TCGv target; 3491 3492 ctx->exception = POWERPC_EXCP_BRANCH; 3493 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3494 target = tcg_temp_local_new(); 3495 if (type == BCOND_CTR) 3496 tcg_gen_mov_tl(target, cpu_ctr); 3497 else if (type == BCOND_TAR) 3498 gen_load_spr(target, SPR_TAR); 3499 else 3500 tcg_gen_mov_tl(target, cpu_lr); 3501 } else { 3502 TCGV_UNUSED(target); 3503 } 3504 if (LK(ctx->opcode)) 3505 gen_setlr(ctx, ctx->nip); 3506 l1 = gen_new_label(); 3507 if ((bo & 0x4) == 0) { 3508 /* Decrement and test CTR */ 3509 TCGv temp = tcg_temp_new(); 3510 if (unlikely(type == BCOND_CTR)) { 3511 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3512 return; 3513 } 3514 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3515 if (NARROW_MODE(ctx)) { 3516 tcg_gen_ext32u_tl(temp, cpu_ctr); 3517 } else { 3518 tcg_gen_mov_tl(temp, cpu_ctr); 3519 } 3520 if (bo & 0x2) { 3521 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3522 } else { 3523 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3524 } 3525 tcg_temp_free(temp); 3526 } 3527 if ((bo & 0x10) == 0) { 3528 /* Test CR */ 3529 uint32_t bi = BI(ctx->opcode); 3530 uint32_t mask = 0x08 >> (bi & 0x03); 3531 TCGv_i32 temp = tcg_temp_new_i32(); 3532 3533 if (bo & 0x8) { 3534 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3535 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3536 } else { 3537 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3538 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3539 } 3540 tcg_temp_free_i32(temp); 3541 } 3542 gen_update_cfar(ctx, ctx->nip - 4); 3543 if (type == BCOND_IM) { 3544 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3545 if (likely(AA(ctx->opcode) == 0)) { 3546 gen_goto_tb(ctx, 0, ctx->nip + li - 4); 3547 } else { 3548 gen_goto_tb(ctx, 0, li); 3549 } 3550 if ((bo & 0x14) != 0x14) { 3551 gen_set_label(l1); 3552 gen_goto_tb(ctx, 1, ctx->nip); 3553 } 3554 } else { 3555 if (NARROW_MODE(ctx)) { 3556 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3557 } else { 3558 tcg_gen_andi_tl(cpu_nip, target, ~3); 3559 } 3560 tcg_gen_exit_tb(0); 3561 if ((bo & 0x14) != 0x14) { 3562 gen_set_label(l1); 3563 gen_update_nip(ctx, ctx->nip); 3564 tcg_gen_exit_tb(0); 3565 } 3566 } 3567 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3568 tcg_temp_free(target); 3569 } 3570 } 3571 3572 static void gen_bc(DisasContext *ctx) 3573 { 3574 gen_bcond(ctx, BCOND_IM); 3575 } 3576 3577 static void gen_bcctr(DisasContext *ctx) 3578 { 3579 gen_bcond(ctx, BCOND_CTR); 3580 } 3581 3582 static void gen_bclr(DisasContext *ctx) 3583 { 3584 gen_bcond(ctx, BCOND_LR); 3585 } 3586 3587 static void gen_bctar(DisasContext *ctx) 3588 { 3589 gen_bcond(ctx, BCOND_TAR); 3590 } 3591 3592 /*** Condition register logical ***/ 3593 #define GEN_CRLOGIC(name, tcg_op, opc) \ 3594 static void glue(gen_, name)(DisasContext *ctx) \ 3595 { \ 3596 uint8_t bitmask; \ 3597 int sh; \ 3598 TCGv_i32 t0, t1; \ 3599 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3600 t0 = tcg_temp_new_i32(); \ 3601 if (sh > 0) \ 3602 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3603 else if (sh < 0) \ 3604 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3605 else \ 3606 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3607 t1 = tcg_temp_new_i32(); \ 3608 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3609 if (sh > 0) \ 3610 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3611 else if (sh < 0) \ 3612 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3613 else \ 3614 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3615 tcg_op(t0, t0, t1); \ 3616 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3617 tcg_gen_andi_i32(t0, t0, bitmask); \ 3618 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3619 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3620 tcg_temp_free_i32(t0); \ 3621 tcg_temp_free_i32(t1); \ 3622 } 3623 3624 /* crand */ 3625 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3626 /* crandc */ 3627 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3628 /* creqv */ 3629 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3630 /* crnand */ 3631 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3632 /* crnor */ 3633 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3634 /* cror */ 3635 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3636 /* crorc */ 3637 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3638 /* crxor */ 3639 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3640 3641 /* mcrf */ 3642 static void gen_mcrf(DisasContext *ctx) 3643 { 3644 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3645 } 3646 3647 /*** System linkage ***/ 3648 3649 /* rfi (supervisor only) */ 3650 static void gen_rfi(DisasContext *ctx) 3651 { 3652 #if defined(CONFIG_USER_ONLY) 3653 GEN_PRIV; 3654 #else 3655 /* This instruction doesn't exist anymore on 64-bit server 3656 * processors compliant with arch 2.x 3657 */ 3658 if (ctx->insns_flags & PPC_SEGMENT_64B) { 3659 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3660 return; 3661 } 3662 /* Restore CPU state */ 3663 CHK_SV; 3664 gen_update_cfar(ctx, ctx->nip - 4); 3665 gen_helper_rfi(cpu_env); 3666 gen_sync_exception(ctx); 3667 #endif 3668 } 3669 3670 #if defined(TARGET_PPC64) 3671 static void gen_rfid(DisasContext *ctx) 3672 { 3673 #if defined(CONFIG_USER_ONLY) 3674 GEN_PRIV; 3675 #else 3676 /* Restore CPU state */ 3677 CHK_SV; 3678 gen_update_cfar(ctx, ctx->nip - 4); 3679 gen_helper_rfid(cpu_env); 3680 gen_sync_exception(ctx); 3681 #endif 3682 } 3683 3684 static void gen_hrfid(DisasContext *ctx) 3685 { 3686 #if defined(CONFIG_USER_ONLY) 3687 GEN_PRIV; 3688 #else 3689 /* Restore CPU state */ 3690 CHK_HV; 3691 gen_helper_hrfid(cpu_env); 3692 gen_sync_exception(ctx); 3693 #endif 3694 } 3695 #endif 3696 3697 /* sc */ 3698 #if defined(CONFIG_USER_ONLY) 3699 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3700 #else 3701 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3702 #endif 3703 static void gen_sc(DisasContext *ctx) 3704 { 3705 uint32_t lev; 3706 3707 lev = (ctx->opcode >> 5) & 0x7F; 3708 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3709 } 3710 3711 /*** Trap ***/ 3712 3713 /* Check for unconditional traps (always or never) */ 3714 static bool check_unconditional_trap(DisasContext *ctx) 3715 { 3716 /* Trap never */ 3717 if (TO(ctx->opcode) == 0) { 3718 return true; 3719 } 3720 /* Trap always */ 3721 if (TO(ctx->opcode) == 31) { 3722 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3723 return true; 3724 } 3725 return false; 3726 } 3727 3728 /* tw */ 3729 static void gen_tw(DisasContext *ctx) 3730 { 3731 TCGv_i32 t0; 3732 3733 if (check_unconditional_trap(ctx)) { 3734 return; 3735 } 3736 t0 = tcg_const_i32(TO(ctx->opcode)); 3737 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3738 t0); 3739 tcg_temp_free_i32(t0); 3740 } 3741 3742 /* twi */ 3743 static void gen_twi(DisasContext *ctx) 3744 { 3745 TCGv t0; 3746 TCGv_i32 t1; 3747 3748 if (check_unconditional_trap(ctx)) { 3749 return; 3750 } 3751 t0 = tcg_const_tl(SIMM(ctx->opcode)); 3752 t1 = tcg_const_i32(TO(ctx->opcode)); 3753 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3754 tcg_temp_free(t0); 3755 tcg_temp_free_i32(t1); 3756 } 3757 3758 #if defined(TARGET_PPC64) 3759 /* td */ 3760 static void gen_td(DisasContext *ctx) 3761 { 3762 TCGv_i32 t0; 3763 3764 if (check_unconditional_trap(ctx)) { 3765 return; 3766 } 3767 t0 = tcg_const_i32(TO(ctx->opcode)); 3768 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3769 t0); 3770 tcg_temp_free_i32(t0); 3771 } 3772 3773 /* tdi */ 3774 static void gen_tdi(DisasContext *ctx) 3775 { 3776 TCGv t0; 3777 TCGv_i32 t1; 3778 3779 if (check_unconditional_trap(ctx)) { 3780 return; 3781 } 3782 t0 = tcg_const_tl(SIMM(ctx->opcode)); 3783 t1 = tcg_const_i32(TO(ctx->opcode)); 3784 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3785 tcg_temp_free(t0); 3786 tcg_temp_free_i32(t1); 3787 } 3788 #endif 3789 3790 /*** Processor control ***/ 3791 3792 static void gen_read_xer(DisasContext *ctx, TCGv dst) 3793 { 3794 TCGv t0 = tcg_temp_new(); 3795 TCGv t1 = tcg_temp_new(); 3796 TCGv t2 = tcg_temp_new(); 3797 tcg_gen_mov_tl(dst, cpu_xer); 3798 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 3799 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 3800 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 3801 tcg_gen_or_tl(t0, t0, t1); 3802 tcg_gen_or_tl(dst, dst, t2); 3803 tcg_gen_or_tl(dst, dst, t0); 3804 if (is_isa300(ctx)) { 3805 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 3806 tcg_gen_or_tl(dst, dst, t0); 3807 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 3808 tcg_gen_or_tl(dst, dst, t0); 3809 } 3810 tcg_temp_free(t0); 3811 tcg_temp_free(t1); 3812 tcg_temp_free(t2); 3813 } 3814 3815 static void gen_write_xer(TCGv src) 3816 { 3817 /* Write all flags, while reading back check for isa300 */ 3818 tcg_gen_andi_tl(cpu_xer, src, 3819 ~((1u << XER_SO) | 3820 (1u << XER_OV) | (1u << XER_OV32) | 3821 (1u << XER_CA) | (1u << XER_CA32))); 3822 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 3823 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 3824 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 3825 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 3826 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 3827 } 3828 3829 /* mcrxr */ 3830 static void gen_mcrxr(DisasContext *ctx) 3831 { 3832 TCGv_i32 t0 = tcg_temp_new_i32(); 3833 TCGv_i32 t1 = tcg_temp_new_i32(); 3834 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 3835 3836 tcg_gen_trunc_tl_i32(t0, cpu_so); 3837 tcg_gen_trunc_tl_i32(t1, cpu_ov); 3838 tcg_gen_trunc_tl_i32(dst, cpu_ca); 3839 tcg_gen_shli_i32(t0, t0, 3); 3840 tcg_gen_shli_i32(t1, t1, 2); 3841 tcg_gen_shli_i32(dst, dst, 1); 3842 tcg_gen_or_i32(dst, dst, t0); 3843 tcg_gen_or_i32(dst, dst, t1); 3844 tcg_temp_free_i32(t0); 3845 tcg_temp_free_i32(t1); 3846 3847 tcg_gen_movi_tl(cpu_so, 0); 3848 tcg_gen_movi_tl(cpu_ov, 0); 3849 tcg_gen_movi_tl(cpu_ca, 0); 3850 } 3851 3852 #ifdef TARGET_PPC64 3853 /* mcrxrx */ 3854 static void gen_mcrxrx(DisasContext *ctx) 3855 { 3856 TCGv t0 = tcg_temp_new(); 3857 TCGv t1 = tcg_temp_new(); 3858 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 3859 3860 /* copy OV and OV32 */ 3861 tcg_gen_shli_tl(t0, cpu_ov, 1); 3862 tcg_gen_or_tl(t0, t0, cpu_ov32); 3863 tcg_gen_shli_tl(t0, t0, 2); 3864 /* copy CA and CA32 */ 3865 tcg_gen_shli_tl(t1, cpu_ca, 1); 3866 tcg_gen_or_tl(t1, t1, cpu_ca32); 3867 tcg_gen_or_tl(t0, t0, t1); 3868 tcg_gen_trunc_tl_i32(dst, t0); 3869 tcg_temp_free(t0); 3870 tcg_temp_free(t1); 3871 } 3872 #endif 3873 3874 /* mfcr mfocrf */ 3875 static void gen_mfcr(DisasContext *ctx) 3876 { 3877 uint32_t crm, crn; 3878 3879 if (likely(ctx->opcode & 0x00100000)) { 3880 crm = CRM(ctx->opcode); 3881 if (likely(crm && ((crm & (crm - 1)) == 0))) { 3882 crn = ctz32 (crm); 3883 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 3884 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 3885 cpu_gpr[rD(ctx->opcode)], crn * 4); 3886 } 3887 } else { 3888 TCGv_i32 t0 = tcg_temp_new_i32(); 3889 tcg_gen_mov_i32(t0, cpu_crf[0]); 3890 tcg_gen_shli_i32(t0, t0, 4); 3891 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 3892 tcg_gen_shli_i32(t0, t0, 4); 3893 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 3894 tcg_gen_shli_i32(t0, t0, 4); 3895 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 3896 tcg_gen_shli_i32(t0, t0, 4); 3897 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 3898 tcg_gen_shli_i32(t0, t0, 4); 3899 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 3900 tcg_gen_shli_i32(t0, t0, 4); 3901 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 3902 tcg_gen_shli_i32(t0, t0, 4); 3903 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 3904 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 3905 tcg_temp_free_i32(t0); 3906 } 3907 } 3908 3909 /* mfmsr */ 3910 static void gen_mfmsr(DisasContext *ctx) 3911 { 3912 CHK_SV; 3913 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 3914 } 3915 3916 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 3917 { 3918 #if 0 3919 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 3920 printf("ERROR: try to access SPR %d !\n", sprn); 3921 #endif 3922 } 3923 #define SPR_NOACCESS (&spr_noaccess) 3924 3925 /* mfspr */ 3926 static inline void gen_op_mfspr(DisasContext *ctx) 3927 { 3928 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 3929 uint32_t sprn = SPR(ctx->opcode); 3930 3931 #if defined(CONFIG_USER_ONLY) 3932 read_cb = ctx->spr_cb[sprn].uea_read; 3933 #else 3934 if (ctx->pr) { 3935 read_cb = ctx->spr_cb[sprn].uea_read; 3936 } else if (ctx->hv) { 3937 read_cb = ctx->spr_cb[sprn].hea_read; 3938 } else { 3939 read_cb = ctx->spr_cb[sprn].oea_read; 3940 } 3941 #endif 3942 if (likely(read_cb != NULL)) { 3943 if (likely(read_cb != SPR_NOACCESS)) { 3944 (*read_cb)(ctx, rD(ctx->opcode), sprn); 3945 } else { 3946 /* Privilege exception */ 3947 /* This is a hack to avoid warnings when running Linux: 3948 * this OS breaks the PowerPC virtualisation model, 3949 * allowing userland application to read the PVR 3950 */ 3951 if (sprn != SPR_PVR) { 3952 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at " 3953 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3954 if (qemu_log_separate()) { 3955 qemu_log("Trying to read privileged spr %d (0x%03x) at " 3956 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3957 } 3958 } 3959 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 3960 } 3961 } else { 3962 /* ISA 2.07 defines these as no-ops */ 3963 if ((ctx->insns_flags2 & PPC2_ISA207S) && 3964 (sprn >= 808 && sprn <= 811)) { 3965 /* This is a nop */ 3966 return; 3967 } 3968 /* Not defined */ 3969 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at " 3970 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3971 if (qemu_log_separate()) { 3972 qemu_log("Trying to read invalid spr %d (0x%03x) at " 3973 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3974 } 3975 3976 /* The behaviour depends on MSR:PR and SPR# bit 0x10, 3977 * it can generate a priv, a hv emu or a no-op 3978 */ 3979 if (sprn & 0x10) { 3980 if (ctx->pr) { 3981 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3982 } 3983 } else { 3984 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 3985 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3986 } 3987 } 3988 } 3989 } 3990 3991 static void gen_mfspr(DisasContext *ctx) 3992 { 3993 gen_op_mfspr(ctx); 3994 } 3995 3996 /* mftb */ 3997 static void gen_mftb(DisasContext *ctx) 3998 { 3999 gen_op_mfspr(ctx); 4000 } 4001 4002 /* mtcrf mtocrf*/ 4003 static void gen_mtcrf(DisasContext *ctx) 4004 { 4005 uint32_t crm, crn; 4006 4007 crm = CRM(ctx->opcode); 4008 if (likely((ctx->opcode & 0x00100000))) { 4009 if (crm && ((crm & (crm - 1)) == 0)) { 4010 TCGv_i32 temp = tcg_temp_new_i32(); 4011 crn = ctz32 (crm); 4012 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4013 tcg_gen_shri_i32(temp, temp, crn * 4); 4014 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4015 tcg_temp_free_i32(temp); 4016 } 4017 } else { 4018 TCGv_i32 temp = tcg_temp_new_i32(); 4019 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4020 for (crn = 0 ; crn < 8 ; crn++) { 4021 if (crm & (1 << crn)) { 4022 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4023 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4024 } 4025 } 4026 tcg_temp_free_i32(temp); 4027 } 4028 } 4029 4030 /* mtmsr */ 4031 #if defined(TARGET_PPC64) 4032 static void gen_mtmsrd(DisasContext *ctx) 4033 { 4034 CHK_SV; 4035 4036 #if !defined(CONFIG_USER_ONLY) 4037 if (ctx->opcode & 0x00010000) { 4038 /* Special form that does not need any synchronisation */ 4039 TCGv t0 = tcg_temp_new(); 4040 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4041 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4042 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4043 tcg_temp_free(t0); 4044 } else { 4045 /* XXX: we need to update nip before the store 4046 * if we enter power saving mode, we will exit the loop 4047 * directly from ppc_store_msr 4048 */ 4049 gen_update_nip(ctx, ctx->nip); 4050 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4051 /* Must stop the translation as machine state (may have) changed */ 4052 /* Note that mtmsr is not always defined as context-synchronizing */ 4053 gen_stop_exception(ctx); 4054 } 4055 #endif /* !defined(CONFIG_USER_ONLY) */ 4056 } 4057 #endif /* defined(TARGET_PPC64) */ 4058 4059 static void gen_mtmsr(DisasContext *ctx) 4060 { 4061 CHK_SV; 4062 4063 #if !defined(CONFIG_USER_ONLY) 4064 if (ctx->opcode & 0x00010000) { 4065 /* Special form that does not need any synchronisation */ 4066 TCGv t0 = tcg_temp_new(); 4067 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4068 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4069 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4070 tcg_temp_free(t0); 4071 } else { 4072 TCGv msr = tcg_temp_new(); 4073 4074 /* XXX: we need to update nip before the store 4075 * if we enter power saving mode, we will exit the loop 4076 * directly from ppc_store_msr 4077 */ 4078 gen_update_nip(ctx, ctx->nip); 4079 #if defined(TARGET_PPC64) 4080 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4081 #else 4082 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4083 #endif 4084 gen_helper_store_msr(cpu_env, msr); 4085 tcg_temp_free(msr); 4086 /* Must stop the translation as machine state (may have) changed */ 4087 /* Note that mtmsr is not always defined as context-synchronizing */ 4088 gen_stop_exception(ctx); 4089 } 4090 #endif 4091 } 4092 4093 /* mtspr */ 4094 static void gen_mtspr(DisasContext *ctx) 4095 { 4096 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4097 uint32_t sprn = SPR(ctx->opcode); 4098 4099 #if defined(CONFIG_USER_ONLY) 4100 write_cb = ctx->spr_cb[sprn].uea_write; 4101 #else 4102 if (ctx->pr) { 4103 write_cb = ctx->spr_cb[sprn].uea_write; 4104 } else if (ctx->hv) { 4105 write_cb = ctx->spr_cb[sprn].hea_write; 4106 } else { 4107 write_cb = ctx->spr_cb[sprn].oea_write; 4108 } 4109 #endif 4110 if (likely(write_cb != NULL)) { 4111 if (likely(write_cb != SPR_NOACCESS)) { 4112 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4113 } else { 4114 /* Privilege exception */ 4115 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at " 4116 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4117 if (qemu_log_separate()) { 4118 qemu_log("Trying to write privileged spr %d (0x%03x) at " 4119 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4120 } 4121 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4122 } 4123 } else { 4124 /* ISA 2.07 defines these as no-ops */ 4125 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4126 (sprn >= 808 && sprn <= 811)) { 4127 /* This is a nop */ 4128 return; 4129 } 4130 4131 /* Not defined */ 4132 if (qemu_log_separate()) { 4133 qemu_log("Trying to write invalid spr %d (0x%03x) at " 4134 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4135 } 4136 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at " 4137 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4138 4139 4140 /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4141 * it can generate a priv, a hv emu or a no-op 4142 */ 4143 if (sprn & 0x10) { 4144 if (ctx->pr) { 4145 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4146 } 4147 } else { 4148 if (ctx->pr || sprn == 0) { 4149 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4150 } 4151 } 4152 } 4153 } 4154 4155 #if defined(TARGET_PPC64) 4156 /* setb */ 4157 static void gen_setb(DisasContext *ctx) 4158 { 4159 TCGv_i32 t0 = tcg_temp_new_i32(); 4160 TCGv_i32 t8 = tcg_temp_new_i32(); 4161 TCGv_i32 tm1 = tcg_temp_new_i32(); 4162 int crf = crfS(ctx->opcode); 4163 4164 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4165 tcg_gen_movi_i32(t8, 8); 4166 tcg_gen_movi_i32(tm1, -1); 4167 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4168 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4169 4170 tcg_temp_free_i32(t0); 4171 tcg_temp_free_i32(t8); 4172 tcg_temp_free_i32(tm1); 4173 } 4174 #endif 4175 4176 /*** Cache management ***/ 4177 4178 /* dcbf */ 4179 static void gen_dcbf(DisasContext *ctx) 4180 { 4181 /* XXX: specification says this is treated as a load by the MMU */ 4182 TCGv t0; 4183 gen_set_access_type(ctx, ACCESS_CACHE); 4184 t0 = tcg_temp_new(); 4185 gen_addr_reg_index(ctx, t0); 4186 gen_qemu_ld8u(ctx, t0, t0); 4187 tcg_temp_free(t0); 4188 } 4189 4190 /* dcbi (Supervisor only) */ 4191 static void gen_dcbi(DisasContext *ctx) 4192 { 4193 #if defined(CONFIG_USER_ONLY) 4194 GEN_PRIV; 4195 #else 4196 TCGv EA, val; 4197 4198 CHK_SV; 4199 EA = tcg_temp_new(); 4200 gen_set_access_type(ctx, ACCESS_CACHE); 4201 gen_addr_reg_index(ctx, EA); 4202 val = tcg_temp_new(); 4203 /* XXX: specification says this should be treated as a store by the MMU */ 4204 gen_qemu_ld8u(ctx, val, EA); 4205 gen_qemu_st8(ctx, val, EA); 4206 tcg_temp_free(val); 4207 tcg_temp_free(EA); 4208 #endif /* defined(CONFIG_USER_ONLY) */ 4209 } 4210 4211 /* dcdst */ 4212 static void gen_dcbst(DisasContext *ctx) 4213 { 4214 /* XXX: specification say this is treated as a load by the MMU */ 4215 TCGv t0; 4216 gen_set_access_type(ctx, ACCESS_CACHE); 4217 t0 = tcg_temp_new(); 4218 gen_addr_reg_index(ctx, t0); 4219 gen_qemu_ld8u(ctx, t0, t0); 4220 tcg_temp_free(t0); 4221 } 4222 4223 /* dcbt */ 4224 static void gen_dcbt(DisasContext *ctx) 4225 { 4226 /* interpreted as no-op */ 4227 /* XXX: specification say this is treated as a load by the MMU 4228 * but does not generate any exception 4229 */ 4230 } 4231 4232 /* dcbtst */ 4233 static void gen_dcbtst(DisasContext *ctx) 4234 { 4235 /* interpreted as no-op */ 4236 /* XXX: specification say this is treated as a load by the MMU 4237 * but does not generate any exception 4238 */ 4239 } 4240 4241 /* dcbtls */ 4242 static void gen_dcbtls(DisasContext *ctx) 4243 { 4244 /* Always fails locking the cache */ 4245 TCGv t0 = tcg_temp_new(); 4246 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4247 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4248 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4249 tcg_temp_free(t0); 4250 } 4251 4252 /* dcbz */ 4253 static void gen_dcbz(DisasContext *ctx) 4254 { 4255 TCGv tcgv_addr; 4256 TCGv_i32 tcgv_op; 4257 4258 gen_set_access_type(ctx, ACCESS_CACHE); 4259 tcgv_addr = tcg_temp_new(); 4260 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4261 gen_addr_reg_index(ctx, tcgv_addr); 4262 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4263 tcg_temp_free(tcgv_addr); 4264 tcg_temp_free_i32(tcgv_op); 4265 } 4266 4267 /* dst / dstt */ 4268 static void gen_dst(DisasContext *ctx) 4269 { 4270 if (rA(ctx->opcode) == 0) { 4271 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4272 } else { 4273 /* interpreted as no-op */ 4274 } 4275 } 4276 4277 /* dstst /dststt */ 4278 static void gen_dstst(DisasContext *ctx) 4279 { 4280 if (rA(ctx->opcode) == 0) { 4281 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4282 } else { 4283 /* interpreted as no-op */ 4284 } 4285 4286 } 4287 4288 /* dss / dssall */ 4289 static void gen_dss(DisasContext *ctx) 4290 { 4291 /* interpreted as no-op */ 4292 } 4293 4294 /* icbi */ 4295 static void gen_icbi(DisasContext *ctx) 4296 { 4297 TCGv t0; 4298 gen_set_access_type(ctx, ACCESS_CACHE); 4299 t0 = tcg_temp_new(); 4300 gen_addr_reg_index(ctx, t0); 4301 gen_helper_icbi(cpu_env, t0); 4302 tcg_temp_free(t0); 4303 } 4304 4305 /* Optional: */ 4306 /* dcba */ 4307 static void gen_dcba(DisasContext *ctx) 4308 { 4309 /* interpreted as no-op */ 4310 /* XXX: specification say this is treated as a store by the MMU 4311 * but does not generate any exception 4312 */ 4313 } 4314 4315 /*** Segment register manipulation ***/ 4316 /* Supervisor only: */ 4317 4318 /* mfsr */ 4319 static void gen_mfsr(DisasContext *ctx) 4320 { 4321 #if defined(CONFIG_USER_ONLY) 4322 GEN_PRIV; 4323 #else 4324 TCGv t0; 4325 4326 CHK_SV; 4327 t0 = tcg_const_tl(SR(ctx->opcode)); 4328 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4329 tcg_temp_free(t0); 4330 #endif /* defined(CONFIG_USER_ONLY) */ 4331 } 4332 4333 /* mfsrin */ 4334 static void gen_mfsrin(DisasContext *ctx) 4335 { 4336 #if defined(CONFIG_USER_ONLY) 4337 GEN_PRIV; 4338 #else 4339 TCGv t0; 4340 4341 CHK_SV; 4342 t0 = tcg_temp_new(); 4343 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4344 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4345 tcg_temp_free(t0); 4346 #endif /* defined(CONFIG_USER_ONLY) */ 4347 } 4348 4349 /* mtsr */ 4350 static void gen_mtsr(DisasContext *ctx) 4351 { 4352 #if defined(CONFIG_USER_ONLY) 4353 GEN_PRIV; 4354 #else 4355 TCGv t0; 4356 4357 CHK_SV; 4358 t0 = tcg_const_tl(SR(ctx->opcode)); 4359 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4360 tcg_temp_free(t0); 4361 #endif /* defined(CONFIG_USER_ONLY) */ 4362 } 4363 4364 /* mtsrin */ 4365 static void gen_mtsrin(DisasContext *ctx) 4366 { 4367 #if defined(CONFIG_USER_ONLY) 4368 GEN_PRIV; 4369 #else 4370 TCGv t0; 4371 CHK_SV; 4372 4373 t0 = tcg_temp_new(); 4374 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4375 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4376 tcg_temp_free(t0); 4377 #endif /* defined(CONFIG_USER_ONLY) */ 4378 } 4379 4380 #if defined(TARGET_PPC64) 4381 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4382 4383 /* mfsr */ 4384 static void gen_mfsr_64b(DisasContext *ctx) 4385 { 4386 #if defined(CONFIG_USER_ONLY) 4387 GEN_PRIV; 4388 #else 4389 TCGv t0; 4390 4391 CHK_SV; 4392 t0 = tcg_const_tl(SR(ctx->opcode)); 4393 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4394 tcg_temp_free(t0); 4395 #endif /* defined(CONFIG_USER_ONLY) */ 4396 } 4397 4398 /* mfsrin */ 4399 static void gen_mfsrin_64b(DisasContext *ctx) 4400 { 4401 #if defined(CONFIG_USER_ONLY) 4402 GEN_PRIV; 4403 #else 4404 TCGv t0; 4405 4406 CHK_SV; 4407 t0 = tcg_temp_new(); 4408 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4409 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4410 tcg_temp_free(t0); 4411 #endif /* defined(CONFIG_USER_ONLY) */ 4412 } 4413 4414 /* mtsr */ 4415 static void gen_mtsr_64b(DisasContext *ctx) 4416 { 4417 #if defined(CONFIG_USER_ONLY) 4418 GEN_PRIV; 4419 #else 4420 TCGv t0; 4421 4422 CHK_SV; 4423 t0 = tcg_const_tl(SR(ctx->opcode)); 4424 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4425 tcg_temp_free(t0); 4426 #endif /* defined(CONFIG_USER_ONLY) */ 4427 } 4428 4429 /* mtsrin */ 4430 static void gen_mtsrin_64b(DisasContext *ctx) 4431 { 4432 #if defined(CONFIG_USER_ONLY) 4433 GEN_PRIV; 4434 #else 4435 TCGv t0; 4436 4437 CHK_SV; 4438 t0 = tcg_temp_new(); 4439 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4440 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4441 tcg_temp_free(t0); 4442 #endif /* defined(CONFIG_USER_ONLY) */ 4443 } 4444 4445 /* slbmte */ 4446 static void gen_slbmte(DisasContext *ctx) 4447 { 4448 #if defined(CONFIG_USER_ONLY) 4449 GEN_PRIV; 4450 #else 4451 CHK_SV; 4452 4453 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4454 cpu_gpr[rS(ctx->opcode)]); 4455 #endif /* defined(CONFIG_USER_ONLY) */ 4456 } 4457 4458 static void gen_slbmfee(DisasContext *ctx) 4459 { 4460 #if defined(CONFIG_USER_ONLY) 4461 GEN_PRIV; 4462 #else 4463 CHK_SV; 4464 4465 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4466 cpu_gpr[rB(ctx->opcode)]); 4467 #endif /* defined(CONFIG_USER_ONLY) */ 4468 } 4469 4470 static void gen_slbmfev(DisasContext *ctx) 4471 { 4472 #if defined(CONFIG_USER_ONLY) 4473 GEN_PRIV; 4474 #else 4475 CHK_SV; 4476 4477 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4478 cpu_gpr[rB(ctx->opcode)]); 4479 #endif /* defined(CONFIG_USER_ONLY) */ 4480 } 4481 4482 static void gen_slbfee_(DisasContext *ctx) 4483 { 4484 #if defined(CONFIG_USER_ONLY) 4485 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4486 #else 4487 TCGLabel *l1, *l2; 4488 4489 if (unlikely(ctx->pr)) { 4490 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4491 return; 4492 } 4493 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4494 cpu_gpr[rB(ctx->opcode)]); 4495 l1 = gen_new_label(); 4496 l2 = gen_new_label(); 4497 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4498 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4499 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4500 tcg_gen_br(l2); 4501 gen_set_label(l1); 4502 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4503 gen_set_label(l2); 4504 #endif 4505 } 4506 #endif /* defined(TARGET_PPC64) */ 4507 4508 /*** Lookaside buffer management ***/ 4509 /* Optional & supervisor only: */ 4510 4511 /* tlbia */ 4512 static void gen_tlbia(DisasContext *ctx) 4513 { 4514 #if defined(CONFIG_USER_ONLY) 4515 GEN_PRIV; 4516 #else 4517 CHK_HV; 4518 4519 gen_helper_tlbia(cpu_env); 4520 #endif /* defined(CONFIG_USER_ONLY) */ 4521 } 4522 4523 /* tlbiel */ 4524 static void gen_tlbiel(DisasContext *ctx) 4525 { 4526 #if defined(CONFIG_USER_ONLY) 4527 GEN_PRIV; 4528 #else 4529 CHK_SV; 4530 4531 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4532 #endif /* defined(CONFIG_USER_ONLY) */ 4533 } 4534 4535 /* tlbie */ 4536 static void gen_tlbie(DisasContext *ctx) 4537 { 4538 #if defined(CONFIG_USER_ONLY) 4539 GEN_PRIV; 4540 #else 4541 TCGv_i32 t1; 4542 4543 if (ctx->gtse) { 4544 CHK_SV; /* If gtse is set then tblie is supervisor privileged */ 4545 } else { 4546 CHK_HV; /* Else hypervisor privileged */ 4547 } 4548 4549 if (NARROW_MODE(ctx)) { 4550 TCGv t0 = tcg_temp_new(); 4551 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4552 gen_helper_tlbie(cpu_env, t0); 4553 tcg_temp_free(t0); 4554 } else { 4555 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4556 } 4557 t1 = tcg_temp_new_i32(); 4558 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4559 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4560 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4561 tcg_temp_free_i32(t1); 4562 #endif /* defined(CONFIG_USER_ONLY) */ 4563 } 4564 4565 /* tlbsync */ 4566 static void gen_tlbsync(DisasContext *ctx) 4567 { 4568 #if defined(CONFIG_USER_ONLY) 4569 GEN_PRIV; 4570 #else 4571 CHK_HV; 4572 4573 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4574 if (ctx->insns_flags & PPC_BOOKE) { 4575 gen_check_tlb_flush(ctx, true); 4576 } 4577 #endif /* defined(CONFIG_USER_ONLY) */ 4578 } 4579 4580 #if defined(TARGET_PPC64) 4581 /* slbia */ 4582 static void gen_slbia(DisasContext *ctx) 4583 { 4584 #if defined(CONFIG_USER_ONLY) 4585 GEN_PRIV; 4586 #else 4587 CHK_SV; 4588 4589 gen_helper_slbia(cpu_env); 4590 #endif /* defined(CONFIG_USER_ONLY) */ 4591 } 4592 4593 /* slbie */ 4594 static void gen_slbie(DisasContext *ctx) 4595 { 4596 #if defined(CONFIG_USER_ONLY) 4597 GEN_PRIV; 4598 #else 4599 CHK_SV; 4600 4601 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4602 #endif /* defined(CONFIG_USER_ONLY) */ 4603 } 4604 4605 /* slbieg */ 4606 static void gen_slbieg(DisasContext *ctx) 4607 { 4608 #if defined(CONFIG_USER_ONLY) 4609 GEN_PRIV; 4610 #else 4611 CHK_SV; 4612 4613 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4614 #endif /* defined(CONFIG_USER_ONLY) */ 4615 } 4616 4617 /* slbsync */ 4618 static void gen_slbsync(DisasContext *ctx) 4619 { 4620 #if defined(CONFIG_USER_ONLY) 4621 GEN_PRIV; 4622 #else 4623 CHK_SV; 4624 gen_check_tlb_flush(ctx, true); 4625 #endif /* defined(CONFIG_USER_ONLY) */ 4626 } 4627 4628 #endif /* defined(TARGET_PPC64) */ 4629 4630 /*** External control ***/ 4631 /* Optional: */ 4632 4633 /* eciwx */ 4634 static void gen_eciwx(DisasContext *ctx) 4635 { 4636 TCGv t0; 4637 /* Should check EAR[E] ! */ 4638 gen_set_access_type(ctx, ACCESS_EXT); 4639 t0 = tcg_temp_new(); 4640 gen_addr_reg_index(ctx, t0); 4641 gen_check_align(ctx, t0, 0x03); 4642 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4643 tcg_temp_free(t0); 4644 } 4645 4646 /* ecowx */ 4647 static void gen_ecowx(DisasContext *ctx) 4648 { 4649 TCGv t0; 4650 /* Should check EAR[E] ! */ 4651 gen_set_access_type(ctx, ACCESS_EXT); 4652 t0 = tcg_temp_new(); 4653 gen_addr_reg_index(ctx, t0); 4654 gen_check_align(ctx, t0, 0x03); 4655 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4656 tcg_temp_free(t0); 4657 } 4658 4659 /* PowerPC 601 specific instructions */ 4660 4661 /* abs - abs. */ 4662 static void gen_abs(DisasContext *ctx) 4663 { 4664 TCGLabel *l1 = gen_new_label(); 4665 TCGLabel *l2 = gen_new_label(); 4666 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); 4667 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4668 tcg_gen_br(l2); 4669 gen_set_label(l1); 4670 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4671 gen_set_label(l2); 4672 if (unlikely(Rc(ctx->opcode) != 0)) 4673 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4674 } 4675 4676 /* abso - abso. */ 4677 static void gen_abso(DisasContext *ctx) 4678 { 4679 TCGLabel *l1 = gen_new_label(); 4680 TCGLabel *l2 = gen_new_label(); 4681 TCGLabel *l3 = gen_new_label(); 4682 /* Start with XER OV disabled, the most likely case */ 4683 tcg_gen_movi_tl(cpu_ov, 0); 4684 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); 4685 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); 4686 tcg_gen_movi_tl(cpu_ov, 1); 4687 tcg_gen_movi_tl(cpu_so, 1); 4688 tcg_gen_br(l2); 4689 gen_set_label(l1); 4690 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4691 tcg_gen_br(l3); 4692 gen_set_label(l2); 4693 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4694 gen_set_label(l3); 4695 if (unlikely(Rc(ctx->opcode) != 0)) 4696 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4697 } 4698 4699 /* clcs */ 4700 static void gen_clcs(DisasContext *ctx) 4701 { 4702 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 4703 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4704 tcg_temp_free_i32(t0); 4705 /* Rc=1 sets CR0 to an undefined state */ 4706 } 4707 4708 /* div - div. */ 4709 static void gen_div(DisasContext *ctx) 4710 { 4711 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4712 cpu_gpr[rB(ctx->opcode)]); 4713 if (unlikely(Rc(ctx->opcode) != 0)) 4714 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4715 } 4716 4717 /* divo - divo. */ 4718 static void gen_divo(DisasContext *ctx) 4719 { 4720 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4721 cpu_gpr[rB(ctx->opcode)]); 4722 if (unlikely(Rc(ctx->opcode) != 0)) 4723 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4724 } 4725 4726 /* divs - divs. */ 4727 static void gen_divs(DisasContext *ctx) 4728 { 4729 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4730 cpu_gpr[rB(ctx->opcode)]); 4731 if (unlikely(Rc(ctx->opcode) != 0)) 4732 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4733 } 4734 4735 /* divso - divso. */ 4736 static void gen_divso(DisasContext *ctx) 4737 { 4738 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 4739 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4740 if (unlikely(Rc(ctx->opcode) != 0)) 4741 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4742 } 4743 4744 /* doz - doz. */ 4745 static void gen_doz(DisasContext *ctx) 4746 { 4747 TCGLabel *l1 = gen_new_label(); 4748 TCGLabel *l2 = gen_new_label(); 4749 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4750 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4751 tcg_gen_br(l2); 4752 gen_set_label(l1); 4753 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4754 gen_set_label(l2); 4755 if (unlikely(Rc(ctx->opcode) != 0)) 4756 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4757 } 4758 4759 /* dozo - dozo. */ 4760 static void gen_dozo(DisasContext *ctx) 4761 { 4762 TCGLabel *l1 = gen_new_label(); 4763 TCGLabel *l2 = gen_new_label(); 4764 TCGv t0 = tcg_temp_new(); 4765 TCGv t1 = tcg_temp_new(); 4766 TCGv t2 = tcg_temp_new(); 4767 /* Start with XER OV disabled, the most likely case */ 4768 tcg_gen_movi_tl(cpu_ov, 0); 4769 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4770 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4771 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4772 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 4773 tcg_gen_andc_tl(t1, t1, t2); 4774 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 4775 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 4776 tcg_gen_movi_tl(cpu_ov, 1); 4777 tcg_gen_movi_tl(cpu_so, 1); 4778 tcg_gen_br(l2); 4779 gen_set_label(l1); 4780 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4781 gen_set_label(l2); 4782 tcg_temp_free(t0); 4783 tcg_temp_free(t1); 4784 tcg_temp_free(t2); 4785 if (unlikely(Rc(ctx->opcode) != 0)) 4786 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4787 } 4788 4789 /* dozi */ 4790 static void gen_dozi(DisasContext *ctx) 4791 { 4792 target_long simm = SIMM(ctx->opcode); 4793 TCGLabel *l1 = gen_new_label(); 4794 TCGLabel *l2 = gen_new_label(); 4795 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 4796 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 4797 tcg_gen_br(l2); 4798 gen_set_label(l1); 4799 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4800 gen_set_label(l2); 4801 if (unlikely(Rc(ctx->opcode) != 0)) 4802 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4803 } 4804 4805 /* lscbx - lscbx. */ 4806 static void gen_lscbx(DisasContext *ctx) 4807 { 4808 TCGv t0 = tcg_temp_new(); 4809 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 4810 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 4811 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 4812 4813 gen_addr_reg_index(ctx, t0); 4814 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 4815 tcg_temp_free_i32(t1); 4816 tcg_temp_free_i32(t2); 4817 tcg_temp_free_i32(t3); 4818 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 4819 tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 4820 if (unlikely(Rc(ctx->opcode) != 0)) 4821 gen_set_Rc0(ctx, t0); 4822 tcg_temp_free(t0); 4823 } 4824 4825 /* maskg - maskg. */ 4826 static void gen_maskg(DisasContext *ctx) 4827 { 4828 TCGLabel *l1 = gen_new_label(); 4829 TCGv t0 = tcg_temp_new(); 4830 TCGv t1 = tcg_temp_new(); 4831 TCGv t2 = tcg_temp_new(); 4832 TCGv t3 = tcg_temp_new(); 4833 tcg_gen_movi_tl(t3, 0xFFFFFFFF); 4834 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4835 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 4836 tcg_gen_addi_tl(t2, t0, 1); 4837 tcg_gen_shr_tl(t2, t3, t2); 4838 tcg_gen_shr_tl(t3, t3, t1); 4839 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 4840 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 4841 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4842 gen_set_label(l1); 4843 tcg_temp_free(t0); 4844 tcg_temp_free(t1); 4845 tcg_temp_free(t2); 4846 tcg_temp_free(t3); 4847 if (unlikely(Rc(ctx->opcode) != 0)) 4848 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4849 } 4850 4851 /* maskir - maskir. */ 4852 static void gen_maskir(DisasContext *ctx) 4853 { 4854 TCGv t0 = tcg_temp_new(); 4855 TCGv t1 = tcg_temp_new(); 4856 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4857 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4858 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4859 tcg_temp_free(t0); 4860 tcg_temp_free(t1); 4861 if (unlikely(Rc(ctx->opcode) != 0)) 4862 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4863 } 4864 4865 /* mul - mul. */ 4866 static void gen_mul(DisasContext *ctx) 4867 { 4868 TCGv_i64 t0 = tcg_temp_new_i64(); 4869 TCGv_i64 t1 = tcg_temp_new_i64(); 4870 TCGv t2 = tcg_temp_new(); 4871 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4872 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4873 tcg_gen_mul_i64(t0, t0, t1); 4874 tcg_gen_trunc_i64_tl(t2, t0); 4875 gen_store_spr(SPR_MQ, t2); 4876 tcg_gen_shri_i64(t1, t0, 32); 4877 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4878 tcg_temp_free_i64(t0); 4879 tcg_temp_free_i64(t1); 4880 tcg_temp_free(t2); 4881 if (unlikely(Rc(ctx->opcode) != 0)) 4882 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4883 } 4884 4885 /* mulo - mulo. */ 4886 static void gen_mulo(DisasContext *ctx) 4887 { 4888 TCGLabel *l1 = gen_new_label(); 4889 TCGv_i64 t0 = tcg_temp_new_i64(); 4890 TCGv_i64 t1 = tcg_temp_new_i64(); 4891 TCGv t2 = tcg_temp_new(); 4892 /* Start with XER OV disabled, the most likely case */ 4893 tcg_gen_movi_tl(cpu_ov, 0); 4894 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4895 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4896 tcg_gen_mul_i64(t0, t0, t1); 4897 tcg_gen_trunc_i64_tl(t2, t0); 4898 gen_store_spr(SPR_MQ, t2); 4899 tcg_gen_shri_i64(t1, t0, 32); 4900 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4901 tcg_gen_ext32s_i64(t1, t0); 4902 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 4903 tcg_gen_movi_tl(cpu_ov, 1); 4904 tcg_gen_movi_tl(cpu_so, 1); 4905 gen_set_label(l1); 4906 tcg_temp_free_i64(t0); 4907 tcg_temp_free_i64(t1); 4908 tcg_temp_free(t2); 4909 if (unlikely(Rc(ctx->opcode) != 0)) 4910 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4911 } 4912 4913 /* nabs - nabs. */ 4914 static void gen_nabs(DisasContext *ctx) 4915 { 4916 TCGLabel *l1 = gen_new_label(); 4917 TCGLabel *l2 = gen_new_label(); 4918 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4919 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4920 tcg_gen_br(l2); 4921 gen_set_label(l1); 4922 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4923 gen_set_label(l2); 4924 if (unlikely(Rc(ctx->opcode) != 0)) 4925 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4926 } 4927 4928 /* nabso - nabso. */ 4929 static void gen_nabso(DisasContext *ctx) 4930 { 4931 TCGLabel *l1 = gen_new_label(); 4932 TCGLabel *l2 = gen_new_label(); 4933 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4934 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4935 tcg_gen_br(l2); 4936 gen_set_label(l1); 4937 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4938 gen_set_label(l2); 4939 /* nabs never overflows */ 4940 tcg_gen_movi_tl(cpu_ov, 0); 4941 if (unlikely(Rc(ctx->opcode) != 0)) 4942 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4943 } 4944 4945 /* rlmi - rlmi. */ 4946 static void gen_rlmi(DisasContext *ctx) 4947 { 4948 uint32_t mb = MB(ctx->opcode); 4949 uint32_t me = ME(ctx->opcode); 4950 TCGv t0 = tcg_temp_new(); 4951 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4952 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4953 tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 4954 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); 4955 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 4956 tcg_temp_free(t0); 4957 if (unlikely(Rc(ctx->opcode) != 0)) 4958 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4959 } 4960 4961 /* rrib - rrib. */ 4962 static void gen_rrib(DisasContext *ctx) 4963 { 4964 TCGv t0 = tcg_temp_new(); 4965 TCGv t1 = tcg_temp_new(); 4966 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4967 tcg_gen_movi_tl(t1, 0x80000000); 4968 tcg_gen_shr_tl(t1, t1, t0); 4969 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4970 tcg_gen_and_tl(t0, t0, t1); 4971 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 4972 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4973 tcg_temp_free(t0); 4974 tcg_temp_free(t1); 4975 if (unlikely(Rc(ctx->opcode) != 0)) 4976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4977 } 4978 4979 /* sle - sle. */ 4980 static void gen_sle(DisasContext *ctx) 4981 { 4982 TCGv t0 = tcg_temp_new(); 4983 TCGv t1 = tcg_temp_new(); 4984 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 4985 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 4986 tcg_gen_subfi_tl(t1, 32, t1); 4987 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 4988 tcg_gen_or_tl(t1, t0, t1); 4989 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4990 gen_store_spr(SPR_MQ, t1); 4991 tcg_temp_free(t0); 4992 tcg_temp_free(t1); 4993 if (unlikely(Rc(ctx->opcode) != 0)) 4994 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4995 } 4996 4997 /* sleq - sleq. */ 4998 static void gen_sleq(DisasContext *ctx) 4999 { 5000 TCGv t0 = tcg_temp_new(); 5001 TCGv t1 = tcg_temp_new(); 5002 TCGv t2 = tcg_temp_new(); 5003 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5004 tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5005 tcg_gen_shl_tl(t2, t2, t0); 5006 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5007 gen_load_spr(t1, SPR_MQ); 5008 gen_store_spr(SPR_MQ, t0); 5009 tcg_gen_and_tl(t0, t0, t2); 5010 tcg_gen_andc_tl(t1, t1, t2); 5011 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5012 tcg_temp_free(t0); 5013 tcg_temp_free(t1); 5014 tcg_temp_free(t2); 5015 if (unlikely(Rc(ctx->opcode) != 0)) 5016 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5017 } 5018 5019 /* sliq - sliq. */ 5020 static void gen_sliq(DisasContext *ctx) 5021 { 5022 int sh = SH(ctx->opcode); 5023 TCGv t0 = tcg_temp_new(); 5024 TCGv t1 = tcg_temp_new(); 5025 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5026 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5027 tcg_gen_or_tl(t1, t0, t1); 5028 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5029 gen_store_spr(SPR_MQ, t1); 5030 tcg_temp_free(t0); 5031 tcg_temp_free(t1); 5032 if (unlikely(Rc(ctx->opcode) != 0)) 5033 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5034 } 5035 5036 /* slliq - slliq. */ 5037 static void gen_slliq(DisasContext *ctx) 5038 { 5039 int sh = SH(ctx->opcode); 5040 TCGv t0 = tcg_temp_new(); 5041 TCGv t1 = tcg_temp_new(); 5042 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5043 gen_load_spr(t1, SPR_MQ); 5044 gen_store_spr(SPR_MQ, t0); 5045 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5046 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5047 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5048 tcg_temp_free(t0); 5049 tcg_temp_free(t1); 5050 if (unlikely(Rc(ctx->opcode) != 0)) 5051 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5052 } 5053 5054 /* sllq - sllq. */ 5055 static void gen_sllq(DisasContext *ctx) 5056 { 5057 TCGLabel *l1 = gen_new_label(); 5058 TCGLabel *l2 = gen_new_label(); 5059 TCGv t0 = tcg_temp_local_new(); 5060 TCGv t1 = tcg_temp_local_new(); 5061 TCGv t2 = tcg_temp_local_new(); 5062 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5063 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5064 tcg_gen_shl_tl(t1, t1, t2); 5065 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5066 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5067 gen_load_spr(t0, SPR_MQ); 5068 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5069 tcg_gen_br(l2); 5070 gen_set_label(l1); 5071 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5072 gen_load_spr(t2, SPR_MQ); 5073 tcg_gen_andc_tl(t1, t2, t1); 5074 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5075 gen_set_label(l2); 5076 tcg_temp_free(t0); 5077 tcg_temp_free(t1); 5078 tcg_temp_free(t2); 5079 if (unlikely(Rc(ctx->opcode) != 0)) 5080 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5081 } 5082 5083 /* slq - slq. */ 5084 static void gen_slq(DisasContext *ctx) 5085 { 5086 TCGLabel *l1 = gen_new_label(); 5087 TCGv t0 = tcg_temp_new(); 5088 TCGv t1 = tcg_temp_new(); 5089 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5090 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5091 tcg_gen_subfi_tl(t1, 32, t1); 5092 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5093 tcg_gen_or_tl(t1, t0, t1); 5094 gen_store_spr(SPR_MQ, t1); 5095 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5096 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5097 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5098 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5099 gen_set_label(l1); 5100 tcg_temp_free(t0); 5101 tcg_temp_free(t1); 5102 if (unlikely(Rc(ctx->opcode) != 0)) 5103 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5104 } 5105 5106 /* sraiq - sraiq. */ 5107 static void gen_sraiq(DisasContext *ctx) 5108 { 5109 int sh = SH(ctx->opcode); 5110 TCGLabel *l1 = gen_new_label(); 5111 TCGv t0 = tcg_temp_new(); 5112 TCGv t1 = tcg_temp_new(); 5113 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5114 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5115 tcg_gen_or_tl(t0, t0, t1); 5116 gen_store_spr(SPR_MQ, t0); 5117 tcg_gen_movi_tl(cpu_ca, 0); 5118 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5119 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5120 tcg_gen_movi_tl(cpu_ca, 1); 5121 gen_set_label(l1); 5122 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5123 tcg_temp_free(t0); 5124 tcg_temp_free(t1); 5125 if (unlikely(Rc(ctx->opcode) != 0)) 5126 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5127 } 5128 5129 /* sraq - sraq. */ 5130 static void gen_sraq(DisasContext *ctx) 5131 { 5132 TCGLabel *l1 = gen_new_label(); 5133 TCGLabel *l2 = gen_new_label(); 5134 TCGv t0 = tcg_temp_new(); 5135 TCGv t1 = tcg_temp_local_new(); 5136 TCGv t2 = tcg_temp_local_new(); 5137 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5138 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5139 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5140 tcg_gen_subfi_tl(t2, 32, t2); 5141 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5142 tcg_gen_or_tl(t0, t0, t2); 5143 gen_store_spr(SPR_MQ, t0); 5144 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5145 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5146 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5147 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5148 gen_set_label(l1); 5149 tcg_temp_free(t0); 5150 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5151 tcg_gen_movi_tl(cpu_ca, 0); 5152 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5153 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5154 tcg_gen_movi_tl(cpu_ca, 1); 5155 gen_set_label(l2); 5156 tcg_temp_free(t1); 5157 tcg_temp_free(t2); 5158 if (unlikely(Rc(ctx->opcode) != 0)) 5159 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5160 } 5161 5162 /* sre - sre. */ 5163 static void gen_sre(DisasContext *ctx) 5164 { 5165 TCGv t0 = tcg_temp_new(); 5166 TCGv t1 = tcg_temp_new(); 5167 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5168 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5169 tcg_gen_subfi_tl(t1, 32, t1); 5170 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5171 tcg_gen_or_tl(t1, t0, t1); 5172 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5173 gen_store_spr(SPR_MQ, t1); 5174 tcg_temp_free(t0); 5175 tcg_temp_free(t1); 5176 if (unlikely(Rc(ctx->opcode) != 0)) 5177 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5178 } 5179 5180 /* srea - srea. */ 5181 static void gen_srea(DisasContext *ctx) 5182 { 5183 TCGv t0 = tcg_temp_new(); 5184 TCGv t1 = tcg_temp_new(); 5185 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5186 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5187 gen_store_spr(SPR_MQ, t0); 5188 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5189 tcg_temp_free(t0); 5190 tcg_temp_free(t1); 5191 if (unlikely(Rc(ctx->opcode) != 0)) 5192 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5193 } 5194 5195 /* sreq */ 5196 static void gen_sreq(DisasContext *ctx) 5197 { 5198 TCGv t0 = tcg_temp_new(); 5199 TCGv t1 = tcg_temp_new(); 5200 TCGv t2 = tcg_temp_new(); 5201 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5202 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5203 tcg_gen_shr_tl(t1, t1, t0); 5204 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5205 gen_load_spr(t2, SPR_MQ); 5206 gen_store_spr(SPR_MQ, t0); 5207 tcg_gen_and_tl(t0, t0, t1); 5208 tcg_gen_andc_tl(t2, t2, t1); 5209 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5210 tcg_temp_free(t0); 5211 tcg_temp_free(t1); 5212 tcg_temp_free(t2); 5213 if (unlikely(Rc(ctx->opcode) != 0)) 5214 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5215 } 5216 5217 /* sriq */ 5218 static void gen_sriq(DisasContext *ctx) 5219 { 5220 int sh = SH(ctx->opcode); 5221 TCGv t0 = tcg_temp_new(); 5222 TCGv t1 = tcg_temp_new(); 5223 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5224 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5225 tcg_gen_or_tl(t1, t0, t1); 5226 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5227 gen_store_spr(SPR_MQ, t1); 5228 tcg_temp_free(t0); 5229 tcg_temp_free(t1); 5230 if (unlikely(Rc(ctx->opcode) != 0)) 5231 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5232 } 5233 5234 /* srliq */ 5235 static void gen_srliq(DisasContext *ctx) 5236 { 5237 int sh = SH(ctx->opcode); 5238 TCGv t0 = tcg_temp_new(); 5239 TCGv t1 = tcg_temp_new(); 5240 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5241 gen_load_spr(t1, SPR_MQ); 5242 gen_store_spr(SPR_MQ, t0); 5243 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5244 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5245 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5246 tcg_temp_free(t0); 5247 tcg_temp_free(t1); 5248 if (unlikely(Rc(ctx->opcode) != 0)) 5249 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5250 } 5251 5252 /* srlq */ 5253 static void gen_srlq(DisasContext *ctx) 5254 { 5255 TCGLabel *l1 = gen_new_label(); 5256 TCGLabel *l2 = gen_new_label(); 5257 TCGv t0 = tcg_temp_local_new(); 5258 TCGv t1 = tcg_temp_local_new(); 5259 TCGv t2 = tcg_temp_local_new(); 5260 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5261 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5262 tcg_gen_shr_tl(t2, t1, t2); 5263 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5264 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5265 gen_load_spr(t0, SPR_MQ); 5266 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5267 tcg_gen_br(l2); 5268 gen_set_label(l1); 5269 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5270 tcg_gen_and_tl(t0, t0, t2); 5271 gen_load_spr(t1, SPR_MQ); 5272 tcg_gen_andc_tl(t1, t1, t2); 5273 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5274 gen_set_label(l2); 5275 tcg_temp_free(t0); 5276 tcg_temp_free(t1); 5277 tcg_temp_free(t2); 5278 if (unlikely(Rc(ctx->opcode) != 0)) 5279 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5280 } 5281 5282 /* srq */ 5283 static void gen_srq(DisasContext *ctx) 5284 { 5285 TCGLabel *l1 = gen_new_label(); 5286 TCGv t0 = tcg_temp_new(); 5287 TCGv t1 = tcg_temp_new(); 5288 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5289 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5290 tcg_gen_subfi_tl(t1, 32, t1); 5291 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5292 tcg_gen_or_tl(t1, t0, t1); 5293 gen_store_spr(SPR_MQ, t1); 5294 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5295 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5296 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5297 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5298 gen_set_label(l1); 5299 tcg_temp_free(t0); 5300 tcg_temp_free(t1); 5301 if (unlikely(Rc(ctx->opcode) != 0)) 5302 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5303 } 5304 5305 /* PowerPC 602 specific instructions */ 5306 5307 /* dsa */ 5308 static void gen_dsa(DisasContext *ctx) 5309 { 5310 /* XXX: TODO */ 5311 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5312 } 5313 5314 /* esa */ 5315 static void gen_esa(DisasContext *ctx) 5316 { 5317 /* XXX: TODO */ 5318 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5319 } 5320 5321 /* mfrom */ 5322 static void gen_mfrom(DisasContext *ctx) 5323 { 5324 #if defined(CONFIG_USER_ONLY) 5325 GEN_PRIV; 5326 #else 5327 CHK_SV; 5328 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5329 #endif /* defined(CONFIG_USER_ONLY) */ 5330 } 5331 5332 /* 602 - 603 - G2 TLB management */ 5333 5334 /* tlbld */ 5335 static void gen_tlbld_6xx(DisasContext *ctx) 5336 { 5337 #if defined(CONFIG_USER_ONLY) 5338 GEN_PRIV; 5339 #else 5340 CHK_SV; 5341 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5342 #endif /* defined(CONFIG_USER_ONLY) */ 5343 } 5344 5345 /* tlbli */ 5346 static void gen_tlbli_6xx(DisasContext *ctx) 5347 { 5348 #if defined(CONFIG_USER_ONLY) 5349 GEN_PRIV; 5350 #else 5351 CHK_SV; 5352 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5353 #endif /* defined(CONFIG_USER_ONLY) */ 5354 } 5355 5356 /* 74xx TLB management */ 5357 5358 /* tlbld */ 5359 static void gen_tlbld_74xx(DisasContext *ctx) 5360 { 5361 #if defined(CONFIG_USER_ONLY) 5362 GEN_PRIV; 5363 #else 5364 CHK_SV; 5365 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5366 #endif /* defined(CONFIG_USER_ONLY) */ 5367 } 5368 5369 /* tlbli */ 5370 static void gen_tlbli_74xx(DisasContext *ctx) 5371 { 5372 #if defined(CONFIG_USER_ONLY) 5373 GEN_PRIV; 5374 #else 5375 CHK_SV; 5376 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5377 #endif /* defined(CONFIG_USER_ONLY) */ 5378 } 5379 5380 /* POWER instructions not in PowerPC 601 */ 5381 5382 /* clf */ 5383 static void gen_clf(DisasContext *ctx) 5384 { 5385 /* Cache line flush: implemented as no-op */ 5386 } 5387 5388 /* cli */ 5389 static void gen_cli(DisasContext *ctx) 5390 { 5391 #if defined(CONFIG_USER_ONLY) 5392 GEN_PRIV; 5393 #else 5394 /* Cache line invalidate: privileged and treated as no-op */ 5395 CHK_SV; 5396 #endif /* defined(CONFIG_USER_ONLY) */ 5397 } 5398 5399 /* dclst */ 5400 static void gen_dclst(DisasContext *ctx) 5401 { 5402 /* Data cache line store: treated as no-op */ 5403 } 5404 5405 static void gen_mfsri(DisasContext *ctx) 5406 { 5407 #if defined(CONFIG_USER_ONLY) 5408 GEN_PRIV; 5409 #else 5410 int ra = rA(ctx->opcode); 5411 int rd = rD(ctx->opcode); 5412 TCGv t0; 5413 5414 CHK_SV; 5415 t0 = tcg_temp_new(); 5416 gen_addr_reg_index(ctx, t0); 5417 tcg_gen_extract_tl(t0, t0, 28, 4); 5418 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5419 tcg_temp_free(t0); 5420 if (ra != 0 && ra != rd) 5421 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5422 #endif /* defined(CONFIG_USER_ONLY) */ 5423 } 5424 5425 static void gen_rac(DisasContext *ctx) 5426 { 5427 #if defined(CONFIG_USER_ONLY) 5428 GEN_PRIV; 5429 #else 5430 TCGv t0; 5431 5432 CHK_SV; 5433 t0 = tcg_temp_new(); 5434 gen_addr_reg_index(ctx, t0); 5435 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5436 tcg_temp_free(t0); 5437 #endif /* defined(CONFIG_USER_ONLY) */ 5438 } 5439 5440 static void gen_rfsvc(DisasContext *ctx) 5441 { 5442 #if defined(CONFIG_USER_ONLY) 5443 GEN_PRIV; 5444 #else 5445 CHK_SV; 5446 5447 gen_helper_rfsvc(cpu_env); 5448 gen_sync_exception(ctx); 5449 #endif /* defined(CONFIG_USER_ONLY) */ 5450 } 5451 5452 /* svc is not implemented for now */ 5453 5454 /* BookE specific instructions */ 5455 5456 /* XXX: not implemented on 440 ? */ 5457 static void gen_mfapidi(DisasContext *ctx) 5458 { 5459 /* XXX: TODO */ 5460 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5461 } 5462 5463 /* XXX: not implemented on 440 ? */ 5464 static void gen_tlbiva(DisasContext *ctx) 5465 { 5466 #if defined(CONFIG_USER_ONLY) 5467 GEN_PRIV; 5468 #else 5469 TCGv t0; 5470 5471 CHK_SV; 5472 t0 = tcg_temp_new(); 5473 gen_addr_reg_index(ctx, t0); 5474 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5475 tcg_temp_free(t0); 5476 #endif /* defined(CONFIG_USER_ONLY) */ 5477 } 5478 5479 /* All 405 MAC instructions are translated here */ 5480 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5481 int ra, int rb, int rt, int Rc) 5482 { 5483 TCGv t0, t1; 5484 5485 t0 = tcg_temp_local_new(); 5486 t1 = tcg_temp_local_new(); 5487 5488 switch (opc3 & 0x0D) { 5489 case 0x05: 5490 /* macchw - macchw. - macchwo - macchwo. */ 5491 /* macchws - macchws. - macchwso - macchwso. */ 5492 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5493 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5494 /* mulchw - mulchw. */ 5495 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5496 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5497 tcg_gen_ext16s_tl(t1, t1); 5498 break; 5499 case 0x04: 5500 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5501 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5502 /* mulchwu - mulchwu. */ 5503 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5504 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5505 tcg_gen_ext16u_tl(t1, t1); 5506 break; 5507 case 0x01: 5508 /* machhw - machhw. - machhwo - machhwo. */ 5509 /* machhws - machhws. - machhwso - machhwso. */ 5510 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5511 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5512 /* mulhhw - mulhhw. */ 5513 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5514 tcg_gen_ext16s_tl(t0, t0); 5515 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5516 tcg_gen_ext16s_tl(t1, t1); 5517 break; 5518 case 0x00: 5519 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5520 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5521 /* mulhhwu - mulhhwu. */ 5522 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5523 tcg_gen_ext16u_tl(t0, t0); 5524 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5525 tcg_gen_ext16u_tl(t1, t1); 5526 break; 5527 case 0x0D: 5528 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5529 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5530 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5531 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5532 /* mullhw - mullhw. */ 5533 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5534 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5535 break; 5536 case 0x0C: 5537 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5538 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5539 /* mullhwu - mullhwu. */ 5540 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5541 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5542 break; 5543 } 5544 if (opc2 & 0x04) { 5545 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5546 tcg_gen_mul_tl(t1, t0, t1); 5547 if (opc2 & 0x02) { 5548 /* nmultiply-and-accumulate (0x0E) */ 5549 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5550 } else { 5551 /* multiply-and-accumulate (0x0C) */ 5552 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5553 } 5554 5555 if (opc3 & 0x12) { 5556 /* Check overflow and/or saturate */ 5557 TCGLabel *l1 = gen_new_label(); 5558 5559 if (opc3 & 0x10) { 5560 /* Start with XER OV disabled, the most likely case */ 5561 tcg_gen_movi_tl(cpu_ov, 0); 5562 } 5563 if (opc3 & 0x01) { 5564 /* Signed */ 5565 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5566 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5567 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5568 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5569 if (opc3 & 0x02) { 5570 /* Saturate */ 5571 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5572 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5573 } 5574 } else { 5575 /* Unsigned */ 5576 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5577 if (opc3 & 0x02) { 5578 /* Saturate */ 5579 tcg_gen_movi_tl(t0, UINT32_MAX); 5580 } 5581 } 5582 if (opc3 & 0x10) { 5583 /* Check overflow */ 5584 tcg_gen_movi_tl(cpu_ov, 1); 5585 tcg_gen_movi_tl(cpu_so, 1); 5586 } 5587 gen_set_label(l1); 5588 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5589 } 5590 } else { 5591 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5592 } 5593 tcg_temp_free(t0); 5594 tcg_temp_free(t1); 5595 if (unlikely(Rc) != 0) { 5596 /* Update Rc0 */ 5597 gen_set_Rc0(ctx, cpu_gpr[rt]); 5598 } 5599 } 5600 5601 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5602 static void glue(gen_, name)(DisasContext *ctx) \ 5603 { \ 5604 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5605 rD(ctx->opcode), Rc(ctx->opcode)); \ 5606 } 5607 5608 /* macchw - macchw. */ 5609 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5610 /* macchwo - macchwo. */ 5611 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5612 /* macchws - macchws. */ 5613 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5614 /* macchwso - macchwso. */ 5615 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5616 /* macchwsu - macchwsu. */ 5617 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5618 /* macchwsuo - macchwsuo. */ 5619 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5620 /* macchwu - macchwu. */ 5621 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5622 /* macchwuo - macchwuo. */ 5623 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5624 /* machhw - machhw. */ 5625 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5626 /* machhwo - machhwo. */ 5627 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5628 /* machhws - machhws. */ 5629 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5630 /* machhwso - machhwso. */ 5631 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5632 /* machhwsu - machhwsu. */ 5633 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5634 /* machhwsuo - machhwsuo. */ 5635 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5636 /* machhwu - machhwu. */ 5637 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5638 /* machhwuo - machhwuo. */ 5639 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5640 /* maclhw - maclhw. */ 5641 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5642 /* maclhwo - maclhwo. */ 5643 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5644 /* maclhws - maclhws. */ 5645 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5646 /* maclhwso - maclhwso. */ 5647 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5648 /* maclhwu - maclhwu. */ 5649 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5650 /* maclhwuo - maclhwuo. */ 5651 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5652 /* maclhwsu - maclhwsu. */ 5653 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5654 /* maclhwsuo - maclhwsuo. */ 5655 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5656 /* nmacchw - nmacchw. */ 5657 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5658 /* nmacchwo - nmacchwo. */ 5659 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5660 /* nmacchws - nmacchws. */ 5661 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5662 /* nmacchwso - nmacchwso. */ 5663 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5664 /* nmachhw - nmachhw. */ 5665 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5666 /* nmachhwo - nmachhwo. */ 5667 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5668 /* nmachhws - nmachhws. */ 5669 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5670 /* nmachhwso - nmachhwso. */ 5671 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5672 /* nmaclhw - nmaclhw. */ 5673 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5674 /* nmaclhwo - nmaclhwo. */ 5675 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5676 /* nmaclhws - nmaclhws. */ 5677 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5678 /* nmaclhwso - nmaclhwso. */ 5679 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5680 5681 /* mulchw - mulchw. */ 5682 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5683 /* mulchwu - mulchwu. */ 5684 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5685 /* mulhhw - mulhhw. */ 5686 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5687 /* mulhhwu - mulhhwu. */ 5688 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5689 /* mullhw - mullhw. */ 5690 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5691 /* mullhwu - mullhwu. */ 5692 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5693 5694 /* mfdcr */ 5695 static void gen_mfdcr(DisasContext *ctx) 5696 { 5697 #if defined(CONFIG_USER_ONLY) 5698 GEN_PRIV; 5699 #else 5700 TCGv dcrn; 5701 5702 CHK_SV; 5703 dcrn = tcg_const_tl(SPR(ctx->opcode)); 5704 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5705 tcg_temp_free(dcrn); 5706 #endif /* defined(CONFIG_USER_ONLY) */ 5707 } 5708 5709 /* mtdcr */ 5710 static void gen_mtdcr(DisasContext *ctx) 5711 { 5712 #if defined(CONFIG_USER_ONLY) 5713 GEN_PRIV; 5714 #else 5715 TCGv dcrn; 5716 5717 CHK_SV; 5718 dcrn = tcg_const_tl(SPR(ctx->opcode)); 5719 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5720 tcg_temp_free(dcrn); 5721 #endif /* defined(CONFIG_USER_ONLY) */ 5722 } 5723 5724 /* mfdcrx */ 5725 /* XXX: not implemented on 440 ? */ 5726 static void gen_mfdcrx(DisasContext *ctx) 5727 { 5728 #if defined(CONFIG_USER_ONLY) 5729 GEN_PRIV; 5730 #else 5731 CHK_SV; 5732 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5733 cpu_gpr[rA(ctx->opcode)]); 5734 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5735 #endif /* defined(CONFIG_USER_ONLY) */ 5736 } 5737 5738 /* mtdcrx */ 5739 /* XXX: not implemented on 440 ? */ 5740 static void gen_mtdcrx(DisasContext *ctx) 5741 { 5742 #if defined(CONFIG_USER_ONLY) 5743 GEN_PRIV; 5744 #else 5745 CHK_SV; 5746 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5747 cpu_gpr[rS(ctx->opcode)]); 5748 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5749 #endif /* defined(CONFIG_USER_ONLY) */ 5750 } 5751 5752 /* mfdcrux (PPC 460) : user-mode access to DCR */ 5753 static void gen_mfdcrux(DisasContext *ctx) 5754 { 5755 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5756 cpu_gpr[rA(ctx->opcode)]); 5757 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5758 } 5759 5760 /* mtdcrux (PPC 460) : user-mode access to DCR */ 5761 static void gen_mtdcrux(DisasContext *ctx) 5762 { 5763 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5764 cpu_gpr[rS(ctx->opcode)]); 5765 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5766 } 5767 5768 /* dccci */ 5769 static void gen_dccci(DisasContext *ctx) 5770 { 5771 CHK_SV; 5772 /* interpreted as no-op */ 5773 } 5774 5775 /* dcread */ 5776 static void gen_dcread(DisasContext *ctx) 5777 { 5778 #if defined(CONFIG_USER_ONLY) 5779 GEN_PRIV; 5780 #else 5781 TCGv EA, val; 5782 5783 CHK_SV; 5784 gen_set_access_type(ctx, ACCESS_CACHE); 5785 EA = tcg_temp_new(); 5786 gen_addr_reg_index(ctx, EA); 5787 val = tcg_temp_new(); 5788 gen_qemu_ld32u(ctx, val, EA); 5789 tcg_temp_free(val); 5790 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5791 tcg_temp_free(EA); 5792 #endif /* defined(CONFIG_USER_ONLY) */ 5793 } 5794 5795 /* icbt */ 5796 static void gen_icbt_40x(DisasContext *ctx) 5797 { 5798 /* interpreted as no-op */ 5799 /* XXX: specification say this is treated as a load by the MMU 5800 * but does not generate any exception 5801 */ 5802 } 5803 5804 /* iccci */ 5805 static void gen_iccci(DisasContext *ctx) 5806 { 5807 CHK_SV; 5808 /* interpreted as no-op */ 5809 } 5810 5811 /* icread */ 5812 static void gen_icread(DisasContext *ctx) 5813 { 5814 CHK_SV; 5815 /* interpreted as no-op */ 5816 } 5817 5818 /* rfci (supervisor only) */ 5819 static void gen_rfci_40x(DisasContext *ctx) 5820 { 5821 #if defined(CONFIG_USER_ONLY) 5822 GEN_PRIV; 5823 #else 5824 CHK_SV; 5825 /* Restore CPU state */ 5826 gen_helper_40x_rfci(cpu_env); 5827 gen_sync_exception(ctx); 5828 #endif /* defined(CONFIG_USER_ONLY) */ 5829 } 5830 5831 static void gen_rfci(DisasContext *ctx) 5832 { 5833 #if defined(CONFIG_USER_ONLY) 5834 GEN_PRIV; 5835 #else 5836 CHK_SV; 5837 /* Restore CPU state */ 5838 gen_helper_rfci(cpu_env); 5839 gen_sync_exception(ctx); 5840 #endif /* defined(CONFIG_USER_ONLY) */ 5841 } 5842 5843 /* BookE specific */ 5844 5845 /* XXX: not implemented on 440 ? */ 5846 static void gen_rfdi(DisasContext *ctx) 5847 { 5848 #if defined(CONFIG_USER_ONLY) 5849 GEN_PRIV; 5850 #else 5851 CHK_SV; 5852 /* Restore CPU state */ 5853 gen_helper_rfdi(cpu_env); 5854 gen_sync_exception(ctx); 5855 #endif /* defined(CONFIG_USER_ONLY) */ 5856 } 5857 5858 /* XXX: not implemented on 440 ? */ 5859 static void gen_rfmci(DisasContext *ctx) 5860 { 5861 #if defined(CONFIG_USER_ONLY) 5862 GEN_PRIV; 5863 #else 5864 CHK_SV; 5865 /* Restore CPU state */ 5866 gen_helper_rfmci(cpu_env); 5867 gen_sync_exception(ctx); 5868 #endif /* defined(CONFIG_USER_ONLY) */ 5869 } 5870 5871 /* TLB management - PowerPC 405 implementation */ 5872 5873 /* tlbre */ 5874 static void gen_tlbre_40x(DisasContext *ctx) 5875 { 5876 #if defined(CONFIG_USER_ONLY) 5877 GEN_PRIV; 5878 #else 5879 CHK_SV; 5880 switch (rB(ctx->opcode)) { 5881 case 0: 5882 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5883 cpu_gpr[rA(ctx->opcode)]); 5884 break; 5885 case 1: 5886 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5887 cpu_gpr[rA(ctx->opcode)]); 5888 break; 5889 default: 5890 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5891 break; 5892 } 5893 #endif /* defined(CONFIG_USER_ONLY) */ 5894 } 5895 5896 /* tlbsx - tlbsx. */ 5897 static void gen_tlbsx_40x(DisasContext *ctx) 5898 { 5899 #if defined(CONFIG_USER_ONLY) 5900 GEN_PRIV; 5901 #else 5902 TCGv t0; 5903 5904 CHK_SV; 5905 t0 = tcg_temp_new(); 5906 gen_addr_reg_index(ctx, t0); 5907 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5908 tcg_temp_free(t0); 5909 if (Rc(ctx->opcode)) { 5910 TCGLabel *l1 = gen_new_label(); 5911 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5912 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5913 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5914 gen_set_label(l1); 5915 } 5916 #endif /* defined(CONFIG_USER_ONLY) */ 5917 } 5918 5919 /* tlbwe */ 5920 static void gen_tlbwe_40x(DisasContext *ctx) 5921 { 5922 #if defined(CONFIG_USER_ONLY) 5923 GEN_PRIV; 5924 #else 5925 CHK_SV; 5926 5927 switch (rB(ctx->opcode)) { 5928 case 0: 5929 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5930 cpu_gpr[rS(ctx->opcode)]); 5931 break; 5932 case 1: 5933 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5934 cpu_gpr[rS(ctx->opcode)]); 5935 break; 5936 default: 5937 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5938 break; 5939 } 5940 #endif /* defined(CONFIG_USER_ONLY) */ 5941 } 5942 5943 /* TLB management - PowerPC 440 implementation */ 5944 5945 /* tlbre */ 5946 static void gen_tlbre_440(DisasContext *ctx) 5947 { 5948 #if defined(CONFIG_USER_ONLY) 5949 GEN_PRIV; 5950 #else 5951 CHK_SV; 5952 5953 switch (rB(ctx->opcode)) { 5954 case 0: 5955 case 1: 5956 case 2: 5957 { 5958 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 5959 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5960 t0, cpu_gpr[rA(ctx->opcode)]); 5961 tcg_temp_free_i32(t0); 5962 } 5963 break; 5964 default: 5965 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5966 break; 5967 } 5968 #endif /* defined(CONFIG_USER_ONLY) */ 5969 } 5970 5971 /* tlbsx - tlbsx. */ 5972 static void gen_tlbsx_440(DisasContext *ctx) 5973 { 5974 #if defined(CONFIG_USER_ONLY) 5975 GEN_PRIV; 5976 #else 5977 TCGv t0; 5978 5979 CHK_SV; 5980 t0 = tcg_temp_new(); 5981 gen_addr_reg_index(ctx, t0); 5982 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5983 tcg_temp_free(t0); 5984 if (Rc(ctx->opcode)) { 5985 TCGLabel *l1 = gen_new_label(); 5986 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5987 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5988 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5989 gen_set_label(l1); 5990 } 5991 #endif /* defined(CONFIG_USER_ONLY) */ 5992 } 5993 5994 /* tlbwe */ 5995 static void gen_tlbwe_440(DisasContext *ctx) 5996 { 5997 #if defined(CONFIG_USER_ONLY) 5998 GEN_PRIV; 5999 #else 6000 CHK_SV; 6001 switch (rB(ctx->opcode)) { 6002 case 0: 6003 case 1: 6004 case 2: 6005 { 6006 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6007 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6008 cpu_gpr[rS(ctx->opcode)]); 6009 tcg_temp_free_i32(t0); 6010 } 6011 break; 6012 default: 6013 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6014 break; 6015 } 6016 #endif /* defined(CONFIG_USER_ONLY) */ 6017 } 6018 6019 /* TLB management - PowerPC BookE 2.06 implementation */ 6020 6021 /* tlbre */ 6022 static void gen_tlbre_booke206(DisasContext *ctx) 6023 { 6024 #if defined(CONFIG_USER_ONLY) 6025 GEN_PRIV; 6026 #else 6027 CHK_SV; 6028 gen_helper_booke206_tlbre(cpu_env); 6029 #endif /* defined(CONFIG_USER_ONLY) */ 6030 } 6031 6032 /* tlbsx - tlbsx. */ 6033 static void gen_tlbsx_booke206(DisasContext *ctx) 6034 { 6035 #if defined(CONFIG_USER_ONLY) 6036 GEN_PRIV; 6037 #else 6038 TCGv t0; 6039 6040 CHK_SV; 6041 if (rA(ctx->opcode)) { 6042 t0 = tcg_temp_new(); 6043 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6044 } else { 6045 t0 = tcg_const_tl(0); 6046 } 6047 6048 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6049 gen_helper_booke206_tlbsx(cpu_env, t0); 6050 tcg_temp_free(t0); 6051 #endif /* defined(CONFIG_USER_ONLY) */ 6052 } 6053 6054 /* tlbwe */ 6055 static void gen_tlbwe_booke206(DisasContext *ctx) 6056 { 6057 #if defined(CONFIG_USER_ONLY) 6058 GEN_PRIV; 6059 #else 6060 CHK_SV; 6061 gen_helper_booke206_tlbwe(cpu_env); 6062 #endif /* defined(CONFIG_USER_ONLY) */ 6063 } 6064 6065 static void gen_tlbivax_booke206(DisasContext *ctx) 6066 { 6067 #if defined(CONFIG_USER_ONLY) 6068 GEN_PRIV; 6069 #else 6070 TCGv t0; 6071 6072 CHK_SV; 6073 t0 = tcg_temp_new(); 6074 gen_addr_reg_index(ctx, t0); 6075 gen_helper_booke206_tlbivax(cpu_env, t0); 6076 tcg_temp_free(t0); 6077 #endif /* defined(CONFIG_USER_ONLY) */ 6078 } 6079 6080 static void gen_tlbilx_booke206(DisasContext *ctx) 6081 { 6082 #if defined(CONFIG_USER_ONLY) 6083 GEN_PRIV; 6084 #else 6085 TCGv t0; 6086 6087 CHK_SV; 6088 t0 = tcg_temp_new(); 6089 gen_addr_reg_index(ctx, t0); 6090 6091 switch((ctx->opcode >> 21) & 0x3) { 6092 case 0: 6093 gen_helper_booke206_tlbilx0(cpu_env, t0); 6094 break; 6095 case 1: 6096 gen_helper_booke206_tlbilx1(cpu_env, t0); 6097 break; 6098 case 3: 6099 gen_helper_booke206_tlbilx3(cpu_env, t0); 6100 break; 6101 default: 6102 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6103 break; 6104 } 6105 6106 tcg_temp_free(t0); 6107 #endif /* defined(CONFIG_USER_ONLY) */ 6108 } 6109 6110 6111 /* wrtee */ 6112 static void gen_wrtee(DisasContext *ctx) 6113 { 6114 #if defined(CONFIG_USER_ONLY) 6115 GEN_PRIV; 6116 #else 6117 TCGv t0; 6118 6119 CHK_SV; 6120 t0 = tcg_temp_new(); 6121 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6122 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6123 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6124 tcg_temp_free(t0); 6125 /* Stop translation to have a chance to raise an exception 6126 * if we just set msr_ee to 1 6127 */ 6128 gen_stop_exception(ctx); 6129 #endif /* defined(CONFIG_USER_ONLY) */ 6130 } 6131 6132 /* wrteei */ 6133 static void gen_wrteei(DisasContext *ctx) 6134 { 6135 #if defined(CONFIG_USER_ONLY) 6136 GEN_PRIV; 6137 #else 6138 CHK_SV; 6139 if (ctx->opcode & 0x00008000) { 6140 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6141 /* Stop translation to have a chance to raise an exception */ 6142 gen_stop_exception(ctx); 6143 } else { 6144 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6145 } 6146 #endif /* defined(CONFIG_USER_ONLY) */ 6147 } 6148 6149 /* PowerPC 440 specific instructions */ 6150 6151 /* dlmzb */ 6152 static void gen_dlmzb(DisasContext *ctx) 6153 { 6154 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6155 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6156 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6157 tcg_temp_free_i32(t0); 6158 } 6159 6160 /* mbar replaces eieio on 440 */ 6161 static void gen_mbar(DisasContext *ctx) 6162 { 6163 /* interpreted as no-op */ 6164 } 6165 6166 /* msync replaces sync on 440 */ 6167 static void gen_msync_4xx(DisasContext *ctx) 6168 { 6169 /* interpreted as no-op */ 6170 } 6171 6172 /* icbt */ 6173 static void gen_icbt_440(DisasContext *ctx) 6174 { 6175 /* interpreted as no-op */ 6176 /* XXX: specification say this is treated as a load by the MMU 6177 * but does not generate any exception 6178 */ 6179 } 6180 6181 /* Embedded.Processor Control */ 6182 6183 static void gen_msgclr(DisasContext *ctx) 6184 { 6185 #if defined(CONFIG_USER_ONLY) 6186 GEN_PRIV; 6187 #else 6188 CHK_SV; 6189 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6190 #endif /* defined(CONFIG_USER_ONLY) */ 6191 } 6192 6193 static void gen_msgsnd(DisasContext *ctx) 6194 { 6195 #if defined(CONFIG_USER_ONLY) 6196 GEN_PRIV; 6197 #else 6198 CHK_SV; 6199 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6200 #endif /* defined(CONFIG_USER_ONLY) */ 6201 } 6202 6203 6204 #if defined(TARGET_PPC64) 6205 static void gen_maddld(DisasContext *ctx) 6206 { 6207 TCGv_i64 t1 = tcg_temp_new_i64(); 6208 6209 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6210 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6211 tcg_temp_free_i64(t1); 6212 } 6213 6214 /* maddhd maddhdu */ 6215 static void gen_maddhd_maddhdu(DisasContext *ctx) 6216 { 6217 TCGv_i64 lo = tcg_temp_new_i64(); 6218 TCGv_i64 hi = tcg_temp_new_i64(); 6219 TCGv_i64 t1 = tcg_temp_new_i64(); 6220 6221 if (Rc(ctx->opcode)) { 6222 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6223 cpu_gpr[rB(ctx->opcode)]); 6224 tcg_gen_movi_i64(t1, 0); 6225 } else { 6226 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6227 cpu_gpr[rB(ctx->opcode)]); 6228 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6229 } 6230 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6231 cpu_gpr[rC(ctx->opcode)], t1); 6232 tcg_temp_free_i64(lo); 6233 tcg_temp_free_i64(hi); 6234 tcg_temp_free_i64(t1); 6235 } 6236 #endif /* defined(TARGET_PPC64) */ 6237 6238 static void gen_tbegin(DisasContext *ctx) 6239 { 6240 if (unlikely(!ctx->tm_enabled)) { 6241 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6242 return; 6243 } 6244 gen_helper_tbegin(cpu_env); 6245 } 6246 6247 #define GEN_TM_NOOP(name) \ 6248 static inline void gen_##name(DisasContext *ctx) \ 6249 { \ 6250 if (unlikely(!ctx->tm_enabled)) { \ 6251 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6252 return; \ 6253 } \ 6254 /* Because tbegin always fails in QEMU, these user \ 6255 * space instructions all have a simple implementation: \ 6256 * \ 6257 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6258 * = 0b0 || 0b00 || 0b0 \ 6259 */ \ 6260 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6261 } 6262 6263 GEN_TM_NOOP(tend); 6264 GEN_TM_NOOP(tabort); 6265 GEN_TM_NOOP(tabortwc); 6266 GEN_TM_NOOP(tabortwci); 6267 GEN_TM_NOOP(tabortdc); 6268 GEN_TM_NOOP(tabortdci); 6269 GEN_TM_NOOP(tsr); 6270 static inline void gen_cp_abort(DisasContext *ctx) 6271 { 6272 // Do Nothing 6273 } 6274 6275 #define GEN_CP_PASTE_NOOP(name) \ 6276 static inline void gen_##name(DisasContext *ctx) \ 6277 { \ 6278 /* Generate invalid exception until \ 6279 * we have an implementation of the copy \ 6280 * paste facility \ 6281 */ \ 6282 gen_invalid(ctx); \ 6283 } 6284 6285 GEN_CP_PASTE_NOOP(copy) 6286 GEN_CP_PASTE_NOOP(paste) 6287 6288 static void gen_tcheck(DisasContext *ctx) 6289 { 6290 if (unlikely(!ctx->tm_enabled)) { 6291 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6292 return; 6293 } 6294 /* Because tbegin always fails, the tcheck implementation 6295 * is simple: 6296 * 6297 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6298 * = 0b1 || 0b00 || 0b0 6299 */ 6300 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6301 } 6302 6303 #if defined(CONFIG_USER_ONLY) 6304 #define GEN_TM_PRIV_NOOP(name) \ 6305 static inline void gen_##name(DisasContext *ctx) \ 6306 { \ 6307 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6308 } 6309 6310 #else 6311 6312 #define GEN_TM_PRIV_NOOP(name) \ 6313 static inline void gen_##name(DisasContext *ctx) \ 6314 { \ 6315 CHK_SV; \ 6316 if (unlikely(!ctx->tm_enabled)) { \ 6317 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6318 return; \ 6319 } \ 6320 /* Because tbegin always fails, the implementation is \ 6321 * simple: \ 6322 * \ 6323 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6324 * = 0b0 || 0b00 | 0b0 \ 6325 */ \ 6326 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6327 } 6328 6329 #endif 6330 6331 GEN_TM_PRIV_NOOP(treclaim); 6332 GEN_TM_PRIV_NOOP(trechkpt); 6333 6334 #include "translate/fp-impl.inc.c" 6335 6336 #include "translate/vmx-impl.inc.c" 6337 6338 #include "translate/vsx-impl.inc.c" 6339 6340 #include "translate/dfp-impl.inc.c" 6341 6342 #include "translate/spe-impl.inc.c" 6343 6344 /* Handles lfdp, lxsd, lxssp */ 6345 static void gen_dform39(DisasContext *ctx) 6346 { 6347 switch (ctx->opcode & 0x3) { 6348 case 0: /* lfdp */ 6349 if (ctx->insns_flags2 & PPC2_ISA205) { 6350 return gen_lfdp(ctx); 6351 } 6352 break; 6353 case 2: /* lxsd */ 6354 if (ctx->insns_flags2 & PPC2_ISA300) { 6355 return gen_lxsd(ctx); 6356 } 6357 break; 6358 case 3: /* lxssp */ 6359 if (ctx->insns_flags2 & PPC2_ISA300) { 6360 return gen_lxssp(ctx); 6361 } 6362 break; 6363 } 6364 return gen_invalid(ctx); 6365 } 6366 6367 /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6368 static void gen_dform3D(DisasContext *ctx) 6369 { 6370 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6371 switch (ctx->opcode & 0x7) { 6372 case 1: /* lxv */ 6373 if (ctx->insns_flags2 & PPC2_ISA300) { 6374 return gen_lxv(ctx); 6375 } 6376 break; 6377 case 5: /* stxv */ 6378 if (ctx->insns_flags2 & PPC2_ISA300) { 6379 return gen_stxv(ctx); 6380 } 6381 break; 6382 } 6383 } else { /* DS-FORM */ 6384 switch (ctx->opcode & 0x3) { 6385 case 0: /* stfdp */ 6386 if (ctx->insns_flags2 & PPC2_ISA205) { 6387 return gen_stfdp(ctx); 6388 } 6389 break; 6390 case 2: /* stxsd */ 6391 if (ctx->insns_flags2 & PPC2_ISA300) { 6392 return gen_stxsd(ctx); 6393 } 6394 break; 6395 case 3: /* stxssp */ 6396 if (ctx->insns_flags2 & PPC2_ISA300) { 6397 return gen_stxssp(ctx); 6398 } 6399 break; 6400 } 6401 } 6402 return gen_invalid(ctx); 6403 } 6404 6405 static opcode_t opcodes[] = { 6406 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6407 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6408 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6409 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6410 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6411 #if defined(TARGET_PPC64) 6412 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6413 #endif 6414 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6415 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6416 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6417 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6418 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6419 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6420 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6421 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6422 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6423 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6424 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6425 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6426 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6427 #if defined(TARGET_PPC64) 6428 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6429 #endif 6430 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6431 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6432 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6433 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6434 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6435 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6436 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6437 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6438 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6439 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6440 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6441 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6442 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6443 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6444 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6445 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6446 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6447 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6448 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6449 #if defined(TARGET_PPC64) 6450 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6451 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6452 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6453 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6454 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6455 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6456 #endif 6457 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6458 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6459 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6460 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6461 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6462 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6463 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6464 #if defined(TARGET_PPC64) 6465 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6466 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6467 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6468 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6469 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6470 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6471 PPC_NONE, PPC2_ISA300), 6472 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6473 PPC_NONE, PPC2_ISA300), 6474 #endif 6475 #if defined(TARGET_PPC64) 6476 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6477 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6478 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6479 #endif 6480 /* handles lfdp, lxsd, lxssp */ 6481 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6482 /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6483 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6484 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6485 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6486 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6487 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6488 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6489 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6490 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), 6491 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6492 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6493 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6494 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6495 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6496 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6497 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6498 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6499 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6500 #if defined(TARGET_PPC64) 6501 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6502 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6503 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6504 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6505 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6506 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6507 #endif 6508 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6509 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 6510 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 6511 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6512 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6513 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6514 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6515 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6516 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6517 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6518 #if defined(TARGET_PPC64) 6519 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6520 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6521 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6522 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6523 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6524 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6525 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6526 #endif 6527 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 6528 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6529 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6530 #if defined(TARGET_PPC64) 6531 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6532 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6533 #endif 6534 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6535 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6536 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6537 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6538 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6539 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6540 #if defined(TARGET_PPC64) 6541 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6542 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6543 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6544 #endif 6545 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6546 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6547 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6548 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6549 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6550 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6551 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6552 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6553 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6554 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6555 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), 6556 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6557 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6558 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6559 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6560 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6561 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6562 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6563 #if defined(TARGET_PPC64) 6564 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6565 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6566 PPC_SEGMENT_64B), 6567 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6568 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6569 PPC_SEGMENT_64B), 6570 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 6571 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 6572 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 6573 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 6574 #endif 6575 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6576 /* XXX Those instructions will need to be handled differently for 6577 * different ISA versions */ 6578 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 6579 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 6580 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 6581 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 6582 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6583 #if defined(TARGET_PPC64) 6584 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 6585 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 6586 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 6587 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6588 #endif 6589 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6590 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6591 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 6592 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 6593 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 6594 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 6595 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 6596 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 6597 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 6598 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 6599 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 6600 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6601 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 6602 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 6603 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 6604 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 6605 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 6606 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 6607 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 6608 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6609 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 6610 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 6611 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 6612 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 6613 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 6614 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 6615 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 6616 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 6617 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 6618 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 6619 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 6620 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 6621 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 6622 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 6623 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 6624 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 6625 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 6626 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 6627 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 6628 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6629 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6630 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 6631 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 6632 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 6633 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 6634 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 6635 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 6636 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 6637 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 6638 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6639 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6640 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 6641 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 6642 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6643 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6644 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 6645 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 6646 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6647 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6648 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6649 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6650 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6651 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6652 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 6653 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 6654 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6655 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6656 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6657 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6658 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6659 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6660 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6661 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6662 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6663 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6664 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6665 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6666 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6667 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6668 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6669 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6670 PPC_NONE, PPC2_BOOKE206), 6671 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6672 PPC_NONE, PPC2_BOOKE206), 6673 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6674 PPC_NONE, PPC2_BOOKE206), 6675 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6676 PPC_NONE, PPC2_BOOKE206), 6677 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6678 PPC_NONE, PPC2_BOOKE206), 6679 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 6680 PPC_NONE, PPC2_PRCNTL), 6681 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 6682 PPC_NONE, PPC2_PRCNTL), 6683 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6684 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6685 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6686 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6687 PPC_BOOKE, PPC2_BOOKE206), 6688 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), 6689 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6690 PPC_BOOKE, PPC2_BOOKE206), 6691 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6692 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6693 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6694 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6695 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 6696 #if defined(TARGET_PPC64) 6697 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6698 PPC2_ISA300), 6699 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6700 #endif 6701 6702 #undef GEN_INT_ARITH_ADD 6703 #undef GEN_INT_ARITH_ADD_CONST 6704 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6705 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6706 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6707 add_ca, compute_ca, compute_ov) \ 6708 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6709 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6710 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6711 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6712 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6713 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6714 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6715 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6716 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6717 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6718 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6719 6720 #undef GEN_INT_ARITH_DIVW 6721 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6722 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6723 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6724 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6725 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6726 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6727 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6728 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6729 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6730 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6731 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6732 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6733 6734 #if defined(TARGET_PPC64) 6735 #undef GEN_INT_ARITH_DIVD 6736 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6737 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6738 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6739 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6740 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6741 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6742 6743 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6744 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6745 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6746 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6747 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6748 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6749 6750 #undef GEN_INT_ARITH_MUL_HELPER 6751 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6752 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6753 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6754 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6755 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6756 #endif 6757 6758 #undef GEN_INT_ARITH_SUBF 6759 #undef GEN_INT_ARITH_SUBF_CONST 6760 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6761 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6762 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6763 add_ca, compute_ca, compute_ov) \ 6764 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6765 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6766 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6767 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6768 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6769 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6770 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6771 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6772 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6773 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6774 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6775 6776 #undef GEN_LOGICAL1 6777 #undef GEN_LOGICAL2 6778 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6779 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6780 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6781 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6782 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6783 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6784 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6785 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6786 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6787 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6788 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6789 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6790 #if defined(TARGET_PPC64) 6791 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6792 #endif 6793 6794 #if defined(TARGET_PPC64) 6795 #undef GEN_PPC64_R2 6796 #undef GEN_PPC64_R4 6797 #define GEN_PPC64_R2(name, opc1, opc2) \ 6798 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6799 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6800 PPC_64B) 6801 #define GEN_PPC64_R4(name, opc1, opc2) \ 6802 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6803 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6804 PPC_64B), \ 6805 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6806 PPC_64B), \ 6807 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6808 PPC_64B) 6809 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6810 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6811 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6812 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6813 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6814 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6815 #endif 6816 6817 #undef GEN_LD 6818 #undef GEN_LDU 6819 #undef GEN_LDUX 6820 #undef GEN_LDX_E 6821 #undef GEN_LDS 6822 #define GEN_LD(name, ldop, opc, type) \ 6823 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6824 #define GEN_LDU(name, ldop, opc, type) \ 6825 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 6826 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 6827 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6828 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6829 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6830 #define GEN_LDS(name, ldop, op, type) \ 6831 GEN_LD(name, ldop, op | 0x20, type) \ 6832 GEN_LDU(name, ldop, op | 0x21, type) \ 6833 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 6834 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 6835 6836 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 6837 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 6838 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 6839 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 6840 #if defined(TARGET_PPC64) 6841 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 6842 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 6843 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 6844 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 6845 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6846 6847 /* HV/P7 and later only */ 6848 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6849 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6850 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6851 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6852 #endif 6853 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6854 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6855 6856 #undef GEN_ST 6857 #undef GEN_STU 6858 #undef GEN_STUX 6859 #undef GEN_STX_E 6860 #undef GEN_STS 6861 #define GEN_ST(name, stop, opc, type) \ 6862 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6863 #define GEN_STU(name, stop, opc, type) \ 6864 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 6865 #define GEN_STUX(name, stop, opc2, opc3, type) \ 6866 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6867 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6868 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6869 #define GEN_STS(name, stop, op, type) \ 6870 GEN_ST(name, stop, op | 0x20, type) \ 6871 GEN_STU(name, stop, op | 0x21, type) \ 6872 GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 6873 GEN_STX(name, stop, 0x17, op | 0x00, type) 6874 6875 GEN_STS(stb, st8, 0x06, PPC_INTEGER) 6876 GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 6877 GEN_STS(stw, st32, 0x04, PPC_INTEGER) 6878 #if defined(TARGET_PPC64) 6879 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 6880 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 6881 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6882 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6883 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6884 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6885 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6886 #endif 6887 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6888 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6889 6890 #undef GEN_CRLOGIC 6891 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6892 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6893 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6894 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6895 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6896 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6897 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6898 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6899 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6900 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6901 6902 #undef GEN_MAC_HANDLER 6903 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6904 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6905 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6906 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6907 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6908 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6909 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6910 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6911 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6912 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6913 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6914 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6915 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6916 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6917 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6918 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6919 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6920 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6921 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6922 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6923 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6924 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6925 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6926 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6927 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6928 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6929 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6930 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6931 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6932 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6933 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6934 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6935 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6936 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6937 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6938 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6939 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6940 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6941 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6942 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6943 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6944 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6945 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6946 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6947 6948 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6949 PPC_NONE, PPC2_TM), 6950 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6951 PPC_NONE, PPC2_TM), 6952 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6953 PPC_NONE, PPC2_TM), 6954 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6955 PPC_NONE, PPC2_TM), 6956 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6957 PPC_NONE, PPC2_TM), 6958 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6959 PPC_NONE, PPC2_TM), 6960 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6961 PPC_NONE, PPC2_TM), 6962 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6963 PPC_NONE, PPC2_TM), 6964 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6965 PPC_NONE, PPC2_TM), 6966 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6967 PPC_NONE, PPC2_TM), 6968 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6969 PPC_NONE, PPC2_TM), 6970 6971 #include "translate/fp-ops.inc.c" 6972 6973 #include "translate/vmx-ops.inc.c" 6974 6975 #include "translate/vsx-ops.inc.c" 6976 6977 #include "translate/dfp-ops.inc.c" 6978 6979 #include "translate/spe-ops.inc.c" 6980 }; 6981 6982 #include "helper_regs.h" 6983 #include "translate_init.c" 6984 6985 /*****************************************************************************/ 6986 /* Misc PowerPC helpers */ 6987 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 6988 int flags) 6989 { 6990 #define RGPL 4 6991 #define RFPL 4 6992 6993 PowerPCCPU *cpu = POWERPC_CPU(cs); 6994 CPUPPCState *env = &cpu->env; 6995 int i; 6996 6997 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 6998 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 6999 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7000 cs->cpu_index); 7001 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7002 TARGET_FMT_lx " iidx %d didx %d\n", 7003 env->msr, env->spr[SPR_HID0], 7004 env->hflags, env->immu_idx, env->dmmu_idx); 7005 #if !defined(NO_TIMER_DUMP) 7006 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7007 #if !defined(CONFIG_USER_ONLY) 7008 " DECR %08" PRIu32 7009 #endif 7010 "\n", 7011 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7012 #if !defined(CONFIG_USER_ONLY) 7013 , cpu_ppc_load_decr(env) 7014 #endif 7015 ); 7016 #endif 7017 for (i = 0; i < 32; i++) { 7018 if ((i & (RGPL - 1)) == 0) 7019 cpu_fprintf(f, "GPR%02d", i); 7020 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7021 if ((i & (RGPL - 1)) == (RGPL - 1)) 7022 cpu_fprintf(f, "\n"); 7023 } 7024 cpu_fprintf(f, "CR "); 7025 for (i = 0; i < 8; i++) 7026 cpu_fprintf(f, "%01x", env->crf[i]); 7027 cpu_fprintf(f, " ["); 7028 for (i = 0; i < 8; i++) { 7029 char a = '-'; 7030 if (env->crf[i] & 0x08) 7031 a = 'L'; 7032 else if (env->crf[i] & 0x04) 7033 a = 'G'; 7034 else if (env->crf[i] & 0x02) 7035 a = 'E'; 7036 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7037 } 7038 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7039 env->reserve_addr); 7040 for (i = 0; i < 32; i++) { 7041 if ((i & (RFPL - 1)) == 0) 7042 cpu_fprintf(f, "FPR%02d", i); 7043 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); 7044 if ((i & (RFPL - 1)) == (RFPL - 1)) 7045 cpu_fprintf(f, "\n"); 7046 } 7047 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7048 #if !defined(CONFIG_USER_ONLY) 7049 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7050 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7051 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7052 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7053 7054 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7055 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7056 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7057 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7058 7059 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7060 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7061 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7062 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7063 7064 #if defined(TARGET_PPC64) 7065 if (env->excp_model == POWERPC_EXCP_POWER7 || 7066 env->excp_model == POWERPC_EXCP_POWER8) { 7067 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7068 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7069 } 7070 #endif 7071 if (env->excp_model == POWERPC_EXCP_BOOKE) { 7072 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7073 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7074 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7075 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7076 7077 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7078 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7079 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7080 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7081 7082 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7083 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7084 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7085 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7086 7087 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7088 " EPR " TARGET_FMT_lx "\n", 7089 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7090 env->spr[SPR_BOOKE_EPR]); 7091 7092 /* FSL-specific */ 7093 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7094 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7095 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7096 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7097 7098 /* 7099 * IVORs are left out as they are large and do not change often -- 7100 * they can be read with "p $ivor0", "p $ivor1", etc. 7101 */ 7102 } 7103 7104 #if defined(TARGET_PPC64) 7105 if (env->flags & POWERPC_FLAG_CFAR) { 7106 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7107 } 7108 #endif 7109 7110 if (env->spr_cb[SPR_LPCR].name) 7111 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7112 7113 switch (POWERPC_MMU_VER(env->mmu_model)) { 7114 case POWERPC_MMU_32B: 7115 case POWERPC_MMU_601: 7116 case POWERPC_MMU_SOFT_6xx: 7117 case POWERPC_MMU_SOFT_74xx: 7118 #if defined(TARGET_PPC64) 7119 case POWERPC_MMU_VER_64B: 7120 case POWERPC_MMU_VER_2_03: 7121 case POWERPC_MMU_VER_2_06: 7122 case POWERPC_MMU_VER_2_07: 7123 case POWERPC_MMU_VER_3_00: 7124 #endif 7125 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7126 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7127 } 7128 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7129 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7130 break; 7131 case POWERPC_MMU_BOOKE206: 7132 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7133 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7134 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7135 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7136 7137 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7138 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7139 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7140 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7141 7142 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7143 " TLB1CFG " TARGET_FMT_lx "\n", 7144 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7145 env->spr[SPR_BOOKE_TLB1CFG]); 7146 break; 7147 default: 7148 break; 7149 } 7150 #endif 7151 7152 #undef RGPL 7153 #undef RFPL 7154 } 7155 7156 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, 7157 fprintf_function cpu_fprintf, int flags) 7158 { 7159 #if defined(DO_PPC_STATISTICS) 7160 PowerPCCPU *cpu = POWERPC_CPU(cs); 7161 opc_handler_t **t1, **t2, **t3, *handler; 7162 int op1, op2, op3; 7163 7164 t1 = cpu->env.opcodes; 7165 for (op1 = 0; op1 < 64; op1++) { 7166 handler = t1[op1]; 7167 if (is_indirect_opcode(handler)) { 7168 t2 = ind_table(handler); 7169 for (op2 = 0; op2 < 32; op2++) { 7170 handler = t2[op2]; 7171 if (is_indirect_opcode(handler)) { 7172 t3 = ind_table(handler); 7173 for (op3 = 0; op3 < 32; op3++) { 7174 handler = t3[op3]; 7175 if (handler->count == 0) 7176 continue; 7177 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " 7178 "%016" PRIx64 " %" PRId64 "\n", 7179 op1, op2, op3, op1, (op3 << 5) | op2, 7180 handler->oname, 7181 handler->count, handler->count); 7182 } 7183 } else { 7184 if (handler->count == 0) 7185 continue; 7186 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " 7187 "%016" PRIx64 " %" PRId64 "\n", 7188 op1, op2, op1, op2, handler->oname, 7189 handler->count, handler->count); 7190 } 7191 } 7192 } else { 7193 if (handler->count == 0) 7194 continue; 7195 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 7196 " %" PRId64 "\n", 7197 op1, op1, handler->oname, 7198 handler->count, handler->count); 7199 } 7200 } 7201 #endif 7202 } 7203 7204 /*****************************************************************************/ 7205 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 7206 { 7207 CPUPPCState *env = cs->env_ptr; 7208 DisasContext ctx, *ctxp = &ctx; 7209 opc_handler_t **table, *handler; 7210 target_ulong pc_start; 7211 int num_insns; 7212 int max_insns; 7213 7214 pc_start = tb->pc; 7215 ctx.nip = pc_start; 7216 ctx.tb = tb; 7217 ctx.exception = POWERPC_EXCP_NONE; 7218 ctx.spr_cb = env->spr_cb; 7219 ctx.pr = msr_pr; 7220 ctx.mem_idx = env->dmmu_idx; 7221 ctx.dr = msr_dr; 7222 #if !defined(CONFIG_USER_ONLY) 7223 ctx.hv = msr_hv || !env->has_hv_mode; 7224 #endif 7225 ctx.insns_flags = env->insns_flags; 7226 ctx.insns_flags2 = env->insns_flags2; 7227 ctx.access_type = -1; 7228 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7229 ctx.le_mode = !!(env->hflags & (1 << MSR_LE)); 7230 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE; 7231 #if defined(TARGET_PPC64) 7232 ctx.sf_mode = msr_is_64bit(env, env->msr); 7233 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7234 #endif 7235 if (env->mmu_model == POWERPC_MMU_32B || 7236 env->mmu_model == POWERPC_MMU_601 || 7237 (env->mmu_model & POWERPC_MMU_64B)) 7238 ctx.lazy_tlb_flush = true; 7239 7240 ctx.fpu_enabled = !!msr_fp; 7241 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7242 ctx.spe_enabled = !!msr_spe; 7243 else 7244 ctx.spe_enabled = false; 7245 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) 7246 ctx.altivec_enabled = !!msr_vr; 7247 else 7248 ctx.altivec_enabled = false; 7249 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7250 ctx.vsx_enabled = !!msr_vsx; 7251 } else { 7252 ctx.vsx_enabled = false; 7253 } 7254 #if defined(TARGET_PPC64) 7255 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7256 ctx.tm_enabled = !!msr_tm; 7257 } else { 7258 ctx.tm_enabled = false; 7259 } 7260 #endif 7261 ctx.gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7262 if ((env->flags & POWERPC_FLAG_SE) && msr_se) 7263 ctx.singlestep_enabled = CPU_SINGLE_STEP; 7264 else 7265 ctx.singlestep_enabled = 0; 7266 if ((env->flags & POWERPC_FLAG_BE) && msr_be) 7267 ctx.singlestep_enabled |= CPU_BRANCH_STEP; 7268 if (unlikely(cs->singlestep_enabled)) { 7269 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7270 } 7271 #if defined (DO_SINGLE_STEP) && 0 7272 /* Single step trace mode */ 7273 msr_se = 1; 7274 #endif 7275 num_insns = 0; 7276 max_insns = tb_cflags(tb) & CF_COUNT_MASK; 7277 if (max_insns == 0) { 7278 max_insns = CF_COUNT_MASK; 7279 } 7280 if (max_insns > TCG_MAX_INSNS) { 7281 max_insns = TCG_MAX_INSNS; 7282 } 7283 7284 gen_tb_start(tb); 7285 tcg_clear_temp_count(); 7286 /* Set env in case of segfault during code fetch */ 7287 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) { 7288 tcg_gen_insn_start(ctx.nip); 7289 num_insns++; 7290 7291 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) { 7292 gen_debug_exception(ctxp); 7293 /* The address covered by the breakpoint must be included in 7294 [tb->pc, tb->pc + tb->size) in order to for it to be 7295 properly cleared -- thus we increment the PC here so that 7296 the logic setting tb->size below does the right thing. */ 7297 ctx.nip += 4; 7298 break; 7299 } 7300 7301 LOG_DISAS("----------------\n"); 7302 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7303 ctx.nip, ctx.mem_idx, (int)msr_ir); 7304 if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) 7305 gen_io_start(); 7306 if (unlikely(need_byteswap(&ctx))) { 7307 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); 7308 } else { 7309 ctx.opcode = cpu_ldl_code(env, ctx.nip); 7310 } 7311 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7312 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), 7313 opc3(ctx.opcode), opc4(ctx.opcode), 7314 ctx.le_mode ? "little" : "big"); 7315 ctx.nip += 4; 7316 table = env->opcodes; 7317 handler = table[opc1(ctx.opcode)]; 7318 if (is_indirect_opcode(handler)) { 7319 table = ind_table(handler); 7320 handler = table[opc2(ctx.opcode)]; 7321 if (is_indirect_opcode(handler)) { 7322 table = ind_table(handler); 7323 handler = table[opc3(ctx.opcode)]; 7324 if (is_indirect_opcode(handler)) { 7325 table = ind_table(handler); 7326 handler = table[opc4(ctx.opcode)]; 7327 } 7328 } 7329 } 7330 /* Is opcode *REALLY* valid ? */ 7331 if (unlikely(handler->handler == &gen_invalid)) { 7332 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7333 "%02x - %02x - %02x - %02x (%08x) " 7334 TARGET_FMT_lx " %d\n", 7335 opc1(ctx.opcode), opc2(ctx.opcode), 7336 opc3(ctx.opcode), opc4(ctx.opcode), 7337 ctx.opcode, ctx.nip - 4, (int)msr_ir); 7338 } else { 7339 uint32_t inval; 7340 7341 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { 7342 inval = handler->inval2; 7343 } else { 7344 inval = handler->inval1; 7345 } 7346 7347 if (unlikely((ctx.opcode & inval) != 0)) { 7348 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7349 "%02x - %02x - %02x - %02x (%08x) " 7350 TARGET_FMT_lx "\n", ctx.opcode & inval, 7351 opc1(ctx.opcode), opc2(ctx.opcode), 7352 opc3(ctx.opcode), opc4(ctx.opcode), 7353 ctx.opcode, ctx.nip - 4); 7354 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); 7355 break; 7356 } 7357 } 7358 (*(handler->handler))(&ctx); 7359 #if defined(DO_PPC_STATISTICS) 7360 handler->count++; 7361 #endif 7362 /* Check trace mode exceptions */ 7363 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && 7364 (ctx.nip <= 0x100 || ctx.nip > 0xF00) && 7365 ctx.exception != POWERPC_SYSCALL && 7366 ctx.exception != POWERPC_EXCP_TRAP && 7367 ctx.exception != POWERPC_EXCP_BRANCH)) { 7368 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip); 7369 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || 7370 (cs->singlestep_enabled) || 7371 singlestep || 7372 num_insns >= max_insns)) { 7373 /* if we reach a page boundary or are single stepping, stop 7374 * generation 7375 */ 7376 break; 7377 } 7378 if (tcg_check_temp_count()) { 7379 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked " 7380 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode), 7381 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode); 7382 exit(1); 7383 } 7384 } 7385 if (tb_cflags(tb) & CF_LAST_IO) 7386 gen_io_end(); 7387 if (ctx.exception == POWERPC_EXCP_NONE) { 7388 gen_goto_tb(&ctx, 0, ctx.nip); 7389 } else if (ctx.exception != POWERPC_EXCP_BRANCH) { 7390 if (unlikely(cs->singlestep_enabled)) { 7391 gen_debug_exception(ctxp); 7392 } 7393 /* Generate the return instruction */ 7394 tcg_gen_exit_tb(0); 7395 } 7396 gen_tb_end(tb, num_insns); 7397 7398 tb->size = ctx.nip - pc_start; 7399 tb->icount = num_insns; 7400 7401 #if defined(DEBUG_DISAS) 7402 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 7403 && qemu_log_in_addr_range(pc_start)) { 7404 int flags; 7405 flags = env->bfd_mach; 7406 flags |= ctx.le_mode << 16; 7407 qemu_log_lock(); 7408 qemu_log("IN: %s\n", lookup_symbol(pc_start)); 7409 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags); 7410 qemu_log("\n"); 7411 qemu_log_unlock(); 7412 } 7413 #endif 7414 } 7415 7416 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7417 target_ulong *data) 7418 { 7419 env->nip = data[0]; 7420 } 7421