1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg-op.h" 27 #include "qemu/host-utils.h" 28 #include "exec/cpu_ldst.h" 29 30 #include "exec/helper-proto.h" 31 #include "exec/helper-gen.h" 32 33 #include "trace-tcg.h" 34 #include "exec/log.h" 35 36 37 #define CPU_SINGLE_STEP 0x1 38 #define CPU_BRANCH_STEP 0x2 39 #define GDBSTUB_SINGLE_STEP 0x4 40 41 /* Include definitions for instructions classes and implementations flags */ 42 //#define PPC_DEBUG_DISAS 43 //#define DO_PPC_STATISTICS 44 45 #ifdef PPC_DEBUG_DISAS 46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 47 #else 48 # define LOG_DISAS(...) do { } while (0) 49 #endif 50 /*****************************************************************************/ 51 /* Code translation helpers */ 52 53 /* global register indexes */ 54 static TCGv_env cpu_env; 55 static char cpu_reg_names[10*3 + 22*4 /* GPR */ 56 + 10*4 + 22*5 /* SPE GPRh */ 57 + 10*4 + 22*5 /* FPR */ 58 + 2*(10*6 + 22*7) /* AVRh, AVRl */ 59 + 10*5 + 22*6 /* VSR */ 60 + 8*5 /* CRF */]; 61 static TCGv cpu_gpr[32]; 62 static TCGv cpu_gprh[32]; 63 static TCGv_i64 cpu_fpr[32]; 64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; 65 static TCGv_i64 cpu_vsr[32]; 66 static TCGv_i32 cpu_crf[8]; 67 static TCGv cpu_nip; 68 static TCGv cpu_msr; 69 static TCGv cpu_ctr; 70 static TCGv cpu_lr; 71 #if defined(TARGET_PPC64) 72 static TCGv cpu_cfar; 73 #endif 74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; 75 static TCGv cpu_reserve; 76 static TCGv cpu_fpscr; 77 static TCGv_i32 cpu_access_type; 78 79 #include "exec/gen-icount.h" 80 81 void ppc_translate_init(void) 82 { 83 int i; 84 char* p; 85 size_t cpu_reg_names_size; 86 static int done_init = 0; 87 88 if (done_init) 89 return; 90 91 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 92 tcg_ctx.tcg_env = cpu_env; 93 94 p = cpu_reg_names; 95 cpu_reg_names_size = sizeof(cpu_reg_names); 96 97 for (i = 0; i < 8; i++) { 98 snprintf(p, cpu_reg_names_size, "crf%d", i); 99 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 100 offsetof(CPUPPCState, crf[i]), p); 101 p += 5; 102 cpu_reg_names_size -= 5; 103 } 104 105 for (i = 0; i < 32; i++) { 106 snprintf(p, cpu_reg_names_size, "r%d", i); 107 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 108 offsetof(CPUPPCState, gpr[i]), p); 109 p += (i < 10) ? 3 : 4; 110 cpu_reg_names_size -= (i < 10) ? 3 : 4; 111 snprintf(p, cpu_reg_names_size, "r%dH", i); 112 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 113 offsetof(CPUPPCState, gprh[i]), p); 114 p += (i < 10) ? 4 : 5; 115 cpu_reg_names_size -= (i < 10) ? 4 : 5; 116 117 snprintf(p, cpu_reg_names_size, "fp%d", i); 118 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 119 offsetof(CPUPPCState, fpr[i]), p); 120 p += (i < 10) ? 4 : 5; 121 cpu_reg_names_size -= (i < 10) ? 4 : 5; 122 123 snprintf(p, cpu_reg_names_size, "avr%dH", i); 124 #ifdef HOST_WORDS_BIGENDIAN 125 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 126 offsetof(CPUPPCState, avr[i].u64[0]), p); 127 #else 128 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 129 offsetof(CPUPPCState, avr[i].u64[1]), p); 130 #endif 131 p += (i < 10) ? 6 : 7; 132 cpu_reg_names_size -= (i < 10) ? 6 : 7; 133 134 snprintf(p, cpu_reg_names_size, "avr%dL", i); 135 #ifdef HOST_WORDS_BIGENDIAN 136 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 137 offsetof(CPUPPCState, avr[i].u64[1]), p); 138 #else 139 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 140 offsetof(CPUPPCState, avr[i].u64[0]), p); 141 #endif 142 p += (i < 10) ? 6 : 7; 143 cpu_reg_names_size -= (i < 10) ? 6 : 7; 144 snprintf(p, cpu_reg_names_size, "vsr%d", i); 145 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, 146 offsetof(CPUPPCState, vsr[i]), p); 147 p += (i < 10) ? 5 : 6; 148 cpu_reg_names_size -= (i < 10) ? 5 : 6; 149 } 150 151 cpu_nip = tcg_global_mem_new(cpu_env, 152 offsetof(CPUPPCState, nip), "nip"); 153 154 cpu_msr = tcg_global_mem_new(cpu_env, 155 offsetof(CPUPPCState, msr), "msr"); 156 157 cpu_ctr = tcg_global_mem_new(cpu_env, 158 offsetof(CPUPPCState, ctr), "ctr"); 159 160 cpu_lr = tcg_global_mem_new(cpu_env, 161 offsetof(CPUPPCState, lr), "lr"); 162 163 #if defined(TARGET_PPC64) 164 cpu_cfar = tcg_global_mem_new(cpu_env, 165 offsetof(CPUPPCState, cfar), "cfar"); 166 #endif 167 168 cpu_xer = tcg_global_mem_new(cpu_env, 169 offsetof(CPUPPCState, xer), "xer"); 170 cpu_so = tcg_global_mem_new(cpu_env, 171 offsetof(CPUPPCState, so), "SO"); 172 cpu_ov = tcg_global_mem_new(cpu_env, 173 offsetof(CPUPPCState, ov), "OV"); 174 cpu_ca = tcg_global_mem_new(cpu_env, 175 offsetof(CPUPPCState, ca), "CA"); 176 177 cpu_reserve = tcg_global_mem_new(cpu_env, 178 offsetof(CPUPPCState, reserve_addr), 179 "reserve_addr"); 180 181 cpu_fpscr = tcg_global_mem_new(cpu_env, 182 offsetof(CPUPPCState, fpscr), "fpscr"); 183 184 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 185 offsetof(CPUPPCState, access_type), "access_type"); 186 187 done_init = 1; 188 } 189 190 /* internal defines */ 191 struct DisasContext { 192 struct TranslationBlock *tb; 193 target_ulong nip; 194 uint32_t opcode; 195 uint32_t exception; 196 /* Routine used to access memory */ 197 bool pr, hv, dr, le_mode; 198 bool lazy_tlb_flush; 199 bool need_access_type; 200 int mem_idx; 201 int access_type; 202 /* Translation flags */ 203 TCGMemOp default_tcg_memop_mask; 204 #if defined(TARGET_PPC64) 205 bool sf_mode; 206 bool has_cfar; 207 #endif 208 bool fpu_enabled; 209 bool altivec_enabled; 210 bool vsx_enabled; 211 bool spe_enabled; 212 bool tm_enabled; 213 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 214 int singlestep_enabled; 215 uint64_t insns_flags; 216 uint64_t insns_flags2; 217 }; 218 219 /* Return true iff byteswap is needed in a scalar memop */ 220 static inline bool need_byteswap(const DisasContext *ctx) 221 { 222 #if defined(TARGET_WORDS_BIGENDIAN) 223 return ctx->le_mode; 224 #else 225 return !ctx->le_mode; 226 #endif 227 } 228 229 /* True when active word size < size of target_long. */ 230 #ifdef TARGET_PPC64 231 # define NARROW_MODE(C) (!(C)->sf_mode) 232 #else 233 # define NARROW_MODE(C) 0 234 #endif 235 236 struct opc_handler_t { 237 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 238 uint32_t inval1; 239 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 240 uint32_t inval2; 241 /* instruction type */ 242 uint64_t type; 243 /* extended instruction type */ 244 uint64_t type2; 245 /* handler */ 246 void (*handler)(DisasContext *ctx); 247 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 248 const char *oname; 249 #endif 250 #if defined(DO_PPC_STATISTICS) 251 uint64_t count; 252 #endif 253 }; 254 255 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 256 { 257 if (ctx->need_access_type && ctx->access_type != access_type) { 258 tcg_gen_movi_i32(cpu_access_type, access_type); 259 ctx->access_type = access_type; 260 } 261 } 262 263 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 264 { 265 if (NARROW_MODE(ctx)) { 266 nip = (uint32_t)nip; 267 } 268 tcg_gen_movi_tl(cpu_nip, nip); 269 } 270 271 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 272 { 273 TCGv_i32 t0, t1; 274 275 /* These are all synchronous exceptions, we set the PC back to 276 * the faulting instruction 277 */ 278 if (ctx->exception == POWERPC_EXCP_NONE) { 279 gen_update_nip(ctx, ctx->nip - 4); 280 } 281 t0 = tcg_const_i32(excp); 282 t1 = tcg_const_i32(error); 283 gen_helper_raise_exception_err(cpu_env, t0, t1); 284 tcg_temp_free_i32(t0); 285 tcg_temp_free_i32(t1); 286 ctx->exception = (excp); 287 } 288 289 static void gen_exception(DisasContext *ctx, uint32_t excp) 290 { 291 TCGv_i32 t0; 292 293 /* These are all synchronous exceptions, we set the PC back to 294 * the faulting instruction 295 */ 296 if (ctx->exception == POWERPC_EXCP_NONE) { 297 gen_update_nip(ctx, ctx->nip - 4); 298 } 299 t0 = tcg_const_i32(excp); 300 gen_helper_raise_exception(cpu_env, t0); 301 tcg_temp_free_i32(t0); 302 ctx->exception = (excp); 303 } 304 305 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 306 target_ulong nip) 307 { 308 TCGv_i32 t0; 309 310 gen_update_nip(ctx, nip); 311 t0 = tcg_const_i32(excp); 312 gen_helper_raise_exception(cpu_env, t0); 313 tcg_temp_free_i32(t0); 314 ctx->exception = (excp); 315 } 316 317 static void gen_debug_exception(DisasContext *ctx) 318 { 319 TCGv_i32 t0; 320 321 /* These are all synchronous exceptions, we set the PC back to 322 * the faulting instruction 323 */ 324 if ((ctx->exception != POWERPC_EXCP_BRANCH) && 325 (ctx->exception != POWERPC_EXCP_SYNC)) { 326 gen_update_nip(ctx, ctx->nip); 327 } 328 t0 = tcg_const_i32(EXCP_DEBUG); 329 gen_helper_raise_exception(cpu_env, t0); 330 tcg_temp_free_i32(t0); 331 } 332 333 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 334 { 335 /* Will be converted to program check if needed */ 336 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 337 } 338 339 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 340 { 341 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 342 } 343 344 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 345 { 346 /* Will be converted to program check if needed */ 347 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 348 } 349 350 /* Stop translation */ 351 static inline void gen_stop_exception(DisasContext *ctx) 352 { 353 gen_update_nip(ctx, ctx->nip); 354 ctx->exception = POWERPC_EXCP_STOP; 355 } 356 357 #ifndef CONFIG_USER_ONLY 358 /* No need to update nip here, as execution flow will change */ 359 static inline void gen_sync_exception(DisasContext *ctx) 360 { 361 ctx->exception = POWERPC_EXCP_SYNC; 362 } 363 #endif 364 365 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 366 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 367 368 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 369 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 370 371 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 372 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 373 374 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 375 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 376 377 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 378 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 379 380 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 381 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 382 383 typedef struct opcode_t { 384 unsigned char opc1, opc2, opc3, opc4; 385 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 386 unsigned char pad[4]; 387 #endif 388 opc_handler_t handler; 389 const char *oname; 390 } opcode_t; 391 392 /* Helpers for priv. check */ 393 #define GEN_PRIV \ 394 do { \ 395 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 396 } while (0) 397 398 #if defined(CONFIG_USER_ONLY) 399 #define CHK_HV GEN_PRIV 400 #define CHK_SV GEN_PRIV 401 #define CHK_HVRM GEN_PRIV 402 #else 403 #define CHK_HV \ 404 do { \ 405 if (unlikely(ctx->pr || !ctx->hv)) { \ 406 GEN_PRIV; \ 407 } \ 408 } while (0) 409 #define CHK_SV \ 410 do { \ 411 if (unlikely(ctx->pr)) { \ 412 GEN_PRIV; \ 413 } \ 414 } while (0) 415 #define CHK_HVRM \ 416 do { \ 417 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 418 GEN_PRIV; \ 419 } \ 420 } while (0) 421 #endif 422 423 #define CHK_NONE 424 425 /*****************************************************************************/ 426 /* PowerPC instructions table */ 427 428 #if defined(DO_PPC_STATISTICS) 429 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 430 { \ 431 .opc1 = op1, \ 432 .opc2 = op2, \ 433 .opc3 = op3, \ 434 .opc4 = 0xff, \ 435 .handler = { \ 436 .inval1 = invl, \ 437 .type = _typ, \ 438 .type2 = _typ2, \ 439 .handler = &gen_##name, \ 440 .oname = stringify(name), \ 441 }, \ 442 .oname = stringify(name), \ 443 } 444 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 445 { \ 446 .opc1 = op1, \ 447 .opc2 = op2, \ 448 .opc3 = op3, \ 449 .opc4 = 0xff, \ 450 .handler = { \ 451 .inval1 = invl1, \ 452 .inval2 = invl2, \ 453 .type = _typ, \ 454 .type2 = _typ2, \ 455 .handler = &gen_##name, \ 456 .oname = stringify(name), \ 457 }, \ 458 .oname = stringify(name), \ 459 } 460 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 461 { \ 462 .opc1 = op1, \ 463 .opc2 = op2, \ 464 .opc3 = op3, \ 465 .opc4 = 0xff, \ 466 .handler = { \ 467 .inval1 = invl, \ 468 .type = _typ, \ 469 .type2 = _typ2, \ 470 .handler = &gen_##name, \ 471 .oname = onam, \ 472 }, \ 473 .oname = onam, \ 474 } 475 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 476 { \ 477 .opc1 = op1, \ 478 .opc2 = op2, \ 479 .opc3 = op3, \ 480 .opc4 = op4, \ 481 .handler = { \ 482 .inval1 = invl, \ 483 .type = _typ, \ 484 .type2 = _typ2, \ 485 .handler = &gen_##name, \ 486 .oname = stringify(name), \ 487 }, \ 488 .oname = stringify(name), \ 489 } 490 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 491 { \ 492 .opc1 = op1, \ 493 .opc2 = op2, \ 494 .opc3 = op3, \ 495 .opc4 = op4, \ 496 .handler = { \ 497 .inval1 = invl, \ 498 .type = _typ, \ 499 .type2 = _typ2, \ 500 .handler = &gen_##name, \ 501 .oname = onam, \ 502 }, \ 503 .oname = onam, \ 504 } 505 #else 506 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 507 { \ 508 .opc1 = op1, \ 509 .opc2 = op2, \ 510 .opc3 = op3, \ 511 .opc4 = 0xff, \ 512 .handler = { \ 513 .inval1 = invl, \ 514 .type = _typ, \ 515 .type2 = _typ2, \ 516 .handler = &gen_##name, \ 517 }, \ 518 .oname = stringify(name), \ 519 } 520 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 521 { \ 522 .opc1 = op1, \ 523 .opc2 = op2, \ 524 .opc3 = op3, \ 525 .opc4 = 0xff, \ 526 .handler = { \ 527 .inval1 = invl1, \ 528 .inval2 = invl2, \ 529 .type = _typ, \ 530 .type2 = _typ2, \ 531 .handler = &gen_##name, \ 532 }, \ 533 .oname = stringify(name), \ 534 } 535 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 536 { \ 537 .opc1 = op1, \ 538 .opc2 = op2, \ 539 .opc3 = op3, \ 540 .opc4 = 0xff, \ 541 .handler = { \ 542 .inval1 = invl, \ 543 .type = _typ, \ 544 .type2 = _typ2, \ 545 .handler = &gen_##name, \ 546 }, \ 547 .oname = onam, \ 548 } 549 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 550 { \ 551 .opc1 = op1, \ 552 .opc2 = op2, \ 553 .opc3 = op3, \ 554 .opc4 = op4, \ 555 .handler = { \ 556 .inval1 = invl, \ 557 .type = _typ, \ 558 .type2 = _typ2, \ 559 .handler = &gen_##name, \ 560 }, \ 561 .oname = stringify(name), \ 562 } 563 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 564 { \ 565 .opc1 = op1, \ 566 .opc2 = op2, \ 567 .opc3 = op3, \ 568 .opc4 = op4, \ 569 .handler = { \ 570 .inval1 = invl, \ 571 .type = _typ, \ 572 .type2 = _typ2, \ 573 .handler = &gen_##name, \ 574 }, \ 575 .oname = onam, \ 576 } 577 #endif 578 579 /* SPR load/store helpers */ 580 static inline void gen_load_spr(TCGv t, int reg) 581 { 582 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 583 } 584 585 static inline void gen_store_spr(int reg, TCGv t) 586 { 587 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 588 } 589 590 /* Invalid instruction */ 591 static void gen_invalid(DisasContext *ctx) 592 { 593 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 594 } 595 596 static opc_handler_t invalid_handler = { 597 .inval1 = 0xFFFFFFFF, 598 .inval2 = 0xFFFFFFFF, 599 .type = PPC_NONE, 600 .type2 = PPC_NONE, 601 .handler = gen_invalid, 602 }; 603 604 /*** Integer comparison ***/ 605 606 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 607 { 608 TCGv t0 = tcg_temp_new(); 609 TCGv_i32 t1 = tcg_temp_new_i32(); 610 611 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 612 613 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); 614 tcg_gen_trunc_tl_i32(t1, t0); 615 tcg_gen_shli_i32(t1, t1, CRF_LT_BIT); 616 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 617 618 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); 619 tcg_gen_trunc_tl_i32(t1, t0); 620 tcg_gen_shli_i32(t1, t1, CRF_GT_BIT); 621 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 622 623 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); 624 tcg_gen_trunc_tl_i32(t1, t0); 625 tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT); 626 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 627 628 tcg_temp_free(t0); 629 tcg_temp_free_i32(t1); 630 } 631 632 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 633 { 634 TCGv t0 = tcg_const_tl(arg1); 635 gen_op_cmp(arg0, t0, s, crf); 636 tcg_temp_free(t0); 637 } 638 639 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 640 { 641 TCGv t0, t1; 642 t0 = tcg_temp_new(); 643 t1 = tcg_temp_new(); 644 if (s) { 645 tcg_gen_ext32s_tl(t0, arg0); 646 tcg_gen_ext32s_tl(t1, arg1); 647 } else { 648 tcg_gen_ext32u_tl(t0, arg0); 649 tcg_gen_ext32u_tl(t1, arg1); 650 } 651 gen_op_cmp(t0, t1, s, crf); 652 tcg_temp_free(t1); 653 tcg_temp_free(t0); 654 } 655 656 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 657 { 658 TCGv t0 = tcg_const_tl(arg1); 659 gen_op_cmp32(arg0, t0, s, crf); 660 tcg_temp_free(t0); 661 } 662 663 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 664 { 665 if (NARROW_MODE(ctx)) { 666 gen_op_cmpi32(reg, 0, 1, 0); 667 } else { 668 gen_op_cmpi(reg, 0, 1, 0); 669 } 670 } 671 672 /* cmp */ 673 static void gen_cmp(DisasContext *ctx) 674 { 675 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 676 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 677 1, crfD(ctx->opcode)); 678 } else { 679 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 680 1, crfD(ctx->opcode)); 681 } 682 } 683 684 /* cmpi */ 685 static void gen_cmpi(DisasContext *ctx) 686 { 687 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 688 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 689 1, crfD(ctx->opcode)); 690 } else { 691 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 692 1, crfD(ctx->opcode)); 693 } 694 } 695 696 /* cmpl */ 697 static void gen_cmpl(DisasContext *ctx) 698 { 699 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 700 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 701 0, crfD(ctx->opcode)); 702 } else { 703 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 704 0, crfD(ctx->opcode)); 705 } 706 } 707 708 /* cmpli */ 709 static void gen_cmpli(DisasContext *ctx) 710 { 711 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 712 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 713 0, crfD(ctx->opcode)); 714 } else { 715 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 716 0, crfD(ctx->opcode)); 717 } 718 } 719 720 /* cmprb - range comparison: isupper, isaplha, islower*/ 721 static void gen_cmprb(DisasContext *ctx) 722 { 723 TCGv_i32 src1 = tcg_temp_new_i32(); 724 TCGv_i32 src2 = tcg_temp_new_i32(); 725 TCGv_i32 src2lo = tcg_temp_new_i32(); 726 TCGv_i32 src2hi = tcg_temp_new_i32(); 727 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 728 729 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 730 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 731 732 tcg_gen_andi_i32(src1, src1, 0xFF); 733 tcg_gen_ext8u_i32(src2lo, src2); 734 tcg_gen_shri_i32(src2, src2, 8); 735 tcg_gen_ext8u_i32(src2hi, src2); 736 737 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 738 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 739 tcg_gen_and_i32(crf, src2lo, src2hi); 740 741 if (ctx->opcode & 0x00200000) { 742 tcg_gen_shri_i32(src2, src2, 8); 743 tcg_gen_ext8u_i32(src2lo, src2); 744 tcg_gen_shri_i32(src2, src2, 8); 745 tcg_gen_ext8u_i32(src2hi, src2); 746 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 747 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 748 tcg_gen_and_i32(src2lo, src2lo, src2hi); 749 tcg_gen_or_i32(crf, crf, src2lo); 750 } 751 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 752 tcg_temp_free_i32(src1); 753 tcg_temp_free_i32(src2); 754 tcg_temp_free_i32(src2lo); 755 tcg_temp_free_i32(src2hi); 756 } 757 758 #if defined(TARGET_PPC64) 759 /* cmpeqb */ 760 static void gen_cmpeqb(DisasContext *ctx) 761 { 762 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 763 cpu_gpr[rB(ctx->opcode)]); 764 } 765 #endif 766 767 /* isel (PowerPC 2.03 specification) */ 768 static void gen_isel(DisasContext *ctx) 769 { 770 uint32_t bi = rC(ctx->opcode); 771 uint32_t mask = 0x08 >> (bi & 0x03); 772 TCGv t0 = tcg_temp_new(); 773 TCGv zr; 774 775 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 776 tcg_gen_andi_tl(t0, t0, mask); 777 778 zr = tcg_const_tl(0); 779 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 780 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 781 cpu_gpr[rB(ctx->opcode)]); 782 tcg_temp_free(zr); 783 tcg_temp_free(t0); 784 } 785 786 /* cmpb: PowerPC 2.05 specification */ 787 static void gen_cmpb(DisasContext *ctx) 788 { 789 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 790 cpu_gpr[rB(ctx->opcode)]); 791 } 792 793 /*** Integer arithmetic ***/ 794 795 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 796 TCGv arg1, TCGv arg2, int sub) 797 { 798 TCGv t0 = tcg_temp_new(); 799 800 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 801 tcg_gen_xor_tl(t0, arg1, arg2); 802 if (sub) { 803 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 804 } else { 805 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 806 } 807 tcg_temp_free(t0); 808 if (NARROW_MODE(ctx)) { 809 tcg_gen_ext32s_tl(cpu_ov, cpu_ov); 810 } 811 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); 812 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 813 } 814 815 /* Common add function */ 816 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 817 TCGv arg2, bool add_ca, bool compute_ca, 818 bool compute_ov, bool compute_rc0) 819 { 820 TCGv t0 = ret; 821 822 if (compute_ca || compute_ov) { 823 t0 = tcg_temp_new(); 824 } 825 826 if (compute_ca) { 827 if (NARROW_MODE(ctx)) { 828 /* Caution: a non-obvious corner case of the spec is that we 829 must produce the *entire* 64-bit addition, but produce the 830 carry into bit 32. */ 831 TCGv t1 = tcg_temp_new(); 832 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 833 tcg_gen_add_tl(t0, arg1, arg2); 834 if (add_ca) { 835 tcg_gen_add_tl(t0, t0, cpu_ca); 836 } 837 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ 838 tcg_temp_free(t1); 839 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ 840 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); 841 } else { 842 TCGv zero = tcg_const_tl(0); 843 if (add_ca) { 844 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); 845 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); 846 } else { 847 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); 848 } 849 tcg_temp_free(zero); 850 } 851 } else { 852 tcg_gen_add_tl(t0, arg1, arg2); 853 if (add_ca) { 854 tcg_gen_add_tl(t0, t0, cpu_ca); 855 } 856 } 857 858 if (compute_ov) { 859 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 860 } 861 if (unlikely(compute_rc0)) { 862 gen_set_Rc0(ctx, t0); 863 } 864 865 if (!TCGV_EQUAL(t0, ret)) { 866 tcg_gen_mov_tl(ret, t0); 867 tcg_temp_free(t0); 868 } 869 } 870 /* Add functions with two operands */ 871 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 872 static void glue(gen_, name)(DisasContext *ctx) \ 873 { \ 874 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 875 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 876 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 877 } 878 /* Add functions with one operand and one immediate */ 879 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 880 add_ca, compute_ca, compute_ov) \ 881 static void glue(gen_, name)(DisasContext *ctx) \ 882 { \ 883 TCGv t0 = tcg_const_tl(const_val); \ 884 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 885 cpu_gpr[rA(ctx->opcode)], t0, \ 886 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 887 tcg_temp_free(t0); \ 888 } 889 890 /* add add. addo addo. */ 891 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 892 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 893 /* addc addc. addco addco. */ 894 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 895 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 896 /* adde adde. addeo addeo. */ 897 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 898 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 899 /* addme addme. addmeo addmeo. */ 900 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 901 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 902 /* addze addze. addzeo addzeo.*/ 903 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 904 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 905 /* addi */ 906 static void gen_addi(DisasContext *ctx) 907 { 908 target_long simm = SIMM(ctx->opcode); 909 910 if (rA(ctx->opcode) == 0) { 911 /* li case */ 912 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 913 } else { 914 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 915 cpu_gpr[rA(ctx->opcode)], simm); 916 } 917 } 918 /* addic addic.*/ 919 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 920 { 921 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 922 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 923 c, 0, 1, 0, compute_rc0); 924 tcg_temp_free(c); 925 } 926 927 static void gen_addic(DisasContext *ctx) 928 { 929 gen_op_addic(ctx, 0); 930 } 931 932 static void gen_addic_(DisasContext *ctx) 933 { 934 gen_op_addic(ctx, 1); 935 } 936 937 /* addis */ 938 static void gen_addis(DisasContext *ctx) 939 { 940 target_long simm = SIMM(ctx->opcode); 941 942 if (rA(ctx->opcode) == 0) { 943 /* lis case */ 944 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 945 } else { 946 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 947 cpu_gpr[rA(ctx->opcode)], simm << 16); 948 } 949 } 950 951 /* addpcis */ 952 static void gen_addpcis(DisasContext *ctx) 953 { 954 target_long d = DX(ctx->opcode); 955 956 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16)); 957 } 958 959 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 960 TCGv arg2, int sign, int compute_ov) 961 { 962 TCGv_i32 t0 = tcg_temp_new_i32(); 963 TCGv_i32 t1 = tcg_temp_new_i32(); 964 TCGv_i32 t2 = tcg_temp_new_i32(); 965 TCGv_i32 t3 = tcg_temp_new_i32(); 966 967 tcg_gen_trunc_tl_i32(t0, arg1); 968 tcg_gen_trunc_tl_i32(t1, arg2); 969 if (sign) { 970 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 971 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 972 tcg_gen_and_i32(t2, t2, t3); 973 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 974 tcg_gen_or_i32(t2, t2, t3); 975 tcg_gen_movi_i32(t3, 0); 976 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 977 tcg_gen_div_i32(t3, t0, t1); 978 tcg_gen_extu_i32_tl(ret, t3); 979 } else { 980 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 981 tcg_gen_movi_i32(t3, 0); 982 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 983 tcg_gen_divu_i32(t3, t0, t1); 984 tcg_gen_extu_i32_tl(ret, t3); 985 } 986 if (compute_ov) { 987 tcg_gen_extu_i32_tl(cpu_ov, t2); 988 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 989 } 990 tcg_temp_free_i32(t0); 991 tcg_temp_free_i32(t1); 992 tcg_temp_free_i32(t2); 993 tcg_temp_free_i32(t3); 994 995 if (unlikely(Rc(ctx->opcode) != 0)) 996 gen_set_Rc0(ctx, ret); 997 } 998 /* Div functions */ 999 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1000 static void glue(gen_, name)(DisasContext *ctx) \ 1001 { \ 1002 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1004 sign, compute_ov); \ 1005 } 1006 /* divwu divwu. divwuo divwuo. */ 1007 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1008 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1009 /* divw divw. divwo divwo. */ 1010 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1011 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1012 1013 /* div[wd]eu[o][.] */ 1014 #define GEN_DIVE(name, hlpr, compute_ov) \ 1015 static void gen_##name(DisasContext *ctx) \ 1016 { \ 1017 TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1018 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1019 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1020 tcg_temp_free_i32(t0); \ 1021 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1022 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1023 } \ 1024 } 1025 1026 GEN_DIVE(divweu, divweu, 0); 1027 GEN_DIVE(divweuo, divweu, 1); 1028 GEN_DIVE(divwe, divwe, 0); 1029 GEN_DIVE(divweo, divwe, 1); 1030 1031 #if defined(TARGET_PPC64) 1032 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1033 TCGv arg2, int sign, int compute_ov) 1034 { 1035 TCGv_i64 t0 = tcg_temp_new_i64(); 1036 TCGv_i64 t1 = tcg_temp_new_i64(); 1037 TCGv_i64 t2 = tcg_temp_new_i64(); 1038 TCGv_i64 t3 = tcg_temp_new_i64(); 1039 1040 tcg_gen_mov_i64(t0, arg1); 1041 tcg_gen_mov_i64(t1, arg2); 1042 if (sign) { 1043 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1044 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1045 tcg_gen_and_i64(t2, t2, t3); 1046 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1047 tcg_gen_or_i64(t2, t2, t3); 1048 tcg_gen_movi_i64(t3, 0); 1049 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1050 tcg_gen_div_i64(ret, t0, t1); 1051 } else { 1052 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1053 tcg_gen_movi_i64(t3, 0); 1054 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1055 tcg_gen_divu_i64(ret, t0, t1); 1056 } 1057 if (compute_ov) { 1058 tcg_gen_mov_tl(cpu_ov, t2); 1059 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1060 } 1061 tcg_temp_free_i64(t0); 1062 tcg_temp_free_i64(t1); 1063 tcg_temp_free_i64(t2); 1064 tcg_temp_free_i64(t3); 1065 1066 if (unlikely(Rc(ctx->opcode) != 0)) 1067 gen_set_Rc0(ctx, ret); 1068 } 1069 1070 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1071 static void glue(gen_, name)(DisasContext *ctx) \ 1072 { \ 1073 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1074 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1075 sign, compute_ov); \ 1076 } 1077 /* divwu divwu. divwuo divwuo. */ 1078 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1079 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1080 /* divw divw. divwo divwo. */ 1081 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1082 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1083 1084 GEN_DIVE(divdeu, divdeu, 0); 1085 GEN_DIVE(divdeuo, divdeu, 1); 1086 GEN_DIVE(divde, divde, 0); 1087 GEN_DIVE(divdeo, divde, 1); 1088 #endif 1089 1090 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1091 TCGv arg2, int sign) 1092 { 1093 TCGv_i32 t0 = tcg_temp_new_i32(); 1094 TCGv_i32 t1 = tcg_temp_new_i32(); 1095 1096 tcg_gen_trunc_tl_i32(t0, arg1); 1097 tcg_gen_trunc_tl_i32(t1, arg2); 1098 if (sign) { 1099 TCGv_i32 t2 = tcg_temp_new_i32(); 1100 TCGv_i32 t3 = tcg_temp_new_i32(); 1101 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1102 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1103 tcg_gen_and_i32(t2, t2, t3); 1104 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1105 tcg_gen_or_i32(t2, t2, t3); 1106 tcg_gen_movi_i32(t3, 0); 1107 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1108 tcg_gen_rem_i32(t3, t0, t1); 1109 tcg_gen_ext_i32_tl(ret, t3); 1110 tcg_temp_free_i32(t2); 1111 tcg_temp_free_i32(t3); 1112 } else { 1113 TCGv_i32 t2 = tcg_const_i32(1); 1114 TCGv_i32 t3 = tcg_const_i32(0); 1115 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1116 tcg_gen_remu_i32(t3, t0, t1); 1117 tcg_gen_extu_i32_tl(ret, t3); 1118 tcg_temp_free_i32(t2); 1119 tcg_temp_free_i32(t3); 1120 } 1121 tcg_temp_free_i32(t0); 1122 tcg_temp_free_i32(t1); 1123 } 1124 1125 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1126 static void glue(gen_, name)(DisasContext *ctx) \ 1127 { \ 1128 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1129 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1130 sign); \ 1131 } 1132 1133 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1134 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1135 1136 #if defined(TARGET_PPC64) 1137 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1138 TCGv arg2, int sign) 1139 { 1140 TCGv_i64 t0 = tcg_temp_new_i64(); 1141 TCGv_i64 t1 = tcg_temp_new_i64(); 1142 1143 tcg_gen_mov_i64(t0, arg1); 1144 tcg_gen_mov_i64(t1, arg2); 1145 if (sign) { 1146 TCGv_i64 t2 = tcg_temp_new_i64(); 1147 TCGv_i64 t3 = tcg_temp_new_i64(); 1148 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1149 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1150 tcg_gen_and_i64(t2, t2, t3); 1151 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1152 tcg_gen_or_i64(t2, t2, t3); 1153 tcg_gen_movi_i64(t3, 0); 1154 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1155 tcg_gen_rem_i64(ret, t0, t1); 1156 tcg_temp_free_i64(t2); 1157 tcg_temp_free_i64(t3); 1158 } else { 1159 TCGv_i64 t2 = tcg_const_i64(1); 1160 TCGv_i64 t3 = tcg_const_i64(0); 1161 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1162 tcg_gen_remu_i64(ret, t0, t1); 1163 tcg_temp_free_i64(t2); 1164 tcg_temp_free_i64(t3); 1165 } 1166 tcg_temp_free_i64(t0); 1167 tcg_temp_free_i64(t1); 1168 } 1169 1170 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1171 static void glue(gen_, name)(DisasContext *ctx) \ 1172 { \ 1173 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1174 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1175 sign); \ 1176 } 1177 1178 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1179 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1180 #endif 1181 1182 /* mulhw mulhw. */ 1183 static void gen_mulhw(DisasContext *ctx) 1184 { 1185 TCGv_i32 t0 = tcg_temp_new_i32(); 1186 TCGv_i32 t1 = tcg_temp_new_i32(); 1187 1188 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1189 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1190 tcg_gen_muls2_i32(t0, t1, t0, t1); 1191 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1192 tcg_temp_free_i32(t0); 1193 tcg_temp_free_i32(t1); 1194 if (unlikely(Rc(ctx->opcode) != 0)) 1195 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1196 } 1197 1198 /* mulhwu mulhwu. */ 1199 static void gen_mulhwu(DisasContext *ctx) 1200 { 1201 TCGv_i32 t0 = tcg_temp_new_i32(); 1202 TCGv_i32 t1 = tcg_temp_new_i32(); 1203 1204 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1205 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1206 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1207 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1208 tcg_temp_free_i32(t0); 1209 tcg_temp_free_i32(t1); 1210 if (unlikely(Rc(ctx->opcode) != 0)) 1211 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1212 } 1213 1214 /* mullw mullw. */ 1215 static void gen_mullw(DisasContext *ctx) 1216 { 1217 #if defined(TARGET_PPC64) 1218 TCGv_i64 t0, t1; 1219 t0 = tcg_temp_new_i64(); 1220 t1 = tcg_temp_new_i64(); 1221 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1222 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1223 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1224 tcg_temp_free(t0); 1225 tcg_temp_free(t1); 1226 #else 1227 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1228 cpu_gpr[rB(ctx->opcode)]); 1229 #endif 1230 if (unlikely(Rc(ctx->opcode) != 0)) 1231 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1232 } 1233 1234 /* mullwo mullwo. */ 1235 static void gen_mullwo(DisasContext *ctx) 1236 { 1237 TCGv_i32 t0 = tcg_temp_new_i32(); 1238 TCGv_i32 t1 = tcg_temp_new_i32(); 1239 1240 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1241 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1242 tcg_gen_muls2_i32(t0, t1, t0, t1); 1243 #if defined(TARGET_PPC64) 1244 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1245 #else 1246 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1247 #endif 1248 1249 tcg_gen_sari_i32(t0, t0, 31); 1250 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1251 tcg_gen_extu_i32_tl(cpu_ov, t0); 1252 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1253 1254 tcg_temp_free_i32(t0); 1255 tcg_temp_free_i32(t1); 1256 if (unlikely(Rc(ctx->opcode) != 0)) 1257 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1258 } 1259 1260 /* mulli */ 1261 static void gen_mulli(DisasContext *ctx) 1262 { 1263 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1264 SIMM(ctx->opcode)); 1265 } 1266 1267 #if defined(TARGET_PPC64) 1268 /* mulhd mulhd. */ 1269 static void gen_mulhd(DisasContext *ctx) 1270 { 1271 TCGv lo = tcg_temp_new(); 1272 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1273 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1274 tcg_temp_free(lo); 1275 if (unlikely(Rc(ctx->opcode) != 0)) { 1276 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1277 } 1278 } 1279 1280 /* mulhdu mulhdu. */ 1281 static void gen_mulhdu(DisasContext *ctx) 1282 { 1283 TCGv lo = tcg_temp_new(); 1284 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1285 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1286 tcg_temp_free(lo); 1287 if (unlikely(Rc(ctx->opcode) != 0)) { 1288 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1289 } 1290 } 1291 1292 /* mulld mulld. */ 1293 static void gen_mulld(DisasContext *ctx) 1294 { 1295 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1296 cpu_gpr[rB(ctx->opcode)]); 1297 if (unlikely(Rc(ctx->opcode) != 0)) 1298 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1299 } 1300 1301 /* mulldo mulldo. */ 1302 static void gen_mulldo(DisasContext *ctx) 1303 { 1304 TCGv_i64 t0 = tcg_temp_new_i64(); 1305 TCGv_i64 t1 = tcg_temp_new_i64(); 1306 1307 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1308 cpu_gpr[rB(ctx->opcode)]); 1309 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1310 1311 tcg_gen_sari_i64(t0, t0, 63); 1312 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 1313 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1314 1315 tcg_temp_free_i64(t0); 1316 tcg_temp_free_i64(t1); 1317 1318 if (unlikely(Rc(ctx->opcode) != 0)) { 1319 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1320 } 1321 } 1322 #endif 1323 1324 /* Common subf function */ 1325 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1326 TCGv arg2, bool add_ca, bool compute_ca, 1327 bool compute_ov, bool compute_rc0) 1328 { 1329 TCGv t0 = ret; 1330 1331 if (compute_ca || compute_ov) { 1332 t0 = tcg_temp_new(); 1333 } 1334 1335 if (compute_ca) { 1336 /* dest = ~arg1 + arg2 [+ ca]. */ 1337 if (NARROW_MODE(ctx)) { 1338 /* Caution: a non-obvious corner case of the spec is that we 1339 must produce the *entire* 64-bit addition, but produce the 1340 carry into bit 32. */ 1341 TCGv inv1 = tcg_temp_new(); 1342 TCGv t1 = tcg_temp_new(); 1343 tcg_gen_not_tl(inv1, arg1); 1344 if (add_ca) { 1345 tcg_gen_add_tl(t0, arg2, cpu_ca); 1346 } else { 1347 tcg_gen_addi_tl(t0, arg2, 1); 1348 } 1349 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1350 tcg_gen_add_tl(t0, t0, inv1); 1351 tcg_temp_free(inv1); 1352 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1353 tcg_temp_free(t1); 1354 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ 1355 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); 1356 } else if (add_ca) { 1357 TCGv zero, inv1 = tcg_temp_new(); 1358 tcg_gen_not_tl(inv1, arg1); 1359 zero = tcg_const_tl(0); 1360 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1361 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 1362 tcg_temp_free(zero); 1363 tcg_temp_free(inv1); 1364 } else { 1365 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1366 tcg_gen_sub_tl(t0, arg2, arg1); 1367 } 1368 } else if (add_ca) { 1369 /* Since we're ignoring carry-out, we can simplify the 1370 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ 1371 tcg_gen_sub_tl(t0, arg2, arg1); 1372 tcg_gen_add_tl(t0, t0, cpu_ca); 1373 tcg_gen_subi_tl(t0, t0, 1); 1374 } else { 1375 tcg_gen_sub_tl(t0, arg2, arg1); 1376 } 1377 1378 if (compute_ov) { 1379 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1380 } 1381 if (unlikely(compute_rc0)) { 1382 gen_set_Rc0(ctx, t0); 1383 } 1384 1385 if (!TCGV_EQUAL(t0, ret)) { 1386 tcg_gen_mov_tl(ret, t0); 1387 tcg_temp_free(t0); 1388 } 1389 } 1390 /* Sub functions with Two operands functions */ 1391 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1392 static void glue(gen_, name)(DisasContext *ctx) \ 1393 { \ 1394 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1395 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1396 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1397 } 1398 /* Sub functions with one operand and one immediate */ 1399 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1400 add_ca, compute_ca, compute_ov) \ 1401 static void glue(gen_, name)(DisasContext *ctx) \ 1402 { \ 1403 TCGv t0 = tcg_const_tl(const_val); \ 1404 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1405 cpu_gpr[rA(ctx->opcode)], t0, \ 1406 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1407 tcg_temp_free(t0); \ 1408 } 1409 /* subf subf. subfo subfo. */ 1410 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1411 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1412 /* subfc subfc. subfco subfco. */ 1413 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1414 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1415 /* subfe subfe. subfeo subfo. */ 1416 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1417 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1418 /* subfme subfme. subfmeo subfmeo. */ 1419 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1420 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1421 /* subfze subfze. subfzeo subfzeo.*/ 1422 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1423 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1424 1425 /* subfic */ 1426 static void gen_subfic(DisasContext *ctx) 1427 { 1428 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1429 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1430 c, 0, 1, 0, 0); 1431 tcg_temp_free(c); 1432 } 1433 1434 /* neg neg. nego nego. */ 1435 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1436 { 1437 TCGv zero = tcg_const_tl(0); 1438 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1439 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1440 tcg_temp_free(zero); 1441 } 1442 1443 static void gen_neg(DisasContext *ctx) 1444 { 1445 gen_op_arith_neg(ctx, 0); 1446 } 1447 1448 static void gen_nego(DisasContext *ctx) 1449 { 1450 gen_op_arith_neg(ctx, 1); 1451 } 1452 1453 /*** Integer logical ***/ 1454 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1455 static void glue(gen_, name)(DisasContext *ctx) \ 1456 { \ 1457 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1458 cpu_gpr[rB(ctx->opcode)]); \ 1459 if (unlikely(Rc(ctx->opcode) != 0)) \ 1460 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1461 } 1462 1463 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1464 static void glue(gen_, name)(DisasContext *ctx) \ 1465 { \ 1466 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1467 if (unlikely(Rc(ctx->opcode) != 0)) \ 1468 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1469 } 1470 1471 /* and & and. */ 1472 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1473 /* andc & andc. */ 1474 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1475 1476 /* andi. */ 1477 static void gen_andi_(DisasContext *ctx) 1478 { 1479 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); 1480 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1481 } 1482 1483 /* andis. */ 1484 static void gen_andis_(DisasContext *ctx) 1485 { 1486 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); 1487 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1488 } 1489 1490 /* cntlzw */ 1491 static void gen_cntlzw(DisasContext *ctx) 1492 { 1493 TCGv_i32 t = tcg_temp_new_i32(); 1494 1495 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1496 tcg_gen_clzi_i32(t, t, 32); 1497 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1498 tcg_temp_free_i32(t); 1499 1500 if (unlikely(Rc(ctx->opcode) != 0)) 1501 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1502 } 1503 1504 /* cnttzw */ 1505 static void gen_cnttzw(DisasContext *ctx) 1506 { 1507 TCGv_i32 t = tcg_temp_new_i32(); 1508 1509 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1510 tcg_gen_ctzi_i32(t, t, 32); 1511 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1512 tcg_temp_free_i32(t); 1513 1514 if (unlikely(Rc(ctx->opcode) != 0)) { 1515 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1516 } 1517 } 1518 1519 /* eqv & eqv. */ 1520 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1521 /* extsb & extsb. */ 1522 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1523 /* extsh & extsh. */ 1524 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1525 /* nand & nand. */ 1526 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1527 /* nor & nor. */ 1528 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1529 1530 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1531 static void gen_pause(DisasContext *ctx) 1532 { 1533 TCGv_i32 t0 = tcg_const_i32(0); 1534 tcg_gen_st_i32(t0, cpu_env, 1535 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1536 tcg_temp_free_i32(t0); 1537 1538 /* Stop translation, this gives other CPUs a chance to run */ 1539 gen_exception_nip(ctx, EXCP_HLT, ctx->nip); 1540 } 1541 #endif /* defined(TARGET_PPC64) */ 1542 1543 /* or & or. */ 1544 static void gen_or(DisasContext *ctx) 1545 { 1546 int rs, ra, rb; 1547 1548 rs = rS(ctx->opcode); 1549 ra = rA(ctx->opcode); 1550 rb = rB(ctx->opcode); 1551 /* Optimisation for mr. ri case */ 1552 if (rs != ra || rs != rb) { 1553 if (rs != rb) 1554 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1555 else 1556 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1557 if (unlikely(Rc(ctx->opcode) != 0)) 1558 gen_set_Rc0(ctx, cpu_gpr[ra]); 1559 } else if (unlikely(Rc(ctx->opcode) != 0)) { 1560 gen_set_Rc0(ctx, cpu_gpr[rs]); 1561 #if defined(TARGET_PPC64) 1562 } else if (rs != 0) { /* 0 is nop */ 1563 int prio = 0; 1564 1565 switch (rs) { 1566 case 1: 1567 /* Set process priority to low */ 1568 prio = 2; 1569 break; 1570 case 6: 1571 /* Set process priority to medium-low */ 1572 prio = 3; 1573 break; 1574 case 2: 1575 /* Set process priority to normal */ 1576 prio = 4; 1577 break; 1578 #if !defined(CONFIG_USER_ONLY) 1579 case 31: 1580 if (!ctx->pr) { 1581 /* Set process priority to very low */ 1582 prio = 1; 1583 } 1584 break; 1585 case 5: 1586 if (!ctx->pr) { 1587 /* Set process priority to medium-hight */ 1588 prio = 5; 1589 } 1590 break; 1591 case 3: 1592 if (!ctx->pr) { 1593 /* Set process priority to high */ 1594 prio = 6; 1595 } 1596 break; 1597 case 7: 1598 if (ctx->hv && !ctx->pr) { 1599 /* Set process priority to very high */ 1600 prio = 7; 1601 } 1602 break; 1603 #endif 1604 default: 1605 break; 1606 } 1607 if (prio) { 1608 TCGv t0 = tcg_temp_new(); 1609 gen_load_spr(t0, SPR_PPR); 1610 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1611 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1612 gen_store_spr(SPR_PPR, t0); 1613 tcg_temp_free(t0); 1614 } 1615 #if !defined(CONFIG_USER_ONLY) 1616 /* Pause out of TCG otherwise spin loops with smt_low eat too much 1617 * CPU and the kernel hangs. This applies to all encodings other 1618 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), 1619 * and all currently undefined. 1620 */ 1621 gen_pause(ctx); 1622 #endif 1623 #endif 1624 } 1625 } 1626 /* orc & orc. */ 1627 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1628 1629 /* xor & xor. */ 1630 static void gen_xor(DisasContext *ctx) 1631 { 1632 /* Optimisation for "set to zero" case */ 1633 if (rS(ctx->opcode) != rB(ctx->opcode)) 1634 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1635 else 1636 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1637 if (unlikely(Rc(ctx->opcode) != 0)) 1638 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1639 } 1640 1641 /* ori */ 1642 static void gen_ori(DisasContext *ctx) 1643 { 1644 target_ulong uimm = UIMM(ctx->opcode); 1645 1646 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1647 return; 1648 } 1649 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1650 } 1651 1652 /* oris */ 1653 static void gen_oris(DisasContext *ctx) 1654 { 1655 target_ulong uimm = UIMM(ctx->opcode); 1656 1657 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1658 /* NOP */ 1659 return; 1660 } 1661 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1662 } 1663 1664 /* xori */ 1665 static void gen_xori(DisasContext *ctx) 1666 { 1667 target_ulong uimm = UIMM(ctx->opcode); 1668 1669 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1670 /* NOP */ 1671 return; 1672 } 1673 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1674 } 1675 1676 /* xoris */ 1677 static void gen_xoris(DisasContext *ctx) 1678 { 1679 target_ulong uimm = UIMM(ctx->opcode); 1680 1681 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1682 /* NOP */ 1683 return; 1684 } 1685 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1686 } 1687 1688 /* popcntb : PowerPC 2.03 specification */ 1689 static void gen_popcntb(DisasContext *ctx) 1690 { 1691 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1692 } 1693 1694 static void gen_popcntw(DisasContext *ctx) 1695 { 1696 #if defined(TARGET_PPC64) 1697 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1698 #else 1699 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1700 #endif 1701 } 1702 1703 #if defined(TARGET_PPC64) 1704 /* popcntd: PowerPC 2.06 specification */ 1705 static void gen_popcntd(DisasContext *ctx) 1706 { 1707 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1708 } 1709 #endif 1710 1711 /* prtyw: PowerPC 2.05 specification */ 1712 static void gen_prtyw(DisasContext *ctx) 1713 { 1714 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1715 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1716 TCGv t0 = tcg_temp_new(); 1717 tcg_gen_shri_tl(t0, rs, 16); 1718 tcg_gen_xor_tl(ra, rs, t0); 1719 tcg_gen_shri_tl(t0, ra, 8); 1720 tcg_gen_xor_tl(ra, ra, t0); 1721 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1722 tcg_temp_free(t0); 1723 } 1724 1725 #if defined(TARGET_PPC64) 1726 /* prtyd: PowerPC 2.05 specification */ 1727 static void gen_prtyd(DisasContext *ctx) 1728 { 1729 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1730 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1731 TCGv t0 = tcg_temp_new(); 1732 tcg_gen_shri_tl(t0, rs, 32); 1733 tcg_gen_xor_tl(ra, rs, t0); 1734 tcg_gen_shri_tl(t0, ra, 16); 1735 tcg_gen_xor_tl(ra, ra, t0); 1736 tcg_gen_shri_tl(t0, ra, 8); 1737 tcg_gen_xor_tl(ra, ra, t0); 1738 tcg_gen_andi_tl(ra, ra, 1); 1739 tcg_temp_free(t0); 1740 } 1741 #endif 1742 1743 #if defined(TARGET_PPC64) 1744 /* bpermd */ 1745 static void gen_bpermd(DisasContext *ctx) 1746 { 1747 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1748 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1749 } 1750 #endif 1751 1752 #if defined(TARGET_PPC64) 1753 /* extsw & extsw. */ 1754 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1755 1756 /* cntlzd */ 1757 static void gen_cntlzd(DisasContext *ctx) 1758 { 1759 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1760 if (unlikely(Rc(ctx->opcode) != 0)) 1761 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1762 } 1763 1764 /* cnttzd */ 1765 static void gen_cnttzd(DisasContext *ctx) 1766 { 1767 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1768 if (unlikely(Rc(ctx->opcode) != 0)) { 1769 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1770 } 1771 } 1772 1773 /* darn */ 1774 static void gen_darn(DisasContext *ctx) 1775 { 1776 int l = L(ctx->opcode); 1777 1778 if (l == 0) { 1779 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1780 } else if (l <= 2) { 1781 /* Return 64-bit random for both CRN and RRN */ 1782 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1783 } else { 1784 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1785 } 1786 } 1787 #endif 1788 1789 /*** Integer rotate ***/ 1790 1791 /* rlwimi & rlwimi. */ 1792 static void gen_rlwimi(DisasContext *ctx) 1793 { 1794 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1795 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1796 uint32_t sh = SH(ctx->opcode); 1797 uint32_t mb = MB(ctx->opcode); 1798 uint32_t me = ME(ctx->opcode); 1799 1800 if (sh == (31-me) && mb <= me) { 1801 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1802 } else { 1803 target_ulong mask; 1804 TCGv t1; 1805 1806 #if defined(TARGET_PPC64) 1807 mb += 32; 1808 me += 32; 1809 #endif 1810 mask = MASK(mb, me); 1811 1812 t1 = tcg_temp_new(); 1813 if (mask <= 0xffffffffu) { 1814 TCGv_i32 t0 = tcg_temp_new_i32(); 1815 tcg_gen_trunc_tl_i32(t0, t_rs); 1816 tcg_gen_rotli_i32(t0, t0, sh); 1817 tcg_gen_extu_i32_tl(t1, t0); 1818 tcg_temp_free_i32(t0); 1819 } else { 1820 #if defined(TARGET_PPC64) 1821 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1822 tcg_gen_rotli_i64(t1, t1, sh); 1823 #else 1824 g_assert_not_reached(); 1825 #endif 1826 } 1827 1828 tcg_gen_andi_tl(t1, t1, mask); 1829 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1830 tcg_gen_or_tl(t_ra, t_ra, t1); 1831 tcg_temp_free(t1); 1832 } 1833 if (unlikely(Rc(ctx->opcode) != 0)) { 1834 gen_set_Rc0(ctx, t_ra); 1835 } 1836 } 1837 1838 /* rlwinm & rlwinm. */ 1839 static void gen_rlwinm(DisasContext *ctx) 1840 { 1841 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1842 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1843 int sh = SH(ctx->opcode); 1844 int mb = MB(ctx->opcode); 1845 int me = ME(ctx->opcode); 1846 int len = me - mb + 1; 1847 int rsh = (32 - sh) & 31; 1848 1849 if (sh != 0 && len > 0 && me == (31 - sh)) { 1850 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 1851 } else if (me == 31 && rsh + len <= 32) { 1852 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1853 } else { 1854 target_ulong mask; 1855 #if defined(TARGET_PPC64) 1856 mb += 32; 1857 me += 32; 1858 #endif 1859 mask = MASK(mb, me); 1860 if (sh == 0) { 1861 tcg_gen_andi_tl(t_ra, t_rs, mask); 1862 } else if (mask <= 0xffffffffu) { 1863 TCGv_i32 t0 = tcg_temp_new_i32(); 1864 tcg_gen_trunc_tl_i32(t0, t_rs); 1865 tcg_gen_rotli_i32(t0, t0, sh); 1866 tcg_gen_andi_i32(t0, t0, mask); 1867 tcg_gen_extu_i32_tl(t_ra, t0); 1868 tcg_temp_free_i32(t0); 1869 } else { 1870 #if defined(TARGET_PPC64) 1871 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1872 tcg_gen_rotli_i64(t_ra, t_ra, sh); 1873 tcg_gen_andi_i64(t_ra, t_ra, mask); 1874 #else 1875 g_assert_not_reached(); 1876 #endif 1877 } 1878 } 1879 if (unlikely(Rc(ctx->opcode) != 0)) { 1880 gen_set_Rc0(ctx, t_ra); 1881 } 1882 } 1883 1884 /* rlwnm & rlwnm. */ 1885 static void gen_rlwnm(DisasContext *ctx) 1886 { 1887 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1888 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1889 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1890 uint32_t mb = MB(ctx->opcode); 1891 uint32_t me = ME(ctx->opcode); 1892 target_ulong mask; 1893 1894 #if defined(TARGET_PPC64) 1895 mb += 32; 1896 me += 32; 1897 #endif 1898 mask = MASK(mb, me); 1899 1900 if (mask <= 0xffffffffu) { 1901 TCGv_i32 t0 = tcg_temp_new_i32(); 1902 TCGv_i32 t1 = tcg_temp_new_i32(); 1903 tcg_gen_trunc_tl_i32(t0, t_rb); 1904 tcg_gen_trunc_tl_i32(t1, t_rs); 1905 tcg_gen_andi_i32(t0, t0, 0x1f); 1906 tcg_gen_rotl_i32(t1, t1, t0); 1907 tcg_gen_extu_i32_tl(t_ra, t1); 1908 tcg_temp_free_i32(t0); 1909 tcg_temp_free_i32(t1); 1910 } else { 1911 #if defined(TARGET_PPC64) 1912 TCGv_i64 t0 = tcg_temp_new_i64(); 1913 tcg_gen_andi_i64(t0, t_rb, 0x1f); 1914 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1915 tcg_gen_rotl_i64(t_ra, t_ra, t0); 1916 tcg_temp_free_i64(t0); 1917 #else 1918 g_assert_not_reached(); 1919 #endif 1920 } 1921 1922 tcg_gen_andi_tl(t_ra, t_ra, mask); 1923 1924 if (unlikely(Rc(ctx->opcode) != 0)) { 1925 gen_set_Rc0(ctx, t_ra); 1926 } 1927 } 1928 1929 #if defined(TARGET_PPC64) 1930 #define GEN_PPC64_R2(name, opc1, opc2) \ 1931 static void glue(gen_, name##0)(DisasContext *ctx) \ 1932 { \ 1933 gen_##name(ctx, 0); \ 1934 } \ 1935 \ 1936 static void glue(gen_, name##1)(DisasContext *ctx) \ 1937 { \ 1938 gen_##name(ctx, 1); \ 1939 } 1940 #define GEN_PPC64_R4(name, opc1, opc2) \ 1941 static void glue(gen_, name##0)(DisasContext *ctx) \ 1942 { \ 1943 gen_##name(ctx, 0, 0); \ 1944 } \ 1945 \ 1946 static void glue(gen_, name##1)(DisasContext *ctx) \ 1947 { \ 1948 gen_##name(ctx, 0, 1); \ 1949 } \ 1950 \ 1951 static void glue(gen_, name##2)(DisasContext *ctx) \ 1952 { \ 1953 gen_##name(ctx, 1, 0); \ 1954 } \ 1955 \ 1956 static void glue(gen_, name##3)(DisasContext *ctx) \ 1957 { \ 1958 gen_##name(ctx, 1, 1); \ 1959 } 1960 1961 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 1962 { 1963 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1964 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1965 int len = me - mb + 1; 1966 int rsh = (64 - sh) & 63; 1967 1968 if (sh != 0 && len > 0 && me == (63 - sh)) { 1969 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 1970 } else if (me == 63 && rsh + len <= 64) { 1971 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1972 } else { 1973 tcg_gen_rotli_tl(t_ra, t_rs, sh); 1974 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 1975 } 1976 if (unlikely(Rc(ctx->opcode) != 0)) { 1977 gen_set_Rc0(ctx, t_ra); 1978 } 1979 } 1980 1981 /* rldicl - rldicl. */ 1982 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 1983 { 1984 uint32_t sh, mb; 1985 1986 sh = SH(ctx->opcode) | (shn << 5); 1987 mb = MB(ctx->opcode) | (mbn << 5); 1988 gen_rldinm(ctx, mb, 63, sh); 1989 } 1990 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 1991 1992 /* rldicr - rldicr. */ 1993 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 1994 { 1995 uint32_t sh, me; 1996 1997 sh = SH(ctx->opcode) | (shn << 5); 1998 me = MB(ctx->opcode) | (men << 5); 1999 gen_rldinm(ctx, 0, me, sh); 2000 } 2001 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2002 2003 /* rldic - rldic. */ 2004 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2005 { 2006 uint32_t sh, mb; 2007 2008 sh = SH(ctx->opcode) | (shn << 5); 2009 mb = MB(ctx->opcode) | (mbn << 5); 2010 gen_rldinm(ctx, mb, 63 - sh, sh); 2011 } 2012 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2013 2014 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2015 { 2016 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2017 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2018 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2019 TCGv t0; 2020 2021 t0 = tcg_temp_new(); 2022 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2023 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2024 tcg_temp_free(t0); 2025 2026 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2027 if (unlikely(Rc(ctx->opcode) != 0)) { 2028 gen_set_Rc0(ctx, t_ra); 2029 } 2030 } 2031 2032 /* rldcl - rldcl. */ 2033 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2034 { 2035 uint32_t mb; 2036 2037 mb = MB(ctx->opcode) | (mbn << 5); 2038 gen_rldnm(ctx, mb, 63); 2039 } 2040 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2041 2042 /* rldcr - rldcr. */ 2043 static inline void gen_rldcr(DisasContext *ctx, int men) 2044 { 2045 uint32_t me; 2046 2047 me = MB(ctx->opcode) | (men << 5); 2048 gen_rldnm(ctx, 0, me); 2049 } 2050 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2051 2052 /* rldimi - rldimi. */ 2053 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2054 { 2055 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2056 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2057 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2058 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2059 uint32_t me = 63 - sh; 2060 2061 if (mb <= me) { 2062 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2063 } else { 2064 target_ulong mask = MASK(mb, me); 2065 TCGv t1 = tcg_temp_new(); 2066 2067 tcg_gen_rotli_tl(t1, t_rs, sh); 2068 tcg_gen_andi_tl(t1, t1, mask); 2069 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2070 tcg_gen_or_tl(t_ra, t_ra, t1); 2071 tcg_temp_free(t1); 2072 } 2073 if (unlikely(Rc(ctx->opcode) != 0)) { 2074 gen_set_Rc0(ctx, t_ra); 2075 } 2076 } 2077 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2078 #endif 2079 2080 /*** Integer shift ***/ 2081 2082 /* slw & slw. */ 2083 static void gen_slw(DisasContext *ctx) 2084 { 2085 TCGv t0, t1; 2086 2087 t0 = tcg_temp_new(); 2088 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2089 #if defined(TARGET_PPC64) 2090 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2091 tcg_gen_sari_tl(t0, t0, 0x3f); 2092 #else 2093 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2094 tcg_gen_sari_tl(t0, t0, 0x1f); 2095 #endif 2096 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2097 t1 = tcg_temp_new(); 2098 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2099 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2100 tcg_temp_free(t1); 2101 tcg_temp_free(t0); 2102 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2103 if (unlikely(Rc(ctx->opcode) != 0)) 2104 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2105 } 2106 2107 /* sraw & sraw. */ 2108 static void gen_sraw(DisasContext *ctx) 2109 { 2110 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2111 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2112 if (unlikely(Rc(ctx->opcode) != 0)) 2113 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2114 } 2115 2116 /* srawi & srawi. */ 2117 static void gen_srawi(DisasContext *ctx) 2118 { 2119 int sh = SH(ctx->opcode); 2120 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2121 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2122 if (sh == 0) { 2123 tcg_gen_ext32s_tl(dst, src); 2124 tcg_gen_movi_tl(cpu_ca, 0); 2125 } else { 2126 TCGv t0; 2127 tcg_gen_ext32s_tl(dst, src); 2128 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2129 t0 = tcg_temp_new(); 2130 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2131 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2132 tcg_temp_free(t0); 2133 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2134 tcg_gen_sari_tl(dst, dst, sh); 2135 } 2136 if (unlikely(Rc(ctx->opcode) != 0)) { 2137 gen_set_Rc0(ctx, dst); 2138 } 2139 } 2140 2141 /* srw & srw. */ 2142 static void gen_srw(DisasContext *ctx) 2143 { 2144 TCGv t0, t1; 2145 2146 t0 = tcg_temp_new(); 2147 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2148 #if defined(TARGET_PPC64) 2149 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2150 tcg_gen_sari_tl(t0, t0, 0x3f); 2151 #else 2152 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2153 tcg_gen_sari_tl(t0, t0, 0x1f); 2154 #endif 2155 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2156 tcg_gen_ext32u_tl(t0, t0); 2157 t1 = tcg_temp_new(); 2158 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2159 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2160 tcg_temp_free(t1); 2161 tcg_temp_free(t0); 2162 if (unlikely(Rc(ctx->opcode) != 0)) 2163 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2164 } 2165 2166 #if defined(TARGET_PPC64) 2167 /* sld & sld. */ 2168 static void gen_sld(DisasContext *ctx) 2169 { 2170 TCGv t0, t1; 2171 2172 t0 = tcg_temp_new(); 2173 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2174 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2175 tcg_gen_sari_tl(t0, t0, 0x3f); 2176 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2177 t1 = tcg_temp_new(); 2178 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2179 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2180 tcg_temp_free(t1); 2181 tcg_temp_free(t0); 2182 if (unlikely(Rc(ctx->opcode) != 0)) 2183 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2184 } 2185 2186 /* srad & srad. */ 2187 static void gen_srad(DisasContext *ctx) 2188 { 2189 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2190 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2191 if (unlikely(Rc(ctx->opcode) != 0)) 2192 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2193 } 2194 /* sradi & sradi. */ 2195 static inline void gen_sradi(DisasContext *ctx, int n) 2196 { 2197 int sh = SH(ctx->opcode) + (n << 5); 2198 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2199 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2200 if (sh == 0) { 2201 tcg_gen_mov_tl(dst, src); 2202 tcg_gen_movi_tl(cpu_ca, 0); 2203 } else { 2204 TCGv t0; 2205 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2206 t0 = tcg_temp_new(); 2207 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2208 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2209 tcg_temp_free(t0); 2210 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2211 tcg_gen_sari_tl(dst, src, sh); 2212 } 2213 if (unlikely(Rc(ctx->opcode) != 0)) { 2214 gen_set_Rc0(ctx, dst); 2215 } 2216 } 2217 2218 static void gen_sradi0(DisasContext *ctx) 2219 { 2220 gen_sradi(ctx, 0); 2221 } 2222 2223 static void gen_sradi1(DisasContext *ctx) 2224 { 2225 gen_sradi(ctx, 1); 2226 } 2227 2228 /* extswsli & extswsli. */ 2229 static inline void gen_extswsli(DisasContext *ctx, int n) 2230 { 2231 int sh = SH(ctx->opcode) + (n << 5); 2232 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2233 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2234 2235 tcg_gen_ext32s_tl(dst, src); 2236 tcg_gen_shli_tl(dst, dst, sh); 2237 if (unlikely(Rc(ctx->opcode) != 0)) { 2238 gen_set_Rc0(ctx, dst); 2239 } 2240 } 2241 2242 static void gen_extswsli0(DisasContext *ctx) 2243 { 2244 gen_extswsli(ctx, 0); 2245 } 2246 2247 static void gen_extswsli1(DisasContext *ctx) 2248 { 2249 gen_extswsli(ctx, 1); 2250 } 2251 2252 /* srd & srd. */ 2253 static void gen_srd(DisasContext *ctx) 2254 { 2255 TCGv t0, t1; 2256 2257 t0 = tcg_temp_new(); 2258 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2259 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2260 tcg_gen_sari_tl(t0, t0, 0x3f); 2261 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2262 t1 = tcg_temp_new(); 2263 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2264 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2265 tcg_temp_free(t1); 2266 tcg_temp_free(t0); 2267 if (unlikely(Rc(ctx->opcode) != 0)) 2268 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2269 } 2270 #endif 2271 2272 /*** Addressing modes ***/ 2273 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2274 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2275 target_long maskl) 2276 { 2277 target_long simm = SIMM(ctx->opcode); 2278 2279 simm &= ~maskl; 2280 if (rA(ctx->opcode) == 0) { 2281 if (NARROW_MODE(ctx)) { 2282 simm = (uint32_t)simm; 2283 } 2284 tcg_gen_movi_tl(EA, simm); 2285 } else if (likely(simm != 0)) { 2286 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2287 if (NARROW_MODE(ctx)) { 2288 tcg_gen_ext32u_tl(EA, EA); 2289 } 2290 } else { 2291 if (NARROW_MODE(ctx)) { 2292 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2293 } else { 2294 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2295 } 2296 } 2297 } 2298 2299 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2300 { 2301 if (rA(ctx->opcode) == 0) { 2302 if (NARROW_MODE(ctx)) { 2303 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2304 } else { 2305 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2306 } 2307 } else { 2308 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2309 if (NARROW_MODE(ctx)) { 2310 tcg_gen_ext32u_tl(EA, EA); 2311 } 2312 } 2313 } 2314 2315 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2316 { 2317 if (rA(ctx->opcode) == 0) { 2318 tcg_gen_movi_tl(EA, 0); 2319 } else if (NARROW_MODE(ctx)) { 2320 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2321 } else { 2322 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2323 } 2324 } 2325 2326 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2327 target_long val) 2328 { 2329 tcg_gen_addi_tl(ret, arg1, val); 2330 if (NARROW_MODE(ctx)) { 2331 tcg_gen_ext32u_tl(ret, ret); 2332 } 2333 } 2334 2335 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) 2336 { 2337 TCGLabel *l1 = gen_new_label(); 2338 TCGv t0 = tcg_temp_new(); 2339 TCGv_i32 t1, t2; 2340 tcg_gen_andi_tl(t0, EA, mask); 2341 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 2342 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); 2343 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); 2344 gen_update_nip(ctx, ctx->nip - 4); 2345 gen_helper_raise_exception_err(cpu_env, t1, t2); 2346 tcg_temp_free_i32(t1); 2347 tcg_temp_free_i32(t2); 2348 gen_set_label(l1); 2349 tcg_temp_free(t0); 2350 } 2351 2352 static inline void gen_align_no_le(DisasContext *ctx) 2353 { 2354 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2355 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2356 } 2357 2358 /*** Integer load ***/ 2359 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2360 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2361 2362 #define GEN_QEMU_LOAD_TL(ldop, op) \ 2363 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2364 TCGv val, \ 2365 TCGv addr) \ 2366 { \ 2367 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2368 } 2369 2370 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2371 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2372 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2373 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2374 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2375 2376 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2377 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2378 2379 #define GEN_QEMU_LOAD_64(ldop, op) \ 2380 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2381 TCGv_i64 val, \ 2382 TCGv addr) \ 2383 { \ 2384 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2385 } 2386 2387 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2388 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2389 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2390 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2391 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2392 2393 #if defined(TARGET_PPC64) 2394 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2395 #endif 2396 2397 #define GEN_QEMU_STORE_TL(stop, op) \ 2398 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2399 TCGv val, \ 2400 TCGv addr) \ 2401 { \ 2402 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2403 } 2404 2405 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2406 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2407 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2408 2409 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2410 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2411 2412 #define GEN_QEMU_STORE_64(stop, op) \ 2413 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2414 TCGv_i64 val, \ 2415 TCGv addr) \ 2416 { \ 2417 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2418 } 2419 2420 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2421 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2422 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2423 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2424 2425 #if defined(TARGET_PPC64) 2426 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2427 #endif 2428 2429 #define GEN_LD(name, ldop, opc, type) \ 2430 static void glue(gen_, name)(DisasContext *ctx) \ 2431 { \ 2432 TCGv EA; \ 2433 gen_set_access_type(ctx, ACCESS_INT); \ 2434 EA = tcg_temp_new(); \ 2435 gen_addr_imm_index(ctx, EA, 0); \ 2436 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2437 tcg_temp_free(EA); \ 2438 } 2439 2440 #define GEN_LDU(name, ldop, opc, type) \ 2441 static void glue(gen_, name##u)(DisasContext *ctx) \ 2442 { \ 2443 TCGv EA; \ 2444 if (unlikely(rA(ctx->opcode) == 0 || \ 2445 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2446 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2447 return; \ 2448 } \ 2449 gen_set_access_type(ctx, ACCESS_INT); \ 2450 EA = tcg_temp_new(); \ 2451 if (type == PPC_64B) \ 2452 gen_addr_imm_index(ctx, EA, 0x03); \ 2453 else \ 2454 gen_addr_imm_index(ctx, EA, 0); \ 2455 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2456 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2457 tcg_temp_free(EA); \ 2458 } 2459 2460 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2461 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2462 { \ 2463 TCGv EA; \ 2464 if (unlikely(rA(ctx->opcode) == 0 || \ 2465 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2466 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2467 return; \ 2468 } \ 2469 gen_set_access_type(ctx, ACCESS_INT); \ 2470 EA = tcg_temp_new(); \ 2471 gen_addr_reg_index(ctx, EA); \ 2472 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2473 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2474 tcg_temp_free(EA); \ 2475 } 2476 2477 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2478 static void glue(gen_, name##x)(DisasContext *ctx) \ 2479 { \ 2480 TCGv EA; \ 2481 chk; \ 2482 gen_set_access_type(ctx, ACCESS_INT); \ 2483 EA = tcg_temp_new(); \ 2484 gen_addr_reg_index(ctx, EA); \ 2485 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2486 tcg_temp_free(EA); \ 2487 } 2488 2489 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2490 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2491 2492 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2493 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2494 2495 #define GEN_LDS(name, ldop, op, type) \ 2496 GEN_LD(name, ldop, op | 0x20, type); \ 2497 GEN_LDU(name, ldop, op | 0x21, type); \ 2498 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2499 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2500 2501 /* lbz lbzu lbzux lbzx */ 2502 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2503 /* lha lhau lhaux lhax */ 2504 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2505 /* lhz lhzu lhzux lhzx */ 2506 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2507 /* lwz lwzu lwzux lwzx */ 2508 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2509 #if defined(TARGET_PPC64) 2510 /* lwaux */ 2511 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2512 /* lwax */ 2513 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2514 /* ldux */ 2515 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2516 /* ldx */ 2517 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2518 2519 /* CI load/store variants */ 2520 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2521 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2522 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2523 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2524 2525 static void gen_ld(DisasContext *ctx) 2526 { 2527 TCGv EA; 2528 if (Rc(ctx->opcode)) { 2529 if (unlikely(rA(ctx->opcode) == 0 || 2530 rA(ctx->opcode) == rD(ctx->opcode))) { 2531 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2532 return; 2533 } 2534 } 2535 gen_set_access_type(ctx, ACCESS_INT); 2536 EA = tcg_temp_new(); 2537 gen_addr_imm_index(ctx, EA, 0x03); 2538 if (ctx->opcode & 0x02) { 2539 /* lwa (lwau is undefined) */ 2540 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2541 } else { 2542 /* ld - ldu */ 2543 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2544 } 2545 if (Rc(ctx->opcode)) 2546 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2547 tcg_temp_free(EA); 2548 } 2549 2550 /* lq */ 2551 static void gen_lq(DisasContext *ctx) 2552 { 2553 int ra, rd; 2554 TCGv EA; 2555 2556 /* lq is a legal user mode instruction starting in ISA 2.07 */ 2557 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2558 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2559 2560 if (!legal_in_user_mode && ctx->pr) { 2561 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2562 return; 2563 } 2564 2565 if (!le_is_supported && ctx->le_mode) { 2566 gen_align_no_le(ctx); 2567 return; 2568 } 2569 ra = rA(ctx->opcode); 2570 rd = rD(ctx->opcode); 2571 if (unlikely((rd & 1) || rd == ra)) { 2572 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2573 return; 2574 } 2575 2576 gen_set_access_type(ctx, ACCESS_INT); 2577 EA = tcg_temp_new(); 2578 gen_addr_imm_index(ctx, EA, 0x0F); 2579 2580 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does 2581 necessary 64-bit byteswap already. */ 2582 if (unlikely(ctx->le_mode)) { 2583 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2584 gen_addr_add(ctx, EA, EA, 8); 2585 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2586 } else { 2587 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2588 gen_addr_add(ctx, EA, EA, 8); 2589 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2590 } 2591 tcg_temp_free(EA); 2592 } 2593 #endif 2594 2595 /*** Integer store ***/ 2596 #define GEN_ST(name, stop, opc, type) \ 2597 static void glue(gen_, name)(DisasContext *ctx) \ 2598 { \ 2599 TCGv EA; \ 2600 gen_set_access_type(ctx, ACCESS_INT); \ 2601 EA = tcg_temp_new(); \ 2602 gen_addr_imm_index(ctx, EA, 0); \ 2603 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2604 tcg_temp_free(EA); \ 2605 } 2606 2607 #define GEN_STU(name, stop, opc, type) \ 2608 static void glue(gen_, stop##u)(DisasContext *ctx) \ 2609 { \ 2610 TCGv EA; \ 2611 if (unlikely(rA(ctx->opcode) == 0)) { \ 2612 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2613 return; \ 2614 } \ 2615 gen_set_access_type(ctx, ACCESS_INT); \ 2616 EA = tcg_temp_new(); \ 2617 if (type == PPC_64B) \ 2618 gen_addr_imm_index(ctx, EA, 0x03); \ 2619 else \ 2620 gen_addr_imm_index(ctx, EA, 0); \ 2621 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2622 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2623 tcg_temp_free(EA); \ 2624 } 2625 2626 #define GEN_STUX(name, stop, opc2, opc3, type) \ 2627 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2628 { \ 2629 TCGv EA; \ 2630 if (unlikely(rA(ctx->opcode) == 0)) { \ 2631 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2632 return; \ 2633 } \ 2634 gen_set_access_type(ctx, ACCESS_INT); \ 2635 EA = tcg_temp_new(); \ 2636 gen_addr_reg_index(ctx, EA); \ 2637 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2638 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2639 tcg_temp_free(EA); \ 2640 } 2641 2642 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2643 static void glue(gen_, name##x)(DisasContext *ctx) \ 2644 { \ 2645 TCGv EA; \ 2646 chk; \ 2647 gen_set_access_type(ctx, ACCESS_INT); \ 2648 EA = tcg_temp_new(); \ 2649 gen_addr_reg_index(ctx, EA); \ 2650 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2651 tcg_temp_free(EA); \ 2652 } 2653 #define GEN_STX(name, stop, opc2, opc3, type) \ 2654 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2655 2656 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2657 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2658 2659 #define GEN_STS(name, stop, op, type) \ 2660 GEN_ST(name, stop, op | 0x20, type); \ 2661 GEN_STU(name, stop, op | 0x21, type); \ 2662 GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2663 GEN_STX(name, stop, 0x17, op | 0x00, type) 2664 2665 /* stb stbu stbux stbx */ 2666 GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2667 /* sth sthu sthux sthx */ 2668 GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2669 /* stw stwu stwux stwx */ 2670 GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2671 #if defined(TARGET_PPC64) 2672 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2673 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2674 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2675 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2676 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2677 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2678 2679 static void gen_std(DisasContext *ctx) 2680 { 2681 int rs; 2682 TCGv EA; 2683 2684 rs = rS(ctx->opcode); 2685 if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2686 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2687 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2688 2689 if (!(ctx->insns_flags & PPC_64BX)) { 2690 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2691 } 2692 2693 if (!legal_in_user_mode && ctx->pr) { 2694 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2695 return; 2696 } 2697 2698 if (!le_is_supported && ctx->le_mode) { 2699 gen_align_no_le(ctx); 2700 return; 2701 } 2702 2703 if (unlikely(rs & 1)) { 2704 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2705 return; 2706 } 2707 gen_set_access_type(ctx, ACCESS_INT); 2708 EA = tcg_temp_new(); 2709 gen_addr_imm_index(ctx, EA, 0x03); 2710 2711 /* We only need to swap high and low halves. gen_qemu_st64_i64 does 2712 necessary 64-bit byteswap already. */ 2713 if (unlikely(ctx->le_mode)) { 2714 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2715 gen_addr_add(ctx, EA, EA, 8); 2716 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2717 } else { 2718 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2719 gen_addr_add(ctx, EA, EA, 8); 2720 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2721 } 2722 tcg_temp_free(EA); 2723 } else { 2724 /* std / stdu*/ 2725 if (Rc(ctx->opcode)) { 2726 if (unlikely(rA(ctx->opcode) == 0)) { 2727 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2728 return; 2729 } 2730 } 2731 gen_set_access_type(ctx, ACCESS_INT); 2732 EA = tcg_temp_new(); 2733 gen_addr_imm_index(ctx, EA, 0x03); 2734 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2735 if (Rc(ctx->opcode)) 2736 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2737 tcg_temp_free(EA); 2738 } 2739 } 2740 #endif 2741 /*** Integer load and store with byte reverse ***/ 2742 2743 /* lhbrx */ 2744 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2745 2746 /* lwbrx */ 2747 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2748 2749 #if defined(TARGET_PPC64) 2750 /* ldbrx */ 2751 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2752 /* stdbrx */ 2753 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2754 #endif /* TARGET_PPC64 */ 2755 2756 /* sthbrx */ 2757 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2758 /* stwbrx */ 2759 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2760 2761 /*** Integer load and store multiple ***/ 2762 2763 /* lmw */ 2764 static void gen_lmw(DisasContext *ctx) 2765 { 2766 TCGv t0; 2767 TCGv_i32 t1; 2768 2769 if (ctx->le_mode) { 2770 gen_align_no_le(ctx); 2771 return; 2772 } 2773 gen_set_access_type(ctx, ACCESS_INT); 2774 t0 = tcg_temp_new(); 2775 t1 = tcg_const_i32(rD(ctx->opcode)); 2776 gen_addr_imm_index(ctx, t0, 0); 2777 gen_helper_lmw(cpu_env, t0, t1); 2778 tcg_temp_free(t0); 2779 tcg_temp_free_i32(t1); 2780 } 2781 2782 /* stmw */ 2783 static void gen_stmw(DisasContext *ctx) 2784 { 2785 TCGv t0; 2786 TCGv_i32 t1; 2787 2788 if (ctx->le_mode) { 2789 gen_align_no_le(ctx); 2790 return; 2791 } 2792 gen_set_access_type(ctx, ACCESS_INT); 2793 t0 = tcg_temp_new(); 2794 t1 = tcg_const_i32(rS(ctx->opcode)); 2795 gen_addr_imm_index(ctx, t0, 0); 2796 gen_helper_stmw(cpu_env, t0, t1); 2797 tcg_temp_free(t0); 2798 tcg_temp_free_i32(t1); 2799 } 2800 2801 /*** Integer load and store strings ***/ 2802 2803 /* lswi */ 2804 /* PowerPC32 specification says we must generate an exception if 2805 * rA is in the range of registers to be loaded. 2806 * In an other hand, IBM says this is valid, but rA won't be loaded. 2807 * For now, I'll follow the spec... 2808 */ 2809 static void gen_lswi(DisasContext *ctx) 2810 { 2811 TCGv t0; 2812 TCGv_i32 t1, t2; 2813 int nb = NB(ctx->opcode); 2814 int start = rD(ctx->opcode); 2815 int ra = rA(ctx->opcode); 2816 int nr; 2817 2818 if (ctx->le_mode) { 2819 gen_align_no_le(ctx); 2820 return; 2821 } 2822 if (nb == 0) 2823 nb = 32; 2824 nr = (nb + 3) / 4; 2825 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2826 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2827 return; 2828 } 2829 gen_set_access_type(ctx, ACCESS_INT); 2830 t0 = tcg_temp_new(); 2831 gen_addr_register(ctx, t0); 2832 t1 = tcg_const_i32(nb); 2833 t2 = tcg_const_i32(start); 2834 gen_helper_lsw(cpu_env, t0, t1, t2); 2835 tcg_temp_free(t0); 2836 tcg_temp_free_i32(t1); 2837 tcg_temp_free_i32(t2); 2838 } 2839 2840 /* lswx */ 2841 static void gen_lswx(DisasContext *ctx) 2842 { 2843 TCGv t0; 2844 TCGv_i32 t1, t2, t3; 2845 2846 if (ctx->le_mode) { 2847 gen_align_no_le(ctx); 2848 return; 2849 } 2850 gen_set_access_type(ctx, ACCESS_INT); 2851 t0 = tcg_temp_new(); 2852 gen_addr_reg_index(ctx, t0); 2853 t1 = tcg_const_i32(rD(ctx->opcode)); 2854 t2 = tcg_const_i32(rA(ctx->opcode)); 2855 t3 = tcg_const_i32(rB(ctx->opcode)); 2856 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 2857 tcg_temp_free(t0); 2858 tcg_temp_free_i32(t1); 2859 tcg_temp_free_i32(t2); 2860 tcg_temp_free_i32(t3); 2861 } 2862 2863 /* stswi */ 2864 static void gen_stswi(DisasContext *ctx) 2865 { 2866 TCGv t0; 2867 TCGv_i32 t1, t2; 2868 int nb = NB(ctx->opcode); 2869 2870 if (ctx->le_mode) { 2871 gen_align_no_le(ctx); 2872 return; 2873 } 2874 gen_set_access_type(ctx, ACCESS_INT); 2875 t0 = tcg_temp_new(); 2876 gen_addr_register(ctx, t0); 2877 if (nb == 0) 2878 nb = 32; 2879 t1 = tcg_const_i32(nb); 2880 t2 = tcg_const_i32(rS(ctx->opcode)); 2881 gen_helper_stsw(cpu_env, t0, t1, t2); 2882 tcg_temp_free(t0); 2883 tcg_temp_free_i32(t1); 2884 tcg_temp_free_i32(t2); 2885 } 2886 2887 /* stswx */ 2888 static void gen_stswx(DisasContext *ctx) 2889 { 2890 TCGv t0; 2891 TCGv_i32 t1, t2; 2892 2893 if (ctx->le_mode) { 2894 gen_align_no_le(ctx); 2895 return; 2896 } 2897 gen_set_access_type(ctx, ACCESS_INT); 2898 t0 = tcg_temp_new(); 2899 gen_addr_reg_index(ctx, t0); 2900 t1 = tcg_temp_new_i32(); 2901 tcg_gen_trunc_tl_i32(t1, cpu_xer); 2902 tcg_gen_andi_i32(t1, t1, 0x7F); 2903 t2 = tcg_const_i32(rS(ctx->opcode)); 2904 gen_helper_stsw(cpu_env, t0, t1, t2); 2905 tcg_temp_free(t0); 2906 tcg_temp_free_i32(t1); 2907 tcg_temp_free_i32(t2); 2908 } 2909 2910 /*** Memory synchronisation ***/ 2911 /* eieio */ 2912 static void gen_eieio(DisasContext *ctx) 2913 { 2914 } 2915 2916 #if !defined(CONFIG_USER_ONLY) 2917 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 2918 { 2919 TCGv_i32 t; 2920 TCGLabel *l; 2921 2922 if (!ctx->lazy_tlb_flush) { 2923 return; 2924 } 2925 l = gen_new_label(); 2926 t = tcg_temp_new_i32(); 2927 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 2928 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 2929 if (global) { 2930 gen_helper_check_tlb_flush_global(cpu_env); 2931 } else { 2932 gen_helper_check_tlb_flush_local(cpu_env); 2933 } 2934 gen_set_label(l); 2935 tcg_temp_free_i32(t); 2936 } 2937 #else 2938 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 2939 #endif 2940 2941 /* isync */ 2942 static void gen_isync(DisasContext *ctx) 2943 { 2944 /* 2945 * We need to check for a pending TLB flush. This can only happen in 2946 * kernel mode however so check MSR_PR 2947 */ 2948 if (!ctx->pr) { 2949 gen_check_tlb_flush(ctx, false); 2950 } 2951 gen_stop_exception(ctx); 2952 } 2953 2954 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 2955 2956 #define LARX(name, memop) \ 2957 static void gen_##name(DisasContext *ctx) \ 2958 { \ 2959 TCGv t0; \ 2960 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ 2961 int len = MEMOP_GET_SIZE(memop); \ 2962 gen_set_access_type(ctx, ACCESS_RES); \ 2963 t0 = tcg_temp_local_new(); \ 2964 gen_addr_reg_index(ctx, t0); \ 2965 if ((len) > 1) { \ 2966 gen_check_align(ctx, t0, (len)-1); \ 2967 } \ 2968 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ 2969 tcg_gen_mov_tl(cpu_reserve, t0); \ 2970 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \ 2971 tcg_temp_free(t0); \ 2972 } 2973 2974 /* lwarx */ 2975 LARX(lbarx, DEF_MEMOP(MO_UB)) 2976 LARX(lharx, DEF_MEMOP(MO_UW)) 2977 LARX(lwarx, DEF_MEMOP(MO_UL)) 2978 2979 #define LD_ATOMIC(name, memop, tp, op, eop) \ 2980 static void gen_##name(DisasContext *ctx) \ 2981 { \ 2982 int len = MEMOP_GET_SIZE(memop); \ 2983 uint32_t gpr_FC = FC(ctx->opcode); \ 2984 TCGv EA = tcg_temp_local_new(); \ 2985 TCGv_##tp t0, t1; \ 2986 \ 2987 gen_addr_register(ctx, EA); \ 2988 if (len > 1) { \ 2989 gen_check_align(ctx, EA, len - 1); \ 2990 } \ 2991 t0 = tcg_temp_new_##tp(); \ 2992 t1 = tcg_temp_new_##tp(); \ 2993 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 2994 \ 2995 switch (gpr_FC) { \ 2996 case 0: /* Fetch and add */ \ 2997 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 2998 break; \ 2999 case 1: /* Fetch and xor */ \ 3000 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3001 break; \ 3002 case 2: /* Fetch and or */ \ 3003 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3004 break; \ 3005 case 3: /* Fetch and 'and' */ \ 3006 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3007 break; \ 3008 case 8: /* Swap */ \ 3009 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3010 break; \ 3011 case 4: /* Fetch and max unsigned */ \ 3012 case 5: /* Fetch and max signed */ \ 3013 case 6: /* Fetch and min unsigned */ \ 3014 case 7: /* Fetch and min signed */ \ 3015 case 16: /* compare and swap not equal */ \ 3016 case 24: /* Fetch and increment bounded */ \ 3017 case 25: /* Fetch and increment equal */ \ 3018 case 28: /* Fetch and decrement bounded */ \ 3019 gen_invalid(ctx); \ 3020 break; \ 3021 default: \ 3022 /* invoke data storage error handler */ \ 3023 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3024 } \ 3025 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \ 3026 tcg_temp_free_##tp(t0); \ 3027 tcg_temp_free_##tp(t1); \ 3028 tcg_temp_free(EA); \ 3029 } 3030 3031 LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl) 3032 #if defined(TARGET_PPC64) 3033 LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64) 3034 #endif 3035 3036 #define ST_ATOMIC(name, memop, tp, op) \ 3037 static void gen_##name(DisasContext *ctx) \ 3038 { \ 3039 int len = MEMOP_GET_SIZE(memop); \ 3040 uint32_t gpr_FC = FC(ctx->opcode); \ 3041 TCGv EA = tcg_temp_local_new(); \ 3042 TCGv_##tp t0, t1; \ 3043 \ 3044 gen_addr_register(ctx, EA); \ 3045 if (len > 1) { \ 3046 gen_check_align(ctx, EA, len - 1); \ 3047 } \ 3048 t0 = tcg_temp_new_##tp(); \ 3049 t1 = tcg_temp_new_##tp(); \ 3050 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3051 \ 3052 switch (gpr_FC) { \ 3053 case 0: /* add and Store */ \ 3054 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3055 break; \ 3056 case 1: /* xor and Store */ \ 3057 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3058 break; \ 3059 case 2: /* Or and Store */ \ 3060 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3061 break; \ 3062 case 3: /* 'and' and Store */ \ 3063 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3064 break; \ 3065 case 4: /* Store max unsigned */ \ 3066 case 5: /* Store max signed */ \ 3067 case 6: /* Store min unsigned */ \ 3068 case 7: /* Store min signed */ \ 3069 case 24: /* Store twin */ \ 3070 gen_invalid(ctx); \ 3071 break; \ 3072 default: \ 3073 /* invoke data storage error handler */ \ 3074 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3075 } \ 3076 tcg_temp_free_##tp(t0); \ 3077 tcg_temp_free_##tp(t1); \ 3078 tcg_temp_free(EA); \ 3079 } 3080 3081 ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) 3082 #if defined(TARGET_PPC64) 3083 ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) 3084 #endif 3085 3086 #if defined(CONFIG_USER_ONLY) 3087 static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3088 int reg, int memop) 3089 { 3090 TCGv t0 = tcg_temp_new(); 3091 3092 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); 3093 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); 3094 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); 3095 tcg_temp_free(t0); 3096 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); 3097 } 3098 #else 3099 static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3100 int reg, int memop) 3101 { 3102 TCGLabel *l1; 3103 3104 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3105 l1 = gen_new_label(); 3106 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3107 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3108 tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop); 3109 gen_set_label(l1); 3110 tcg_gen_movi_tl(cpu_reserve, -1); 3111 } 3112 #endif 3113 3114 #define STCX(name, memop) \ 3115 static void gen_##name(DisasContext *ctx) \ 3116 { \ 3117 TCGv t0; \ 3118 int len = MEMOP_GET_SIZE(memop); \ 3119 gen_set_access_type(ctx, ACCESS_RES); \ 3120 t0 = tcg_temp_local_new(); \ 3121 gen_addr_reg_index(ctx, t0); \ 3122 if (len > 1) { \ 3123 gen_check_align(ctx, t0, (len) - 1); \ 3124 } \ 3125 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ 3126 tcg_temp_free(t0); \ 3127 } 3128 3129 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3130 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3131 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3132 3133 #if defined(TARGET_PPC64) 3134 /* ldarx */ 3135 LARX(ldarx, DEF_MEMOP(MO_Q)) 3136 /* stdcx. */ 3137 STCX(stdcx_, DEF_MEMOP(MO_Q)) 3138 3139 /* lqarx */ 3140 static void gen_lqarx(DisasContext *ctx) 3141 { 3142 TCGv EA; 3143 int rd = rD(ctx->opcode); 3144 TCGv gpr1, gpr2; 3145 3146 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3147 (rd == rB(ctx->opcode)))) { 3148 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3149 return; 3150 } 3151 3152 gen_set_access_type(ctx, ACCESS_RES); 3153 EA = tcg_temp_local_new(); 3154 gen_addr_reg_index(ctx, EA); 3155 gen_check_align(ctx, EA, 15); 3156 if (unlikely(ctx->le_mode)) { 3157 gpr1 = cpu_gpr[rd+1]; 3158 gpr2 = cpu_gpr[rd]; 3159 } else { 3160 gpr1 = cpu_gpr[rd]; 3161 gpr2 = cpu_gpr[rd+1]; 3162 } 3163 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3164 tcg_gen_mov_tl(cpu_reserve, EA); 3165 gen_addr_add(ctx, EA, EA, 8); 3166 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3167 3168 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); 3169 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3170 tcg_temp_free(EA); 3171 } 3172 3173 /* stqcx. */ 3174 static void gen_stqcx_(DisasContext *ctx) 3175 { 3176 TCGv EA; 3177 int reg = rS(ctx->opcode); 3178 int len = 16; 3179 #if !defined(CONFIG_USER_ONLY) 3180 TCGLabel *l1; 3181 TCGv gpr1, gpr2; 3182 #endif 3183 3184 if (unlikely((rD(ctx->opcode) & 1))) { 3185 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3186 return; 3187 } 3188 gen_set_access_type(ctx, ACCESS_RES); 3189 EA = tcg_temp_local_new(); 3190 gen_addr_reg_index(ctx, EA); 3191 if (len > 1) { 3192 gen_check_align(ctx, EA, (len) - 1); 3193 } 3194 3195 #if defined(CONFIG_USER_ONLY) 3196 gen_conditional_store(ctx, EA, reg, 16); 3197 #else 3198 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3199 l1 = gen_new_label(); 3200 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3201 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3202 3203 if (unlikely(ctx->le_mode)) { 3204 gpr1 = cpu_gpr[reg + 1]; 3205 gpr2 = cpu_gpr[reg]; 3206 } else { 3207 gpr1 = cpu_gpr[reg]; 3208 gpr2 = cpu_gpr[reg + 1]; 3209 } 3210 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3211 gen_addr_add(ctx, EA, EA, 8); 3212 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3213 3214 gen_set_label(l1); 3215 tcg_gen_movi_tl(cpu_reserve, -1); 3216 #endif 3217 tcg_temp_free(EA); 3218 } 3219 3220 #endif /* defined(TARGET_PPC64) */ 3221 3222 /* sync */ 3223 static void gen_sync(DisasContext *ctx) 3224 { 3225 uint32_t l = (ctx->opcode >> 21) & 3; 3226 3227 /* 3228 * We may need to check for a pending TLB flush. 3229 * 3230 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3231 * 3232 * Additionally, this can only happen in kernel mode however so 3233 * check MSR_PR as well. 3234 */ 3235 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3236 gen_check_tlb_flush(ctx, true); 3237 } 3238 } 3239 3240 /* wait */ 3241 static void gen_wait(DisasContext *ctx) 3242 { 3243 TCGv_i32 t0 = tcg_const_i32(1); 3244 tcg_gen_st_i32(t0, cpu_env, 3245 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3246 tcg_temp_free_i32(t0); 3247 /* Stop translation, as the CPU is supposed to sleep from now */ 3248 gen_exception_nip(ctx, EXCP_HLT, ctx->nip); 3249 } 3250 3251 #if defined(TARGET_PPC64) 3252 static void gen_doze(DisasContext *ctx) 3253 { 3254 #if defined(CONFIG_USER_ONLY) 3255 GEN_PRIV; 3256 #else 3257 TCGv_i32 t; 3258 3259 CHK_HV; 3260 t = tcg_const_i32(PPC_PM_DOZE); 3261 gen_helper_pminsn(cpu_env, t); 3262 tcg_temp_free_i32(t); 3263 gen_stop_exception(ctx); 3264 #endif /* defined(CONFIG_USER_ONLY) */ 3265 } 3266 3267 static void gen_nap(DisasContext *ctx) 3268 { 3269 #if defined(CONFIG_USER_ONLY) 3270 GEN_PRIV; 3271 #else 3272 TCGv_i32 t; 3273 3274 CHK_HV; 3275 t = tcg_const_i32(PPC_PM_NAP); 3276 gen_helper_pminsn(cpu_env, t); 3277 tcg_temp_free_i32(t); 3278 gen_stop_exception(ctx); 3279 #endif /* defined(CONFIG_USER_ONLY) */ 3280 } 3281 3282 static void gen_stop(DisasContext *ctx) 3283 { 3284 gen_nap(ctx); 3285 } 3286 3287 static void gen_sleep(DisasContext *ctx) 3288 { 3289 #if defined(CONFIG_USER_ONLY) 3290 GEN_PRIV; 3291 #else 3292 TCGv_i32 t; 3293 3294 CHK_HV; 3295 t = tcg_const_i32(PPC_PM_SLEEP); 3296 gen_helper_pminsn(cpu_env, t); 3297 tcg_temp_free_i32(t); 3298 gen_stop_exception(ctx); 3299 #endif /* defined(CONFIG_USER_ONLY) */ 3300 } 3301 3302 static void gen_rvwinkle(DisasContext *ctx) 3303 { 3304 #if defined(CONFIG_USER_ONLY) 3305 GEN_PRIV; 3306 #else 3307 TCGv_i32 t; 3308 3309 CHK_HV; 3310 t = tcg_const_i32(PPC_PM_RVWINKLE); 3311 gen_helper_pminsn(cpu_env, t); 3312 tcg_temp_free_i32(t); 3313 gen_stop_exception(ctx); 3314 #endif /* defined(CONFIG_USER_ONLY) */ 3315 } 3316 #endif /* #if defined(TARGET_PPC64) */ 3317 3318 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3319 { 3320 #if defined(TARGET_PPC64) 3321 if (ctx->has_cfar) 3322 tcg_gen_movi_tl(cpu_cfar, nip); 3323 #endif 3324 } 3325 3326 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3327 { 3328 if (unlikely(ctx->singlestep_enabled)) { 3329 return false; 3330 } 3331 3332 #ifndef CONFIG_USER_ONLY 3333 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3334 #else 3335 return true; 3336 #endif 3337 } 3338 3339 /*** Branch ***/ 3340 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3341 { 3342 if (NARROW_MODE(ctx)) { 3343 dest = (uint32_t) dest; 3344 } 3345 if (use_goto_tb(ctx, dest)) { 3346 tcg_gen_goto_tb(n); 3347 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3348 tcg_gen_exit_tb((uintptr_t)ctx->tb + n); 3349 } else { 3350 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3351 if (unlikely(ctx->singlestep_enabled)) { 3352 if ((ctx->singlestep_enabled & 3353 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && 3354 (ctx->exception == POWERPC_EXCP_BRANCH || 3355 ctx->exception == POWERPC_EXCP_TRACE)) { 3356 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest); 3357 } 3358 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { 3359 gen_debug_exception(ctx); 3360 } 3361 } 3362 tcg_gen_exit_tb(0); 3363 } 3364 } 3365 3366 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3367 { 3368 if (NARROW_MODE(ctx)) { 3369 nip = (uint32_t)nip; 3370 } 3371 tcg_gen_movi_tl(cpu_lr, nip); 3372 } 3373 3374 /* b ba bl bla */ 3375 static void gen_b(DisasContext *ctx) 3376 { 3377 target_ulong li, target; 3378 3379 ctx->exception = POWERPC_EXCP_BRANCH; 3380 /* sign extend LI */ 3381 li = LI(ctx->opcode); 3382 li = (li ^ 0x02000000) - 0x02000000; 3383 if (likely(AA(ctx->opcode) == 0)) { 3384 target = ctx->nip + li - 4; 3385 } else { 3386 target = li; 3387 } 3388 if (LK(ctx->opcode)) { 3389 gen_setlr(ctx, ctx->nip); 3390 } 3391 gen_update_cfar(ctx, ctx->nip - 4); 3392 gen_goto_tb(ctx, 0, target); 3393 } 3394 3395 #define BCOND_IM 0 3396 #define BCOND_LR 1 3397 #define BCOND_CTR 2 3398 #define BCOND_TAR 3 3399 3400 static inline void gen_bcond(DisasContext *ctx, int type) 3401 { 3402 uint32_t bo = BO(ctx->opcode); 3403 TCGLabel *l1; 3404 TCGv target; 3405 3406 ctx->exception = POWERPC_EXCP_BRANCH; 3407 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3408 target = tcg_temp_local_new(); 3409 if (type == BCOND_CTR) 3410 tcg_gen_mov_tl(target, cpu_ctr); 3411 else if (type == BCOND_TAR) 3412 gen_load_spr(target, SPR_TAR); 3413 else 3414 tcg_gen_mov_tl(target, cpu_lr); 3415 } else { 3416 TCGV_UNUSED(target); 3417 } 3418 if (LK(ctx->opcode)) 3419 gen_setlr(ctx, ctx->nip); 3420 l1 = gen_new_label(); 3421 if ((bo & 0x4) == 0) { 3422 /* Decrement and test CTR */ 3423 TCGv temp = tcg_temp_new(); 3424 if (unlikely(type == BCOND_CTR)) { 3425 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3426 return; 3427 } 3428 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3429 if (NARROW_MODE(ctx)) { 3430 tcg_gen_ext32u_tl(temp, cpu_ctr); 3431 } else { 3432 tcg_gen_mov_tl(temp, cpu_ctr); 3433 } 3434 if (bo & 0x2) { 3435 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3436 } else { 3437 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3438 } 3439 tcg_temp_free(temp); 3440 } 3441 if ((bo & 0x10) == 0) { 3442 /* Test CR */ 3443 uint32_t bi = BI(ctx->opcode); 3444 uint32_t mask = 0x08 >> (bi & 0x03); 3445 TCGv_i32 temp = tcg_temp_new_i32(); 3446 3447 if (bo & 0x8) { 3448 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3449 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3450 } else { 3451 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3452 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3453 } 3454 tcg_temp_free_i32(temp); 3455 } 3456 gen_update_cfar(ctx, ctx->nip - 4); 3457 if (type == BCOND_IM) { 3458 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3459 if (likely(AA(ctx->opcode) == 0)) { 3460 gen_goto_tb(ctx, 0, ctx->nip + li - 4); 3461 } else { 3462 gen_goto_tb(ctx, 0, li); 3463 } 3464 if ((bo & 0x14) != 0x14) { 3465 gen_set_label(l1); 3466 gen_goto_tb(ctx, 1, ctx->nip); 3467 } 3468 } else { 3469 if (NARROW_MODE(ctx)) { 3470 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3471 } else { 3472 tcg_gen_andi_tl(cpu_nip, target, ~3); 3473 } 3474 tcg_gen_exit_tb(0); 3475 if ((bo & 0x14) != 0x14) { 3476 gen_set_label(l1); 3477 gen_update_nip(ctx, ctx->nip); 3478 tcg_gen_exit_tb(0); 3479 } 3480 } 3481 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3482 tcg_temp_free(target); 3483 } 3484 } 3485 3486 static void gen_bc(DisasContext *ctx) 3487 { 3488 gen_bcond(ctx, BCOND_IM); 3489 } 3490 3491 static void gen_bcctr(DisasContext *ctx) 3492 { 3493 gen_bcond(ctx, BCOND_CTR); 3494 } 3495 3496 static void gen_bclr(DisasContext *ctx) 3497 { 3498 gen_bcond(ctx, BCOND_LR); 3499 } 3500 3501 static void gen_bctar(DisasContext *ctx) 3502 { 3503 gen_bcond(ctx, BCOND_TAR); 3504 } 3505 3506 /*** Condition register logical ***/ 3507 #define GEN_CRLOGIC(name, tcg_op, opc) \ 3508 static void glue(gen_, name)(DisasContext *ctx) \ 3509 { \ 3510 uint8_t bitmask; \ 3511 int sh; \ 3512 TCGv_i32 t0, t1; \ 3513 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3514 t0 = tcg_temp_new_i32(); \ 3515 if (sh > 0) \ 3516 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3517 else if (sh < 0) \ 3518 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3519 else \ 3520 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3521 t1 = tcg_temp_new_i32(); \ 3522 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3523 if (sh > 0) \ 3524 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3525 else if (sh < 0) \ 3526 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3527 else \ 3528 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3529 tcg_op(t0, t0, t1); \ 3530 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3531 tcg_gen_andi_i32(t0, t0, bitmask); \ 3532 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3533 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3534 tcg_temp_free_i32(t0); \ 3535 tcg_temp_free_i32(t1); \ 3536 } 3537 3538 /* crand */ 3539 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3540 /* crandc */ 3541 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3542 /* creqv */ 3543 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3544 /* crnand */ 3545 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3546 /* crnor */ 3547 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3548 /* cror */ 3549 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3550 /* crorc */ 3551 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3552 /* crxor */ 3553 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3554 3555 /* mcrf */ 3556 static void gen_mcrf(DisasContext *ctx) 3557 { 3558 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3559 } 3560 3561 /*** System linkage ***/ 3562 3563 /* rfi (supervisor only) */ 3564 static void gen_rfi(DisasContext *ctx) 3565 { 3566 #if defined(CONFIG_USER_ONLY) 3567 GEN_PRIV; 3568 #else 3569 /* This instruction doesn't exist anymore on 64-bit server 3570 * processors compliant with arch 2.x 3571 */ 3572 if (ctx->insns_flags & PPC_SEGMENT_64B) { 3573 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3574 return; 3575 } 3576 /* Restore CPU state */ 3577 CHK_SV; 3578 gen_update_cfar(ctx, ctx->nip - 4); 3579 gen_helper_rfi(cpu_env); 3580 gen_sync_exception(ctx); 3581 #endif 3582 } 3583 3584 #if defined(TARGET_PPC64) 3585 static void gen_rfid(DisasContext *ctx) 3586 { 3587 #if defined(CONFIG_USER_ONLY) 3588 GEN_PRIV; 3589 #else 3590 /* Restore CPU state */ 3591 CHK_SV; 3592 gen_update_cfar(ctx, ctx->nip - 4); 3593 gen_helper_rfid(cpu_env); 3594 gen_sync_exception(ctx); 3595 #endif 3596 } 3597 3598 static void gen_hrfid(DisasContext *ctx) 3599 { 3600 #if defined(CONFIG_USER_ONLY) 3601 GEN_PRIV; 3602 #else 3603 /* Restore CPU state */ 3604 CHK_HV; 3605 gen_helper_hrfid(cpu_env); 3606 gen_sync_exception(ctx); 3607 #endif 3608 } 3609 #endif 3610 3611 /* sc */ 3612 #if defined(CONFIG_USER_ONLY) 3613 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3614 #else 3615 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3616 #endif 3617 static void gen_sc(DisasContext *ctx) 3618 { 3619 uint32_t lev; 3620 3621 lev = (ctx->opcode >> 5) & 0x7F; 3622 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3623 } 3624 3625 /*** Trap ***/ 3626 3627 /* Check for unconditional traps (always or never) */ 3628 static bool check_unconditional_trap(DisasContext *ctx) 3629 { 3630 /* Trap never */ 3631 if (TO(ctx->opcode) == 0) { 3632 return true; 3633 } 3634 /* Trap always */ 3635 if (TO(ctx->opcode) == 31) { 3636 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3637 return true; 3638 } 3639 return false; 3640 } 3641 3642 /* tw */ 3643 static void gen_tw(DisasContext *ctx) 3644 { 3645 TCGv_i32 t0; 3646 3647 if (check_unconditional_trap(ctx)) { 3648 return; 3649 } 3650 t0 = tcg_const_i32(TO(ctx->opcode)); 3651 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3652 t0); 3653 tcg_temp_free_i32(t0); 3654 } 3655 3656 /* twi */ 3657 static void gen_twi(DisasContext *ctx) 3658 { 3659 TCGv t0; 3660 TCGv_i32 t1; 3661 3662 if (check_unconditional_trap(ctx)) { 3663 return; 3664 } 3665 t0 = tcg_const_tl(SIMM(ctx->opcode)); 3666 t1 = tcg_const_i32(TO(ctx->opcode)); 3667 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3668 tcg_temp_free(t0); 3669 tcg_temp_free_i32(t1); 3670 } 3671 3672 #if defined(TARGET_PPC64) 3673 /* td */ 3674 static void gen_td(DisasContext *ctx) 3675 { 3676 TCGv_i32 t0; 3677 3678 if (check_unconditional_trap(ctx)) { 3679 return; 3680 } 3681 t0 = tcg_const_i32(TO(ctx->opcode)); 3682 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3683 t0); 3684 tcg_temp_free_i32(t0); 3685 } 3686 3687 /* tdi */ 3688 static void gen_tdi(DisasContext *ctx) 3689 { 3690 TCGv t0; 3691 TCGv_i32 t1; 3692 3693 if (check_unconditional_trap(ctx)) { 3694 return; 3695 } 3696 t0 = tcg_const_tl(SIMM(ctx->opcode)); 3697 t1 = tcg_const_i32(TO(ctx->opcode)); 3698 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3699 tcg_temp_free(t0); 3700 tcg_temp_free_i32(t1); 3701 } 3702 #endif 3703 3704 /*** Processor control ***/ 3705 3706 static void gen_read_xer(TCGv dst) 3707 { 3708 TCGv t0 = tcg_temp_new(); 3709 TCGv t1 = tcg_temp_new(); 3710 TCGv t2 = tcg_temp_new(); 3711 tcg_gen_mov_tl(dst, cpu_xer); 3712 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 3713 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 3714 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 3715 tcg_gen_or_tl(t0, t0, t1); 3716 tcg_gen_or_tl(dst, dst, t2); 3717 tcg_gen_or_tl(dst, dst, t0); 3718 tcg_temp_free(t0); 3719 tcg_temp_free(t1); 3720 tcg_temp_free(t2); 3721 } 3722 3723 static void gen_write_xer(TCGv src) 3724 { 3725 tcg_gen_andi_tl(cpu_xer, src, 3726 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); 3727 tcg_gen_shri_tl(cpu_so, src, XER_SO); 3728 tcg_gen_shri_tl(cpu_ov, src, XER_OV); 3729 tcg_gen_shri_tl(cpu_ca, src, XER_CA); 3730 tcg_gen_andi_tl(cpu_so, cpu_so, 1); 3731 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); 3732 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); 3733 } 3734 3735 /* mcrxr */ 3736 static void gen_mcrxr(DisasContext *ctx) 3737 { 3738 TCGv_i32 t0 = tcg_temp_new_i32(); 3739 TCGv_i32 t1 = tcg_temp_new_i32(); 3740 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 3741 3742 tcg_gen_trunc_tl_i32(t0, cpu_so); 3743 tcg_gen_trunc_tl_i32(t1, cpu_ov); 3744 tcg_gen_trunc_tl_i32(dst, cpu_ca); 3745 tcg_gen_shli_i32(t0, t0, 3); 3746 tcg_gen_shli_i32(t1, t1, 2); 3747 tcg_gen_shli_i32(dst, dst, 1); 3748 tcg_gen_or_i32(dst, dst, t0); 3749 tcg_gen_or_i32(dst, dst, t1); 3750 tcg_temp_free_i32(t0); 3751 tcg_temp_free_i32(t1); 3752 3753 tcg_gen_movi_tl(cpu_so, 0); 3754 tcg_gen_movi_tl(cpu_ov, 0); 3755 tcg_gen_movi_tl(cpu_ca, 0); 3756 } 3757 3758 /* mfcr mfocrf */ 3759 static void gen_mfcr(DisasContext *ctx) 3760 { 3761 uint32_t crm, crn; 3762 3763 if (likely(ctx->opcode & 0x00100000)) { 3764 crm = CRM(ctx->opcode); 3765 if (likely(crm && ((crm & (crm - 1)) == 0))) { 3766 crn = ctz32 (crm); 3767 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 3768 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 3769 cpu_gpr[rD(ctx->opcode)], crn * 4); 3770 } 3771 } else { 3772 TCGv_i32 t0 = tcg_temp_new_i32(); 3773 tcg_gen_mov_i32(t0, cpu_crf[0]); 3774 tcg_gen_shli_i32(t0, t0, 4); 3775 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 3776 tcg_gen_shli_i32(t0, t0, 4); 3777 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 3778 tcg_gen_shli_i32(t0, t0, 4); 3779 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 3780 tcg_gen_shli_i32(t0, t0, 4); 3781 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 3782 tcg_gen_shli_i32(t0, t0, 4); 3783 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 3784 tcg_gen_shli_i32(t0, t0, 4); 3785 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 3786 tcg_gen_shli_i32(t0, t0, 4); 3787 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 3788 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 3789 tcg_temp_free_i32(t0); 3790 } 3791 } 3792 3793 /* mfmsr */ 3794 static void gen_mfmsr(DisasContext *ctx) 3795 { 3796 CHK_SV; 3797 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 3798 } 3799 3800 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 3801 { 3802 #if 0 3803 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 3804 printf("ERROR: try to access SPR %d !\n", sprn); 3805 #endif 3806 } 3807 #define SPR_NOACCESS (&spr_noaccess) 3808 3809 /* mfspr */ 3810 static inline void gen_op_mfspr(DisasContext *ctx) 3811 { 3812 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 3813 uint32_t sprn = SPR(ctx->opcode); 3814 3815 #if defined(CONFIG_USER_ONLY) 3816 read_cb = ctx->spr_cb[sprn].uea_read; 3817 #else 3818 if (ctx->pr) { 3819 read_cb = ctx->spr_cb[sprn].uea_read; 3820 } else if (ctx->hv) { 3821 read_cb = ctx->spr_cb[sprn].hea_read; 3822 } else { 3823 read_cb = ctx->spr_cb[sprn].oea_read; 3824 } 3825 #endif 3826 if (likely(read_cb != NULL)) { 3827 if (likely(read_cb != SPR_NOACCESS)) { 3828 (*read_cb)(ctx, rD(ctx->opcode), sprn); 3829 } else { 3830 /* Privilege exception */ 3831 /* This is a hack to avoid warnings when running Linux: 3832 * this OS breaks the PowerPC virtualisation model, 3833 * allowing userland application to read the PVR 3834 */ 3835 if (sprn != SPR_PVR) { 3836 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at " 3837 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3838 if (qemu_log_separate()) { 3839 qemu_log("Trying to read privileged spr %d (0x%03x) at " 3840 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3841 } 3842 } 3843 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 3844 } 3845 } else { 3846 /* ISA 2.07 defines these as no-ops */ 3847 if ((ctx->insns_flags2 & PPC2_ISA207S) && 3848 (sprn >= 808 && sprn <= 811)) { 3849 /* This is a nop */ 3850 return; 3851 } 3852 /* Not defined */ 3853 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at " 3854 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3855 if (qemu_log_separate()) { 3856 qemu_log("Trying to read invalid spr %d (0x%03x) at " 3857 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3858 } 3859 3860 /* The behaviour depends on MSR:PR and SPR# bit 0x10, 3861 * it can generate a priv, a hv emu or a no-op 3862 */ 3863 if (sprn & 0x10) { 3864 if (ctx->pr) { 3865 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3866 } 3867 } else { 3868 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 3869 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3870 } 3871 } 3872 } 3873 } 3874 3875 static void gen_mfspr(DisasContext *ctx) 3876 { 3877 gen_op_mfspr(ctx); 3878 } 3879 3880 /* mftb */ 3881 static void gen_mftb(DisasContext *ctx) 3882 { 3883 gen_op_mfspr(ctx); 3884 } 3885 3886 /* mtcrf mtocrf*/ 3887 static void gen_mtcrf(DisasContext *ctx) 3888 { 3889 uint32_t crm, crn; 3890 3891 crm = CRM(ctx->opcode); 3892 if (likely((ctx->opcode & 0x00100000))) { 3893 if (crm && ((crm & (crm - 1)) == 0)) { 3894 TCGv_i32 temp = tcg_temp_new_i32(); 3895 crn = ctz32 (crm); 3896 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 3897 tcg_gen_shri_i32(temp, temp, crn * 4); 3898 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 3899 tcg_temp_free_i32(temp); 3900 } 3901 } else { 3902 TCGv_i32 temp = tcg_temp_new_i32(); 3903 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 3904 for (crn = 0 ; crn < 8 ; crn++) { 3905 if (crm & (1 << crn)) { 3906 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 3907 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 3908 } 3909 } 3910 tcg_temp_free_i32(temp); 3911 } 3912 } 3913 3914 /* mtmsr */ 3915 #if defined(TARGET_PPC64) 3916 static void gen_mtmsrd(DisasContext *ctx) 3917 { 3918 CHK_SV; 3919 3920 #if !defined(CONFIG_USER_ONLY) 3921 if (ctx->opcode & 0x00010000) { 3922 /* Special form that does not need any synchronisation */ 3923 TCGv t0 = tcg_temp_new(); 3924 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 3925 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 3926 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 3927 tcg_temp_free(t0); 3928 } else { 3929 /* XXX: we need to update nip before the store 3930 * if we enter power saving mode, we will exit the loop 3931 * directly from ppc_store_msr 3932 */ 3933 gen_update_nip(ctx, ctx->nip); 3934 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 3935 /* Must stop the translation as machine state (may have) changed */ 3936 /* Note that mtmsr is not always defined as context-synchronizing */ 3937 gen_stop_exception(ctx); 3938 } 3939 #endif /* !defined(CONFIG_USER_ONLY) */ 3940 } 3941 #endif /* defined(TARGET_PPC64) */ 3942 3943 static void gen_mtmsr(DisasContext *ctx) 3944 { 3945 CHK_SV; 3946 3947 #if !defined(CONFIG_USER_ONLY) 3948 if (ctx->opcode & 0x00010000) { 3949 /* Special form that does not need any synchronisation */ 3950 TCGv t0 = tcg_temp_new(); 3951 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 3952 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 3953 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 3954 tcg_temp_free(t0); 3955 } else { 3956 TCGv msr = tcg_temp_new(); 3957 3958 /* XXX: we need to update nip before the store 3959 * if we enter power saving mode, we will exit the loop 3960 * directly from ppc_store_msr 3961 */ 3962 gen_update_nip(ctx, ctx->nip); 3963 #if defined(TARGET_PPC64) 3964 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 3965 #else 3966 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 3967 #endif 3968 gen_helper_store_msr(cpu_env, msr); 3969 tcg_temp_free(msr); 3970 /* Must stop the translation as machine state (may have) changed */ 3971 /* Note that mtmsr is not always defined as context-synchronizing */ 3972 gen_stop_exception(ctx); 3973 } 3974 #endif 3975 } 3976 3977 /* mtspr */ 3978 static void gen_mtspr(DisasContext *ctx) 3979 { 3980 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 3981 uint32_t sprn = SPR(ctx->opcode); 3982 3983 #if defined(CONFIG_USER_ONLY) 3984 write_cb = ctx->spr_cb[sprn].uea_write; 3985 #else 3986 if (ctx->pr) { 3987 write_cb = ctx->spr_cb[sprn].uea_write; 3988 } else if (ctx->hv) { 3989 write_cb = ctx->spr_cb[sprn].hea_write; 3990 } else { 3991 write_cb = ctx->spr_cb[sprn].oea_write; 3992 } 3993 #endif 3994 if (likely(write_cb != NULL)) { 3995 if (likely(write_cb != SPR_NOACCESS)) { 3996 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 3997 } else { 3998 /* Privilege exception */ 3999 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at " 4000 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4001 if (qemu_log_separate()) { 4002 qemu_log("Trying to write privileged spr %d (0x%03x) at " 4003 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4004 } 4005 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4006 } 4007 } else { 4008 /* ISA 2.07 defines these as no-ops */ 4009 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4010 (sprn >= 808 && sprn <= 811)) { 4011 /* This is a nop */ 4012 return; 4013 } 4014 4015 /* Not defined */ 4016 if (qemu_log_separate()) { 4017 qemu_log("Trying to write invalid spr %d (0x%03x) at " 4018 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4019 } 4020 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at " 4021 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4022 4023 4024 /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4025 * it can generate a priv, a hv emu or a no-op 4026 */ 4027 if (sprn & 0x10) { 4028 if (ctx->pr) { 4029 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4030 } 4031 } else { 4032 if (ctx->pr || sprn == 0) { 4033 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4034 } 4035 } 4036 } 4037 } 4038 4039 #if defined(TARGET_PPC64) 4040 /* setb */ 4041 static void gen_setb(DisasContext *ctx) 4042 { 4043 TCGv_i32 t0 = tcg_temp_new_i32(); 4044 TCGv_i32 t8 = tcg_temp_new_i32(); 4045 TCGv_i32 tm1 = tcg_temp_new_i32(); 4046 int crf = crfS(ctx->opcode); 4047 4048 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4049 tcg_gen_movi_i32(t8, 8); 4050 tcg_gen_movi_i32(tm1, -1); 4051 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4052 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4053 4054 tcg_temp_free_i32(t0); 4055 tcg_temp_free_i32(t8); 4056 tcg_temp_free_i32(tm1); 4057 } 4058 #endif 4059 4060 /*** Cache management ***/ 4061 4062 /* dcbf */ 4063 static void gen_dcbf(DisasContext *ctx) 4064 { 4065 /* XXX: specification says this is treated as a load by the MMU */ 4066 TCGv t0; 4067 gen_set_access_type(ctx, ACCESS_CACHE); 4068 t0 = tcg_temp_new(); 4069 gen_addr_reg_index(ctx, t0); 4070 gen_qemu_ld8u(ctx, t0, t0); 4071 tcg_temp_free(t0); 4072 } 4073 4074 /* dcbi (Supervisor only) */ 4075 static void gen_dcbi(DisasContext *ctx) 4076 { 4077 #if defined(CONFIG_USER_ONLY) 4078 GEN_PRIV; 4079 #else 4080 TCGv EA, val; 4081 4082 CHK_SV; 4083 EA = tcg_temp_new(); 4084 gen_set_access_type(ctx, ACCESS_CACHE); 4085 gen_addr_reg_index(ctx, EA); 4086 val = tcg_temp_new(); 4087 /* XXX: specification says this should be treated as a store by the MMU */ 4088 gen_qemu_ld8u(ctx, val, EA); 4089 gen_qemu_st8(ctx, val, EA); 4090 tcg_temp_free(val); 4091 tcg_temp_free(EA); 4092 #endif /* defined(CONFIG_USER_ONLY) */ 4093 } 4094 4095 /* dcdst */ 4096 static void gen_dcbst(DisasContext *ctx) 4097 { 4098 /* XXX: specification say this is treated as a load by the MMU */ 4099 TCGv t0; 4100 gen_set_access_type(ctx, ACCESS_CACHE); 4101 t0 = tcg_temp_new(); 4102 gen_addr_reg_index(ctx, t0); 4103 gen_qemu_ld8u(ctx, t0, t0); 4104 tcg_temp_free(t0); 4105 } 4106 4107 /* dcbt */ 4108 static void gen_dcbt(DisasContext *ctx) 4109 { 4110 /* interpreted as no-op */ 4111 /* XXX: specification say this is treated as a load by the MMU 4112 * but does not generate any exception 4113 */ 4114 } 4115 4116 /* dcbtst */ 4117 static void gen_dcbtst(DisasContext *ctx) 4118 { 4119 /* interpreted as no-op */ 4120 /* XXX: specification say this is treated as a load by the MMU 4121 * but does not generate any exception 4122 */ 4123 } 4124 4125 /* dcbtls */ 4126 static void gen_dcbtls(DisasContext *ctx) 4127 { 4128 /* Always fails locking the cache */ 4129 TCGv t0 = tcg_temp_new(); 4130 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4131 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4132 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4133 tcg_temp_free(t0); 4134 } 4135 4136 /* dcbz */ 4137 static void gen_dcbz(DisasContext *ctx) 4138 { 4139 TCGv tcgv_addr; 4140 TCGv_i32 tcgv_op; 4141 4142 gen_set_access_type(ctx, ACCESS_CACHE); 4143 tcgv_addr = tcg_temp_new(); 4144 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4145 gen_addr_reg_index(ctx, tcgv_addr); 4146 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4147 tcg_temp_free(tcgv_addr); 4148 tcg_temp_free_i32(tcgv_op); 4149 } 4150 4151 /* dst / dstt */ 4152 static void gen_dst(DisasContext *ctx) 4153 { 4154 if (rA(ctx->opcode) == 0) { 4155 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4156 } else { 4157 /* interpreted as no-op */ 4158 } 4159 } 4160 4161 /* dstst /dststt */ 4162 static void gen_dstst(DisasContext *ctx) 4163 { 4164 if (rA(ctx->opcode) == 0) { 4165 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4166 } else { 4167 /* interpreted as no-op */ 4168 } 4169 4170 } 4171 4172 /* dss / dssall */ 4173 static void gen_dss(DisasContext *ctx) 4174 { 4175 /* interpreted as no-op */ 4176 } 4177 4178 /* icbi */ 4179 static void gen_icbi(DisasContext *ctx) 4180 { 4181 TCGv t0; 4182 gen_set_access_type(ctx, ACCESS_CACHE); 4183 t0 = tcg_temp_new(); 4184 gen_addr_reg_index(ctx, t0); 4185 gen_helper_icbi(cpu_env, t0); 4186 tcg_temp_free(t0); 4187 } 4188 4189 /* Optional: */ 4190 /* dcba */ 4191 static void gen_dcba(DisasContext *ctx) 4192 { 4193 /* interpreted as no-op */ 4194 /* XXX: specification say this is treated as a store by the MMU 4195 * but does not generate any exception 4196 */ 4197 } 4198 4199 /*** Segment register manipulation ***/ 4200 /* Supervisor only: */ 4201 4202 /* mfsr */ 4203 static void gen_mfsr(DisasContext *ctx) 4204 { 4205 #if defined(CONFIG_USER_ONLY) 4206 GEN_PRIV; 4207 #else 4208 TCGv t0; 4209 4210 CHK_SV; 4211 t0 = tcg_const_tl(SR(ctx->opcode)); 4212 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4213 tcg_temp_free(t0); 4214 #endif /* defined(CONFIG_USER_ONLY) */ 4215 } 4216 4217 /* mfsrin */ 4218 static void gen_mfsrin(DisasContext *ctx) 4219 { 4220 #if defined(CONFIG_USER_ONLY) 4221 GEN_PRIV; 4222 #else 4223 TCGv t0; 4224 4225 CHK_SV; 4226 t0 = tcg_temp_new(); 4227 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4228 tcg_gen_andi_tl(t0, t0, 0xF); 4229 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4230 tcg_temp_free(t0); 4231 #endif /* defined(CONFIG_USER_ONLY) */ 4232 } 4233 4234 /* mtsr */ 4235 static void gen_mtsr(DisasContext *ctx) 4236 { 4237 #if defined(CONFIG_USER_ONLY) 4238 GEN_PRIV; 4239 #else 4240 TCGv t0; 4241 4242 CHK_SV; 4243 t0 = tcg_const_tl(SR(ctx->opcode)); 4244 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4245 tcg_temp_free(t0); 4246 #endif /* defined(CONFIG_USER_ONLY) */ 4247 } 4248 4249 /* mtsrin */ 4250 static void gen_mtsrin(DisasContext *ctx) 4251 { 4252 #if defined(CONFIG_USER_ONLY) 4253 GEN_PRIV; 4254 #else 4255 TCGv t0; 4256 CHK_SV; 4257 4258 t0 = tcg_temp_new(); 4259 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4260 tcg_gen_andi_tl(t0, t0, 0xF); 4261 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4262 tcg_temp_free(t0); 4263 #endif /* defined(CONFIG_USER_ONLY) */ 4264 } 4265 4266 #if defined(TARGET_PPC64) 4267 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4268 4269 /* mfsr */ 4270 static void gen_mfsr_64b(DisasContext *ctx) 4271 { 4272 #if defined(CONFIG_USER_ONLY) 4273 GEN_PRIV; 4274 #else 4275 TCGv t0; 4276 4277 CHK_SV; 4278 t0 = tcg_const_tl(SR(ctx->opcode)); 4279 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4280 tcg_temp_free(t0); 4281 #endif /* defined(CONFIG_USER_ONLY) */ 4282 } 4283 4284 /* mfsrin */ 4285 static void gen_mfsrin_64b(DisasContext *ctx) 4286 { 4287 #if defined(CONFIG_USER_ONLY) 4288 GEN_PRIV; 4289 #else 4290 TCGv t0; 4291 4292 CHK_SV; 4293 t0 = tcg_temp_new(); 4294 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4295 tcg_gen_andi_tl(t0, t0, 0xF); 4296 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4297 tcg_temp_free(t0); 4298 #endif /* defined(CONFIG_USER_ONLY) */ 4299 } 4300 4301 /* mtsr */ 4302 static void gen_mtsr_64b(DisasContext *ctx) 4303 { 4304 #if defined(CONFIG_USER_ONLY) 4305 GEN_PRIV; 4306 #else 4307 TCGv t0; 4308 4309 CHK_SV; 4310 t0 = tcg_const_tl(SR(ctx->opcode)); 4311 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4312 tcg_temp_free(t0); 4313 #endif /* defined(CONFIG_USER_ONLY) */ 4314 } 4315 4316 /* mtsrin */ 4317 static void gen_mtsrin_64b(DisasContext *ctx) 4318 { 4319 #if defined(CONFIG_USER_ONLY) 4320 GEN_PRIV; 4321 #else 4322 TCGv t0; 4323 4324 CHK_SV; 4325 t0 = tcg_temp_new(); 4326 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); 4327 tcg_gen_andi_tl(t0, t0, 0xF); 4328 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4329 tcg_temp_free(t0); 4330 #endif /* defined(CONFIG_USER_ONLY) */ 4331 } 4332 4333 /* slbmte */ 4334 static void gen_slbmte(DisasContext *ctx) 4335 { 4336 #if defined(CONFIG_USER_ONLY) 4337 GEN_PRIV; 4338 #else 4339 CHK_SV; 4340 4341 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4342 cpu_gpr[rS(ctx->opcode)]); 4343 #endif /* defined(CONFIG_USER_ONLY) */ 4344 } 4345 4346 static void gen_slbmfee(DisasContext *ctx) 4347 { 4348 #if defined(CONFIG_USER_ONLY) 4349 GEN_PRIV; 4350 #else 4351 CHK_SV; 4352 4353 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4354 cpu_gpr[rB(ctx->opcode)]); 4355 #endif /* defined(CONFIG_USER_ONLY) */ 4356 } 4357 4358 static void gen_slbmfev(DisasContext *ctx) 4359 { 4360 #if defined(CONFIG_USER_ONLY) 4361 GEN_PRIV; 4362 #else 4363 CHK_SV; 4364 4365 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4366 cpu_gpr[rB(ctx->opcode)]); 4367 #endif /* defined(CONFIG_USER_ONLY) */ 4368 } 4369 4370 static void gen_slbfee_(DisasContext *ctx) 4371 { 4372 #if defined(CONFIG_USER_ONLY) 4373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4374 #else 4375 TCGLabel *l1, *l2; 4376 4377 if (unlikely(ctx->pr)) { 4378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4379 return; 4380 } 4381 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4382 cpu_gpr[rB(ctx->opcode)]); 4383 l1 = gen_new_label(); 4384 l2 = gen_new_label(); 4385 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4386 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4387 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4388 tcg_gen_br(l2); 4389 gen_set_label(l1); 4390 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4391 gen_set_label(l2); 4392 #endif 4393 } 4394 #endif /* defined(TARGET_PPC64) */ 4395 4396 /*** Lookaside buffer management ***/ 4397 /* Optional & supervisor only: */ 4398 4399 /* tlbia */ 4400 static void gen_tlbia(DisasContext *ctx) 4401 { 4402 #if defined(CONFIG_USER_ONLY) 4403 GEN_PRIV; 4404 #else 4405 CHK_HV; 4406 4407 gen_helper_tlbia(cpu_env); 4408 #endif /* defined(CONFIG_USER_ONLY) */ 4409 } 4410 4411 /* tlbiel */ 4412 static void gen_tlbiel(DisasContext *ctx) 4413 { 4414 #if defined(CONFIG_USER_ONLY) 4415 GEN_PRIV; 4416 #else 4417 CHK_SV; 4418 4419 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4420 #endif /* defined(CONFIG_USER_ONLY) */ 4421 } 4422 4423 /* tlbie */ 4424 static void gen_tlbie(DisasContext *ctx) 4425 { 4426 #if defined(CONFIG_USER_ONLY) 4427 GEN_PRIV; 4428 #else 4429 TCGv_i32 t1; 4430 CHK_HV; 4431 4432 if (NARROW_MODE(ctx)) { 4433 TCGv t0 = tcg_temp_new(); 4434 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4435 gen_helper_tlbie(cpu_env, t0); 4436 tcg_temp_free(t0); 4437 } else { 4438 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4439 } 4440 t1 = tcg_temp_new_i32(); 4441 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4442 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4443 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4444 tcg_temp_free_i32(t1); 4445 #endif /* defined(CONFIG_USER_ONLY) */ 4446 } 4447 4448 /* tlbsync */ 4449 static void gen_tlbsync(DisasContext *ctx) 4450 { 4451 #if defined(CONFIG_USER_ONLY) 4452 GEN_PRIV; 4453 #else 4454 CHK_HV; 4455 4456 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4457 if (ctx->insns_flags & PPC_BOOKE) { 4458 gen_check_tlb_flush(ctx, true); 4459 } 4460 #endif /* defined(CONFIG_USER_ONLY) */ 4461 } 4462 4463 #if defined(TARGET_PPC64) 4464 /* slbia */ 4465 static void gen_slbia(DisasContext *ctx) 4466 { 4467 #if defined(CONFIG_USER_ONLY) 4468 GEN_PRIV; 4469 #else 4470 CHK_SV; 4471 4472 gen_helper_slbia(cpu_env); 4473 #endif /* defined(CONFIG_USER_ONLY) */ 4474 } 4475 4476 /* slbie */ 4477 static void gen_slbie(DisasContext *ctx) 4478 { 4479 #if defined(CONFIG_USER_ONLY) 4480 GEN_PRIV; 4481 #else 4482 CHK_SV; 4483 4484 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4485 #endif /* defined(CONFIG_USER_ONLY) */ 4486 } 4487 4488 /* slbieg */ 4489 static void gen_slbieg(DisasContext *ctx) 4490 { 4491 #if defined(CONFIG_USER_ONLY) 4492 GEN_PRIV; 4493 #else 4494 CHK_SV; 4495 4496 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4497 #endif /* defined(CONFIG_USER_ONLY) */ 4498 } 4499 4500 /* slbsync */ 4501 static void gen_slbsync(DisasContext *ctx) 4502 { 4503 #if defined(CONFIG_USER_ONLY) 4504 GEN_PRIV; 4505 #else 4506 CHK_SV; 4507 gen_check_tlb_flush(ctx, true); 4508 #endif /* defined(CONFIG_USER_ONLY) */ 4509 } 4510 4511 #endif /* defined(TARGET_PPC64) */ 4512 4513 /*** External control ***/ 4514 /* Optional: */ 4515 4516 /* eciwx */ 4517 static void gen_eciwx(DisasContext *ctx) 4518 { 4519 TCGv t0; 4520 /* Should check EAR[E] ! */ 4521 gen_set_access_type(ctx, ACCESS_EXT); 4522 t0 = tcg_temp_new(); 4523 gen_addr_reg_index(ctx, t0); 4524 gen_check_align(ctx, t0, 0x03); 4525 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4526 tcg_temp_free(t0); 4527 } 4528 4529 /* ecowx */ 4530 static void gen_ecowx(DisasContext *ctx) 4531 { 4532 TCGv t0; 4533 /* Should check EAR[E] ! */ 4534 gen_set_access_type(ctx, ACCESS_EXT); 4535 t0 = tcg_temp_new(); 4536 gen_addr_reg_index(ctx, t0); 4537 gen_check_align(ctx, t0, 0x03); 4538 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4539 tcg_temp_free(t0); 4540 } 4541 4542 /* PowerPC 601 specific instructions */ 4543 4544 /* abs - abs. */ 4545 static void gen_abs(DisasContext *ctx) 4546 { 4547 TCGLabel *l1 = gen_new_label(); 4548 TCGLabel *l2 = gen_new_label(); 4549 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); 4550 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4551 tcg_gen_br(l2); 4552 gen_set_label(l1); 4553 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4554 gen_set_label(l2); 4555 if (unlikely(Rc(ctx->opcode) != 0)) 4556 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4557 } 4558 4559 /* abso - abso. */ 4560 static void gen_abso(DisasContext *ctx) 4561 { 4562 TCGLabel *l1 = gen_new_label(); 4563 TCGLabel *l2 = gen_new_label(); 4564 TCGLabel *l3 = gen_new_label(); 4565 /* Start with XER OV disabled, the most likely case */ 4566 tcg_gen_movi_tl(cpu_ov, 0); 4567 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); 4568 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); 4569 tcg_gen_movi_tl(cpu_ov, 1); 4570 tcg_gen_movi_tl(cpu_so, 1); 4571 tcg_gen_br(l2); 4572 gen_set_label(l1); 4573 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4574 tcg_gen_br(l3); 4575 gen_set_label(l2); 4576 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4577 gen_set_label(l3); 4578 if (unlikely(Rc(ctx->opcode) != 0)) 4579 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4580 } 4581 4582 /* clcs */ 4583 static void gen_clcs(DisasContext *ctx) 4584 { 4585 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 4586 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4587 tcg_temp_free_i32(t0); 4588 /* Rc=1 sets CR0 to an undefined state */ 4589 } 4590 4591 /* div - div. */ 4592 static void gen_div(DisasContext *ctx) 4593 { 4594 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4595 cpu_gpr[rB(ctx->opcode)]); 4596 if (unlikely(Rc(ctx->opcode) != 0)) 4597 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4598 } 4599 4600 /* divo - divo. */ 4601 static void gen_divo(DisasContext *ctx) 4602 { 4603 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4604 cpu_gpr[rB(ctx->opcode)]); 4605 if (unlikely(Rc(ctx->opcode) != 0)) 4606 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4607 } 4608 4609 /* divs - divs. */ 4610 static void gen_divs(DisasContext *ctx) 4611 { 4612 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4613 cpu_gpr[rB(ctx->opcode)]); 4614 if (unlikely(Rc(ctx->opcode) != 0)) 4615 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4616 } 4617 4618 /* divso - divso. */ 4619 static void gen_divso(DisasContext *ctx) 4620 { 4621 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 4622 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4623 if (unlikely(Rc(ctx->opcode) != 0)) 4624 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4625 } 4626 4627 /* doz - doz. */ 4628 static void gen_doz(DisasContext *ctx) 4629 { 4630 TCGLabel *l1 = gen_new_label(); 4631 TCGLabel *l2 = gen_new_label(); 4632 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4633 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4634 tcg_gen_br(l2); 4635 gen_set_label(l1); 4636 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4637 gen_set_label(l2); 4638 if (unlikely(Rc(ctx->opcode) != 0)) 4639 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4640 } 4641 4642 /* dozo - dozo. */ 4643 static void gen_dozo(DisasContext *ctx) 4644 { 4645 TCGLabel *l1 = gen_new_label(); 4646 TCGLabel *l2 = gen_new_label(); 4647 TCGv t0 = tcg_temp_new(); 4648 TCGv t1 = tcg_temp_new(); 4649 TCGv t2 = tcg_temp_new(); 4650 /* Start with XER OV disabled, the most likely case */ 4651 tcg_gen_movi_tl(cpu_ov, 0); 4652 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4653 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4654 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4655 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 4656 tcg_gen_andc_tl(t1, t1, t2); 4657 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 4658 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 4659 tcg_gen_movi_tl(cpu_ov, 1); 4660 tcg_gen_movi_tl(cpu_so, 1); 4661 tcg_gen_br(l2); 4662 gen_set_label(l1); 4663 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4664 gen_set_label(l2); 4665 tcg_temp_free(t0); 4666 tcg_temp_free(t1); 4667 tcg_temp_free(t2); 4668 if (unlikely(Rc(ctx->opcode) != 0)) 4669 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4670 } 4671 4672 /* dozi */ 4673 static void gen_dozi(DisasContext *ctx) 4674 { 4675 target_long simm = SIMM(ctx->opcode); 4676 TCGLabel *l1 = gen_new_label(); 4677 TCGLabel *l2 = gen_new_label(); 4678 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 4679 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 4680 tcg_gen_br(l2); 4681 gen_set_label(l1); 4682 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4683 gen_set_label(l2); 4684 if (unlikely(Rc(ctx->opcode) != 0)) 4685 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4686 } 4687 4688 /* lscbx - lscbx. */ 4689 static void gen_lscbx(DisasContext *ctx) 4690 { 4691 TCGv t0 = tcg_temp_new(); 4692 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 4693 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 4694 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 4695 4696 gen_addr_reg_index(ctx, t0); 4697 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 4698 tcg_temp_free_i32(t1); 4699 tcg_temp_free_i32(t2); 4700 tcg_temp_free_i32(t3); 4701 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 4702 tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 4703 if (unlikely(Rc(ctx->opcode) != 0)) 4704 gen_set_Rc0(ctx, t0); 4705 tcg_temp_free(t0); 4706 } 4707 4708 /* maskg - maskg. */ 4709 static void gen_maskg(DisasContext *ctx) 4710 { 4711 TCGLabel *l1 = gen_new_label(); 4712 TCGv t0 = tcg_temp_new(); 4713 TCGv t1 = tcg_temp_new(); 4714 TCGv t2 = tcg_temp_new(); 4715 TCGv t3 = tcg_temp_new(); 4716 tcg_gen_movi_tl(t3, 0xFFFFFFFF); 4717 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4718 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 4719 tcg_gen_addi_tl(t2, t0, 1); 4720 tcg_gen_shr_tl(t2, t3, t2); 4721 tcg_gen_shr_tl(t3, t3, t1); 4722 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 4723 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 4724 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4725 gen_set_label(l1); 4726 tcg_temp_free(t0); 4727 tcg_temp_free(t1); 4728 tcg_temp_free(t2); 4729 tcg_temp_free(t3); 4730 if (unlikely(Rc(ctx->opcode) != 0)) 4731 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4732 } 4733 4734 /* maskir - maskir. */ 4735 static void gen_maskir(DisasContext *ctx) 4736 { 4737 TCGv t0 = tcg_temp_new(); 4738 TCGv t1 = tcg_temp_new(); 4739 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4740 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4741 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4742 tcg_temp_free(t0); 4743 tcg_temp_free(t1); 4744 if (unlikely(Rc(ctx->opcode) != 0)) 4745 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4746 } 4747 4748 /* mul - mul. */ 4749 static void gen_mul(DisasContext *ctx) 4750 { 4751 TCGv_i64 t0 = tcg_temp_new_i64(); 4752 TCGv_i64 t1 = tcg_temp_new_i64(); 4753 TCGv t2 = tcg_temp_new(); 4754 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4755 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4756 tcg_gen_mul_i64(t0, t0, t1); 4757 tcg_gen_trunc_i64_tl(t2, t0); 4758 gen_store_spr(SPR_MQ, t2); 4759 tcg_gen_shri_i64(t1, t0, 32); 4760 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4761 tcg_temp_free_i64(t0); 4762 tcg_temp_free_i64(t1); 4763 tcg_temp_free(t2); 4764 if (unlikely(Rc(ctx->opcode) != 0)) 4765 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4766 } 4767 4768 /* mulo - mulo. */ 4769 static void gen_mulo(DisasContext *ctx) 4770 { 4771 TCGLabel *l1 = gen_new_label(); 4772 TCGv_i64 t0 = tcg_temp_new_i64(); 4773 TCGv_i64 t1 = tcg_temp_new_i64(); 4774 TCGv t2 = tcg_temp_new(); 4775 /* Start with XER OV disabled, the most likely case */ 4776 tcg_gen_movi_tl(cpu_ov, 0); 4777 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4778 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4779 tcg_gen_mul_i64(t0, t0, t1); 4780 tcg_gen_trunc_i64_tl(t2, t0); 4781 gen_store_spr(SPR_MQ, t2); 4782 tcg_gen_shri_i64(t1, t0, 32); 4783 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4784 tcg_gen_ext32s_i64(t1, t0); 4785 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 4786 tcg_gen_movi_tl(cpu_ov, 1); 4787 tcg_gen_movi_tl(cpu_so, 1); 4788 gen_set_label(l1); 4789 tcg_temp_free_i64(t0); 4790 tcg_temp_free_i64(t1); 4791 tcg_temp_free(t2); 4792 if (unlikely(Rc(ctx->opcode) != 0)) 4793 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4794 } 4795 4796 /* nabs - nabs. */ 4797 static void gen_nabs(DisasContext *ctx) 4798 { 4799 TCGLabel *l1 = gen_new_label(); 4800 TCGLabel *l2 = gen_new_label(); 4801 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4802 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4803 tcg_gen_br(l2); 4804 gen_set_label(l1); 4805 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4806 gen_set_label(l2); 4807 if (unlikely(Rc(ctx->opcode) != 0)) 4808 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4809 } 4810 4811 /* nabso - nabso. */ 4812 static void gen_nabso(DisasContext *ctx) 4813 { 4814 TCGLabel *l1 = gen_new_label(); 4815 TCGLabel *l2 = gen_new_label(); 4816 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4817 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4818 tcg_gen_br(l2); 4819 gen_set_label(l1); 4820 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4821 gen_set_label(l2); 4822 /* nabs never overflows */ 4823 tcg_gen_movi_tl(cpu_ov, 0); 4824 if (unlikely(Rc(ctx->opcode) != 0)) 4825 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4826 } 4827 4828 /* rlmi - rlmi. */ 4829 static void gen_rlmi(DisasContext *ctx) 4830 { 4831 uint32_t mb = MB(ctx->opcode); 4832 uint32_t me = ME(ctx->opcode); 4833 TCGv t0 = tcg_temp_new(); 4834 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4835 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4836 tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 4837 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); 4838 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 4839 tcg_temp_free(t0); 4840 if (unlikely(Rc(ctx->opcode) != 0)) 4841 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4842 } 4843 4844 /* rrib - rrib. */ 4845 static void gen_rrib(DisasContext *ctx) 4846 { 4847 TCGv t0 = tcg_temp_new(); 4848 TCGv t1 = tcg_temp_new(); 4849 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4850 tcg_gen_movi_tl(t1, 0x80000000); 4851 tcg_gen_shr_tl(t1, t1, t0); 4852 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4853 tcg_gen_and_tl(t0, t0, t1); 4854 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 4855 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4856 tcg_temp_free(t0); 4857 tcg_temp_free(t1); 4858 if (unlikely(Rc(ctx->opcode) != 0)) 4859 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4860 } 4861 4862 /* sle - sle. */ 4863 static void gen_sle(DisasContext *ctx) 4864 { 4865 TCGv t0 = tcg_temp_new(); 4866 TCGv t1 = tcg_temp_new(); 4867 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 4868 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 4869 tcg_gen_subfi_tl(t1, 32, t1); 4870 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 4871 tcg_gen_or_tl(t1, t0, t1); 4872 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4873 gen_store_spr(SPR_MQ, t1); 4874 tcg_temp_free(t0); 4875 tcg_temp_free(t1); 4876 if (unlikely(Rc(ctx->opcode) != 0)) 4877 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4878 } 4879 4880 /* sleq - sleq. */ 4881 static void gen_sleq(DisasContext *ctx) 4882 { 4883 TCGv t0 = tcg_temp_new(); 4884 TCGv t1 = tcg_temp_new(); 4885 TCGv t2 = tcg_temp_new(); 4886 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4887 tcg_gen_movi_tl(t2, 0xFFFFFFFF); 4888 tcg_gen_shl_tl(t2, t2, t0); 4889 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4890 gen_load_spr(t1, SPR_MQ); 4891 gen_store_spr(SPR_MQ, t0); 4892 tcg_gen_and_tl(t0, t0, t2); 4893 tcg_gen_andc_tl(t1, t1, t2); 4894 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4895 tcg_temp_free(t0); 4896 tcg_temp_free(t1); 4897 tcg_temp_free(t2); 4898 if (unlikely(Rc(ctx->opcode) != 0)) 4899 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4900 } 4901 4902 /* sliq - sliq. */ 4903 static void gen_sliq(DisasContext *ctx) 4904 { 4905 int sh = SH(ctx->opcode); 4906 TCGv t0 = tcg_temp_new(); 4907 TCGv t1 = tcg_temp_new(); 4908 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 4909 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 4910 tcg_gen_or_tl(t1, t0, t1); 4911 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4912 gen_store_spr(SPR_MQ, t1); 4913 tcg_temp_free(t0); 4914 tcg_temp_free(t1); 4915 if (unlikely(Rc(ctx->opcode) != 0)) 4916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4917 } 4918 4919 /* slliq - slliq. */ 4920 static void gen_slliq(DisasContext *ctx) 4921 { 4922 int sh = SH(ctx->opcode); 4923 TCGv t0 = tcg_temp_new(); 4924 TCGv t1 = tcg_temp_new(); 4925 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 4926 gen_load_spr(t1, SPR_MQ); 4927 gen_store_spr(SPR_MQ, t0); 4928 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 4929 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 4930 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4931 tcg_temp_free(t0); 4932 tcg_temp_free(t1); 4933 if (unlikely(Rc(ctx->opcode) != 0)) 4934 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4935 } 4936 4937 /* sllq - sllq. */ 4938 static void gen_sllq(DisasContext *ctx) 4939 { 4940 TCGLabel *l1 = gen_new_label(); 4941 TCGLabel *l2 = gen_new_label(); 4942 TCGv t0 = tcg_temp_local_new(); 4943 TCGv t1 = tcg_temp_local_new(); 4944 TCGv t2 = tcg_temp_local_new(); 4945 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 4946 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 4947 tcg_gen_shl_tl(t1, t1, t2); 4948 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 4949 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 4950 gen_load_spr(t0, SPR_MQ); 4951 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4952 tcg_gen_br(l2); 4953 gen_set_label(l1); 4954 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 4955 gen_load_spr(t2, SPR_MQ); 4956 tcg_gen_andc_tl(t1, t2, t1); 4957 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4958 gen_set_label(l2); 4959 tcg_temp_free(t0); 4960 tcg_temp_free(t1); 4961 tcg_temp_free(t2); 4962 if (unlikely(Rc(ctx->opcode) != 0)) 4963 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4964 } 4965 4966 /* slq - slq. */ 4967 static void gen_slq(DisasContext *ctx) 4968 { 4969 TCGLabel *l1 = gen_new_label(); 4970 TCGv t0 = tcg_temp_new(); 4971 TCGv t1 = tcg_temp_new(); 4972 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 4973 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 4974 tcg_gen_subfi_tl(t1, 32, t1); 4975 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 4976 tcg_gen_or_tl(t1, t0, t1); 4977 gen_store_spr(SPR_MQ, t1); 4978 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 4979 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4980 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 4981 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 4982 gen_set_label(l1); 4983 tcg_temp_free(t0); 4984 tcg_temp_free(t1); 4985 if (unlikely(Rc(ctx->opcode) != 0)) 4986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4987 } 4988 4989 /* sraiq - sraiq. */ 4990 static void gen_sraiq(DisasContext *ctx) 4991 { 4992 int sh = SH(ctx->opcode); 4993 TCGLabel *l1 = gen_new_label(); 4994 TCGv t0 = tcg_temp_new(); 4995 TCGv t1 = tcg_temp_new(); 4996 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 4997 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 4998 tcg_gen_or_tl(t0, t0, t1); 4999 gen_store_spr(SPR_MQ, t0); 5000 tcg_gen_movi_tl(cpu_ca, 0); 5001 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5002 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5003 tcg_gen_movi_tl(cpu_ca, 1); 5004 gen_set_label(l1); 5005 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5006 tcg_temp_free(t0); 5007 tcg_temp_free(t1); 5008 if (unlikely(Rc(ctx->opcode) != 0)) 5009 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5010 } 5011 5012 /* sraq - sraq. */ 5013 static void gen_sraq(DisasContext *ctx) 5014 { 5015 TCGLabel *l1 = gen_new_label(); 5016 TCGLabel *l2 = gen_new_label(); 5017 TCGv t0 = tcg_temp_new(); 5018 TCGv t1 = tcg_temp_local_new(); 5019 TCGv t2 = tcg_temp_local_new(); 5020 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5021 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5022 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5023 tcg_gen_subfi_tl(t2, 32, t2); 5024 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5025 tcg_gen_or_tl(t0, t0, t2); 5026 gen_store_spr(SPR_MQ, t0); 5027 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5028 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5029 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5030 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5031 gen_set_label(l1); 5032 tcg_temp_free(t0); 5033 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5034 tcg_gen_movi_tl(cpu_ca, 0); 5035 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5036 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5037 tcg_gen_movi_tl(cpu_ca, 1); 5038 gen_set_label(l2); 5039 tcg_temp_free(t1); 5040 tcg_temp_free(t2); 5041 if (unlikely(Rc(ctx->opcode) != 0)) 5042 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5043 } 5044 5045 /* sre - sre. */ 5046 static void gen_sre(DisasContext *ctx) 5047 { 5048 TCGv t0 = tcg_temp_new(); 5049 TCGv t1 = tcg_temp_new(); 5050 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5051 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5052 tcg_gen_subfi_tl(t1, 32, t1); 5053 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5054 tcg_gen_or_tl(t1, t0, t1); 5055 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5056 gen_store_spr(SPR_MQ, t1); 5057 tcg_temp_free(t0); 5058 tcg_temp_free(t1); 5059 if (unlikely(Rc(ctx->opcode) != 0)) 5060 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5061 } 5062 5063 /* srea - srea. */ 5064 static void gen_srea(DisasContext *ctx) 5065 { 5066 TCGv t0 = tcg_temp_new(); 5067 TCGv t1 = tcg_temp_new(); 5068 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5069 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5070 gen_store_spr(SPR_MQ, t0); 5071 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5072 tcg_temp_free(t0); 5073 tcg_temp_free(t1); 5074 if (unlikely(Rc(ctx->opcode) != 0)) 5075 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5076 } 5077 5078 /* sreq */ 5079 static void gen_sreq(DisasContext *ctx) 5080 { 5081 TCGv t0 = tcg_temp_new(); 5082 TCGv t1 = tcg_temp_new(); 5083 TCGv t2 = tcg_temp_new(); 5084 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5085 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5086 tcg_gen_shr_tl(t1, t1, t0); 5087 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5088 gen_load_spr(t2, SPR_MQ); 5089 gen_store_spr(SPR_MQ, t0); 5090 tcg_gen_and_tl(t0, t0, t1); 5091 tcg_gen_andc_tl(t2, t2, t1); 5092 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5093 tcg_temp_free(t0); 5094 tcg_temp_free(t1); 5095 tcg_temp_free(t2); 5096 if (unlikely(Rc(ctx->opcode) != 0)) 5097 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5098 } 5099 5100 /* sriq */ 5101 static void gen_sriq(DisasContext *ctx) 5102 { 5103 int sh = SH(ctx->opcode); 5104 TCGv t0 = tcg_temp_new(); 5105 TCGv t1 = tcg_temp_new(); 5106 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5107 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5108 tcg_gen_or_tl(t1, t0, t1); 5109 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5110 gen_store_spr(SPR_MQ, t1); 5111 tcg_temp_free(t0); 5112 tcg_temp_free(t1); 5113 if (unlikely(Rc(ctx->opcode) != 0)) 5114 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5115 } 5116 5117 /* srliq */ 5118 static void gen_srliq(DisasContext *ctx) 5119 { 5120 int sh = SH(ctx->opcode); 5121 TCGv t0 = tcg_temp_new(); 5122 TCGv t1 = tcg_temp_new(); 5123 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5124 gen_load_spr(t1, SPR_MQ); 5125 gen_store_spr(SPR_MQ, t0); 5126 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5127 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5128 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5129 tcg_temp_free(t0); 5130 tcg_temp_free(t1); 5131 if (unlikely(Rc(ctx->opcode) != 0)) 5132 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5133 } 5134 5135 /* srlq */ 5136 static void gen_srlq(DisasContext *ctx) 5137 { 5138 TCGLabel *l1 = gen_new_label(); 5139 TCGLabel *l2 = gen_new_label(); 5140 TCGv t0 = tcg_temp_local_new(); 5141 TCGv t1 = tcg_temp_local_new(); 5142 TCGv t2 = tcg_temp_local_new(); 5143 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5144 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5145 tcg_gen_shr_tl(t2, t1, t2); 5146 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5147 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5148 gen_load_spr(t0, SPR_MQ); 5149 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5150 tcg_gen_br(l2); 5151 gen_set_label(l1); 5152 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5153 tcg_gen_and_tl(t0, t0, t2); 5154 gen_load_spr(t1, SPR_MQ); 5155 tcg_gen_andc_tl(t1, t1, t2); 5156 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5157 gen_set_label(l2); 5158 tcg_temp_free(t0); 5159 tcg_temp_free(t1); 5160 tcg_temp_free(t2); 5161 if (unlikely(Rc(ctx->opcode) != 0)) 5162 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5163 } 5164 5165 /* srq */ 5166 static void gen_srq(DisasContext *ctx) 5167 { 5168 TCGLabel *l1 = gen_new_label(); 5169 TCGv t0 = tcg_temp_new(); 5170 TCGv t1 = tcg_temp_new(); 5171 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5172 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5173 tcg_gen_subfi_tl(t1, 32, t1); 5174 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5175 tcg_gen_or_tl(t1, t0, t1); 5176 gen_store_spr(SPR_MQ, t1); 5177 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5178 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5179 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5180 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5181 gen_set_label(l1); 5182 tcg_temp_free(t0); 5183 tcg_temp_free(t1); 5184 if (unlikely(Rc(ctx->opcode) != 0)) 5185 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5186 } 5187 5188 /* PowerPC 602 specific instructions */ 5189 5190 /* dsa */ 5191 static void gen_dsa(DisasContext *ctx) 5192 { 5193 /* XXX: TODO */ 5194 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5195 } 5196 5197 /* esa */ 5198 static void gen_esa(DisasContext *ctx) 5199 { 5200 /* XXX: TODO */ 5201 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5202 } 5203 5204 /* mfrom */ 5205 static void gen_mfrom(DisasContext *ctx) 5206 { 5207 #if defined(CONFIG_USER_ONLY) 5208 GEN_PRIV; 5209 #else 5210 CHK_SV; 5211 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5212 #endif /* defined(CONFIG_USER_ONLY) */ 5213 } 5214 5215 /* 602 - 603 - G2 TLB management */ 5216 5217 /* tlbld */ 5218 static void gen_tlbld_6xx(DisasContext *ctx) 5219 { 5220 #if defined(CONFIG_USER_ONLY) 5221 GEN_PRIV; 5222 #else 5223 CHK_SV; 5224 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5225 #endif /* defined(CONFIG_USER_ONLY) */ 5226 } 5227 5228 /* tlbli */ 5229 static void gen_tlbli_6xx(DisasContext *ctx) 5230 { 5231 #if defined(CONFIG_USER_ONLY) 5232 GEN_PRIV; 5233 #else 5234 CHK_SV; 5235 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5236 #endif /* defined(CONFIG_USER_ONLY) */ 5237 } 5238 5239 /* 74xx TLB management */ 5240 5241 /* tlbld */ 5242 static void gen_tlbld_74xx(DisasContext *ctx) 5243 { 5244 #if defined(CONFIG_USER_ONLY) 5245 GEN_PRIV; 5246 #else 5247 CHK_SV; 5248 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5249 #endif /* defined(CONFIG_USER_ONLY) */ 5250 } 5251 5252 /* tlbli */ 5253 static void gen_tlbli_74xx(DisasContext *ctx) 5254 { 5255 #if defined(CONFIG_USER_ONLY) 5256 GEN_PRIV; 5257 #else 5258 CHK_SV; 5259 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5260 #endif /* defined(CONFIG_USER_ONLY) */ 5261 } 5262 5263 /* POWER instructions not in PowerPC 601 */ 5264 5265 /* clf */ 5266 static void gen_clf(DisasContext *ctx) 5267 { 5268 /* Cache line flush: implemented as no-op */ 5269 } 5270 5271 /* cli */ 5272 static void gen_cli(DisasContext *ctx) 5273 { 5274 #if defined(CONFIG_USER_ONLY) 5275 GEN_PRIV; 5276 #else 5277 /* Cache line invalidate: privileged and treated as no-op */ 5278 CHK_SV; 5279 #endif /* defined(CONFIG_USER_ONLY) */ 5280 } 5281 5282 /* dclst */ 5283 static void gen_dclst(DisasContext *ctx) 5284 { 5285 /* Data cache line store: treated as no-op */ 5286 } 5287 5288 static void gen_mfsri(DisasContext *ctx) 5289 { 5290 #if defined(CONFIG_USER_ONLY) 5291 GEN_PRIV; 5292 #else 5293 int ra = rA(ctx->opcode); 5294 int rd = rD(ctx->opcode); 5295 TCGv t0; 5296 5297 CHK_SV; 5298 t0 = tcg_temp_new(); 5299 gen_addr_reg_index(ctx, t0); 5300 tcg_gen_shri_tl(t0, t0, 28); 5301 tcg_gen_andi_tl(t0, t0, 0xF); 5302 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5303 tcg_temp_free(t0); 5304 if (ra != 0 && ra != rd) 5305 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5306 #endif /* defined(CONFIG_USER_ONLY) */ 5307 } 5308 5309 static void gen_rac(DisasContext *ctx) 5310 { 5311 #if defined(CONFIG_USER_ONLY) 5312 GEN_PRIV; 5313 #else 5314 TCGv t0; 5315 5316 CHK_SV; 5317 t0 = tcg_temp_new(); 5318 gen_addr_reg_index(ctx, t0); 5319 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5320 tcg_temp_free(t0); 5321 #endif /* defined(CONFIG_USER_ONLY) */ 5322 } 5323 5324 static void gen_rfsvc(DisasContext *ctx) 5325 { 5326 #if defined(CONFIG_USER_ONLY) 5327 GEN_PRIV; 5328 #else 5329 CHK_SV; 5330 5331 gen_helper_rfsvc(cpu_env); 5332 gen_sync_exception(ctx); 5333 #endif /* defined(CONFIG_USER_ONLY) */ 5334 } 5335 5336 /* svc is not implemented for now */ 5337 5338 /* BookE specific instructions */ 5339 5340 /* XXX: not implemented on 440 ? */ 5341 static void gen_mfapidi(DisasContext *ctx) 5342 { 5343 /* XXX: TODO */ 5344 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5345 } 5346 5347 /* XXX: not implemented on 440 ? */ 5348 static void gen_tlbiva(DisasContext *ctx) 5349 { 5350 #if defined(CONFIG_USER_ONLY) 5351 GEN_PRIV; 5352 #else 5353 TCGv t0; 5354 5355 CHK_SV; 5356 t0 = tcg_temp_new(); 5357 gen_addr_reg_index(ctx, t0); 5358 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5359 tcg_temp_free(t0); 5360 #endif /* defined(CONFIG_USER_ONLY) */ 5361 } 5362 5363 /* All 405 MAC instructions are translated here */ 5364 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5365 int ra, int rb, int rt, int Rc) 5366 { 5367 TCGv t0, t1; 5368 5369 t0 = tcg_temp_local_new(); 5370 t1 = tcg_temp_local_new(); 5371 5372 switch (opc3 & 0x0D) { 5373 case 0x05: 5374 /* macchw - macchw. - macchwo - macchwo. */ 5375 /* macchws - macchws. - macchwso - macchwso. */ 5376 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5377 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5378 /* mulchw - mulchw. */ 5379 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5380 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5381 tcg_gen_ext16s_tl(t1, t1); 5382 break; 5383 case 0x04: 5384 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5385 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5386 /* mulchwu - mulchwu. */ 5387 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5388 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5389 tcg_gen_ext16u_tl(t1, t1); 5390 break; 5391 case 0x01: 5392 /* machhw - machhw. - machhwo - machhwo. */ 5393 /* machhws - machhws. - machhwso - machhwso. */ 5394 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5395 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5396 /* mulhhw - mulhhw. */ 5397 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5398 tcg_gen_ext16s_tl(t0, t0); 5399 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5400 tcg_gen_ext16s_tl(t1, t1); 5401 break; 5402 case 0x00: 5403 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5404 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5405 /* mulhhwu - mulhhwu. */ 5406 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5407 tcg_gen_ext16u_tl(t0, t0); 5408 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5409 tcg_gen_ext16u_tl(t1, t1); 5410 break; 5411 case 0x0D: 5412 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5413 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5414 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5415 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5416 /* mullhw - mullhw. */ 5417 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5418 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5419 break; 5420 case 0x0C: 5421 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5422 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5423 /* mullhwu - mullhwu. */ 5424 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5425 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5426 break; 5427 } 5428 if (opc2 & 0x04) { 5429 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5430 tcg_gen_mul_tl(t1, t0, t1); 5431 if (opc2 & 0x02) { 5432 /* nmultiply-and-accumulate (0x0E) */ 5433 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5434 } else { 5435 /* multiply-and-accumulate (0x0C) */ 5436 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5437 } 5438 5439 if (opc3 & 0x12) { 5440 /* Check overflow and/or saturate */ 5441 TCGLabel *l1 = gen_new_label(); 5442 5443 if (opc3 & 0x10) { 5444 /* Start with XER OV disabled, the most likely case */ 5445 tcg_gen_movi_tl(cpu_ov, 0); 5446 } 5447 if (opc3 & 0x01) { 5448 /* Signed */ 5449 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5450 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5451 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5452 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5453 if (opc3 & 0x02) { 5454 /* Saturate */ 5455 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5456 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5457 } 5458 } else { 5459 /* Unsigned */ 5460 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5461 if (opc3 & 0x02) { 5462 /* Saturate */ 5463 tcg_gen_movi_tl(t0, UINT32_MAX); 5464 } 5465 } 5466 if (opc3 & 0x10) { 5467 /* Check overflow */ 5468 tcg_gen_movi_tl(cpu_ov, 1); 5469 tcg_gen_movi_tl(cpu_so, 1); 5470 } 5471 gen_set_label(l1); 5472 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5473 } 5474 } else { 5475 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5476 } 5477 tcg_temp_free(t0); 5478 tcg_temp_free(t1); 5479 if (unlikely(Rc) != 0) { 5480 /* Update Rc0 */ 5481 gen_set_Rc0(ctx, cpu_gpr[rt]); 5482 } 5483 } 5484 5485 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5486 static void glue(gen_, name)(DisasContext *ctx) \ 5487 { \ 5488 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5489 rD(ctx->opcode), Rc(ctx->opcode)); \ 5490 } 5491 5492 /* macchw - macchw. */ 5493 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5494 /* macchwo - macchwo. */ 5495 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5496 /* macchws - macchws. */ 5497 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5498 /* macchwso - macchwso. */ 5499 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5500 /* macchwsu - macchwsu. */ 5501 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5502 /* macchwsuo - macchwsuo. */ 5503 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5504 /* macchwu - macchwu. */ 5505 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5506 /* macchwuo - macchwuo. */ 5507 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5508 /* machhw - machhw. */ 5509 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5510 /* machhwo - machhwo. */ 5511 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5512 /* machhws - machhws. */ 5513 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5514 /* machhwso - machhwso. */ 5515 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5516 /* machhwsu - machhwsu. */ 5517 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5518 /* machhwsuo - machhwsuo. */ 5519 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5520 /* machhwu - machhwu. */ 5521 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5522 /* machhwuo - machhwuo. */ 5523 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5524 /* maclhw - maclhw. */ 5525 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5526 /* maclhwo - maclhwo. */ 5527 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5528 /* maclhws - maclhws. */ 5529 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5530 /* maclhwso - maclhwso. */ 5531 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5532 /* maclhwu - maclhwu. */ 5533 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5534 /* maclhwuo - maclhwuo. */ 5535 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5536 /* maclhwsu - maclhwsu. */ 5537 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5538 /* maclhwsuo - maclhwsuo. */ 5539 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5540 /* nmacchw - nmacchw. */ 5541 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5542 /* nmacchwo - nmacchwo. */ 5543 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5544 /* nmacchws - nmacchws. */ 5545 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5546 /* nmacchwso - nmacchwso. */ 5547 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5548 /* nmachhw - nmachhw. */ 5549 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5550 /* nmachhwo - nmachhwo. */ 5551 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5552 /* nmachhws - nmachhws. */ 5553 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5554 /* nmachhwso - nmachhwso. */ 5555 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5556 /* nmaclhw - nmaclhw. */ 5557 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5558 /* nmaclhwo - nmaclhwo. */ 5559 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5560 /* nmaclhws - nmaclhws. */ 5561 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5562 /* nmaclhwso - nmaclhwso. */ 5563 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5564 5565 /* mulchw - mulchw. */ 5566 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5567 /* mulchwu - mulchwu. */ 5568 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5569 /* mulhhw - mulhhw. */ 5570 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5571 /* mulhhwu - mulhhwu. */ 5572 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5573 /* mullhw - mullhw. */ 5574 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5575 /* mullhwu - mullhwu. */ 5576 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5577 5578 /* mfdcr */ 5579 static void gen_mfdcr(DisasContext *ctx) 5580 { 5581 #if defined(CONFIG_USER_ONLY) 5582 GEN_PRIV; 5583 #else 5584 TCGv dcrn; 5585 5586 CHK_SV; 5587 dcrn = tcg_const_tl(SPR(ctx->opcode)); 5588 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5589 tcg_temp_free(dcrn); 5590 #endif /* defined(CONFIG_USER_ONLY) */ 5591 } 5592 5593 /* mtdcr */ 5594 static void gen_mtdcr(DisasContext *ctx) 5595 { 5596 #if defined(CONFIG_USER_ONLY) 5597 GEN_PRIV; 5598 #else 5599 TCGv dcrn; 5600 5601 CHK_SV; 5602 dcrn = tcg_const_tl(SPR(ctx->opcode)); 5603 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5604 tcg_temp_free(dcrn); 5605 #endif /* defined(CONFIG_USER_ONLY) */ 5606 } 5607 5608 /* mfdcrx */ 5609 /* XXX: not implemented on 440 ? */ 5610 static void gen_mfdcrx(DisasContext *ctx) 5611 { 5612 #if defined(CONFIG_USER_ONLY) 5613 GEN_PRIV; 5614 #else 5615 CHK_SV; 5616 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5617 cpu_gpr[rA(ctx->opcode)]); 5618 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5619 #endif /* defined(CONFIG_USER_ONLY) */ 5620 } 5621 5622 /* mtdcrx */ 5623 /* XXX: not implemented on 440 ? */ 5624 static void gen_mtdcrx(DisasContext *ctx) 5625 { 5626 #if defined(CONFIG_USER_ONLY) 5627 GEN_PRIV; 5628 #else 5629 CHK_SV; 5630 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5631 cpu_gpr[rS(ctx->opcode)]); 5632 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5633 #endif /* defined(CONFIG_USER_ONLY) */ 5634 } 5635 5636 /* mfdcrux (PPC 460) : user-mode access to DCR */ 5637 static void gen_mfdcrux(DisasContext *ctx) 5638 { 5639 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5640 cpu_gpr[rA(ctx->opcode)]); 5641 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5642 } 5643 5644 /* mtdcrux (PPC 460) : user-mode access to DCR */ 5645 static void gen_mtdcrux(DisasContext *ctx) 5646 { 5647 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5648 cpu_gpr[rS(ctx->opcode)]); 5649 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5650 } 5651 5652 /* dccci */ 5653 static void gen_dccci(DisasContext *ctx) 5654 { 5655 CHK_SV; 5656 /* interpreted as no-op */ 5657 } 5658 5659 /* dcread */ 5660 static void gen_dcread(DisasContext *ctx) 5661 { 5662 #if defined(CONFIG_USER_ONLY) 5663 GEN_PRIV; 5664 #else 5665 TCGv EA, val; 5666 5667 CHK_SV; 5668 gen_set_access_type(ctx, ACCESS_CACHE); 5669 EA = tcg_temp_new(); 5670 gen_addr_reg_index(ctx, EA); 5671 val = tcg_temp_new(); 5672 gen_qemu_ld32u(ctx, val, EA); 5673 tcg_temp_free(val); 5674 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5675 tcg_temp_free(EA); 5676 #endif /* defined(CONFIG_USER_ONLY) */ 5677 } 5678 5679 /* icbt */ 5680 static void gen_icbt_40x(DisasContext *ctx) 5681 { 5682 /* interpreted as no-op */ 5683 /* XXX: specification say this is treated as a load by the MMU 5684 * but does not generate any exception 5685 */ 5686 } 5687 5688 /* iccci */ 5689 static void gen_iccci(DisasContext *ctx) 5690 { 5691 CHK_SV; 5692 /* interpreted as no-op */ 5693 } 5694 5695 /* icread */ 5696 static void gen_icread(DisasContext *ctx) 5697 { 5698 CHK_SV; 5699 /* interpreted as no-op */ 5700 } 5701 5702 /* rfci (supervisor only) */ 5703 static void gen_rfci_40x(DisasContext *ctx) 5704 { 5705 #if defined(CONFIG_USER_ONLY) 5706 GEN_PRIV; 5707 #else 5708 CHK_SV; 5709 /* Restore CPU state */ 5710 gen_helper_40x_rfci(cpu_env); 5711 gen_sync_exception(ctx); 5712 #endif /* defined(CONFIG_USER_ONLY) */ 5713 } 5714 5715 static void gen_rfci(DisasContext *ctx) 5716 { 5717 #if defined(CONFIG_USER_ONLY) 5718 GEN_PRIV; 5719 #else 5720 CHK_SV; 5721 /* Restore CPU state */ 5722 gen_helper_rfci(cpu_env); 5723 gen_sync_exception(ctx); 5724 #endif /* defined(CONFIG_USER_ONLY) */ 5725 } 5726 5727 /* BookE specific */ 5728 5729 /* XXX: not implemented on 440 ? */ 5730 static void gen_rfdi(DisasContext *ctx) 5731 { 5732 #if defined(CONFIG_USER_ONLY) 5733 GEN_PRIV; 5734 #else 5735 CHK_SV; 5736 /* Restore CPU state */ 5737 gen_helper_rfdi(cpu_env); 5738 gen_sync_exception(ctx); 5739 #endif /* defined(CONFIG_USER_ONLY) */ 5740 } 5741 5742 /* XXX: not implemented on 440 ? */ 5743 static void gen_rfmci(DisasContext *ctx) 5744 { 5745 #if defined(CONFIG_USER_ONLY) 5746 GEN_PRIV; 5747 #else 5748 CHK_SV; 5749 /* Restore CPU state */ 5750 gen_helper_rfmci(cpu_env); 5751 gen_sync_exception(ctx); 5752 #endif /* defined(CONFIG_USER_ONLY) */ 5753 } 5754 5755 /* TLB management - PowerPC 405 implementation */ 5756 5757 /* tlbre */ 5758 static void gen_tlbre_40x(DisasContext *ctx) 5759 { 5760 #if defined(CONFIG_USER_ONLY) 5761 GEN_PRIV; 5762 #else 5763 CHK_SV; 5764 switch (rB(ctx->opcode)) { 5765 case 0: 5766 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5767 cpu_gpr[rA(ctx->opcode)]); 5768 break; 5769 case 1: 5770 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5771 cpu_gpr[rA(ctx->opcode)]); 5772 break; 5773 default: 5774 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5775 break; 5776 } 5777 #endif /* defined(CONFIG_USER_ONLY) */ 5778 } 5779 5780 /* tlbsx - tlbsx. */ 5781 static void gen_tlbsx_40x(DisasContext *ctx) 5782 { 5783 #if defined(CONFIG_USER_ONLY) 5784 GEN_PRIV; 5785 #else 5786 TCGv t0; 5787 5788 CHK_SV; 5789 t0 = tcg_temp_new(); 5790 gen_addr_reg_index(ctx, t0); 5791 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5792 tcg_temp_free(t0); 5793 if (Rc(ctx->opcode)) { 5794 TCGLabel *l1 = gen_new_label(); 5795 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5796 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5797 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5798 gen_set_label(l1); 5799 } 5800 #endif /* defined(CONFIG_USER_ONLY) */ 5801 } 5802 5803 /* tlbwe */ 5804 static void gen_tlbwe_40x(DisasContext *ctx) 5805 { 5806 #if defined(CONFIG_USER_ONLY) 5807 GEN_PRIV; 5808 #else 5809 CHK_SV; 5810 5811 switch (rB(ctx->opcode)) { 5812 case 0: 5813 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5814 cpu_gpr[rS(ctx->opcode)]); 5815 break; 5816 case 1: 5817 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5818 cpu_gpr[rS(ctx->opcode)]); 5819 break; 5820 default: 5821 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5822 break; 5823 } 5824 #endif /* defined(CONFIG_USER_ONLY) */ 5825 } 5826 5827 /* TLB management - PowerPC 440 implementation */ 5828 5829 /* tlbre */ 5830 static void gen_tlbre_440(DisasContext *ctx) 5831 { 5832 #if defined(CONFIG_USER_ONLY) 5833 GEN_PRIV; 5834 #else 5835 CHK_SV; 5836 5837 switch (rB(ctx->opcode)) { 5838 case 0: 5839 case 1: 5840 case 2: 5841 { 5842 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 5843 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5844 t0, cpu_gpr[rA(ctx->opcode)]); 5845 tcg_temp_free_i32(t0); 5846 } 5847 break; 5848 default: 5849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5850 break; 5851 } 5852 #endif /* defined(CONFIG_USER_ONLY) */ 5853 } 5854 5855 /* tlbsx - tlbsx. */ 5856 static void gen_tlbsx_440(DisasContext *ctx) 5857 { 5858 #if defined(CONFIG_USER_ONLY) 5859 GEN_PRIV; 5860 #else 5861 TCGv t0; 5862 5863 CHK_SV; 5864 t0 = tcg_temp_new(); 5865 gen_addr_reg_index(ctx, t0); 5866 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5867 tcg_temp_free(t0); 5868 if (Rc(ctx->opcode)) { 5869 TCGLabel *l1 = gen_new_label(); 5870 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5871 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5872 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5873 gen_set_label(l1); 5874 } 5875 #endif /* defined(CONFIG_USER_ONLY) */ 5876 } 5877 5878 /* tlbwe */ 5879 static void gen_tlbwe_440(DisasContext *ctx) 5880 { 5881 #if defined(CONFIG_USER_ONLY) 5882 GEN_PRIV; 5883 #else 5884 CHK_SV; 5885 switch (rB(ctx->opcode)) { 5886 case 0: 5887 case 1: 5888 case 2: 5889 { 5890 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 5891 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5892 cpu_gpr[rS(ctx->opcode)]); 5893 tcg_temp_free_i32(t0); 5894 } 5895 break; 5896 default: 5897 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5898 break; 5899 } 5900 #endif /* defined(CONFIG_USER_ONLY) */ 5901 } 5902 5903 /* TLB management - PowerPC BookE 2.06 implementation */ 5904 5905 /* tlbre */ 5906 static void gen_tlbre_booke206(DisasContext *ctx) 5907 { 5908 #if defined(CONFIG_USER_ONLY) 5909 GEN_PRIV; 5910 #else 5911 CHK_SV; 5912 gen_helper_booke206_tlbre(cpu_env); 5913 #endif /* defined(CONFIG_USER_ONLY) */ 5914 } 5915 5916 /* tlbsx - tlbsx. */ 5917 static void gen_tlbsx_booke206(DisasContext *ctx) 5918 { 5919 #if defined(CONFIG_USER_ONLY) 5920 GEN_PRIV; 5921 #else 5922 TCGv t0; 5923 5924 CHK_SV; 5925 if (rA(ctx->opcode)) { 5926 t0 = tcg_temp_new(); 5927 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 5928 } else { 5929 t0 = tcg_const_tl(0); 5930 } 5931 5932 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 5933 gen_helper_booke206_tlbsx(cpu_env, t0); 5934 tcg_temp_free(t0); 5935 #endif /* defined(CONFIG_USER_ONLY) */ 5936 } 5937 5938 /* tlbwe */ 5939 static void gen_tlbwe_booke206(DisasContext *ctx) 5940 { 5941 #if defined(CONFIG_USER_ONLY) 5942 GEN_PRIV; 5943 #else 5944 CHK_SV; 5945 gen_helper_booke206_tlbwe(cpu_env); 5946 #endif /* defined(CONFIG_USER_ONLY) */ 5947 } 5948 5949 static void gen_tlbivax_booke206(DisasContext *ctx) 5950 { 5951 #if defined(CONFIG_USER_ONLY) 5952 GEN_PRIV; 5953 #else 5954 TCGv t0; 5955 5956 CHK_SV; 5957 t0 = tcg_temp_new(); 5958 gen_addr_reg_index(ctx, t0); 5959 gen_helper_booke206_tlbivax(cpu_env, t0); 5960 tcg_temp_free(t0); 5961 #endif /* defined(CONFIG_USER_ONLY) */ 5962 } 5963 5964 static void gen_tlbilx_booke206(DisasContext *ctx) 5965 { 5966 #if defined(CONFIG_USER_ONLY) 5967 GEN_PRIV; 5968 #else 5969 TCGv t0; 5970 5971 CHK_SV; 5972 t0 = tcg_temp_new(); 5973 gen_addr_reg_index(ctx, t0); 5974 5975 switch((ctx->opcode >> 21) & 0x3) { 5976 case 0: 5977 gen_helper_booke206_tlbilx0(cpu_env, t0); 5978 break; 5979 case 1: 5980 gen_helper_booke206_tlbilx1(cpu_env, t0); 5981 break; 5982 case 3: 5983 gen_helper_booke206_tlbilx3(cpu_env, t0); 5984 break; 5985 default: 5986 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5987 break; 5988 } 5989 5990 tcg_temp_free(t0); 5991 #endif /* defined(CONFIG_USER_ONLY) */ 5992 } 5993 5994 5995 /* wrtee */ 5996 static void gen_wrtee(DisasContext *ctx) 5997 { 5998 #if defined(CONFIG_USER_ONLY) 5999 GEN_PRIV; 6000 #else 6001 TCGv t0; 6002 6003 CHK_SV; 6004 t0 = tcg_temp_new(); 6005 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6006 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6007 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6008 tcg_temp_free(t0); 6009 /* Stop translation to have a chance to raise an exception 6010 * if we just set msr_ee to 1 6011 */ 6012 gen_stop_exception(ctx); 6013 #endif /* defined(CONFIG_USER_ONLY) */ 6014 } 6015 6016 /* wrteei */ 6017 static void gen_wrteei(DisasContext *ctx) 6018 { 6019 #if defined(CONFIG_USER_ONLY) 6020 GEN_PRIV; 6021 #else 6022 CHK_SV; 6023 if (ctx->opcode & 0x00008000) { 6024 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6025 /* Stop translation to have a chance to raise an exception */ 6026 gen_stop_exception(ctx); 6027 } else { 6028 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6029 } 6030 #endif /* defined(CONFIG_USER_ONLY) */ 6031 } 6032 6033 /* PowerPC 440 specific instructions */ 6034 6035 /* dlmzb */ 6036 static void gen_dlmzb(DisasContext *ctx) 6037 { 6038 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6039 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6040 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6041 tcg_temp_free_i32(t0); 6042 } 6043 6044 /* mbar replaces eieio on 440 */ 6045 static void gen_mbar(DisasContext *ctx) 6046 { 6047 /* interpreted as no-op */ 6048 } 6049 6050 /* msync replaces sync on 440 */ 6051 static void gen_msync_4xx(DisasContext *ctx) 6052 { 6053 /* interpreted as no-op */ 6054 } 6055 6056 /* icbt */ 6057 static void gen_icbt_440(DisasContext *ctx) 6058 { 6059 /* interpreted as no-op */ 6060 /* XXX: specification say this is treated as a load by the MMU 6061 * but does not generate any exception 6062 */ 6063 } 6064 6065 /* Embedded.Processor Control */ 6066 6067 static void gen_msgclr(DisasContext *ctx) 6068 { 6069 #if defined(CONFIG_USER_ONLY) 6070 GEN_PRIV; 6071 #else 6072 CHK_SV; 6073 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6074 #endif /* defined(CONFIG_USER_ONLY) */ 6075 } 6076 6077 static void gen_msgsnd(DisasContext *ctx) 6078 { 6079 #if defined(CONFIG_USER_ONLY) 6080 GEN_PRIV; 6081 #else 6082 CHK_SV; 6083 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6084 #endif /* defined(CONFIG_USER_ONLY) */ 6085 } 6086 6087 6088 #if defined(TARGET_PPC64) 6089 static void gen_maddld(DisasContext *ctx) 6090 { 6091 TCGv_i64 t1 = tcg_temp_new_i64(); 6092 6093 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6094 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6095 tcg_temp_free_i64(t1); 6096 } 6097 6098 /* maddhd maddhdu */ 6099 static void gen_maddhd_maddhdu(DisasContext *ctx) 6100 { 6101 TCGv_i64 lo = tcg_temp_new_i64(); 6102 TCGv_i64 hi = tcg_temp_new_i64(); 6103 TCGv_i64 t1 = tcg_temp_new_i64(); 6104 6105 if (Rc(ctx->opcode)) { 6106 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6107 cpu_gpr[rB(ctx->opcode)]); 6108 tcg_gen_movi_i64(t1, 0); 6109 } else { 6110 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6111 cpu_gpr[rB(ctx->opcode)]); 6112 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6113 } 6114 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6115 cpu_gpr[rC(ctx->opcode)], t1); 6116 tcg_temp_free_i64(lo); 6117 tcg_temp_free_i64(hi); 6118 tcg_temp_free_i64(t1); 6119 } 6120 #endif /* defined(TARGET_PPC64) */ 6121 6122 static void gen_tbegin(DisasContext *ctx) 6123 { 6124 if (unlikely(!ctx->tm_enabled)) { 6125 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6126 return; 6127 } 6128 gen_helper_tbegin(cpu_env); 6129 } 6130 6131 #define GEN_TM_NOOP(name) \ 6132 static inline void gen_##name(DisasContext *ctx) \ 6133 { \ 6134 if (unlikely(!ctx->tm_enabled)) { \ 6135 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6136 return; \ 6137 } \ 6138 /* Because tbegin always fails in QEMU, these user \ 6139 * space instructions all have a simple implementation: \ 6140 * \ 6141 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6142 * = 0b0 || 0b00 || 0b0 \ 6143 */ \ 6144 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6145 } 6146 6147 GEN_TM_NOOP(tend); 6148 GEN_TM_NOOP(tabort); 6149 GEN_TM_NOOP(tabortwc); 6150 GEN_TM_NOOP(tabortwci); 6151 GEN_TM_NOOP(tabortdc); 6152 GEN_TM_NOOP(tabortdci); 6153 GEN_TM_NOOP(tsr); 6154 static inline void gen_cp_abort(DisasContext *ctx) 6155 { 6156 // Do Nothing 6157 } 6158 6159 #define GEN_CP_PASTE_NOOP(name) \ 6160 static inline void gen_##name(DisasContext *ctx) \ 6161 { \ 6162 /* Generate invalid exception until \ 6163 * we have an implementation of the copy \ 6164 * paste facility \ 6165 */ \ 6166 gen_invalid(ctx); \ 6167 } 6168 6169 GEN_CP_PASTE_NOOP(copy) 6170 GEN_CP_PASTE_NOOP(paste) 6171 6172 static void gen_tcheck(DisasContext *ctx) 6173 { 6174 if (unlikely(!ctx->tm_enabled)) { 6175 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6176 return; 6177 } 6178 /* Because tbegin always fails, the tcheck implementation 6179 * is simple: 6180 * 6181 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6182 * = 0b1 || 0b00 || 0b0 6183 */ 6184 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6185 } 6186 6187 #if defined(CONFIG_USER_ONLY) 6188 #define GEN_TM_PRIV_NOOP(name) \ 6189 static inline void gen_##name(DisasContext *ctx) \ 6190 { \ 6191 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6192 } 6193 6194 #else 6195 6196 #define GEN_TM_PRIV_NOOP(name) \ 6197 static inline void gen_##name(DisasContext *ctx) \ 6198 { \ 6199 CHK_SV; \ 6200 if (unlikely(!ctx->tm_enabled)) { \ 6201 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6202 return; \ 6203 } \ 6204 /* Because tbegin always fails, the implementation is \ 6205 * simple: \ 6206 * \ 6207 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6208 * = 0b0 || 0b00 | 0b0 \ 6209 */ \ 6210 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6211 } 6212 6213 #endif 6214 6215 GEN_TM_PRIV_NOOP(treclaim); 6216 GEN_TM_PRIV_NOOP(trechkpt); 6217 6218 #include "translate/fp-impl.inc.c" 6219 6220 #include "translate/vmx-impl.inc.c" 6221 6222 #include "translate/vsx-impl.inc.c" 6223 6224 #include "translate/dfp-impl.inc.c" 6225 6226 #include "translate/spe-impl.inc.c" 6227 6228 /* Handles lfdp, lxsd, lxssp */ 6229 static void gen_dform39(DisasContext *ctx) 6230 { 6231 switch (ctx->opcode & 0x3) { 6232 case 0: /* lfdp */ 6233 if (ctx->insns_flags2 & PPC2_ISA205) { 6234 return gen_lfdp(ctx); 6235 } 6236 break; 6237 case 2: /* lxsd */ 6238 if (ctx->insns_flags2 & PPC2_ISA300) { 6239 return gen_lxsd(ctx); 6240 } 6241 break; 6242 case 3: /* lxssp */ 6243 if (ctx->insns_flags2 & PPC2_ISA300) { 6244 return gen_lxssp(ctx); 6245 } 6246 break; 6247 } 6248 return gen_invalid(ctx); 6249 } 6250 6251 /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6252 static void gen_dform3D(DisasContext *ctx) 6253 { 6254 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6255 switch (ctx->opcode & 0x7) { 6256 case 1: /* lxv */ 6257 if (ctx->insns_flags2 & PPC2_ISA300) { 6258 return gen_lxv(ctx); 6259 } 6260 break; 6261 case 5: /* stxv */ 6262 if (ctx->insns_flags2 & PPC2_ISA300) { 6263 return gen_stxv(ctx); 6264 } 6265 break; 6266 } 6267 } else { /* DS-FORM */ 6268 switch (ctx->opcode & 0x3) { 6269 case 0: /* stfdp */ 6270 if (ctx->insns_flags2 & PPC2_ISA205) { 6271 return gen_stfdp(ctx); 6272 } 6273 break; 6274 case 2: /* stxsd */ 6275 if (ctx->insns_flags2 & PPC2_ISA300) { 6276 return gen_stxsd(ctx); 6277 } 6278 break; 6279 case 3: /* stxssp */ 6280 if (ctx->insns_flags2 & PPC2_ISA300) { 6281 return gen_stxssp(ctx); 6282 } 6283 break; 6284 } 6285 } 6286 return gen_invalid(ctx); 6287 } 6288 6289 static opcode_t opcodes[] = { 6290 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6291 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6292 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6293 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6294 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6295 #if defined(TARGET_PPC64) 6296 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6297 #endif 6298 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6299 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6300 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6301 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6302 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6303 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6304 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6305 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6306 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6307 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6308 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6309 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6310 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6311 #if defined(TARGET_PPC64) 6312 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6313 #endif 6314 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6315 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6316 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6317 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6318 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6319 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6320 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6321 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6322 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6323 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6324 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6325 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6326 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6327 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6328 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6329 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6330 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6331 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6332 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6333 #if defined(TARGET_PPC64) 6334 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6335 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6336 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6337 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6338 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6339 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6340 #endif 6341 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6342 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6343 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6344 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6345 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6346 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6347 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6348 #if defined(TARGET_PPC64) 6349 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6350 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6351 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6352 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6353 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6354 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6355 PPC_NONE, PPC2_ISA300), 6356 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6357 PPC_NONE, PPC2_ISA300), 6358 #endif 6359 #if defined(TARGET_PPC64) 6360 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6361 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6362 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6363 #endif 6364 /* handles lfdp, lxsd, lxssp */ 6365 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6366 /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6367 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6368 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6369 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6370 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6371 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6372 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6373 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6374 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), 6375 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6376 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6377 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6378 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6379 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6380 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6381 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6382 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6383 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6384 #if defined(TARGET_PPC64) 6385 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6386 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6387 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6388 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6389 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6390 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6391 #endif 6392 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6393 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 6394 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 6395 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6396 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6397 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6398 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6399 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6400 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6401 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6402 #if defined(TARGET_PPC64) 6403 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6404 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6405 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6406 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6407 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6408 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6409 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6410 #endif 6411 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 6412 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6413 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6414 #if defined(TARGET_PPC64) 6415 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6416 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6417 #endif 6418 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6419 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6420 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6421 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6422 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6423 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6424 #if defined(TARGET_PPC64) 6425 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6426 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6427 #endif 6428 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6429 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6430 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6431 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6432 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6433 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6434 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6435 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6436 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6437 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6438 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), 6439 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6440 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6441 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6442 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6443 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6444 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6445 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6446 #if defined(TARGET_PPC64) 6447 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6448 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6449 PPC_SEGMENT_64B), 6450 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6451 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6452 PPC_SEGMENT_64B), 6453 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 6454 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 6455 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 6456 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 6457 #endif 6458 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6459 /* XXX Those instructions will need to be handled differently for 6460 * different ISA versions */ 6461 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 6462 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 6463 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6464 #if defined(TARGET_PPC64) 6465 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 6466 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 6467 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 6468 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6469 #endif 6470 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6471 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6472 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 6473 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 6474 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 6475 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 6476 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 6477 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 6478 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 6479 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 6480 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 6481 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6482 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 6483 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 6484 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 6485 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 6486 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 6487 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 6488 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 6489 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6490 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 6491 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 6492 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 6493 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 6494 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 6495 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 6496 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 6497 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 6498 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 6499 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 6500 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 6501 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 6502 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 6503 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 6504 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 6505 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 6506 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 6507 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 6508 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 6509 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6510 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6511 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 6512 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 6513 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 6514 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 6515 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 6516 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 6517 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 6518 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 6519 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6520 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6521 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 6522 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 6523 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6524 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6525 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 6526 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 6527 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6528 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6529 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6530 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6531 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6532 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6533 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 6534 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 6535 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6536 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6537 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6538 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6539 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6540 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6541 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6542 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6543 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6544 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6545 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6546 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6547 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6548 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6549 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6550 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6551 PPC_NONE, PPC2_BOOKE206), 6552 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6553 PPC_NONE, PPC2_BOOKE206), 6554 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6555 PPC_NONE, PPC2_BOOKE206), 6556 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6557 PPC_NONE, PPC2_BOOKE206), 6558 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6559 PPC_NONE, PPC2_BOOKE206), 6560 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 6561 PPC_NONE, PPC2_PRCNTL), 6562 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 6563 PPC_NONE, PPC2_PRCNTL), 6564 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6565 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6566 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6567 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6568 PPC_BOOKE, PPC2_BOOKE206), 6569 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), 6570 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6571 PPC_BOOKE, PPC2_BOOKE206), 6572 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6573 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6574 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6575 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6576 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 6577 #if defined(TARGET_PPC64) 6578 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6579 PPC2_ISA300), 6580 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6581 #endif 6582 6583 #undef GEN_INT_ARITH_ADD 6584 #undef GEN_INT_ARITH_ADD_CONST 6585 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6586 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6587 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6588 add_ca, compute_ca, compute_ov) \ 6589 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6590 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6591 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6592 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6593 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6594 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6595 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6596 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6597 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6598 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6599 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6600 6601 #undef GEN_INT_ARITH_DIVW 6602 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6603 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6604 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6605 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6606 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6607 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6608 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6609 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6610 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6611 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6612 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6613 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6614 6615 #if defined(TARGET_PPC64) 6616 #undef GEN_INT_ARITH_DIVD 6617 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6618 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6619 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6620 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6621 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6622 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6623 6624 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6625 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6626 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6627 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6628 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6629 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6630 6631 #undef GEN_INT_ARITH_MUL_HELPER 6632 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6633 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6634 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6635 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6636 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6637 #endif 6638 6639 #undef GEN_INT_ARITH_SUBF 6640 #undef GEN_INT_ARITH_SUBF_CONST 6641 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6642 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6643 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6644 add_ca, compute_ca, compute_ov) \ 6645 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6646 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6647 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6648 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6649 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6650 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6651 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6652 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6653 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6654 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6655 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6656 6657 #undef GEN_LOGICAL1 6658 #undef GEN_LOGICAL2 6659 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6660 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6661 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6662 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6663 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6664 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6665 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6666 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6667 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6668 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6669 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6670 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6671 #if defined(TARGET_PPC64) 6672 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6673 #endif 6674 6675 #if defined(TARGET_PPC64) 6676 #undef GEN_PPC64_R2 6677 #undef GEN_PPC64_R4 6678 #define GEN_PPC64_R2(name, opc1, opc2) \ 6679 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6680 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6681 PPC_64B) 6682 #define GEN_PPC64_R4(name, opc1, opc2) \ 6683 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6684 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6685 PPC_64B), \ 6686 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6687 PPC_64B), \ 6688 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6689 PPC_64B) 6690 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6691 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6692 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6693 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6694 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6695 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6696 #endif 6697 6698 #undef GEN_LD 6699 #undef GEN_LDU 6700 #undef GEN_LDUX 6701 #undef GEN_LDX_E 6702 #undef GEN_LDS 6703 #define GEN_LD(name, ldop, opc, type) \ 6704 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6705 #define GEN_LDU(name, ldop, opc, type) \ 6706 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 6707 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 6708 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6709 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6710 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6711 #define GEN_LDS(name, ldop, op, type) \ 6712 GEN_LD(name, ldop, op | 0x20, type) \ 6713 GEN_LDU(name, ldop, op | 0x21, type) \ 6714 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 6715 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 6716 6717 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 6718 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 6719 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 6720 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 6721 #if defined(TARGET_PPC64) 6722 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 6723 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 6724 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 6725 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 6726 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6727 6728 /* HV/P7 and later only */ 6729 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6730 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6731 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6732 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6733 #endif 6734 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6735 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6736 6737 #undef GEN_ST 6738 #undef GEN_STU 6739 #undef GEN_STUX 6740 #undef GEN_STX_E 6741 #undef GEN_STS 6742 #define GEN_ST(name, stop, opc, type) \ 6743 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6744 #define GEN_STU(name, stop, opc, type) \ 6745 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 6746 #define GEN_STUX(name, stop, opc2, opc3, type) \ 6747 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6748 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6749 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6750 #define GEN_STS(name, stop, op, type) \ 6751 GEN_ST(name, stop, op | 0x20, type) \ 6752 GEN_STU(name, stop, op | 0x21, type) \ 6753 GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 6754 GEN_STX(name, stop, 0x17, op | 0x00, type) 6755 6756 GEN_STS(stb, st8, 0x06, PPC_INTEGER) 6757 GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 6758 GEN_STS(stw, st32, 0x04, PPC_INTEGER) 6759 #if defined(TARGET_PPC64) 6760 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 6761 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 6762 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6763 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6764 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6765 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6766 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6767 #endif 6768 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6769 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6770 6771 #undef GEN_CRLOGIC 6772 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6773 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6774 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6775 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6776 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6777 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6778 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6779 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6780 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6781 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6782 6783 #undef GEN_MAC_HANDLER 6784 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6785 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6786 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6787 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6788 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6789 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6790 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6791 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6792 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6793 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6794 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6795 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6796 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6797 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6798 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6799 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6800 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6801 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6802 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6803 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6804 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6805 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6806 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6807 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6808 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6809 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6810 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6811 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6812 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6813 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6814 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6815 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6816 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6817 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6818 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6819 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6820 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6821 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6822 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6823 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6824 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6825 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6826 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6827 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6828 6829 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6830 PPC_NONE, PPC2_TM), 6831 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6832 PPC_NONE, PPC2_TM), 6833 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6834 PPC_NONE, PPC2_TM), 6835 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6836 PPC_NONE, PPC2_TM), 6837 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6838 PPC_NONE, PPC2_TM), 6839 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6840 PPC_NONE, PPC2_TM), 6841 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6842 PPC_NONE, PPC2_TM), 6843 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6844 PPC_NONE, PPC2_TM), 6845 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6846 PPC_NONE, PPC2_TM), 6847 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6848 PPC_NONE, PPC2_TM), 6849 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6850 PPC_NONE, PPC2_TM), 6851 6852 #include "translate/fp-ops.inc.c" 6853 6854 #include "translate/vmx-ops.inc.c" 6855 6856 #include "translate/vsx-ops.inc.c" 6857 6858 #include "translate/dfp-ops.inc.c" 6859 6860 #include "translate/spe-ops.inc.c" 6861 }; 6862 6863 #include "helper_regs.h" 6864 #include "translate_init.c" 6865 6866 /*****************************************************************************/ 6867 /* Misc PowerPC helpers */ 6868 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 6869 int flags) 6870 { 6871 #define RGPL 4 6872 #define RFPL 4 6873 6874 PowerPCCPU *cpu = POWERPC_CPU(cs); 6875 CPUPPCState *env = &cpu->env; 6876 int i; 6877 6878 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 6879 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 6880 env->nip, env->lr, env->ctr, cpu_read_xer(env), 6881 cs->cpu_index); 6882 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 6883 TARGET_FMT_lx " iidx %d didx %d\n", 6884 env->msr, env->spr[SPR_HID0], 6885 env->hflags, env->immu_idx, env->dmmu_idx); 6886 #if !defined(NO_TIMER_DUMP) 6887 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 6888 #if !defined(CONFIG_USER_ONLY) 6889 " DECR %08" PRIu32 6890 #endif 6891 "\n", 6892 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 6893 #if !defined(CONFIG_USER_ONLY) 6894 , cpu_ppc_load_decr(env) 6895 #endif 6896 ); 6897 #endif 6898 for (i = 0; i < 32; i++) { 6899 if ((i & (RGPL - 1)) == 0) 6900 cpu_fprintf(f, "GPR%02d", i); 6901 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 6902 if ((i & (RGPL - 1)) == (RGPL - 1)) 6903 cpu_fprintf(f, "\n"); 6904 } 6905 cpu_fprintf(f, "CR "); 6906 for (i = 0; i < 8; i++) 6907 cpu_fprintf(f, "%01x", env->crf[i]); 6908 cpu_fprintf(f, " ["); 6909 for (i = 0; i < 8; i++) { 6910 char a = '-'; 6911 if (env->crf[i] & 0x08) 6912 a = 'L'; 6913 else if (env->crf[i] & 0x04) 6914 a = 'G'; 6915 else if (env->crf[i] & 0x02) 6916 a = 'E'; 6917 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 6918 } 6919 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 6920 env->reserve_addr); 6921 for (i = 0; i < 32; i++) { 6922 if ((i & (RFPL - 1)) == 0) 6923 cpu_fprintf(f, "FPR%02d", i); 6924 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); 6925 if ((i & (RFPL - 1)) == (RFPL - 1)) 6926 cpu_fprintf(f, "\n"); 6927 } 6928 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 6929 #if !defined(CONFIG_USER_ONLY) 6930 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 6931 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 6932 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 6933 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 6934 6935 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 6936 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 6937 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 6938 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 6939 6940 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 6941 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 6942 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 6943 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 6944 6945 #if defined(TARGET_PPC64) 6946 if (env->excp_model == POWERPC_EXCP_POWER7 || 6947 env->excp_model == POWERPC_EXCP_POWER8) { 6948 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 6949 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 6950 } 6951 #endif 6952 if (env->excp_model == POWERPC_EXCP_BOOKE) { 6953 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 6954 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 6955 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 6956 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 6957 6958 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 6959 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 6960 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 6961 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 6962 6963 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 6964 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 6965 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 6966 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 6967 6968 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 6969 " EPR " TARGET_FMT_lx "\n", 6970 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 6971 env->spr[SPR_BOOKE_EPR]); 6972 6973 /* FSL-specific */ 6974 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 6975 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 6976 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 6977 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 6978 6979 /* 6980 * IVORs are left out as they are large and do not change often -- 6981 * they can be read with "p $ivor0", "p $ivor1", etc. 6982 */ 6983 } 6984 6985 #if defined(TARGET_PPC64) 6986 if (env->flags & POWERPC_FLAG_CFAR) { 6987 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 6988 } 6989 #endif 6990 6991 if (env->spr_cb[SPR_LPCR].name) 6992 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 6993 6994 switch (env->mmu_model) { 6995 case POWERPC_MMU_32B: 6996 case POWERPC_MMU_601: 6997 case POWERPC_MMU_SOFT_6xx: 6998 case POWERPC_MMU_SOFT_74xx: 6999 #if defined(TARGET_PPC64) 7000 case POWERPC_MMU_64B: 7001 case POWERPC_MMU_2_03: 7002 case POWERPC_MMU_2_06: 7003 case POWERPC_MMU_2_06a: 7004 case POWERPC_MMU_2_07: 7005 case POWERPC_MMU_2_07a: 7006 #endif 7007 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx 7008 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], 7009 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7010 break; 7011 case POWERPC_MMU_BOOKE206: 7012 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7013 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7014 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7015 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7016 7017 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7018 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7019 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7020 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7021 7022 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7023 " TLB1CFG " TARGET_FMT_lx "\n", 7024 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7025 env->spr[SPR_BOOKE_TLB1CFG]); 7026 break; 7027 default: 7028 break; 7029 } 7030 #endif 7031 7032 #undef RGPL 7033 #undef RFPL 7034 } 7035 7036 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, 7037 fprintf_function cpu_fprintf, int flags) 7038 { 7039 #if defined(DO_PPC_STATISTICS) 7040 PowerPCCPU *cpu = POWERPC_CPU(cs); 7041 opc_handler_t **t1, **t2, **t3, *handler; 7042 int op1, op2, op3; 7043 7044 t1 = cpu->env.opcodes; 7045 for (op1 = 0; op1 < 64; op1++) { 7046 handler = t1[op1]; 7047 if (is_indirect_opcode(handler)) { 7048 t2 = ind_table(handler); 7049 for (op2 = 0; op2 < 32; op2++) { 7050 handler = t2[op2]; 7051 if (is_indirect_opcode(handler)) { 7052 t3 = ind_table(handler); 7053 for (op3 = 0; op3 < 32; op3++) { 7054 handler = t3[op3]; 7055 if (handler->count == 0) 7056 continue; 7057 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " 7058 "%016" PRIx64 " %" PRId64 "\n", 7059 op1, op2, op3, op1, (op3 << 5) | op2, 7060 handler->oname, 7061 handler->count, handler->count); 7062 } 7063 } else { 7064 if (handler->count == 0) 7065 continue; 7066 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " 7067 "%016" PRIx64 " %" PRId64 "\n", 7068 op1, op2, op1, op2, handler->oname, 7069 handler->count, handler->count); 7070 } 7071 } 7072 } else { 7073 if (handler->count == 0) 7074 continue; 7075 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 7076 " %" PRId64 "\n", 7077 op1, op1, handler->oname, 7078 handler->count, handler->count); 7079 } 7080 } 7081 #endif 7082 } 7083 7084 /*****************************************************************************/ 7085 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) 7086 { 7087 PowerPCCPU *cpu = ppc_env_get_cpu(env); 7088 CPUState *cs = CPU(cpu); 7089 DisasContext ctx, *ctxp = &ctx; 7090 opc_handler_t **table, *handler; 7091 target_ulong pc_start; 7092 int num_insns; 7093 int max_insns; 7094 7095 pc_start = tb->pc; 7096 ctx.nip = pc_start; 7097 ctx.tb = tb; 7098 ctx.exception = POWERPC_EXCP_NONE; 7099 ctx.spr_cb = env->spr_cb; 7100 ctx.pr = msr_pr; 7101 ctx.mem_idx = env->dmmu_idx; 7102 ctx.dr = msr_dr; 7103 #if !defined(CONFIG_USER_ONLY) 7104 ctx.hv = msr_hv || !env->has_hv_mode; 7105 #endif 7106 ctx.insns_flags = env->insns_flags; 7107 ctx.insns_flags2 = env->insns_flags2; 7108 ctx.access_type = -1; 7109 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7110 ctx.le_mode = !!(env->hflags & (1 << MSR_LE)); 7111 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE; 7112 #if defined(TARGET_PPC64) 7113 ctx.sf_mode = msr_is_64bit(env, env->msr); 7114 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7115 #endif 7116 if (env->mmu_model == POWERPC_MMU_32B || 7117 env->mmu_model == POWERPC_MMU_601 || 7118 (env->mmu_model & POWERPC_MMU_64B)) 7119 ctx.lazy_tlb_flush = true; 7120 7121 ctx.fpu_enabled = !!msr_fp; 7122 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7123 ctx.spe_enabled = !!msr_spe; 7124 else 7125 ctx.spe_enabled = false; 7126 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) 7127 ctx.altivec_enabled = !!msr_vr; 7128 else 7129 ctx.altivec_enabled = false; 7130 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7131 ctx.vsx_enabled = !!msr_vsx; 7132 } else { 7133 ctx.vsx_enabled = false; 7134 } 7135 #if defined(TARGET_PPC64) 7136 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7137 ctx.tm_enabled = !!msr_tm; 7138 } else { 7139 ctx.tm_enabled = false; 7140 } 7141 #endif 7142 if ((env->flags & POWERPC_FLAG_SE) && msr_se) 7143 ctx.singlestep_enabled = CPU_SINGLE_STEP; 7144 else 7145 ctx.singlestep_enabled = 0; 7146 if ((env->flags & POWERPC_FLAG_BE) && msr_be) 7147 ctx.singlestep_enabled |= CPU_BRANCH_STEP; 7148 if (unlikely(cs->singlestep_enabled)) { 7149 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7150 } 7151 #if defined (DO_SINGLE_STEP) && 0 7152 /* Single step trace mode */ 7153 msr_se = 1; 7154 #endif 7155 num_insns = 0; 7156 max_insns = tb->cflags & CF_COUNT_MASK; 7157 if (max_insns == 0) { 7158 max_insns = CF_COUNT_MASK; 7159 } 7160 if (max_insns > TCG_MAX_INSNS) { 7161 max_insns = TCG_MAX_INSNS; 7162 } 7163 7164 gen_tb_start(tb); 7165 tcg_clear_temp_count(); 7166 /* Set env in case of segfault during code fetch */ 7167 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) { 7168 tcg_gen_insn_start(ctx.nip); 7169 num_insns++; 7170 7171 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) { 7172 gen_debug_exception(ctxp); 7173 /* The address covered by the breakpoint must be included in 7174 [tb->pc, tb->pc + tb->size) in order to for it to be 7175 properly cleared -- thus we increment the PC here so that 7176 the logic setting tb->size below does the right thing. */ 7177 ctx.nip += 4; 7178 break; 7179 } 7180 7181 LOG_DISAS("----------------\n"); 7182 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7183 ctx.nip, ctx.mem_idx, (int)msr_ir); 7184 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) 7185 gen_io_start(); 7186 if (unlikely(need_byteswap(&ctx))) { 7187 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); 7188 } else { 7189 ctx.opcode = cpu_ldl_code(env, ctx.nip); 7190 } 7191 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7192 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), 7193 opc3(ctx.opcode), opc4(ctx.opcode), 7194 ctx.le_mode ? "little" : "big"); 7195 ctx.nip += 4; 7196 table = env->opcodes; 7197 handler = table[opc1(ctx.opcode)]; 7198 if (is_indirect_opcode(handler)) { 7199 table = ind_table(handler); 7200 handler = table[opc2(ctx.opcode)]; 7201 if (is_indirect_opcode(handler)) { 7202 table = ind_table(handler); 7203 handler = table[opc3(ctx.opcode)]; 7204 if (is_indirect_opcode(handler)) { 7205 table = ind_table(handler); 7206 handler = table[opc4(ctx.opcode)]; 7207 } 7208 } 7209 } 7210 /* Is opcode *REALLY* valid ? */ 7211 if (unlikely(handler->handler == &gen_invalid)) { 7212 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7213 "%02x - %02x - %02x - %02x (%08x) " 7214 TARGET_FMT_lx " %d\n", 7215 opc1(ctx.opcode), opc2(ctx.opcode), 7216 opc3(ctx.opcode), opc4(ctx.opcode), 7217 ctx.opcode, ctx.nip - 4, (int)msr_ir); 7218 } else { 7219 uint32_t inval; 7220 7221 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { 7222 inval = handler->inval2; 7223 } else { 7224 inval = handler->inval1; 7225 } 7226 7227 if (unlikely((ctx.opcode & inval) != 0)) { 7228 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7229 "%02x - %02x - %02x - %02x (%08x) " 7230 TARGET_FMT_lx "\n", ctx.opcode & inval, 7231 opc1(ctx.opcode), opc2(ctx.opcode), 7232 opc3(ctx.opcode), opc4(ctx.opcode), 7233 ctx.opcode, ctx.nip - 4); 7234 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); 7235 break; 7236 } 7237 } 7238 (*(handler->handler))(&ctx); 7239 #if defined(DO_PPC_STATISTICS) 7240 handler->count++; 7241 #endif 7242 /* Check trace mode exceptions */ 7243 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && 7244 (ctx.nip <= 0x100 || ctx.nip > 0xF00) && 7245 ctx.exception != POWERPC_SYSCALL && 7246 ctx.exception != POWERPC_EXCP_TRAP && 7247 ctx.exception != POWERPC_EXCP_BRANCH)) { 7248 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip); 7249 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || 7250 (cs->singlestep_enabled) || 7251 singlestep || 7252 num_insns >= max_insns)) { 7253 /* if we reach a page boundary or are single stepping, stop 7254 * generation 7255 */ 7256 break; 7257 } 7258 if (tcg_check_temp_count()) { 7259 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked " 7260 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode), 7261 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode); 7262 exit(1); 7263 } 7264 } 7265 if (tb->cflags & CF_LAST_IO) 7266 gen_io_end(); 7267 if (ctx.exception == POWERPC_EXCP_NONE) { 7268 gen_goto_tb(&ctx, 0, ctx.nip); 7269 } else if (ctx.exception != POWERPC_EXCP_BRANCH) { 7270 if (unlikely(cs->singlestep_enabled)) { 7271 gen_debug_exception(ctxp); 7272 } 7273 /* Generate the return instruction */ 7274 tcg_gen_exit_tb(0); 7275 } 7276 gen_tb_end(tb, num_insns); 7277 7278 tb->size = ctx.nip - pc_start; 7279 tb->icount = num_insns; 7280 7281 #if defined(DEBUG_DISAS) 7282 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 7283 && qemu_log_in_addr_range(pc_start)) { 7284 int flags; 7285 flags = env->bfd_mach; 7286 flags |= ctx.le_mode << 16; 7287 qemu_log_lock(); 7288 qemu_log("IN: %s\n", lookup_symbol(pc_start)); 7289 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags); 7290 qemu_log("\n"); 7291 qemu_log_unlock(); 7292 } 7293 #endif 7294 } 7295 7296 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7297 target_ulong *data) 7298 { 7299 env->nip = data[0]; 7300 } 7301