1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg-op.h" 27 #include "qemu/host-utils.h" 28 #include "exec/cpu_ldst.h" 29 30 #include "exec/helper-proto.h" 31 #include "exec/helper-gen.h" 32 33 #include "trace-tcg.h" 34 #include "exec/translator.h" 35 #include "exec/log.h" 36 #include "qemu/atomic128.h" 37 38 39 #define CPU_SINGLE_STEP 0x1 40 #define CPU_BRANCH_STEP 0x2 41 #define GDBSTUB_SINGLE_STEP 0x4 42 43 /* Include definitions for instructions classes and implementations flags */ 44 //#define PPC_DEBUG_DISAS 45 //#define DO_PPC_STATISTICS 46 47 #ifdef PPC_DEBUG_DISAS 48 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 49 #else 50 # define LOG_DISAS(...) do { } while (0) 51 #endif 52 /*****************************************************************************/ 53 /* Code translation helpers */ 54 55 /* global register indexes */ 56 static char cpu_reg_names[10*3 + 22*4 /* GPR */ 57 + 10*4 + 22*5 /* SPE GPRh */ 58 + 10*4 + 22*5 /* FPR */ 59 + 2*(10*6 + 22*7) /* AVRh, AVRl */ 60 + 10*5 + 22*6 /* VSR */ 61 + 8*5 /* CRF */]; 62 static TCGv cpu_gpr[32]; 63 static TCGv cpu_gprh[32]; 64 static TCGv_i64 cpu_fpr[32]; 65 static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; 66 static TCGv_i64 cpu_vsr[32]; 67 static TCGv_i32 cpu_crf[8]; 68 static TCGv cpu_nip; 69 static TCGv cpu_msr; 70 static TCGv cpu_ctr; 71 static TCGv cpu_lr; 72 #if defined(TARGET_PPC64) 73 static TCGv cpu_cfar; 74 #endif 75 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 76 static TCGv cpu_reserve; 77 static TCGv cpu_reserve_val; 78 static TCGv cpu_fpscr; 79 static TCGv_i32 cpu_access_type; 80 81 #include "exec/gen-icount.h" 82 83 void ppc_translate_init(void) 84 { 85 int i; 86 char* p; 87 size_t cpu_reg_names_size; 88 89 p = cpu_reg_names; 90 cpu_reg_names_size = sizeof(cpu_reg_names); 91 92 for (i = 0; i < 8; i++) { 93 snprintf(p, cpu_reg_names_size, "crf%d", i); 94 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 95 offsetof(CPUPPCState, crf[i]), p); 96 p += 5; 97 cpu_reg_names_size -= 5; 98 } 99 100 for (i = 0; i < 32; i++) { 101 snprintf(p, cpu_reg_names_size, "r%d", i); 102 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 103 offsetof(CPUPPCState, gpr[i]), p); 104 p += (i < 10) ? 3 : 4; 105 cpu_reg_names_size -= (i < 10) ? 3 : 4; 106 snprintf(p, cpu_reg_names_size, "r%dH", i); 107 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 108 offsetof(CPUPPCState, gprh[i]), p); 109 p += (i < 10) ? 4 : 5; 110 cpu_reg_names_size -= (i < 10) ? 4 : 5; 111 112 snprintf(p, cpu_reg_names_size, "fp%d", i); 113 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 114 offsetof(CPUPPCState, fpr[i]), p); 115 p += (i < 10) ? 4 : 5; 116 cpu_reg_names_size -= (i < 10) ? 4 : 5; 117 118 snprintf(p, cpu_reg_names_size, "avr%dH", i); 119 #ifdef HOST_WORDS_BIGENDIAN 120 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 121 offsetof(CPUPPCState, avr[i].u64[0]), p); 122 #else 123 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 124 offsetof(CPUPPCState, avr[i].u64[1]), p); 125 #endif 126 p += (i < 10) ? 6 : 7; 127 cpu_reg_names_size -= (i < 10) ? 6 : 7; 128 129 snprintf(p, cpu_reg_names_size, "avr%dL", i); 130 #ifdef HOST_WORDS_BIGENDIAN 131 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 132 offsetof(CPUPPCState, avr[i].u64[1]), p); 133 #else 134 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 135 offsetof(CPUPPCState, avr[i].u64[0]), p); 136 #endif 137 p += (i < 10) ? 6 : 7; 138 cpu_reg_names_size -= (i < 10) ? 6 : 7; 139 snprintf(p, cpu_reg_names_size, "vsr%d", i); 140 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, 141 offsetof(CPUPPCState, vsr[i]), p); 142 p += (i < 10) ? 5 : 6; 143 cpu_reg_names_size -= (i < 10) ? 5 : 6; 144 } 145 146 cpu_nip = tcg_global_mem_new(cpu_env, 147 offsetof(CPUPPCState, nip), "nip"); 148 149 cpu_msr = tcg_global_mem_new(cpu_env, 150 offsetof(CPUPPCState, msr), "msr"); 151 152 cpu_ctr = tcg_global_mem_new(cpu_env, 153 offsetof(CPUPPCState, ctr), "ctr"); 154 155 cpu_lr = tcg_global_mem_new(cpu_env, 156 offsetof(CPUPPCState, lr), "lr"); 157 158 #if defined(TARGET_PPC64) 159 cpu_cfar = tcg_global_mem_new(cpu_env, 160 offsetof(CPUPPCState, cfar), "cfar"); 161 #endif 162 163 cpu_xer = tcg_global_mem_new(cpu_env, 164 offsetof(CPUPPCState, xer), "xer"); 165 cpu_so = tcg_global_mem_new(cpu_env, 166 offsetof(CPUPPCState, so), "SO"); 167 cpu_ov = tcg_global_mem_new(cpu_env, 168 offsetof(CPUPPCState, ov), "OV"); 169 cpu_ca = tcg_global_mem_new(cpu_env, 170 offsetof(CPUPPCState, ca), "CA"); 171 cpu_ov32 = tcg_global_mem_new(cpu_env, 172 offsetof(CPUPPCState, ov32), "OV32"); 173 cpu_ca32 = tcg_global_mem_new(cpu_env, 174 offsetof(CPUPPCState, ca32), "CA32"); 175 176 cpu_reserve = tcg_global_mem_new(cpu_env, 177 offsetof(CPUPPCState, reserve_addr), 178 "reserve_addr"); 179 cpu_reserve_val = tcg_global_mem_new(cpu_env, 180 offsetof(CPUPPCState, reserve_val), 181 "reserve_val"); 182 183 cpu_fpscr = tcg_global_mem_new(cpu_env, 184 offsetof(CPUPPCState, fpscr), "fpscr"); 185 186 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 187 offsetof(CPUPPCState, access_type), "access_type"); 188 } 189 190 /* internal defines */ 191 struct DisasContext { 192 DisasContextBase base; 193 uint32_t opcode; 194 uint32_t exception; 195 /* Routine used to access memory */ 196 bool pr, hv, dr, le_mode; 197 bool lazy_tlb_flush; 198 bool need_access_type; 199 int mem_idx; 200 int access_type; 201 /* Translation flags */ 202 TCGMemOp default_tcg_memop_mask; 203 #if defined(TARGET_PPC64) 204 bool sf_mode; 205 bool has_cfar; 206 #endif 207 bool fpu_enabled; 208 bool altivec_enabled; 209 bool vsx_enabled; 210 bool spe_enabled; 211 bool tm_enabled; 212 bool gtse; 213 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 214 int singlestep_enabled; 215 uint32_t flags; 216 uint64_t insns_flags; 217 uint64_t insns_flags2; 218 }; 219 220 /* Return true iff byteswap is needed in a scalar memop */ 221 static inline bool need_byteswap(const DisasContext *ctx) 222 { 223 #if defined(TARGET_WORDS_BIGENDIAN) 224 return ctx->le_mode; 225 #else 226 return !ctx->le_mode; 227 #endif 228 } 229 230 /* True when active word size < size of target_long. */ 231 #ifdef TARGET_PPC64 232 # define NARROW_MODE(C) (!(C)->sf_mode) 233 #else 234 # define NARROW_MODE(C) 0 235 #endif 236 237 struct opc_handler_t { 238 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 239 uint32_t inval1; 240 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 241 uint32_t inval2; 242 /* instruction type */ 243 uint64_t type; 244 /* extended instruction type */ 245 uint64_t type2; 246 /* handler */ 247 void (*handler)(DisasContext *ctx); 248 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 249 const char *oname; 250 #endif 251 #if defined(DO_PPC_STATISTICS) 252 uint64_t count; 253 #endif 254 }; 255 256 /* SPR load/store helpers */ 257 static inline void gen_load_spr(TCGv t, int reg) 258 { 259 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 260 } 261 262 static inline void gen_store_spr(int reg, TCGv t) 263 { 264 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 265 } 266 267 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 268 { 269 if (ctx->need_access_type && ctx->access_type != access_type) { 270 tcg_gen_movi_i32(cpu_access_type, access_type); 271 ctx->access_type = access_type; 272 } 273 } 274 275 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 276 { 277 if (NARROW_MODE(ctx)) { 278 nip = (uint32_t)nip; 279 } 280 tcg_gen_movi_tl(cpu_nip, nip); 281 } 282 283 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 284 { 285 TCGv_i32 t0, t1; 286 287 /* These are all synchronous exceptions, we set the PC back to 288 * the faulting instruction 289 */ 290 if (ctx->exception == POWERPC_EXCP_NONE) { 291 gen_update_nip(ctx, ctx->base.pc_next - 4); 292 } 293 t0 = tcg_const_i32(excp); 294 t1 = tcg_const_i32(error); 295 gen_helper_raise_exception_err(cpu_env, t0, t1); 296 tcg_temp_free_i32(t0); 297 tcg_temp_free_i32(t1); 298 ctx->exception = (excp); 299 } 300 301 static void gen_exception(DisasContext *ctx, uint32_t excp) 302 { 303 TCGv_i32 t0; 304 305 /* These are all synchronous exceptions, we set the PC back to 306 * the faulting instruction 307 */ 308 if (ctx->exception == POWERPC_EXCP_NONE) { 309 gen_update_nip(ctx, ctx->base.pc_next - 4); 310 } 311 t0 = tcg_const_i32(excp); 312 gen_helper_raise_exception(cpu_env, t0); 313 tcg_temp_free_i32(t0); 314 ctx->exception = (excp); 315 } 316 317 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 318 target_ulong nip) 319 { 320 TCGv_i32 t0; 321 322 gen_update_nip(ctx, nip); 323 t0 = tcg_const_i32(excp); 324 gen_helper_raise_exception(cpu_env, t0); 325 tcg_temp_free_i32(t0); 326 ctx->exception = (excp); 327 } 328 329 /* Translates the EXCP_TRACE/BRANCH exceptions used on most PowerPCs to 330 * EXCP_DEBUG, if we are running on cores using the debug enable bit (e.g. 331 * BookE). 332 */ 333 static uint32_t gen_prep_dbgex(DisasContext *ctx, uint32_t excp) 334 { 335 if ((ctx->singlestep_enabled & CPU_SINGLE_STEP) 336 && (excp == POWERPC_EXCP_BRANCH)) { 337 /* Trace excpt. has priority */ 338 excp = POWERPC_EXCP_TRACE; 339 } 340 if (ctx->flags & POWERPC_FLAG_DE) { 341 target_ulong dbsr = 0; 342 switch (excp) { 343 case POWERPC_EXCP_TRACE: 344 dbsr = DBCR0_ICMP; 345 break; 346 case POWERPC_EXCP_BRANCH: 347 dbsr = DBCR0_BRT; 348 break; 349 } 350 TCGv t0 = tcg_temp_new(); 351 gen_load_spr(t0, SPR_BOOKE_DBSR); 352 tcg_gen_ori_tl(t0, t0, dbsr); 353 gen_store_spr(SPR_BOOKE_DBSR, t0); 354 tcg_temp_free(t0); 355 return POWERPC_EXCP_DEBUG; 356 } else { 357 return excp; 358 } 359 } 360 361 static void gen_debug_exception(DisasContext *ctx) 362 { 363 TCGv_i32 t0; 364 365 /* These are all synchronous exceptions, we set the PC back to 366 * the faulting instruction 367 */ 368 if ((ctx->exception != POWERPC_EXCP_BRANCH) && 369 (ctx->exception != POWERPC_EXCP_SYNC)) { 370 gen_update_nip(ctx, ctx->base.pc_next); 371 } 372 t0 = tcg_const_i32(EXCP_DEBUG); 373 gen_helper_raise_exception(cpu_env, t0); 374 tcg_temp_free_i32(t0); 375 } 376 377 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 378 { 379 /* Will be converted to program check if needed */ 380 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 381 } 382 383 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 384 { 385 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 386 } 387 388 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 389 { 390 /* Will be converted to program check if needed */ 391 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 392 } 393 394 /* Stop translation */ 395 static inline void gen_stop_exception(DisasContext *ctx) 396 { 397 gen_update_nip(ctx, ctx->base.pc_next); 398 ctx->exception = POWERPC_EXCP_STOP; 399 } 400 401 #ifndef CONFIG_USER_ONLY 402 /* No need to update nip here, as execution flow will change */ 403 static inline void gen_sync_exception(DisasContext *ctx) 404 { 405 ctx->exception = POWERPC_EXCP_SYNC; 406 } 407 #endif 408 409 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 410 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 411 412 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 413 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 414 415 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 416 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 417 418 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 419 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 420 421 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 422 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 423 424 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 425 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 426 427 typedef struct opcode_t { 428 unsigned char opc1, opc2, opc3, opc4; 429 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 430 unsigned char pad[4]; 431 #endif 432 opc_handler_t handler; 433 const char *oname; 434 } opcode_t; 435 436 /* Helpers for priv. check */ 437 #define GEN_PRIV \ 438 do { \ 439 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 440 } while (0) 441 442 #if defined(CONFIG_USER_ONLY) 443 #define CHK_HV GEN_PRIV 444 #define CHK_SV GEN_PRIV 445 #define CHK_HVRM GEN_PRIV 446 #else 447 #define CHK_HV \ 448 do { \ 449 if (unlikely(ctx->pr || !ctx->hv)) { \ 450 GEN_PRIV; \ 451 } \ 452 } while (0) 453 #define CHK_SV \ 454 do { \ 455 if (unlikely(ctx->pr)) { \ 456 GEN_PRIV; \ 457 } \ 458 } while (0) 459 #define CHK_HVRM \ 460 do { \ 461 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 462 GEN_PRIV; \ 463 } \ 464 } while (0) 465 #endif 466 467 #define CHK_NONE 468 469 /*****************************************************************************/ 470 /* PowerPC instructions table */ 471 472 #if defined(DO_PPC_STATISTICS) 473 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 474 { \ 475 .opc1 = op1, \ 476 .opc2 = op2, \ 477 .opc3 = op3, \ 478 .opc4 = 0xff, \ 479 .handler = { \ 480 .inval1 = invl, \ 481 .type = _typ, \ 482 .type2 = _typ2, \ 483 .handler = &gen_##name, \ 484 .oname = stringify(name), \ 485 }, \ 486 .oname = stringify(name), \ 487 } 488 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 489 { \ 490 .opc1 = op1, \ 491 .opc2 = op2, \ 492 .opc3 = op3, \ 493 .opc4 = 0xff, \ 494 .handler = { \ 495 .inval1 = invl1, \ 496 .inval2 = invl2, \ 497 .type = _typ, \ 498 .type2 = _typ2, \ 499 .handler = &gen_##name, \ 500 .oname = stringify(name), \ 501 }, \ 502 .oname = stringify(name), \ 503 } 504 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 505 { \ 506 .opc1 = op1, \ 507 .opc2 = op2, \ 508 .opc3 = op3, \ 509 .opc4 = 0xff, \ 510 .handler = { \ 511 .inval1 = invl, \ 512 .type = _typ, \ 513 .type2 = _typ2, \ 514 .handler = &gen_##name, \ 515 .oname = onam, \ 516 }, \ 517 .oname = onam, \ 518 } 519 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 520 { \ 521 .opc1 = op1, \ 522 .opc2 = op2, \ 523 .opc3 = op3, \ 524 .opc4 = op4, \ 525 .handler = { \ 526 .inval1 = invl, \ 527 .type = _typ, \ 528 .type2 = _typ2, \ 529 .handler = &gen_##name, \ 530 .oname = stringify(name), \ 531 }, \ 532 .oname = stringify(name), \ 533 } 534 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 535 { \ 536 .opc1 = op1, \ 537 .opc2 = op2, \ 538 .opc3 = op3, \ 539 .opc4 = op4, \ 540 .handler = { \ 541 .inval1 = invl, \ 542 .type = _typ, \ 543 .type2 = _typ2, \ 544 .handler = &gen_##name, \ 545 .oname = onam, \ 546 }, \ 547 .oname = onam, \ 548 } 549 #else 550 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 551 { \ 552 .opc1 = op1, \ 553 .opc2 = op2, \ 554 .opc3 = op3, \ 555 .opc4 = 0xff, \ 556 .handler = { \ 557 .inval1 = invl, \ 558 .type = _typ, \ 559 .type2 = _typ2, \ 560 .handler = &gen_##name, \ 561 }, \ 562 .oname = stringify(name), \ 563 } 564 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 565 { \ 566 .opc1 = op1, \ 567 .opc2 = op2, \ 568 .opc3 = op3, \ 569 .opc4 = 0xff, \ 570 .handler = { \ 571 .inval1 = invl1, \ 572 .inval2 = invl2, \ 573 .type = _typ, \ 574 .type2 = _typ2, \ 575 .handler = &gen_##name, \ 576 }, \ 577 .oname = stringify(name), \ 578 } 579 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 580 { \ 581 .opc1 = op1, \ 582 .opc2 = op2, \ 583 .opc3 = op3, \ 584 .opc4 = 0xff, \ 585 .handler = { \ 586 .inval1 = invl, \ 587 .type = _typ, \ 588 .type2 = _typ2, \ 589 .handler = &gen_##name, \ 590 }, \ 591 .oname = onam, \ 592 } 593 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 594 { \ 595 .opc1 = op1, \ 596 .opc2 = op2, \ 597 .opc3 = op3, \ 598 .opc4 = op4, \ 599 .handler = { \ 600 .inval1 = invl, \ 601 .type = _typ, \ 602 .type2 = _typ2, \ 603 .handler = &gen_##name, \ 604 }, \ 605 .oname = stringify(name), \ 606 } 607 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 608 { \ 609 .opc1 = op1, \ 610 .opc2 = op2, \ 611 .opc3 = op3, \ 612 .opc4 = op4, \ 613 .handler = { \ 614 .inval1 = invl, \ 615 .type = _typ, \ 616 .type2 = _typ2, \ 617 .handler = &gen_##name, \ 618 }, \ 619 .oname = onam, \ 620 } 621 #endif 622 623 /* Invalid instruction */ 624 static void gen_invalid(DisasContext *ctx) 625 { 626 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 627 } 628 629 static opc_handler_t invalid_handler = { 630 .inval1 = 0xFFFFFFFF, 631 .inval2 = 0xFFFFFFFF, 632 .type = PPC_NONE, 633 .type2 = PPC_NONE, 634 .handler = gen_invalid, 635 }; 636 637 /*** Integer comparison ***/ 638 639 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 640 { 641 TCGv t0 = tcg_temp_new(); 642 TCGv t1 = tcg_temp_new(); 643 TCGv_i32 t = tcg_temp_new_i32(); 644 645 tcg_gen_movi_tl(t0, CRF_EQ); 646 tcg_gen_movi_tl(t1, CRF_LT); 647 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0); 648 tcg_gen_movi_tl(t1, CRF_GT); 649 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0); 650 651 tcg_gen_trunc_tl_i32(t, t0); 652 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 653 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 654 655 tcg_temp_free(t0); 656 tcg_temp_free(t1); 657 tcg_temp_free_i32(t); 658 } 659 660 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 661 { 662 TCGv t0 = tcg_const_tl(arg1); 663 gen_op_cmp(arg0, t0, s, crf); 664 tcg_temp_free(t0); 665 } 666 667 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 668 { 669 TCGv t0, t1; 670 t0 = tcg_temp_new(); 671 t1 = tcg_temp_new(); 672 if (s) { 673 tcg_gen_ext32s_tl(t0, arg0); 674 tcg_gen_ext32s_tl(t1, arg1); 675 } else { 676 tcg_gen_ext32u_tl(t0, arg0); 677 tcg_gen_ext32u_tl(t1, arg1); 678 } 679 gen_op_cmp(t0, t1, s, crf); 680 tcg_temp_free(t1); 681 tcg_temp_free(t0); 682 } 683 684 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 685 { 686 TCGv t0 = tcg_const_tl(arg1); 687 gen_op_cmp32(arg0, t0, s, crf); 688 tcg_temp_free(t0); 689 } 690 691 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 692 { 693 if (NARROW_MODE(ctx)) { 694 gen_op_cmpi32(reg, 0, 1, 0); 695 } else { 696 gen_op_cmpi(reg, 0, 1, 0); 697 } 698 } 699 700 /* cmp */ 701 static void gen_cmp(DisasContext *ctx) 702 { 703 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 704 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 705 1, crfD(ctx->opcode)); 706 } else { 707 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 708 1, crfD(ctx->opcode)); 709 } 710 } 711 712 /* cmpi */ 713 static void gen_cmpi(DisasContext *ctx) 714 { 715 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 716 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 717 1, crfD(ctx->opcode)); 718 } else { 719 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 720 1, crfD(ctx->opcode)); 721 } 722 } 723 724 /* cmpl */ 725 static void gen_cmpl(DisasContext *ctx) 726 { 727 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 728 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 729 0, crfD(ctx->opcode)); 730 } else { 731 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 732 0, crfD(ctx->opcode)); 733 } 734 } 735 736 /* cmpli */ 737 static void gen_cmpli(DisasContext *ctx) 738 { 739 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 740 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 741 0, crfD(ctx->opcode)); 742 } else { 743 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 744 0, crfD(ctx->opcode)); 745 } 746 } 747 748 /* cmprb - range comparison: isupper, isaplha, islower*/ 749 static void gen_cmprb(DisasContext *ctx) 750 { 751 TCGv_i32 src1 = tcg_temp_new_i32(); 752 TCGv_i32 src2 = tcg_temp_new_i32(); 753 TCGv_i32 src2lo = tcg_temp_new_i32(); 754 TCGv_i32 src2hi = tcg_temp_new_i32(); 755 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 756 757 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 758 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 759 760 tcg_gen_andi_i32(src1, src1, 0xFF); 761 tcg_gen_ext8u_i32(src2lo, src2); 762 tcg_gen_shri_i32(src2, src2, 8); 763 tcg_gen_ext8u_i32(src2hi, src2); 764 765 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 766 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 767 tcg_gen_and_i32(crf, src2lo, src2hi); 768 769 if (ctx->opcode & 0x00200000) { 770 tcg_gen_shri_i32(src2, src2, 8); 771 tcg_gen_ext8u_i32(src2lo, src2); 772 tcg_gen_shri_i32(src2, src2, 8); 773 tcg_gen_ext8u_i32(src2hi, src2); 774 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 775 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 776 tcg_gen_and_i32(src2lo, src2lo, src2hi); 777 tcg_gen_or_i32(crf, crf, src2lo); 778 } 779 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 780 tcg_temp_free_i32(src1); 781 tcg_temp_free_i32(src2); 782 tcg_temp_free_i32(src2lo); 783 tcg_temp_free_i32(src2hi); 784 } 785 786 #if defined(TARGET_PPC64) 787 /* cmpeqb */ 788 static void gen_cmpeqb(DisasContext *ctx) 789 { 790 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 791 cpu_gpr[rB(ctx->opcode)]); 792 } 793 #endif 794 795 /* isel (PowerPC 2.03 specification) */ 796 static void gen_isel(DisasContext *ctx) 797 { 798 uint32_t bi = rC(ctx->opcode); 799 uint32_t mask = 0x08 >> (bi & 0x03); 800 TCGv t0 = tcg_temp_new(); 801 TCGv zr; 802 803 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 804 tcg_gen_andi_tl(t0, t0, mask); 805 806 zr = tcg_const_tl(0); 807 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 808 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 809 cpu_gpr[rB(ctx->opcode)]); 810 tcg_temp_free(zr); 811 tcg_temp_free(t0); 812 } 813 814 /* cmpb: PowerPC 2.05 specification */ 815 static void gen_cmpb(DisasContext *ctx) 816 { 817 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 818 cpu_gpr[rB(ctx->opcode)]); 819 } 820 821 /*** Integer arithmetic ***/ 822 823 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 824 TCGv arg1, TCGv arg2, int sub) 825 { 826 TCGv t0 = tcg_temp_new(); 827 828 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 829 tcg_gen_xor_tl(t0, arg1, arg2); 830 if (sub) { 831 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 832 } else { 833 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 834 } 835 tcg_temp_free(t0); 836 if (NARROW_MODE(ctx)) { 837 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 838 if (is_isa300(ctx)) { 839 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 840 } 841 } else { 842 if (is_isa300(ctx)) { 843 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 844 } 845 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 846 } 847 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 848 } 849 850 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 851 TCGv res, TCGv arg0, TCGv arg1, 852 int sub) 853 { 854 TCGv t0; 855 856 if (!is_isa300(ctx)) { 857 return; 858 } 859 860 t0 = tcg_temp_new(); 861 if (sub) { 862 tcg_gen_eqv_tl(t0, arg0, arg1); 863 } else { 864 tcg_gen_xor_tl(t0, arg0, arg1); 865 } 866 tcg_gen_xor_tl(t0, t0, res); 867 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1); 868 tcg_temp_free(t0); 869 } 870 871 /* Common add function */ 872 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 873 TCGv arg2, bool add_ca, bool compute_ca, 874 bool compute_ov, bool compute_rc0) 875 { 876 TCGv t0 = ret; 877 878 if (compute_ca || compute_ov) { 879 t0 = tcg_temp_new(); 880 } 881 882 if (compute_ca) { 883 if (NARROW_MODE(ctx)) { 884 /* Caution: a non-obvious corner case of the spec is that we 885 must produce the *entire* 64-bit addition, but produce the 886 carry into bit 32. */ 887 TCGv t1 = tcg_temp_new(); 888 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 889 tcg_gen_add_tl(t0, arg1, arg2); 890 if (add_ca) { 891 tcg_gen_add_tl(t0, t0, cpu_ca); 892 } 893 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ 894 tcg_temp_free(t1); 895 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 896 if (is_isa300(ctx)) { 897 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 898 } 899 } else { 900 TCGv zero = tcg_const_tl(0); 901 if (add_ca) { 902 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); 903 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); 904 } else { 905 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); 906 } 907 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0); 908 tcg_temp_free(zero); 909 } 910 } else { 911 tcg_gen_add_tl(t0, arg1, arg2); 912 if (add_ca) { 913 tcg_gen_add_tl(t0, t0, cpu_ca); 914 } 915 } 916 917 if (compute_ov) { 918 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 919 } 920 if (unlikely(compute_rc0)) { 921 gen_set_Rc0(ctx, t0); 922 } 923 924 if (t0 != ret) { 925 tcg_gen_mov_tl(ret, t0); 926 tcg_temp_free(t0); 927 } 928 } 929 /* Add functions with two operands */ 930 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 931 static void glue(gen_, name)(DisasContext *ctx) \ 932 { \ 933 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 934 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 935 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 936 } 937 /* Add functions with one operand and one immediate */ 938 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 939 add_ca, compute_ca, compute_ov) \ 940 static void glue(gen_, name)(DisasContext *ctx) \ 941 { \ 942 TCGv t0 = tcg_const_tl(const_val); \ 943 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 944 cpu_gpr[rA(ctx->opcode)], t0, \ 945 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 946 tcg_temp_free(t0); \ 947 } 948 949 /* add add. addo addo. */ 950 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 951 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 952 /* addc addc. addco addco. */ 953 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 954 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 955 /* adde adde. addeo addeo. */ 956 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 957 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 958 /* addme addme. addmeo addmeo. */ 959 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 960 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 961 /* addze addze. addzeo addzeo.*/ 962 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 963 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 964 /* addi */ 965 static void gen_addi(DisasContext *ctx) 966 { 967 target_long simm = SIMM(ctx->opcode); 968 969 if (rA(ctx->opcode) == 0) { 970 /* li case */ 971 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 972 } else { 973 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 974 cpu_gpr[rA(ctx->opcode)], simm); 975 } 976 } 977 /* addic addic.*/ 978 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 979 { 980 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 981 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 982 c, 0, 1, 0, compute_rc0); 983 tcg_temp_free(c); 984 } 985 986 static void gen_addic(DisasContext *ctx) 987 { 988 gen_op_addic(ctx, 0); 989 } 990 991 static void gen_addic_(DisasContext *ctx) 992 { 993 gen_op_addic(ctx, 1); 994 } 995 996 /* addis */ 997 static void gen_addis(DisasContext *ctx) 998 { 999 target_long simm = SIMM(ctx->opcode); 1000 1001 if (rA(ctx->opcode) == 0) { 1002 /* lis case */ 1003 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 1004 } else { 1005 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1006 cpu_gpr[rA(ctx->opcode)], simm << 16); 1007 } 1008 } 1009 1010 /* addpcis */ 1011 static void gen_addpcis(DisasContext *ctx) 1012 { 1013 target_long d = DX(ctx->opcode); 1014 1015 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 1016 } 1017 1018 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1019 TCGv arg2, int sign, int compute_ov) 1020 { 1021 TCGv_i32 t0 = tcg_temp_new_i32(); 1022 TCGv_i32 t1 = tcg_temp_new_i32(); 1023 TCGv_i32 t2 = tcg_temp_new_i32(); 1024 TCGv_i32 t3 = tcg_temp_new_i32(); 1025 1026 tcg_gen_trunc_tl_i32(t0, arg1); 1027 tcg_gen_trunc_tl_i32(t1, arg2); 1028 if (sign) { 1029 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1030 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1031 tcg_gen_and_i32(t2, t2, t3); 1032 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1033 tcg_gen_or_i32(t2, t2, t3); 1034 tcg_gen_movi_i32(t3, 0); 1035 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1036 tcg_gen_div_i32(t3, t0, t1); 1037 tcg_gen_extu_i32_tl(ret, t3); 1038 } else { 1039 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1040 tcg_gen_movi_i32(t3, 0); 1041 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1042 tcg_gen_divu_i32(t3, t0, t1); 1043 tcg_gen_extu_i32_tl(ret, t3); 1044 } 1045 if (compute_ov) { 1046 tcg_gen_extu_i32_tl(cpu_ov, t2); 1047 if (is_isa300(ctx)) { 1048 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1049 } 1050 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1051 } 1052 tcg_temp_free_i32(t0); 1053 tcg_temp_free_i32(t1); 1054 tcg_temp_free_i32(t2); 1055 tcg_temp_free_i32(t3); 1056 1057 if (unlikely(Rc(ctx->opcode) != 0)) 1058 gen_set_Rc0(ctx, ret); 1059 } 1060 /* Div functions */ 1061 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1062 static void glue(gen_, name)(DisasContext *ctx) \ 1063 { \ 1064 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1065 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1066 sign, compute_ov); \ 1067 } 1068 /* divwu divwu. divwuo divwuo. */ 1069 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1070 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1071 /* divw divw. divwo divwo. */ 1072 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1073 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1074 1075 /* div[wd]eu[o][.] */ 1076 #define GEN_DIVE(name, hlpr, compute_ov) \ 1077 static void gen_##name(DisasContext *ctx) \ 1078 { \ 1079 TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1080 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1081 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1082 tcg_temp_free_i32(t0); \ 1083 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1084 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1085 } \ 1086 } 1087 1088 GEN_DIVE(divweu, divweu, 0); 1089 GEN_DIVE(divweuo, divweu, 1); 1090 GEN_DIVE(divwe, divwe, 0); 1091 GEN_DIVE(divweo, divwe, 1); 1092 1093 #if defined(TARGET_PPC64) 1094 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1095 TCGv arg2, int sign, int compute_ov) 1096 { 1097 TCGv_i64 t0 = tcg_temp_new_i64(); 1098 TCGv_i64 t1 = tcg_temp_new_i64(); 1099 TCGv_i64 t2 = tcg_temp_new_i64(); 1100 TCGv_i64 t3 = tcg_temp_new_i64(); 1101 1102 tcg_gen_mov_i64(t0, arg1); 1103 tcg_gen_mov_i64(t1, arg2); 1104 if (sign) { 1105 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1106 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1107 tcg_gen_and_i64(t2, t2, t3); 1108 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1109 tcg_gen_or_i64(t2, t2, t3); 1110 tcg_gen_movi_i64(t3, 0); 1111 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1112 tcg_gen_div_i64(ret, t0, t1); 1113 } else { 1114 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1115 tcg_gen_movi_i64(t3, 0); 1116 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1117 tcg_gen_divu_i64(ret, t0, t1); 1118 } 1119 if (compute_ov) { 1120 tcg_gen_mov_tl(cpu_ov, t2); 1121 if (is_isa300(ctx)) { 1122 tcg_gen_mov_tl(cpu_ov32, t2); 1123 } 1124 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1125 } 1126 tcg_temp_free_i64(t0); 1127 tcg_temp_free_i64(t1); 1128 tcg_temp_free_i64(t2); 1129 tcg_temp_free_i64(t3); 1130 1131 if (unlikely(Rc(ctx->opcode) != 0)) 1132 gen_set_Rc0(ctx, ret); 1133 } 1134 1135 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1136 static void glue(gen_, name)(DisasContext *ctx) \ 1137 { \ 1138 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1139 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1140 sign, compute_ov); \ 1141 } 1142 /* divdu divdu. divduo divduo. */ 1143 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1144 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1145 /* divd divd. divdo divdo. */ 1146 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1147 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1148 1149 GEN_DIVE(divdeu, divdeu, 0); 1150 GEN_DIVE(divdeuo, divdeu, 1); 1151 GEN_DIVE(divde, divde, 0); 1152 GEN_DIVE(divdeo, divde, 1); 1153 #endif 1154 1155 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1156 TCGv arg2, int sign) 1157 { 1158 TCGv_i32 t0 = tcg_temp_new_i32(); 1159 TCGv_i32 t1 = tcg_temp_new_i32(); 1160 1161 tcg_gen_trunc_tl_i32(t0, arg1); 1162 tcg_gen_trunc_tl_i32(t1, arg2); 1163 if (sign) { 1164 TCGv_i32 t2 = tcg_temp_new_i32(); 1165 TCGv_i32 t3 = tcg_temp_new_i32(); 1166 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1167 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1168 tcg_gen_and_i32(t2, t2, t3); 1169 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1170 tcg_gen_or_i32(t2, t2, t3); 1171 tcg_gen_movi_i32(t3, 0); 1172 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1173 tcg_gen_rem_i32(t3, t0, t1); 1174 tcg_gen_ext_i32_tl(ret, t3); 1175 tcg_temp_free_i32(t2); 1176 tcg_temp_free_i32(t3); 1177 } else { 1178 TCGv_i32 t2 = tcg_const_i32(1); 1179 TCGv_i32 t3 = tcg_const_i32(0); 1180 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1181 tcg_gen_remu_i32(t3, t0, t1); 1182 tcg_gen_extu_i32_tl(ret, t3); 1183 tcg_temp_free_i32(t2); 1184 tcg_temp_free_i32(t3); 1185 } 1186 tcg_temp_free_i32(t0); 1187 tcg_temp_free_i32(t1); 1188 } 1189 1190 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1191 static void glue(gen_, name)(DisasContext *ctx) \ 1192 { \ 1193 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1194 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1195 sign); \ 1196 } 1197 1198 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1199 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1200 1201 #if defined(TARGET_PPC64) 1202 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1203 TCGv arg2, int sign) 1204 { 1205 TCGv_i64 t0 = tcg_temp_new_i64(); 1206 TCGv_i64 t1 = tcg_temp_new_i64(); 1207 1208 tcg_gen_mov_i64(t0, arg1); 1209 tcg_gen_mov_i64(t1, arg2); 1210 if (sign) { 1211 TCGv_i64 t2 = tcg_temp_new_i64(); 1212 TCGv_i64 t3 = tcg_temp_new_i64(); 1213 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1214 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1215 tcg_gen_and_i64(t2, t2, t3); 1216 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1217 tcg_gen_or_i64(t2, t2, t3); 1218 tcg_gen_movi_i64(t3, 0); 1219 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1220 tcg_gen_rem_i64(ret, t0, t1); 1221 tcg_temp_free_i64(t2); 1222 tcg_temp_free_i64(t3); 1223 } else { 1224 TCGv_i64 t2 = tcg_const_i64(1); 1225 TCGv_i64 t3 = tcg_const_i64(0); 1226 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1227 tcg_gen_remu_i64(ret, t0, t1); 1228 tcg_temp_free_i64(t2); 1229 tcg_temp_free_i64(t3); 1230 } 1231 tcg_temp_free_i64(t0); 1232 tcg_temp_free_i64(t1); 1233 } 1234 1235 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1236 static void glue(gen_, name)(DisasContext *ctx) \ 1237 { \ 1238 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1239 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1240 sign); \ 1241 } 1242 1243 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1244 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1245 #endif 1246 1247 /* mulhw mulhw. */ 1248 static void gen_mulhw(DisasContext *ctx) 1249 { 1250 TCGv_i32 t0 = tcg_temp_new_i32(); 1251 TCGv_i32 t1 = tcg_temp_new_i32(); 1252 1253 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1254 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1255 tcg_gen_muls2_i32(t0, t1, t0, t1); 1256 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1257 tcg_temp_free_i32(t0); 1258 tcg_temp_free_i32(t1); 1259 if (unlikely(Rc(ctx->opcode) != 0)) 1260 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1261 } 1262 1263 /* mulhwu mulhwu. */ 1264 static void gen_mulhwu(DisasContext *ctx) 1265 { 1266 TCGv_i32 t0 = tcg_temp_new_i32(); 1267 TCGv_i32 t1 = tcg_temp_new_i32(); 1268 1269 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1270 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1271 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1272 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1273 tcg_temp_free_i32(t0); 1274 tcg_temp_free_i32(t1); 1275 if (unlikely(Rc(ctx->opcode) != 0)) 1276 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1277 } 1278 1279 /* mullw mullw. */ 1280 static void gen_mullw(DisasContext *ctx) 1281 { 1282 #if defined(TARGET_PPC64) 1283 TCGv_i64 t0, t1; 1284 t0 = tcg_temp_new_i64(); 1285 t1 = tcg_temp_new_i64(); 1286 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1287 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1288 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1289 tcg_temp_free(t0); 1290 tcg_temp_free(t1); 1291 #else 1292 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1293 cpu_gpr[rB(ctx->opcode)]); 1294 #endif 1295 if (unlikely(Rc(ctx->opcode) != 0)) 1296 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1297 } 1298 1299 /* mullwo mullwo. */ 1300 static void gen_mullwo(DisasContext *ctx) 1301 { 1302 TCGv_i32 t0 = tcg_temp_new_i32(); 1303 TCGv_i32 t1 = tcg_temp_new_i32(); 1304 1305 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1306 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1307 tcg_gen_muls2_i32(t0, t1, t0, t1); 1308 #if defined(TARGET_PPC64) 1309 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1310 #else 1311 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1312 #endif 1313 1314 tcg_gen_sari_i32(t0, t0, 31); 1315 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1316 tcg_gen_extu_i32_tl(cpu_ov, t0); 1317 if (is_isa300(ctx)) { 1318 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1319 } 1320 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1321 1322 tcg_temp_free_i32(t0); 1323 tcg_temp_free_i32(t1); 1324 if (unlikely(Rc(ctx->opcode) != 0)) 1325 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1326 } 1327 1328 /* mulli */ 1329 static void gen_mulli(DisasContext *ctx) 1330 { 1331 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1332 SIMM(ctx->opcode)); 1333 } 1334 1335 #if defined(TARGET_PPC64) 1336 /* mulhd mulhd. */ 1337 static void gen_mulhd(DisasContext *ctx) 1338 { 1339 TCGv lo = tcg_temp_new(); 1340 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1341 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1342 tcg_temp_free(lo); 1343 if (unlikely(Rc(ctx->opcode) != 0)) { 1344 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1345 } 1346 } 1347 1348 /* mulhdu mulhdu. */ 1349 static void gen_mulhdu(DisasContext *ctx) 1350 { 1351 TCGv lo = tcg_temp_new(); 1352 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1353 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1354 tcg_temp_free(lo); 1355 if (unlikely(Rc(ctx->opcode) != 0)) { 1356 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1357 } 1358 } 1359 1360 /* mulld mulld. */ 1361 static void gen_mulld(DisasContext *ctx) 1362 { 1363 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1364 cpu_gpr[rB(ctx->opcode)]); 1365 if (unlikely(Rc(ctx->opcode) != 0)) 1366 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1367 } 1368 1369 /* mulldo mulldo. */ 1370 static void gen_mulldo(DisasContext *ctx) 1371 { 1372 TCGv_i64 t0 = tcg_temp_new_i64(); 1373 TCGv_i64 t1 = tcg_temp_new_i64(); 1374 1375 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1376 cpu_gpr[rB(ctx->opcode)]); 1377 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1378 1379 tcg_gen_sari_i64(t0, t0, 63); 1380 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 1381 if (is_isa300(ctx)) { 1382 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1383 } 1384 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1385 1386 tcg_temp_free_i64(t0); 1387 tcg_temp_free_i64(t1); 1388 1389 if (unlikely(Rc(ctx->opcode) != 0)) { 1390 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1391 } 1392 } 1393 #endif 1394 1395 /* Common subf function */ 1396 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1397 TCGv arg2, bool add_ca, bool compute_ca, 1398 bool compute_ov, bool compute_rc0) 1399 { 1400 TCGv t0 = ret; 1401 1402 if (compute_ca || compute_ov) { 1403 t0 = tcg_temp_new(); 1404 } 1405 1406 if (compute_ca) { 1407 /* dest = ~arg1 + arg2 [+ ca]. */ 1408 if (NARROW_MODE(ctx)) { 1409 /* Caution: a non-obvious corner case of the spec is that we 1410 must produce the *entire* 64-bit addition, but produce the 1411 carry into bit 32. */ 1412 TCGv inv1 = tcg_temp_new(); 1413 TCGv t1 = tcg_temp_new(); 1414 tcg_gen_not_tl(inv1, arg1); 1415 if (add_ca) { 1416 tcg_gen_add_tl(t0, arg2, cpu_ca); 1417 } else { 1418 tcg_gen_addi_tl(t0, arg2, 1); 1419 } 1420 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1421 tcg_gen_add_tl(t0, t0, inv1); 1422 tcg_temp_free(inv1); 1423 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1424 tcg_temp_free(t1); 1425 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 1426 if (is_isa300(ctx)) { 1427 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 1428 } 1429 } else if (add_ca) { 1430 TCGv zero, inv1 = tcg_temp_new(); 1431 tcg_gen_not_tl(inv1, arg1); 1432 zero = tcg_const_tl(0); 1433 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1434 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 1435 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0); 1436 tcg_temp_free(zero); 1437 tcg_temp_free(inv1); 1438 } else { 1439 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1440 tcg_gen_sub_tl(t0, arg2, arg1); 1441 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1); 1442 } 1443 } else if (add_ca) { 1444 /* Since we're ignoring carry-out, we can simplify the 1445 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ 1446 tcg_gen_sub_tl(t0, arg2, arg1); 1447 tcg_gen_add_tl(t0, t0, cpu_ca); 1448 tcg_gen_subi_tl(t0, t0, 1); 1449 } else { 1450 tcg_gen_sub_tl(t0, arg2, arg1); 1451 } 1452 1453 if (compute_ov) { 1454 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1455 } 1456 if (unlikely(compute_rc0)) { 1457 gen_set_Rc0(ctx, t0); 1458 } 1459 1460 if (t0 != ret) { 1461 tcg_gen_mov_tl(ret, t0); 1462 tcg_temp_free(t0); 1463 } 1464 } 1465 /* Sub functions with Two operands functions */ 1466 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1467 static void glue(gen_, name)(DisasContext *ctx) \ 1468 { \ 1469 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1470 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1471 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1472 } 1473 /* Sub functions with one operand and one immediate */ 1474 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1475 add_ca, compute_ca, compute_ov) \ 1476 static void glue(gen_, name)(DisasContext *ctx) \ 1477 { \ 1478 TCGv t0 = tcg_const_tl(const_val); \ 1479 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1480 cpu_gpr[rA(ctx->opcode)], t0, \ 1481 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1482 tcg_temp_free(t0); \ 1483 } 1484 /* subf subf. subfo subfo. */ 1485 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1486 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1487 /* subfc subfc. subfco subfco. */ 1488 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1489 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1490 /* subfe subfe. subfeo subfo. */ 1491 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1492 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1493 /* subfme subfme. subfmeo subfmeo. */ 1494 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1495 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1496 /* subfze subfze. subfzeo subfzeo.*/ 1497 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1498 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1499 1500 /* subfic */ 1501 static void gen_subfic(DisasContext *ctx) 1502 { 1503 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1504 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1505 c, 0, 1, 0, 0); 1506 tcg_temp_free(c); 1507 } 1508 1509 /* neg neg. nego nego. */ 1510 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1511 { 1512 TCGv zero = tcg_const_tl(0); 1513 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1514 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1515 tcg_temp_free(zero); 1516 } 1517 1518 static void gen_neg(DisasContext *ctx) 1519 { 1520 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 1521 if (unlikely(Rc(ctx->opcode))) { 1522 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1523 } 1524 } 1525 1526 static void gen_nego(DisasContext *ctx) 1527 { 1528 gen_op_arith_neg(ctx, 1); 1529 } 1530 1531 /*** Integer logical ***/ 1532 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1533 static void glue(gen_, name)(DisasContext *ctx) \ 1534 { \ 1535 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1536 cpu_gpr[rB(ctx->opcode)]); \ 1537 if (unlikely(Rc(ctx->opcode) != 0)) \ 1538 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1539 } 1540 1541 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1542 static void glue(gen_, name)(DisasContext *ctx) \ 1543 { \ 1544 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1545 if (unlikely(Rc(ctx->opcode) != 0)) \ 1546 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1547 } 1548 1549 /* and & and. */ 1550 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1551 /* andc & andc. */ 1552 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1553 1554 /* andi. */ 1555 static void gen_andi_(DisasContext *ctx) 1556 { 1557 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); 1558 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1559 } 1560 1561 /* andis. */ 1562 static void gen_andis_(DisasContext *ctx) 1563 { 1564 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); 1565 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1566 } 1567 1568 /* cntlzw */ 1569 static void gen_cntlzw(DisasContext *ctx) 1570 { 1571 TCGv_i32 t = tcg_temp_new_i32(); 1572 1573 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1574 tcg_gen_clzi_i32(t, t, 32); 1575 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1576 tcg_temp_free_i32(t); 1577 1578 if (unlikely(Rc(ctx->opcode) != 0)) 1579 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1580 } 1581 1582 /* cnttzw */ 1583 static void gen_cnttzw(DisasContext *ctx) 1584 { 1585 TCGv_i32 t = tcg_temp_new_i32(); 1586 1587 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1588 tcg_gen_ctzi_i32(t, t, 32); 1589 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1590 tcg_temp_free_i32(t); 1591 1592 if (unlikely(Rc(ctx->opcode) != 0)) { 1593 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1594 } 1595 } 1596 1597 /* eqv & eqv. */ 1598 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1599 /* extsb & extsb. */ 1600 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1601 /* extsh & extsh. */ 1602 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1603 /* nand & nand. */ 1604 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1605 /* nor & nor. */ 1606 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1607 1608 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1609 static void gen_pause(DisasContext *ctx) 1610 { 1611 TCGv_i32 t0 = tcg_const_i32(0); 1612 tcg_gen_st_i32(t0, cpu_env, 1613 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1614 tcg_temp_free_i32(t0); 1615 1616 /* Stop translation, this gives other CPUs a chance to run */ 1617 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1618 } 1619 #endif /* defined(TARGET_PPC64) */ 1620 1621 /* or & or. */ 1622 static void gen_or(DisasContext *ctx) 1623 { 1624 int rs, ra, rb; 1625 1626 rs = rS(ctx->opcode); 1627 ra = rA(ctx->opcode); 1628 rb = rB(ctx->opcode); 1629 /* Optimisation for mr. ri case */ 1630 if (rs != ra || rs != rb) { 1631 if (rs != rb) 1632 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1633 else 1634 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1635 if (unlikely(Rc(ctx->opcode) != 0)) 1636 gen_set_Rc0(ctx, cpu_gpr[ra]); 1637 } else if (unlikely(Rc(ctx->opcode) != 0)) { 1638 gen_set_Rc0(ctx, cpu_gpr[rs]); 1639 #if defined(TARGET_PPC64) 1640 } else if (rs != 0) { /* 0 is nop */ 1641 int prio = 0; 1642 1643 switch (rs) { 1644 case 1: 1645 /* Set process priority to low */ 1646 prio = 2; 1647 break; 1648 case 6: 1649 /* Set process priority to medium-low */ 1650 prio = 3; 1651 break; 1652 case 2: 1653 /* Set process priority to normal */ 1654 prio = 4; 1655 break; 1656 #if !defined(CONFIG_USER_ONLY) 1657 case 31: 1658 if (!ctx->pr) { 1659 /* Set process priority to very low */ 1660 prio = 1; 1661 } 1662 break; 1663 case 5: 1664 if (!ctx->pr) { 1665 /* Set process priority to medium-hight */ 1666 prio = 5; 1667 } 1668 break; 1669 case 3: 1670 if (!ctx->pr) { 1671 /* Set process priority to high */ 1672 prio = 6; 1673 } 1674 break; 1675 case 7: 1676 if (ctx->hv && !ctx->pr) { 1677 /* Set process priority to very high */ 1678 prio = 7; 1679 } 1680 break; 1681 #endif 1682 default: 1683 break; 1684 } 1685 if (prio) { 1686 TCGv t0 = tcg_temp_new(); 1687 gen_load_spr(t0, SPR_PPR); 1688 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1689 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1690 gen_store_spr(SPR_PPR, t0); 1691 tcg_temp_free(t0); 1692 } 1693 #if !defined(CONFIG_USER_ONLY) 1694 /* Pause out of TCG otherwise spin loops with smt_low eat too much 1695 * CPU and the kernel hangs. This applies to all encodings other 1696 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), 1697 * and all currently undefined. 1698 */ 1699 gen_pause(ctx); 1700 #endif 1701 #endif 1702 } 1703 } 1704 /* orc & orc. */ 1705 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1706 1707 /* xor & xor. */ 1708 static void gen_xor(DisasContext *ctx) 1709 { 1710 /* Optimisation for "set to zero" case */ 1711 if (rS(ctx->opcode) != rB(ctx->opcode)) 1712 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1713 else 1714 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1715 if (unlikely(Rc(ctx->opcode) != 0)) 1716 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1717 } 1718 1719 /* ori */ 1720 static void gen_ori(DisasContext *ctx) 1721 { 1722 target_ulong uimm = UIMM(ctx->opcode); 1723 1724 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1725 return; 1726 } 1727 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1728 } 1729 1730 /* oris */ 1731 static void gen_oris(DisasContext *ctx) 1732 { 1733 target_ulong uimm = UIMM(ctx->opcode); 1734 1735 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1736 /* NOP */ 1737 return; 1738 } 1739 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1740 } 1741 1742 /* xori */ 1743 static void gen_xori(DisasContext *ctx) 1744 { 1745 target_ulong uimm = UIMM(ctx->opcode); 1746 1747 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1748 /* NOP */ 1749 return; 1750 } 1751 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1752 } 1753 1754 /* xoris */ 1755 static void gen_xoris(DisasContext *ctx) 1756 { 1757 target_ulong uimm = UIMM(ctx->opcode); 1758 1759 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1760 /* NOP */ 1761 return; 1762 } 1763 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1764 } 1765 1766 /* popcntb : PowerPC 2.03 specification */ 1767 static void gen_popcntb(DisasContext *ctx) 1768 { 1769 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1770 } 1771 1772 static void gen_popcntw(DisasContext *ctx) 1773 { 1774 #if defined(TARGET_PPC64) 1775 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1776 #else 1777 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1778 #endif 1779 } 1780 1781 #if defined(TARGET_PPC64) 1782 /* popcntd: PowerPC 2.06 specification */ 1783 static void gen_popcntd(DisasContext *ctx) 1784 { 1785 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1786 } 1787 #endif 1788 1789 /* prtyw: PowerPC 2.05 specification */ 1790 static void gen_prtyw(DisasContext *ctx) 1791 { 1792 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1793 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1794 TCGv t0 = tcg_temp_new(); 1795 tcg_gen_shri_tl(t0, rs, 16); 1796 tcg_gen_xor_tl(ra, rs, t0); 1797 tcg_gen_shri_tl(t0, ra, 8); 1798 tcg_gen_xor_tl(ra, ra, t0); 1799 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1800 tcg_temp_free(t0); 1801 } 1802 1803 #if defined(TARGET_PPC64) 1804 /* prtyd: PowerPC 2.05 specification */ 1805 static void gen_prtyd(DisasContext *ctx) 1806 { 1807 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1808 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1809 TCGv t0 = tcg_temp_new(); 1810 tcg_gen_shri_tl(t0, rs, 32); 1811 tcg_gen_xor_tl(ra, rs, t0); 1812 tcg_gen_shri_tl(t0, ra, 16); 1813 tcg_gen_xor_tl(ra, ra, t0); 1814 tcg_gen_shri_tl(t0, ra, 8); 1815 tcg_gen_xor_tl(ra, ra, t0); 1816 tcg_gen_andi_tl(ra, ra, 1); 1817 tcg_temp_free(t0); 1818 } 1819 #endif 1820 1821 #if defined(TARGET_PPC64) 1822 /* bpermd */ 1823 static void gen_bpermd(DisasContext *ctx) 1824 { 1825 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1826 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1827 } 1828 #endif 1829 1830 #if defined(TARGET_PPC64) 1831 /* extsw & extsw. */ 1832 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1833 1834 /* cntlzd */ 1835 static void gen_cntlzd(DisasContext *ctx) 1836 { 1837 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1838 if (unlikely(Rc(ctx->opcode) != 0)) 1839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1840 } 1841 1842 /* cnttzd */ 1843 static void gen_cnttzd(DisasContext *ctx) 1844 { 1845 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1846 if (unlikely(Rc(ctx->opcode) != 0)) { 1847 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1848 } 1849 } 1850 1851 /* darn */ 1852 static void gen_darn(DisasContext *ctx) 1853 { 1854 int l = L(ctx->opcode); 1855 1856 if (l == 0) { 1857 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1858 } else if (l <= 2) { 1859 /* Return 64-bit random for both CRN and RRN */ 1860 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1861 } else { 1862 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1863 } 1864 } 1865 #endif 1866 1867 /*** Integer rotate ***/ 1868 1869 /* rlwimi & rlwimi. */ 1870 static void gen_rlwimi(DisasContext *ctx) 1871 { 1872 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1873 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1874 uint32_t sh = SH(ctx->opcode); 1875 uint32_t mb = MB(ctx->opcode); 1876 uint32_t me = ME(ctx->opcode); 1877 1878 if (sh == (31-me) && mb <= me) { 1879 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1880 } else { 1881 target_ulong mask; 1882 TCGv t1; 1883 1884 #if defined(TARGET_PPC64) 1885 mb += 32; 1886 me += 32; 1887 #endif 1888 mask = MASK(mb, me); 1889 1890 t1 = tcg_temp_new(); 1891 if (mask <= 0xffffffffu) { 1892 TCGv_i32 t0 = tcg_temp_new_i32(); 1893 tcg_gen_trunc_tl_i32(t0, t_rs); 1894 tcg_gen_rotli_i32(t0, t0, sh); 1895 tcg_gen_extu_i32_tl(t1, t0); 1896 tcg_temp_free_i32(t0); 1897 } else { 1898 #if defined(TARGET_PPC64) 1899 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1900 tcg_gen_rotli_i64(t1, t1, sh); 1901 #else 1902 g_assert_not_reached(); 1903 #endif 1904 } 1905 1906 tcg_gen_andi_tl(t1, t1, mask); 1907 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1908 tcg_gen_or_tl(t_ra, t_ra, t1); 1909 tcg_temp_free(t1); 1910 } 1911 if (unlikely(Rc(ctx->opcode) != 0)) { 1912 gen_set_Rc0(ctx, t_ra); 1913 } 1914 } 1915 1916 /* rlwinm & rlwinm. */ 1917 static void gen_rlwinm(DisasContext *ctx) 1918 { 1919 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1920 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1921 int sh = SH(ctx->opcode); 1922 int mb = MB(ctx->opcode); 1923 int me = ME(ctx->opcode); 1924 int len = me - mb + 1; 1925 int rsh = (32 - sh) & 31; 1926 1927 if (sh != 0 && len > 0 && me == (31 - sh)) { 1928 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 1929 } else if (me == 31 && rsh + len <= 32) { 1930 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1931 } else { 1932 target_ulong mask; 1933 #if defined(TARGET_PPC64) 1934 mb += 32; 1935 me += 32; 1936 #endif 1937 mask = MASK(mb, me); 1938 if (sh == 0) { 1939 tcg_gen_andi_tl(t_ra, t_rs, mask); 1940 } else if (mask <= 0xffffffffu) { 1941 TCGv_i32 t0 = tcg_temp_new_i32(); 1942 tcg_gen_trunc_tl_i32(t0, t_rs); 1943 tcg_gen_rotli_i32(t0, t0, sh); 1944 tcg_gen_andi_i32(t0, t0, mask); 1945 tcg_gen_extu_i32_tl(t_ra, t0); 1946 tcg_temp_free_i32(t0); 1947 } else { 1948 #if defined(TARGET_PPC64) 1949 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1950 tcg_gen_rotli_i64(t_ra, t_ra, sh); 1951 tcg_gen_andi_i64(t_ra, t_ra, mask); 1952 #else 1953 g_assert_not_reached(); 1954 #endif 1955 } 1956 } 1957 if (unlikely(Rc(ctx->opcode) != 0)) { 1958 gen_set_Rc0(ctx, t_ra); 1959 } 1960 } 1961 1962 /* rlwnm & rlwnm. */ 1963 static void gen_rlwnm(DisasContext *ctx) 1964 { 1965 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1966 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1967 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1968 uint32_t mb = MB(ctx->opcode); 1969 uint32_t me = ME(ctx->opcode); 1970 target_ulong mask; 1971 1972 #if defined(TARGET_PPC64) 1973 mb += 32; 1974 me += 32; 1975 #endif 1976 mask = MASK(mb, me); 1977 1978 if (mask <= 0xffffffffu) { 1979 TCGv_i32 t0 = tcg_temp_new_i32(); 1980 TCGv_i32 t1 = tcg_temp_new_i32(); 1981 tcg_gen_trunc_tl_i32(t0, t_rb); 1982 tcg_gen_trunc_tl_i32(t1, t_rs); 1983 tcg_gen_andi_i32(t0, t0, 0x1f); 1984 tcg_gen_rotl_i32(t1, t1, t0); 1985 tcg_gen_extu_i32_tl(t_ra, t1); 1986 tcg_temp_free_i32(t0); 1987 tcg_temp_free_i32(t1); 1988 } else { 1989 #if defined(TARGET_PPC64) 1990 TCGv_i64 t0 = tcg_temp_new_i64(); 1991 tcg_gen_andi_i64(t0, t_rb, 0x1f); 1992 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1993 tcg_gen_rotl_i64(t_ra, t_ra, t0); 1994 tcg_temp_free_i64(t0); 1995 #else 1996 g_assert_not_reached(); 1997 #endif 1998 } 1999 2000 tcg_gen_andi_tl(t_ra, t_ra, mask); 2001 2002 if (unlikely(Rc(ctx->opcode) != 0)) { 2003 gen_set_Rc0(ctx, t_ra); 2004 } 2005 } 2006 2007 #if defined(TARGET_PPC64) 2008 #define GEN_PPC64_R2(name, opc1, opc2) \ 2009 static void glue(gen_, name##0)(DisasContext *ctx) \ 2010 { \ 2011 gen_##name(ctx, 0); \ 2012 } \ 2013 \ 2014 static void glue(gen_, name##1)(DisasContext *ctx) \ 2015 { \ 2016 gen_##name(ctx, 1); \ 2017 } 2018 #define GEN_PPC64_R4(name, opc1, opc2) \ 2019 static void glue(gen_, name##0)(DisasContext *ctx) \ 2020 { \ 2021 gen_##name(ctx, 0, 0); \ 2022 } \ 2023 \ 2024 static void glue(gen_, name##1)(DisasContext *ctx) \ 2025 { \ 2026 gen_##name(ctx, 0, 1); \ 2027 } \ 2028 \ 2029 static void glue(gen_, name##2)(DisasContext *ctx) \ 2030 { \ 2031 gen_##name(ctx, 1, 0); \ 2032 } \ 2033 \ 2034 static void glue(gen_, name##3)(DisasContext *ctx) \ 2035 { \ 2036 gen_##name(ctx, 1, 1); \ 2037 } 2038 2039 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2040 { 2041 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2042 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2043 int len = me - mb + 1; 2044 int rsh = (64 - sh) & 63; 2045 2046 if (sh != 0 && len > 0 && me == (63 - sh)) { 2047 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2048 } else if (me == 63 && rsh + len <= 64) { 2049 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2050 } else { 2051 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2052 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2053 } 2054 if (unlikely(Rc(ctx->opcode) != 0)) { 2055 gen_set_Rc0(ctx, t_ra); 2056 } 2057 } 2058 2059 /* rldicl - rldicl. */ 2060 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2061 { 2062 uint32_t sh, mb; 2063 2064 sh = SH(ctx->opcode) | (shn << 5); 2065 mb = MB(ctx->opcode) | (mbn << 5); 2066 gen_rldinm(ctx, mb, 63, sh); 2067 } 2068 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2069 2070 /* rldicr - rldicr. */ 2071 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2072 { 2073 uint32_t sh, me; 2074 2075 sh = SH(ctx->opcode) | (shn << 5); 2076 me = MB(ctx->opcode) | (men << 5); 2077 gen_rldinm(ctx, 0, me, sh); 2078 } 2079 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2080 2081 /* rldic - rldic. */ 2082 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2083 { 2084 uint32_t sh, mb; 2085 2086 sh = SH(ctx->opcode) | (shn << 5); 2087 mb = MB(ctx->opcode) | (mbn << 5); 2088 gen_rldinm(ctx, mb, 63 - sh, sh); 2089 } 2090 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2091 2092 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2093 { 2094 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2095 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2096 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2097 TCGv t0; 2098 2099 t0 = tcg_temp_new(); 2100 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2101 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2102 tcg_temp_free(t0); 2103 2104 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2105 if (unlikely(Rc(ctx->opcode) != 0)) { 2106 gen_set_Rc0(ctx, t_ra); 2107 } 2108 } 2109 2110 /* rldcl - rldcl. */ 2111 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2112 { 2113 uint32_t mb; 2114 2115 mb = MB(ctx->opcode) | (mbn << 5); 2116 gen_rldnm(ctx, mb, 63); 2117 } 2118 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2119 2120 /* rldcr - rldcr. */ 2121 static inline void gen_rldcr(DisasContext *ctx, int men) 2122 { 2123 uint32_t me; 2124 2125 me = MB(ctx->opcode) | (men << 5); 2126 gen_rldnm(ctx, 0, me); 2127 } 2128 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2129 2130 /* rldimi - rldimi. */ 2131 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2132 { 2133 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2134 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2135 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2136 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2137 uint32_t me = 63 - sh; 2138 2139 if (mb <= me) { 2140 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2141 } else { 2142 target_ulong mask = MASK(mb, me); 2143 TCGv t1 = tcg_temp_new(); 2144 2145 tcg_gen_rotli_tl(t1, t_rs, sh); 2146 tcg_gen_andi_tl(t1, t1, mask); 2147 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2148 tcg_gen_or_tl(t_ra, t_ra, t1); 2149 tcg_temp_free(t1); 2150 } 2151 if (unlikely(Rc(ctx->opcode) != 0)) { 2152 gen_set_Rc0(ctx, t_ra); 2153 } 2154 } 2155 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2156 #endif 2157 2158 /*** Integer shift ***/ 2159 2160 /* slw & slw. */ 2161 static void gen_slw(DisasContext *ctx) 2162 { 2163 TCGv t0, t1; 2164 2165 t0 = tcg_temp_new(); 2166 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2167 #if defined(TARGET_PPC64) 2168 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2169 tcg_gen_sari_tl(t0, t0, 0x3f); 2170 #else 2171 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2172 tcg_gen_sari_tl(t0, t0, 0x1f); 2173 #endif 2174 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2175 t1 = tcg_temp_new(); 2176 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2177 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2178 tcg_temp_free(t1); 2179 tcg_temp_free(t0); 2180 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2181 if (unlikely(Rc(ctx->opcode) != 0)) 2182 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2183 } 2184 2185 /* sraw & sraw. */ 2186 static void gen_sraw(DisasContext *ctx) 2187 { 2188 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2189 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2190 if (unlikely(Rc(ctx->opcode) != 0)) 2191 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2192 } 2193 2194 /* srawi & srawi. */ 2195 static void gen_srawi(DisasContext *ctx) 2196 { 2197 int sh = SH(ctx->opcode); 2198 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2199 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2200 if (sh == 0) { 2201 tcg_gen_ext32s_tl(dst, src); 2202 tcg_gen_movi_tl(cpu_ca, 0); 2203 if (is_isa300(ctx)) { 2204 tcg_gen_movi_tl(cpu_ca32, 0); 2205 } 2206 } else { 2207 TCGv t0; 2208 tcg_gen_ext32s_tl(dst, src); 2209 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2210 t0 = tcg_temp_new(); 2211 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2212 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2213 tcg_temp_free(t0); 2214 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2215 if (is_isa300(ctx)) { 2216 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2217 } 2218 tcg_gen_sari_tl(dst, dst, sh); 2219 } 2220 if (unlikely(Rc(ctx->opcode) != 0)) { 2221 gen_set_Rc0(ctx, dst); 2222 } 2223 } 2224 2225 /* srw & srw. */ 2226 static void gen_srw(DisasContext *ctx) 2227 { 2228 TCGv t0, t1; 2229 2230 t0 = tcg_temp_new(); 2231 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2232 #if defined(TARGET_PPC64) 2233 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2234 tcg_gen_sari_tl(t0, t0, 0x3f); 2235 #else 2236 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2237 tcg_gen_sari_tl(t0, t0, 0x1f); 2238 #endif 2239 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2240 tcg_gen_ext32u_tl(t0, t0); 2241 t1 = tcg_temp_new(); 2242 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2243 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2244 tcg_temp_free(t1); 2245 tcg_temp_free(t0); 2246 if (unlikely(Rc(ctx->opcode) != 0)) 2247 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2248 } 2249 2250 #if defined(TARGET_PPC64) 2251 /* sld & sld. */ 2252 static void gen_sld(DisasContext *ctx) 2253 { 2254 TCGv t0, t1; 2255 2256 t0 = tcg_temp_new(); 2257 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2258 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2259 tcg_gen_sari_tl(t0, t0, 0x3f); 2260 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2261 t1 = tcg_temp_new(); 2262 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2263 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2264 tcg_temp_free(t1); 2265 tcg_temp_free(t0); 2266 if (unlikely(Rc(ctx->opcode) != 0)) 2267 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2268 } 2269 2270 /* srad & srad. */ 2271 static void gen_srad(DisasContext *ctx) 2272 { 2273 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2274 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2275 if (unlikely(Rc(ctx->opcode) != 0)) 2276 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2277 } 2278 /* sradi & sradi. */ 2279 static inline void gen_sradi(DisasContext *ctx, int n) 2280 { 2281 int sh = SH(ctx->opcode) + (n << 5); 2282 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2283 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2284 if (sh == 0) { 2285 tcg_gen_mov_tl(dst, src); 2286 tcg_gen_movi_tl(cpu_ca, 0); 2287 if (is_isa300(ctx)) { 2288 tcg_gen_movi_tl(cpu_ca32, 0); 2289 } 2290 } else { 2291 TCGv t0; 2292 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2293 t0 = tcg_temp_new(); 2294 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2295 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2296 tcg_temp_free(t0); 2297 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2298 if (is_isa300(ctx)) { 2299 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2300 } 2301 tcg_gen_sari_tl(dst, src, sh); 2302 } 2303 if (unlikely(Rc(ctx->opcode) != 0)) { 2304 gen_set_Rc0(ctx, dst); 2305 } 2306 } 2307 2308 static void gen_sradi0(DisasContext *ctx) 2309 { 2310 gen_sradi(ctx, 0); 2311 } 2312 2313 static void gen_sradi1(DisasContext *ctx) 2314 { 2315 gen_sradi(ctx, 1); 2316 } 2317 2318 /* extswsli & extswsli. */ 2319 static inline void gen_extswsli(DisasContext *ctx, int n) 2320 { 2321 int sh = SH(ctx->opcode) + (n << 5); 2322 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2323 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2324 2325 tcg_gen_ext32s_tl(dst, src); 2326 tcg_gen_shli_tl(dst, dst, sh); 2327 if (unlikely(Rc(ctx->opcode) != 0)) { 2328 gen_set_Rc0(ctx, dst); 2329 } 2330 } 2331 2332 static void gen_extswsli0(DisasContext *ctx) 2333 { 2334 gen_extswsli(ctx, 0); 2335 } 2336 2337 static void gen_extswsli1(DisasContext *ctx) 2338 { 2339 gen_extswsli(ctx, 1); 2340 } 2341 2342 /* srd & srd. */ 2343 static void gen_srd(DisasContext *ctx) 2344 { 2345 TCGv t0, t1; 2346 2347 t0 = tcg_temp_new(); 2348 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2349 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2350 tcg_gen_sari_tl(t0, t0, 0x3f); 2351 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2352 t1 = tcg_temp_new(); 2353 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2354 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2355 tcg_temp_free(t1); 2356 tcg_temp_free(t0); 2357 if (unlikely(Rc(ctx->opcode) != 0)) 2358 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2359 } 2360 #endif 2361 2362 /*** Addressing modes ***/ 2363 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2364 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2365 target_long maskl) 2366 { 2367 target_long simm = SIMM(ctx->opcode); 2368 2369 simm &= ~maskl; 2370 if (rA(ctx->opcode) == 0) { 2371 if (NARROW_MODE(ctx)) { 2372 simm = (uint32_t)simm; 2373 } 2374 tcg_gen_movi_tl(EA, simm); 2375 } else if (likely(simm != 0)) { 2376 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2377 if (NARROW_MODE(ctx)) { 2378 tcg_gen_ext32u_tl(EA, EA); 2379 } 2380 } else { 2381 if (NARROW_MODE(ctx)) { 2382 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2383 } else { 2384 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2385 } 2386 } 2387 } 2388 2389 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2390 { 2391 if (rA(ctx->opcode) == 0) { 2392 if (NARROW_MODE(ctx)) { 2393 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2394 } else { 2395 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2396 } 2397 } else { 2398 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2399 if (NARROW_MODE(ctx)) { 2400 tcg_gen_ext32u_tl(EA, EA); 2401 } 2402 } 2403 } 2404 2405 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2406 { 2407 if (rA(ctx->opcode) == 0) { 2408 tcg_gen_movi_tl(EA, 0); 2409 } else if (NARROW_MODE(ctx)) { 2410 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2411 } else { 2412 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2413 } 2414 } 2415 2416 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2417 target_long val) 2418 { 2419 tcg_gen_addi_tl(ret, arg1, val); 2420 if (NARROW_MODE(ctx)) { 2421 tcg_gen_ext32u_tl(ret, ret); 2422 } 2423 } 2424 2425 static inline void gen_align_no_le(DisasContext *ctx) 2426 { 2427 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2428 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2429 } 2430 2431 /*** Integer load ***/ 2432 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2433 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2434 2435 #define GEN_QEMU_LOAD_TL(ldop, op) \ 2436 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2437 TCGv val, \ 2438 TCGv addr) \ 2439 { \ 2440 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2441 } 2442 2443 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2444 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2445 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2446 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2447 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2448 2449 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2450 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2451 2452 #define GEN_QEMU_LOAD_64(ldop, op) \ 2453 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2454 TCGv_i64 val, \ 2455 TCGv addr) \ 2456 { \ 2457 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2458 } 2459 2460 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2461 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2462 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2463 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2464 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2465 2466 #if defined(TARGET_PPC64) 2467 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2468 #endif 2469 2470 #define GEN_QEMU_STORE_TL(stop, op) \ 2471 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2472 TCGv val, \ 2473 TCGv addr) \ 2474 { \ 2475 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2476 } 2477 2478 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2479 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2480 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2481 2482 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2483 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2484 2485 #define GEN_QEMU_STORE_64(stop, op) \ 2486 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2487 TCGv_i64 val, \ 2488 TCGv addr) \ 2489 { \ 2490 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2491 } 2492 2493 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2494 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2495 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2496 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2497 2498 #if defined(TARGET_PPC64) 2499 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2500 #endif 2501 2502 #define GEN_LD(name, ldop, opc, type) \ 2503 static void glue(gen_, name)(DisasContext *ctx) \ 2504 { \ 2505 TCGv EA; \ 2506 gen_set_access_type(ctx, ACCESS_INT); \ 2507 EA = tcg_temp_new(); \ 2508 gen_addr_imm_index(ctx, EA, 0); \ 2509 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2510 tcg_temp_free(EA); \ 2511 } 2512 2513 #define GEN_LDU(name, ldop, opc, type) \ 2514 static void glue(gen_, name##u)(DisasContext *ctx) \ 2515 { \ 2516 TCGv EA; \ 2517 if (unlikely(rA(ctx->opcode) == 0 || \ 2518 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2519 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2520 return; \ 2521 } \ 2522 gen_set_access_type(ctx, ACCESS_INT); \ 2523 EA = tcg_temp_new(); \ 2524 if (type == PPC_64B) \ 2525 gen_addr_imm_index(ctx, EA, 0x03); \ 2526 else \ 2527 gen_addr_imm_index(ctx, EA, 0); \ 2528 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2529 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2530 tcg_temp_free(EA); \ 2531 } 2532 2533 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2534 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2535 { \ 2536 TCGv EA; \ 2537 if (unlikely(rA(ctx->opcode) == 0 || \ 2538 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2539 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2540 return; \ 2541 } \ 2542 gen_set_access_type(ctx, ACCESS_INT); \ 2543 EA = tcg_temp_new(); \ 2544 gen_addr_reg_index(ctx, EA); \ 2545 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2546 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2547 tcg_temp_free(EA); \ 2548 } 2549 2550 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2551 static void glue(gen_, name##x)(DisasContext *ctx) \ 2552 { \ 2553 TCGv EA; \ 2554 chk; \ 2555 gen_set_access_type(ctx, ACCESS_INT); \ 2556 EA = tcg_temp_new(); \ 2557 gen_addr_reg_index(ctx, EA); \ 2558 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2559 tcg_temp_free(EA); \ 2560 } 2561 2562 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2563 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2564 2565 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2566 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2567 2568 #define GEN_LDS(name, ldop, op, type) \ 2569 GEN_LD(name, ldop, op | 0x20, type); \ 2570 GEN_LDU(name, ldop, op | 0x21, type); \ 2571 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2572 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2573 2574 /* lbz lbzu lbzux lbzx */ 2575 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2576 /* lha lhau lhaux lhax */ 2577 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2578 /* lhz lhzu lhzux lhzx */ 2579 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2580 /* lwz lwzu lwzux lwzx */ 2581 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2582 #if defined(TARGET_PPC64) 2583 /* lwaux */ 2584 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2585 /* lwax */ 2586 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2587 /* ldux */ 2588 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2589 /* ldx */ 2590 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2591 2592 /* CI load/store variants */ 2593 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2594 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2595 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2596 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2597 2598 static void gen_ld(DisasContext *ctx) 2599 { 2600 TCGv EA; 2601 if (Rc(ctx->opcode)) { 2602 if (unlikely(rA(ctx->opcode) == 0 || 2603 rA(ctx->opcode) == rD(ctx->opcode))) { 2604 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2605 return; 2606 } 2607 } 2608 gen_set_access_type(ctx, ACCESS_INT); 2609 EA = tcg_temp_new(); 2610 gen_addr_imm_index(ctx, EA, 0x03); 2611 if (ctx->opcode & 0x02) { 2612 /* lwa (lwau is undefined) */ 2613 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2614 } else { 2615 /* ld - ldu */ 2616 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2617 } 2618 if (Rc(ctx->opcode)) 2619 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2620 tcg_temp_free(EA); 2621 } 2622 2623 /* lq */ 2624 static void gen_lq(DisasContext *ctx) 2625 { 2626 int ra, rd; 2627 TCGv EA, hi, lo; 2628 2629 /* lq is a legal user mode instruction starting in ISA 2.07 */ 2630 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2631 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2632 2633 if (!legal_in_user_mode && ctx->pr) { 2634 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2635 return; 2636 } 2637 2638 if (!le_is_supported && ctx->le_mode) { 2639 gen_align_no_le(ctx); 2640 return; 2641 } 2642 ra = rA(ctx->opcode); 2643 rd = rD(ctx->opcode); 2644 if (unlikely((rd & 1) || rd == ra)) { 2645 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2646 return; 2647 } 2648 2649 gen_set_access_type(ctx, ACCESS_INT); 2650 EA = tcg_temp_new(); 2651 gen_addr_imm_index(ctx, EA, 0x0F); 2652 2653 /* Note that the low part is always in RD+1, even in LE mode. */ 2654 lo = cpu_gpr[rd + 1]; 2655 hi = cpu_gpr[rd]; 2656 2657 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2658 if (HAVE_ATOMIC128) { 2659 TCGv_i32 oi = tcg_temp_new_i32(); 2660 if (ctx->le_mode) { 2661 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2662 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 2663 } else { 2664 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2665 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 2666 } 2667 tcg_temp_free_i32(oi); 2668 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 2669 } else { 2670 /* Restart with exclusive lock. */ 2671 gen_helper_exit_atomic(cpu_env); 2672 ctx->base.is_jmp = DISAS_NORETURN; 2673 } 2674 } else if (ctx->le_mode) { 2675 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2676 gen_addr_add(ctx, EA, EA, 8); 2677 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2678 } else { 2679 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2680 gen_addr_add(ctx, EA, EA, 8); 2681 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2682 } 2683 tcg_temp_free(EA); 2684 } 2685 #endif 2686 2687 /*** Integer store ***/ 2688 #define GEN_ST(name, stop, opc, type) \ 2689 static void glue(gen_, name)(DisasContext *ctx) \ 2690 { \ 2691 TCGv EA; \ 2692 gen_set_access_type(ctx, ACCESS_INT); \ 2693 EA = tcg_temp_new(); \ 2694 gen_addr_imm_index(ctx, EA, 0); \ 2695 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2696 tcg_temp_free(EA); \ 2697 } 2698 2699 #define GEN_STU(name, stop, opc, type) \ 2700 static void glue(gen_, stop##u)(DisasContext *ctx) \ 2701 { \ 2702 TCGv EA; \ 2703 if (unlikely(rA(ctx->opcode) == 0)) { \ 2704 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2705 return; \ 2706 } \ 2707 gen_set_access_type(ctx, ACCESS_INT); \ 2708 EA = tcg_temp_new(); \ 2709 if (type == PPC_64B) \ 2710 gen_addr_imm_index(ctx, EA, 0x03); \ 2711 else \ 2712 gen_addr_imm_index(ctx, EA, 0); \ 2713 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2714 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2715 tcg_temp_free(EA); \ 2716 } 2717 2718 #define GEN_STUX(name, stop, opc2, opc3, type) \ 2719 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2720 { \ 2721 TCGv EA; \ 2722 if (unlikely(rA(ctx->opcode) == 0)) { \ 2723 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2724 return; \ 2725 } \ 2726 gen_set_access_type(ctx, ACCESS_INT); \ 2727 EA = tcg_temp_new(); \ 2728 gen_addr_reg_index(ctx, EA); \ 2729 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2730 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2731 tcg_temp_free(EA); \ 2732 } 2733 2734 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2735 static void glue(gen_, name##x)(DisasContext *ctx) \ 2736 { \ 2737 TCGv EA; \ 2738 chk; \ 2739 gen_set_access_type(ctx, ACCESS_INT); \ 2740 EA = tcg_temp_new(); \ 2741 gen_addr_reg_index(ctx, EA); \ 2742 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2743 tcg_temp_free(EA); \ 2744 } 2745 #define GEN_STX(name, stop, opc2, opc3, type) \ 2746 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2747 2748 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2749 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2750 2751 #define GEN_STS(name, stop, op, type) \ 2752 GEN_ST(name, stop, op | 0x20, type); \ 2753 GEN_STU(name, stop, op | 0x21, type); \ 2754 GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2755 GEN_STX(name, stop, 0x17, op | 0x00, type) 2756 2757 /* stb stbu stbux stbx */ 2758 GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2759 /* sth sthu sthux sthx */ 2760 GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2761 /* stw stwu stwux stwx */ 2762 GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2763 #if defined(TARGET_PPC64) 2764 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2765 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2766 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2767 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2768 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2769 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2770 2771 static void gen_std(DisasContext *ctx) 2772 { 2773 int rs; 2774 TCGv EA; 2775 2776 rs = rS(ctx->opcode); 2777 if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2778 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2779 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2780 TCGv hi, lo; 2781 2782 if (!(ctx->insns_flags & PPC_64BX)) { 2783 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2784 } 2785 2786 if (!legal_in_user_mode && ctx->pr) { 2787 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2788 return; 2789 } 2790 2791 if (!le_is_supported && ctx->le_mode) { 2792 gen_align_no_le(ctx); 2793 return; 2794 } 2795 2796 if (unlikely(rs & 1)) { 2797 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2798 return; 2799 } 2800 gen_set_access_type(ctx, ACCESS_INT); 2801 EA = tcg_temp_new(); 2802 gen_addr_imm_index(ctx, EA, 0x03); 2803 2804 /* Note that the low part is always in RS+1, even in LE mode. */ 2805 lo = cpu_gpr[rs + 1]; 2806 hi = cpu_gpr[rs]; 2807 2808 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2809 if (HAVE_ATOMIC128) { 2810 TCGv_i32 oi = tcg_temp_new_i32(); 2811 if (ctx->le_mode) { 2812 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2813 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 2814 } else { 2815 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2816 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 2817 } 2818 tcg_temp_free_i32(oi); 2819 } else { 2820 /* Restart with exclusive lock. */ 2821 gen_helper_exit_atomic(cpu_env); 2822 ctx->base.is_jmp = DISAS_NORETURN; 2823 } 2824 } else if (ctx->le_mode) { 2825 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2826 gen_addr_add(ctx, EA, EA, 8); 2827 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2828 } else { 2829 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2830 gen_addr_add(ctx, EA, EA, 8); 2831 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2832 } 2833 tcg_temp_free(EA); 2834 } else { 2835 /* std / stdu */ 2836 if (Rc(ctx->opcode)) { 2837 if (unlikely(rA(ctx->opcode) == 0)) { 2838 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2839 return; 2840 } 2841 } 2842 gen_set_access_type(ctx, ACCESS_INT); 2843 EA = tcg_temp_new(); 2844 gen_addr_imm_index(ctx, EA, 0x03); 2845 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2846 if (Rc(ctx->opcode)) 2847 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2848 tcg_temp_free(EA); 2849 } 2850 } 2851 #endif 2852 /*** Integer load and store with byte reverse ***/ 2853 2854 /* lhbrx */ 2855 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2856 2857 /* lwbrx */ 2858 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2859 2860 #if defined(TARGET_PPC64) 2861 /* ldbrx */ 2862 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2863 /* stdbrx */ 2864 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2865 #endif /* TARGET_PPC64 */ 2866 2867 /* sthbrx */ 2868 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2869 /* stwbrx */ 2870 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2871 2872 /*** Integer load and store multiple ***/ 2873 2874 /* lmw */ 2875 static void gen_lmw(DisasContext *ctx) 2876 { 2877 TCGv t0; 2878 TCGv_i32 t1; 2879 2880 if (ctx->le_mode) { 2881 gen_align_no_le(ctx); 2882 return; 2883 } 2884 gen_set_access_type(ctx, ACCESS_INT); 2885 t0 = tcg_temp_new(); 2886 t1 = tcg_const_i32(rD(ctx->opcode)); 2887 gen_addr_imm_index(ctx, t0, 0); 2888 gen_helper_lmw(cpu_env, t0, t1); 2889 tcg_temp_free(t0); 2890 tcg_temp_free_i32(t1); 2891 } 2892 2893 /* stmw */ 2894 static void gen_stmw(DisasContext *ctx) 2895 { 2896 TCGv t0; 2897 TCGv_i32 t1; 2898 2899 if (ctx->le_mode) { 2900 gen_align_no_le(ctx); 2901 return; 2902 } 2903 gen_set_access_type(ctx, ACCESS_INT); 2904 t0 = tcg_temp_new(); 2905 t1 = tcg_const_i32(rS(ctx->opcode)); 2906 gen_addr_imm_index(ctx, t0, 0); 2907 gen_helper_stmw(cpu_env, t0, t1); 2908 tcg_temp_free(t0); 2909 tcg_temp_free_i32(t1); 2910 } 2911 2912 /*** Integer load and store strings ***/ 2913 2914 /* lswi */ 2915 /* PowerPC32 specification says we must generate an exception if 2916 * rA is in the range of registers to be loaded. 2917 * In an other hand, IBM says this is valid, but rA won't be loaded. 2918 * For now, I'll follow the spec... 2919 */ 2920 static void gen_lswi(DisasContext *ctx) 2921 { 2922 TCGv t0; 2923 TCGv_i32 t1, t2; 2924 int nb = NB(ctx->opcode); 2925 int start = rD(ctx->opcode); 2926 int ra = rA(ctx->opcode); 2927 int nr; 2928 2929 if (ctx->le_mode) { 2930 gen_align_no_le(ctx); 2931 return; 2932 } 2933 if (nb == 0) 2934 nb = 32; 2935 nr = DIV_ROUND_UP(nb, 4); 2936 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2937 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2938 return; 2939 } 2940 gen_set_access_type(ctx, ACCESS_INT); 2941 t0 = tcg_temp_new(); 2942 gen_addr_register(ctx, t0); 2943 t1 = tcg_const_i32(nb); 2944 t2 = tcg_const_i32(start); 2945 gen_helper_lsw(cpu_env, t0, t1, t2); 2946 tcg_temp_free(t0); 2947 tcg_temp_free_i32(t1); 2948 tcg_temp_free_i32(t2); 2949 } 2950 2951 /* lswx */ 2952 static void gen_lswx(DisasContext *ctx) 2953 { 2954 TCGv t0; 2955 TCGv_i32 t1, t2, t3; 2956 2957 if (ctx->le_mode) { 2958 gen_align_no_le(ctx); 2959 return; 2960 } 2961 gen_set_access_type(ctx, ACCESS_INT); 2962 t0 = tcg_temp_new(); 2963 gen_addr_reg_index(ctx, t0); 2964 t1 = tcg_const_i32(rD(ctx->opcode)); 2965 t2 = tcg_const_i32(rA(ctx->opcode)); 2966 t3 = tcg_const_i32(rB(ctx->opcode)); 2967 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 2968 tcg_temp_free(t0); 2969 tcg_temp_free_i32(t1); 2970 tcg_temp_free_i32(t2); 2971 tcg_temp_free_i32(t3); 2972 } 2973 2974 /* stswi */ 2975 static void gen_stswi(DisasContext *ctx) 2976 { 2977 TCGv t0; 2978 TCGv_i32 t1, t2; 2979 int nb = NB(ctx->opcode); 2980 2981 if (ctx->le_mode) { 2982 gen_align_no_le(ctx); 2983 return; 2984 } 2985 gen_set_access_type(ctx, ACCESS_INT); 2986 t0 = tcg_temp_new(); 2987 gen_addr_register(ctx, t0); 2988 if (nb == 0) 2989 nb = 32; 2990 t1 = tcg_const_i32(nb); 2991 t2 = tcg_const_i32(rS(ctx->opcode)); 2992 gen_helper_stsw(cpu_env, t0, t1, t2); 2993 tcg_temp_free(t0); 2994 tcg_temp_free_i32(t1); 2995 tcg_temp_free_i32(t2); 2996 } 2997 2998 /* stswx */ 2999 static void gen_stswx(DisasContext *ctx) 3000 { 3001 TCGv t0; 3002 TCGv_i32 t1, t2; 3003 3004 if (ctx->le_mode) { 3005 gen_align_no_le(ctx); 3006 return; 3007 } 3008 gen_set_access_type(ctx, ACCESS_INT); 3009 t0 = tcg_temp_new(); 3010 gen_addr_reg_index(ctx, t0); 3011 t1 = tcg_temp_new_i32(); 3012 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3013 tcg_gen_andi_i32(t1, t1, 0x7F); 3014 t2 = tcg_const_i32(rS(ctx->opcode)); 3015 gen_helper_stsw(cpu_env, t0, t1, t2); 3016 tcg_temp_free(t0); 3017 tcg_temp_free_i32(t1); 3018 tcg_temp_free_i32(t2); 3019 } 3020 3021 /*** Memory synchronisation ***/ 3022 /* eieio */ 3023 static void gen_eieio(DisasContext *ctx) 3024 { 3025 TCGBar bar = TCG_MO_LD_ST; 3026 3027 /* 3028 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3029 * tell the CPU it is a store-forwarding barrier. 3030 */ 3031 if (ctx->opcode & 0x2000000) { 3032 /* 3033 * ISA says that "Reserved fields in instructions are ignored 3034 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3035 * as this is not an instruction software should be using, 3036 * complain to the user. 3037 */ 3038 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3039 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3040 TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 3041 } else { 3042 bar = TCG_MO_ST_LD; 3043 } 3044 } 3045 3046 tcg_gen_mb(bar | TCG_BAR_SC); 3047 } 3048 3049 #if !defined(CONFIG_USER_ONLY) 3050 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3051 { 3052 TCGv_i32 t; 3053 TCGLabel *l; 3054 3055 if (!ctx->lazy_tlb_flush) { 3056 return; 3057 } 3058 l = gen_new_label(); 3059 t = tcg_temp_new_i32(); 3060 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3061 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3062 if (global) { 3063 gen_helper_check_tlb_flush_global(cpu_env); 3064 } else { 3065 gen_helper_check_tlb_flush_local(cpu_env); 3066 } 3067 gen_set_label(l); 3068 tcg_temp_free_i32(t); 3069 } 3070 #else 3071 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3072 #endif 3073 3074 /* isync */ 3075 static void gen_isync(DisasContext *ctx) 3076 { 3077 /* 3078 * We need to check for a pending TLB flush. This can only happen in 3079 * kernel mode however so check MSR_PR 3080 */ 3081 if (!ctx->pr) { 3082 gen_check_tlb_flush(ctx, false); 3083 } 3084 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3085 gen_stop_exception(ctx); 3086 } 3087 3088 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3089 3090 static void gen_load_locked(DisasContext *ctx, TCGMemOp memop) 3091 { 3092 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3093 TCGv t0 = tcg_temp_new(); 3094 3095 gen_set_access_type(ctx, ACCESS_RES); 3096 gen_addr_reg_index(ctx, t0); 3097 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3098 tcg_gen_mov_tl(cpu_reserve, t0); 3099 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3100 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 3101 tcg_temp_free(t0); 3102 } 3103 3104 #define LARX(name, memop) \ 3105 static void gen_##name(DisasContext *ctx) \ 3106 { \ 3107 gen_load_locked(ctx, memop); \ 3108 } 3109 3110 /* lwarx */ 3111 LARX(lbarx, DEF_MEMOP(MO_UB)) 3112 LARX(lharx, DEF_MEMOP(MO_UW)) 3113 LARX(lwarx, DEF_MEMOP(MO_UL)) 3114 3115 static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop, 3116 TCGv EA, TCGCond cond, int addend) 3117 { 3118 TCGv t = tcg_temp_new(); 3119 TCGv t2 = tcg_temp_new(); 3120 TCGv u = tcg_temp_new(); 3121 3122 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3123 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3124 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3125 tcg_gen_addi_tl(u, t, addend); 3126 3127 /* E.g. for fetch and increment bounded... */ 3128 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3129 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3130 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3131 3132 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3133 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3134 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3135 3136 tcg_temp_free(t); 3137 tcg_temp_free(t2); 3138 tcg_temp_free(u); 3139 } 3140 3141 static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) 3142 { 3143 uint32_t gpr_FC = FC(ctx->opcode); 3144 TCGv EA = tcg_temp_new(); 3145 int rt = rD(ctx->opcode); 3146 bool need_serial; 3147 TCGv src, dst; 3148 3149 gen_addr_register(ctx, EA); 3150 dst = cpu_gpr[rt]; 3151 src = cpu_gpr[(rt + 1) & 31]; 3152 3153 need_serial = false; 3154 memop |= MO_ALIGN; 3155 switch (gpr_FC) { 3156 case 0: /* Fetch and add */ 3157 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3158 break; 3159 case 1: /* Fetch and xor */ 3160 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3161 break; 3162 case 2: /* Fetch and or */ 3163 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3164 break; 3165 case 3: /* Fetch and 'and' */ 3166 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3167 break; 3168 case 4: /* Fetch and max unsigned */ 3169 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3170 break; 3171 case 5: /* Fetch and max signed */ 3172 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3173 break; 3174 case 6: /* Fetch and min unsigned */ 3175 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3176 break; 3177 case 7: /* Fetch and min signed */ 3178 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3179 break; 3180 case 8: /* Swap */ 3181 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3182 break; 3183 3184 case 16: /* Compare and swap not equal */ 3185 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3186 need_serial = true; 3187 } else { 3188 TCGv t0 = tcg_temp_new(); 3189 TCGv t1 = tcg_temp_new(); 3190 3191 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3192 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3193 tcg_gen_mov_tl(t1, src); 3194 } else { 3195 tcg_gen_ext32u_tl(t1, src); 3196 } 3197 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3198 cpu_gpr[(rt + 2) & 31], t0); 3199 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3200 tcg_gen_mov_tl(dst, t0); 3201 3202 tcg_temp_free(t0); 3203 tcg_temp_free(t1); 3204 } 3205 break; 3206 3207 case 24: /* Fetch and increment bounded */ 3208 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3209 need_serial = true; 3210 } else { 3211 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3212 } 3213 break; 3214 case 25: /* Fetch and increment equal */ 3215 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3216 need_serial = true; 3217 } else { 3218 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3219 } 3220 break; 3221 case 28: /* Fetch and decrement bounded */ 3222 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3223 need_serial = true; 3224 } else { 3225 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3226 } 3227 break; 3228 3229 default: 3230 /* invoke data storage error handler */ 3231 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3232 } 3233 tcg_temp_free(EA); 3234 3235 if (need_serial) { 3236 /* Restart with exclusive lock. */ 3237 gen_helper_exit_atomic(cpu_env); 3238 ctx->base.is_jmp = DISAS_NORETURN; 3239 } 3240 } 3241 3242 static void gen_lwat(DisasContext *ctx) 3243 { 3244 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3245 } 3246 3247 #ifdef TARGET_PPC64 3248 static void gen_ldat(DisasContext *ctx) 3249 { 3250 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 3251 } 3252 #endif 3253 3254 static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) 3255 { 3256 uint32_t gpr_FC = FC(ctx->opcode); 3257 TCGv EA = tcg_temp_new(); 3258 TCGv src, discard; 3259 3260 gen_addr_register(ctx, EA); 3261 src = cpu_gpr[rD(ctx->opcode)]; 3262 discard = tcg_temp_new(); 3263 3264 memop |= MO_ALIGN; 3265 switch (gpr_FC) { 3266 case 0: /* add and Store */ 3267 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3268 break; 3269 case 1: /* xor and Store */ 3270 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3271 break; 3272 case 2: /* Or and Store */ 3273 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3274 break; 3275 case 3: /* 'and' and Store */ 3276 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3277 break; 3278 case 4: /* Store max unsigned */ 3279 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3280 break; 3281 case 5: /* Store max signed */ 3282 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3283 break; 3284 case 6: /* Store min unsigned */ 3285 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3286 break; 3287 case 7: /* Store min signed */ 3288 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3289 break; 3290 case 24: /* Store twin */ 3291 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3292 /* Restart with exclusive lock. */ 3293 gen_helper_exit_atomic(cpu_env); 3294 ctx->base.is_jmp = DISAS_NORETURN; 3295 } else { 3296 TCGv t = tcg_temp_new(); 3297 TCGv t2 = tcg_temp_new(); 3298 TCGv s = tcg_temp_new(); 3299 TCGv s2 = tcg_temp_new(); 3300 TCGv ea_plus_s = tcg_temp_new(); 3301 3302 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3303 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3304 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3305 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3306 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3307 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3308 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3309 3310 tcg_temp_free(ea_plus_s); 3311 tcg_temp_free(s2); 3312 tcg_temp_free(s); 3313 tcg_temp_free(t2); 3314 tcg_temp_free(t); 3315 } 3316 break; 3317 default: 3318 /* invoke data storage error handler */ 3319 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3320 } 3321 tcg_temp_free(discard); 3322 tcg_temp_free(EA); 3323 } 3324 3325 static void gen_stwat(DisasContext *ctx) 3326 { 3327 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3328 } 3329 3330 #ifdef TARGET_PPC64 3331 static void gen_stdat(DisasContext *ctx) 3332 { 3333 gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 3334 } 3335 #endif 3336 3337 static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) 3338 { 3339 TCGLabel *l1 = gen_new_label(); 3340 TCGLabel *l2 = gen_new_label(); 3341 TCGv t0 = tcg_temp_new(); 3342 int reg = rS(ctx->opcode); 3343 3344 gen_set_access_type(ctx, ACCESS_RES); 3345 gen_addr_reg_index(ctx, t0); 3346 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3347 tcg_temp_free(t0); 3348 3349 t0 = tcg_temp_new(); 3350 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3351 cpu_gpr[reg], ctx->mem_idx, 3352 DEF_MEMOP(memop) | MO_ALIGN); 3353 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3354 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3355 tcg_gen_or_tl(t0, t0, cpu_so); 3356 tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3357 tcg_temp_free(t0); 3358 tcg_gen_br(l2); 3359 3360 gen_set_label(l1); 3361 3362 /* Address mismatch implies failure. But we still need to provide the 3363 memory barrier semantics of the instruction. */ 3364 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3365 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3366 3367 gen_set_label(l2); 3368 tcg_gen_movi_tl(cpu_reserve, -1); 3369 } 3370 3371 #define STCX(name, memop) \ 3372 static void gen_##name(DisasContext *ctx) \ 3373 { \ 3374 gen_conditional_store(ctx, memop); \ 3375 } 3376 3377 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3378 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3379 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3380 3381 #if defined(TARGET_PPC64) 3382 /* ldarx */ 3383 LARX(ldarx, DEF_MEMOP(MO_Q)) 3384 /* stdcx. */ 3385 STCX(stdcx_, DEF_MEMOP(MO_Q)) 3386 3387 /* lqarx */ 3388 static void gen_lqarx(DisasContext *ctx) 3389 { 3390 int rd = rD(ctx->opcode); 3391 TCGv EA, hi, lo; 3392 3393 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3394 (rd == rB(ctx->opcode)))) { 3395 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3396 return; 3397 } 3398 3399 gen_set_access_type(ctx, ACCESS_RES); 3400 EA = tcg_temp_new(); 3401 gen_addr_reg_index(ctx, EA); 3402 3403 /* Note that the low part is always in RD+1, even in LE mode. */ 3404 lo = cpu_gpr[rd + 1]; 3405 hi = cpu_gpr[rd]; 3406 3407 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3408 if (HAVE_ATOMIC128) { 3409 TCGv_i32 oi = tcg_temp_new_i32(); 3410 if (ctx->le_mode) { 3411 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 3412 ctx->mem_idx)); 3413 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3414 } else { 3415 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 3416 ctx->mem_idx)); 3417 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3418 } 3419 tcg_temp_free_i32(oi); 3420 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3421 } else { 3422 /* Restart with exclusive lock. */ 3423 gen_helper_exit_atomic(cpu_env); 3424 ctx->base.is_jmp = DISAS_NORETURN; 3425 tcg_temp_free(EA); 3426 return; 3427 } 3428 } else if (ctx->le_mode) { 3429 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3430 tcg_gen_mov_tl(cpu_reserve, EA); 3431 gen_addr_add(ctx, EA, EA, 8); 3432 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3433 } else { 3434 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 3435 tcg_gen_mov_tl(cpu_reserve, EA); 3436 gen_addr_add(ctx, EA, EA, 8); 3437 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3438 } 3439 tcg_temp_free(EA); 3440 3441 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3442 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3443 } 3444 3445 /* stqcx. */ 3446 static void gen_stqcx_(DisasContext *ctx) 3447 { 3448 int rs = rS(ctx->opcode); 3449 TCGv EA, hi, lo; 3450 3451 if (unlikely(rs & 1)) { 3452 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3453 return; 3454 } 3455 3456 gen_set_access_type(ctx, ACCESS_RES); 3457 EA = tcg_temp_new(); 3458 gen_addr_reg_index(ctx, EA); 3459 3460 /* Note that the low part is always in RS+1, even in LE mode. */ 3461 lo = cpu_gpr[rs + 1]; 3462 hi = cpu_gpr[rs]; 3463 3464 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3465 if (HAVE_CMPXCHG128) { 3466 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 3467 if (ctx->le_mode) { 3468 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 3469 EA, lo, hi, oi); 3470 } else { 3471 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 3472 EA, lo, hi, oi); 3473 } 3474 tcg_temp_free_i32(oi); 3475 } else { 3476 /* Restart with exclusive lock. */ 3477 gen_helper_exit_atomic(cpu_env); 3478 ctx->base.is_jmp = DISAS_NORETURN; 3479 } 3480 tcg_temp_free(EA); 3481 } else { 3482 TCGLabel *lab_fail = gen_new_label(); 3483 TCGLabel *lab_over = gen_new_label(); 3484 TCGv_i64 t0 = tcg_temp_new_i64(); 3485 TCGv_i64 t1 = tcg_temp_new_i64(); 3486 3487 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 3488 tcg_temp_free(EA); 3489 3490 gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 3491 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 3492 ? offsetof(CPUPPCState, reserve_val2) 3493 : offsetof(CPUPPCState, reserve_val))); 3494 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 3495 3496 tcg_gen_addi_i64(t0, cpu_reserve, 8); 3497 gen_qemu_ld64_i64(ctx, t0, t0); 3498 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 3499 ? offsetof(CPUPPCState, reserve_val) 3500 : offsetof(CPUPPCState, reserve_val2))); 3501 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 3502 3503 /* Success */ 3504 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 3505 tcg_gen_addi_i64(t0, cpu_reserve, 8); 3506 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 3507 3508 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3509 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3510 tcg_gen_br(lab_over); 3511 3512 gen_set_label(lab_fail); 3513 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3514 3515 gen_set_label(lab_over); 3516 tcg_gen_movi_tl(cpu_reserve, -1); 3517 tcg_temp_free_i64(t0); 3518 tcg_temp_free_i64(t1); 3519 } 3520 } 3521 #endif /* defined(TARGET_PPC64) */ 3522 3523 /* sync */ 3524 static void gen_sync(DisasContext *ctx) 3525 { 3526 uint32_t l = (ctx->opcode >> 21) & 3; 3527 3528 /* 3529 * We may need to check for a pending TLB flush. 3530 * 3531 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3532 * 3533 * Additionally, this can only happen in kernel mode however so 3534 * check MSR_PR as well. 3535 */ 3536 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3537 gen_check_tlb_flush(ctx, true); 3538 } 3539 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3540 } 3541 3542 /* wait */ 3543 static void gen_wait(DisasContext *ctx) 3544 { 3545 TCGv_i32 t0 = tcg_const_i32(1); 3546 tcg_gen_st_i32(t0, cpu_env, 3547 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3548 tcg_temp_free_i32(t0); 3549 /* Stop translation, as the CPU is supposed to sleep from now */ 3550 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3551 } 3552 3553 #if defined(TARGET_PPC64) 3554 static void gen_doze(DisasContext *ctx) 3555 { 3556 #if defined(CONFIG_USER_ONLY) 3557 GEN_PRIV; 3558 #else 3559 TCGv_i32 t; 3560 3561 CHK_HV; 3562 t = tcg_const_i32(PPC_PM_DOZE); 3563 gen_helper_pminsn(cpu_env, t); 3564 tcg_temp_free_i32(t); 3565 gen_stop_exception(ctx); 3566 #endif /* defined(CONFIG_USER_ONLY) */ 3567 } 3568 3569 static void gen_nap(DisasContext *ctx) 3570 { 3571 #if defined(CONFIG_USER_ONLY) 3572 GEN_PRIV; 3573 #else 3574 TCGv_i32 t; 3575 3576 CHK_HV; 3577 t = tcg_const_i32(PPC_PM_NAP); 3578 gen_helper_pminsn(cpu_env, t); 3579 tcg_temp_free_i32(t); 3580 gen_stop_exception(ctx); 3581 #endif /* defined(CONFIG_USER_ONLY) */ 3582 } 3583 3584 static void gen_stop(DisasContext *ctx) 3585 { 3586 gen_nap(ctx); 3587 } 3588 3589 static void gen_sleep(DisasContext *ctx) 3590 { 3591 #if defined(CONFIG_USER_ONLY) 3592 GEN_PRIV; 3593 #else 3594 TCGv_i32 t; 3595 3596 CHK_HV; 3597 t = tcg_const_i32(PPC_PM_SLEEP); 3598 gen_helper_pminsn(cpu_env, t); 3599 tcg_temp_free_i32(t); 3600 gen_stop_exception(ctx); 3601 #endif /* defined(CONFIG_USER_ONLY) */ 3602 } 3603 3604 static void gen_rvwinkle(DisasContext *ctx) 3605 { 3606 #if defined(CONFIG_USER_ONLY) 3607 GEN_PRIV; 3608 #else 3609 TCGv_i32 t; 3610 3611 CHK_HV; 3612 t = tcg_const_i32(PPC_PM_RVWINKLE); 3613 gen_helper_pminsn(cpu_env, t); 3614 tcg_temp_free_i32(t); 3615 gen_stop_exception(ctx); 3616 #endif /* defined(CONFIG_USER_ONLY) */ 3617 } 3618 #endif /* #if defined(TARGET_PPC64) */ 3619 3620 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3621 { 3622 #if defined(TARGET_PPC64) 3623 if (ctx->has_cfar) 3624 tcg_gen_movi_tl(cpu_cfar, nip); 3625 #endif 3626 } 3627 3628 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3629 { 3630 if (unlikely(ctx->singlestep_enabled)) { 3631 return false; 3632 } 3633 3634 #ifndef CONFIG_USER_ONLY 3635 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3636 #else 3637 return true; 3638 #endif 3639 } 3640 3641 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 3642 { 3643 int sse = ctx->singlestep_enabled; 3644 if (unlikely(sse)) { 3645 if (sse & GDBSTUB_SINGLE_STEP) { 3646 gen_debug_exception(ctx); 3647 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 3648 uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_BRANCH); 3649 if (excp != POWERPC_EXCP_NONE) { 3650 gen_exception(ctx, excp); 3651 } 3652 } 3653 tcg_gen_exit_tb(NULL, 0); 3654 } else { 3655 tcg_gen_lookup_and_goto_ptr(); 3656 } 3657 } 3658 3659 /*** Branch ***/ 3660 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3661 { 3662 if (NARROW_MODE(ctx)) { 3663 dest = (uint32_t) dest; 3664 } 3665 if (use_goto_tb(ctx, dest)) { 3666 tcg_gen_goto_tb(n); 3667 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3668 tcg_gen_exit_tb(ctx->base.tb, n); 3669 } else { 3670 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3671 gen_lookup_and_goto_ptr(ctx); 3672 } 3673 } 3674 3675 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3676 { 3677 if (NARROW_MODE(ctx)) { 3678 nip = (uint32_t)nip; 3679 } 3680 tcg_gen_movi_tl(cpu_lr, nip); 3681 } 3682 3683 /* b ba bl bla */ 3684 static void gen_b(DisasContext *ctx) 3685 { 3686 target_ulong li, target; 3687 3688 ctx->exception = POWERPC_EXCP_BRANCH; 3689 /* sign extend LI */ 3690 li = LI(ctx->opcode); 3691 li = (li ^ 0x02000000) - 0x02000000; 3692 if (likely(AA(ctx->opcode) == 0)) { 3693 target = ctx->base.pc_next + li - 4; 3694 } else { 3695 target = li; 3696 } 3697 if (LK(ctx->opcode)) { 3698 gen_setlr(ctx, ctx->base.pc_next); 3699 } 3700 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3701 gen_goto_tb(ctx, 0, target); 3702 } 3703 3704 #define BCOND_IM 0 3705 #define BCOND_LR 1 3706 #define BCOND_CTR 2 3707 #define BCOND_TAR 3 3708 3709 static void gen_bcond(DisasContext *ctx, int type) 3710 { 3711 uint32_t bo = BO(ctx->opcode); 3712 TCGLabel *l1; 3713 TCGv target; 3714 ctx->exception = POWERPC_EXCP_BRANCH; 3715 3716 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3717 target = tcg_temp_local_new(); 3718 if (type == BCOND_CTR) 3719 tcg_gen_mov_tl(target, cpu_ctr); 3720 else if (type == BCOND_TAR) 3721 gen_load_spr(target, SPR_TAR); 3722 else 3723 tcg_gen_mov_tl(target, cpu_lr); 3724 } else { 3725 target = NULL; 3726 } 3727 if (LK(ctx->opcode)) 3728 gen_setlr(ctx, ctx->base.pc_next); 3729 l1 = gen_new_label(); 3730 if ((bo & 0x4) == 0) { 3731 /* Decrement and test CTR */ 3732 TCGv temp = tcg_temp_new(); 3733 if (unlikely(type == BCOND_CTR)) { 3734 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3735 return; 3736 } 3737 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3738 if (NARROW_MODE(ctx)) { 3739 tcg_gen_ext32u_tl(temp, cpu_ctr); 3740 } else { 3741 tcg_gen_mov_tl(temp, cpu_ctr); 3742 } 3743 if (bo & 0x2) { 3744 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3745 } else { 3746 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3747 } 3748 tcg_temp_free(temp); 3749 } 3750 if ((bo & 0x10) == 0) { 3751 /* Test CR */ 3752 uint32_t bi = BI(ctx->opcode); 3753 uint32_t mask = 0x08 >> (bi & 0x03); 3754 TCGv_i32 temp = tcg_temp_new_i32(); 3755 3756 if (bo & 0x8) { 3757 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3758 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3759 } else { 3760 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3761 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3762 } 3763 tcg_temp_free_i32(temp); 3764 } 3765 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3766 if (type == BCOND_IM) { 3767 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3768 if (likely(AA(ctx->opcode) == 0)) { 3769 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3770 } else { 3771 gen_goto_tb(ctx, 0, li); 3772 } 3773 } else { 3774 if (NARROW_MODE(ctx)) { 3775 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3776 } else { 3777 tcg_gen_andi_tl(cpu_nip, target, ~3); 3778 } 3779 gen_lookup_and_goto_ptr(ctx); 3780 tcg_temp_free(target); 3781 } 3782 if ((bo & 0x14) != 0x14) { 3783 /* fallthrough case */ 3784 gen_set_label(l1); 3785 gen_goto_tb(ctx, 1, ctx->base.pc_next); 3786 } 3787 } 3788 3789 static void gen_bc(DisasContext *ctx) 3790 { 3791 gen_bcond(ctx, BCOND_IM); 3792 } 3793 3794 static void gen_bcctr(DisasContext *ctx) 3795 { 3796 gen_bcond(ctx, BCOND_CTR); 3797 } 3798 3799 static void gen_bclr(DisasContext *ctx) 3800 { 3801 gen_bcond(ctx, BCOND_LR); 3802 } 3803 3804 static void gen_bctar(DisasContext *ctx) 3805 { 3806 gen_bcond(ctx, BCOND_TAR); 3807 } 3808 3809 /*** Condition register logical ***/ 3810 #define GEN_CRLOGIC(name, tcg_op, opc) \ 3811 static void glue(gen_, name)(DisasContext *ctx) \ 3812 { \ 3813 uint8_t bitmask; \ 3814 int sh; \ 3815 TCGv_i32 t0, t1; \ 3816 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3817 t0 = tcg_temp_new_i32(); \ 3818 if (sh > 0) \ 3819 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3820 else if (sh < 0) \ 3821 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3822 else \ 3823 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3824 t1 = tcg_temp_new_i32(); \ 3825 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3826 if (sh > 0) \ 3827 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3828 else if (sh < 0) \ 3829 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3830 else \ 3831 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3832 tcg_op(t0, t0, t1); \ 3833 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3834 tcg_gen_andi_i32(t0, t0, bitmask); \ 3835 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3836 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3837 tcg_temp_free_i32(t0); \ 3838 tcg_temp_free_i32(t1); \ 3839 } 3840 3841 /* crand */ 3842 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3843 /* crandc */ 3844 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3845 /* creqv */ 3846 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3847 /* crnand */ 3848 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3849 /* crnor */ 3850 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3851 /* cror */ 3852 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3853 /* crorc */ 3854 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3855 /* crxor */ 3856 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3857 3858 /* mcrf */ 3859 static void gen_mcrf(DisasContext *ctx) 3860 { 3861 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3862 } 3863 3864 /*** System linkage ***/ 3865 3866 /* rfi (supervisor only) */ 3867 static void gen_rfi(DisasContext *ctx) 3868 { 3869 #if defined(CONFIG_USER_ONLY) 3870 GEN_PRIV; 3871 #else 3872 /* This instruction doesn't exist anymore on 64-bit server 3873 * processors compliant with arch 2.x 3874 */ 3875 if (ctx->insns_flags & PPC_SEGMENT_64B) { 3876 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3877 return; 3878 } 3879 /* Restore CPU state */ 3880 CHK_SV; 3881 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3882 gen_helper_rfi(cpu_env); 3883 gen_sync_exception(ctx); 3884 #endif 3885 } 3886 3887 #if defined(TARGET_PPC64) 3888 static void gen_rfid(DisasContext *ctx) 3889 { 3890 #if defined(CONFIG_USER_ONLY) 3891 GEN_PRIV; 3892 #else 3893 /* Restore CPU state */ 3894 CHK_SV; 3895 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3896 gen_helper_rfid(cpu_env); 3897 gen_sync_exception(ctx); 3898 #endif 3899 } 3900 3901 static void gen_hrfid(DisasContext *ctx) 3902 { 3903 #if defined(CONFIG_USER_ONLY) 3904 GEN_PRIV; 3905 #else 3906 /* Restore CPU state */ 3907 CHK_HV; 3908 gen_helper_hrfid(cpu_env); 3909 gen_sync_exception(ctx); 3910 #endif 3911 } 3912 #endif 3913 3914 /* sc */ 3915 #if defined(CONFIG_USER_ONLY) 3916 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3917 #else 3918 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3919 #endif 3920 static void gen_sc(DisasContext *ctx) 3921 { 3922 uint32_t lev; 3923 3924 lev = (ctx->opcode >> 5) & 0x7F; 3925 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3926 } 3927 3928 /*** Trap ***/ 3929 3930 /* Check for unconditional traps (always or never) */ 3931 static bool check_unconditional_trap(DisasContext *ctx) 3932 { 3933 /* Trap never */ 3934 if (TO(ctx->opcode) == 0) { 3935 return true; 3936 } 3937 /* Trap always */ 3938 if (TO(ctx->opcode) == 31) { 3939 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3940 return true; 3941 } 3942 return false; 3943 } 3944 3945 /* tw */ 3946 static void gen_tw(DisasContext *ctx) 3947 { 3948 TCGv_i32 t0; 3949 3950 if (check_unconditional_trap(ctx)) { 3951 return; 3952 } 3953 t0 = tcg_const_i32(TO(ctx->opcode)); 3954 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3955 t0); 3956 tcg_temp_free_i32(t0); 3957 } 3958 3959 /* twi */ 3960 static void gen_twi(DisasContext *ctx) 3961 { 3962 TCGv t0; 3963 TCGv_i32 t1; 3964 3965 if (check_unconditional_trap(ctx)) { 3966 return; 3967 } 3968 t0 = tcg_const_tl(SIMM(ctx->opcode)); 3969 t1 = tcg_const_i32(TO(ctx->opcode)); 3970 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3971 tcg_temp_free(t0); 3972 tcg_temp_free_i32(t1); 3973 } 3974 3975 #if defined(TARGET_PPC64) 3976 /* td */ 3977 static void gen_td(DisasContext *ctx) 3978 { 3979 TCGv_i32 t0; 3980 3981 if (check_unconditional_trap(ctx)) { 3982 return; 3983 } 3984 t0 = tcg_const_i32(TO(ctx->opcode)); 3985 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3986 t0); 3987 tcg_temp_free_i32(t0); 3988 } 3989 3990 /* tdi */ 3991 static void gen_tdi(DisasContext *ctx) 3992 { 3993 TCGv t0; 3994 TCGv_i32 t1; 3995 3996 if (check_unconditional_trap(ctx)) { 3997 return; 3998 } 3999 t0 = tcg_const_tl(SIMM(ctx->opcode)); 4000 t1 = tcg_const_i32(TO(ctx->opcode)); 4001 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4002 tcg_temp_free(t0); 4003 tcg_temp_free_i32(t1); 4004 } 4005 #endif 4006 4007 /*** Processor control ***/ 4008 4009 static void gen_read_xer(DisasContext *ctx, TCGv dst) 4010 { 4011 TCGv t0 = tcg_temp_new(); 4012 TCGv t1 = tcg_temp_new(); 4013 TCGv t2 = tcg_temp_new(); 4014 tcg_gen_mov_tl(dst, cpu_xer); 4015 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 4016 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 4017 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 4018 tcg_gen_or_tl(t0, t0, t1); 4019 tcg_gen_or_tl(dst, dst, t2); 4020 tcg_gen_or_tl(dst, dst, t0); 4021 if (is_isa300(ctx)) { 4022 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 4023 tcg_gen_or_tl(dst, dst, t0); 4024 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 4025 tcg_gen_or_tl(dst, dst, t0); 4026 } 4027 tcg_temp_free(t0); 4028 tcg_temp_free(t1); 4029 tcg_temp_free(t2); 4030 } 4031 4032 static void gen_write_xer(TCGv src) 4033 { 4034 /* Write all flags, while reading back check for isa300 */ 4035 tcg_gen_andi_tl(cpu_xer, src, 4036 ~((1u << XER_SO) | 4037 (1u << XER_OV) | (1u << XER_OV32) | 4038 (1u << XER_CA) | (1u << XER_CA32))); 4039 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 4040 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 4041 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 4042 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 4043 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 4044 } 4045 4046 /* mcrxr */ 4047 static void gen_mcrxr(DisasContext *ctx) 4048 { 4049 TCGv_i32 t0 = tcg_temp_new_i32(); 4050 TCGv_i32 t1 = tcg_temp_new_i32(); 4051 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4052 4053 tcg_gen_trunc_tl_i32(t0, cpu_so); 4054 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4055 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4056 tcg_gen_shli_i32(t0, t0, 3); 4057 tcg_gen_shli_i32(t1, t1, 2); 4058 tcg_gen_shli_i32(dst, dst, 1); 4059 tcg_gen_or_i32(dst, dst, t0); 4060 tcg_gen_or_i32(dst, dst, t1); 4061 tcg_temp_free_i32(t0); 4062 tcg_temp_free_i32(t1); 4063 4064 tcg_gen_movi_tl(cpu_so, 0); 4065 tcg_gen_movi_tl(cpu_ov, 0); 4066 tcg_gen_movi_tl(cpu_ca, 0); 4067 } 4068 4069 #ifdef TARGET_PPC64 4070 /* mcrxrx */ 4071 static void gen_mcrxrx(DisasContext *ctx) 4072 { 4073 TCGv t0 = tcg_temp_new(); 4074 TCGv t1 = tcg_temp_new(); 4075 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4076 4077 /* copy OV and OV32 */ 4078 tcg_gen_shli_tl(t0, cpu_ov, 1); 4079 tcg_gen_or_tl(t0, t0, cpu_ov32); 4080 tcg_gen_shli_tl(t0, t0, 2); 4081 /* copy CA and CA32 */ 4082 tcg_gen_shli_tl(t1, cpu_ca, 1); 4083 tcg_gen_or_tl(t1, t1, cpu_ca32); 4084 tcg_gen_or_tl(t0, t0, t1); 4085 tcg_gen_trunc_tl_i32(dst, t0); 4086 tcg_temp_free(t0); 4087 tcg_temp_free(t1); 4088 } 4089 #endif 4090 4091 /* mfcr mfocrf */ 4092 static void gen_mfcr(DisasContext *ctx) 4093 { 4094 uint32_t crm, crn; 4095 4096 if (likely(ctx->opcode & 0x00100000)) { 4097 crm = CRM(ctx->opcode); 4098 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4099 crn = ctz32 (crm); 4100 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4101 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4102 cpu_gpr[rD(ctx->opcode)], crn * 4); 4103 } 4104 } else { 4105 TCGv_i32 t0 = tcg_temp_new_i32(); 4106 tcg_gen_mov_i32(t0, cpu_crf[0]); 4107 tcg_gen_shli_i32(t0, t0, 4); 4108 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4109 tcg_gen_shli_i32(t0, t0, 4); 4110 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4111 tcg_gen_shli_i32(t0, t0, 4); 4112 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4113 tcg_gen_shli_i32(t0, t0, 4); 4114 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4115 tcg_gen_shli_i32(t0, t0, 4); 4116 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4117 tcg_gen_shli_i32(t0, t0, 4); 4118 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4119 tcg_gen_shli_i32(t0, t0, 4); 4120 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4121 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4122 tcg_temp_free_i32(t0); 4123 } 4124 } 4125 4126 /* mfmsr */ 4127 static void gen_mfmsr(DisasContext *ctx) 4128 { 4129 CHK_SV; 4130 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4131 } 4132 4133 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 4134 { 4135 #if 0 4136 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 4137 printf("ERROR: try to access SPR %d !\n", sprn); 4138 #endif 4139 } 4140 #define SPR_NOACCESS (&spr_noaccess) 4141 4142 /* mfspr */ 4143 static inline void gen_op_mfspr(DisasContext *ctx) 4144 { 4145 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4146 uint32_t sprn = SPR(ctx->opcode); 4147 4148 #if defined(CONFIG_USER_ONLY) 4149 read_cb = ctx->spr_cb[sprn].uea_read; 4150 #else 4151 if (ctx->pr) { 4152 read_cb = ctx->spr_cb[sprn].uea_read; 4153 } else if (ctx->hv) { 4154 read_cb = ctx->spr_cb[sprn].hea_read; 4155 } else { 4156 read_cb = ctx->spr_cb[sprn].oea_read; 4157 } 4158 #endif 4159 if (likely(read_cb != NULL)) { 4160 if (likely(read_cb != SPR_NOACCESS)) { 4161 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4162 } else { 4163 /* Privilege exception */ 4164 /* This is a hack to avoid warnings when running Linux: 4165 * this OS breaks the PowerPC virtualisation model, 4166 * allowing userland application to read the PVR 4167 */ 4168 if (sprn != SPR_PVR) { 4169 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4170 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4171 ctx->base.pc_next - 4); 4172 } 4173 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4174 } 4175 } else { 4176 /* ISA 2.07 defines these as no-ops */ 4177 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4178 (sprn >= 808 && sprn <= 811)) { 4179 /* This is a nop */ 4180 return; 4181 } 4182 /* Not defined */ 4183 qemu_log_mask(LOG_GUEST_ERROR, 4184 "Trying to read invalid spr %d (0x%03x) at " 4185 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4186 4187 /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4188 * it can generate a priv, a hv emu or a no-op 4189 */ 4190 if (sprn & 0x10) { 4191 if (ctx->pr) { 4192 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4193 } 4194 } else { 4195 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4196 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4197 } 4198 } 4199 } 4200 } 4201 4202 static void gen_mfspr(DisasContext *ctx) 4203 { 4204 gen_op_mfspr(ctx); 4205 } 4206 4207 /* mftb */ 4208 static void gen_mftb(DisasContext *ctx) 4209 { 4210 gen_op_mfspr(ctx); 4211 } 4212 4213 /* mtcrf mtocrf*/ 4214 static void gen_mtcrf(DisasContext *ctx) 4215 { 4216 uint32_t crm, crn; 4217 4218 crm = CRM(ctx->opcode); 4219 if (likely((ctx->opcode & 0x00100000))) { 4220 if (crm && ((crm & (crm - 1)) == 0)) { 4221 TCGv_i32 temp = tcg_temp_new_i32(); 4222 crn = ctz32 (crm); 4223 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4224 tcg_gen_shri_i32(temp, temp, crn * 4); 4225 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4226 tcg_temp_free_i32(temp); 4227 } 4228 } else { 4229 TCGv_i32 temp = tcg_temp_new_i32(); 4230 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4231 for (crn = 0 ; crn < 8 ; crn++) { 4232 if (crm & (1 << crn)) { 4233 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4234 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4235 } 4236 } 4237 tcg_temp_free_i32(temp); 4238 } 4239 } 4240 4241 /* mtmsr */ 4242 #if defined(TARGET_PPC64) 4243 static void gen_mtmsrd(DisasContext *ctx) 4244 { 4245 CHK_SV; 4246 4247 #if !defined(CONFIG_USER_ONLY) 4248 if (ctx->opcode & 0x00010000) { 4249 /* Special form that does not need any synchronisation */ 4250 TCGv t0 = tcg_temp_new(); 4251 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4252 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4253 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4254 tcg_temp_free(t0); 4255 } else { 4256 /* XXX: we need to update nip before the store 4257 * if we enter power saving mode, we will exit the loop 4258 * directly from ppc_store_msr 4259 */ 4260 gen_update_nip(ctx, ctx->base.pc_next); 4261 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4262 /* Must stop the translation as machine state (may have) changed */ 4263 /* Note that mtmsr is not always defined as context-synchronizing */ 4264 gen_stop_exception(ctx); 4265 } 4266 #endif /* !defined(CONFIG_USER_ONLY) */ 4267 } 4268 #endif /* defined(TARGET_PPC64) */ 4269 4270 static void gen_mtmsr(DisasContext *ctx) 4271 { 4272 CHK_SV; 4273 4274 #if !defined(CONFIG_USER_ONLY) 4275 if (ctx->opcode & 0x00010000) { 4276 /* Special form that does not need any synchronisation */ 4277 TCGv t0 = tcg_temp_new(); 4278 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4279 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4280 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4281 tcg_temp_free(t0); 4282 } else { 4283 TCGv msr = tcg_temp_new(); 4284 4285 /* XXX: we need to update nip before the store 4286 * if we enter power saving mode, we will exit the loop 4287 * directly from ppc_store_msr 4288 */ 4289 gen_update_nip(ctx, ctx->base.pc_next); 4290 #if defined(TARGET_PPC64) 4291 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4292 #else 4293 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4294 #endif 4295 gen_helper_store_msr(cpu_env, msr); 4296 tcg_temp_free(msr); 4297 /* Must stop the translation as machine state (may have) changed */ 4298 /* Note that mtmsr is not always defined as context-synchronizing */ 4299 gen_stop_exception(ctx); 4300 } 4301 #endif 4302 } 4303 4304 /* mtspr */ 4305 static void gen_mtspr(DisasContext *ctx) 4306 { 4307 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4308 uint32_t sprn = SPR(ctx->opcode); 4309 4310 #if defined(CONFIG_USER_ONLY) 4311 write_cb = ctx->spr_cb[sprn].uea_write; 4312 #else 4313 if (ctx->pr) { 4314 write_cb = ctx->spr_cb[sprn].uea_write; 4315 } else if (ctx->hv) { 4316 write_cb = ctx->spr_cb[sprn].hea_write; 4317 } else { 4318 write_cb = ctx->spr_cb[sprn].oea_write; 4319 } 4320 #endif 4321 if (likely(write_cb != NULL)) { 4322 if (likely(write_cb != SPR_NOACCESS)) { 4323 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4324 } else { 4325 /* Privilege exception */ 4326 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4327 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4328 ctx->base.pc_next - 4); 4329 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4330 } 4331 } else { 4332 /* ISA 2.07 defines these as no-ops */ 4333 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4334 (sprn >= 808 && sprn <= 811)) { 4335 /* This is a nop */ 4336 return; 4337 } 4338 4339 /* Not defined */ 4340 qemu_log_mask(LOG_GUEST_ERROR, 4341 "Trying to write invalid spr %d (0x%03x) at " 4342 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4343 4344 4345 /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4346 * it can generate a priv, a hv emu or a no-op 4347 */ 4348 if (sprn & 0x10) { 4349 if (ctx->pr) { 4350 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4351 } 4352 } else { 4353 if (ctx->pr || sprn == 0) { 4354 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4355 } 4356 } 4357 } 4358 } 4359 4360 #if defined(TARGET_PPC64) 4361 /* setb */ 4362 static void gen_setb(DisasContext *ctx) 4363 { 4364 TCGv_i32 t0 = tcg_temp_new_i32(); 4365 TCGv_i32 t8 = tcg_temp_new_i32(); 4366 TCGv_i32 tm1 = tcg_temp_new_i32(); 4367 int crf = crfS(ctx->opcode); 4368 4369 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4370 tcg_gen_movi_i32(t8, 8); 4371 tcg_gen_movi_i32(tm1, -1); 4372 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4373 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4374 4375 tcg_temp_free_i32(t0); 4376 tcg_temp_free_i32(t8); 4377 tcg_temp_free_i32(tm1); 4378 } 4379 #endif 4380 4381 /*** Cache management ***/ 4382 4383 /* dcbf */ 4384 static void gen_dcbf(DisasContext *ctx) 4385 { 4386 /* XXX: specification says this is treated as a load by the MMU */ 4387 TCGv t0; 4388 gen_set_access_type(ctx, ACCESS_CACHE); 4389 t0 = tcg_temp_new(); 4390 gen_addr_reg_index(ctx, t0); 4391 gen_qemu_ld8u(ctx, t0, t0); 4392 tcg_temp_free(t0); 4393 } 4394 4395 /* dcbi (Supervisor only) */ 4396 static void gen_dcbi(DisasContext *ctx) 4397 { 4398 #if defined(CONFIG_USER_ONLY) 4399 GEN_PRIV; 4400 #else 4401 TCGv EA, val; 4402 4403 CHK_SV; 4404 EA = tcg_temp_new(); 4405 gen_set_access_type(ctx, ACCESS_CACHE); 4406 gen_addr_reg_index(ctx, EA); 4407 val = tcg_temp_new(); 4408 /* XXX: specification says this should be treated as a store by the MMU */ 4409 gen_qemu_ld8u(ctx, val, EA); 4410 gen_qemu_st8(ctx, val, EA); 4411 tcg_temp_free(val); 4412 tcg_temp_free(EA); 4413 #endif /* defined(CONFIG_USER_ONLY) */ 4414 } 4415 4416 /* dcdst */ 4417 static void gen_dcbst(DisasContext *ctx) 4418 { 4419 /* XXX: specification say this is treated as a load by the MMU */ 4420 TCGv t0; 4421 gen_set_access_type(ctx, ACCESS_CACHE); 4422 t0 = tcg_temp_new(); 4423 gen_addr_reg_index(ctx, t0); 4424 gen_qemu_ld8u(ctx, t0, t0); 4425 tcg_temp_free(t0); 4426 } 4427 4428 /* dcbt */ 4429 static void gen_dcbt(DisasContext *ctx) 4430 { 4431 /* interpreted as no-op */ 4432 /* XXX: specification say this is treated as a load by the MMU 4433 * but does not generate any exception 4434 */ 4435 } 4436 4437 /* dcbtst */ 4438 static void gen_dcbtst(DisasContext *ctx) 4439 { 4440 /* interpreted as no-op */ 4441 /* XXX: specification say this is treated as a load by the MMU 4442 * but does not generate any exception 4443 */ 4444 } 4445 4446 /* dcbtls */ 4447 static void gen_dcbtls(DisasContext *ctx) 4448 { 4449 /* Always fails locking the cache */ 4450 TCGv t0 = tcg_temp_new(); 4451 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4452 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4453 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4454 tcg_temp_free(t0); 4455 } 4456 4457 /* dcbz */ 4458 static void gen_dcbz(DisasContext *ctx) 4459 { 4460 TCGv tcgv_addr; 4461 TCGv_i32 tcgv_op; 4462 4463 gen_set_access_type(ctx, ACCESS_CACHE); 4464 tcgv_addr = tcg_temp_new(); 4465 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4466 gen_addr_reg_index(ctx, tcgv_addr); 4467 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4468 tcg_temp_free(tcgv_addr); 4469 tcg_temp_free_i32(tcgv_op); 4470 } 4471 4472 /* dst / dstt */ 4473 static void gen_dst(DisasContext *ctx) 4474 { 4475 if (rA(ctx->opcode) == 0) { 4476 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4477 } else { 4478 /* interpreted as no-op */ 4479 } 4480 } 4481 4482 /* dstst /dststt */ 4483 static void gen_dstst(DisasContext *ctx) 4484 { 4485 if (rA(ctx->opcode) == 0) { 4486 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4487 } else { 4488 /* interpreted as no-op */ 4489 } 4490 4491 } 4492 4493 /* dss / dssall */ 4494 static void gen_dss(DisasContext *ctx) 4495 { 4496 /* interpreted as no-op */ 4497 } 4498 4499 /* icbi */ 4500 static void gen_icbi(DisasContext *ctx) 4501 { 4502 TCGv t0; 4503 gen_set_access_type(ctx, ACCESS_CACHE); 4504 t0 = tcg_temp_new(); 4505 gen_addr_reg_index(ctx, t0); 4506 gen_helper_icbi(cpu_env, t0); 4507 tcg_temp_free(t0); 4508 } 4509 4510 /* Optional: */ 4511 /* dcba */ 4512 static void gen_dcba(DisasContext *ctx) 4513 { 4514 /* interpreted as no-op */ 4515 /* XXX: specification say this is treated as a store by the MMU 4516 * but does not generate any exception 4517 */ 4518 } 4519 4520 /*** Segment register manipulation ***/ 4521 /* Supervisor only: */ 4522 4523 /* mfsr */ 4524 static void gen_mfsr(DisasContext *ctx) 4525 { 4526 #if defined(CONFIG_USER_ONLY) 4527 GEN_PRIV; 4528 #else 4529 TCGv t0; 4530 4531 CHK_SV; 4532 t0 = tcg_const_tl(SR(ctx->opcode)); 4533 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4534 tcg_temp_free(t0); 4535 #endif /* defined(CONFIG_USER_ONLY) */ 4536 } 4537 4538 /* mfsrin */ 4539 static void gen_mfsrin(DisasContext *ctx) 4540 { 4541 #if defined(CONFIG_USER_ONLY) 4542 GEN_PRIV; 4543 #else 4544 TCGv t0; 4545 4546 CHK_SV; 4547 t0 = tcg_temp_new(); 4548 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4549 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4550 tcg_temp_free(t0); 4551 #endif /* defined(CONFIG_USER_ONLY) */ 4552 } 4553 4554 /* mtsr */ 4555 static void gen_mtsr(DisasContext *ctx) 4556 { 4557 #if defined(CONFIG_USER_ONLY) 4558 GEN_PRIV; 4559 #else 4560 TCGv t0; 4561 4562 CHK_SV; 4563 t0 = tcg_const_tl(SR(ctx->opcode)); 4564 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4565 tcg_temp_free(t0); 4566 #endif /* defined(CONFIG_USER_ONLY) */ 4567 } 4568 4569 /* mtsrin */ 4570 static void gen_mtsrin(DisasContext *ctx) 4571 { 4572 #if defined(CONFIG_USER_ONLY) 4573 GEN_PRIV; 4574 #else 4575 TCGv t0; 4576 CHK_SV; 4577 4578 t0 = tcg_temp_new(); 4579 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4580 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4581 tcg_temp_free(t0); 4582 #endif /* defined(CONFIG_USER_ONLY) */ 4583 } 4584 4585 #if defined(TARGET_PPC64) 4586 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4587 4588 /* mfsr */ 4589 static void gen_mfsr_64b(DisasContext *ctx) 4590 { 4591 #if defined(CONFIG_USER_ONLY) 4592 GEN_PRIV; 4593 #else 4594 TCGv t0; 4595 4596 CHK_SV; 4597 t0 = tcg_const_tl(SR(ctx->opcode)); 4598 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4599 tcg_temp_free(t0); 4600 #endif /* defined(CONFIG_USER_ONLY) */ 4601 } 4602 4603 /* mfsrin */ 4604 static void gen_mfsrin_64b(DisasContext *ctx) 4605 { 4606 #if defined(CONFIG_USER_ONLY) 4607 GEN_PRIV; 4608 #else 4609 TCGv t0; 4610 4611 CHK_SV; 4612 t0 = tcg_temp_new(); 4613 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4614 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4615 tcg_temp_free(t0); 4616 #endif /* defined(CONFIG_USER_ONLY) */ 4617 } 4618 4619 /* mtsr */ 4620 static void gen_mtsr_64b(DisasContext *ctx) 4621 { 4622 #if defined(CONFIG_USER_ONLY) 4623 GEN_PRIV; 4624 #else 4625 TCGv t0; 4626 4627 CHK_SV; 4628 t0 = tcg_const_tl(SR(ctx->opcode)); 4629 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4630 tcg_temp_free(t0); 4631 #endif /* defined(CONFIG_USER_ONLY) */ 4632 } 4633 4634 /* mtsrin */ 4635 static void gen_mtsrin_64b(DisasContext *ctx) 4636 { 4637 #if defined(CONFIG_USER_ONLY) 4638 GEN_PRIV; 4639 #else 4640 TCGv t0; 4641 4642 CHK_SV; 4643 t0 = tcg_temp_new(); 4644 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4645 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4646 tcg_temp_free(t0); 4647 #endif /* defined(CONFIG_USER_ONLY) */ 4648 } 4649 4650 /* slbmte */ 4651 static void gen_slbmte(DisasContext *ctx) 4652 { 4653 #if defined(CONFIG_USER_ONLY) 4654 GEN_PRIV; 4655 #else 4656 CHK_SV; 4657 4658 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4659 cpu_gpr[rS(ctx->opcode)]); 4660 #endif /* defined(CONFIG_USER_ONLY) */ 4661 } 4662 4663 static void gen_slbmfee(DisasContext *ctx) 4664 { 4665 #if defined(CONFIG_USER_ONLY) 4666 GEN_PRIV; 4667 #else 4668 CHK_SV; 4669 4670 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4671 cpu_gpr[rB(ctx->opcode)]); 4672 #endif /* defined(CONFIG_USER_ONLY) */ 4673 } 4674 4675 static void gen_slbmfev(DisasContext *ctx) 4676 { 4677 #if defined(CONFIG_USER_ONLY) 4678 GEN_PRIV; 4679 #else 4680 CHK_SV; 4681 4682 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4683 cpu_gpr[rB(ctx->opcode)]); 4684 #endif /* defined(CONFIG_USER_ONLY) */ 4685 } 4686 4687 static void gen_slbfee_(DisasContext *ctx) 4688 { 4689 #if defined(CONFIG_USER_ONLY) 4690 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4691 #else 4692 TCGLabel *l1, *l2; 4693 4694 if (unlikely(ctx->pr)) { 4695 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4696 return; 4697 } 4698 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4699 cpu_gpr[rB(ctx->opcode)]); 4700 l1 = gen_new_label(); 4701 l2 = gen_new_label(); 4702 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4703 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4704 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4705 tcg_gen_br(l2); 4706 gen_set_label(l1); 4707 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4708 gen_set_label(l2); 4709 #endif 4710 } 4711 #endif /* defined(TARGET_PPC64) */ 4712 4713 /*** Lookaside buffer management ***/ 4714 /* Optional & supervisor only: */ 4715 4716 /* tlbia */ 4717 static void gen_tlbia(DisasContext *ctx) 4718 { 4719 #if defined(CONFIG_USER_ONLY) 4720 GEN_PRIV; 4721 #else 4722 CHK_HV; 4723 4724 gen_helper_tlbia(cpu_env); 4725 #endif /* defined(CONFIG_USER_ONLY) */ 4726 } 4727 4728 /* tlbiel */ 4729 static void gen_tlbiel(DisasContext *ctx) 4730 { 4731 #if defined(CONFIG_USER_ONLY) 4732 GEN_PRIV; 4733 #else 4734 CHK_SV; 4735 4736 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4737 #endif /* defined(CONFIG_USER_ONLY) */ 4738 } 4739 4740 /* tlbie */ 4741 static void gen_tlbie(DisasContext *ctx) 4742 { 4743 #if defined(CONFIG_USER_ONLY) 4744 GEN_PRIV; 4745 #else 4746 TCGv_i32 t1; 4747 4748 if (ctx->gtse) { 4749 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 4750 } else { 4751 CHK_HV; /* Else hypervisor privileged */ 4752 } 4753 4754 if (NARROW_MODE(ctx)) { 4755 TCGv t0 = tcg_temp_new(); 4756 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4757 gen_helper_tlbie(cpu_env, t0); 4758 tcg_temp_free(t0); 4759 } else { 4760 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4761 } 4762 t1 = tcg_temp_new_i32(); 4763 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4764 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4765 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4766 tcg_temp_free_i32(t1); 4767 #endif /* defined(CONFIG_USER_ONLY) */ 4768 } 4769 4770 /* tlbsync */ 4771 static void gen_tlbsync(DisasContext *ctx) 4772 { 4773 #if defined(CONFIG_USER_ONLY) 4774 GEN_PRIV; 4775 #else 4776 4777 if (ctx->gtse) { 4778 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 4779 } else { 4780 CHK_HV; /* Else hypervisor privileged */ 4781 } 4782 4783 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4784 if (ctx->insns_flags & PPC_BOOKE) { 4785 gen_check_tlb_flush(ctx, true); 4786 } 4787 #endif /* defined(CONFIG_USER_ONLY) */ 4788 } 4789 4790 #if defined(TARGET_PPC64) 4791 /* slbia */ 4792 static void gen_slbia(DisasContext *ctx) 4793 { 4794 #if defined(CONFIG_USER_ONLY) 4795 GEN_PRIV; 4796 #else 4797 CHK_SV; 4798 4799 gen_helper_slbia(cpu_env); 4800 #endif /* defined(CONFIG_USER_ONLY) */ 4801 } 4802 4803 /* slbie */ 4804 static void gen_slbie(DisasContext *ctx) 4805 { 4806 #if defined(CONFIG_USER_ONLY) 4807 GEN_PRIV; 4808 #else 4809 CHK_SV; 4810 4811 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4812 #endif /* defined(CONFIG_USER_ONLY) */ 4813 } 4814 4815 /* slbieg */ 4816 static void gen_slbieg(DisasContext *ctx) 4817 { 4818 #if defined(CONFIG_USER_ONLY) 4819 GEN_PRIV; 4820 #else 4821 CHK_SV; 4822 4823 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4824 #endif /* defined(CONFIG_USER_ONLY) */ 4825 } 4826 4827 /* slbsync */ 4828 static void gen_slbsync(DisasContext *ctx) 4829 { 4830 #if defined(CONFIG_USER_ONLY) 4831 GEN_PRIV; 4832 #else 4833 CHK_SV; 4834 gen_check_tlb_flush(ctx, true); 4835 #endif /* defined(CONFIG_USER_ONLY) */ 4836 } 4837 4838 #endif /* defined(TARGET_PPC64) */ 4839 4840 /*** External control ***/ 4841 /* Optional: */ 4842 4843 /* eciwx */ 4844 static void gen_eciwx(DisasContext *ctx) 4845 { 4846 TCGv t0; 4847 /* Should check EAR[E] ! */ 4848 gen_set_access_type(ctx, ACCESS_EXT); 4849 t0 = tcg_temp_new(); 4850 gen_addr_reg_index(ctx, t0); 4851 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4852 DEF_MEMOP(MO_UL | MO_ALIGN)); 4853 tcg_temp_free(t0); 4854 } 4855 4856 /* ecowx */ 4857 static void gen_ecowx(DisasContext *ctx) 4858 { 4859 TCGv t0; 4860 /* Should check EAR[E] ! */ 4861 gen_set_access_type(ctx, ACCESS_EXT); 4862 t0 = tcg_temp_new(); 4863 gen_addr_reg_index(ctx, t0); 4864 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4865 DEF_MEMOP(MO_UL | MO_ALIGN)); 4866 tcg_temp_free(t0); 4867 } 4868 4869 /* PowerPC 601 specific instructions */ 4870 4871 /* abs - abs. */ 4872 static void gen_abs(DisasContext *ctx) 4873 { 4874 TCGLabel *l1 = gen_new_label(); 4875 TCGLabel *l2 = gen_new_label(); 4876 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); 4877 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4878 tcg_gen_br(l2); 4879 gen_set_label(l1); 4880 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4881 gen_set_label(l2); 4882 if (unlikely(Rc(ctx->opcode) != 0)) 4883 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4884 } 4885 4886 /* abso - abso. */ 4887 static void gen_abso(DisasContext *ctx) 4888 { 4889 TCGLabel *l1 = gen_new_label(); 4890 TCGLabel *l2 = gen_new_label(); 4891 TCGLabel *l3 = gen_new_label(); 4892 /* Start with XER OV disabled, the most likely case */ 4893 tcg_gen_movi_tl(cpu_ov, 0); 4894 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); 4895 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); 4896 tcg_gen_movi_tl(cpu_ov, 1); 4897 tcg_gen_movi_tl(cpu_so, 1); 4898 tcg_gen_br(l2); 4899 gen_set_label(l1); 4900 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4901 tcg_gen_br(l3); 4902 gen_set_label(l2); 4903 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4904 gen_set_label(l3); 4905 if (unlikely(Rc(ctx->opcode) != 0)) 4906 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4907 } 4908 4909 /* clcs */ 4910 static void gen_clcs(DisasContext *ctx) 4911 { 4912 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 4913 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4914 tcg_temp_free_i32(t0); 4915 /* Rc=1 sets CR0 to an undefined state */ 4916 } 4917 4918 /* div - div. */ 4919 static void gen_div(DisasContext *ctx) 4920 { 4921 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4922 cpu_gpr[rB(ctx->opcode)]); 4923 if (unlikely(Rc(ctx->opcode) != 0)) 4924 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4925 } 4926 4927 /* divo - divo. */ 4928 static void gen_divo(DisasContext *ctx) 4929 { 4930 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4931 cpu_gpr[rB(ctx->opcode)]); 4932 if (unlikely(Rc(ctx->opcode) != 0)) 4933 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4934 } 4935 4936 /* divs - divs. */ 4937 static void gen_divs(DisasContext *ctx) 4938 { 4939 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4940 cpu_gpr[rB(ctx->opcode)]); 4941 if (unlikely(Rc(ctx->opcode) != 0)) 4942 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4943 } 4944 4945 /* divso - divso. */ 4946 static void gen_divso(DisasContext *ctx) 4947 { 4948 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 4949 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4950 if (unlikely(Rc(ctx->opcode) != 0)) 4951 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4952 } 4953 4954 /* doz - doz. */ 4955 static void gen_doz(DisasContext *ctx) 4956 { 4957 TCGLabel *l1 = gen_new_label(); 4958 TCGLabel *l2 = gen_new_label(); 4959 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4960 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4961 tcg_gen_br(l2); 4962 gen_set_label(l1); 4963 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4964 gen_set_label(l2); 4965 if (unlikely(Rc(ctx->opcode) != 0)) 4966 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4967 } 4968 4969 /* dozo - dozo. */ 4970 static void gen_dozo(DisasContext *ctx) 4971 { 4972 TCGLabel *l1 = gen_new_label(); 4973 TCGLabel *l2 = gen_new_label(); 4974 TCGv t0 = tcg_temp_new(); 4975 TCGv t1 = tcg_temp_new(); 4976 TCGv t2 = tcg_temp_new(); 4977 /* Start with XER OV disabled, the most likely case */ 4978 tcg_gen_movi_tl(cpu_ov, 0); 4979 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4980 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4981 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4982 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 4983 tcg_gen_andc_tl(t1, t1, t2); 4984 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 4985 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 4986 tcg_gen_movi_tl(cpu_ov, 1); 4987 tcg_gen_movi_tl(cpu_so, 1); 4988 tcg_gen_br(l2); 4989 gen_set_label(l1); 4990 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4991 gen_set_label(l2); 4992 tcg_temp_free(t0); 4993 tcg_temp_free(t1); 4994 tcg_temp_free(t2); 4995 if (unlikely(Rc(ctx->opcode) != 0)) 4996 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4997 } 4998 4999 /* dozi */ 5000 static void gen_dozi(DisasContext *ctx) 5001 { 5002 target_long simm = SIMM(ctx->opcode); 5003 TCGLabel *l1 = gen_new_label(); 5004 TCGLabel *l2 = gen_new_label(); 5005 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5006 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5007 tcg_gen_br(l2); 5008 gen_set_label(l1); 5009 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5010 gen_set_label(l2); 5011 if (unlikely(Rc(ctx->opcode) != 0)) 5012 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5013 } 5014 5015 /* lscbx - lscbx. */ 5016 static void gen_lscbx(DisasContext *ctx) 5017 { 5018 TCGv t0 = tcg_temp_new(); 5019 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5020 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5021 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5022 5023 gen_addr_reg_index(ctx, t0); 5024 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5025 tcg_temp_free_i32(t1); 5026 tcg_temp_free_i32(t2); 5027 tcg_temp_free_i32(t3); 5028 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5029 tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5030 if (unlikely(Rc(ctx->opcode) != 0)) 5031 gen_set_Rc0(ctx, t0); 5032 tcg_temp_free(t0); 5033 } 5034 5035 /* maskg - maskg. */ 5036 static void gen_maskg(DisasContext *ctx) 5037 { 5038 TCGLabel *l1 = gen_new_label(); 5039 TCGv t0 = tcg_temp_new(); 5040 TCGv t1 = tcg_temp_new(); 5041 TCGv t2 = tcg_temp_new(); 5042 TCGv t3 = tcg_temp_new(); 5043 tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5044 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5045 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5046 tcg_gen_addi_tl(t2, t0, 1); 5047 tcg_gen_shr_tl(t2, t3, t2); 5048 tcg_gen_shr_tl(t3, t3, t1); 5049 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5050 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5051 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5052 gen_set_label(l1); 5053 tcg_temp_free(t0); 5054 tcg_temp_free(t1); 5055 tcg_temp_free(t2); 5056 tcg_temp_free(t3); 5057 if (unlikely(Rc(ctx->opcode) != 0)) 5058 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5059 } 5060 5061 /* maskir - maskir. */ 5062 static void gen_maskir(DisasContext *ctx) 5063 { 5064 TCGv t0 = tcg_temp_new(); 5065 TCGv t1 = tcg_temp_new(); 5066 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5067 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5068 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5069 tcg_temp_free(t0); 5070 tcg_temp_free(t1); 5071 if (unlikely(Rc(ctx->opcode) != 0)) 5072 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5073 } 5074 5075 /* mul - mul. */ 5076 static void gen_mul(DisasContext *ctx) 5077 { 5078 TCGv_i64 t0 = tcg_temp_new_i64(); 5079 TCGv_i64 t1 = tcg_temp_new_i64(); 5080 TCGv t2 = tcg_temp_new(); 5081 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5082 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5083 tcg_gen_mul_i64(t0, t0, t1); 5084 tcg_gen_trunc_i64_tl(t2, t0); 5085 gen_store_spr(SPR_MQ, t2); 5086 tcg_gen_shri_i64(t1, t0, 32); 5087 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5088 tcg_temp_free_i64(t0); 5089 tcg_temp_free_i64(t1); 5090 tcg_temp_free(t2); 5091 if (unlikely(Rc(ctx->opcode) != 0)) 5092 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5093 } 5094 5095 /* mulo - mulo. */ 5096 static void gen_mulo(DisasContext *ctx) 5097 { 5098 TCGLabel *l1 = gen_new_label(); 5099 TCGv_i64 t0 = tcg_temp_new_i64(); 5100 TCGv_i64 t1 = tcg_temp_new_i64(); 5101 TCGv t2 = tcg_temp_new(); 5102 /* Start with XER OV disabled, the most likely case */ 5103 tcg_gen_movi_tl(cpu_ov, 0); 5104 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5105 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5106 tcg_gen_mul_i64(t0, t0, t1); 5107 tcg_gen_trunc_i64_tl(t2, t0); 5108 gen_store_spr(SPR_MQ, t2); 5109 tcg_gen_shri_i64(t1, t0, 32); 5110 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5111 tcg_gen_ext32s_i64(t1, t0); 5112 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5113 tcg_gen_movi_tl(cpu_ov, 1); 5114 tcg_gen_movi_tl(cpu_so, 1); 5115 gen_set_label(l1); 5116 tcg_temp_free_i64(t0); 5117 tcg_temp_free_i64(t1); 5118 tcg_temp_free(t2); 5119 if (unlikely(Rc(ctx->opcode) != 0)) 5120 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5121 } 5122 5123 /* nabs - nabs. */ 5124 static void gen_nabs(DisasContext *ctx) 5125 { 5126 TCGLabel *l1 = gen_new_label(); 5127 TCGLabel *l2 = gen_new_label(); 5128 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 5129 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5130 tcg_gen_br(l2); 5131 gen_set_label(l1); 5132 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5133 gen_set_label(l2); 5134 if (unlikely(Rc(ctx->opcode) != 0)) 5135 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5136 } 5137 5138 /* nabso - nabso. */ 5139 static void gen_nabso(DisasContext *ctx) 5140 { 5141 TCGLabel *l1 = gen_new_label(); 5142 TCGLabel *l2 = gen_new_label(); 5143 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 5144 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5145 tcg_gen_br(l2); 5146 gen_set_label(l1); 5147 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5148 gen_set_label(l2); 5149 /* nabs never overflows */ 5150 tcg_gen_movi_tl(cpu_ov, 0); 5151 if (unlikely(Rc(ctx->opcode) != 0)) 5152 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5153 } 5154 5155 /* rlmi - rlmi. */ 5156 static void gen_rlmi(DisasContext *ctx) 5157 { 5158 uint32_t mb = MB(ctx->opcode); 5159 uint32_t me = ME(ctx->opcode); 5160 TCGv t0 = tcg_temp_new(); 5161 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5162 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5163 tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5164 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); 5165 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5166 tcg_temp_free(t0); 5167 if (unlikely(Rc(ctx->opcode) != 0)) 5168 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5169 } 5170 5171 /* rrib - rrib. */ 5172 static void gen_rrib(DisasContext *ctx) 5173 { 5174 TCGv t0 = tcg_temp_new(); 5175 TCGv t1 = tcg_temp_new(); 5176 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5177 tcg_gen_movi_tl(t1, 0x80000000); 5178 tcg_gen_shr_tl(t1, t1, t0); 5179 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5180 tcg_gen_and_tl(t0, t0, t1); 5181 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5182 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5183 tcg_temp_free(t0); 5184 tcg_temp_free(t1); 5185 if (unlikely(Rc(ctx->opcode) != 0)) 5186 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5187 } 5188 5189 /* sle - sle. */ 5190 static void gen_sle(DisasContext *ctx) 5191 { 5192 TCGv t0 = tcg_temp_new(); 5193 TCGv t1 = tcg_temp_new(); 5194 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5195 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5196 tcg_gen_subfi_tl(t1, 32, t1); 5197 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5198 tcg_gen_or_tl(t1, t0, t1); 5199 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5200 gen_store_spr(SPR_MQ, t1); 5201 tcg_temp_free(t0); 5202 tcg_temp_free(t1); 5203 if (unlikely(Rc(ctx->opcode) != 0)) 5204 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5205 } 5206 5207 /* sleq - sleq. */ 5208 static void gen_sleq(DisasContext *ctx) 5209 { 5210 TCGv t0 = tcg_temp_new(); 5211 TCGv t1 = tcg_temp_new(); 5212 TCGv t2 = tcg_temp_new(); 5213 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5214 tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5215 tcg_gen_shl_tl(t2, t2, t0); 5216 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5217 gen_load_spr(t1, SPR_MQ); 5218 gen_store_spr(SPR_MQ, t0); 5219 tcg_gen_and_tl(t0, t0, t2); 5220 tcg_gen_andc_tl(t1, t1, t2); 5221 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5222 tcg_temp_free(t0); 5223 tcg_temp_free(t1); 5224 tcg_temp_free(t2); 5225 if (unlikely(Rc(ctx->opcode) != 0)) 5226 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5227 } 5228 5229 /* sliq - sliq. */ 5230 static void gen_sliq(DisasContext *ctx) 5231 { 5232 int sh = SH(ctx->opcode); 5233 TCGv t0 = tcg_temp_new(); 5234 TCGv t1 = tcg_temp_new(); 5235 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5236 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5237 tcg_gen_or_tl(t1, t0, t1); 5238 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5239 gen_store_spr(SPR_MQ, t1); 5240 tcg_temp_free(t0); 5241 tcg_temp_free(t1); 5242 if (unlikely(Rc(ctx->opcode) != 0)) 5243 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5244 } 5245 5246 /* slliq - slliq. */ 5247 static void gen_slliq(DisasContext *ctx) 5248 { 5249 int sh = SH(ctx->opcode); 5250 TCGv t0 = tcg_temp_new(); 5251 TCGv t1 = tcg_temp_new(); 5252 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5253 gen_load_spr(t1, SPR_MQ); 5254 gen_store_spr(SPR_MQ, t0); 5255 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5256 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5257 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5258 tcg_temp_free(t0); 5259 tcg_temp_free(t1); 5260 if (unlikely(Rc(ctx->opcode) != 0)) 5261 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5262 } 5263 5264 /* sllq - sllq. */ 5265 static void gen_sllq(DisasContext *ctx) 5266 { 5267 TCGLabel *l1 = gen_new_label(); 5268 TCGLabel *l2 = gen_new_label(); 5269 TCGv t0 = tcg_temp_local_new(); 5270 TCGv t1 = tcg_temp_local_new(); 5271 TCGv t2 = tcg_temp_local_new(); 5272 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5273 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5274 tcg_gen_shl_tl(t1, t1, t2); 5275 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5276 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5277 gen_load_spr(t0, SPR_MQ); 5278 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5279 tcg_gen_br(l2); 5280 gen_set_label(l1); 5281 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5282 gen_load_spr(t2, SPR_MQ); 5283 tcg_gen_andc_tl(t1, t2, t1); 5284 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5285 gen_set_label(l2); 5286 tcg_temp_free(t0); 5287 tcg_temp_free(t1); 5288 tcg_temp_free(t2); 5289 if (unlikely(Rc(ctx->opcode) != 0)) 5290 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5291 } 5292 5293 /* slq - slq. */ 5294 static void gen_slq(DisasContext *ctx) 5295 { 5296 TCGLabel *l1 = gen_new_label(); 5297 TCGv t0 = tcg_temp_new(); 5298 TCGv t1 = tcg_temp_new(); 5299 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5300 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5301 tcg_gen_subfi_tl(t1, 32, t1); 5302 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5303 tcg_gen_or_tl(t1, t0, t1); 5304 gen_store_spr(SPR_MQ, t1); 5305 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5306 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5307 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5308 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5309 gen_set_label(l1); 5310 tcg_temp_free(t0); 5311 tcg_temp_free(t1); 5312 if (unlikely(Rc(ctx->opcode) != 0)) 5313 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5314 } 5315 5316 /* sraiq - sraiq. */ 5317 static void gen_sraiq(DisasContext *ctx) 5318 { 5319 int sh = SH(ctx->opcode); 5320 TCGLabel *l1 = gen_new_label(); 5321 TCGv t0 = tcg_temp_new(); 5322 TCGv t1 = tcg_temp_new(); 5323 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5324 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5325 tcg_gen_or_tl(t0, t0, t1); 5326 gen_store_spr(SPR_MQ, t0); 5327 tcg_gen_movi_tl(cpu_ca, 0); 5328 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5329 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5330 tcg_gen_movi_tl(cpu_ca, 1); 5331 gen_set_label(l1); 5332 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5333 tcg_temp_free(t0); 5334 tcg_temp_free(t1); 5335 if (unlikely(Rc(ctx->opcode) != 0)) 5336 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5337 } 5338 5339 /* sraq - sraq. */ 5340 static void gen_sraq(DisasContext *ctx) 5341 { 5342 TCGLabel *l1 = gen_new_label(); 5343 TCGLabel *l2 = gen_new_label(); 5344 TCGv t0 = tcg_temp_new(); 5345 TCGv t1 = tcg_temp_local_new(); 5346 TCGv t2 = tcg_temp_local_new(); 5347 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5348 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5349 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5350 tcg_gen_subfi_tl(t2, 32, t2); 5351 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5352 tcg_gen_or_tl(t0, t0, t2); 5353 gen_store_spr(SPR_MQ, t0); 5354 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5355 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5356 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5357 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5358 gen_set_label(l1); 5359 tcg_temp_free(t0); 5360 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5361 tcg_gen_movi_tl(cpu_ca, 0); 5362 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5363 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5364 tcg_gen_movi_tl(cpu_ca, 1); 5365 gen_set_label(l2); 5366 tcg_temp_free(t1); 5367 tcg_temp_free(t2); 5368 if (unlikely(Rc(ctx->opcode) != 0)) 5369 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5370 } 5371 5372 /* sre - sre. */ 5373 static void gen_sre(DisasContext *ctx) 5374 { 5375 TCGv t0 = tcg_temp_new(); 5376 TCGv t1 = tcg_temp_new(); 5377 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5378 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5379 tcg_gen_subfi_tl(t1, 32, t1); 5380 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5381 tcg_gen_or_tl(t1, t0, t1); 5382 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5383 gen_store_spr(SPR_MQ, t1); 5384 tcg_temp_free(t0); 5385 tcg_temp_free(t1); 5386 if (unlikely(Rc(ctx->opcode) != 0)) 5387 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5388 } 5389 5390 /* srea - srea. */ 5391 static void gen_srea(DisasContext *ctx) 5392 { 5393 TCGv t0 = tcg_temp_new(); 5394 TCGv t1 = tcg_temp_new(); 5395 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5396 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5397 gen_store_spr(SPR_MQ, t0); 5398 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5399 tcg_temp_free(t0); 5400 tcg_temp_free(t1); 5401 if (unlikely(Rc(ctx->opcode) != 0)) 5402 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5403 } 5404 5405 /* sreq */ 5406 static void gen_sreq(DisasContext *ctx) 5407 { 5408 TCGv t0 = tcg_temp_new(); 5409 TCGv t1 = tcg_temp_new(); 5410 TCGv t2 = tcg_temp_new(); 5411 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5412 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5413 tcg_gen_shr_tl(t1, t1, t0); 5414 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5415 gen_load_spr(t2, SPR_MQ); 5416 gen_store_spr(SPR_MQ, t0); 5417 tcg_gen_and_tl(t0, t0, t1); 5418 tcg_gen_andc_tl(t2, t2, t1); 5419 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5420 tcg_temp_free(t0); 5421 tcg_temp_free(t1); 5422 tcg_temp_free(t2); 5423 if (unlikely(Rc(ctx->opcode) != 0)) 5424 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5425 } 5426 5427 /* sriq */ 5428 static void gen_sriq(DisasContext *ctx) 5429 { 5430 int sh = SH(ctx->opcode); 5431 TCGv t0 = tcg_temp_new(); 5432 TCGv t1 = tcg_temp_new(); 5433 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5434 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5435 tcg_gen_or_tl(t1, t0, t1); 5436 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5437 gen_store_spr(SPR_MQ, t1); 5438 tcg_temp_free(t0); 5439 tcg_temp_free(t1); 5440 if (unlikely(Rc(ctx->opcode) != 0)) 5441 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5442 } 5443 5444 /* srliq */ 5445 static void gen_srliq(DisasContext *ctx) 5446 { 5447 int sh = SH(ctx->opcode); 5448 TCGv t0 = tcg_temp_new(); 5449 TCGv t1 = tcg_temp_new(); 5450 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5451 gen_load_spr(t1, SPR_MQ); 5452 gen_store_spr(SPR_MQ, t0); 5453 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5454 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5455 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5456 tcg_temp_free(t0); 5457 tcg_temp_free(t1); 5458 if (unlikely(Rc(ctx->opcode) != 0)) 5459 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5460 } 5461 5462 /* srlq */ 5463 static void gen_srlq(DisasContext *ctx) 5464 { 5465 TCGLabel *l1 = gen_new_label(); 5466 TCGLabel *l2 = gen_new_label(); 5467 TCGv t0 = tcg_temp_local_new(); 5468 TCGv t1 = tcg_temp_local_new(); 5469 TCGv t2 = tcg_temp_local_new(); 5470 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5471 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5472 tcg_gen_shr_tl(t2, t1, t2); 5473 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5474 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5475 gen_load_spr(t0, SPR_MQ); 5476 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5477 tcg_gen_br(l2); 5478 gen_set_label(l1); 5479 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5480 tcg_gen_and_tl(t0, t0, t2); 5481 gen_load_spr(t1, SPR_MQ); 5482 tcg_gen_andc_tl(t1, t1, t2); 5483 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5484 gen_set_label(l2); 5485 tcg_temp_free(t0); 5486 tcg_temp_free(t1); 5487 tcg_temp_free(t2); 5488 if (unlikely(Rc(ctx->opcode) != 0)) 5489 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5490 } 5491 5492 /* srq */ 5493 static void gen_srq(DisasContext *ctx) 5494 { 5495 TCGLabel *l1 = gen_new_label(); 5496 TCGv t0 = tcg_temp_new(); 5497 TCGv t1 = tcg_temp_new(); 5498 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5499 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5500 tcg_gen_subfi_tl(t1, 32, t1); 5501 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5502 tcg_gen_or_tl(t1, t0, t1); 5503 gen_store_spr(SPR_MQ, t1); 5504 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5505 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5506 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5507 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5508 gen_set_label(l1); 5509 tcg_temp_free(t0); 5510 tcg_temp_free(t1); 5511 if (unlikely(Rc(ctx->opcode) != 0)) 5512 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5513 } 5514 5515 /* PowerPC 602 specific instructions */ 5516 5517 /* dsa */ 5518 static void gen_dsa(DisasContext *ctx) 5519 { 5520 /* XXX: TODO */ 5521 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5522 } 5523 5524 /* esa */ 5525 static void gen_esa(DisasContext *ctx) 5526 { 5527 /* XXX: TODO */ 5528 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5529 } 5530 5531 /* mfrom */ 5532 static void gen_mfrom(DisasContext *ctx) 5533 { 5534 #if defined(CONFIG_USER_ONLY) 5535 GEN_PRIV; 5536 #else 5537 CHK_SV; 5538 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5539 #endif /* defined(CONFIG_USER_ONLY) */ 5540 } 5541 5542 /* 602 - 603 - G2 TLB management */ 5543 5544 /* tlbld */ 5545 static void gen_tlbld_6xx(DisasContext *ctx) 5546 { 5547 #if defined(CONFIG_USER_ONLY) 5548 GEN_PRIV; 5549 #else 5550 CHK_SV; 5551 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5552 #endif /* defined(CONFIG_USER_ONLY) */ 5553 } 5554 5555 /* tlbli */ 5556 static void gen_tlbli_6xx(DisasContext *ctx) 5557 { 5558 #if defined(CONFIG_USER_ONLY) 5559 GEN_PRIV; 5560 #else 5561 CHK_SV; 5562 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5563 #endif /* defined(CONFIG_USER_ONLY) */ 5564 } 5565 5566 /* 74xx TLB management */ 5567 5568 /* tlbld */ 5569 static void gen_tlbld_74xx(DisasContext *ctx) 5570 { 5571 #if defined(CONFIG_USER_ONLY) 5572 GEN_PRIV; 5573 #else 5574 CHK_SV; 5575 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5576 #endif /* defined(CONFIG_USER_ONLY) */ 5577 } 5578 5579 /* tlbli */ 5580 static void gen_tlbli_74xx(DisasContext *ctx) 5581 { 5582 #if defined(CONFIG_USER_ONLY) 5583 GEN_PRIV; 5584 #else 5585 CHK_SV; 5586 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5587 #endif /* defined(CONFIG_USER_ONLY) */ 5588 } 5589 5590 /* POWER instructions not in PowerPC 601 */ 5591 5592 /* clf */ 5593 static void gen_clf(DisasContext *ctx) 5594 { 5595 /* Cache line flush: implemented as no-op */ 5596 } 5597 5598 /* cli */ 5599 static void gen_cli(DisasContext *ctx) 5600 { 5601 #if defined(CONFIG_USER_ONLY) 5602 GEN_PRIV; 5603 #else 5604 /* Cache line invalidate: privileged and treated as no-op */ 5605 CHK_SV; 5606 #endif /* defined(CONFIG_USER_ONLY) */ 5607 } 5608 5609 /* dclst */ 5610 static void gen_dclst(DisasContext *ctx) 5611 { 5612 /* Data cache line store: treated as no-op */ 5613 } 5614 5615 static void gen_mfsri(DisasContext *ctx) 5616 { 5617 #if defined(CONFIG_USER_ONLY) 5618 GEN_PRIV; 5619 #else 5620 int ra = rA(ctx->opcode); 5621 int rd = rD(ctx->opcode); 5622 TCGv t0; 5623 5624 CHK_SV; 5625 t0 = tcg_temp_new(); 5626 gen_addr_reg_index(ctx, t0); 5627 tcg_gen_extract_tl(t0, t0, 28, 4); 5628 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5629 tcg_temp_free(t0); 5630 if (ra != 0 && ra != rd) 5631 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5632 #endif /* defined(CONFIG_USER_ONLY) */ 5633 } 5634 5635 static void gen_rac(DisasContext *ctx) 5636 { 5637 #if defined(CONFIG_USER_ONLY) 5638 GEN_PRIV; 5639 #else 5640 TCGv t0; 5641 5642 CHK_SV; 5643 t0 = tcg_temp_new(); 5644 gen_addr_reg_index(ctx, t0); 5645 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5646 tcg_temp_free(t0); 5647 #endif /* defined(CONFIG_USER_ONLY) */ 5648 } 5649 5650 static void gen_rfsvc(DisasContext *ctx) 5651 { 5652 #if defined(CONFIG_USER_ONLY) 5653 GEN_PRIV; 5654 #else 5655 CHK_SV; 5656 5657 gen_helper_rfsvc(cpu_env); 5658 gen_sync_exception(ctx); 5659 #endif /* defined(CONFIG_USER_ONLY) */ 5660 } 5661 5662 /* svc is not implemented for now */ 5663 5664 /* BookE specific instructions */ 5665 5666 /* XXX: not implemented on 440 ? */ 5667 static void gen_mfapidi(DisasContext *ctx) 5668 { 5669 /* XXX: TODO */ 5670 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5671 } 5672 5673 /* XXX: not implemented on 440 ? */ 5674 static void gen_tlbiva(DisasContext *ctx) 5675 { 5676 #if defined(CONFIG_USER_ONLY) 5677 GEN_PRIV; 5678 #else 5679 TCGv t0; 5680 5681 CHK_SV; 5682 t0 = tcg_temp_new(); 5683 gen_addr_reg_index(ctx, t0); 5684 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5685 tcg_temp_free(t0); 5686 #endif /* defined(CONFIG_USER_ONLY) */ 5687 } 5688 5689 /* All 405 MAC instructions are translated here */ 5690 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5691 int ra, int rb, int rt, int Rc) 5692 { 5693 TCGv t0, t1; 5694 5695 t0 = tcg_temp_local_new(); 5696 t1 = tcg_temp_local_new(); 5697 5698 switch (opc3 & 0x0D) { 5699 case 0x05: 5700 /* macchw - macchw. - macchwo - macchwo. */ 5701 /* macchws - macchws. - macchwso - macchwso. */ 5702 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5703 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5704 /* mulchw - mulchw. */ 5705 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5706 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5707 tcg_gen_ext16s_tl(t1, t1); 5708 break; 5709 case 0x04: 5710 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5711 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5712 /* mulchwu - mulchwu. */ 5713 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5714 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5715 tcg_gen_ext16u_tl(t1, t1); 5716 break; 5717 case 0x01: 5718 /* machhw - machhw. - machhwo - machhwo. */ 5719 /* machhws - machhws. - machhwso - machhwso. */ 5720 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5721 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5722 /* mulhhw - mulhhw. */ 5723 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5724 tcg_gen_ext16s_tl(t0, t0); 5725 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5726 tcg_gen_ext16s_tl(t1, t1); 5727 break; 5728 case 0x00: 5729 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5730 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5731 /* mulhhwu - mulhhwu. */ 5732 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5733 tcg_gen_ext16u_tl(t0, t0); 5734 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5735 tcg_gen_ext16u_tl(t1, t1); 5736 break; 5737 case 0x0D: 5738 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5739 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5740 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5741 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5742 /* mullhw - mullhw. */ 5743 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5744 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5745 break; 5746 case 0x0C: 5747 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5748 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5749 /* mullhwu - mullhwu. */ 5750 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5751 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5752 break; 5753 } 5754 if (opc2 & 0x04) { 5755 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5756 tcg_gen_mul_tl(t1, t0, t1); 5757 if (opc2 & 0x02) { 5758 /* nmultiply-and-accumulate (0x0E) */ 5759 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5760 } else { 5761 /* multiply-and-accumulate (0x0C) */ 5762 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5763 } 5764 5765 if (opc3 & 0x12) { 5766 /* Check overflow and/or saturate */ 5767 TCGLabel *l1 = gen_new_label(); 5768 5769 if (opc3 & 0x10) { 5770 /* Start with XER OV disabled, the most likely case */ 5771 tcg_gen_movi_tl(cpu_ov, 0); 5772 } 5773 if (opc3 & 0x01) { 5774 /* Signed */ 5775 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5776 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5777 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5778 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5779 if (opc3 & 0x02) { 5780 /* Saturate */ 5781 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5782 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5783 } 5784 } else { 5785 /* Unsigned */ 5786 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5787 if (opc3 & 0x02) { 5788 /* Saturate */ 5789 tcg_gen_movi_tl(t0, UINT32_MAX); 5790 } 5791 } 5792 if (opc3 & 0x10) { 5793 /* Check overflow */ 5794 tcg_gen_movi_tl(cpu_ov, 1); 5795 tcg_gen_movi_tl(cpu_so, 1); 5796 } 5797 gen_set_label(l1); 5798 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5799 } 5800 } else { 5801 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5802 } 5803 tcg_temp_free(t0); 5804 tcg_temp_free(t1); 5805 if (unlikely(Rc) != 0) { 5806 /* Update Rc0 */ 5807 gen_set_Rc0(ctx, cpu_gpr[rt]); 5808 } 5809 } 5810 5811 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5812 static void glue(gen_, name)(DisasContext *ctx) \ 5813 { \ 5814 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5815 rD(ctx->opcode), Rc(ctx->opcode)); \ 5816 } 5817 5818 /* macchw - macchw. */ 5819 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5820 /* macchwo - macchwo. */ 5821 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5822 /* macchws - macchws. */ 5823 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5824 /* macchwso - macchwso. */ 5825 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5826 /* macchwsu - macchwsu. */ 5827 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5828 /* macchwsuo - macchwsuo. */ 5829 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5830 /* macchwu - macchwu. */ 5831 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5832 /* macchwuo - macchwuo. */ 5833 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5834 /* machhw - machhw. */ 5835 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5836 /* machhwo - machhwo. */ 5837 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5838 /* machhws - machhws. */ 5839 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5840 /* machhwso - machhwso. */ 5841 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5842 /* machhwsu - machhwsu. */ 5843 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5844 /* machhwsuo - machhwsuo. */ 5845 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5846 /* machhwu - machhwu. */ 5847 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5848 /* machhwuo - machhwuo. */ 5849 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5850 /* maclhw - maclhw. */ 5851 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5852 /* maclhwo - maclhwo. */ 5853 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5854 /* maclhws - maclhws. */ 5855 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5856 /* maclhwso - maclhwso. */ 5857 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5858 /* maclhwu - maclhwu. */ 5859 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5860 /* maclhwuo - maclhwuo. */ 5861 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5862 /* maclhwsu - maclhwsu. */ 5863 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5864 /* maclhwsuo - maclhwsuo. */ 5865 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5866 /* nmacchw - nmacchw. */ 5867 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5868 /* nmacchwo - nmacchwo. */ 5869 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5870 /* nmacchws - nmacchws. */ 5871 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5872 /* nmacchwso - nmacchwso. */ 5873 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5874 /* nmachhw - nmachhw. */ 5875 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5876 /* nmachhwo - nmachhwo. */ 5877 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5878 /* nmachhws - nmachhws. */ 5879 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5880 /* nmachhwso - nmachhwso. */ 5881 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5882 /* nmaclhw - nmaclhw. */ 5883 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5884 /* nmaclhwo - nmaclhwo. */ 5885 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5886 /* nmaclhws - nmaclhws. */ 5887 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5888 /* nmaclhwso - nmaclhwso. */ 5889 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5890 5891 /* mulchw - mulchw. */ 5892 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5893 /* mulchwu - mulchwu. */ 5894 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5895 /* mulhhw - mulhhw. */ 5896 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5897 /* mulhhwu - mulhhwu. */ 5898 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5899 /* mullhw - mullhw. */ 5900 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5901 /* mullhwu - mullhwu. */ 5902 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5903 5904 /* mfdcr */ 5905 static void gen_mfdcr(DisasContext *ctx) 5906 { 5907 #if defined(CONFIG_USER_ONLY) 5908 GEN_PRIV; 5909 #else 5910 TCGv dcrn; 5911 5912 CHK_SV; 5913 dcrn = tcg_const_tl(SPR(ctx->opcode)); 5914 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5915 tcg_temp_free(dcrn); 5916 #endif /* defined(CONFIG_USER_ONLY) */ 5917 } 5918 5919 /* mtdcr */ 5920 static void gen_mtdcr(DisasContext *ctx) 5921 { 5922 #if defined(CONFIG_USER_ONLY) 5923 GEN_PRIV; 5924 #else 5925 TCGv dcrn; 5926 5927 CHK_SV; 5928 dcrn = tcg_const_tl(SPR(ctx->opcode)); 5929 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5930 tcg_temp_free(dcrn); 5931 #endif /* defined(CONFIG_USER_ONLY) */ 5932 } 5933 5934 /* mfdcrx */ 5935 /* XXX: not implemented on 440 ? */ 5936 static void gen_mfdcrx(DisasContext *ctx) 5937 { 5938 #if defined(CONFIG_USER_ONLY) 5939 GEN_PRIV; 5940 #else 5941 CHK_SV; 5942 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5943 cpu_gpr[rA(ctx->opcode)]); 5944 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5945 #endif /* defined(CONFIG_USER_ONLY) */ 5946 } 5947 5948 /* mtdcrx */ 5949 /* XXX: not implemented on 440 ? */ 5950 static void gen_mtdcrx(DisasContext *ctx) 5951 { 5952 #if defined(CONFIG_USER_ONLY) 5953 GEN_PRIV; 5954 #else 5955 CHK_SV; 5956 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5957 cpu_gpr[rS(ctx->opcode)]); 5958 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5959 #endif /* defined(CONFIG_USER_ONLY) */ 5960 } 5961 5962 /* mfdcrux (PPC 460) : user-mode access to DCR */ 5963 static void gen_mfdcrux(DisasContext *ctx) 5964 { 5965 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5966 cpu_gpr[rA(ctx->opcode)]); 5967 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5968 } 5969 5970 /* mtdcrux (PPC 460) : user-mode access to DCR */ 5971 static void gen_mtdcrux(DisasContext *ctx) 5972 { 5973 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5974 cpu_gpr[rS(ctx->opcode)]); 5975 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5976 } 5977 5978 /* dccci */ 5979 static void gen_dccci(DisasContext *ctx) 5980 { 5981 CHK_SV; 5982 /* interpreted as no-op */ 5983 } 5984 5985 /* dcread */ 5986 static void gen_dcread(DisasContext *ctx) 5987 { 5988 #if defined(CONFIG_USER_ONLY) 5989 GEN_PRIV; 5990 #else 5991 TCGv EA, val; 5992 5993 CHK_SV; 5994 gen_set_access_type(ctx, ACCESS_CACHE); 5995 EA = tcg_temp_new(); 5996 gen_addr_reg_index(ctx, EA); 5997 val = tcg_temp_new(); 5998 gen_qemu_ld32u(ctx, val, EA); 5999 tcg_temp_free(val); 6000 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6001 tcg_temp_free(EA); 6002 #endif /* defined(CONFIG_USER_ONLY) */ 6003 } 6004 6005 /* icbt */ 6006 static void gen_icbt_40x(DisasContext *ctx) 6007 { 6008 /* interpreted as no-op */ 6009 /* XXX: specification say this is treated as a load by the MMU 6010 * but does not generate any exception 6011 */ 6012 } 6013 6014 /* iccci */ 6015 static void gen_iccci(DisasContext *ctx) 6016 { 6017 CHK_SV; 6018 /* interpreted as no-op */ 6019 } 6020 6021 /* icread */ 6022 static void gen_icread(DisasContext *ctx) 6023 { 6024 CHK_SV; 6025 /* interpreted as no-op */ 6026 } 6027 6028 /* rfci (supervisor only) */ 6029 static void gen_rfci_40x(DisasContext *ctx) 6030 { 6031 #if defined(CONFIG_USER_ONLY) 6032 GEN_PRIV; 6033 #else 6034 CHK_SV; 6035 /* Restore CPU state */ 6036 gen_helper_40x_rfci(cpu_env); 6037 gen_sync_exception(ctx); 6038 #endif /* defined(CONFIG_USER_ONLY) */ 6039 } 6040 6041 static void gen_rfci(DisasContext *ctx) 6042 { 6043 #if defined(CONFIG_USER_ONLY) 6044 GEN_PRIV; 6045 #else 6046 CHK_SV; 6047 /* Restore CPU state */ 6048 gen_helper_rfci(cpu_env); 6049 gen_sync_exception(ctx); 6050 #endif /* defined(CONFIG_USER_ONLY) */ 6051 } 6052 6053 /* BookE specific */ 6054 6055 /* XXX: not implemented on 440 ? */ 6056 static void gen_rfdi(DisasContext *ctx) 6057 { 6058 #if defined(CONFIG_USER_ONLY) 6059 GEN_PRIV; 6060 #else 6061 CHK_SV; 6062 /* Restore CPU state */ 6063 gen_helper_rfdi(cpu_env); 6064 gen_sync_exception(ctx); 6065 #endif /* defined(CONFIG_USER_ONLY) */ 6066 } 6067 6068 /* XXX: not implemented on 440 ? */ 6069 static void gen_rfmci(DisasContext *ctx) 6070 { 6071 #if defined(CONFIG_USER_ONLY) 6072 GEN_PRIV; 6073 #else 6074 CHK_SV; 6075 /* Restore CPU state */ 6076 gen_helper_rfmci(cpu_env); 6077 gen_sync_exception(ctx); 6078 #endif /* defined(CONFIG_USER_ONLY) */ 6079 } 6080 6081 /* TLB management - PowerPC 405 implementation */ 6082 6083 /* tlbre */ 6084 static void gen_tlbre_40x(DisasContext *ctx) 6085 { 6086 #if defined(CONFIG_USER_ONLY) 6087 GEN_PRIV; 6088 #else 6089 CHK_SV; 6090 switch (rB(ctx->opcode)) { 6091 case 0: 6092 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6093 cpu_gpr[rA(ctx->opcode)]); 6094 break; 6095 case 1: 6096 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6097 cpu_gpr[rA(ctx->opcode)]); 6098 break; 6099 default: 6100 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6101 break; 6102 } 6103 #endif /* defined(CONFIG_USER_ONLY) */ 6104 } 6105 6106 /* tlbsx - tlbsx. */ 6107 static void gen_tlbsx_40x(DisasContext *ctx) 6108 { 6109 #if defined(CONFIG_USER_ONLY) 6110 GEN_PRIV; 6111 #else 6112 TCGv t0; 6113 6114 CHK_SV; 6115 t0 = tcg_temp_new(); 6116 gen_addr_reg_index(ctx, t0); 6117 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6118 tcg_temp_free(t0); 6119 if (Rc(ctx->opcode)) { 6120 TCGLabel *l1 = gen_new_label(); 6121 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6122 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6123 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6124 gen_set_label(l1); 6125 } 6126 #endif /* defined(CONFIG_USER_ONLY) */ 6127 } 6128 6129 /* tlbwe */ 6130 static void gen_tlbwe_40x(DisasContext *ctx) 6131 { 6132 #if defined(CONFIG_USER_ONLY) 6133 GEN_PRIV; 6134 #else 6135 CHK_SV; 6136 6137 switch (rB(ctx->opcode)) { 6138 case 0: 6139 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6140 cpu_gpr[rS(ctx->opcode)]); 6141 break; 6142 case 1: 6143 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6144 cpu_gpr[rS(ctx->opcode)]); 6145 break; 6146 default: 6147 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6148 break; 6149 } 6150 #endif /* defined(CONFIG_USER_ONLY) */ 6151 } 6152 6153 /* TLB management - PowerPC 440 implementation */ 6154 6155 /* tlbre */ 6156 static void gen_tlbre_440(DisasContext *ctx) 6157 { 6158 #if defined(CONFIG_USER_ONLY) 6159 GEN_PRIV; 6160 #else 6161 CHK_SV; 6162 6163 switch (rB(ctx->opcode)) { 6164 case 0: 6165 case 1: 6166 case 2: 6167 { 6168 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6169 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6170 t0, cpu_gpr[rA(ctx->opcode)]); 6171 tcg_temp_free_i32(t0); 6172 } 6173 break; 6174 default: 6175 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6176 break; 6177 } 6178 #endif /* defined(CONFIG_USER_ONLY) */ 6179 } 6180 6181 /* tlbsx - tlbsx. */ 6182 static void gen_tlbsx_440(DisasContext *ctx) 6183 { 6184 #if defined(CONFIG_USER_ONLY) 6185 GEN_PRIV; 6186 #else 6187 TCGv t0; 6188 6189 CHK_SV; 6190 t0 = tcg_temp_new(); 6191 gen_addr_reg_index(ctx, t0); 6192 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6193 tcg_temp_free(t0); 6194 if (Rc(ctx->opcode)) { 6195 TCGLabel *l1 = gen_new_label(); 6196 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6197 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6198 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6199 gen_set_label(l1); 6200 } 6201 #endif /* defined(CONFIG_USER_ONLY) */ 6202 } 6203 6204 /* tlbwe */ 6205 static void gen_tlbwe_440(DisasContext *ctx) 6206 { 6207 #if defined(CONFIG_USER_ONLY) 6208 GEN_PRIV; 6209 #else 6210 CHK_SV; 6211 switch (rB(ctx->opcode)) { 6212 case 0: 6213 case 1: 6214 case 2: 6215 { 6216 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6217 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6218 cpu_gpr[rS(ctx->opcode)]); 6219 tcg_temp_free_i32(t0); 6220 } 6221 break; 6222 default: 6223 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6224 break; 6225 } 6226 #endif /* defined(CONFIG_USER_ONLY) */ 6227 } 6228 6229 /* TLB management - PowerPC BookE 2.06 implementation */ 6230 6231 /* tlbre */ 6232 static void gen_tlbre_booke206(DisasContext *ctx) 6233 { 6234 #if defined(CONFIG_USER_ONLY) 6235 GEN_PRIV; 6236 #else 6237 CHK_SV; 6238 gen_helper_booke206_tlbre(cpu_env); 6239 #endif /* defined(CONFIG_USER_ONLY) */ 6240 } 6241 6242 /* tlbsx - tlbsx. */ 6243 static void gen_tlbsx_booke206(DisasContext *ctx) 6244 { 6245 #if defined(CONFIG_USER_ONLY) 6246 GEN_PRIV; 6247 #else 6248 TCGv t0; 6249 6250 CHK_SV; 6251 if (rA(ctx->opcode)) { 6252 t0 = tcg_temp_new(); 6253 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6254 } else { 6255 t0 = tcg_const_tl(0); 6256 } 6257 6258 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6259 gen_helper_booke206_tlbsx(cpu_env, t0); 6260 tcg_temp_free(t0); 6261 #endif /* defined(CONFIG_USER_ONLY) */ 6262 } 6263 6264 /* tlbwe */ 6265 static void gen_tlbwe_booke206(DisasContext *ctx) 6266 { 6267 #if defined(CONFIG_USER_ONLY) 6268 GEN_PRIV; 6269 #else 6270 CHK_SV; 6271 gen_helper_booke206_tlbwe(cpu_env); 6272 #endif /* defined(CONFIG_USER_ONLY) */ 6273 } 6274 6275 static void gen_tlbivax_booke206(DisasContext *ctx) 6276 { 6277 #if defined(CONFIG_USER_ONLY) 6278 GEN_PRIV; 6279 #else 6280 TCGv t0; 6281 6282 CHK_SV; 6283 t0 = tcg_temp_new(); 6284 gen_addr_reg_index(ctx, t0); 6285 gen_helper_booke206_tlbivax(cpu_env, t0); 6286 tcg_temp_free(t0); 6287 #endif /* defined(CONFIG_USER_ONLY) */ 6288 } 6289 6290 static void gen_tlbilx_booke206(DisasContext *ctx) 6291 { 6292 #if defined(CONFIG_USER_ONLY) 6293 GEN_PRIV; 6294 #else 6295 TCGv t0; 6296 6297 CHK_SV; 6298 t0 = tcg_temp_new(); 6299 gen_addr_reg_index(ctx, t0); 6300 6301 switch((ctx->opcode >> 21) & 0x3) { 6302 case 0: 6303 gen_helper_booke206_tlbilx0(cpu_env, t0); 6304 break; 6305 case 1: 6306 gen_helper_booke206_tlbilx1(cpu_env, t0); 6307 break; 6308 case 3: 6309 gen_helper_booke206_tlbilx3(cpu_env, t0); 6310 break; 6311 default: 6312 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6313 break; 6314 } 6315 6316 tcg_temp_free(t0); 6317 #endif /* defined(CONFIG_USER_ONLY) */ 6318 } 6319 6320 6321 /* wrtee */ 6322 static void gen_wrtee(DisasContext *ctx) 6323 { 6324 #if defined(CONFIG_USER_ONLY) 6325 GEN_PRIV; 6326 #else 6327 TCGv t0; 6328 6329 CHK_SV; 6330 t0 = tcg_temp_new(); 6331 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6332 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6333 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6334 tcg_temp_free(t0); 6335 /* Stop translation to have a chance to raise an exception 6336 * if we just set msr_ee to 1 6337 */ 6338 gen_stop_exception(ctx); 6339 #endif /* defined(CONFIG_USER_ONLY) */ 6340 } 6341 6342 /* wrteei */ 6343 static void gen_wrteei(DisasContext *ctx) 6344 { 6345 #if defined(CONFIG_USER_ONLY) 6346 GEN_PRIV; 6347 #else 6348 CHK_SV; 6349 if (ctx->opcode & 0x00008000) { 6350 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6351 /* Stop translation to have a chance to raise an exception */ 6352 gen_stop_exception(ctx); 6353 } else { 6354 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6355 } 6356 #endif /* defined(CONFIG_USER_ONLY) */ 6357 } 6358 6359 /* PowerPC 440 specific instructions */ 6360 6361 /* dlmzb */ 6362 static void gen_dlmzb(DisasContext *ctx) 6363 { 6364 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6365 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6366 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6367 tcg_temp_free_i32(t0); 6368 } 6369 6370 /* mbar replaces eieio on 440 */ 6371 static void gen_mbar(DisasContext *ctx) 6372 { 6373 /* interpreted as no-op */ 6374 } 6375 6376 /* msync replaces sync on 440 */ 6377 static void gen_msync_4xx(DisasContext *ctx) 6378 { 6379 /* interpreted as no-op */ 6380 } 6381 6382 /* icbt */ 6383 static void gen_icbt_440(DisasContext *ctx) 6384 { 6385 /* interpreted as no-op */ 6386 /* XXX: specification say this is treated as a load by the MMU 6387 * but does not generate any exception 6388 */ 6389 } 6390 6391 /* Embedded.Processor Control */ 6392 6393 static void gen_msgclr(DisasContext *ctx) 6394 { 6395 #if defined(CONFIG_USER_ONLY) 6396 GEN_PRIV; 6397 #else 6398 CHK_HV; 6399 /* 64-bit server processors compliant with arch 2.x */ 6400 if (ctx->insns_flags & PPC_SEGMENT_64B) { 6401 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6402 } else { 6403 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6404 } 6405 #endif /* defined(CONFIG_USER_ONLY) */ 6406 } 6407 6408 static void gen_msgsnd(DisasContext *ctx) 6409 { 6410 #if defined(CONFIG_USER_ONLY) 6411 GEN_PRIV; 6412 #else 6413 CHK_HV; 6414 /* 64-bit server processors compliant with arch 2.x */ 6415 if (ctx->insns_flags & PPC_SEGMENT_64B) { 6416 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6417 } else { 6418 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6419 } 6420 #endif /* defined(CONFIG_USER_ONLY) */ 6421 } 6422 6423 static void gen_msgsync(DisasContext *ctx) 6424 { 6425 #if defined(CONFIG_USER_ONLY) 6426 GEN_PRIV; 6427 #else 6428 CHK_HV; 6429 #endif /* defined(CONFIG_USER_ONLY) */ 6430 /* interpreted as no-op */ 6431 } 6432 6433 #if defined(TARGET_PPC64) 6434 static void gen_maddld(DisasContext *ctx) 6435 { 6436 TCGv_i64 t1 = tcg_temp_new_i64(); 6437 6438 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6439 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6440 tcg_temp_free_i64(t1); 6441 } 6442 6443 /* maddhd maddhdu */ 6444 static void gen_maddhd_maddhdu(DisasContext *ctx) 6445 { 6446 TCGv_i64 lo = tcg_temp_new_i64(); 6447 TCGv_i64 hi = tcg_temp_new_i64(); 6448 TCGv_i64 t1 = tcg_temp_new_i64(); 6449 6450 if (Rc(ctx->opcode)) { 6451 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6452 cpu_gpr[rB(ctx->opcode)]); 6453 tcg_gen_movi_i64(t1, 0); 6454 } else { 6455 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6456 cpu_gpr[rB(ctx->opcode)]); 6457 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6458 } 6459 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6460 cpu_gpr[rC(ctx->opcode)], t1); 6461 tcg_temp_free_i64(lo); 6462 tcg_temp_free_i64(hi); 6463 tcg_temp_free_i64(t1); 6464 } 6465 #endif /* defined(TARGET_PPC64) */ 6466 6467 static void gen_tbegin(DisasContext *ctx) 6468 { 6469 if (unlikely(!ctx->tm_enabled)) { 6470 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6471 return; 6472 } 6473 gen_helper_tbegin(cpu_env); 6474 } 6475 6476 #define GEN_TM_NOOP(name) \ 6477 static inline void gen_##name(DisasContext *ctx) \ 6478 { \ 6479 if (unlikely(!ctx->tm_enabled)) { \ 6480 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6481 return; \ 6482 } \ 6483 /* Because tbegin always fails in QEMU, these user \ 6484 * space instructions all have a simple implementation: \ 6485 * \ 6486 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6487 * = 0b0 || 0b00 || 0b0 \ 6488 */ \ 6489 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6490 } 6491 6492 GEN_TM_NOOP(tend); 6493 GEN_TM_NOOP(tabort); 6494 GEN_TM_NOOP(tabortwc); 6495 GEN_TM_NOOP(tabortwci); 6496 GEN_TM_NOOP(tabortdc); 6497 GEN_TM_NOOP(tabortdci); 6498 GEN_TM_NOOP(tsr); 6499 static inline void gen_cp_abort(DisasContext *ctx) 6500 { 6501 // Do Nothing 6502 } 6503 6504 #define GEN_CP_PASTE_NOOP(name) \ 6505 static inline void gen_##name(DisasContext *ctx) \ 6506 { \ 6507 /* Generate invalid exception until \ 6508 * we have an implementation of the copy \ 6509 * paste facility \ 6510 */ \ 6511 gen_invalid(ctx); \ 6512 } 6513 6514 GEN_CP_PASTE_NOOP(copy) 6515 GEN_CP_PASTE_NOOP(paste) 6516 6517 static void gen_tcheck(DisasContext *ctx) 6518 { 6519 if (unlikely(!ctx->tm_enabled)) { 6520 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6521 return; 6522 } 6523 /* Because tbegin always fails, the tcheck implementation 6524 * is simple: 6525 * 6526 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6527 * = 0b1 || 0b00 || 0b0 6528 */ 6529 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6530 } 6531 6532 #if defined(CONFIG_USER_ONLY) 6533 #define GEN_TM_PRIV_NOOP(name) \ 6534 static inline void gen_##name(DisasContext *ctx) \ 6535 { \ 6536 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6537 } 6538 6539 #else 6540 6541 #define GEN_TM_PRIV_NOOP(name) \ 6542 static inline void gen_##name(DisasContext *ctx) \ 6543 { \ 6544 CHK_SV; \ 6545 if (unlikely(!ctx->tm_enabled)) { \ 6546 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6547 return; \ 6548 } \ 6549 /* Because tbegin always fails, the implementation is \ 6550 * simple: \ 6551 * \ 6552 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6553 * = 0b0 || 0b00 | 0b0 \ 6554 */ \ 6555 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6556 } 6557 6558 #endif 6559 6560 GEN_TM_PRIV_NOOP(treclaim); 6561 GEN_TM_PRIV_NOOP(trechkpt); 6562 6563 #include "translate/fp-impl.inc.c" 6564 6565 #include "translate/vmx-impl.inc.c" 6566 6567 #include "translate/vsx-impl.inc.c" 6568 6569 #include "translate/dfp-impl.inc.c" 6570 6571 #include "translate/spe-impl.inc.c" 6572 6573 /* Handles lfdp, lxsd, lxssp */ 6574 static void gen_dform39(DisasContext *ctx) 6575 { 6576 switch (ctx->opcode & 0x3) { 6577 case 0: /* lfdp */ 6578 if (ctx->insns_flags2 & PPC2_ISA205) { 6579 return gen_lfdp(ctx); 6580 } 6581 break; 6582 case 2: /* lxsd */ 6583 if (ctx->insns_flags2 & PPC2_ISA300) { 6584 return gen_lxsd(ctx); 6585 } 6586 break; 6587 case 3: /* lxssp */ 6588 if (ctx->insns_flags2 & PPC2_ISA300) { 6589 return gen_lxssp(ctx); 6590 } 6591 break; 6592 } 6593 return gen_invalid(ctx); 6594 } 6595 6596 /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6597 static void gen_dform3D(DisasContext *ctx) 6598 { 6599 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6600 switch (ctx->opcode & 0x7) { 6601 case 1: /* lxv */ 6602 if (ctx->insns_flags2 & PPC2_ISA300) { 6603 return gen_lxv(ctx); 6604 } 6605 break; 6606 case 5: /* stxv */ 6607 if (ctx->insns_flags2 & PPC2_ISA300) { 6608 return gen_stxv(ctx); 6609 } 6610 break; 6611 } 6612 } else { /* DS-FORM */ 6613 switch (ctx->opcode & 0x3) { 6614 case 0: /* stfdp */ 6615 if (ctx->insns_flags2 & PPC2_ISA205) { 6616 return gen_stfdp(ctx); 6617 } 6618 break; 6619 case 2: /* stxsd */ 6620 if (ctx->insns_flags2 & PPC2_ISA300) { 6621 return gen_stxsd(ctx); 6622 } 6623 break; 6624 case 3: /* stxssp */ 6625 if (ctx->insns_flags2 & PPC2_ISA300) { 6626 return gen_stxssp(ctx); 6627 } 6628 break; 6629 } 6630 } 6631 return gen_invalid(ctx); 6632 } 6633 6634 static opcode_t opcodes[] = { 6635 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6636 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6637 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6638 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6639 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6640 #if defined(TARGET_PPC64) 6641 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6642 #endif 6643 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6644 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6645 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6646 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6647 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6648 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6649 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6650 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6651 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6652 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6653 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6654 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6655 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6656 #if defined(TARGET_PPC64) 6657 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6658 #endif 6659 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6660 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6661 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6662 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6663 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6664 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6665 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6666 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6667 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6668 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6669 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6670 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6671 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6672 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6673 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6674 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6675 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6676 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6677 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6678 #if defined(TARGET_PPC64) 6679 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6680 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6681 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6682 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6683 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6684 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6685 #endif 6686 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6687 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6688 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6689 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6690 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6691 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6692 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6693 #if defined(TARGET_PPC64) 6694 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6695 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6696 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6697 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6698 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6699 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6700 PPC_NONE, PPC2_ISA300), 6701 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6702 PPC_NONE, PPC2_ISA300), 6703 #endif 6704 #if defined(TARGET_PPC64) 6705 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6706 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6707 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6708 #endif 6709 /* handles lfdp, lxsd, lxssp */ 6710 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6711 /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6712 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6713 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6714 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6715 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6716 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6717 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6718 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6719 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6720 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6721 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6722 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6723 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6724 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6725 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6726 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6727 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6728 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6729 #if defined(TARGET_PPC64) 6730 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6731 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6732 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6733 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6734 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6735 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6736 #endif 6737 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6738 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 6739 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 6740 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6741 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6742 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6743 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6744 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6745 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6746 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6747 #if defined(TARGET_PPC64) 6748 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6749 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6750 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6751 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6752 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6753 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6754 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6755 #endif 6756 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 6757 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6758 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6759 #if defined(TARGET_PPC64) 6760 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6761 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6762 #endif 6763 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6764 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6765 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6766 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6767 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6768 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6769 #if defined(TARGET_PPC64) 6770 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6771 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6772 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6773 #endif 6774 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6775 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6776 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6777 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6778 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6779 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6780 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6781 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6782 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6783 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6784 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6785 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6786 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6787 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6788 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6789 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6790 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6791 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6792 #if defined(TARGET_PPC64) 6793 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6794 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6795 PPC_SEGMENT_64B), 6796 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6797 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6798 PPC_SEGMENT_64B), 6799 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 6800 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 6801 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 6802 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 6803 #endif 6804 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6805 /* XXX Those instructions will need to be handled differently for 6806 * different ISA versions */ 6807 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 6808 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 6809 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 6810 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 6811 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6812 #if defined(TARGET_PPC64) 6813 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 6814 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 6815 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 6816 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6817 #endif 6818 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6819 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6820 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 6821 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 6822 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 6823 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 6824 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 6825 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 6826 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 6827 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 6828 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 6829 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6830 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 6831 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 6832 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 6833 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 6834 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 6835 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 6836 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 6837 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6838 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 6839 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 6840 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 6841 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 6842 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 6843 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 6844 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 6845 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 6846 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 6847 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 6848 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 6849 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 6850 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 6851 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 6852 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 6853 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 6854 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 6855 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 6856 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 6857 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6858 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6859 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 6860 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 6861 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 6862 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 6863 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 6864 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 6865 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 6866 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 6867 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6868 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6869 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 6870 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 6871 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6872 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6873 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 6874 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 6875 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6876 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6877 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6878 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6879 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6880 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6881 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 6882 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 6883 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6884 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6885 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6886 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6887 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6888 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6889 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6890 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6891 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6892 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6893 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6894 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6895 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6896 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6897 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6898 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6899 PPC_NONE, PPC2_BOOKE206), 6900 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6901 PPC_NONE, PPC2_BOOKE206), 6902 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6903 PPC_NONE, PPC2_BOOKE206), 6904 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6905 PPC_NONE, PPC2_BOOKE206), 6906 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6907 PPC_NONE, PPC2_BOOKE206), 6908 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 6909 PPC_NONE, PPC2_PRCNTL), 6910 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 6911 PPC_NONE, PPC2_PRCNTL), 6912 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 6913 PPC_NONE, PPC2_PRCNTL), 6914 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6915 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6916 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6917 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6918 PPC_BOOKE, PPC2_BOOKE206), 6919 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), 6920 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6921 PPC_BOOKE, PPC2_BOOKE206), 6922 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 6923 PPC_440_SPEC), 6924 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6925 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6926 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6927 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6928 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 6929 #if defined(TARGET_PPC64) 6930 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6931 PPC2_ISA300), 6932 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6933 #endif 6934 6935 #undef GEN_INT_ARITH_ADD 6936 #undef GEN_INT_ARITH_ADD_CONST 6937 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6938 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6939 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6940 add_ca, compute_ca, compute_ov) \ 6941 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6942 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6943 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6944 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6945 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6946 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6947 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6948 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6949 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6950 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6951 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6952 6953 #undef GEN_INT_ARITH_DIVW 6954 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6955 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6956 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6957 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6958 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6959 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6960 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6961 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6962 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6963 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6964 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6965 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6966 6967 #if defined(TARGET_PPC64) 6968 #undef GEN_INT_ARITH_DIVD 6969 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6970 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6971 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6972 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6973 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6974 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6975 6976 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6977 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6978 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6979 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6980 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6981 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6982 6983 #undef GEN_INT_ARITH_MUL_HELPER 6984 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6985 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6986 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6987 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6988 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6989 #endif 6990 6991 #undef GEN_INT_ARITH_SUBF 6992 #undef GEN_INT_ARITH_SUBF_CONST 6993 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6994 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6995 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6996 add_ca, compute_ca, compute_ov) \ 6997 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6998 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6999 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7000 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7001 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7002 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7003 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7004 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7005 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7006 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7007 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7008 7009 #undef GEN_LOGICAL1 7010 #undef GEN_LOGICAL2 7011 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7012 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7013 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7014 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7015 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7016 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7017 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7018 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7019 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7020 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7021 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7022 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7023 #if defined(TARGET_PPC64) 7024 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7025 #endif 7026 7027 #if defined(TARGET_PPC64) 7028 #undef GEN_PPC64_R2 7029 #undef GEN_PPC64_R4 7030 #define GEN_PPC64_R2(name, opc1, opc2) \ 7031 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7032 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7033 PPC_64B) 7034 #define GEN_PPC64_R4(name, opc1, opc2) \ 7035 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7036 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7037 PPC_64B), \ 7038 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7039 PPC_64B), \ 7040 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7041 PPC_64B) 7042 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7043 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7044 GEN_PPC64_R4(rldic, 0x1E, 0x04), 7045 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7046 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7047 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7048 #endif 7049 7050 #undef GEN_LD 7051 #undef GEN_LDU 7052 #undef GEN_LDUX 7053 #undef GEN_LDX_E 7054 #undef GEN_LDS 7055 #define GEN_LD(name, ldop, opc, type) \ 7056 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7057 #define GEN_LDU(name, ldop, opc, type) \ 7058 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 7059 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 7060 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7061 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7062 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7063 #define GEN_LDS(name, ldop, op, type) \ 7064 GEN_LD(name, ldop, op | 0x20, type) \ 7065 GEN_LDU(name, ldop, op | 0x21, type) \ 7066 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 7067 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 7068 7069 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 7070 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 7071 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 7072 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 7073 #if defined(TARGET_PPC64) 7074 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 7075 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 7076 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 7077 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 7078 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7079 7080 /* HV/P7 and later only */ 7081 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7082 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7083 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7084 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7085 #endif 7086 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7087 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7088 7089 #undef GEN_ST 7090 #undef GEN_STU 7091 #undef GEN_STUX 7092 #undef GEN_STX_E 7093 #undef GEN_STS 7094 #define GEN_ST(name, stop, opc, type) \ 7095 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7096 #define GEN_STU(name, stop, opc, type) \ 7097 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 7098 #define GEN_STUX(name, stop, opc2, opc3, type) \ 7099 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7100 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 7101 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7102 #define GEN_STS(name, stop, op, type) \ 7103 GEN_ST(name, stop, op | 0x20, type) \ 7104 GEN_STU(name, stop, op | 0x21, type) \ 7105 GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 7106 GEN_STX(name, stop, 0x17, op | 0x00, type) 7107 7108 GEN_STS(stb, st8, 0x06, PPC_INTEGER) 7109 GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 7110 GEN_STS(stw, st32, 0x04, PPC_INTEGER) 7111 #if defined(TARGET_PPC64) 7112 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 7113 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 7114 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7115 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7116 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7117 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7118 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7119 #endif 7120 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7121 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7122 7123 #undef GEN_CRLOGIC 7124 #define GEN_CRLOGIC(name, tcg_op, opc) \ 7125 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7126 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7127 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7128 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7129 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7130 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7131 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7132 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7133 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7134 7135 #undef GEN_MAC_HANDLER 7136 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7137 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7138 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7139 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7140 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7141 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7142 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7143 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7144 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7145 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7146 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7147 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7148 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7149 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7150 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7151 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7152 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7153 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7154 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7155 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7156 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7157 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7158 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7159 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7160 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7161 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7162 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7163 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7164 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7165 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7166 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7167 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7168 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7169 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7170 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7171 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7172 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7173 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7174 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7175 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7176 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7177 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7178 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7179 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7180 7181 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7182 PPC_NONE, PPC2_TM), 7183 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7184 PPC_NONE, PPC2_TM), 7185 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7186 PPC_NONE, PPC2_TM), 7187 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7188 PPC_NONE, PPC2_TM), 7189 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7190 PPC_NONE, PPC2_TM), 7191 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7192 PPC_NONE, PPC2_TM), 7193 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7194 PPC_NONE, PPC2_TM), 7195 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7196 PPC_NONE, PPC2_TM), 7197 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7198 PPC_NONE, PPC2_TM), 7199 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7200 PPC_NONE, PPC2_TM), 7201 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7202 PPC_NONE, PPC2_TM), 7203 7204 #include "translate/fp-ops.inc.c" 7205 7206 #include "translate/vmx-ops.inc.c" 7207 7208 #include "translate/vsx-ops.inc.c" 7209 7210 #include "translate/dfp-ops.inc.c" 7211 7212 #include "translate/spe-ops.inc.c" 7213 }; 7214 7215 #include "helper_regs.h" 7216 #include "translate_init.inc.c" 7217 7218 /*****************************************************************************/ 7219 /* Misc PowerPC helpers */ 7220 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 7221 int flags) 7222 { 7223 #define RGPL 4 7224 #define RFPL 4 7225 7226 PowerPCCPU *cpu = POWERPC_CPU(cs); 7227 CPUPPCState *env = &cpu->env; 7228 int i; 7229 7230 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7231 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7232 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7233 cs->cpu_index); 7234 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7235 TARGET_FMT_lx " iidx %d didx %d\n", 7236 env->msr, env->spr[SPR_HID0], 7237 env->hflags, env->immu_idx, env->dmmu_idx); 7238 #if !defined(NO_TIMER_DUMP) 7239 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7240 #if !defined(CONFIG_USER_ONLY) 7241 " DECR %08" PRIu32 7242 #endif 7243 "\n", 7244 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7245 #if !defined(CONFIG_USER_ONLY) 7246 , cpu_ppc_load_decr(env) 7247 #endif 7248 ); 7249 #endif 7250 for (i = 0; i < 32; i++) { 7251 if ((i & (RGPL - 1)) == 0) 7252 cpu_fprintf(f, "GPR%02d", i); 7253 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7254 if ((i & (RGPL - 1)) == (RGPL - 1)) 7255 cpu_fprintf(f, "\n"); 7256 } 7257 cpu_fprintf(f, "CR "); 7258 for (i = 0; i < 8; i++) 7259 cpu_fprintf(f, "%01x", env->crf[i]); 7260 cpu_fprintf(f, " ["); 7261 for (i = 0; i < 8; i++) { 7262 char a = '-'; 7263 if (env->crf[i] & 0x08) 7264 a = 'L'; 7265 else if (env->crf[i] & 0x04) 7266 a = 'G'; 7267 else if (env->crf[i] & 0x02) 7268 a = 'E'; 7269 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7270 } 7271 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7272 env->reserve_addr); 7273 7274 if (flags & CPU_DUMP_FPU) { 7275 for (i = 0; i < 32; i++) { 7276 if ((i & (RFPL - 1)) == 0) { 7277 cpu_fprintf(f, "FPR%02d", i); 7278 } 7279 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); 7280 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7281 cpu_fprintf(f, "\n"); 7282 } 7283 } 7284 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7285 } 7286 7287 #if !defined(CONFIG_USER_ONLY) 7288 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7289 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7290 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7291 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7292 7293 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7294 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7295 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7296 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7297 7298 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7299 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7300 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7301 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7302 7303 #if defined(TARGET_PPC64) 7304 if (env->excp_model == POWERPC_EXCP_POWER7 || 7305 env->excp_model == POWERPC_EXCP_POWER8) { 7306 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7307 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7308 } 7309 #endif 7310 if (env->excp_model == POWERPC_EXCP_BOOKE) { 7311 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7312 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7313 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7314 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7315 7316 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7317 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7318 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7319 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7320 7321 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7322 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7323 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7324 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7325 7326 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7327 " EPR " TARGET_FMT_lx "\n", 7328 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7329 env->spr[SPR_BOOKE_EPR]); 7330 7331 /* FSL-specific */ 7332 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7333 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7334 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7335 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7336 7337 /* 7338 * IVORs are left out as they are large and do not change often -- 7339 * they can be read with "p $ivor0", "p $ivor1", etc. 7340 */ 7341 } 7342 7343 #if defined(TARGET_PPC64) 7344 if (env->flags & POWERPC_FLAG_CFAR) { 7345 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7346 } 7347 #endif 7348 7349 if (env->spr_cb[SPR_LPCR].name) 7350 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7351 7352 switch (env->mmu_model) { 7353 case POWERPC_MMU_32B: 7354 case POWERPC_MMU_601: 7355 case POWERPC_MMU_SOFT_6xx: 7356 case POWERPC_MMU_SOFT_74xx: 7357 #if defined(TARGET_PPC64) 7358 case POWERPC_MMU_64B: 7359 case POWERPC_MMU_2_03: 7360 case POWERPC_MMU_2_06: 7361 case POWERPC_MMU_2_07: 7362 case POWERPC_MMU_3_00: 7363 #endif 7364 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7365 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7366 } 7367 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7368 cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7369 } 7370 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7371 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7372 break; 7373 case POWERPC_MMU_BOOKE206: 7374 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7375 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7376 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7377 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7378 7379 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7380 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7381 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7382 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7383 7384 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7385 " TLB1CFG " TARGET_FMT_lx "\n", 7386 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7387 env->spr[SPR_BOOKE_TLB1CFG]); 7388 break; 7389 default: 7390 break; 7391 } 7392 #endif 7393 7394 #undef RGPL 7395 #undef RFPL 7396 } 7397 7398 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, 7399 fprintf_function cpu_fprintf, int flags) 7400 { 7401 #if defined(DO_PPC_STATISTICS) 7402 PowerPCCPU *cpu = POWERPC_CPU(cs); 7403 opc_handler_t **t1, **t2, **t3, *handler; 7404 int op1, op2, op3; 7405 7406 t1 = cpu->env.opcodes; 7407 for (op1 = 0; op1 < 64; op1++) { 7408 handler = t1[op1]; 7409 if (is_indirect_opcode(handler)) { 7410 t2 = ind_table(handler); 7411 for (op2 = 0; op2 < 32; op2++) { 7412 handler = t2[op2]; 7413 if (is_indirect_opcode(handler)) { 7414 t3 = ind_table(handler); 7415 for (op3 = 0; op3 < 32; op3++) { 7416 handler = t3[op3]; 7417 if (handler->count == 0) 7418 continue; 7419 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " 7420 "%016" PRIx64 " %" PRId64 "\n", 7421 op1, op2, op3, op1, (op3 << 5) | op2, 7422 handler->oname, 7423 handler->count, handler->count); 7424 } 7425 } else { 7426 if (handler->count == 0) 7427 continue; 7428 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " 7429 "%016" PRIx64 " %" PRId64 "\n", 7430 op1, op2, op1, op2, handler->oname, 7431 handler->count, handler->count); 7432 } 7433 } 7434 } else { 7435 if (handler->count == 0) 7436 continue; 7437 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 7438 " %" PRId64 "\n", 7439 op1, op1, handler->oname, 7440 handler->count, handler->count); 7441 } 7442 } 7443 #endif 7444 } 7445 7446 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7447 { 7448 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7449 CPUPPCState *env = cs->env_ptr; 7450 int bound; 7451 7452 ctx->exception = POWERPC_EXCP_NONE; 7453 ctx->spr_cb = env->spr_cb; 7454 ctx->pr = msr_pr; 7455 ctx->mem_idx = env->dmmu_idx; 7456 ctx->dr = msr_dr; 7457 #if !defined(CONFIG_USER_ONLY) 7458 ctx->hv = msr_hv || !env->has_hv_mode; 7459 #endif 7460 ctx->insns_flags = env->insns_flags; 7461 ctx->insns_flags2 = env->insns_flags2; 7462 ctx->access_type = -1; 7463 ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7464 ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); 7465 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7466 ctx->flags = env->flags; 7467 #if defined(TARGET_PPC64) 7468 ctx->sf_mode = msr_is_64bit(env, env->msr); 7469 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7470 #endif 7471 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7472 || env->mmu_model == POWERPC_MMU_601 7473 || (env->mmu_model & POWERPC_MMU_64B); 7474 7475 ctx->fpu_enabled = !!msr_fp; 7476 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7477 ctx->spe_enabled = !!msr_spe; 7478 else 7479 ctx->spe_enabled = false; 7480 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) 7481 ctx->altivec_enabled = !!msr_vr; 7482 else 7483 ctx->altivec_enabled = false; 7484 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7485 ctx->vsx_enabled = !!msr_vsx; 7486 } else { 7487 ctx->vsx_enabled = false; 7488 } 7489 #if defined(TARGET_PPC64) 7490 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7491 ctx->tm_enabled = !!msr_tm; 7492 } else { 7493 ctx->tm_enabled = false; 7494 } 7495 #endif 7496 ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7497 if ((env->flags & POWERPC_FLAG_SE) && msr_se) 7498 ctx->singlestep_enabled = CPU_SINGLE_STEP; 7499 else 7500 ctx->singlestep_enabled = 0; 7501 if ((env->flags & POWERPC_FLAG_BE) && msr_be) 7502 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7503 if ((env->flags & POWERPC_FLAG_DE) && msr_de) { 7504 ctx->singlestep_enabled = 0; 7505 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 7506 if (dbcr0 & DBCR0_ICMP) { 7507 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7508 } 7509 if (dbcr0 & DBCR0_BRT) { 7510 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7511 } 7512 7513 } 7514 if (unlikely(ctx->base.singlestep_enabled)) { 7515 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7516 } 7517 #if defined (DO_SINGLE_STEP) && 0 7518 /* Single step trace mode */ 7519 msr_se = 1; 7520 #endif 7521 7522 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 7523 ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 7524 } 7525 7526 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7527 { 7528 } 7529 7530 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7531 { 7532 tcg_gen_insn_start(dcbase->pc_next); 7533 } 7534 7535 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 7536 const CPUBreakpoint *bp) 7537 { 7538 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7539 7540 gen_debug_exception(ctx); 7541 dcbase->is_jmp = DISAS_NORETURN; 7542 /* The address covered by the breakpoint must be included in 7543 [tb->pc, tb->pc + tb->size) in order to for it to be 7544 properly cleared -- thus we increment the PC here so that 7545 the logic setting tb->size below does the right thing. */ 7546 ctx->base.pc_next += 4; 7547 return true; 7548 } 7549 7550 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7551 { 7552 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7553 CPUPPCState *env = cs->env_ptr; 7554 opc_handler_t **table, *handler; 7555 7556 LOG_DISAS("----------------\n"); 7557 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7558 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7559 7560 if (unlikely(need_byteswap(ctx))) { 7561 ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next)); 7562 } else { 7563 ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); 7564 } 7565 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7566 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 7567 opc3(ctx->opcode), opc4(ctx->opcode), 7568 ctx->le_mode ? "little" : "big"); 7569 ctx->base.pc_next += 4; 7570 table = env->opcodes; 7571 handler = table[opc1(ctx->opcode)]; 7572 if (is_indirect_opcode(handler)) { 7573 table = ind_table(handler); 7574 handler = table[opc2(ctx->opcode)]; 7575 if (is_indirect_opcode(handler)) { 7576 table = ind_table(handler); 7577 handler = table[opc3(ctx->opcode)]; 7578 if (is_indirect_opcode(handler)) { 7579 table = ind_table(handler); 7580 handler = table[opc4(ctx->opcode)]; 7581 } 7582 } 7583 } 7584 /* Is opcode *REALLY* valid ? */ 7585 if (unlikely(handler->handler == &gen_invalid)) { 7586 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7587 "%02x - %02x - %02x - %02x (%08x) " 7588 TARGET_FMT_lx " %d\n", 7589 opc1(ctx->opcode), opc2(ctx->opcode), 7590 opc3(ctx->opcode), opc4(ctx->opcode), 7591 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 7592 } else { 7593 uint32_t inval; 7594 7595 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7596 && Rc(ctx->opcode))) { 7597 inval = handler->inval2; 7598 } else { 7599 inval = handler->inval1; 7600 } 7601 7602 if (unlikely((ctx->opcode & inval) != 0)) { 7603 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7604 "%02x - %02x - %02x - %02x (%08x) " 7605 TARGET_FMT_lx "\n", ctx->opcode & inval, 7606 opc1(ctx->opcode), opc2(ctx->opcode), 7607 opc3(ctx->opcode), opc4(ctx->opcode), 7608 ctx->opcode, ctx->base.pc_next - 4); 7609 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7610 ctx->base.is_jmp = DISAS_NORETURN; 7611 return; 7612 } 7613 } 7614 (*(handler->handler))(ctx); 7615 #if defined(DO_PPC_STATISTICS) 7616 handler->count++; 7617 #endif 7618 /* Check trace mode exceptions */ 7619 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 7620 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 7621 ctx->exception != POWERPC_SYSCALL && 7622 ctx->exception != POWERPC_EXCP_TRAP && 7623 ctx->exception != POWERPC_EXCP_BRANCH)) { 7624 uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_TRACE); 7625 if (excp != POWERPC_EXCP_NONE) 7626 gen_exception_nip(ctx, excp, ctx->base.pc_next); 7627 } 7628 7629 if (tcg_check_temp_count()) { 7630 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 7631 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 7632 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 7633 } 7634 7635 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 7636 DISAS_NEXT : DISAS_NORETURN; 7637 } 7638 7639 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7640 { 7641 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7642 7643 if (ctx->exception == POWERPC_EXCP_NONE) { 7644 gen_goto_tb(ctx, 0, ctx->base.pc_next); 7645 } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 7646 if (unlikely(ctx->base.singlestep_enabled)) { 7647 gen_debug_exception(ctx); 7648 } 7649 /* Generate the return instruction */ 7650 tcg_gen_exit_tb(NULL, 0); 7651 } 7652 } 7653 7654 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 7655 { 7656 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 7657 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 7658 } 7659 7660 static const TranslatorOps ppc_tr_ops = { 7661 .init_disas_context = ppc_tr_init_disas_context, 7662 .tb_start = ppc_tr_tb_start, 7663 .insn_start = ppc_tr_insn_start, 7664 .breakpoint_check = ppc_tr_breakpoint_check, 7665 .translate_insn = ppc_tr_translate_insn, 7666 .tb_stop = ppc_tr_tb_stop, 7667 .disas_log = ppc_tr_disas_log, 7668 }; 7669 7670 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 7671 { 7672 DisasContext ctx; 7673 7674 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); 7675 } 7676 7677 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7678 target_ulong *data) 7679 { 7680 env->nip = data[0]; 7681 } 7682