1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg-op.h" 27 #include "qemu/host-utils.h" 28 #include "exec/cpu_ldst.h" 29 30 #include "exec/helper-proto.h" 31 #include "exec/helper-gen.h" 32 33 #include "trace-tcg.h" 34 #include "exec/translator.h" 35 #include "exec/log.h" 36 37 38 #define CPU_SINGLE_STEP 0x1 39 #define CPU_BRANCH_STEP 0x2 40 #define GDBSTUB_SINGLE_STEP 0x4 41 42 /* Include definitions for instructions classes and implementations flags */ 43 //#define PPC_DEBUG_DISAS 44 //#define DO_PPC_STATISTICS 45 46 #ifdef PPC_DEBUG_DISAS 47 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 48 #else 49 # define LOG_DISAS(...) do { } while (0) 50 #endif 51 /*****************************************************************************/ 52 /* Code translation helpers */ 53 54 /* global register indexes */ 55 static char cpu_reg_names[10*3 + 22*4 /* GPR */ 56 + 10*4 + 22*5 /* SPE GPRh */ 57 + 10*4 + 22*5 /* FPR */ 58 + 2*(10*6 + 22*7) /* AVRh, AVRl */ 59 + 10*5 + 22*6 /* VSR */ 60 + 8*5 /* CRF */]; 61 static TCGv cpu_gpr[32]; 62 static TCGv cpu_gprh[32]; 63 static TCGv_i64 cpu_fpr[32]; 64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; 65 static TCGv_i64 cpu_vsr[32]; 66 static TCGv_i32 cpu_crf[8]; 67 static TCGv cpu_nip; 68 static TCGv cpu_msr; 69 static TCGv cpu_ctr; 70 static TCGv cpu_lr; 71 #if defined(TARGET_PPC64) 72 static TCGv cpu_cfar; 73 #endif 74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75 static TCGv cpu_reserve; 76 static TCGv cpu_reserve_val; 77 static TCGv cpu_fpscr; 78 static TCGv_i32 cpu_access_type; 79 80 #include "exec/gen-icount.h" 81 82 void ppc_translate_init(void) 83 { 84 int i; 85 char* p; 86 size_t cpu_reg_names_size; 87 88 p = cpu_reg_names; 89 cpu_reg_names_size = sizeof(cpu_reg_names); 90 91 for (i = 0; i < 8; i++) { 92 snprintf(p, cpu_reg_names_size, "crf%d", i); 93 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94 offsetof(CPUPPCState, crf[i]), p); 95 p += 5; 96 cpu_reg_names_size -= 5; 97 } 98 99 for (i = 0; i < 32; i++) { 100 snprintf(p, cpu_reg_names_size, "r%d", i); 101 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102 offsetof(CPUPPCState, gpr[i]), p); 103 p += (i < 10) ? 3 : 4; 104 cpu_reg_names_size -= (i < 10) ? 3 : 4; 105 snprintf(p, cpu_reg_names_size, "r%dH", i); 106 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107 offsetof(CPUPPCState, gprh[i]), p); 108 p += (i < 10) ? 4 : 5; 109 cpu_reg_names_size -= (i < 10) ? 4 : 5; 110 111 snprintf(p, cpu_reg_names_size, "fp%d", i); 112 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 113 offsetof(CPUPPCState, fpr[i]), p); 114 p += (i < 10) ? 4 : 5; 115 cpu_reg_names_size -= (i < 10) ? 4 : 5; 116 117 snprintf(p, cpu_reg_names_size, "avr%dH", i); 118 #ifdef HOST_WORDS_BIGENDIAN 119 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 120 offsetof(CPUPPCState, avr[i].u64[0]), p); 121 #else 122 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 123 offsetof(CPUPPCState, avr[i].u64[1]), p); 124 #endif 125 p += (i < 10) ? 6 : 7; 126 cpu_reg_names_size -= (i < 10) ? 6 : 7; 127 128 snprintf(p, cpu_reg_names_size, "avr%dL", i); 129 #ifdef HOST_WORDS_BIGENDIAN 130 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 131 offsetof(CPUPPCState, avr[i].u64[1]), p); 132 #else 133 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 134 offsetof(CPUPPCState, avr[i].u64[0]), p); 135 #endif 136 p += (i < 10) ? 6 : 7; 137 cpu_reg_names_size -= (i < 10) ? 6 : 7; 138 snprintf(p, cpu_reg_names_size, "vsr%d", i); 139 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, 140 offsetof(CPUPPCState, vsr[i]), p); 141 p += (i < 10) ? 5 : 6; 142 cpu_reg_names_size -= (i < 10) ? 5 : 6; 143 } 144 145 cpu_nip = tcg_global_mem_new(cpu_env, 146 offsetof(CPUPPCState, nip), "nip"); 147 148 cpu_msr = tcg_global_mem_new(cpu_env, 149 offsetof(CPUPPCState, msr), "msr"); 150 151 cpu_ctr = tcg_global_mem_new(cpu_env, 152 offsetof(CPUPPCState, ctr), "ctr"); 153 154 cpu_lr = tcg_global_mem_new(cpu_env, 155 offsetof(CPUPPCState, lr), "lr"); 156 157 #if defined(TARGET_PPC64) 158 cpu_cfar = tcg_global_mem_new(cpu_env, 159 offsetof(CPUPPCState, cfar), "cfar"); 160 #endif 161 162 cpu_xer = tcg_global_mem_new(cpu_env, 163 offsetof(CPUPPCState, xer), "xer"); 164 cpu_so = tcg_global_mem_new(cpu_env, 165 offsetof(CPUPPCState, so), "SO"); 166 cpu_ov = tcg_global_mem_new(cpu_env, 167 offsetof(CPUPPCState, ov), "OV"); 168 cpu_ca = tcg_global_mem_new(cpu_env, 169 offsetof(CPUPPCState, ca), "CA"); 170 cpu_ov32 = tcg_global_mem_new(cpu_env, 171 offsetof(CPUPPCState, ov32), "OV32"); 172 cpu_ca32 = tcg_global_mem_new(cpu_env, 173 offsetof(CPUPPCState, ca32), "CA32"); 174 175 cpu_reserve = tcg_global_mem_new(cpu_env, 176 offsetof(CPUPPCState, reserve_addr), 177 "reserve_addr"); 178 cpu_reserve_val = tcg_global_mem_new(cpu_env, 179 offsetof(CPUPPCState, reserve_val), 180 "reserve_val"); 181 182 cpu_fpscr = tcg_global_mem_new(cpu_env, 183 offsetof(CPUPPCState, fpscr), "fpscr"); 184 185 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 186 offsetof(CPUPPCState, access_type), "access_type"); 187 } 188 189 /* internal defines */ 190 struct DisasContext { 191 DisasContextBase base; 192 uint32_t opcode; 193 uint32_t exception; 194 /* Routine used to access memory */ 195 bool pr, hv, dr, le_mode; 196 bool lazy_tlb_flush; 197 bool need_access_type; 198 int mem_idx; 199 int access_type; 200 /* Translation flags */ 201 TCGMemOp default_tcg_memop_mask; 202 #if defined(TARGET_PPC64) 203 bool sf_mode; 204 bool has_cfar; 205 #endif 206 bool fpu_enabled; 207 bool altivec_enabled; 208 bool vsx_enabled; 209 bool spe_enabled; 210 bool tm_enabled; 211 bool gtse; 212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 213 int singlestep_enabled; 214 uint64_t insns_flags; 215 uint64_t insns_flags2; 216 }; 217 218 /* Return true iff byteswap is needed in a scalar memop */ 219 static inline bool need_byteswap(const DisasContext *ctx) 220 { 221 #if defined(TARGET_WORDS_BIGENDIAN) 222 return ctx->le_mode; 223 #else 224 return !ctx->le_mode; 225 #endif 226 } 227 228 /* True when active word size < size of target_long. */ 229 #ifdef TARGET_PPC64 230 # define NARROW_MODE(C) (!(C)->sf_mode) 231 #else 232 # define NARROW_MODE(C) 0 233 #endif 234 235 struct opc_handler_t { 236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 237 uint32_t inval1; 238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 239 uint32_t inval2; 240 /* instruction type */ 241 uint64_t type; 242 /* extended instruction type */ 243 uint64_t type2; 244 /* handler */ 245 void (*handler)(DisasContext *ctx); 246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 247 const char *oname; 248 #endif 249 #if defined(DO_PPC_STATISTICS) 250 uint64_t count; 251 #endif 252 }; 253 254 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 255 { 256 if (ctx->need_access_type && ctx->access_type != access_type) { 257 tcg_gen_movi_i32(cpu_access_type, access_type); 258 ctx->access_type = access_type; 259 } 260 } 261 262 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 263 { 264 if (NARROW_MODE(ctx)) { 265 nip = (uint32_t)nip; 266 } 267 tcg_gen_movi_tl(cpu_nip, nip); 268 } 269 270 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 271 { 272 TCGv_i32 t0, t1; 273 274 /* These are all synchronous exceptions, we set the PC back to 275 * the faulting instruction 276 */ 277 if (ctx->exception == POWERPC_EXCP_NONE) { 278 gen_update_nip(ctx, ctx->base.pc_next - 4); 279 } 280 t0 = tcg_const_i32(excp); 281 t1 = tcg_const_i32(error); 282 gen_helper_raise_exception_err(cpu_env, t0, t1); 283 tcg_temp_free_i32(t0); 284 tcg_temp_free_i32(t1); 285 ctx->exception = (excp); 286 } 287 288 static void gen_exception(DisasContext *ctx, uint32_t excp) 289 { 290 TCGv_i32 t0; 291 292 /* These are all synchronous exceptions, we set the PC back to 293 * the faulting instruction 294 */ 295 if (ctx->exception == POWERPC_EXCP_NONE) { 296 gen_update_nip(ctx, ctx->base.pc_next - 4); 297 } 298 t0 = tcg_const_i32(excp); 299 gen_helper_raise_exception(cpu_env, t0); 300 tcg_temp_free_i32(t0); 301 ctx->exception = (excp); 302 } 303 304 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 305 target_ulong nip) 306 { 307 TCGv_i32 t0; 308 309 gen_update_nip(ctx, nip); 310 t0 = tcg_const_i32(excp); 311 gen_helper_raise_exception(cpu_env, t0); 312 tcg_temp_free_i32(t0); 313 ctx->exception = (excp); 314 } 315 316 static void gen_debug_exception(DisasContext *ctx) 317 { 318 TCGv_i32 t0; 319 320 /* These are all synchronous exceptions, we set the PC back to 321 * the faulting instruction 322 */ 323 if ((ctx->exception != POWERPC_EXCP_BRANCH) && 324 (ctx->exception != POWERPC_EXCP_SYNC)) { 325 gen_update_nip(ctx, ctx->base.pc_next); 326 } 327 t0 = tcg_const_i32(EXCP_DEBUG); 328 gen_helper_raise_exception(cpu_env, t0); 329 tcg_temp_free_i32(t0); 330 } 331 332 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 333 { 334 /* Will be converted to program check if needed */ 335 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 336 } 337 338 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 339 { 340 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 341 } 342 343 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 344 { 345 /* Will be converted to program check if needed */ 346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 347 } 348 349 /* Stop translation */ 350 static inline void gen_stop_exception(DisasContext *ctx) 351 { 352 gen_update_nip(ctx, ctx->base.pc_next); 353 ctx->exception = POWERPC_EXCP_STOP; 354 } 355 356 #ifndef CONFIG_USER_ONLY 357 /* No need to update nip here, as execution flow will change */ 358 static inline void gen_sync_exception(DisasContext *ctx) 359 { 360 ctx->exception = POWERPC_EXCP_SYNC; 361 } 362 #endif 363 364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 366 367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 369 370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 372 373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 375 376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 378 379 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 380 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 381 382 typedef struct opcode_t { 383 unsigned char opc1, opc2, opc3, opc4; 384 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 385 unsigned char pad[4]; 386 #endif 387 opc_handler_t handler; 388 const char *oname; 389 } opcode_t; 390 391 /* Helpers for priv. check */ 392 #define GEN_PRIV \ 393 do { \ 394 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 395 } while (0) 396 397 #if defined(CONFIG_USER_ONLY) 398 #define CHK_HV GEN_PRIV 399 #define CHK_SV GEN_PRIV 400 #define CHK_HVRM GEN_PRIV 401 #else 402 #define CHK_HV \ 403 do { \ 404 if (unlikely(ctx->pr || !ctx->hv)) { \ 405 GEN_PRIV; \ 406 } \ 407 } while (0) 408 #define CHK_SV \ 409 do { \ 410 if (unlikely(ctx->pr)) { \ 411 GEN_PRIV; \ 412 } \ 413 } while (0) 414 #define CHK_HVRM \ 415 do { \ 416 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 417 GEN_PRIV; \ 418 } \ 419 } while (0) 420 #endif 421 422 #define CHK_NONE 423 424 /*****************************************************************************/ 425 /* PowerPC instructions table */ 426 427 #if defined(DO_PPC_STATISTICS) 428 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 429 { \ 430 .opc1 = op1, \ 431 .opc2 = op2, \ 432 .opc3 = op3, \ 433 .opc4 = 0xff, \ 434 .handler = { \ 435 .inval1 = invl, \ 436 .type = _typ, \ 437 .type2 = _typ2, \ 438 .handler = &gen_##name, \ 439 .oname = stringify(name), \ 440 }, \ 441 .oname = stringify(name), \ 442 } 443 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 444 { \ 445 .opc1 = op1, \ 446 .opc2 = op2, \ 447 .opc3 = op3, \ 448 .opc4 = 0xff, \ 449 .handler = { \ 450 .inval1 = invl1, \ 451 .inval2 = invl2, \ 452 .type = _typ, \ 453 .type2 = _typ2, \ 454 .handler = &gen_##name, \ 455 .oname = stringify(name), \ 456 }, \ 457 .oname = stringify(name), \ 458 } 459 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 460 { \ 461 .opc1 = op1, \ 462 .opc2 = op2, \ 463 .opc3 = op3, \ 464 .opc4 = 0xff, \ 465 .handler = { \ 466 .inval1 = invl, \ 467 .type = _typ, \ 468 .type2 = _typ2, \ 469 .handler = &gen_##name, \ 470 .oname = onam, \ 471 }, \ 472 .oname = onam, \ 473 } 474 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 475 { \ 476 .opc1 = op1, \ 477 .opc2 = op2, \ 478 .opc3 = op3, \ 479 .opc4 = op4, \ 480 .handler = { \ 481 .inval1 = invl, \ 482 .type = _typ, \ 483 .type2 = _typ2, \ 484 .handler = &gen_##name, \ 485 .oname = stringify(name), \ 486 }, \ 487 .oname = stringify(name), \ 488 } 489 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 490 { \ 491 .opc1 = op1, \ 492 .opc2 = op2, \ 493 .opc3 = op3, \ 494 .opc4 = op4, \ 495 .handler = { \ 496 .inval1 = invl, \ 497 .type = _typ, \ 498 .type2 = _typ2, \ 499 .handler = &gen_##name, \ 500 .oname = onam, \ 501 }, \ 502 .oname = onam, \ 503 } 504 #else 505 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 506 { \ 507 .opc1 = op1, \ 508 .opc2 = op2, \ 509 .opc3 = op3, \ 510 .opc4 = 0xff, \ 511 .handler = { \ 512 .inval1 = invl, \ 513 .type = _typ, \ 514 .type2 = _typ2, \ 515 .handler = &gen_##name, \ 516 }, \ 517 .oname = stringify(name), \ 518 } 519 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 520 { \ 521 .opc1 = op1, \ 522 .opc2 = op2, \ 523 .opc3 = op3, \ 524 .opc4 = 0xff, \ 525 .handler = { \ 526 .inval1 = invl1, \ 527 .inval2 = invl2, \ 528 .type = _typ, \ 529 .type2 = _typ2, \ 530 .handler = &gen_##name, \ 531 }, \ 532 .oname = stringify(name), \ 533 } 534 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 535 { \ 536 .opc1 = op1, \ 537 .opc2 = op2, \ 538 .opc3 = op3, \ 539 .opc4 = 0xff, \ 540 .handler = { \ 541 .inval1 = invl, \ 542 .type = _typ, \ 543 .type2 = _typ2, \ 544 .handler = &gen_##name, \ 545 }, \ 546 .oname = onam, \ 547 } 548 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 549 { \ 550 .opc1 = op1, \ 551 .opc2 = op2, \ 552 .opc3 = op3, \ 553 .opc4 = op4, \ 554 .handler = { \ 555 .inval1 = invl, \ 556 .type = _typ, \ 557 .type2 = _typ2, \ 558 .handler = &gen_##name, \ 559 }, \ 560 .oname = stringify(name), \ 561 } 562 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 563 { \ 564 .opc1 = op1, \ 565 .opc2 = op2, \ 566 .opc3 = op3, \ 567 .opc4 = op4, \ 568 .handler = { \ 569 .inval1 = invl, \ 570 .type = _typ, \ 571 .type2 = _typ2, \ 572 .handler = &gen_##name, \ 573 }, \ 574 .oname = onam, \ 575 } 576 #endif 577 578 /* SPR load/store helpers */ 579 static inline void gen_load_spr(TCGv t, int reg) 580 { 581 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 582 } 583 584 static inline void gen_store_spr(int reg, TCGv t) 585 { 586 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 587 } 588 589 /* Invalid instruction */ 590 static void gen_invalid(DisasContext *ctx) 591 { 592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 593 } 594 595 static opc_handler_t invalid_handler = { 596 .inval1 = 0xFFFFFFFF, 597 .inval2 = 0xFFFFFFFF, 598 .type = PPC_NONE, 599 .type2 = PPC_NONE, 600 .handler = gen_invalid, 601 }; 602 603 /*** Integer comparison ***/ 604 605 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 606 { 607 TCGv t0 = tcg_temp_new(); 608 TCGv t1 = tcg_temp_new(); 609 TCGv_i32 t = tcg_temp_new_i32(); 610 611 tcg_gen_movi_tl(t0, CRF_EQ); 612 tcg_gen_movi_tl(t1, CRF_LT); 613 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0); 614 tcg_gen_movi_tl(t1, CRF_GT); 615 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0); 616 617 tcg_gen_trunc_tl_i32(t, t0); 618 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 619 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 620 621 tcg_temp_free(t0); 622 tcg_temp_free(t1); 623 tcg_temp_free_i32(t); 624 } 625 626 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 627 { 628 TCGv t0 = tcg_const_tl(arg1); 629 gen_op_cmp(arg0, t0, s, crf); 630 tcg_temp_free(t0); 631 } 632 633 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 634 { 635 TCGv t0, t1; 636 t0 = tcg_temp_new(); 637 t1 = tcg_temp_new(); 638 if (s) { 639 tcg_gen_ext32s_tl(t0, arg0); 640 tcg_gen_ext32s_tl(t1, arg1); 641 } else { 642 tcg_gen_ext32u_tl(t0, arg0); 643 tcg_gen_ext32u_tl(t1, arg1); 644 } 645 gen_op_cmp(t0, t1, s, crf); 646 tcg_temp_free(t1); 647 tcg_temp_free(t0); 648 } 649 650 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 651 { 652 TCGv t0 = tcg_const_tl(arg1); 653 gen_op_cmp32(arg0, t0, s, crf); 654 tcg_temp_free(t0); 655 } 656 657 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 658 { 659 if (NARROW_MODE(ctx)) { 660 gen_op_cmpi32(reg, 0, 1, 0); 661 } else { 662 gen_op_cmpi(reg, 0, 1, 0); 663 } 664 } 665 666 /* cmp */ 667 static void gen_cmp(DisasContext *ctx) 668 { 669 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 670 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 671 1, crfD(ctx->opcode)); 672 } else { 673 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 674 1, crfD(ctx->opcode)); 675 } 676 } 677 678 /* cmpi */ 679 static void gen_cmpi(DisasContext *ctx) 680 { 681 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 682 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 683 1, crfD(ctx->opcode)); 684 } else { 685 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 686 1, crfD(ctx->opcode)); 687 } 688 } 689 690 /* cmpl */ 691 static void gen_cmpl(DisasContext *ctx) 692 { 693 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 694 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 695 0, crfD(ctx->opcode)); 696 } else { 697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 698 0, crfD(ctx->opcode)); 699 } 700 } 701 702 /* cmpli */ 703 static void gen_cmpli(DisasContext *ctx) 704 { 705 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 706 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 707 0, crfD(ctx->opcode)); 708 } else { 709 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 710 0, crfD(ctx->opcode)); 711 } 712 } 713 714 /* cmprb - range comparison: isupper, isaplha, islower*/ 715 static void gen_cmprb(DisasContext *ctx) 716 { 717 TCGv_i32 src1 = tcg_temp_new_i32(); 718 TCGv_i32 src2 = tcg_temp_new_i32(); 719 TCGv_i32 src2lo = tcg_temp_new_i32(); 720 TCGv_i32 src2hi = tcg_temp_new_i32(); 721 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 722 723 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 724 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 725 726 tcg_gen_andi_i32(src1, src1, 0xFF); 727 tcg_gen_ext8u_i32(src2lo, src2); 728 tcg_gen_shri_i32(src2, src2, 8); 729 tcg_gen_ext8u_i32(src2hi, src2); 730 731 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 732 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 733 tcg_gen_and_i32(crf, src2lo, src2hi); 734 735 if (ctx->opcode & 0x00200000) { 736 tcg_gen_shri_i32(src2, src2, 8); 737 tcg_gen_ext8u_i32(src2lo, src2); 738 tcg_gen_shri_i32(src2, src2, 8); 739 tcg_gen_ext8u_i32(src2hi, src2); 740 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 741 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 742 tcg_gen_and_i32(src2lo, src2lo, src2hi); 743 tcg_gen_or_i32(crf, crf, src2lo); 744 } 745 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 746 tcg_temp_free_i32(src1); 747 tcg_temp_free_i32(src2); 748 tcg_temp_free_i32(src2lo); 749 tcg_temp_free_i32(src2hi); 750 } 751 752 #if defined(TARGET_PPC64) 753 /* cmpeqb */ 754 static void gen_cmpeqb(DisasContext *ctx) 755 { 756 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 757 cpu_gpr[rB(ctx->opcode)]); 758 } 759 #endif 760 761 /* isel (PowerPC 2.03 specification) */ 762 static void gen_isel(DisasContext *ctx) 763 { 764 uint32_t bi = rC(ctx->opcode); 765 uint32_t mask = 0x08 >> (bi & 0x03); 766 TCGv t0 = tcg_temp_new(); 767 TCGv zr; 768 769 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 770 tcg_gen_andi_tl(t0, t0, mask); 771 772 zr = tcg_const_tl(0); 773 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 774 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 775 cpu_gpr[rB(ctx->opcode)]); 776 tcg_temp_free(zr); 777 tcg_temp_free(t0); 778 } 779 780 /* cmpb: PowerPC 2.05 specification */ 781 static void gen_cmpb(DisasContext *ctx) 782 { 783 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 784 cpu_gpr[rB(ctx->opcode)]); 785 } 786 787 /*** Integer arithmetic ***/ 788 789 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 790 TCGv arg1, TCGv arg2, int sub) 791 { 792 TCGv t0 = tcg_temp_new(); 793 794 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 795 tcg_gen_xor_tl(t0, arg1, arg2); 796 if (sub) { 797 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 798 } else { 799 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 800 } 801 tcg_temp_free(t0); 802 if (NARROW_MODE(ctx)) { 803 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 804 if (is_isa300(ctx)) { 805 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 806 } 807 } else { 808 if (is_isa300(ctx)) { 809 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 810 } 811 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 812 } 813 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 814 } 815 816 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 817 TCGv res, TCGv arg0, TCGv arg1, 818 int sub) 819 { 820 TCGv t0; 821 822 if (!is_isa300(ctx)) { 823 return; 824 } 825 826 t0 = tcg_temp_new(); 827 if (sub) { 828 tcg_gen_eqv_tl(t0, arg0, arg1); 829 } else { 830 tcg_gen_xor_tl(t0, arg0, arg1); 831 } 832 tcg_gen_xor_tl(t0, t0, res); 833 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1); 834 tcg_temp_free(t0); 835 } 836 837 /* Common add function */ 838 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 839 TCGv arg2, bool add_ca, bool compute_ca, 840 bool compute_ov, bool compute_rc0) 841 { 842 TCGv t0 = ret; 843 844 if (compute_ca || compute_ov) { 845 t0 = tcg_temp_new(); 846 } 847 848 if (compute_ca) { 849 if (NARROW_MODE(ctx)) { 850 /* Caution: a non-obvious corner case of the spec is that we 851 must produce the *entire* 64-bit addition, but produce the 852 carry into bit 32. */ 853 TCGv t1 = tcg_temp_new(); 854 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 855 tcg_gen_add_tl(t0, arg1, arg2); 856 if (add_ca) { 857 tcg_gen_add_tl(t0, t0, cpu_ca); 858 } 859 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ 860 tcg_temp_free(t1); 861 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 862 if (is_isa300(ctx)) { 863 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 864 } 865 } else { 866 TCGv zero = tcg_const_tl(0); 867 if (add_ca) { 868 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); 869 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); 870 } else { 871 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); 872 } 873 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0); 874 tcg_temp_free(zero); 875 } 876 } else { 877 tcg_gen_add_tl(t0, arg1, arg2); 878 if (add_ca) { 879 tcg_gen_add_tl(t0, t0, cpu_ca); 880 } 881 } 882 883 if (compute_ov) { 884 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 885 } 886 if (unlikely(compute_rc0)) { 887 gen_set_Rc0(ctx, t0); 888 } 889 890 if (t0 != ret) { 891 tcg_gen_mov_tl(ret, t0); 892 tcg_temp_free(t0); 893 } 894 } 895 /* Add functions with two operands */ 896 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 897 static void glue(gen_, name)(DisasContext *ctx) \ 898 { \ 899 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 900 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 901 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 902 } 903 /* Add functions with one operand and one immediate */ 904 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 905 add_ca, compute_ca, compute_ov) \ 906 static void glue(gen_, name)(DisasContext *ctx) \ 907 { \ 908 TCGv t0 = tcg_const_tl(const_val); \ 909 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 910 cpu_gpr[rA(ctx->opcode)], t0, \ 911 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 912 tcg_temp_free(t0); \ 913 } 914 915 /* add add. addo addo. */ 916 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 917 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 918 /* addc addc. addco addco. */ 919 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 920 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 921 /* adde adde. addeo addeo. */ 922 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 923 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 924 /* addme addme. addmeo addmeo. */ 925 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 926 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 927 /* addze addze. addzeo addzeo.*/ 928 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 929 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 930 /* addi */ 931 static void gen_addi(DisasContext *ctx) 932 { 933 target_long simm = SIMM(ctx->opcode); 934 935 if (rA(ctx->opcode) == 0) { 936 /* li case */ 937 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 938 } else { 939 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 940 cpu_gpr[rA(ctx->opcode)], simm); 941 } 942 } 943 /* addic addic.*/ 944 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 945 { 946 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 947 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 948 c, 0, 1, 0, compute_rc0); 949 tcg_temp_free(c); 950 } 951 952 static void gen_addic(DisasContext *ctx) 953 { 954 gen_op_addic(ctx, 0); 955 } 956 957 static void gen_addic_(DisasContext *ctx) 958 { 959 gen_op_addic(ctx, 1); 960 } 961 962 /* addis */ 963 static void gen_addis(DisasContext *ctx) 964 { 965 target_long simm = SIMM(ctx->opcode); 966 967 if (rA(ctx->opcode) == 0) { 968 /* lis case */ 969 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 970 } else { 971 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 972 cpu_gpr[rA(ctx->opcode)], simm << 16); 973 } 974 } 975 976 /* addpcis */ 977 static void gen_addpcis(DisasContext *ctx) 978 { 979 target_long d = DX(ctx->opcode); 980 981 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 982 } 983 984 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 985 TCGv arg2, int sign, int compute_ov) 986 { 987 TCGv_i32 t0 = tcg_temp_new_i32(); 988 TCGv_i32 t1 = tcg_temp_new_i32(); 989 TCGv_i32 t2 = tcg_temp_new_i32(); 990 TCGv_i32 t3 = tcg_temp_new_i32(); 991 992 tcg_gen_trunc_tl_i32(t0, arg1); 993 tcg_gen_trunc_tl_i32(t1, arg2); 994 if (sign) { 995 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 996 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 997 tcg_gen_and_i32(t2, t2, t3); 998 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 999 tcg_gen_or_i32(t2, t2, t3); 1000 tcg_gen_movi_i32(t3, 0); 1001 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1002 tcg_gen_div_i32(t3, t0, t1); 1003 tcg_gen_extu_i32_tl(ret, t3); 1004 } else { 1005 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1006 tcg_gen_movi_i32(t3, 0); 1007 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1008 tcg_gen_divu_i32(t3, t0, t1); 1009 tcg_gen_extu_i32_tl(ret, t3); 1010 } 1011 if (compute_ov) { 1012 tcg_gen_extu_i32_tl(cpu_ov, t2); 1013 if (is_isa300(ctx)) { 1014 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1015 } 1016 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1017 } 1018 tcg_temp_free_i32(t0); 1019 tcg_temp_free_i32(t1); 1020 tcg_temp_free_i32(t2); 1021 tcg_temp_free_i32(t3); 1022 1023 if (unlikely(Rc(ctx->opcode) != 0)) 1024 gen_set_Rc0(ctx, ret); 1025 } 1026 /* Div functions */ 1027 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1028 static void glue(gen_, name)(DisasContext *ctx) \ 1029 { \ 1030 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1031 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1032 sign, compute_ov); \ 1033 } 1034 /* divwu divwu. divwuo divwuo. */ 1035 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1036 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1037 /* divw divw. divwo divwo. */ 1038 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1039 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1040 1041 /* div[wd]eu[o][.] */ 1042 #define GEN_DIVE(name, hlpr, compute_ov) \ 1043 static void gen_##name(DisasContext *ctx) \ 1044 { \ 1045 TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1046 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1047 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1048 tcg_temp_free_i32(t0); \ 1049 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1050 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1051 } \ 1052 } 1053 1054 GEN_DIVE(divweu, divweu, 0); 1055 GEN_DIVE(divweuo, divweu, 1); 1056 GEN_DIVE(divwe, divwe, 0); 1057 GEN_DIVE(divweo, divwe, 1); 1058 1059 #if defined(TARGET_PPC64) 1060 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1061 TCGv arg2, int sign, int compute_ov) 1062 { 1063 TCGv_i64 t0 = tcg_temp_new_i64(); 1064 TCGv_i64 t1 = tcg_temp_new_i64(); 1065 TCGv_i64 t2 = tcg_temp_new_i64(); 1066 TCGv_i64 t3 = tcg_temp_new_i64(); 1067 1068 tcg_gen_mov_i64(t0, arg1); 1069 tcg_gen_mov_i64(t1, arg2); 1070 if (sign) { 1071 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1072 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1073 tcg_gen_and_i64(t2, t2, t3); 1074 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1075 tcg_gen_or_i64(t2, t2, t3); 1076 tcg_gen_movi_i64(t3, 0); 1077 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1078 tcg_gen_div_i64(ret, t0, t1); 1079 } else { 1080 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1081 tcg_gen_movi_i64(t3, 0); 1082 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1083 tcg_gen_divu_i64(ret, t0, t1); 1084 } 1085 if (compute_ov) { 1086 tcg_gen_mov_tl(cpu_ov, t2); 1087 if (is_isa300(ctx)) { 1088 tcg_gen_mov_tl(cpu_ov32, t2); 1089 } 1090 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1091 } 1092 tcg_temp_free_i64(t0); 1093 tcg_temp_free_i64(t1); 1094 tcg_temp_free_i64(t2); 1095 tcg_temp_free_i64(t3); 1096 1097 if (unlikely(Rc(ctx->opcode) != 0)) 1098 gen_set_Rc0(ctx, ret); 1099 } 1100 1101 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1102 static void glue(gen_, name)(DisasContext *ctx) \ 1103 { \ 1104 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1105 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1106 sign, compute_ov); \ 1107 } 1108 /* divdu divdu. divduo divduo. */ 1109 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1110 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1111 /* divd divd. divdo divdo. */ 1112 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1113 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1114 1115 GEN_DIVE(divdeu, divdeu, 0); 1116 GEN_DIVE(divdeuo, divdeu, 1); 1117 GEN_DIVE(divde, divde, 0); 1118 GEN_DIVE(divdeo, divde, 1); 1119 #endif 1120 1121 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1122 TCGv arg2, int sign) 1123 { 1124 TCGv_i32 t0 = tcg_temp_new_i32(); 1125 TCGv_i32 t1 = tcg_temp_new_i32(); 1126 1127 tcg_gen_trunc_tl_i32(t0, arg1); 1128 tcg_gen_trunc_tl_i32(t1, arg2); 1129 if (sign) { 1130 TCGv_i32 t2 = tcg_temp_new_i32(); 1131 TCGv_i32 t3 = tcg_temp_new_i32(); 1132 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1133 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1134 tcg_gen_and_i32(t2, t2, t3); 1135 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1136 tcg_gen_or_i32(t2, t2, t3); 1137 tcg_gen_movi_i32(t3, 0); 1138 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1139 tcg_gen_rem_i32(t3, t0, t1); 1140 tcg_gen_ext_i32_tl(ret, t3); 1141 tcg_temp_free_i32(t2); 1142 tcg_temp_free_i32(t3); 1143 } else { 1144 TCGv_i32 t2 = tcg_const_i32(1); 1145 TCGv_i32 t3 = tcg_const_i32(0); 1146 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1147 tcg_gen_remu_i32(t3, t0, t1); 1148 tcg_gen_extu_i32_tl(ret, t3); 1149 tcg_temp_free_i32(t2); 1150 tcg_temp_free_i32(t3); 1151 } 1152 tcg_temp_free_i32(t0); 1153 tcg_temp_free_i32(t1); 1154 } 1155 1156 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1157 static void glue(gen_, name)(DisasContext *ctx) \ 1158 { \ 1159 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1161 sign); \ 1162 } 1163 1164 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1165 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1166 1167 #if defined(TARGET_PPC64) 1168 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1169 TCGv arg2, int sign) 1170 { 1171 TCGv_i64 t0 = tcg_temp_new_i64(); 1172 TCGv_i64 t1 = tcg_temp_new_i64(); 1173 1174 tcg_gen_mov_i64(t0, arg1); 1175 tcg_gen_mov_i64(t1, arg2); 1176 if (sign) { 1177 TCGv_i64 t2 = tcg_temp_new_i64(); 1178 TCGv_i64 t3 = tcg_temp_new_i64(); 1179 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1180 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1181 tcg_gen_and_i64(t2, t2, t3); 1182 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1183 tcg_gen_or_i64(t2, t2, t3); 1184 tcg_gen_movi_i64(t3, 0); 1185 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1186 tcg_gen_rem_i64(ret, t0, t1); 1187 tcg_temp_free_i64(t2); 1188 tcg_temp_free_i64(t3); 1189 } else { 1190 TCGv_i64 t2 = tcg_const_i64(1); 1191 TCGv_i64 t3 = tcg_const_i64(0); 1192 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1193 tcg_gen_remu_i64(ret, t0, t1); 1194 tcg_temp_free_i64(t2); 1195 tcg_temp_free_i64(t3); 1196 } 1197 tcg_temp_free_i64(t0); 1198 tcg_temp_free_i64(t1); 1199 } 1200 1201 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1202 static void glue(gen_, name)(DisasContext *ctx) \ 1203 { \ 1204 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1205 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1206 sign); \ 1207 } 1208 1209 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1210 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1211 #endif 1212 1213 /* mulhw mulhw. */ 1214 static void gen_mulhw(DisasContext *ctx) 1215 { 1216 TCGv_i32 t0 = tcg_temp_new_i32(); 1217 TCGv_i32 t1 = tcg_temp_new_i32(); 1218 1219 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1220 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1221 tcg_gen_muls2_i32(t0, t1, t0, t1); 1222 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1223 tcg_temp_free_i32(t0); 1224 tcg_temp_free_i32(t1); 1225 if (unlikely(Rc(ctx->opcode) != 0)) 1226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1227 } 1228 1229 /* mulhwu mulhwu. */ 1230 static void gen_mulhwu(DisasContext *ctx) 1231 { 1232 TCGv_i32 t0 = tcg_temp_new_i32(); 1233 TCGv_i32 t1 = tcg_temp_new_i32(); 1234 1235 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1236 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1237 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1238 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1239 tcg_temp_free_i32(t0); 1240 tcg_temp_free_i32(t1); 1241 if (unlikely(Rc(ctx->opcode) != 0)) 1242 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1243 } 1244 1245 /* mullw mullw. */ 1246 static void gen_mullw(DisasContext *ctx) 1247 { 1248 #if defined(TARGET_PPC64) 1249 TCGv_i64 t0, t1; 1250 t0 = tcg_temp_new_i64(); 1251 t1 = tcg_temp_new_i64(); 1252 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1253 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1254 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1255 tcg_temp_free(t0); 1256 tcg_temp_free(t1); 1257 #else 1258 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1259 cpu_gpr[rB(ctx->opcode)]); 1260 #endif 1261 if (unlikely(Rc(ctx->opcode) != 0)) 1262 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1263 } 1264 1265 /* mullwo mullwo. */ 1266 static void gen_mullwo(DisasContext *ctx) 1267 { 1268 TCGv_i32 t0 = tcg_temp_new_i32(); 1269 TCGv_i32 t1 = tcg_temp_new_i32(); 1270 1271 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1272 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1273 tcg_gen_muls2_i32(t0, t1, t0, t1); 1274 #if defined(TARGET_PPC64) 1275 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1276 #else 1277 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1278 #endif 1279 1280 tcg_gen_sari_i32(t0, t0, 31); 1281 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1282 tcg_gen_extu_i32_tl(cpu_ov, t0); 1283 if (is_isa300(ctx)) { 1284 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1285 } 1286 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1287 1288 tcg_temp_free_i32(t0); 1289 tcg_temp_free_i32(t1); 1290 if (unlikely(Rc(ctx->opcode) != 0)) 1291 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1292 } 1293 1294 /* mulli */ 1295 static void gen_mulli(DisasContext *ctx) 1296 { 1297 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1298 SIMM(ctx->opcode)); 1299 } 1300 1301 #if defined(TARGET_PPC64) 1302 /* mulhd mulhd. */ 1303 static void gen_mulhd(DisasContext *ctx) 1304 { 1305 TCGv lo = tcg_temp_new(); 1306 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1307 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1308 tcg_temp_free(lo); 1309 if (unlikely(Rc(ctx->opcode) != 0)) { 1310 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1311 } 1312 } 1313 1314 /* mulhdu mulhdu. */ 1315 static void gen_mulhdu(DisasContext *ctx) 1316 { 1317 TCGv lo = tcg_temp_new(); 1318 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1319 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1320 tcg_temp_free(lo); 1321 if (unlikely(Rc(ctx->opcode) != 0)) { 1322 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1323 } 1324 } 1325 1326 /* mulld mulld. */ 1327 static void gen_mulld(DisasContext *ctx) 1328 { 1329 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1330 cpu_gpr[rB(ctx->opcode)]); 1331 if (unlikely(Rc(ctx->opcode) != 0)) 1332 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1333 } 1334 1335 /* mulldo mulldo. */ 1336 static void gen_mulldo(DisasContext *ctx) 1337 { 1338 TCGv_i64 t0 = tcg_temp_new_i64(); 1339 TCGv_i64 t1 = tcg_temp_new_i64(); 1340 1341 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1342 cpu_gpr[rB(ctx->opcode)]); 1343 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1344 1345 tcg_gen_sari_i64(t0, t0, 63); 1346 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 1347 if (is_isa300(ctx)) { 1348 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1349 } 1350 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1351 1352 tcg_temp_free_i64(t0); 1353 tcg_temp_free_i64(t1); 1354 1355 if (unlikely(Rc(ctx->opcode) != 0)) { 1356 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1357 } 1358 } 1359 #endif 1360 1361 /* Common subf function */ 1362 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1363 TCGv arg2, bool add_ca, bool compute_ca, 1364 bool compute_ov, bool compute_rc0) 1365 { 1366 TCGv t0 = ret; 1367 1368 if (compute_ca || compute_ov) { 1369 t0 = tcg_temp_new(); 1370 } 1371 1372 if (compute_ca) { 1373 /* dest = ~arg1 + arg2 [+ ca]. */ 1374 if (NARROW_MODE(ctx)) { 1375 /* Caution: a non-obvious corner case of the spec is that we 1376 must produce the *entire* 64-bit addition, but produce the 1377 carry into bit 32. */ 1378 TCGv inv1 = tcg_temp_new(); 1379 TCGv t1 = tcg_temp_new(); 1380 tcg_gen_not_tl(inv1, arg1); 1381 if (add_ca) { 1382 tcg_gen_add_tl(t0, arg2, cpu_ca); 1383 } else { 1384 tcg_gen_addi_tl(t0, arg2, 1); 1385 } 1386 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1387 tcg_gen_add_tl(t0, t0, inv1); 1388 tcg_temp_free(inv1); 1389 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1390 tcg_temp_free(t1); 1391 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 1392 if (is_isa300(ctx)) { 1393 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 1394 } 1395 } else if (add_ca) { 1396 TCGv zero, inv1 = tcg_temp_new(); 1397 tcg_gen_not_tl(inv1, arg1); 1398 zero = tcg_const_tl(0); 1399 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1400 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 1401 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0); 1402 tcg_temp_free(zero); 1403 tcg_temp_free(inv1); 1404 } else { 1405 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1406 tcg_gen_sub_tl(t0, arg2, arg1); 1407 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1); 1408 } 1409 } else if (add_ca) { 1410 /* Since we're ignoring carry-out, we can simplify the 1411 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ 1412 tcg_gen_sub_tl(t0, arg2, arg1); 1413 tcg_gen_add_tl(t0, t0, cpu_ca); 1414 tcg_gen_subi_tl(t0, t0, 1); 1415 } else { 1416 tcg_gen_sub_tl(t0, arg2, arg1); 1417 } 1418 1419 if (compute_ov) { 1420 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1421 } 1422 if (unlikely(compute_rc0)) { 1423 gen_set_Rc0(ctx, t0); 1424 } 1425 1426 if (t0 != ret) { 1427 tcg_gen_mov_tl(ret, t0); 1428 tcg_temp_free(t0); 1429 } 1430 } 1431 /* Sub functions with Two operands functions */ 1432 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1433 static void glue(gen_, name)(DisasContext *ctx) \ 1434 { \ 1435 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1436 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1437 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1438 } 1439 /* Sub functions with one operand and one immediate */ 1440 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1441 add_ca, compute_ca, compute_ov) \ 1442 static void glue(gen_, name)(DisasContext *ctx) \ 1443 { \ 1444 TCGv t0 = tcg_const_tl(const_val); \ 1445 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1446 cpu_gpr[rA(ctx->opcode)], t0, \ 1447 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1448 tcg_temp_free(t0); \ 1449 } 1450 /* subf subf. subfo subfo. */ 1451 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1452 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1453 /* subfc subfc. subfco subfco. */ 1454 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1455 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1456 /* subfe subfe. subfeo subfo. */ 1457 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1458 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1459 /* subfme subfme. subfmeo subfmeo. */ 1460 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1461 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1462 /* subfze subfze. subfzeo subfzeo.*/ 1463 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1464 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1465 1466 /* subfic */ 1467 static void gen_subfic(DisasContext *ctx) 1468 { 1469 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1470 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1471 c, 0, 1, 0, 0); 1472 tcg_temp_free(c); 1473 } 1474 1475 /* neg neg. nego nego. */ 1476 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1477 { 1478 TCGv zero = tcg_const_tl(0); 1479 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1480 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1481 tcg_temp_free(zero); 1482 } 1483 1484 static void gen_neg(DisasContext *ctx) 1485 { 1486 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 1487 if (unlikely(Rc(ctx->opcode))) { 1488 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1489 } 1490 } 1491 1492 static void gen_nego(DisasContext *ctx) 1493 { 1494 gen_op_arith_neg(ctx, 1); 1495 } 1496 1497 /*** Integer logical ***/ 1498 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1499 static void glue(gen_, name)(DisasContext *ctx) \ 1500 { \ 1501 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1502 cpu_gpr[rB(ctx->opcode)]); \ 1503 if (unlikely(Rc(ctx->opcode) != 0)) \ 1504 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1505 } 1506 1507 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1508 static void glue(gen_, name)(DisasContext *ctx) \ 1509 { \ 1510 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1511 if (unlikely(Rc(ctx->opcode) != 0)) \ 1512 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1513 } 1514 1515 /* and & and. */ 1516 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1517 /* andc & andc. */ 1518 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1519 1520 /* andi. */ 1521 static void gen_andi_(DisasContext *ctx) 1522 { 1523 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); 1524 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1525 } 1526 1527 /* andis. */ 1528 static void gen_andis_(DisasContext *ctx) 1529 { 1530 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); 1531 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1532 } 1533 1534 /* cntlzw */ 1535 static void gen_cntlzw(DisasContext *ctx) 1536 { 1537 TCGv_i32 t = tcg_temp_new_i32(); 1538 1539 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1540 tcg_gen_clzi_i32(t, t, 32); 1541 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1542 tcg_temp_free_i32(t); 1543 1544 if (unlikely(Rc(ctx->opcode) != 0)) 1545 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1546 } 1547 1548 /* cnttzw */ 1549 static void gen_cnttzw(DisasContext *ctx) 1550 { 1551 TCGv_i32 t = tcg_temp_new_i32(); 1552 1553 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1554 tcg_gen_ctzi_i32(t, t, 32); 1555 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1556 tcg_temp_free_i32(t); 1557 1558 if (unlikely(Rc(ctx->opcode) != 0)) { 1559 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1560 } 1561 } 1562 1563 /* eqv & eqv. */ 1564 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1565 /* extsb & extsb. */ 1566 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1567 /* extsh & extsh. */ 1568 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1569 /* nand & nand. */ 1570 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1571 /* nor & nor. */ 1572 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1573 1574 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1575 static void gen_pause(DisasContext *ctx) 1576 { 1577 TCGv_i32 t0 = tcg_const_i32(0); 1578 tcg_gen_st_i32(t0, cpu_env, 1579 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1580 tcg_temp_free_i32(t0); 1581 1582 /* Stop translation, this gives other CPUs a chance to run */ 1583 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1584 } 1585 #endif /* defined(TARGET_PPC64) */ 1586 1587 /* or & or. */ 1588 static void gen_or(DisasContext *ctx) 1589 { 1590 int rs, ra, rb; 1591 1592 rs = rS(ctx->opcode); 1593 ra = rA(ctx->opcode); 1594 rb = rB(ctx->opcode); 1595 /* Optimisation for mr. ri case */ 1596 if (rs != ra || rs != rb) { 1597 if (rs != rb) 1598 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1599 else 1600 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1601 if (unlikely(Rc(ctx->opcode) != 0)) 1602 gen_set_Rc0(ctx, cpu_gpr[ra]); 1603 } else if (unlikely(Rc(ctx->opcode) != 0)) { 1604 gen_set_Rc0(ctx, cpu_gpr[rs]); 1605 #if defined(TARGET_PPC64) 1606 } else if (rs != 0) { /* 0 is nop */ 1607 int prio = 0; 1608 1609 switch (rs) { 1610 case 1: 1611 /* Set process priority to low */ 1612 prio = 2; 1613 break; 1614 case 6: 1615 /* Set process priority to medium-low */ 1616 prio = 3; 1617 break; 1618 case 2: 1619 /* Set process priority to normal */ 1620 prio = 4; 1621 break; 1622 #if !defined(CONFIG_USER_ONLY) 1623 case 31: 1624 if (!ctx->pr) { 1625 /* Set process priority to very low */ 1626 prio = 1; 1627 } 1628 break; 1629 case 5: 1630 if (!ctx->pr) { 1631 /* Set process priority to medium-hight */ 1632 prio = 5; 1633 } 1634 break; 1635 case 3: 1636 if (!ctx->pr) { 1637 /* Set process priority to high */ 1638 prio = 6; 1639 } 1640 break; 1641 case 7: 1642 if (ctx->hv && !ctx->pr) { 1643 /* Set process priority to very high */ 1644 prio = 7; 1645 } 1646 break; 1647 #endif 1648 default: 1649 break; 1650 } 1651 if (prio) { 1652 TCGv t0 = tcg_temp_new(); 1653 gen_load_spr(t0, SPR_PPR); 1654 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1655 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1656 gen_store_spr(SPR_PPR, t0); 1657 tcg_temp_free(t0); 1658 } 1659 #if !defined(CONFIG_USER_ONLY) 1660 /* Pause out of TCG otherwise spin loops with smt_low eat too much 1661 * CPU and the kernel hangs. This applies to all encodings other 1662 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), 1663 * and all currently undefined. 1664 */ 1665 gen_pause(ctx); 1666 #endif 1667 #endif 1668 } 1669 } 1670 /* orc & orc. */ 1671 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1672 1673 /* xor & xor. */ 1674 static void gen_xor(DisasContext *ctx) 1675 { 1676 /* Optimisation for "set to zero" case */ 1677 if (rS(ctx->opcode) != rB(ctx->opcode)) 1678 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1679 else 1680 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1681 if (unlikely(Rc(ctx->opcode) != 0)) 1682 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1683 } 1684 1685 /* ori */ 1686 static void gen_ori(DisasContext *ctx) 1687 { 1688 target_ulong uimm = UIMM(ctx->opcode); 1689 1690 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1691 return; 1692 } 1693 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1694 } 1695 1696 /* oris */ 1697 static void gen_oris(DisasContext *ctx) 1698 { 1699 target_ulong uimm = UIMM(ctx->opcode); 1700 1701 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1702 /* NOP */ 1703 return; 1704 } 1705 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1706 } 1707 1708 /* xori */ 1709 static void gen_xori(DisasContext *ctx) 1710 { 1711 target_ulong uimm = UIMM(ctx->opcode); 1712 1713 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1714 /* NOP */ 1715 return; 1716 } 1717 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1718 } 1719 1720 /* xoris */ 1721 static void gen_xoris(DisasContext *ctx) 1722 { 1723 target_ulong uimm = UIMM(ctx->opcode); 1724 1725 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1726 /* NOP */ 1727 return; 1728 } 1729 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1730 } 1731 1732 /* popcntb : PowerPC 2.03 specification */ 1733 static void gen_popcntb(DisasContext *ctx) 1734 { 1735 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1736 } 1737 1738 static void gen_popcntw(DisasContext *ctx) 1739 { 1740 #if defined(TARGET_PPC64) 1741 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1742 #else 1743 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1744 #endif 1745 } 1746 1747 #if defined(TARGET_PPC64) 1748 /* popcntd: PowerPC 2.06 specification */ 1749 static void gen_popcntd(DisasContext *ctx) 1750 { 1751 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1752 } 1753 #endif 1754 1755 /* prtyw: PowerPC 2.05 specification */ 1756 static void gen_prtyw(DisasContext *ctx) 1757 { 1758 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1759 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1760 TCGv t0 = tcg_temp_new(); 1761 tcg_gen_shri_tl(t0, rs, 16); 1762 tcg_gen_xor_tl(ra, rs, t0); 1763 tcg_gen_shri_tl(t0, ra, 8); 1764 tcg_gen_xor_tl(ra, ra, t0); 1765 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1766 tcg_temp_free(t0); 1767 } 1768 1769 #if defined(TARGET_PPC64) 1770 /* prtyd: PowerPC 2.05 specification */ 1771 static void gen_prtyd(DisasContext *ctx) 1772 { 1773 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1774 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1775 TCGv t0 = tcg_temp_new(); 1776 tcg_gen_shri_tl(t0, rs, 32); 1777 tcg_gen_xor_tl(ra, rs, t0); 1778 tcg_gen_shri_tl(t0, ra, 16); 1779 tcg_gen_xor_tl(ra, ra, t0); 1780 tcg_gen_shri_tl(t0, ra, 8); 1781 tcg_gen_xor_tl(ra, ra, t0); 1782 tcg_gen_andi_tl(ra, ra, 1); 1783 tcg_temp_free(t0); 1784 } 1785 #endif 1786 1787 #if defined(TARGET_PPC64) 1788 /* bpermd */ 1789 static void gen_bpermd(DisasContext *ctx) 1790 { 1791 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1792 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1793 } 1794 #endif 1795 1796 #if defined(TARGET_PPC64) 1797 /* extsw & extsw. */ 1798 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1799 1800 /* cntlzd */ 1801 static void gen_cntlzd(DisasContext *ctx) 1802 { 1803 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1804 if (unlikely(Rc(ctx->opcode) != 0)) 1805 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1806 } 1807 1808 /* cnttzd */ 1809 static void gen_cnttzd(DisasContext *ctx) 1810 { 1811 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1812 if (unlikely(Rc(ctx->opcode) != 0)) { 1813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1814 } 1815 } 1816 1817 /* darn */ 1818 static void gen_darn(DisasContext *ctx) 1819 { 1820 int l = L(ctx->opcode); 1821 1822 if (l == 0) { 1823 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1824 } else if (l <= 2) { 1825 /* Return 64-bit random for both CRN and RRN */ 1826 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1827 } else { 1828 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1829 } 1830 } 1831 #endif 1832 1833 /*** Integer rotate ***/ 1834 1835 /* rlwimi & rlwimi. */ 1836 static void gen_rlwimi(DisasContext *ctx) 1837 { 1838 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1839 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1840 uint32_t sh = SH(ctx->opcode); 1841 uint32_t mb = MB(ctx->opcode); 1842 uint32_t me = ME(ctx->opcode); 1843 1844 if (sh == (31-me) && mb <= me) { 1845 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1846 } else { 1847 target_ulong mask; 1848 TCGv t1; 1849 1850 #if defined(TARGET_PPC64) 1851 mb += 32; 1852 me += 32; 1853 #endif 1854 mask = MASK(mb, me); 1855 1856 t1 = tcg_temp_new(); 1857 if (mask <= 0xffffffffu) { 1858 TCGv_i32 t0 = tcg_temp_new_i32(); 1859 tcg_gen_trunc_tl_i32(t0, t_rs); 1860 tcg_gen_rotli_i32(t0, t0, sh); 1861 tcg_gen_extu_i32_tl(t1, t0); 1862 tcg_temp_free_i32(t0); 1863 } else { 1864 #if defined(TARGET_PPC64) 1865 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1866 tcg_gen_rotli_i64(t1, t1, sh); 1867 #else 1868 g_assert_not_reached(); 1869 #endif 1870 } 1871 1872 tcg_gen_andi_tl(t1, t1, mask); 1873 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1874 tcg_gen_or_tl(t_ra, t_ra, t1); 1875 tcg_temp_free(t1); 1876 } 1877 if (unlikely(Rc(ctx->opcode) != 0)) { 1878 gen_set_Rc0(ctx, t_ra); 1879 } 1880 } 1881 1882 /* rlwinm & rlwinm. */ 1883 static void gen_rlwinm(DisasContext *ctx) 1884 { 1885 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1886 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1887 int sh = SH(ctx->opcode); 1888 int mb = MB(ctx->opcode); 1889 int me = ME(ctx->opcode); 1890 int len = me - mb + 1; 1891 int rsh = (32 - sh) & 31; 1892 1893 if (sh != 0 && len > 0 && me == (31 - sh)) { 1894 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 1895 } else if (me == 31 && rsh + len <= 32) { 1896 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1897 } else { 1898 target_ulong mask; 1899 #if defined(TARGET_PPC64) 1900 mb += 32; 1901 me += 32; 1902 #endif 1903 mask = MASK(mb, me); 1904 if (sh == 0) { 1905 tcg_gen_andi_tl(t_ra, t_rs, mask); 1906 } else if (mask <= 0xffffffffu) { 1907 TCGv_i32 t0 = tcg_temp_new_i32(); 1908 tcg_gen_trunc_tl_i32(t0, t_rs); 1909 tcg_gen_rotli_i32(t0, t0, sh); 1910 tcg_gen_andi_i32(t0, t0, mask); 1911 tcg_gen_extu_i32_tl(t_ra, t0); 1912 tcg_temp_free_i32(t0); 1913 } else { 1914 #if defined(TARGET_PPC64) 1915 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1916 tcg_gen_rotli_i64(t_ra, t_ra, sh); 1917 tcg_gen_andi_i64(t_ra, t_ra, mask); 1918 #else 1919 g_assert_not_reached(); 1920 #endif 1921 } 1922 } 1923 if (unlikely(Rc(ctx->opcode) != 0)) { 1924 gen_set_Rc0(ctx, t_ra); 1925 } 1926 } 1927 1928 /* rlwnm & rlwnm. */ 1929 static void gen_rlwnm(DisasContext *ctx) 1930 { 1931 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1932 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1933 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1934 uint32_t mb = MB(ctx->opcode); 1935 uint32_t me = ME(ctx->opcode); 1936 target_ulong mask; 1937 1938 #if defined(TARGET_PPC64) 1939 mb += 32; 1940 me += 32; 1941 #endif 1942 mask = MASK(mb, me); 1943 1944 if (mask <= 0xffffffffu) { 1945 TCGv_i32 t0 = tcg_temp_new_i32(); 1946 TCGv_i32 t1 = tcg_temp_new_i32(); 1947 tcg_gen_trunc_tl_i32(t0, t_rb); 1948 tcg_gen_trunc_tl_i32(t1, t_rs); 1949 tcg_gen_andi_i32(t0, t0, 0x1f); 1950 tcg_gen_rotl_i32(t1, t1, t0); 1951 tcg_gen_extu_i32_tl(t_ra, t1); 1952 tcg_temp_free_i32(t0); 1953 tcg_temp_free_i32(t1); 1954 } else { 1955 #if defined(TARGET_PPC64) 1956 TCGv_i64 t0 = tcg_temp_new_i64(); 1957 tcg_gen_andi_i64(t0, t_rb, 0x1f); 1958 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1959 tcg_gen_rotl_i64(t_ra, t_ra, t0); 1960 tcg_temp_free_i64(t0); 1961 #else 1962 g_assert_not_reached(); 1963 #endif 1964 } 1965 1966 tcg_gen_andi_tl(t_ra, t_ra, mask); 1967 1968 if (unlikely(Rc(ctx->opcode) != 0)) { 1969 gen_set_Rc0(ctx, t_ra); 1970 } 1971 } 1972 1973 #if defined(TARGET_PPC64) 1974 #define GEN_PPC64_R2(name, opc1, opc2) \ 1975 static void glue(gen_, name##0)(DisasContext *ctx) \ 1976 { \ 1977 gen_##name(ctx, 0); \ 1978 } \ 1979 \ 1980 static void glue(gen_, name##1)(DisasContext *ctx) \ 1981 { \ 1982 gen_##name(ctx, 1); \ 1983 } 1984 #define GEN_PPC64_R4(name, opc1, opc2) \ 1985 static void glue(gen_, name##0)(DisasContext *ctx) \ 1986 { \ 1987 gen_##name(ctx, 0, 0); \ 1988 } \ 1989 \ 1990 static void glue(gen_, name##1)(DisasContext *ctx) \ 1991 { \ 1992 gen_##name(ctx, 0, 1); \ 1993 } \ 1994 \ 1995 static void glue(gen_, name##2)(DisasContext *ctx) \ 1996 { \ 1997 gen_##name(ctx, 1, 0); \ 1998 } \ 1999 \ 2000 static void glue(gen_, name##3)(DisasContext *ctx) \ 2001 { \ 2002 gen_##name(ctx, 1, 1); \ 2003 } 2004 2005 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2006 { 2007 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2008 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2009 int len = me - mb + 1; 2010 int rsh = (64 - sh) & 63; 2011 2012 if (sh != 0 && len > 0 && me == (63 - sh)) { 2013 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2014 } else if (me == 63 && rsh + len <= 64) { 2015 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2016 } else { 2017 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2018 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2019 } 2020 if (unlikely(Rc(ctx->opcode) != 0)) { 2021 gen_set_Rc0(ctx, t_ra); 2022 } 2023 } 2024 2025 /* rldicl - rldicl. */ 2026 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2027 { 2028 uint32_t sh, mb; 2029 2030 sh = SH(ctx->opcode) | (shn << 5); 2031 mb = MB(ctx->opcode) | (mbn << 5); 2032 gen_rldinm(ctx, mb, 63, sh); 2033 } 2034 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2035 2036 /* rldicr - rldicr. */ 2037 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2038 { 2039 uint32_t sh, me; 2040 2041 sh = SH(ctx->opcode) | (shn << 5); 2042 me = MB(ctx->opcode) | (men << 5); 2043 gen_rldinm(ctx, 0, me, sh); 2044 } 2045 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2046 2047 /* rldic - rldic. */ 2048 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2049 { 2050 uint32_t sh, mb; 2051 2052 sh = SH(ctx->opcode) | (shn << 5); 2053 mb = MB(ctx->opcode) | (mbn << 5); 2054 gen_rldinm(ctx, mb, 63 - sh, sh); 2055 } 2056 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2057 2058 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2059 { 2060 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2061 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2062 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2063 TCGv t0; 2064 2065 t0 = tcg_temp_new(); 2066 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2067 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2068 tcg_temp_free(t0); 2069 2070 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2071 if (unlikely(Rc(ctx->opcode) != 0)) { 2072 gen_set_Rc0(ctx, t_ra); 2073 } 2074 } 2075 2076 /* rldcl - rldcl. */ 2077 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2078 { 2079 uint32_t mb; 2080 2081 mb = MB(ctx->opcode) | (mbn << 5); 2082 gen_rldnm(ctx, mb, 63); 2083 } 2084 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2085 2086 /* rldcr - rldcr. */ 2087 static inline void gen_rldcr(DisasContext *ctx, int men) 2088 { 2089 uint32_t me; 2090 2091 me = MB(ctx->opcode) | (men << 5); 2092 gen_rldnm(ctx, 0, me); 2093 } 2094 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2095 2096 /* rldimi - rldimi. */ 2097 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2098 { 2099 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2100 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2101 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2102 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2103 uint32_t me = 63 - sh; 2104 2105 if (mb <= me) { 2106 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2107 } else { 2108 target_ulong mask = MASK(mb, me); 2109 TCGv t1 = tcg_temp_new(); 2110 2111 tcg_gen_rotli_tl(t1, t_rs, sh); 2112 tcg_gen_andi_tl(t1, t1, mask); 2113 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2114 tcg_gen_or_tl(t_ra, t_ra, t1); 2115 tcg_temp_free(t1); 2116 } 2117 if (unlikely(Rc(ctx->opcode) != 0)) { 2118 gen_set_Rc0(ctx, t_ra); 2119 } 2120 } 2121 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2122 #endif 2123 2124 /*** Integer shift ***/ 2125 2126 /* slw & slw. */ 2127 static void gen_slw(DisasContext *ctx) 2128 { 2129 TCGv t0, t1; 2130 2131 t0 = tcg_temp_new(); 2132 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2133 #if defined(TARGET_PPC64) 2134 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2135 tcg_gen_sari_tl(t0, t0, 0x3f); 2136 #else 2137 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2138 tcg_gen_sari_tl(t0, t0, 0x1f); 2139 #endif 2140 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2141 t1 = tcg_temp_new(); 2142 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2143 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2144 tcg_temp_free(t1); 2145 tcg_temp_free(t0); 2146 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2147 if (unlikely(Rc(ctx->opcode) != 0)) 2148 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2149 } 2150 2151 /* sraw & sraw. */ 2152 static void gen_sraw(DisasContext *ctx) 2153 { 2154 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2155 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2156 if (unlikely(Rc(ctx->opcode) != 0)) 2157 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2158 } 2159 2160 /* srawi & srawi. */ 2161 static void gen_srawi(DisasContext *ctx) 2162 { 2163 int sh = SH(ctx->opcode); 2164 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2165 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2166 if (sh == 0) { 2167 tcg_gen_ext32s_tl(dst, src); 2168 tcg_gen_movi_tl(cpu_ca, 0); 2169 if (is_isa300(ctx)) { 2170 tcg_gen_movi_tl(cpu_ca32, 0); 2171 } 2172 } else { 2173 TCGv t0; 2174 tcg_gen_ext32s_tl(dst, src); 2175 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2176 t0 = tcg_temp_new(); 2177 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2178 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2179 tcg_temp_free(t0); 2180 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2181 if (is_isa300(ctx)) { 2182 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2183 } 2184 tcg_gen_sari_tl(dst, dst, sh); 2185 } 2186 if (unlikely(Rc(ctx->opcode) != 0)) { 2187 gen_set_Rc0(ctx, dst); 2188 } 2189 } 2190 2191 /* srw & srw. */ 2192 static void gen_srw(DisasContext *ctx) 2193 { 2194 TCGv t0, t1; 2195 2196 t0 = tcg_temp_new(); 2197 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2198 #if defined(TARGET_PPC64) 2199 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2200 tcg_gen_sari_tl(t0, t0, 0x3f); 2201 #else 2202 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2203 tcg_gen_sari_tl(t0, t0, 0x1f); 2204 #endif 2205 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2206 tcg_gen_ext32u_tl(t0, t0); 2207 t1 = tcg_temp_new(); 2208 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2209 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2210 tcg_temp_free(t1); 2211 tcg_temp_free(t0); 2212 if (unlikely(Rc(ctx->opcode) != 0)) 2213 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2214 } 2215 2216 #if defined(TARGET_PPC64) 2217 /* sld & sld. */ 2218 static void gen_sld(DisasContext *ctx) 2219 { 2220 TCGv t0, t1; 2221 2222 t0 = tcg_temp_new(); 2223 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2224 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2225 tcg_gen_sari_tl(t0, t0, 0x3f); 2226 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2227 t1 = tcg_temp_new(); 2228 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2229 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2230 tcg_temp_free(t1); 2231 tcg_temp_free(t0); 2232 if (unlikely(Rc(ctx->opcode) != 0)) 2233 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2234 } 2235 2236 /* srad & srad. */ 2237 static void gen_srad(DisasContext *ctx) 2238 { 2239 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2240 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2241 if (unlikely(Rc(ctx->opcode) != 0)) 2242 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2243 } 2244 /* sradi & sradi. */ 2245 static inline void gen_sradi(DisasContext *ctx, int n) 2246 { 2247 int sh = SH(ctx->opcode) + (n << 5); 2248 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2249 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2250 if (sh == 0) { 2251 tcg_gen_mov_tl(dst, src); 2252 tcg_gen_movi_tl(cpu_ca, 0); 2253 if (is_isa300(ctx)) { 2254 tcg_gen_movi_tl(cpu_ca32, 0); 2255 } 2256 } else { 2257 TCGv t0; 2258 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2259 t0 = tcg_temp_new(); 2260 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2261 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2262 tcg_temp_free(t0); 2263 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2264 if (is_isa300(ctx)) { 2265 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2266 } 2267 tcg_gen_sari_tl(dst, src, sh); 2268 } 2269 if (unlikely(Rc(ctx->opcode) != 0)) { 2270 gen_set_Rc0(ctx, dst); 2271 } 2272 } 2273 2274 static void gen_sradi0(DisasContext *ctx) 2275 { 2276 gen_sradi(ctx, 0); 2277 } 2278 2279 static void gen_sradi1(DisasContext *ctx) 2280 { 2281 gen_sradi(ctx, 1); 2282 } 2283 2284 /* extswsli & extswsli. */ 2285 static inline void gen_extswsli(DisasContext *ctx, int n) 2286 { 2287 int sh = SH(ctx->opcode) + (n << 5); 2288 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2289 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2290 2291 tcg_gen_ext32s_tl(dst, src); 2292 tcg_gen_shli_tl(dst, dst, sh); 2293 if (unlikely(Rc(ctx->opcode) != 0)) { 2294 gen_set_Rc0(ctx, dst); 2295 } 2296 } 2297 2298 static void gen_extswsli0(DisasContext *ctx) 2299 { 2300 gen_extswsli(ctx, 0); 2301 } 2302 2303 static void gen_extswsli1(DisasContext *ctx) 2304 { 2305 gen_extswsli(ctx, 1); 2306 } 2307 2308 /* srd & srd. */ 2309 static void gen_srd(DisasContext *ctx) 2310 { 2311 TCGv t0, t1; 2312 2313 t0 = tcg_temp_new(); 2314 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2315 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2316 tcg_gen_sari_tl(t0, t0, 0x3f); 2317 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2318 t1 = tcg_temp_new(); 2319 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2320 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2321 tcg_temp_free(t1); 2322 tcg_temp_free(t0); 2323 if (unlikely(Rc(ctx->opcode) != 0)) 2324 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2325 } 2326 #endif 2327 2328 /*** Addressing modes ***/ 2329 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2330 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2331 target_long maskl) 2332 { 2333 target_long simm = SIMM(ctx->opcode); 2334 2335 simm &= ~maskl; 2336 if (rA(ctx->opcode) == 0) { 2337 if (NARROW_MODE(ctx)) { 2338 simm = (uint32_t)simm; 2339 } 2340 tcg_gen_movi_tl(EA, simm); 2341 } else if (likely(simm != 0)) { 2342 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2343 if (NARROW_MODE(ctx)) { 2344 tcg_gen_ext32u_tl(EA, EA); 2345 } 2346 } else { 2347 if (NARROW_MODE(ctx)) { 2348 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2349 } else { 2350 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2351 } 2352 } 2353 } 2354 2355 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2356 { 2357 if (rA(ctx->opcode) == 0) { 2358 if (NARROW_MODE(ctx)) { 2359 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2360 } else { 2361 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2362 } 2363 } else { 2364 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2365 if (NARROW_MODE(ctx)) { 2366 tcg_gen_ext32u_tl(EA, EA); 2367 } 2368 } 2369 } 2370 2371 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2372 { 2373 if (rA(ctx->opcode) == 0) { 2374 tcg_gen_movi_tl(EA, 0); 2375 } else if (NARROW_MODE(ctx)) { 2376 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2377 } else { 2378 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2379 } 2380 } 2381 2382 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2383 target_long val) 2384 { 2385 tcg_gen_addi_tl(ret, arg1, val); 2386 if (NARROW_MODE(ctx)) { 2387 tcg_gen_ext32u_tl(ret, ret); 2388 } 2389 } 2390 2391 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) 2392 { 2393 TCGLabel *l1 = gen_new_label(); 2394 TCGv t0 = tcg_temp_new(); 2395 TCGv_i32 t1, t2; 2396 tcg_gen_andi_tl(t0, EA, mask); 2397 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 2398 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); 2399 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); 2400 gen_update_nip(ctx, ctx->base.pc_next - 4); 2401 gen_helper_raise_exception_err(cpu_env, t1, t2); 2402 tcg_temp_free_i32(t1); 2403 tcg_temp_free_i32(t2); 2404 gen_set_label(l1); 2405 tcg_temp_free(t0); 2406 } 2407 2408 static inline void gen_align_no_le(DisasContext *ctx) 2409 { 2410 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2411 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2412 } 2413 2414 /*** Integer load ***/ 2415 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2416 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2417 2418 #define GEN_QEMU_LOAD_TL(ldop, op) \ 2419 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2420 TCGv val, \ 2421 TCGv addr) \ 2422 { \ 2423 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2424 } 2425 2426 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2427 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2428 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2429 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2430 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2431 2432 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2433 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2434 2435 #define GEN_QEMU_LOAD_64(ldop, op) \ 2436 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2437 TCGv_i64 val, \ 2438 TCGv addr) \ 2439 { \ 2440 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2441 } 2442 2443 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2444 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2445 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2446 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2447 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2448 2449 #if defined(TARGET_PPC64) 2450 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2451 #endif 2452 2453 #define GEN_QEMU_STORE_TL(stop, op) \ 2454 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2455 TCGv val, \ 2456 TCGv addr) \ 2457 { \ 2458 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2459 } 2460 2461 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2462 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2463 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2464 2465 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2466 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2467 2468 #define GEN_QEMU_STORE_64(stop, op) \ 2469 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2470 TCGv_i64 val, \ 2471 TCGv addr) \ 2472 { \ 2473 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2474 } 2475 2476 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2477 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2478 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2479 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2480 2481 #if defined(TARGET_PPC64) 2482 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2483 #endif 2484 2485 #define GEN_LD(name, ldop, opc, type) \ 2486 static void glue(gen_, name)(DisasContext *ctx) \ 2487 { \ 2488 TCGv EA; \ 2489 gen_set_access_type(ctx, ACCESS_INT); \ 2490 EA = tcg_temp_new(); \ 2491 gen_addr_imm_index(ctx, EA, 0); \ 2492 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2493 tcg_temp_free(EA); \ 2494 } 2495 2496 #define GEN_LDU(name, ldop, opc, type) \ 2497 static void glue(gen_, name##u)(DisasContext *ctx) \ 2498 { \ 2499 TCGv EA; \ 2500 if (unlikely(rA(ctx->opcode) == 0 || \ 2501 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2502 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2503 return; \ 2504 } \ 2505 gen_set_access_type(ctx, ACCESS_INT); \ 2506 EA = tcg_temp_new(); \ 2507 if (type == PPC_64B) \ 2508 gen_addr_imm_index(ctx, EA, 0x03); \ 2509 else \ 2510 gen_addr_imm_index(ctx, EA, 0); \ 2511 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2512 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2513 tcg_temp_free(EA); \ 2514 } 2515 2516 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2517 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2518 { \ 2519 TCGv EA; \ 2520 if (unlikely(rA(ctx->opcode) == 0 || \ 2521 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2522 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2523 return; \ 2524 } \ 2525 gen_set_access_type(ctx, ACCESS_INT); \ 2526 EA = tcg_temp_new(); \ 2527 gen_addr_reg_index(ctx, EA); \ 2528 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2529 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2530 tcg_temp_free(EA); \ 2531 } 2532 2533 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2534 static void glue(gen_, name##x)(DisasContext *ctx) \ 2535 { \ 2536 TCGv EA; \ 2537 chk; \ 2538 gen_set_access_type(ctx, ACCESS_INT); \ 2539 EA = tcg_temp_new(); \ 2540 gen_addr_reg_index(ctx, EA); \ 2541 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2542 tcg_temp_free(EA); \ 2543 } 2544 2545 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2546 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2547 2548 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2549 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2550 2551 #define GEN_LDS(name, ldop, op, type) \ 2552 GEN_LD(name, ldop, op | 0x20, type); \ 2553 GEN_LDU(name, ldop, op | 0x21, type); \ 2554 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2555 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2556 2557 /* lbz lbzu lbzux lbzx */ 2558 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2559 /* lha lhau lhaux lhax */ 2560 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2561 /* lhz lhzu lhzux lhzx */ 2562 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2563 /* lwz lwzu lwzux lwzx */ 2564 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2565 #if defined(TARGET_PPC64) 2566 /* lwaux */ 2567 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2568 /* lwax */ 2569 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2570 /* ldux */ 2571 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2572 /* ldx */ 2573 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2574 2575 /* CI load/store variants */ 2576 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2577 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2578 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2579 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2580 2581 static void gen_ld(DisasContext *ctx) 2582 { 2583 TCGv EA; 2584 if (Rc(ctx->opcode)) { 2585 if (unlikely(rA(ctx->opcode) == 0 || 2586 rA(ctx->opcode) == rD(ctx->opcode))) { 2587 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2588 return; 2589 } 2590 } 2591 gen_set_access_type(ctx, ACCESS_INT); 2592 EA = tcg_temp_new(); 2593 gen_addr_imm_index(ctx, EA, 0x03); 2594 if (ctx->opcode & 0x02) { 2595 /* lwa (lwau is undefined) */ 2596 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2597 } else { 2598 /* ld - ldu */ 2599 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2600 } 2601 if (Rc(ctx->opcode)) 2602 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2603 tcg_temp_free(EA); 2604 } 2605 2606 /* lq */ 2607 static void gen_lq(DisasContext *ctx) 2608 { 2609 int ra, rd; 2610 TCGv EA; 2611 2612 /* lq is a legal user mode instruction starting in ISA 2.07 */ 2613 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2614 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2615 2616 if (!legal_in_user_mode && ctx->pr) { 2617 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2618 return; 2619 } 2620 2621 if (!le_is_supported && ctx->le_mode) { 2622 gen_align_no_le(ctx); 2623 return; 2624 } 2625 ra = rA(ctx->opcode); 2626 rd = rD(ctx->opcode); 2627 if (unlikely((rd & 1) || rd == ra)) { 2628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2629 return; 2630 } 2631 2632 gen_set_access_type(ctx, ACCESS_INT); 2633 EA = tcg_temp_new(); 2634 gen_addr_imm_index(ctx, EA, 0x0F); 2635 2636 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does 2637 necessary 64-bit byteswap already. */ 2638 if (unlikely(ctx->le_mode)) { 2639 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2640 gen_addr_add(ctx, EA, EA, 8); 2641 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2642 } else { 2643 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2644 gen_addr_add(ctx, EA, EA, 8); 2645 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2646 } 2647 tcg_temp_free(EA); 2648 } 2649 #endif 2650 2651 /*** Integer store ***/ 2652 #define GEN_ST(name, stop, opc, type) \ 2653 static void glue(gen_, name)(DisasContext *ctx) \ 2654 { \ 2655 TCGv EA; \ 2656 gen_set_access_type(ctx, ACCESS_INT); \ 2657 EA = tcg_temp_new(); \ 2658 gen_addr_imm_index(ctx, EA, 0); \ 2659 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2660 tcg_temp_free(EA); \ 2661 } 2662 2663 #define GEN_STU(name, stop, opc, type) \ 2664 static void glue(gen_, stop##u)(DisasContext *ctx) \ 2665 { \ 2666 TCGv EA; \ 2667 if (unlikely(rA(ctx->opcode) == 0)) { \ 2668 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2669 return; \ 2670 } \ 2671 gen_set_access_type(ctx, ACCESS_INT); \ 2672 EA = tcg_temp_new(); \ 2673 if (type == PPC_64B) \ 2674 gen_addr_imm_index(ctx, EA, 0x03); \ 2675 else \ 2676 gen_addr_imm_index(ctx, EA, 0); \ 2677 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2678 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2679 tcg_temp_free(EA); \ 2680 } 2681 2682 #define GEN_STUX(name, stop, opc2, opc3, type) \ 2683 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2684 { \ 2685 TCGv EA; \ 2686 if (unlikely(rA(ctx->opcode) == 0)) { \ 2687 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2688 return; \ 2689 } \ 2690 gen_set_access_type(ctx, ACCESS_INT); \ 2691 EA = tcg_temp_new(); \ 2692 gen_addr_reg_index(ctx, EA); \ 2693 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2694 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2695 tcg_temp_free(EA); \ 2696 } 2697 2698 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2699 static void glue(gen_, name##x)(DisasContext *ctx) \ 2700 { \ 2701 TCGv EA; \ 2702 chk; \ 2703 gen_set_access_type(ctx, ACCESS_INT); \ 2704 EA = tcg_temp_new(); \ 2705 gen_addr_reg_index(ctx, EA); \ 2706 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2707 tcg_temp_free(EA); \ 2708 } 2709 #define GEN_STX(name, stop, opc2, opc3, type) \ 2710 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2711 2712 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2713 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2714 2715 #define GEN_STS(name, stop, op, type) \ 2716 GEN_ST(name, stop, op | 0x20, type); \ 2717 GEN_STU(name, stop, op | 0x21, type); \ 2718 GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2719 GEN_STX(name, stop, 0x17, op | 0x00, type) 2720 2721 /* stb stbu stbux stbx */ 2722 GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2723 /* sth sthu sthux sthx */ 2724 GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2725 /* stw stwu stwux stwx */ 2726 GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2727 #if defined(TARGET_PPC64) 2728 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2729 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2730 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2731 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2732 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2733 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2734 2735 static void gen_std(DisasContext *ctx) 2736 { 2737 int rs; 2738 TCGv EA; 2739 2740 rs = rS(ctx->opcode); 2741 if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2742 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2743 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2744 2745 if (!(ctx->insns_flags & PPC_64BX)) { 2746 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2747 } 2748 2749 if (!legal_in_user_mode && ctx->pr) { 2750 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2751 return; 2752 } 2753 2754 if (!le_is_supported && ctx->le_mode) { 2755 gen_align_no_le(ctx); 2756 return; 2757 } 2758 2759 if (unlikely(rs & 1)) { 2760 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2761 return; 2762 } 2763 gen_set_access_type(ctx, ACCESS_INT); 2764 EA = tcg_temp_new(); 2765 gen_addr_imm_index(ctx, EA, 0x03); 2766 2767 /* We only need to swap high and low halves. gen_qemu_st64_i64 does 2768 necessary 64-bit byteswap already. */ 2769 if (unlikely(ctx->le_mode)) { 2770 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2771 gen_addr_add(ctx, EA, EA, 8); 2772 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2773 } else { 2774 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2775 gen_addr_add(ctx, EA, EA, 8); 2776 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2777 } 2778 tcg_temp_free(EA); 2779 } else { 2780 /* std / stdu*/ 2781 if (Rc(ctx->opcode)) { 2782 if (unlikely(rA(ctx->opcode) == 0)) { 2783 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2784 return; 2785 } 2786 } 2787 gen_set_access_type(ctx, ACCESS_INT); 2788 EA = tcg_temp_new(); 2789 gen_addr_imm_index(ctx, EA, 0x03); 2790 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2791 if (Rc(ctx->opcode)) 2792 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2793 tcg_temp_free(EA); 2794 } 2795 } 2796 #endif 2797 /*** Integer load and store with byte reverse ***/ 2798 2799 /* lhbrx */ 2800 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2801 2802 /* lwbrx */ 2803 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2804 2805 #if defined(TARGET_PPC64) 2806 /* ldbrx */ 2807 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2808 /* stdbrx */ 2809 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2810 #endif /* TARGET_PPC64 */ 2811 2812 /* sthbrx */ 2813 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2814 /* stwbrx */ 2815 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2816 2817 /*** Integer load and store multiple ***/ 2818 2819 /* lmw */ 2820 static void gen_lmw(DisasContext *ctx) 2821 { 2822 TCGv t0; 2823 TCGv_i32 t1; 2824 2825 if (ctx->le_mode) { 2826 gen_align_no_le(ctx); 2827 return; 2828 } 2829 gen_set_access_type(ctx, ACCESS_INT); 2830 t0 = tcg_temp_new(); 2831 t1 = tcg_const_i32(rD(ctx->opcode)); 2832 gen_addr_imm_index(ctx, t0, 0); 2833 gen_helper_lmw(cpu_env, t0, t1); 2834 tcg_temp_free(t0); 2835 tcg_temp_free_i32(t1); 2836 } 2837 2838 /* stmw */ 2839 static void gen_stmw(DisasContext *ctx) 2840 { 2841 TCGv t0; 2842 TCGv_i32 t1; 2843 2844 if (ctx->le_mode) { 2845 gen_align_no_le(ctx); 2846 return; 2847 } 2848 gen_set_access_type(ctx, ACCESS_INT); 2849 t0 = tcg_temp_new(); 2850 t1 = tcg_const_i32(rS(ctx->opcode)); 2851 gen_addr_imm_index(ctx, t0, 0); 2852 gen_helper_stmw(cpu_env, t0, t1); 2853 tcg_temp_free(t0); 2854 tcg_temp_free_i32(t1); 2855 } 2856 2857 /*** Integer load and store strings ***/ 2858 2859 /* lswi */ 2860 /* PowerPC32 specification says we must generate an exception if 2861 * rA is in the range of registers to be loaded. 2862 * In an other hand, IBM says this is valid, but rA won't be loaded. 2863 * For now, I'll follow the spec... 2864 */ 2865 static void gen_lswi(DisasContext *ctx) 2866 { 2867 TCGv t0; 2868 TCGv_i32 t1, t2; 2869 int nb = NB(ctx->opcode); 2870 int start = rD(ctx->opcode); 2871 int ra = rA(ctx->opcode); 2872 int nr; 2873 2874 if (ctx->le_mode) { 2875 gen_align_no_le(ctx); 2876 return; 2877 } 2878 if (nb == 0) 2879 nb = 32; 2880 nr = DIV_ROUND_UP(nb, 4); 2881 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2882 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2883 return; 2884 } 2885 gen_set_access_type(ctx, ACCESS_INT); 2886 t0 = tcg_temp_new(); 2887 gen_addr_register(ctx, t0); 2888 t1 = tcg_const_i32(nb); 2889 t2 = tcg_const_i32(start); 2890 gen_helper_lsw(cpu_env, t0, t1, t2); 2891 tcg_temp_free(t0); 2892 tcg_temp_free_i32(t1); 2893 tcg_temp_free_i32(t2); 2894 } 2895 2896 /* lswx */ 2897 static void gen_lswx(DisasContext *ctx) 2898 { 2899 TCGv t0; 2900 TCGv_i32 t1, t2, t3; 2901 2902 if (ctx->le_mode) { 2903 gen_align_no_le(ctx); 2904 return; 2905 } 2906 gen_set_access_type(ctx, ACCESS_INT); 2907 t0 = tcg_temp_new(); 2908 gen_addr_reg_index(ctx, t0); 2909 t1 = tcg_const_i32(rD(ctx->opcode)); 2910 t2 = tcg_const_i32(rA(ctx->opcode)); 2911 t3 = tcg_const_i32(rB(ctx->opcode)); 2912 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 2913 tcg_temp_free(t0); 2914 tcg_temp_free_i32(t1); 2915 tcg_temp_free_i32(t2); 2916 tcg_temp_free_i32(t3); 2917 } 2918 2919 /* stswi */ 2920 static void gen_stswi(DisasContext *ctx) 2921 { 2922 TCGv t0; 2923 TCGv_i32 t1, t2; 2924 int nb = NB(ctx->opcode); 2925 2926 if (ctx->le_mode) { 2927 gen_align_no_le(ctx); 2928 return; 2929 } 2930 gen_set_access_type(ctx, ACCESS_INT); 2931 t0 = tcg_temp_new(); 2932 gen_addr_register(ctx, t0); 2933 if (nb == 0) 2934 nb = 32; 2935 t1 = tcg_const_i32(nb); 2936 t2 = tcg_const_i32(rS(ctx->opcode)); 2937 gen_helper_stsw(cpu_env, t0, t1, t2); 2938 tcg_temp_free(t0); 2939 tcg_temp_free_i32(t1); 2940 tcg_temp_free_i32(t2); 2941 } 2942 2943 /* stswx */ 2944 static void gen_stswx(DisasContext *ctx) 2945 { 2946 TCGv t0; 2947 TCGv_i32 t1, t2; 2948 2949 if (ctx->le_mode) { 2950 gen_align_no_le(ctx); 2951 return; 2952 } 2953 gen_set_access_type(ctx, ACCESS_INT); 2954 t0 = tcg_temp_new(); 2955 gen_addr_reg_index(ctx, t0); 2956 t1 = tcg_temp_new_i32(); 2957 tcg_gen_trunc_tl_i32(t1, cpu_xer); 2958 tcg_gen_andi_i32(t1, t1, 0x7F); 2959 t2 = tcg_const_i32(rS(ctx->opcode)); 2960 gen_helper_stsw(cpu_env, t0, t1, t2); 2961 tcg_temp_free(t0); 2962 tcg_temp_free_i32(t1); 2963 tcg_temp_free_i32(t2); 2964 } 2965 2966 /*** Memory synchronisation ***/ 2967 /* eieio */ 2968 static void gen_eieio(DisasContext *ctx) 2969 { 2970 tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC); 2971 } 2972 2973 #if !defined(CONFIG_USER_ONLY) 2974 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 2975 { 2976 TCGv_i32 t; 2977 TCGLabel *l; 2978 2979 if (!ctx->lazy_tlb_flush) { 2980 return; 2981 } 2982 l = gen_new_label(); 2983 t = tcg_temp_new_i32(); 2984 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 2985 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 2986 if (global) { 2987 gen_helper_check_tlb_flush_global(cpu_env); 2988 } else { 2989 gen_helper_check_tlb_flush_local(cpu_env); 2990 } 2991 gen_set_label(l); 2992 tcg_temp_free_i32(t); 2993 } 2994 #else 2995 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 2996 #endif 2997 2998 /* isync */ 2999 static void gen_isync(DisasContext *ctx) 3000 { 3001 /* 3002 * We need to check for a pending TLB flush. This can only happen in 3003 * kernel mode however so check MSR_PR 3004 */ 3005 if (!ctx->pr) { 3006 gen_check_tlb_flush(ctx, false); 3007 } 3008 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3009 gen_stop_exception(ctx); 3010 } 3011 3012 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3013 3014 #define LARX(name, memop) \ 3015 static void gen_##name(DisasContext *ctx) \ 3016 { \ 3017 TCGv t0; \ 3018 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ 3019 int len = MEMOP_GET_SIZE(memop); \ 3020 gen_set_access_type(ctx, ACCESS_RES); \ 3021 t0 = tcg_temp_local_new(); \ 3022 gen_addr_reg_index(ctx, t0); \ 3023 if ((len) > 1) { \ 3024 gen_check_align(ctx, t0, (len)-1); \ 3025 } \ 3026 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ 3027 tcg_gen_mov_tl(cpu_reserve, t0); \ 3028 tcg_gen_mov_tl(cpu_reserve_val, gpr); \ 3029 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \ 3030 tcg_temp_free(t0); \ 3031 } 3032 3033 /* lwarx */ 3034 LARX(lbarx, DEF_MEMOP(MO_UB)) 3035 LARX(lharx, DEF_MEMOP(MO_UW)) 3036 LARX(lwarx, DEF_MEMOP(MO_UL)) 3037 3038 #define LD_ATOMIC(name, memop, tp, op, eop) \ 3039 static void gen_##name(DisasContext *ctx) \ 3040 { \ 3041 int len = MEMOP_GET_SIZE(memop); \ 3042 uint32_t gpr_FC = FC(ctx->opcode); \ 3043 TCGv EA = tcg_temp_local_new(); \ 3044 TCGv_##tp t0, t1; \ 3045 \ 3046 gen_addr_register(ctx, EA); \ 3047 if (len > 1) { \ 3048 gen_check_align(ctx, EA, len - 1); \ 3049 } \ 3050 t0 = tcg_temp_new_##tp(); \ 3051 t1 = tcg_temp_new_##tp(); \ 3052 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3053 \ 3054 switch (gpr_FC) { \ 3055 case 0: /* Fetch and add */ \ 3056 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3057 break; \ 3058 case 1: /* Fetch and xor */ \ 3059 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3060 break; \ 3061 case 2: /* Fetch and or */ \ 3062 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3063 break; \ 3064 case 3: /* Fetch and 'and' */ \ 3065 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3066 break; \ 3067 case 8: /* Swap */ \ 3068 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3069 break; \ 3070 case 4: /* Fetch and max unsigned */ \ 3071 case 5: /* Fetch and max signed */ \ 3072 case 6: /* Fetch and min unsigned */ \ 3073 case 7: /* Fetch and min signed */ \ 3074 case 16: /* compare and swap not equal */ \ 3075 case 24: /* Fetch and increment bounded */ \ 3076 case 25: /* Fetch and increment equal */ \ 3077 case 28: /* Fetch and decrement bounded */ \ 3078 gen_invalid(ctx); \ 3079 break; \ 3080 default: \ 3081 /* invoke data storage error handler */ \ 3082 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3083 } \ 3084 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \ 3085 tcg_temp_free_##tp(t0); \ 3086 tcg_temp_free_##tp(t1); \ 3087 tcg_temp_free(EA); \ 3088 } 3089 3090 LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl) 3091 #if defined(TARGET_PPC64) 3092 LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64) 3093 #endif 3094 3095 #define ST_ATOMIC(name, memop, tp, op) \ 3096 static void gen_##name(DisasContext *ctx) \ 3097 { \ 3098 int len = MEMOP_GET_SIZE(memop); \ 3099 uint32_t gpr_FC = FC(ctx->opcode); \ 3100 TCGv EA = tcg_temp_local_new(); \ 3101 TCGv_##tp t0, t1; \ 3102 \ 3103 gen_addr_register(ctx, EA); \ 3104 if (len > 1) { \ 3105 gen_check_align(ctx, EA, len - 1); \ 3106 } \ 3107 t0 = tcg_temp_new_##tp(); \ 3108 t1 = tcg_temp_new_##tp(); \ 3109 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3110 \ 3111 switch (gpr_FC) { \ 3112 case 0: /* add and Store */ \ 3113 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3114 break; \ 3115 case 1: /* xor and Store */ \ 3116 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3117 break; \ 3118 case 2: /* Or and Store */ \ 3119 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3120 break; \ 3121 case 3: /* 'and' and Store */ \ 3122 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3123 break; \ 3124 case 4: /* Store max unsigned */ \ 3125 case 5: /* Store max signed */ \ 3126 case 6: /* Store min unsigned */ \ 3127 case 7: /* Store min signed */ \ 3128 case 24: /* Store twin */ \ 3129 gen_invalid(ctx); \ 3130 break; \ 3131 default: \ 3132 /* invoke data storage error handler */ \ 3133 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3134 } \ 3135 tcg_temp_free_##tp(t0); \ 3136 tcg_temp_free_##tp(t1); \ 3137 tcg_temp_free(EA); \ 3138 } 3139 3140 ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) 3141 #if defined(TARGET_PPC64) 3142 ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) 3143 #endif 3144 3145 #if defined(CONFIG_USER_ONLY) 3146 static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3147 int reg, int memop) 3148 { 3149 TCGv t0 = tcg_temp_new(); 3150 3151 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); 3152 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); 3153 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); 3154 tcg_temp_free(t0); 3155 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); 3156 } 3157 #else 3158 static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3159 int reg, int memop) 3160 { 3161 TCGLabel *l1 = gen_new_label(); 3162 TCGLabel *l2 = gen_new_label(); 3163 TCGv t0; 3164 3165 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3166 3167 t0 = tcg_temp_new(); 3168 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3169 cpu_gpr[reg], ctx->mem_idx, 3170 DEF_MEMOP(memop) | MO_ALIGN); 3171 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3172 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3173 tcg_gen_or_tl(t0, t0, cpu_so); 3174 tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3175 tcg_temp_free(t0); 3176 tcg_gen_br(l2); 3177 3178 gen_set_label(l1); 3179 3180 /* Address mismatch implies failure. But we still need to provide the 3181 memory barrier semantics of the instruction. */ 3182 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3183 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3184 3185 gen_set_label(l2); 3186 tcg_gen_movi_tl(cpu_reserve, -1); 3187 } 3188 #endif 3189 3190 #define STCX(name, memop) \ 3191 static void gen_##name(DisasContext *ctx) \ 3192 { \ 3193 TCGv t0; \ 3194 int len = MEMOP_GET_SIZE(memop); \ 3195 gen_set_access_type(ctx, ACCESS_RES); \ 3196 t0 = tcg_temp_local_new(); \ 3197 gen_addr_reg_index(ctx, t0); \ 3198 if (len > 1) { \ 3199 gen_check_align(ctx, t0, (len) - 1); \ 3200 } \ 3201 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ 3202 tcg_temp_free(t0); \ 3203 } 3204 3205 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3206 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3207 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3208 3209 #if defined(TARGET_PPC64) 3210 /* ldarx */ 3211 LARX(ldarx, DEF_MEMOP(MO_Q)) 3212 /* stdcx. */ 3213 STCX(stdcx_, DEF_MEMOP(MO_Q)) 3214 3215 /* lqarx */ 3216 static void gen_lqarx(DisasContext *ctx) 3217 { 3218 TCGv EA; 3219 int rd = rD(ctx->opcode); 3220 TCGv gpr1, gpr2; 3221 3222 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3223 (rd == rB(ctx->opcode)))) { 3224 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3225 return; 3226 } 3227 3228 gen_set_access_type(ctx, ACCESS_RES); 3229 EA = tcg_temp_local_new(); 3230 gen_addr_reg_index(ctx, EA); 3231 gen_check_align(ctx, EA, 15); 3232 if (unlikely(ctx->le_mode)) { 3233 gpr1 = cpu_gpr[rd+1]; 3234 gpr2 = cpu_gpr[rd]; 3235 } else { 3236 gpr1 = cpu_gpr[rd]; 3237 gpr2 = cpu_gpr[rd+1]; 3238 } 3239 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3240 tcg_gen_mov_tl(cpu_reserve, EA); 3241 gen_addr_add(ctx, EA, EA, 8); 3242 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3243 3244 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); 3245 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3246 tcg_temp_free(EA); 3247 } 3248 3249 /* stqcx. */ 3250 static void gen_stqcx_(DisasContext *ctx) 3251 { 3252 TCGv EA; 3253 int reg = rS(ctx->opcode); 3254 int len = 16; 3255 #if !defined(CONFIG_USER_ONLY) 3256 TCGLabel *l1; 3257 TCGv gpr1, gpr2; 3258 #endif 3259 3260 if (unlikely((rD(ctx->opcode) & 1))) { 3261 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3262 return; 3263 } 3264 gen_set_access_type(ctx, ACCESS_RES); 3265 EA = tcg_temp_local_new(); 3266 gen_addr_reg_index(ctx, EA); 3267 if (len > 1) { 3268 gen_check_align(ctx, EA, (len) - 1); 3269 } 3270 3271 #if defined(CONFIG_USER_ONLY) 3272 gen_conditional_store(ctx, EA, reg, 16); 3273 #else 3274 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3275 l1 = gen_new_label(); 3276 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3277 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3278 3279 if (unlikely(ctx->le_mode)) { 3280 gpr1 = cpu_gpr[reg + 1]; 3281 gpr2 = cpu_gpr[reg]; 3282 } else { 3283 gpr1 = cpu_gpr[reg]; 3284 gpr2 = cpu_gpr[reg + 1]; 3285 } 3286 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3287 gen_addr_add(ctx, EA, EA, 8); 3288 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3289 3290 gen_set_label(l1); 3291 tcg_gen_movi_tl(cpu_reserve, -1); 3292 #endif 3293 tcg_temp_free(EA); 3294 } 3295 3296 #endif /* defined(TARGET_PPC64) */ 3297 3298 /* sync */ 3299 static void gen_sync(DisasContext *ctx) 3300 { 3301 uint32_t l = (ctx->opcode >> 21) & 3; 3302 3303 /* 3304 * We may need to check for a pending TLB flush. 3305 * 3306 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3307 * 3308 * Additionally, this can only happen in kernel mode however so 3309 * check MSR_PR as well. 3310 */ 3311 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3312 gen_check_tlb_flush(ctx, true); 3313 } 3314 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3315 } 3316 3317 /* wait */ 3318 static void gen_wait(DisasContext *ctx) 3319 { 3320 TCGv_i32 t0 = tcg_const_i32(1); 3321 tcg_gen_st_i32(t0, cpu_env, 3322 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3323 tcg_temp_free_i32(t0); 3324 /* Stop translation, as the CPU is supposed to sleep from now */ 3325 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3326 } 3327 3328 #if defined(TARGET_PPC64) 3329 static void gen_doze(DisasContext *ctx) 3330 { 3331 #if defined(CONFIG_USER_ONLY) 3332 GEN_PRIV; 3333 #else 3334 TCGv_i32 t; 3335 3336 CHK_HV; 3337 t = tcg_const_i32(PPC_PM_DOZE); 3338 gen_helper_pminsn(cpu_env, t); 3339 tcg_temp_free_i32(t); 3340 gen_stop_exception(ctx); 3341 #endif /* defined(CONFIG_USER_ONLY) */ 3342 } 3343 3344 static void gen_nap(DisasContext *ctx) 3345 { 3346 #if defined(CONFIG_USER_ONLY) 3347 GEN_PRIV; 3348 #else 3349 TCGv_i32 t; 3350 3351 CHK_HV; 3352 t = tcg_const_i32(PPC_PM_NAP); 3353 gen_helper_pminsn(cpu_env, t); 3354 tcg_temp_free_i32(t); 3355 gen_stop_exception(ctx); 3356 #endif /* defined(CONFIG_USER_ONLY) */ 3357 } 3358 3359 static void gen_stop(DisasContext *ctx) 3360 { 3361 gen_nap(ctx); 3362 } 3363 3364 static void gen_sleep(DisasContext *ctx) 3365 { 3366 #if defined(CONFIG_USER_ONLY) 3367 GEN_PRIV; 3368 #else 3369 TCGv_i32 t; 3370 3371 CHK_HV; 3372 t = tcg_const_i32(PPC_PM_SLEEP); 3373 gen_helper_pminsn(cpu_env, t); 3374 tcg_temp_free_i32(t); 3375 gen_stop_exception(ctx); 3376 #endif /* defined(CONFIG_USER_ONLY) */ 3377 } 3378 3379 static void gen_rvwinkle(DisasContext *ctx) 3380 { 3381 #if defined(CONFIG_USER_ONLY) 3382 GEN_PRIV; 3383 #else 3384 TCGv_i32 t; 3385 3386 CHK_HV; 3387 t = tcg_const_i32(PPC_PM_RVWINKLE); 3388 gen_helper_pminsn(cpu_env, t); 3389 tcg_temp_free_i32(t); 3390 gen_stop_exception(ctx); 3391 #endif /* defined(CONFIG_USER_ONLY) */ 3392 } 3393 #endif /* #if defined(TARGET_PPC64) */ 3394 3395 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3396 { 3397 #if defined(TARGET_PPC64) 3398 if (ctx->has_cfar) 3399 tcg_gen_movi_tl(cpu_cfar, nip); 3400 #endif 3401 } 3402 3403 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3404 { 3405 if (unlikely(ctx->singlestep_enabled)) { 3406 return false; 3407 } 3408 3409 #ifndef CONFIG_USER_ONLY 3410 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3411 #else 3412 return true; 3413 #endif 3414 } 3415 3416 /*** Branch ***/ 3417 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3418 { 3419 if (NARROW_MODE(ctx)) { 3420 dest = (uint32_t) dest; 3421 } 3422 if (use_goto_tb(ctx, dest)) { 3423 tcg_gen_goto_tb(n); 3424 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3425 tcg_gen_exit_tb(ctx->base.tb, n); 3426 } else { 3427 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3428 if (unlikely(ctx->singlestep_enabled)) { 3429 if ((ctx->singlestep_enabled & 3430 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && 3431 (ctx->exception == POWERPC_EXCP_BRANCH || 3432 ctx->exception == POWERPC_EXCP_TRACE)) { 3433 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest); 3434 } 3435 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { 3436 gen_debug_exception(ctx); 3437 } 3438 } 3439 tcg_gen_lookup_and_goto_ptr(); 3440 } 3441 } 3442 3443 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3444 { 3445 if (NARROW_MODE(ctx)) { 3446 nip = (uint32_t)nip; 3447 } 3448 tcg_gen_movi_tl(cpu_lr, nip); 3449 } 3450 3451 /* b ba bl bla */ 3452 static void gen_b(DisasContext *ctx) 3453 { 3454 target_ulong li, target; 3455 3456 ctx->exception = POWERPC_EXCP_BRANCH; 3457 /* sign extend LI */ 3458 li = LI(ctx->opcode); 3459 li = (li ^ 0x02000000) - 0x02000000; 3460 if (likely(AA(ctx->opcode) == 0)) { 3461 target = ctx->base.pc_next + li - 4; 3462 } else { 3463 target = li; 3464 } 3465 if (LK(ctx->opcode)) { 3466 gen_setlr(ctx, ctx->base.pc_next); 3467 } 3468 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3469 gen_goto_tb(ctx, 0, target); 3470 } 3471 3472 #define BCOND_IM 0 3473 #define BCOND_LR 1 3474 #define BCOND_CTR 2 3475 #define BCOND_TAR 3 3476 3477 static void gen_bcond(DisasContext *ctx, int type) 3478 { 3479 uint32_t bo = BO(ctx->opcode); 3480 TCGLabel *l1; 3481 TCGv target; 3482 3483 ctx->exception = POWERPC_EXCP_BRANCH; 3484 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3485 target = tcg_temp_local_new(); 3486 if (type == BCOND_CTR) 3487 tcg_gen_mov_tl(target, cpu_ctr); 3488 else if (type == BCOND_TAR) 3489 gen_load_spr(target, SPR_TAR); 3490 else 3491 tcg_gen_mov_tl(target, cpu_lr); 3492 } else { 3493 target = NULL; 3494 } 3495 if (LK(ctx->opcode)) 3496 gen_setlr(ctx, ctx->base.pc_next); 3497 l1 = gen_new_label(); 3498 if ((bo & 0x4) == 0) { 3499 /* Decrement and test CTR */ 3500 TCGv temp = tcg_temp_new(); 3501 if (unlikely(type == BCOND_CTR)) { 3502 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3503 return; 3504 } 3505 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3506 if (NARROW_MODE(ctx)) { 3507 tcg_gen_ext32u_tl(temp, cpu_ctr); 3508 } else { 3509 tcg_gen_mov_tl(temp, cpu_ctr); 3510 } 3511 if (bo & 0x2) { 3512 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3513 } else { 3514 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3515 } 3516 tcg_temp_free(temp); 3517 } 3518 if ((bo & 0x10) == 0) { 3519 /* Test CR */ 3520 uint32_t bi = BI(ctx->opcode); 3521 uint32_t mask = 0x08 >> (bi & 0x03); 3522 TCGv_i32 temp = tcg_temp_new_i32(); 3523 3524 if (bo & 0x8) { 3525 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3526 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3527 } else { 3528 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3529 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3530 } 3531 tcg_temp_free_i32(temp); 3532 } 3533 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3534 if (type == BCOND_IM) { 3535 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3536 if (likely(AA(ctx->opcode) == 0)) { 3537 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3538 } else { 3539 gen_goto_tb(ctx, 0, li); 3540 } 3541 } else { 3542 if (NARROW_MODE(ctx)) { 3543 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3544 } else { 3545 tcg_gen_andi_tl(cpu_nip, target, ~3); 3546 } 3547 tcg_gen_lookup_and_goto_ptr(); 3548 tcg_temp_free(target); 3549 } 3550 if ((bo & 0x14) != 0x14) { 3551 gen_set_label(l1); 3552 gen_goto_tb(ctx, 1, ctx->base.pc_next); 3553 } 3554 } 3555 3556 static void gen_bc(DisasContext *ctx) 3557 { 3558 gen_bcond(ctx, BCOND_IM); 3559 } 3560 3561 static void gen_bcctr(DisasContext *ctx) 3562 { 3563 gen_bcond(ctx, BCOND_CTR); 3564 } 3565 3566 static void gen_bclr(DisasContext *ctx) 3567 { 3568 gen_bcond(ctx, BCOND_LR); 3569 } 3570 3571 static void gen_bctar(DisasContext *ctx) 3572 { 3573 gen_bcond(ctx, BCOND_TAR); 3574 } 3575 3576 /*** Condition register logical ***/ 3577 #define GEN_CRLOGIC(name, tcg_op, opc) \ 3578 static void glue(gen_, name)(DisasContext *ctx) \ 3579 { \ 3580 uint8_t bitmask; \ 3581 int sh; \ 3582 TCGv_i32 t0, t1; \ 3583 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3584 t0 = tcg_temp_new_i32(); \ 3585 if (sh > 0) \ 3586 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3587 else if (sh < 0) \ 3588 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3589 else \ 3590 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3591 t1 = tcg_temp_new_i32(); \ 3592 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3593 if (sh > 0) \ 3594 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3595 else if (sh < 0) \ 3596 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3597 else \ 3598 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3599 tcg_op(t0, t0, t1); \ 3600 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3601 tcg_gen_andi_i32(t0, t0, bitmask); \ 3602 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3603 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3604 tcg_temp_free_i32(t0); \ 3605 tcg_temp_free_i32(t1); \ 3606 } 3607 3608 /* crand */ 3609 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3610 /* crandc */ 3611 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3612 /* creqv */ 3613 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3614 /* crnand */ 3615 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3616 /* crnor */ 3617 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3618 /* cror */ 3619 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3620 /* crorc */ 3621 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3622 /* crxor */ 3623 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3624 3625 /* mcrf */ 3626 static void gen_mcrf(DisasContext *ctx) 3627 { 3628 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3629 } 3630 3631 /*** System linkage ***/ 3632 3633 /* rfi (supervisor only) */ 3634 static void gen_rfi(DisasContext *ctx) 3635 { 3636 #if defined(CONFIG_USER_ONLY) 3637 GEN_PRIV; 3638 #else 3639 /* This instruction doesn't exist anymore on 64-bit server 3640 * processors compliant with arch 2.x 3641 */ 3642 if (ctx->insns_flags & PPC_SEGMENT_64B) { 3643 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3644 return; 3645 } 3646 /* Restore CPU state */ 3647 CHK_SV; 3648 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3649 gen_helper_rfi(cpu_env); 3650 gen_sync_exception(ctx); 3651 #endif 3652 } 3653 3654 #if defined(TARGET_PPC64) 3655 static void gen_rfid(DisasContext *ctx) 3656 { 3657 #if defined(CONFIG_USER_ONLY) 3658 GEN_PRIV; 3659 #else 3660 /* Restore CPU state */ 3661 CHK_SV; 3662 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3663 gen_helper_rfid(cpu_env); 3664 gen_sync_exception(ctx); 3665 #endif 3666 } 3667 3668 static void gen_hrfid(DisasContext *ctx) 3669 { 3670 #if defined(CONFIG_USER_ONLY) 3671 GEN_PRIV; 3672 #else 3673 /* Restore CPU state */ 3674 CHK_HV; 3675 gen_helper_hrfid(cpu_env); 3676 gen_sync_exception(ctx); 3677 #endif 3678 } 3679 #endif 3680 3681 /* sc */ 3682 #if defined(CONFIG_USER_ONLY) 3683 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3684 #else 3685 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3686 #endif 3687 static void gen_sc(DisasContext *ctx) 3688 { 3689 uint32_t lev; 3690 3691 lev = (ctx->opcode >> 5) & 0x7F; 3692 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3693 } 3694 3695 /*** Trap ***/ 3696 3697 /* Check for unconditional traps (always or never) */ 3698 static bool check_unconditional_trap(DisasContext *ctx) 3699 { 3700 /* Trap never */ 3701 if (TO(ctx->opcode) == 0) { 3702 return true; 3703 } 3704 /* Trap always */ 3705 if (TO(ctx->opcode) == 31) { 3706 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3707 return true; 3708 } 3709 return false; 3710 } 3711 3712 /* tw */ 3713 static void gen_tw(DisasContext *ctx) 3714 { 3715 TCGv_i32 t0; 3716 3717 if (check_unconditional_trap(ctx)) { 3718 return; 3719 } 3720 t0 = tcg_const_i32(TO(ctx->opcode)); 3721 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3722 t0); 3723 tcg_temp_free_i32(t0); 3724 } 3725 3726 /* twi */ 3727 static void gen_twi(DisasContext *ctx) 3728 { 3729 TCGv t0; 3730 TCGv_i32 t1; 3731 3732 if (check_unconditional_trap(ctx)) { 3733 return; 3734 } 3735 t0 = tcg_const_tl(SIMM(ctx->opcode)); 3736 t1 = tcg_const_i32(TO(ctx->opcode)); 3737 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3738 tcg_temp_free(t0); 3739 tcg_temp_free_i32(t1); 3740 } 3741 3742 #if defined(TARGET_PPC64) 3743 /* td */ 3744 static void gen_td(DisasContext *ctx) 3745 { 3746 TCGv_i32 t0; 3747 3748 if (check_unconditional_trap(ctx)) { 3749 return; 3750 } 3751 t0 = tcg_const_i32(TO(ctx->opcode)); 3752 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3753 t0); 3754 tcg_temp_free_i32(t0); 3755 } 3756 3757 /* tdi */ 3758 static void gen_tdi(DisasContext *ctx) 3759 { 3760 TCGv t0; 3761 TCGv_i32 t1; 3762 3763 if (check_unconditional_trap(ctx)) { 3764 return; 3765 } 3766 t0 = tcg_const_tl(SIMM(ctx->opcode)); 3767 t1 = tcg_const_i32(TO(ctx->opcode)); 3768 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3769 tcg_temp_free(t0); 3770 tcg_temp_free_i32(t1); 3771 } 3772 #endif 3773 3774 /*** Processor control ***/ 3775 3776 static void gen_read_xer(DisasContext *ctx, TCGv dst) 3777 { 3778 TCGv t0 = tcg_temp_new(); 3779 TCGv t1 = tcg_temp_new(); 3780 TCGv t2 = tcg_temp_new(); 3781 tcg_gen_mov_tl(dst, cpu_xer); 3782 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 3783 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 3784 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 3785 tcg_gen_or_tl(t0, t0, t1); 3786 tcg_gen_or_tl(dst, dst, t2); 3787 tcg_gen_or_tl(dst, dst, t0); 3788 if (is_isa300(ctx)) { 3789 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 3790 tcg_gen_or_tl(dst, dst, t0); 3791 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 3792 tcg_gen_or_tl(dst, dst, t0); 3793 } 3794 tcg_temp_free(t0); 3795 tcg_temp_free(t1); 3796 tcg_temp_free(t2); 3797 } 3798 3799 static void gen_write_xer(TCGv src) 3800 { 3801 /* Write all flags, while reading back check for isa300 */ 3802 tcg_gen_andi_tl(cpu_xer, src, 3803 ~((1u << XER_SO) | 3804 (1u << XER_OV) | (1u << XER_OV32) | 3805 (1u << XER_CA) | (1u << XER_CA32))); 3806 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 3807 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 3808 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 3809 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 3810 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 3811 } 3812 3813 /* mcrxr */ 3814 static void gen_mcrxr(DisasContext *ctx) 3815 { 3816 TCGv_i32 t0 = tcg_temp_new_i32(); 3817 TCGv_i32 t1 = tcg_temp_new_i32(); 3818 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 3819 3820 tcg_gen_trunc_tl_i32(t0, cpu_so); 3821 tcg_gen_trunc_tl_i32(t1, cpu_ov); 3822 tcg_gen_trunc_tl_i32(dst, cpu_ca); 3823 tcg_gen_shli_i32(t0, t0, 3); 3824 tcg_gen_shli_i32(t1, t1, 2); 3825 tcg_gen_shli_i32(dst, dst, 1); 3826 tcg_gen_or_i32(dst, dst, t0); 3827 tcg_gen_or_i32(dst, dst, t1); 3828 tcg_temp_free_i32(t0); 3829 tcg_temp_free_i32(t1); 3830 3831 tcg_gen_movi_tl(cpu_so, 0); 3832 tcg_gen_movi_tl(cpu_ov, 0); 3833 tcg_gen_movi_tl(cpu_ca, 0); 3834 } 3835 3836 #ifdef TARGET_PPC64 3837 /* mcrxrx */ 3838 static void gen_mcrxrx(DisasContext *ctx) 3839 { 3840 TCGv t0 = tcg_temp_new(); 3841 TCGv t1 = tcg_temp_new(); 3842 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 3843 3844 /* copy OV and OV32 */ 3845 tcg_gen_shli_tl(t0, cpu_ov, 1); 3846 tcg_gen_or_tl(t0, t0, cpu_ov32); 3847 tcg_gen_shli_tl(t0, t0, 2); 3848 /* copy CA and CA32 */ 3849 tcg_gen_shli_tl(t1, cpu_ca, 1); 3850 tcg_gen_or_tl(t1, t1, cpu_ca32); 3851 tcg_gen_or_tl(t0, t0, t1); 3852 tcg_gen_trunc_tl_i32(dst, t0); 3853 tcg_temp_free(t0); 3854 tcg_temp_free(t1); 3855 } 3856 #endif 3857 3858 /* mfcr mfocrf */ 3859 static void gen_mfcr(DisasContext *ctx) 3860 { 3861 uint32_t crm, crn; 3862 3863 if (likely(ctx->opcode & 0x00100000)) { 3864 crm = CRM(ctx->opcode); 3865 if (likely(crm && ((crm & (crm - 1)) == 0))) { 3866 crn = ctz32 (crm); 3867 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 3868 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 3869 cpu_gpr[rD(ctx->opcode)], crn * 4); 3870 } 3871 } else { 3872 TCGv_i32 t0 = tcg_temp_new_i32(); 3873 tcg_gen_mov_i32(t0, cpu_crf[0]); 3874 tcg_gen_shli_i32(t0, t0, 4); 3875 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 3876 tcg_gen_shli_i32(t0, t0, 4); 3877 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 3878 tcg_gen_shli_i32(t0, t0, 4); 3879 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 3880 tcg_gen_shli_i32(t0, t0, 4); 3881 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 3882 tcg_gen_shli_i32(t0, t0, 4); 3883 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 3884 tcg_gen_shli_i32(t0, t0, 4); 3885 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 3886 tcg_gen_shli_i32(t0, t0, 4); 3887 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 3888 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 3889 tcg_temp_free_i32(t0); 3890 } 3891 } 3892 3893 /* mfmsr */ 3894 static void gen_mfmsr(DisasContext *ctx) 3895 { 3896 CHK_SV; 3897 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 3898 } 3899 3900 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 3901 { 3902 #if 0 3903 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 3904 printf("ERROR: try to access SPR %d !\n", sprn); 3905 #endif 3906 } 3907 #define SPR_NOACCESS (&spr_noaccess) 3908 3909 /* mfspr */ 3910 static inline void gen_op_mfspr(DisasContext *ctx) 3911 { 3912 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 3913 uint32_t sprn = SPR(ctx->opcode); 3914 3915 #if defined(CONFIG_USER_ONLY) 3916 read_cb = ctx->spr_cb[sprn].uea_read; 3917 #else 3918 if (ctx->pr) { 3919 read_cb = ctx->spr_cb[sprn].uea_read; 3920 } else if (ctx->hv) { 3921 read_cb = ctx->spr_cb[sprn].hea_read; 3922 } else { 3923 read_cb = ctx->spr_cb[sprn].oea_read; 3924 } 3925 #endif 3926 if (likely(read_cb != NULL)) { 3927 if (likely(read_cb != SPR_NOACCESS)) { 3928 (*read_cb)(ctx, rD(ctx->opcode), sprn); 3929 } else { 3930 /* Privilege exception */ 3931 /* This is a hack to avoid warnings when running Linux: 3932 * this OS breaks the PowerPC virtualisation model, 3933 * allowing userland application to read the PVR 3934 */ 3935 if (sprn != SPR_PVR) { 3936 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 3937 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 3938 ctx->base.pc_next - 4); 3939 } 3940 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 3941 } 3942 } else { 3943 /* ISA 2.07 defines these as no-ops */ 3944 if ((ctx->insns_flags2 & PPC2_ISA207S) && 3945 (sprn >= 808 && sprn <= 811)) { 3946 /* This is a nop */ 3947 return; 3948 } 3949 /* Not defined */ 3950 qemu_log_mask(LOG_GUEST_ERROR, 3951 "Trying to read invalid spr %d (0x%03x) at " 3952 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 3953 3954 /* The behaviour depends on MSR:PR and SPR# bit 0x10, 3955 * it can generate a priv, a hv emu or a no-op 3956 */ 3957 if (sprn & 0x10) { 3958 if (ctx->pr) { 3959 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3960 } 3961 } else { 3962 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 3963 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3964 } 3965 } 3966 } 3967 } 3968 3969 static void gen_mfspr(DisasContext *ctx) 3970 { 3971 gen_op_mfspr(ctx); 3972 } 3973 3974 /* mftb */ 3975 static void gen_mftb(DisasContext *ctx) 3976 { 3977 gen_op_mfspr(ctx); 3978 } 3979 3980 /* mtcrf mtocrf*/ 3981 static void gen_mtcrf(DisasContext *ctx) 3982 { 3983 uint32_t crm, crn; 3984 3985 crm = CRM(ctx->opcode); 3986 if (likely((ctx->opcode & 0x00100000))) { 3987 if (crm && ((crm & (crm - 1)) == 0)) { 3988 TCGv_i32 temp = tcg_temp_new_i32(); 3989 crn = ctz32 (crm); 3990 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 3991 tcg_gen_shri_i32(temp, temp, crn * 4); 3992 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 3993 tcg_temp_free_i32(temp); 3994 } 3995 } else { 3996 TCGv_i32 temp = tcg_temp_new_i32(); 3997 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 3998 for (crn = 0 ; crn < 8 ; crn++) { 3999 if (crm & (1 << crn)) { 4000 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4001 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4002 } 4003 } 4004 tcg_temp_free_i32(temp); 4005 } 4006 } 4007 4008 /* mtmsr */ 4009 #if defined(TARGET_PPC64) 4010 static void gen_mtmsrd(DisasContext *ctx) 4011 { 4012 CHK_SV; 4013 4014 #if !defined(CONFIG_USER_ONLY) 4015 if (ctx->opcode & 0x00010000) { 4016 /* Special form that does not need any synchronisation */ 4017 TCGv t0 = tcg_temp_new(); 4018 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4019 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4020 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4021 tcg_temp_free(t0); 4022 } else { 4023 /* XXX: we need to update nip before the store 4024 * if we enter power saving mode, we will exit the loop 4025 * directly from ppc_store_msr 4026 */ 4027 gen_update_nip(ctx, ctx->base.pc_next); 4028 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4029 /* Must stop the translation as machine state (may have) changed */ 4030 /* Note that mtmsr is not always defined as context-synchronizing */ 4031 gen_stop_exception(ctx); 4032 } 4033 #endif /* !defined(CONFIG_USER_ONLY) */ 4034 } 4035 #endif /* defined(TARGET_PPC64) */ 4036 4037 static void gen_mtmsr(DisasContext *ctx) 4038 { 4039 CHK_SV; 4040 4041 #if !defined(CONFIG_USER_ONLY) 4042 if (ctx->opcode & 0x00010000) { 4043 /* Special form that does not need any synchronisation */ 4044 TCGv t0 = tcg_temp_new(); 4045 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4046 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4047 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4048 tcg_temp_free(t0); 4049 } else { 4050 TCGv msr = tcg_temp_new(); 4051 4052 /* XXX: we need to update nip before the store 4053 * if we enter power saving mode, we will exit the loop 4054 * directly from ppc_store_msr 4055 */ 4056 gen_update_nip(ctx, ctx->base.pc_next); 4057 #if defined(TARGET_PPC64) 4058 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4059 #else 4060 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4061 #endif 4062 gen_helper_store_msr(cpu_env, msr); 4063 tcg_temp_free(msr); 4064 /* Must stop the translation as machine state (may have) changed */ 4065 /* Note that mtmsr is not always defined as context-synchronizing */ 4066 gen_stop_exception(ctx); 4067 } 4068 #endif 4069 } 4070 4071 /* mtspr */ 4072 static void gen_mtspr(DisasContext *ctx) 4073 { 4074 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4075 uint32_t sprn = SPR(ctx->opcode); 4076 4077 #if defined(CONFIG_USER_ONLY) 4078 write_cb = ctx->spr_cb[sprn].uea_write; 4079 #else 4080 if (ctx->pr) { 4081 write_cb = ctx->spr_cb[sprn].uea_write; 4082 } else if (ctx->hv) { 4083 write_cb = ctx->spr_cb[sprn].hea_write; 4084 } else { 4085 write_cb = ctx->spr_cb[sprn].oea_write; 4086 } 4087 #endif 4088 if (likely(write_cb != NULL)) { 4089 if (likely(write_cb != SPR_NOACCESS)) { 4090 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4091 } else { 4092 /* Privilege exception */ 4093 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4094 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4095 ctx->base.pc_next - 4); 4096 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4097 } 4098 } else { 4099 /* ISA 2.07 defines these as no-ops */ 4100 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4101 (sprn >= 808 && sprn <= 811)) { 4102 /* This is a nop */ 4103 return; 4104 } 4105 4106 /* Not defined */ 4107 qemu_log_mask(LOG_GUEST_ERROR, 4108 "Trying to write invalid spr %d (0x%03x) at " 4109 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4110 4111 4112 /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4113 * it can generate a priv, a hv emu or a no-op 4114 */ 4115 if (sprn & 0x10) { 4116 if (ctx->pr) { 4117 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4118 } 4119 } else { 4120 if (ctx->pr || sprn == 0) { 4121 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4122 } 4123 } 4124 } 4125 } 4126 4127 #if defined(TARGET_PPC64) 4128 /* setb */ 4129 static void gen_setb(DisasContext *ctx) 4130 { 4131 TCGv_i32 t0 = tcg_temp_new_i32(); 4132 TCGv_i32 t8 = tcg_temp_new_i32(); 4133 TCGv_i32 tm1 = tcg_temp_new_i32(); 4134 int crf = crfS(ctx->opcode); 4135 4136 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4137 tcg_gen_movi_i32(t8, 8); 4138 tcg_gen_movi_i32(tm1, -1); 4139 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4140 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4141 4142 tcg_temp_free_i32(t0); 4143 tcg_temp_free_i32(t8); 4144 tcg_temp_free_i32(tm1); 4145 } 4146 #endif 4147 4148 /*** Cache management ***/ 4149 4150 /* dcbf */ 4151 static void gen_dcbf(DisasContext *ctx) 4152 { 4153 /* XXX: specification says this is treated as a load by the MMU */ 4154 TCGv t0; 4155 gen_set_access_type(ctx, ACCESS_CACHE); 4156 t0 = tcg_temp_new(); 4157 gen_addr_reg_index(ctx, t0); 4158 gen_qemu_ld8u(ctx, t0, t0); 4159 tcg_temp_free(t0); 4160 } 4161 4162 /* dcbi (Supervisor only) */ 4163 static void gen_dcbi(DisasContext *ctx) 4164 { 4165 #if defined(CONFIG_USER_ONLY) 4166 GEN_PRIV; 4167 #else 4168 TCGv EA, val; 4169 4170 CHK_SV; 4171 EA = tcg_temp_new(); 4172 gen_set_access_type(ctx, ACCESS_CACHE); 4173 gen_addr_reg_index(ctx, EA); 4174 val = tcg_temp_new(); 4175 /* XXX: specification says this should be treated as a store by the MMU */ 4176 gen_qemu_ld8u(ctx, val, EA); 4177 gen_qemu_st8(ctx, val, EA); 4178 tcg_temp_free(val); 4179 tcg_temp_free(EA); 4180 #endif /* defined(CONFIG_USER_ONLY) */ 4181 } 4182 4183 /* dcdst */ 4184 static void gen_dcbst(DisasContext *ctx) 4185 { 4186 /* XXX: specification say this is treated as a load by the MMU */ 4187 TCGv t0; 4188 gen_set_access_type(ctx, ACCESS_CACHE); 4189 t0 = tcg_temp_new(); 4190 gen_addr_reg_index(ctx, t0); 4191 gen_qemu_ld8u(ctx, t0, t0); 4192 tcg_temp_free(t0); 4193 } 4194 4195 /* dcbt */ 4196 static void gen_dcbt(DisasContext *ctx) 4197 { 4198 /* interpreted as no-op */ 4199 /* XXX: specification say this is treated as a load by the MMU 4200 * but does not generate any exception 4201 */ 4202 } 4203 4204 /* dcbtst */ 4205 static void gen_dcbtst(DisasContext *ctx) 4206 { 4207 /* interpreted as no-op */ 4208 /* XXX: specification say this is treated as a load by the MMU 4209 * but does not generate any exception 4210 */ 4211 } 4212 4213 /* dcbtls */ 4214 static void gen_dcbtls(DisasContext *ctx) 4215 { 4216 /* Always fails locking the cache */ 4217 TCGv t0 = tcg_temp_new(); 4218 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4219 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4220 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4221 tcg_temp_free(t0); 4222 } 4223 4224 /* dcbz */ 4225 static void gen_dcbz(DisasContext *ctx) 4226 { 4227 TCGv tcgv_addr; 4228 TCGv_i32 tcgv_op; 4229 4230 gen_set_access_type(ctx, ACCESS_CACHE); 4231 tcgv_addr = tcg_temp_new(); 4232 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4233 gen_addr_reg_index(ctx, tcgv_addr); 4234 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4235 tcg_temp_free(tcgv_addr); 4236 tcg_temp_free_i32(tcgv_op); 4237 } 4238 4239 /* dst / dstt */ 4240 static void gen_dst(DisasContext *ctx) 4241 { 4242 if (rA(ctx->opcode) == 0) { 4243 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4244 } else { 4245 /* interpreted as no-op */ 4246 } 4247 } 4248 4249 /* dstst /dststt */ 4250 static void gen_dstst(DisasContext *ctx) 4251 { 4252 if (rA(ctx->opcode) == 0) { 4253 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4254 } else { 4255 /* interpreted as no-op */ 4256 } 4257 4258 } 4259 4260 /* dss / dssall */ 4261 static void gen_dss(DisasContext *ctx) 4262 { 4263 /* interpreted as no-op */ 4264 } 4265 4266 /* icbi */ 4267 static void gen_icbi(DisasContext *ctx) 4268 { 4269 TCGv t0; 4270 gen_set_access_type(ctx, ACCESS_CACHE); 4271 t0 = tcg_temp_new(); 4272 gen_addr_reg_index(ctx, t0); 4273 gen_helper_icbi(cpu_env, t0); 4274 tcg_temp_free(t0); 4275 } 4276 4277 /* Optional: */ 4278 /* dcba */ 4279 static void gen_dcba(DisasContext *ctx) 4280 { 4281 /* interpreted as no-op */ 4282 /* XXX: specification say this is treated as a store by the MMU 4283 * but does not generate any exception 4284 */ 4285 } 4286 4287 /*** Segment register manipulation ***/ 4288 /* Supervisor only: */ 4289 4290 /* mfsr */ 4291 static void gen_mfsr(DisasContext *ctx) 4292 { 4293 #if defined(CONFIG_USER_ONLY) 4294 GEN_PRIV; 4295 #else 4296 TCGv t0; 4297 4298 CHK_SV; 4299 t0 = tcg_const_tl(SR(ctx->opcode)); 4300 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4301 tcg_temp_free(t0); 4302 #endif /* defined(CONFIG_USER_ONLY) */ 4303 } 4304 4305 /* mfsrin */ 4306 static void gen_mfsrin(DisasContext *ctx) 4307 { 4308 #if defined(CONFIG_USER_ONLY) 4309 GEN_PRIV; 4310 #else 4311 TCGv t0; 4312 4313 CHK_SV; 4314 t0 = tcg_temp_new(); 4315 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4316 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4317 tcg_temp_free(t0); 4318 #endif /* defined(CONFIG_USER_ONLY) */ 4319 } 4320 4321 /* mtsr */ 4322 static void gen_mtsr(DisasContext *ctx) 4323 { 4324 #if defined(CONFIG_USER_ONLY) 4325 GEN_PRIV; 4326 #else 4327 TCGv t0; 4328 4329 CHK_SV; 4330 t0 = tcg_const_tl(SR(ctx->opcode)); 4331 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4332 tcg_temp_free(t0); 4333 #endif /* defined(CONFIG_USER_ONLY) */ 4334 } 4335 4336 /* mtsrin */ 4337 static void gen_mtsrin(DisasContext *ctx) 4338 { 4339 #if defined(CONFIG_USER_ONLY) 4340 GEN_PRIV; 4341 #else 4342 TCGv t0; 4343 CHK_SV; 4344 4345 t0 = tcg_temp_new(); 4346 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4347 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4348 tcg_temp_free(t0); 4349 #endif /* defined(CONFIG_USER_ONLY) */ 4350 } 4351 4352 #if defined(TARGET_PPC64) 4353 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4354 4355 /* mfsr */ 4356 static void gen_mfsr_64b(DisasContext *ctx) 4357 { 4358 #if defined(CONFIG_USER_ONLY) 4359 GEN_PRIV; 4360 #else 4361 TCGv t0; 4362 4363 CHK_SV; 4364 t0 = tcg_const_tl(SR(ctx->opcode)); 4365 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4366 tcg_temp_free(t0); 4367 #endif /* defined(CONFIG_USER_ONLY) */ 4368 } 4369 4370 /* mfsrin */ 4371 static void gen_mfsrin_64b(DisasContext *ctx) 4372 { 4373 #if defined(CONFIG_USER_ONLY) 4374 GEN_PRIV; 4375 #else 4376 TCGv t0; 4377 4378 CHK_SV; 4379 t0 = tcg_temp_new(); 4380 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4381 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4382 tcg_temp_free(t0); 4383 #endif /* defined(CONFIG_USER_ONLY) */ 4384 } 4385 4386 /* mtsr */ 4387 static void gen_mtsr_64b(DisasContext *ctx) 4388 { 4389 #if defined(CONFIG_USER_ONLY) 4390 GEN_PRIV; 4391 #else 4392 TCGv t0; 4393 4394 CHK_SV; 4395 t0 = tcg_const_tl(SR(ctx->opcode)); 4396 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4397 tcg_temp_free(t0); 4398 #endif /* defined(CONFIG_USER_ONLY) */ 4399 } 4400 4401 /* mtsrin */ 4402 static void gen_mtsrin_64b(DisasContext *ctx) 4403 { 4404 #if defined(CONFIG_USER_ONLY) 4405 GEN_PRIV; 4406 #else 4407 TCGv t0; 4408 4409 CHK_SV; 4410 t0 = tcg_temp_new(); 4411 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4412 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4413 tcg_temp_free(t0); 4414 #endif /* defined(CONFIG_USER_ONLY) */ 4415 } 4416 4417 /* slbmte */ 4418 static void gen_slbmte(DisasContext *ctx) 4419 { 4420 #if defined(CONFIG_USER_ONLY) 4421 GEN_PRIV; 4422 #else 4423 CHK_SV; 4424 4425 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4426 cpu_gpr[rS(ctx->opcode)]); 4427 #endif /* defined(CONFIG_USER_ONLY) */ 4428 } 4429 4430 static void gen_slbmfee(DisasContext *ctx) 4431 { 4432 #if defined(CONFIG_USER_ONLY) 4433 GEN_PRIV; 4434 #else 4435 CHK_SV; 4436 4437 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4438 cpu_gpr[rB(ctx->opcode)]); 4439 #endif /* defined(CONFIG_USER_ONLY) */ 4440 } 4441 4442 static void gen_slbmfev(DisasContext *ctx) 4443 { 4444 #if defined(CONFIG_USER_ONLY) 4445 GEN_PRIV; 4446 #else 4447 CHK_SV; 4448 4449 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4450 cpu_gpr[rB(ctx->opcode)]); 4451 #endif /* defined(CONFIG_USER_ONLY) */ 4452 } 4453 4454 static void gen_slbfee_(DisasContext *ctx) 4455 { 4456 #if defined(CONFIG_USER_ONLY) 4457 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4458 #else 4459 TCGLabel *l1, *l2; 4460 4461 if (unlikely(ctx->pr)) { 4462 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4463 return; 4464 } 4465 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4466 cpu_gpr[rB(ctx->opcode)]); 4467 l1 = gen_new_label(); 4468 l2 = gen_new_label(); 4469 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4470 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4471 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4472 tcg_gen_br(l2); 4473 gen_set_label(l1); 4474 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4475 gen_set_label(l2); 4476 #endif 4477 } 4478 #endif /* defined(TARGET_PPC64) */ 4479 4480 /*** Lookaside buffer management ***/ 4481 /* Optional & supervisor only: */ 4482 4483 /* tlbia */ 4484 static void gen_tlbia(DisasContext *ctx) 4485 { 4486 #if defined(CONFIG_USER_ONLY) 4487 GEN_PRIV; 4488 #else 4489 CHK_HV; 4490 4491 gen_helper_tlbia(cpu_env); 4492 #endif /* defined(CONFIG_USER_ONLY) */ 4493 } 4494 4495 /* tlbiel */ 4496 static void gen_tlbiel(DisasContext *ctx) 4497 { 4498 #if defined(CONFIG_USER_ONLY) 4499 GEN_PRIV; 4500 #else 4501 CHK_SV; 4502 4503 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4504 #endif /* defined(CONFIG_USER_ONLY) */ 4505 } 4506 4507 /* tlbie */ 4508 static void gen_tlbie(DisasContext *ctx) 4509 { 4510 #if defined(CONFIG_USER_ONLY) 4511 GEN_PRIV; 4512 #else 4513 TCGv_i32 t1; 4514 4515 if (ctx->gtse) { 4516 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 4517 } else { 4518 CHK_HV; /* Else hypervisor privileged */ 4519 } 4520 4521 if (NARROW_MODE(ctx)) { 4522 TCGv t0 = tcg_temp_new(); 4523 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4524 gen_helper_tlbie(cpu_env, t0); 4525 tcg_temp_free(t0); 4526 } else { 4527 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4528 } 4529 t1 = tcg_temp_new_i32(); 4530 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4531 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4532 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4533 tcg_temp_free_i32(t1); 4534 #endif /* defined(CONFIG_USER_ONLY) */ 4535 } 4536 4537 /* tlbsync */ 4538 static void gen_tlbsync(DisasContext *ctx) 4539 { 4540 #if defined(CONFIG_USER_ONLY) 4541 GEN_PRIV; 4542 #else 4543 4544 if (ctx->gtse) { 4545 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 4546 } else { 4547 CHK_HV; /* Else hypervisor privileged */ 4548 } 4549 4550 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4551 if (ctx->insns_flags & PPC_BOOKE) { 4552 gen_check_tlb_flush(ctx, true); 4553 } 4554 #endif /* defined(CONFIG_USER_ONLY) */ 4555 } 4556 4557 #if defined(TARGET_PPC64) 4558 /* slbia */ 4559 static void gen_slbia(DisasContext *ctx) 4560 { 4561 #if defined(CONFIG_USER_ONLY) 4562 GEN_PRIV; 4563 #else 4564 CHK_SV; 4565 4566 gen_helper_slbia(cpu_env); 4567 #endif /* defined(CONFIG_USER_ONLY) */ 4568 } 4569 4570 /* slbie */ 4571 static void gen_slbie(DisasContext *ctx) 4572 { 4573 #if defined(CONFIG_USER_ONLY) 4574 GEN_PRIV; 4575 #else 4576 CHK_SV; 4577 4578 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4579 #endif /* defined(CONFIG_USER_ONLY) */ 4580 } 4581 4582 /* slbieg */ 4583 static void gen_slbieg(DisasContext *ctx) 4584 { 4585 #if defined(CONFIG_USER_ONLY) 4586 GEN_PRIV; 4587 #else 4588 CHK_SV; 4589 4590 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4591 #endif /* defined(CONFIG_USER_ONLY) */ 4592 } 4593 4594 /* slbsync */ 4595 static void gen_slbsync(DisasContext *ctx) 4596 { 4597 #if defined(CONFIG_USER_ONLY) 4598 GEN_PRIV; 4599 #else 4600 CHK_SV; 4601 gen_check_tlb_flush(ctx, true); 4602 #endif /* defined(CONFIG_USER_ONLY) */ 4603 } 4604 4605 #endif /* defined(TARGET_PPC64) */ 4606 4607 /*** External control ***/ 4608 /* Optional: */ 4609 4610 /* eciwx */ 4611 static void gen_eciwx(DisasContext *ctx) 4612 { 4613 TCGv t0; 4614 /* Should check EAR[E] ! */ 4615 gen_set_access_type(ctx, ACCESS_EXT); 4616 t0 = tcg_temp_new(); 4617 gen_addr_reg_index(ctx, t0); 4618 gen_check_align(ctx, t0, 0x03); 4619 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4620 tcg_temp_free(t0); 4621 } 4622 4623 /* ecowx */ 4624 static void gen_ecowx(DisasContext *ctx) 4625 { 4626 TCGv t0; 4627 /* Should check EAR[E] ! */ 4628 gen_set_access_type(ctx, ACCESS_EXT); 4629 t0 = tcg_temp_new(); 4630 gen_addr_reg_index(ctx, t0); 4631 gen_check_align(ctx, t0, 0x03); 4632 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4633 tcg_temp_free(t0); 4634 } 4635 4636 /* PowerPC 601 specific instructions */ 4637 4638 /* abs - abs. */ 4639 static void gen_abs(DisasContext *ctx) 4640 { 4641 TCGLabel *l1 = gen_new_label(); 4642 TCGLabel *l2 = gen_new_label(); 4643 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); 4644 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4645 tcg_gen_br(l2); 4646 gen_set_label(l1); 4647 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4648 gen_set_label(l2); 4649 if (unlikely(Rc(ctx->opcode) != 0)) 4650 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4651 } 4652 4653 /* abso - abso. */ 4654 static void gen_abso(DisasContext *ctx) 4655 { 4656 TCGLabel *l1 = gen_new_label(); 4657 TCGLabel *l2 = gen_new_label(); 4658 TCGLabel *l3 = gen_new_label(); 4659 /* Start with XER OV disabled, the most likely case */ 4660 tcg_gen_movi_tl(cpu_ov, 0); 4661 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); 4662 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); 4663 tcg_gen_movi_tl(cpu_ov, 1); 4664 tcg_gen_movi_tl(cpu_so, 1); 4665 tcg_gen_br(l2); 4666 gen_set_label(l1); 4667 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4668 tcg_gen_br(l3); 4669 gen_set_label(l2); 4670 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4671 gen_set_label(l3); 4672 if (unlikely(Rc(ctx->opcode) != 0)) 4673 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4674 } 4675 4676 /* clcs */ 4677 static void gen_clcs(DisasContext *ctx) 4678 { 4679 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 4680 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4681 tcg_temp_free_i32(t0); 4682 /* Rc=1 sets CR0 to an undefined state */ 4683 } 4684 4685 /* div - div. */ 4686 static void gen_div(DisasContext *ctx) 4687 { 4688 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4689 cpu_gpr[rB(ctx->opcode)]); 4690 if (unlikely(Rc(ctx->opcode) != 0)) 4691 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4692 } 4693 4694 /* divo - divo. */ 4695 static void gen_divo(DisasContext *ctx) 4696 { 4697 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4698 cpu_gpr[rB(ctx->opcode)]); 4699 if (unlikely(Rc(ctx->opcode) != 0)) 4700 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4701 } 4702 4703 /* divs - divs. */ 4704 static void gen_divs(DisasContext *ctx) 4705 { 4706 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4707 cpu_gpr[rB(ctx->opcode)]); 4708 if (unlikely(Rc(ctx->opcode) != 0)) 4709 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4710 } 4711 4712 /* divso - divso. */ 4713 static void gen_divso(DisasContext *ctx) 4714 { 4715 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 4716 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4717 if (unlikely(Rc(ctx->opcode) != 0)) 4718 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4719 } 4720 4721 /* doz - doz. */ 4722 static void gen_doz(DisasContext *ctx) 4723 { 4724 TCGLabel *l1 = gen_new_label(); 4725 TCGLabel *l2 = gen_new_label(); 4726 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4727 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4728 tcg_gen_br(l2); 4729 gen_set_label(l1); 4730 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4731 gen_set_label(l2); 4732 if (unlikely(Rc(ctx->opcode) != 0)) 4733 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4734 } 4735 4736 /* dozo - dozo. */ 4737 static void gen_dozo(DisasContext *ctx) 4738 { 4739 TCGLabel *l1 = gen_new_label(); 4740 TCGLabel *l2 = gen_new_label(); 4741 TCGv t0 = tcg_temp_new(); 4742 TCGv t1 = tcg_temp_new(); 4743 TCGv t2 = tcg_temp_new(); 4744 /* Start with XER OV disabled, the most likely case */ 4745 tcg_gen_movi_tl(cpu_ov, 0); 4746 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4747 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4748 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4749 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 4750 tcg_gen_andc_tl(t1, t1, t2); 4751 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 4752 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 4753 tcg_gen_movi_tl(cpu_ov, 1); 4754 tcg_gen_movi_tl(cpu_so, 1); 4755 tcg_gen_br(l2); 4756 gen_set_label(l1); 4757 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4758 gen_set_label(l2); 4759 tcg_temp_free(t0); 4760 tcg_temp_free(t1); 4761 tcg_temp_free(t2); 4762 if (unlikely(Rc(ctx->opcode) != 0)) 4763 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4764 } 4765 4766 /* dozi */ 4767 static void gen_dozi(DisasContext *ctx) 4768 { 4769 target_long simm = SIMM(ctx->opcode); 4770 TCGLabel *l1 = gen_new_label(); 4771 TCGLabel *l2 = gen_new_label(); 4772 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 4773 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 4774 tcg_gen_br(l2); 4775 gen_set_label(l1); 4776 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4777 gen_set_label(l2); 4778 if (unlikely(Rc(ctx->opcode) != 0)) 4779 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4780 } 4781 4782 /* lscbx - lscbx. */ 4783 static void gen_lscbx(DisasContext *ctx) 4784 { 4785 TCGv t0 = tcg_temp_new(); 4786 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 4787 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 4788 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 4789 4790 gen_addr_reg_index(ctx, t0); 4791 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 4792 tcg_temp_free_i32(t1); 4793 tcg_temp_free_i32(t2); 4794 tcg_temp_free_i32(t3); 4795 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 4796 tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 4797 if (unlikely(Rc(ctx->opcode) != 0)) 4798 gen_set_Rc0(ctx, t0); 4799 tcg_temp_free(t0); 4800 } 4801 4802 /* maskg - maskg. */ 4803 static void gen_maskg(DisasContext *ctx) 4804 { 4805 TCGLabel *l1 = gen_new_label(); 4806 TCGv t0 = tcg_temp_new(); 4807 TCGv t1 = tcg_temp_new(); 4808 TCGv t2 = tcg_temp_new(); 4809 TCGv t3 = tcg_temp_new(); 4810 tcg_gen_movi_tl(t3, 0xFFFFFFFF); 4811 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4812 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 4813 tcg_gen_addi_tl(t2, t0, 1); 4814 tcg_gen_shr_tl(t2, t3, t2); 4815 tcg_gen_shr_tl(t3, t3, t1); 4816 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 4817 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 4818 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4819 gen_set_label(l1); 4820 tcg_temp_free(t0); 4821 tcg_temp_free(t1); 4822 tcg_temp_free(t2); 4823 tcg_temp_free(t3); 4824 if (unlikely(Rc(ctx->opcode) != 0)) 4825 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4826 } 4827 4828 /* maskir - maskir. */ 4829 static void gen_maskir(DisasContext *ctx) 4830 { 4831 TCGv t0 = tcg_temp_new(); 4832 TCGv t1 = tcg_temp_new(); 4833 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4834 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4835 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4836 tcg_temp_free(t0); 4837 tcg_temp_free(t1); 4838 if (unlikely(Rc(ctx->opcode) != 0)) 4839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4840 } 4841 4842 /* mul - mul. */ 4843 static void gen_mul(DisasContext *ctx) 4844 { 4845 TCGv_i64 t0 = tcg_temp_new_i64(); 4846 TCGv_i64 t1 = tcg_temp_new_i64(); 4847 TCGv t2 = tcg_temp_new(); 4848 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4849 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4850 tcg_gen_mul_i64(t0, t0, t1); 4851 tcg_gen_trunc_i64_tl(t2, t0); 4852 gen_store_spr(SPR_MQ, t2); 4853 tcg_gen_shri_i64(t1, t0, 32); 4854 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4855 tcg_temp_free_i64(t0); 4856 tcg_temp_free_i64(t1); 4857 tcg_temp_free(t2); 4858 if (unlikely(Rc(ctx->opcode) != 0)) 4859 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4860 } 4861 4862 /* mulo - mulo. */ 4863 static void gen_mulo(DisasContext *ctx) 4864 { 4865 TCGLabel *l1 = gen_new_label(); 4866 TCGv_i64 t0 = tcg_temp_new_i64(); 4867 TCGv_i64 t1 = tcg_temp_new_i64(); 4868 TCGv t2 = tcg_temp_new(); 4869 /* Start with XER OV disabled, the most likely case */ 4870 tcg_gen_movi_tl(cpu_ov, 0); 4871 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4872 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4873 tcg_gen_mul_i64(t0, t0, t1); 4874 tcg_gen_trunc_i64_tl(t2, t0); 4875 gen_store_spr(SPR_MQ, t2); 4876 tcg_gen_shri_i64(t1, t0, 32); 4877 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4878 tcg_gen_ext32s_i64(t1, t0); 4879 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 4880 tcg_gen_movi_tl(cpu_ov, 1); 4881 tcg_gen_movi_tl(cpu_so, 1); 4882 gen_set_label(l1); 4883 tcg_temp_free_i64(t0); 4884 tcg_temp_free_i64(t1); 4885 tcg_temp_free(t2); 4886 if (unlikely(Rc(ctx->opcode) != 0)) 4887 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4888 } 4889 4890 /* nabs - nabs. */ 4891 static void gen_nabs(DisasContext *ctx) 4892 { 4893 TCGLabel *l1 = gen_new_label(); 4894 TCGLabel *l2 = gen_new_label(); 4895 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4896 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4897 tcg_gen_br(l2); 4898 gen_set_label(l1); 4899 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4900 gen_set_label(l2); 4901 if (unlikely(Rc(ctx->opcode) != 0)) 4902 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4903 } 4904 4905 /* nabso - nabso. */ 4906 static void gen_nabso(DisasContext *ctx) 4907 { 4908 TCGLabel *l1 = gen_new_label(); 4909 TCGLabel *l2 = gen_new_label(); 4910 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4911 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4912 tcg_gen_br(l2); 4913 gen_set_label(l1); 4914 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4915 gen_set_label(l2); 4916 /* nabs never overflows */ 4917 tcg_gen_movi_tl(cpu_ov, 0); 4918 if (unlikely(Rc(ctx->opcode) != 0)) 4919 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4920 } 4921 4922 /* rlmi - rlmi. */ 4923 static void gen_rlmi(DisasContext *ctx) 4924 { 4925 uint32_t mb = MB(ctx->opcode); 4926 uint32_t me = ME(ctx->opcode); 4927 TCGv t0 = tcg_temp_new(); 4928 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4929 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4930 tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 4931 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); 4932 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 4933 tcg_temp_free(t0); 4934 if (unlikely(Rc(ctx->opcode) != 0)) 4935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4936 } 4937 4938 /* rrib - rrib. */ 4939 static void gen_rrib(DisasContext *ctx) 4940 { 4941 TCGv t0 = tcg_temp_new(); 4942 TCGv t1 = tcg_temp_new(); 4943 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4944 tcg_gen_movi_tl(t1, 0x80000000); 4945 tcg_gen_shr_tl(t1, t1, t0); 4946 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4947 tcg_gen_and_tl(t0, t0, t1); 4948 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 4949 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4950 tcg_temp_free(t0); 4951 tcg_temp_free(t1); 4952 if (unlikely(Rc(ctx->opcode) != 0)) 4953 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4954 } 4955 4956 /* sle - sle. */ 4957 static void gen_sle(DisasContext *ctx) 4958 { 4959 TCGv t0 = tcg_temp_new(); 4960 TCGv t1 = tcg_temp_new(); 4961 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 4962 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 4963 tcg_gen_subfi_tl(t1, 32, t1); 4964 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 4965 tcg_gen_or_tl(t1, t0, t1); 4966 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4967 gen_store_spr(SPR_MQ, t1); 4968 tcg_temp_free(t0); 4969 tcg_temp_free(t1); 4970 if (unlikely(Rc(ctx->opcode) != 0)) 4971 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4972 } 4973 4974 /* sleq - sleq. */ 4975 static void gen_sleq(DisasContext *ctx) 4976 { 4977 TCGv t0 = tcg_temp_new(); 4978 TCGv t1 = tcg_temp_new(); 4979 TCGv t2 = tcg_temp_new(); 4980 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4981 tcg_gen_movi_tl(t2, 0xFFFFFFFF); 4982 tcg_gen_shl_tl(t2, t2, t0); 4983 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4984 gen_load_spr(t1, SPR_MQ); 4985 gen_store_spr(SPR_MQ, t0); 4986 tcg_gen_and_tl(t0, t0, t2); 4987 tcg_gen_andc_tl(t1, t1, t2); 4988 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4989 tcg_temp_free(t0); 4990 tcg_temp_free(t1); 4991 tcg_temp_free(t2); 4992 if (unlikely(Rc(ctx->opcode) != 0)) 4993 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4994 } 4995 4996 /* sliq - sliq. */ 4997 static void gen_sliq(DisasContext *ctx) 4998 { 4999 int sh = SH(ctx->opcode); 5000 TCGv t0 = tcg_temp_new(); 5001 TCGv t1 = tcg_temp_new(); 5002 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5003 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5004 tcg_gen_or_tl(t1, t0, t1); 5005 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5006 gen_store_spr(SPR_MQ, t1); 5007 tcg_temp_free(t0); 5008 tcg_temp_free(t1); 5009 if (unlikely(Rc(ctx->opcode) != 0)) 5010 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5011 } 5012 5013 /* slliq - slliq. */ 5014 static void gen_slliq(DisasContext *ctx) 5015 { 5016 int sh = SH(ctx->opcode); 5017 TCGv t0 = tcg_temp_new(); 5018 TCGv t1 = tcg_temp_new(); 5019 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5020 gen_load_spr(t1, SPR_MQ); 5021 gen_store_spr(SPR_MQ, t0); 5022 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5023 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5024 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5025 tcg_temp_free(t0); 5026 tcg_temp_free(t1); 5027 if (unlikely(Rc(ctx->opcode) != 0)) 5028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5029 } 5030 5031 /* sllq - sllq. */ 5032 static void gen_sllq(DisasContext *ctx) 5033 { 5034 TCGLabel *l1 = gen_new_label(); 5035 TCGLabel *l2 = gen_new_label(); 5036 TCGv t0 = tcg_temp_local_new(); 5037 TCGv t1 = tcg_temp_local_new(); 5038 TCGv t2 = tcg_temp_local_new(); 5039 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5040 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5041 tcg_gen_shl_tl(t1, t1, t2); 5042 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5043 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5044 gen_load_spr(t0, SPR_MQ); 5045 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5046 tcg_gen_br(l2); 5047 gen_set_label(l1); 5048 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5049 gen_load_spr(t2, SPR_MQ); 5050 tcg_gen_andc_tl(t1, t2, t1); 5051 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5052 gen_set_label(l2); 5053 tcg_temp_free(t0); 5054 tcg_temp_free(t1); 5055 tcg_temp_free(t2); 5056 if (unlikely(Rc(ctx->opcode) != 0)) 5057 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5058 } 5059 5060 /* slq - slq. */ 5061 static void gen_slq(DisasContext *ctx) 5062 { 5063 TCGLabel *l1 = gen_new_label(); 5064 TCGv t0 = tcg_temp_new(); 5065 TCGv t1 = tcg_temp_new(); 5066 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5067 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5068 tcg_gen_subfi_tl(t1, 32, t1); 5069 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5070 tcg_gen_or_tl(t1, t0, t1); 5071 gen_store_spr(SPR_MQ, t1); 5072 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5073 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5074 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5075 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5076 gen_set_label(l1); 5077 tcg_temp_free(t0); 5078 tcg_temp_free(t1); 5079 if (unlikely(Rc(ctx->opcode) != 0)) 5080 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5081 } 5082 5083 /* sraiq - sraiq. */ 5084 static void gen_sraiq(DisasContext *ctx) 5085 { 5086 int sh = SH(ctx->opcode); 5087 TCGLabel *l1 = gen_new_label(); 5088 TCGv t0 = tcg_temp_new(); 5089 TCGv t1 = tcg_temp_new(); 5090 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5091 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5092 tcg_gen_or_tl(t0, t0, t1); 5093 gen_store_spr(SPR_MQ, t0); 5094 tcg_gen_movi_tl(cpu_ca, 0); 5095 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5096 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5097 tcg_gen_movi_tl(cpu_ca, 1); 5098 gen_set_label(l1); 5099 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5100 tcg_temp_free(t0); 5101 tcg_temp_free(t1); 5102 if (unlikely(Rc(ctx->opcode) != 0)) 5103 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5104 } 5105 5106 /* sraq - sraq. */ 5107 static void gen_sraq(DisasContext *ctx) 5108 { 5109 TCGLabel *l1 = gen_new_label(); 5110 TCGLabel *l2 = gen_new_label(); 5111 TCGv t0 = tcg_temp_new(); 5112 TCGv t1 = tcg_temp_local_new(); 5113 TCGv t2 = tcg_temp_local_new(); 5114 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5115 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5116 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5117 tcg_gen_subfi_tl(t2, 32, t2); 5118 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5119 tcg_gen_or_tl(t0, t0, t2); 5120 gen_store_spr(SPR_MQ, t0); 5121 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5122 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5123 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5124 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5125 gen_set_label(l1); 5126 tcg_temp_free(t0); 5127 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5128 tcg_gen_movi_tl(cpu_ca, 0); 5129 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5130 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5131 tcg_gen_movi_tl(cpu_ca, 1); 5132 gen_set_label(l2); 5133 tcg_temp_free(t1); 5134 tcg_temp_free(t2); 5135 if (unlikely(Rc(ctx->opcode) != 0)) 5136 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5137 } 5138 5139 /* sre - sre. */ 5140 static void gen_sre(DisasContext *ctx) 5141 { 5142 TCGv t0 = tcg_temp_new(); 5143 TCGv t1 = tcg_temp_new(); 5144 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5145 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5146 tcg_gen_subfi_tl(t1, 32, t1); 5147 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5148 tcg_gen_or_tl(t1, t0, t1); 5149 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5150 gen_store_spr(SPR_MQ, t1); 5151 tcg_temp_free(t0); 5152 tcg_temp_free(t1); 5153 if (unlikely(Rc(ctx->opcode) != 0)) 5154 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5155 } 5156 5157 /* srea - srea. */ 5158 static void gen_srea(DisasContext *ctx) 5159 { 5160 TCGv t0 = tcg_temp_new(); 5161 TCGv t1 = tcg_temp_new(); 5162 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5163 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5164 gen_store_spr(SPR_MQ, t0); 5165 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5166 tcg_temp_free(t0); 5167 tcg_temp_free(t1); 5168 if (unlikely(Rc(ctx->opcode) != 0)) 5169 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5170 } 5171 5172 /* sreq */ 5173 static void gen_sreq(DisasContext *ctx) 5174 { 5175 TCGv t0 = tcg_temp_new(); 5176 TCGv t1 = tcg_temp_new(); 5177 TCGv t2 = tcg_temp_new(); 5178 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5179 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5180 tcg_gen_shr_tl(t1, t1, t0); 5181 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5182 gen_load_spr(t2, SPR_MQ); 5183 gen_store_spr(SPR_MQ, t0); 5184 tcg_gen_and_tl(t0, t0, t1); 5185 tcg_gen_andc_tl(t2, t2, t1); 5186 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5187 tcg_temp_free(t0); 5188 tcg_temp_free(t1); 5189 tcg_temp_free(t2); 5190 if (unlikely(Rc(ctx->opcode) != 0)) 5191 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5192 } 5193 5194 /* sriq */ 5195 static void gen_sriq(DisasContext *ctx) 5196 { 5197 int sh = SH(ctx->opcode); 5198 TCGv t0 = tcg_temp_new(); 5199 TCGv t1 = tcg_temp_new(); 5200 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5201 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5202 tcg_gen_or_tl(t1, t0, t1); 5203 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5204 gen_store_spr(SPR_MQ, t1); 5205 tcg_temp_free(t0); 5206 tcg_temp_free(t1); 5207 if (unlikely(Rc(ctx->opcode) != 0)) 5208 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5209 } 5210 5211 /* srliq */ 5212 static void gen_srliq(DisasContext *ctx) 5213 { 5214 int sh = SH(ctx->opcode); 5215 TCGv t0 = tcg_temp_new(); 5216 TCGv t1 = tcg_temp_new(); 5217 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5218 gen_load_spr(t1, SPR_MQ); 5219 gen_store_spr(SPR_MQ, t0); 5220 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5221 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5222 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5223 tcg_temp_free(t0); 5224 tcg_temp_free(t1); 5225 if (unlikely(Rc(ctx->opcode) != 0)) 5226 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5227 } 5228 5229 /* srlq */ 5230 static void gen_srlq(DisasContext *ctx) 5231 { 5232 TCGLabel *l1 = gen_new_label(); 5233 TCGLabel *l2 = gen_new_label(); 5234 TCGv t0 = tcg_temp_local_new(); 5235 TCGv t1 = tcg_temp_local_new(); 5236 TCGv t2 = tcg_temp_local_new(); 5237 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5238 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5239 tcg_gen_shr_tl(t2, t1, t2); 5240 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5241 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5242 gen_load_spr(t0, SPR_MQ); 5243 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5244 tcg_gen_br(l2); 5245 gen_set_label(l1); 5246 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5247 tcg_gen_and_tl(t0, t0, t2); 5248 gen_load_spr(t1, SPR_MQ); 5249 tcg_gen_andc_tl(t1, t1, t2); 5250 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5251 gen_set_label(l2); 5252 tcg_temp_free(t0); 5253 tcg_temp_free(t1); 5254 tcg_temp_free(t2); 5255 if (unlikely(Rc(ctx->opcode) != 0)) 5256 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5257 } 5258 5259 /* srq */ 5260 static void gen_srq(DisasContext *ctx) 5261 { 5262 TCGLabel *l1 = gen_new_label(); 5263 TCGv t0 = tcg_temp_new(); 5264 TCGv t1 = tcg_temp_new(); 5265 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5266 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5267 tcg_gen_subfi_tl(t1, 32, t1); 5268 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5269 tcg_gen_or_tl(t1, t0, t1); 5270 gen_store_spr(SPR_MQ, t1); 5271 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5272 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5273 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5274 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5275 gen_set_label(l1); 5276 tcg_temp_free(t0); 5277 tcg_temp_free(t1); 5278 if (unlikely(Rc(ctx->opcode) != 0)) 5279 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5280 } 5281 5282 /* PowerPC 602 specific instructions */ 5283 5284 /* dsa */ 5285 static void gen_dsa(DisasContext *ctx) 5286 { 5287 /* XXX: TODO */ 5288 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5289 } 5290 5291 /* esa */ 5292 static void gen_esa(DisasContext *ctx) 5293 { 5294 /* XXX: TODO */ 5295 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5296 } 5297 5298 /* mfrom */ 5299 static void gen_mfrom(DisasContext *ctx) 5300 { 5301 #if defined(CONFIG_USER_ONLY) 5302 GEN_PRIV; 5303 #else 5304 CHK_SV; 5305 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5306 #endif /* defined(CONFIG_USER_ONLY) */ 5307 } 5308 5309 /* 602 - 603 - G2 TLB management */ 5310 5311 /* tlbld */ 5312 static void gen_tlbld_6xx(DisasContext *ctx) 5313 { 5314 #if defined(CONFIG_USER_ONLY) 5315 GEN_PRIV; 5316 #else 5317 CHK_SV; 5318 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5319 #endif /* defined(CONFIG_USER_ONLY) */ 5320 } 5321 5322 /* tlbli */ 5323 static void gen_tlbli_6xx(DisasContext *ctx) 5324 { 5325 #if defined(CONFIG_USER_ONLY) 5326 GEN_PRIV; 5327 #else 5328 CHK_SV; 5329 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5330 #endif /* defined(CONFIG_USER_ONLY) */ 5331 } 5332 5333 /* 74xx TLB management */ 5334 5335 /* tlbld */ 5336 static void gen_tlbld_74xx(DisasContext *ctx) 5337 { 5338 #if defined(CONFIG_USER_ONLY) 5339 GEN_PRIV; 5340 #else 5341 CHK_SV; 5342 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5343 #endif /* defined(CONFIG_USER_ONLY) */ 5344 } 5345 5346 /* tlbli */ 5347 static void gen_tlbli_74xx(DisasContext *ctx) 5348 { 5349 #if defined(CONFIG_USER_ONLY) 5350 GEN_PRIV; 5351 #else 5352 CHK_SV; 5353 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5354 #endif /* defined(CONFIG_USER_ONLY) */ 5355 } 5356 5357 /* POWER instructions not in PowerPC 601 */ 5358 5359 /* clf */ 5360 static void gen_clf(DisasContext *ctx) 5361 { 5362 /* Cache line flush: implemented as no-op */ 5363 } 5364 5365 /* cli */ 5366 static void gen_cli(DisasContext *ctx) 5367 { 5368 #if defined(CONFIG_USER_ONLY) 5369 GEN_PRIV; 5370 #else 5371 /* Cache line invalidate: privileged and treated as no-op */ 5372 CHK_SV; 5373 #endif /* defined(CONFIG_USER_ONLY) */ 5374 } 5375 5376 /* dclst */ 5377 static void gen_dclst(DisasContext *ctx) 5378 { 5379 /* Data cache line store: treated as no-op */ 5380 } 5381 5382 static void gen_mfsri(DisasContext *ctx) 5383 { 5384 #if defined(CONFIG_USER_ONLY) 5385 GEN_PRIV; 5386 #else 5387 int ra = rA(ctx->opcode); 5388 int rd = rD(ctx->opcode); 5389 TCGv t0; 5390 5391 CHK_SV; 5392 t0 = tcg_temp_new(); 5393 gen_addr_reg_index(ctx, t0); 5394 tcg_gen_extract_tl(t0, t0, 28, 4); 5395 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5396 tcg_temp_free(t0); 5397 if (ra != 0 && ra != rd) 5398 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5399 #endif /* defined(CONFIG_USER_ONLY) */ 5400 } 5401 5402 static void gen_rac(DisasContext *ctx) 5403 { 5404 #if defined(CONFIG_USER_ONLY) 5405 GEN_PRIV; 5406 #else 5407 TCGv t0; 5408 5409 CHK_SV; 5410 t0 = tcg_temp_new(); 5411 gen_addr_reg_index(ctx, t0); 5412 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5413 tcg_temp_free(t0); 5414 #endif /* defined(CONFIG_USER_ONLY) */ 5415 } 5416 5417 static void gen_rfsvc(DisasContext *ctx) 5418 { 5419 #if defined(CONFIG_USER_ONLY) 5420 GEN_PRIV; 5421 #else 5422 CHK_SV; 5423 5424 gen_helper_rfsvc(cpu_env); 5425 gen_sync_exception(ctx); 5426 #endif /* defined(CONFIG_USER_ONLY) */ 5427 } 5428 5429 /* svc is not implemented for now */ 5430 5431 /* BookE specific instructions */ 5432 5433 /* XXX: not implemented on 440 ? */ 5434 static void gen_mfapidi(DisasContext *ctx) 5435 { 5436 /* XXX: TODO */ 5437 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5438 } 5439 5440 /* XXX: not implemented on 440 ? */ 5441 static void gen_tlbiva(DisasContext *ctx) 5442 { 5443 #if defined(CONFIG_USER_ONLY) 5444 GEN_PRIV; 5445 #else 5446 TCGv t0; 5447 5448 CHK_SV; 5449 t0 = tcg_temp_new(); 5450 gen_addr_reg_index(ctx, t0); 5451 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5452 tcg_temp_free(t0); 5453 #endif /* defined(CONFIG_USER_ONLY) */ 5454 } 5455 5456 /* All 405 MAC instructions are translated here */ 5457 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5458 int ra, int rb, int rt, int Rc) 5459 { 5460 TCGv t0, t1; 5461 5462 t0 = tcg_temp_local_new(); 5463 t1 = tcg_temp_local_new(); 5464 5465 switch (opc3 & 0x0D) { 5466 case 0x05: 5467 /* macchw - macchw. - macchwo - macchwo. */ 5468 /* macchws - macchws. - macchwso - macchwso. */ 5469 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5470 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5471 /* mulchw - mulchw. */ 5472 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5473 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5474 tcg_gen_ext16s_tl(t1, t1); 5475 break; 5476 case 0x04: 5477 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5478 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5479 /* mulchwu - mulchwu. */ 5480 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5481 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5482 tcg_gen_ext16u_tl(t1, t1); 5483 break; 5484 case 0x01: 5485 /* machhw - machhw. - machhwo - machhwo. */ 5486 /* machhws - machhws. - machhwso - machhwso. */ 5487 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5488 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5489 /* mulhhw - mulhhw. */ 5490 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5491 tcg_gen_ext16s_tl(t0, t0); 5492 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5493 tcg_gen_ext16s_tl(t1, t1); 5494 break; 5495 case 0x00: 5496 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5497 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5498 /* mulhhwu - mulhhwu. */ 5499 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5500 tcg_gen_ext16u_tl(t0, t0); 5501 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5502 tcg_gen_ext16u_tl(t1, t1); 5503 break; 5504 case 0x0D: 5505 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5506 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5507 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5508 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5509 /* mullhw - mullhw. */ 5510 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5511 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5512 break; 5513 case 0x0C: 5514 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5515 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5516 /* mullhwu - mullhwu. */ 5517 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5518 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5519 break; 5520 } 5521 if (opc2 & 0x04) { 5522 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5523 tcg_gen_mul_tl(t1, t0, t1); 5524 if (opc2 & 0x02) { 5525 /* nmultiply-and-accumulate (0x0E) */ 5526 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5527 } else { 5528 /* multiply-and-accumulate (0x0C) */ 5529 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5530 } 5531 5532 if (opc3 & 0x12) { 5533 /* Check overflow and/or saturate */ 5534 TCGLabel *l1 = gen_new_label(); 5535 5536 if (opc3 & 0x10) { 5537 /* Start with XER OV disabled, the most likely case */ 5538 tcg_gen_movi_tl(cpu_ov, 0); 5539 } 5540 if (opc3 & 0x01) { 5541 /* Signed */ 5542 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5543 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5544 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5545 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5546 if (opc3 & 0x02) { 5547 /* Saturate */ 5548 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5549 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5550 } 5551 } else { 5552 /* Unsigned */ 5553 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5554 if (opc3 & 0x02) { 5555 /* Saturate */ 5556 tcg_gen_movi_tl(t0, UINT32_MAX); 5557 } 5558 } 5559 if (opc3 & 0x10) { 5560 /* Check overflow */ 5561 tcg_gen_movi_tl(cpu_ov, 1); 5562 tcg_gen_movi_tl(cpu_so, 1); 5563 } 5564 gen_set_label(l1); 5565 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5566 } 5567 } else { 5568 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5569 } 5570 tcg_temp_free(t0); 5571 tcg_temp_free(t1); 5572 if (unlikely(Rc) != 0) { 5573 /* Update Rc0 */ 5574 gen_set_Rc0(ctx, cpu_gpr[rt]); 5575 } 5576 } 5577 5578 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5579 static void glue(gen_, name)(DisasContext *ctx) \ 5580 { \ 5581 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5582 rD(ctx->opcode), Rc(ctx->opcode)); \ 5583 } 5584 5585 /* macchw - macchw. */ 5586 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5587 /* macchwo - macchwo. */ 5588 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5589 /* macchws - macchws. */ 5590 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5591 /* macchwso - macchwso. */ 5592 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5593 /* macchwsu - macchwsu. */ 5594 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5595 /* macchwsuo - macchwsuo. */ 5596 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5597 /* macchwu - macchwu. */ 5598 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5599 /* macchwuo - macchwuo. */ 5600 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5601 /* machhw - machhw. */ 5602 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5603 /* machhwo - machhwo. */ 5604 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5605 /* machhws - machhws. */ 5606 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5607 /* machhwso - machhwso. */ 5608 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5609 /* machhwsu - machhwsu. */ 5610 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5611 /* machhwsuo - machhwsuo. */ 5612 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5613 /* machhwu - machhwu. */ 5614 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5615 /* machhwuo - machhwuo. */ 5616 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5617 /* maclhw - maclhw. */ 5618 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5619 /* maclhwo - maclhwo. */ 5620 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5621 /* maclhws - maclhws. */ 5622 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5623 /* maclhwso - maclhwso. */ 5624 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5625 /* maclhwu - maclhwu. */ 5626 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5627 /* maclhwuo - maclhwuo. */ 5628 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5629 /* maclhwsu - maclhwsu. */ 5630 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5631 /* maclhwsuo - maclhwsuo. */ 5632 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5633 /* nmacchw - nmacchw. */ 5634 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5635 /* nmacchwo - nmacchwo. */ 5636 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5637 /* nmacchws - nmacchws. */ 5638 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5639 /* nmacchwso - nmacchwso. */ 5640 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5641 /* nmachhw - nmachhw. */ 5642 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5643 /* nmachhwo - nmachhwo. */ 5644 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5645 /* nmachhws - nmachhws. */ 5646 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5647 /* nmachhwso - nmachhwso. */ 5648 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5649 /* nmaclhw - nmaclhw. */ 5650 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5651 /* nmaclhwo - nmaclhwo. */ 5652 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5653 /* nmaclhws - nmaclhws. */ 5654 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5655 /* nmaclhwso - nmaclhwso. */ 5656 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5657 5658 /* mulchw - mulchw. */ 5659 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5660 /* mulchwu - mulchwu. */ 5661 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5662 /* mulhhw - mulhhw. */ 5663 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5664 /* mulhhwu - mulhhwu. */ 5665 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5666 /* mullhw - mullhw. */ 5667 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5668 /* mullhwu - mullhwu. */ 5669 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5670 5671 /* mfdcr */ 5672 static void gen_mfdcr(DisasContext *ctx) 5673 { 5674 #if defined(CONFIG_USER_ONLY) 5675 GEN_PRIV; 5676 #else 5677 TCGv dcrn; 5678 5679 CHK_SV; 5680 dcrn = tcg_const_tl(SPR(ctx->opcode)); 5681 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5682 tcg_temp_free(dcrn); 5683 #endif /* defined(CONFIG_USER_ONLY) */ 5684 } 5685 5686 /* mtdcr */ 5687 static void gen_mtdcr(DisasContext *ctx) 5688 { 5689 #if defined(CONFIG_USER_ONLY) 5690 GEN_PRIV; 5691 #else 5692 TCGv dcrn; 5693 5694 CHK_SV; 5695 dcrn = tcg_const_tl(SPR(ctx->opcode)); 5696 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5697 tcg_temp_free(dcrn); 5698 #endif /* defined(CONFIG_USER_ONLY) */ 5699 } 5700 5701 /* mfdcrx */ 5702 /* XXX: not implemented on 440 ? */ 5703 static void gen_mfdcrx(DisasContext *ctx) 5704 { 5705 #if defined(CONFIG_USER_ONLY) 5706 GEN_PRIV; 5707 #else 5708 CHK_SV; 5709 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5710 cpu_gpr[rA(ctx->opcode)]); 5711 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5712 #endif /* defined(CONFIG_USER_ONLY) */ 5713 } 5714 5715 /* mtdcrx */ 5716 /* XXX: not implemented on 440 ? */ 5717 static void gen_mtdcrx(DisasContext *ctx) 5718 { 5719 #if defined(CONFIG_USER_ONLY) 5720 GEN_PRIV; 5721 #else 5722 CHK_SV; 5723 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5724 cpu_gpr[rS(ctx->opcode)]); 5725 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5726 #endif /* defined(CONFIG_USER_ONLY) */ 5727 } 5728 5729 /* mfdcrux (PPC 460) : user-mode access to DCR */ 5730 static void gen_mfdcrux(DisasContext *ctx) 5731 { 5732 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5733 cpu_gpr[rA(ctx->opcode)]); 5734 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5735 } 5736 5737 /* mtdcrux (PPC 460) : user-mode access to DCR */ 5738 static void gen_mtdcrux(DisasContext *ctx) 5739 { 5740 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5741 cpu_gpr[rS(ctx->opcode)]); 5742 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5743 } 5744 5745 /* dccci */ 5746 static void gen_dccci(DisasContext *ctx) 5747 { 5748 CHK_SV; 5749 /* interpreted as no-op */ 5750 } 5751 5752 /* dcread */ 5753 static void gen_dcread(DisasContext *ctx) 5754 { 5755 #if defined(CONFIG_USER_ONLY) 5756 GEN_PRIV; 5757 #else 5758 TCGv EA, val; 5759 5760 CHK_SV; 5761 gen_set_access_type(ctx, ACCESS_CACHE); 5762 EA = tcg_temp_new(); 5763 gen_addr_reg_index(ctx, EA); 5764 val = tcg_temp_new(); 5765 gen_qemu_ld32u(ctx, val, EA); 5766 tcg_temp_free(val); 5767 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5768 tcg_temp_free(EA); 5769 #endif /* defined(CONFIG_USER_ONLY) */ 5770 } 5771 5772 /* icbt */ 5773 static void gen_icbt_40x(DisasContext *ctx) 5774 { 5775 /* interpreted as no-op */ 5776 /* XXX: specification say this is treated as a load by the MMU 5777 * but does not generate any exception 5778 */ 5779 } 5780 5781 /* iccci */ 5782 static void gen_iccci(DisasContext *ctx) 5783 { 5784 CHK_SV; 5785 /* interpreted as no-op */ 5786 } 5787 5788 /* icread */ 5789 static void gen_icread(DisasContext *ctx) 5790 { 5791 CHK_SV; 5792 /* interpreted as no-op */ 5793 } 5794 5795 /* rfci (supervisor only) */ 5796 static void gen_rfci_40x(DisasContext *ctx) 5797 { 5798 #if defined(CONFIG_USER_ONLY) 5799 GEN_PRIV; 5800 #else 5801 CHK_SV; 5802 /* Restore CPU state */ 5803 gen_helper_40x_rfci(cpu_env); 5804 gen_sync_exception(ctx); 5805 #endif /* defined(CONFIG_USER_ONLY) */ 5806 } 5807 5808 static void gen_rfci(DisasContext *ctx) 5809 { 5810 #if defined(CONFIG_USER_ONLY) 5811 GEN_PRIV; 5812 #else 5813 CHK_SV; 5814 /* Restore CPU state */ 5815 gen_helper_rfci(cpu_env); 5816 gen_sync_exception(ctx); 5817 #endif /* defined(CONFIG_USER_ONLY) */ 5818 } 5819 5820 /* BookE specific */ 5821 5822 /* XXX: not implemented on 440 ? */ 5823 static void gen_rfdi(DisasContext *ctx) 5824 { 5825 #if defined(CONFIG_USER_ONLY) 5826 GEN_PRIV; 5827 #else 5828 CHK_SV; 5829 /* Restore CPU state */ 5830 gen_helper_rfdi(cpu_env); 5831 gen_sync_exception(ctx); 5832 #endif /* defined(CONFIG_USER_ONLY) */ 5833 } 5834 5835 /* XXX: not implemented on 440 ? */ 5836 static void gen_rfmci(DisasContext *ctx) 5837 { 5838 #if defined(CONFIG_USER_ONLY) 5839 GEN_PRIV; 5840 #else 5841 CHK_SV; 5842 /* Restore CPU state */ 5843 gen_helper_rfmci(cpu_env); 5844 gen_sync_exception(ctx); 5845 #endif /* defined(CONFIG_USER_ONLY) */ 5846 } 5847 5848 /* TLB management - PowerPC 405 implementation */ 5849 5850 /* tlbre */ 5851 static void gen_tlbre_40x(DisasContext *ctx) 5852 { 5853 #if defined(CONFIG_USER_ONLY) 5854 GEN_PRIV; 5855 #else 5856 CHK_SV; 5857 switch (rB(ctx->opcode)) { 5858 case 0: 5859 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5860 cpu_gpr[rA(ctx->opcode)]); 5861 break; 5862 case 1: 5863 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5864 cpu_gpr[rA(ctx->opcode)]); 5865 break; 5866 default: 5867 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5868 break; 5869 } 5870 #endif /* defined(CONFIG_USER_ONLY) */ 5871 } 5872 5873 /* tlbsx - tlbsx. */ 5874 static void gen_tlbsx_40x(DisasContext *ctx) 5875 { 5876 #if defined(CONFIG_USER_ONLY) 5877 GEN_PRIV; 5878 #else 5879 TCGv t0; 5880 5881 CHK_SV; 5882 t0 = tcg_temp_new(); 5883 gen_addr_reg_index(ctx, t0); 5884 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5885 tcg_temp_free(t0); 5886 if (Rc(ctx->opcode)) { 5887 TCGLabel *l1 = gen_new_label(); 5888 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5889 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5890 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5891 gen_set_label(l1); 5892 } 5893 #endif /* defined(CONFIG_USER_ONLY) */ 5894 } 5895 5896 /* tlbwe */ 5897 static void gen_tlbwe_40x(DisasContext *ctx) 5898 { 5899 #if defined(CONFIG_USER_ONLY) 5900 GEN_PRIV; 5901 #else 5902 CHK_SV; 5903 5904 switch (rB(ctx->opcode)) { 5905 case 0: 5906 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5907 cpu_gpr[rS(ctx->opcode)]); 5908 break; 5909 case 1: 5910 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5911 cpu_gpr[rS(ctx->opcode)]); 5912 break; 5913 default: 5914 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5915 break; 5916 } 5917 #endif /* defined(CONFIG_USER_ONLY) */ 5918 } 5919 5920 /* TLB management - PowerPC 440 implementation */ 5921 5922 /* tlbre */ 5923 static void gen_tlbre_440(DisasContext *ctx) 5924 { 5925 #if defined(CONFIG_USER_ONLY) 5926 GEN_PRIV; 5927 #else 5928 CHK_SV; 5929 5930 switch (rB(ctx->opcode)) { 5931 case 0: 5932 case 1: 5933 case 2: 5934 { 5935 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 5936 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5937 t0, cpu_gpr[rA(ctx->opcode)]); 5938 tcg_temp_free_i32(t0); 5939 } 5940 break; 5941 default: 5942 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5943 break; 5944 } 5945 #endif /* defined(CONFIG_USER_ONLY) */ 5946 } 5947 5948 /* tlbsx - tlbsx. */ 5949 static void gen_tlbsx_440(DisasContext *ctx) 5950 { 5951 #if defined(CONFIG_USER_ONLY) 5952 GEN_PRIV; 5953 #else 5954 TCGv t0; 5955 5956 CHK_SV; 5957 t0 = tcg_temp_new(); 5958 gen_addr_reg_index(ctx, t0); 5959 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5960 tcg_temp_free(t0); 5961 if (Rc(ctx->opcode)) { 5962 TCGLabel *l1 = gen_new_label(); 5963 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5964 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5965 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5966 gen_set_label(l1); 5967 } 5968 #endif /* defined(CONFIG_USER_ONLY) */ 5969 } 5970 5971 /* tlbwe */ 5972 static void gen_tlbwe_440(DisasContext *ctx) 5973 { 5974 #if defined(CONFIG_USER_ONLY) 5975 GEN_PRIV; 5976 #else 5977 CHK_SV; 5978 switch (rB(ctx->opcode)) { 5979 case 0: 5980 case 1: 5981 case 2: 5982 { 5983 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 5984 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5985 cpu_gpr[rS(ctx->opcode)]); 5986 tcg_temp_free_i32(t0); 5987 } 5988 break; 5989 default: 5990 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5991 break; 5992 } 5993 #endif /* defined(CONFIG_USER_ONLY) */ 5994 } 5995 5996 /* TLB management - PowerPC BookE 2.06 implementation */ 5997 5998 /* tlbre */ 5999 static void gen_tlbre_booke206(DisasContext *ctx) 6000 { 6001 #if defined(CONFIG_USER_ONLY) 6002 GEN_PRIV; 6003 #else 6004 CHK_SV; 6005 gen_helper_booke206_tlbre(cpu_env); 6006 #endif /* defined(CONFIG_USER_ONLY) */ 6007 } 6008 6009 /* tlbsx - tlbsx. */ 6010 static void gen_tlbsx_booke206(DisasContext *ctx) 6011 { 6012 #if defined(CONFIG_USER_ONLY) 6013 GEN_PRIV; 6014 #else 6015 TCGv t0; 6016 6017 CHK_SV; 6018 if (rA(ctx->opcode)) { 6019 t0 = tcg_temp_new(); 6020 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6021 } else { 6022 t0 = tcg_const_tl(0); 6023 } 6024 6025 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6026 gen_helper_booke206_tlbsx(cpu_env, t0); 6027 tcg_temp_free(t0); 6028 #endif /* defined(CONFIG_USER_ONLY) */ 6029 } 6030 6031 /* tlbwe */ 6032 static void gen_tlbwe_booke206(DisasContext *ctx) 6033 { 6034 #if defined(CONFIG_USER_ONLY) 6035 GEN_PRIV; 6036 #else 6037 CHK_SV; 6038 gen_helper_booke206_tlbwe(cpu_env); 6039 #endif /* defined(CONFIG_USER_ONLY) */ 6040 } 6041 6042 static void gen_tlbivax_booke206(DisasContext *ctx) 6043 { 6044 #if defined(CONFIG_USER_ONLY) 6045 GEN_PRIV; 6046 #else 6047 TCGv t0; 6048 6049 CHK_SV; 6050 t0 = tcg_temp_new(); 6051 gen_addr_reg_index(ctx, t0); 6052 gen_helper_booke206_tlbivax(cpu_env, t0); 6053 tcg_temp_free(t0); 6054 #endif /* defined(CONFIG_USER_ONLY) */ 6055 } 6056 6057 static void gen_tlbilx_booke206(DisasContext *ctx) 6058 { 6059 #if defined(CONFIG_USER_ONLY) 6060 GEN_PRIV; 6061 #else 6062 TCGv t0; 6063 6064 CHK_SV; 6065 t0 = tcg_temp_new(); 6066 gen_addr_reg_index(ctx, t0); 6067 6068 switch((ctx->opcode >> 21) & 0x3) { 6069 case 0: 6070 gen_helper_booke206_tlbilx0(cpu_env, t0); 6071 break; 6072 case 1: 6073 gen_helper_booke206_tlbilx1(cpu_env, t0); 6074 break; 6075 case 3: 6076 gen_helper_booke206_tlbilx3(cpu_env, t0); 6077 break; 6078 default: 6079 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6080 break; 6081 } 6082 6083 tcg_temp_free(t0); 6084 #endif /* defined(CONFIG_USER_ONLY) */ 6085 } 6086 6087 6088 /* wrtee */ 6089 static void gen_wrtee(DisasContext *ctx) 6090 { 6091 #if defined(CONFIG_USER_ONLY) 6092 GEN_PRIV; 6093 #else 6094 TCGv t0; 6095 6096 CHK_SV; 6097 t0 = tcg_temp_new(); 6098 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6099 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6100 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6101 tcg_temp_free(t0); 6102 /* Stop translation to have a chance to raise an exception 6103 * if we just set msr_ee to 1 6104 */ 6105 gen_stop_exception(ctx); 6106 #endif /* defined(CONFIG_USER_ONLY) */ 6107 } 6108 6109 /* wrteei */ 6110 static void gen_wrteei(DisasContext *ctx) 6111 { 6112 #if defined(CONFIG_USER_ONLY) 6113 GEN_PRIV; 6114 #else 6115 CHK_SV; 6116 if (ctx->opcode & 0x00008000) { 6117 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6118 /* Stop translation to have a chance to raise an exception */ 6119 gen_stop_exception(ctx); 6120 } else { 6121 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6122 } 6123 #endif /* defined(CONFIG_USER_ONLY) */ 6124 } 6125 6126 /* PowerPC 440 specific instructions */ 6127 6128 /* dlmzb */ 6129 static void gen_dlmzb(DisasContext *ctx) 6130 { 6131 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6132 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6133 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6134 tcg_temp_free_i32(t0); 6135 } 6136 6137 /* mbar replaces eieio on 440 */ 6138 static void gen_mbar(DisasContext *ctx) 6139 { 6140 /* interpreted as no-op */ 6141 } 6142 6143 /* msync replaces sync on 440 */ 6144 static void gen_msync_4xx(DisasContext *ctx) 6145 { 6146 /* interpreted as no-op */ 6147 } 6148 6149 /* icbt */ 6150 static void gen_icbt_440(DisasContext *ctx) 6151 { 6152 /* interpreted as no-op */ 6153 /* XXX: specification say this is treated as a load by the MMU 6154 * but does not generate any exception 6155 */ 6156 } 6157 6158 /* Embedded.Processor Control */ 6159 6160 static void gen_msgclr(DisasContext *ctx) 6161 { 6162 #if defined(CONFIG_USER_ONLY) 6163 GEN_PRIV; 6164 #else 6165 CHK_HV; 6166 /* 64-bit server processors compliant with arch 2.x */ 6167 if (ctx->insns_flags & PPC_SEGMENT_64B) { 6168 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6169 } else { 6170 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6171 } 6172 #endif /* defined(CONFIG_USER_ONLY) */ 6173 } 6174 6175 static void gen_msgsnd(DisasContext *ctx) 6176 { 6177 #if defined(CONFIG_USER_ONLY) 6178 GEN_PRIV; 6179 #else 6180 CHK_HV; 6181 /* 64-bit server processors compliant with arch 2.x */ 6182 if (ctx->insns_flags & PPC_SEGMENT_64B) { 6183 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6184 } else { 6185 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6186 } 6187 #endif /* defined(CONFIG_USER_ONLY) */ 6188 } 6189 6190 static void gen_msgsync(DisasContext *ctx) 6191 { 6192 #if defined(CONFIG_USER_ONLY) 6193 GEN_PRIV; 6194 #else 6195 CHK_HV; 6196 #endif /* defined(CONFIG_USER_ONLY) */ 6197 /* interpreted as no-op */ 6198 } 6199 6200 #if defined(TARGET_PPC64) 6201 static void gen_maddld(DisasContext *ctx) 6202 { 6203 TCGv_i64 t1 = tcg_temp_new_i64(); 6204 6205 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6206 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6207 tcg_temp_free_i64(t1); 6208 } 6209 6210 /* maddhd maddhdu */ 6211 static void gen_maddhd_maddhdu(DisasContext *ctx) 6212 { 6213 TCGv_i64 lo = tcg_temp_new_i64(); 6214 TCGv_i64 hi = tcg_temp_new_i64(); 6215 TCGv_i64 t1 = tcg_temp_new_i64(); 6216 6217 if (Rc(ctx->opcode)) { 6218 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6219 cpu_gpr[rB(ctx->opcode)]); 6220 tcg_gen_movi_i64(t1, 0); 6221 } else { 6222 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6223 cpu_gpr[rB(ctx->opcode)]); 6224 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6225 } 6226 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6227 cpu_gpr[rC(ctx->opcode)], t1); 6228 tcg_temp_free_i64(lo); 6229 tcg_temp_free_i64(hi); 6230 tcg_temp_free_i64(t1); 6231 } 6232 #endif /* defined(TARGET_PPC64) */ 6233 6234 static void gen_tbegin(DisasContext *ctx) 6235 { 6236 if (unlikely(!ctx->tm_enabled)) { 6237 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6238 return; 6239 } 6240 gen_helper_tbegin(cpu_env); 6241 } 6242 6243 #define GEN_TM_NOOP(name) \ 6244 static inline void gen_##name(DisasContext *ctx) \ 6245 { \ 6246 if (unlikely(!ctx->tm_enabled)) { \ 6247 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6248 return; \ 6249 } \ 6250 /* Because tbegin always fails in QEMU, these user \ 6251 * space instructions all have a simple implementation: \ 6252 * \ 6253 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6254 * = 0b0 || 0b00 || 0b0 \ 6255 */ \ 6256 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6257 } 6258 6259 GEN_TM_NOOP(tend); 6260 GEN_TM_NOOP(tabort); 6261 GEN_TM_NOOP(tabortwc); 6262 GEN_TM_NOOP(tabortwci); 6263 GEN_TM_NOOP(tabortdc); 6264 GEN_TM_NOOP(tabortdci); 6265 GEN_TM_NOOP(tsr); 6266 static inline void gen_cp_abort(DisasContext *ctx) 6267 { 6268 // Do Nothing 6269 } 6270 6271 #define GEN_CP_PASTE_NOOP(name) \ 6272 static inline void gen_##name(DisasContext *ctx) \ 6273 { \ 6274 /* Generate invalid exception until \ 6275 * we have an implementation of the copy \ 6276 * paste facility \ 6277 */ \ 6278 gen_invalid(ctx); \ 6279 } 6280 6281 GEN_CP_PASTE_NOOP(copy) 6282 GEN_CP_PASTE_NOOP(paste) 6283 6284 static void gen_tcheck(DisasContext *ctx) 6285 { 6286 if (unlikely(!ctx->tm_enabled)) { 6287 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6288 return; 6289 } 6290 /* Because tbegin always fails, the tcheck implementation 6291 * is simple: 6292 * 6293 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6294 * = 0b1 || 0b00 || 0b0 6295 */ 6296 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6297 } 6298 6299 #if defined(CONFIG_USER_ONLY) 6300 #define GEN_TM_PRIV_NOOP(name) \ 6301 static inline void gen_##name(DisasContext *ctx) \ 6302 { \ 6303 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6304 } 6305 6306 #else 6307 6308 #define GEN_TM_PRIV_NOOP(name) \ 6309 static inline void gen_##name(DisasContext *ctx) \ 6310 { \ 6311 CHK_SV; \ 6312 if (unlikely(!ctx->tm_enabled)) { \ 6313 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6314 return; \ 6315 } \ 6316 /* Because tbegin always fails, the implementation is \ 6317 * simple: \ 6318 * \ 6319 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6320 * = 0b0 || 0b00 | 0b0 \ 6321 */ \ 6322 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6323 } 6324 6325 #endif 6326 6327 GEN_TM_PRIV_NOOP(treclaim); 6328 GEN_TM_PRIV_NOOP(trechkpt); 6329 6330 #include "translate/fp-impl.inc.c" 6331 6332 #include "translate/vmx-impl.inc.c" 6333 6334 #include "translate/vsx-impl.inc.c" 6335 6336 #include "translate/dfp-impl.inc.c" 6337 6338 #include "translate/spe-impl.inc.c" 6339 6340 /* Handles lfdp, lxsd, lxssp */ 6341 static void gen_dform39(DisasContext *ctx) 6342 { 6343 switch (ctx->opcode & 0x3) { 6344 case 0: /* lfdp */ 6345 if (ctx->insns_flags2 & PPC2_ISA205) { 6346 return gen_lfdp(ctx); 6347 } 6348 break; 6349 case 2: /* lxsd */ 6350 if (ctx->insns_flags2 & PPC2_ISA300) { 6351 return gen_lxsd(ctx); 6352 } 6353 break; 6354 case 3: /* lxssp */ 6355 if (ctx->insns_flags2 & PPC2_ISA300) { 6356 return gen_lxssp(ctx); 6357 } 6358 break; 6359 } 6360 return gen_invalid(ctx); 6361 } 6362 6363 /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6364 static void gen_dform3D(DisasContext *ctx) 6365 { 6366 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6367 switch (ctx->opcode & 0x7) { 6368 case 1: /* lxv */ 6369 if (ctx->insns_flags2 & PPC2_ISA300) { 6370 return gen_lxv(ctx); 6371 } 6372 break; 6373 case 5: /* stxv */ 6374 if (ctx->insns_flags2 & PPC2_ISA300) { 6375 return gen_stxv(ctx); 6376 } 6377 break; 6378 } 6379 } else { /* DS-FORM */ 6380 switch (ctx->opcode & 0x3) { 6381 case 0: /* stfdp */ 6382 if (ctx->insns_flags2 & PPC2_ISA205) { 6383 return gen_stfdp(ctx); 6384 } 6385 break; 6386 case 2: /* stxsd */ 6387 if (ctx->insns_flags2 & PPC2_ISA300) { 6388 return gen_stxsd(ctx); 6389 } 6390 break; 6391 case 3: /* stxssp */ 6392 if (ctx->insns_flags2 & PPC2_ISA300) { 6393 return gen_stxssp(ctx); 6394 } 6395 break; 6396 } 6397 } 6398 return gen_invalid(ctx); 6399 } 6400 6401 static opcode_t opcodes[] = { 6402 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6403 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6404 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6405 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6406 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6407 #if defined(TARGET_PPC64) 6408 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6409 #endif 6410 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6411 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6412 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6413 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6414 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6415 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6416 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6417 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6418 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6419 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6420 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6421 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6422 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6423 #if defined(TARGET_PPC64) 6424 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6425 #endif 6426 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6427 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6428 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6429 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6430 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6431 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6432 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6433 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6434 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6435 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6436 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6437 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6438 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6439 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6440 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6441 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6442 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6443 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6444 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6445 #if defined(TARGET_PPC64) 6446 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6447 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6448 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6449 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6450 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6451 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6452 #endif 6453 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6454 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6455 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6456 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6457 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6458 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6459 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6460 #if defined(TARGET_PPC64) 6461 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6462 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6463 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6464 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6465 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6466 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6467 PPC_NONE, PPC2_ISA300), 6468 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6469 PPC_NONE, PPC2_ISA300), 6470 #endif 6471 #if defined(TARGET_PPC64) 6472 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6473 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6474 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6475 #endif 6476 /* handles lfdp, lxsd, lxssp */ 6477 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6478 /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6479 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6480 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6481 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6482 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6483 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6484 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6485 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6486 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), 6487 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6488 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6489 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6490 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6491 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6492 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6493 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6494 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6495 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6496 #if defined(TARGET_PPC64) 6497 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6498 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6499 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6500 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6501 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6502 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6503 #endif 6504 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6505 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 6506 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 6507 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6508 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6509 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6510 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6511 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6512 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6513 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6514 #if defined(TARGET_PPC64) 6515 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6516 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6517 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6518 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6519 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6520 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6521 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6522 #endif 6523 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 6524 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6525 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6526 #if defined(TARGET_PPC64) 6527 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6528 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6529 #endif 6530 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6531 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6532 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6533 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6534 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6535 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6536 #if defined(TARGET_PPC64) 6537 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6538 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6539 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6540 #endif 6541 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6542 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6543 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6544 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6545 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6546 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6547 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6548 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6549 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6550 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6551 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6552 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6553 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6554 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6555 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6556 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6557 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6558 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6559 #if defined(TARGET_PPC64) 6560 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6561 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6562 PPC_SEGMENT_64B), 6563 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6564 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6565 PPC_SEGMENT_64B), 6566 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 6567 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 6568 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 6569 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 6570 #endif 6571 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6572 /* XXX Those instructions will need to be handled differently for 6573 * different ISA versions */ 6574 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 6575 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 6576 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 6577 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 6578 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6579 #if defined(TARGET_PPC64) 6580 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 6581 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 6582 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 6583 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6584 #endif 6585 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6586 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6587 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 6588 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 6589 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 6590 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 6591 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 6592 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 6593 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 6594 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 6595 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 6596 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6597 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 6598 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 6599 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 6600 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 6601 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 6602 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 6603 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 6604 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6605 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 6606 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 6607 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 6608 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 6609 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 6610 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 6611 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 6612 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 6613 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 6614 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 6615 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 6616 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 6617 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 6618 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 6619 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 6620 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 6621 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 6622 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 6623 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 6624 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6625 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6626 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 6627 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 6628 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 6629 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 6630 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 6631 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 6632 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 6633 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 6634 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6635 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6636 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 6637 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 6638 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6639 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6640 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 6641 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 6642 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6643 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6644 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6645 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6646 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6647 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6648 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 6649 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 6650 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6651 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6652 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6653 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6654 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6655 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6656 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6657 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6658 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6659 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6660 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6661 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6662 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6663 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6664 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6665 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6666 PPC_NONE, PPC2_BOOKE206), 6667 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6668 PPC_NONE, PPC2_BOOKE206), 6669 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6670 PPC_NONE, PPC2_BOOKE206), 6671 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6672 PPC_NONE, PPC2_BOOKE206), 6673 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6674 PPC_NONE, PPC2_BOOKE206), 6675 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 6676 PPC_NONE, PPC2_PRCNTL), 6677 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 6678 PPC_NONE, PPC2_PRCNTL), 6679 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 6680 PPC_NONE, PPC2_PRCNTL), 6681 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6682 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6683 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6684 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6685 PPC_BOOKE, PPC2_BOOKE206), 6686 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), 6687 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6688 PPC_BOOKE, PPC2_BOOKE206), 6689 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6690 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6691 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6692 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6693 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 6694 #if defined(TARGET_PPC64) 6695 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6696 PPC2_ISA300), 6697 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6698 #endif 6699 6700 #undef GEN_INT_ARITH_ADD 6701 #undef GEN_INT_ARITH_ADD_CONST 6702 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6703 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6704 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6705 add_ca, compute_ca, compute_ov) \ 6706 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6707 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6708 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6709 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6710 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6711 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6712 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6713 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6714 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6715 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6716 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6717 6718 #undef GEN_INT_ARITH_DIVW 6719 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6720 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6721 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6722 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6723 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6724 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6725 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6726 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6727 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6728 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6729 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6730 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6731 6732 #if defined(TARGET_PPC64) 6733 #undef GEN_INT_ARITH_DIVD 6734 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6735 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6736 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6737 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6738 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6739 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6740 6741 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6742 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6743 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6744 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6745 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6746 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6747 6748 #undef GEN_INT_ARITH_MUL_HELPER 6749 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6750 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6751 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6752 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6753 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6754 #endif 6755 6756 #undef GEN_INT_ARITH_SUBF 6757 #undef GEN_INT_ARITH_SUBF_CONST 6758 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6759 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6760 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6761 add_ca, compute_ca, compute_ov) \ 6762 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6763 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6764 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6765 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6766 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6767 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6768 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6769 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6770 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6771 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6772 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6773 6774 #undef GEN_LOGICAL1 6775 #undef GEN_LOGICAL2 6776 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6777 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6778 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6779 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6780 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6781 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6782 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6783 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6784 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6785 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6786 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6787 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6788 #if defined(TARGET_PPC64) 6789 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6790 #endif 6791 6792 #if defined(TARGET_PPC64) 6793 #undef GEN_PPC64_R2 6794 #undef GEN_PPC64_R4 6795 #define GEN_PPC64_R2(name, opc1, opc2) \ 6796 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6797 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6798 PPC_64B) 6799 #define GEN_PPC64_R4(name, opc1, opc2) \ 6800 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6801 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6802 PPC_64B), \ 6803 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6804 PPC_64B), \ 6805 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6806 PPC_64B) 6807 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6808 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6809 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6810 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6811 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6812 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6813 #endif 6814 6815 #undef GEN_LD 6816 #undef GEN_LDU 6817 #undef GEN_LDUX 6818 #undef GEN_LDX_E 6819 #undef GEN_LDS 6820 #define GEN_LD(name, ldop, opc, type) \ 6821 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6822 #define GEN_LDU(name, ldop, opc, type) \ 6823 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 6824 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 6825 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6826 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6827 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6828 #define GEN_LDS(name, ldop, op, type) \ 6829 GEN_LD(name, ldop, op | 0x20, type) \ 6830 GEN_LDU(name, ldop, op | 0x21, type) \ 6831 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 6832 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 6833 6834 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 6835 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 6836 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 6837 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 6838 #if defined(TARGET_PPC64) 6839 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 6840 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 6841 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 6842 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 6843 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6844 6845 /* HV/P7 and later only */ 6846 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6847 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6848 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6849 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6850 #endif 6851 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6852 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6853 6854 #undef GEN_ST 6855 #undef GEN_STU 6856 #undef GEN_STUX 6857 #undef GEN_STX_E 6858 #undef GEN_STS 6859 #define GEN_ST(name, stop, opc, type) \ 6860 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6861 #define GEN_STU(name, stop, opc, type) \ 6862 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 6863 #define GEN_STUX(name, stop, opc2, opc3, type) \ 6864 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6865 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6866 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6867 #define GEN_STS(name, stop, op, type) \ 6868 GEN_ST(name, stop, op | 0x20, type) \ 6869 GEN_STU(name, stop, op | 0x21, type) \ 6870 GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 6871 GEN_STX(name, stop, 0x17, op | 0x00, type) 6872 6873 GEN_STS(stb, st8, 0x06, PPC_INTEGER) 6874 GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 6875 GEN_STS(stw, st32, 0x04, PPC_INTEGER) 6876 #if defined(TARGET_PPC64) 6877 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 6878 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 6879 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6880 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6881 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6882 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6883 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6884 #endif 6885 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6886 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6887 6888 #undef GEN_CRLOGIC 6889 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6890 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6891 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6892 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6893 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6894 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6895 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6896 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6897 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6898 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6899 6900 #undef GEN_MAC_HANDLER 6901 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6902 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6903 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6904 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6905 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6906 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6907 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6908 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6909 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6910 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6911 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6912 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6913 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6914 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6915 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6916 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6917 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6918 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6919 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6920 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6921 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6922 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6923 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6924 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6925 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6926 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6927 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6928 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6929 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6930 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6931 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6932 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6933 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6934 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6935 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6936 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6937 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6938 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6939 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6940 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6941 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6942 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6943 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6944 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6945 6946 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6947 PPC_NONE, PPC2_TM), 6948 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6949 PPC_NONE, PPC2_TM), 6950 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6951 PPC_NONE, PPC2_TM), 6952 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6953 PPC_NONE, PPC2_TM), 6954 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6955 PPC_NONE, PPC2_TM), 6956 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6957 PPC_NONE, PPC2_TM), 6958 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6959 PPC_NONE, PPC2_TM), 6960 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6961 PPC_NONE, PPC2_TM), 6962 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6963 PPC_NONE, PPC2_TM), 6964 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6965 PPC_NONE, PPC2_TM), 6966 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6967 PPC_NONE, PPC2_TM), 6968 6969 #include "translate/fp-ops.inc.c" 6970 6971 #include "translate/vmx-ops.inc.c" 6972 6973 #include "translate/vsx-ops.inc.c" 6974 6975 #include "translate/dfp-ops.inc.c" 6976 6977 #include "translate/spe-ops.inc.c" 6978 }; 6979 6980 #include "helper_regs.h" 6981 #include "translate_init.inc.c" 6982 6983 /*****************************************************************************/ 6984 /* Misc PowerPC helpers */ 6985 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 6986 int flags) 6987 { 6988 #define RGPL 4 6989 #define RFPL 4 6990 6991 PowerPCCPU *cpu = POWERPC_CPU(cs); 6992 CPUPPCState *env = &cpu->env; 6993 int i; 6994 6995 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 6996 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 6997 env->nip, env->lr, env->ctr, cpu_read_xer(env), 6998 cs->cpu_index); 6999 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7000 TARGET_FMT_lx " iidx %d didx %d\n", 7001 env->msr, env->spr[SPR_HID0], 7002 env->hflags, env->immu_idx, env->dmmu_idx); 7003 #if !defined(NO_TIMER_DUMP) 7004 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7005 #if !defined(CONFIG_USER_ONLY) 7006 " DECR %08" PRIu32 7007 #endif 7008 "\n", 7009 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7010 #if !defined(CONFIG_USER_ONLY) 7011 , cpu_ppc_load_decr(env) 7012 #endif 7013 ); 7014 #endif 7015 for (i = 0; i < 32; i++) { 7016 if ((i & (RGPL - 1)) == 0) 7017 cpu_fprintf(f, "GPR%02d", i); 7018 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7019 if ((i & (RGPL - 1)) == (RGPL - 1)) 7020 cpu_fprintf(f, "\n"); 7021 } 7022 cpu_fprintf(f, "CR "); 7023 for (i = 0; i < 8; i++) 7024 cpu_fprintf(f, "%01x", env->crf[i]); 7025 cpu_fprintf(f, " ["); 7026 for (i = 0; i < 8; i++) { 7027 char a = '-'; 7028 if (env->crf[i] & 0x08) 7029 a = 'L'; 7030 else if (env->crf[i] & 0x04) 7031 a = 'G'; 7032 else if (env->crf[i] & 0x02) 7033 a = 'E'; 7034 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7035 } 7036 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7037 env->reserve_addr); 7038 7039 if (flags & CPU_DUMP_FPU) { 7040 for (i = 0; i < 32; i++) { 7041 if ((i & (RFPL - 1)) == 0) { 7042 cpu_fprintf(f, "FPR%02d", i); 7043 } 7044 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); 7045 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7046 cpu_fprintf(f, "\n"); 7047 } 7048 } 7049 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7050 } 7051 7052 #if !defined(CONFIG_USER_ONLY) 7053 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7054 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7055 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7056 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7057 7058 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7059 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7060 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7061 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7062 7063 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7064 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7065 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7066 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7067 7068 #if defined(TARGET_PPC64) 7069 if (env->excp_model == POWERPC_EXCP_POWER7 || 7070 env->excp_model == POWERPC_EXCP_POWER8) { 7071 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7072 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7073 } 7074 #endif 7075 if (env->excp_model == POWERPC_EXCP_BOOKE) { 7076 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7077 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7078 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7079 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7080 7081 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7082 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7083 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7084 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7085 7086 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7087 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7088 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7089 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7090 7091 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7092 " EPR " TARGET_FMT_lx "\n", 7093 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7094 env->spr[SPR_BOOKE_EPR]); 7095 7096 /* FSL-specific */ 7097 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7098 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7099 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7100 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7101 7102 /* 7103 * IVORs are left out as they are large and do not change often -- 7104 * they can be read with "p $ivor0", "p $ivor1", etc. 7105 */ 7106 } 7107 7108 #if defined(TARGET_PPC64) 7109 if (env->flags & POWERPC_FLAG_CFAR) { 7110 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7111 } 7112 #endif 7113 7114 if (env->spr_cb[SPR_LPCR].name) 7115 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7116 7117 switch (env->mmu_model) { 7118 case POWERPC_MMU_32B: 7119 case POWERPC_MMU_601: 7120 case POWERPC_MMU_SOFT_6xx: 7121 case POWERPC_MMU_SOFT_74xx: 7122 #if defined(TARGET_PPC64) 7123 case POWERPC_MMU_64B: 7124 case POWERPC_MMU_2_03: 7125 case POWERPC_MMU_2_06: 7126 case POWERPC_MMU_2_07: 7127 case POWERPC_MMU_3_00: 7128 #endif 7129 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7130 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7131 } 7132 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7133 cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7134 } 7135 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7136 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7137 break; 7138 case POWERPC_MMU_BOOKE206: 7139 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7140 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7141 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7142 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7143 7144 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7145 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7146 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7147 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7148 7149 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7150 " TLB1CFG " TARGET_FMT_lx "\n", 7151 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7152 env->spr[SPR_BOOKE_TLB1CFG]); 7153 break; 7154 default: 7155 break; 7156 } 7157 #endif 7158 7159 #undef RGPL 7160 #undef RFPL 7161 } 7162 7163 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, 7164 fprintf_function cpu_fprintf, int flags) 7165 { 7166 #if defined(DO_PPC_STATISTICS) 7167 PowerPCCPU *cpu = POWERPC_CPU(cs); 7168 opc_handler_t **t1, **t2, **t3, *handler; 7169 int op1, op2, op3; 7170 7171 t1 = cpu->env.opcodes; 7172 for (op1 = 0; op1 < 64; op1++) { 7173 handler = t1[op1]; 7174 if (is_indirect_opcode(handler)) { 7175 t2 = ind_table(handler); 7176 for (op2 = 0; op2 < 32; op2++) { 7177 handler = t2[op2]; 7178 if (is_indirect_opcode(handler)) { 7179 t3 = ind_table(handler); 7180 for (op3 = 0; op3 < 32; op3++) { 7181 handler = t3[op3]; 7182 if (handler->count == 0) 7183 continue; 7184 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " 7185 "%016" PRIx64 " %" PRId64 "\n", 7186 op1, op2, op3, op1, (op3 << 5) | op2, 7187 handler->oname, 7188 handler->count, handler->count); 7189 } 7190 } else { 7191 if (handler->count == 0) 7192 continue; 7193 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " 7194 "%016" PRIx64 " %" PRId64 "\n", 7195 op1, op2, op1, op2, handler->oname, 7196 handler->count, handler->count); 7197 } 7198 } 7199 } else { 7200 if (handler->count == 0) 7201 continue; 7202 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 7203 " %" PRId64 "\n", 7204 op1, op1, handler->oname, 7205 handler->count, handler->count); 7206 } 7207 } 7208 #endif 7209 } 7210 7211 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7212 { 7213 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7214 CPUPPCState *env = cs->env_ptr; 7215 int bound; 7216 7217 ctx->exception = POWERPC_EXCP_NONE; 7218 ctx->spr_cb = env->spr_cb; 7219 ctx->pr = msr_pr; 7220 ctx->mem_idx = env->dmmu_idx; 7221 ctx->dr = msr_dr; 7222 #if !defined(CONFIG_USER_ONLY) 7223 ctx->hv = msr_hv || !env->has_hv_mode; 7224 #endif 7225 ctx->insns_flags = env->insns_flags; 7226 ctx->insns_flags2 = env->insns_flags2; 7227 ctx->access_type = -1; 7228 ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7229 ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); 7230 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7231 #if defined(TARGET_PPC64) 7232 ctx->sf_mode = msr_is_64bit(env, env->msr); 7233 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7234 #endif 7235 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7236 || env->mmu_model == POWERPC_MMU_601 7237 || (env->mmu_model & POWERPC_MMU_64B); 7238 7239 ctx->fpu_enabled = !!msr_fp; 7240 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7241 ctx->spe_enabled = !!msr_spe; 7242 else 7243 ctx->spe_enabled = false; 7244 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) 7245 ctx->altivec_enabled = !!msr_vr; 7246 else 7247 ctx->altivec_enabled = false; 7248 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7249 ctx->vsx_enabled = !!msr_vsx; 7250 } else { 7251 ctx->vsx_enabled = false; 7252 } 7253 #if defined(TARGET_PPC64) 7254 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7255 ctx->tm_enabled = !!msr_tm; 7256 } else { 7257 ctx->tm_enabled = false; 7258 } 7259 #endif 7260 ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7261 if ((env->flags & POWERPC_FLAG_SE) && msr_se) 7262 ctx->singlestep_enabled = CPU_SINGLE_STEP; 7263 else 7264 ctx->singlestep_enabled = 0; 7265 if ((env->flags & POWERPC_FLAG_BE) && msr_be) 7266 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7267 if (unlikely(ctx->base.singlestep_enabled)) { 7268 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7269 } 7270 #if defined (DO_SINGLE_STEP) && 0 7271 /* Single step trace mode */ 7272 msr_se = 1; 7273 #endif 7274 7275 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 7276 ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 7277 } 7278 7279 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7280 { 7281 } 7282 7283 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7284 { 7285 tcg_gen_insn_start(dcbase->pc_next); 7286 } 7287 7288 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 7289 const CPUBreakpoint *bp) 7290 { 7291 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7292 7293 gen_debug_exception(ctx); 7294 /* The address covered by the breakpoint must be included in 7295 [tb->pc, tb->pc + tb->size) in order to for it to be 7296 properly cleared -- thus we increment the PC here so that 7297 the logic setting tb->size below does the right thing. */ 7298 ctx->base.pc_next += 4; 7299 return true; 7300 } 7301 7302 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7303 { 7304 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7305 CPUPPCState *env = cs->env_ptr; 7306 opc_handler_t **table, *handler; 7307 7308 LOG_DISAS("----------------\n"); 7309 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7310 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7311 7312 if (unlikely(need_byteswap(ctx))) { 7313 ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next)); 7314 } else { 7315 ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); 7316 } 7317 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7318 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 7319 opc3(ctx->opcode), opc4(ctx->opcode), 7320 ctx->le_mode ? "little" : "big"); 7321 ctx->base.pc_next += 4; 7322 table = env->opcodes; 7323 handler = table[opc1(ctx->opcode)]; 7324 if (is_indirect_opcode(handler)) { 7325 table = ind_table(handler); 7326 handler = table[opc2(ctx->opcode)]; 7327 if (is_indirect_opcode(handler)) { 7328 table = ind_table(handler); 7329 handler = table[opc3(ctx->opcode)]; 7330 if (is_indirect_opcode(handler)) { 7331 table = ind_table(handler); 7332 handler = table[opc4(ctx->opcode)]; 7333 } 7334 } 7335 } 7336 /* Is opcode *REALLY* valid ? */ 7337 if (unlikely(handler->handler == &gen_invalid)) { 7338 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7339 "%02x - %02x - %02x - %02x (%08x) " 7340 TARGET_FMT_lx " %d\n", 7341 opc1(ctx->opcode), opc2(ctx->opcode), 7342 opc3(ctx->opcode), opc4(ctx->opcode), 7343 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 7344 } else { 7345 uint32_t inval; 7346 7347 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7348 && Rc(ctx->opcode))) { 7349 inval = handler->inval2; 7350 } else { 7351 inval = handler->inval1; 7352 } 7353 7354 if (unlikely((ctx->opcode & inval) != 0)) { 7355 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7356 "%02x - %02x - %02x - %02x (%08x) " 7357 TARGET_FMT_lx "\n", ctx->opcode & inval, 7358 opc1(ctx->opcode), opc2(ctx->opcode), 7359 opc3(ctx->opcode), opc4(ctx->opcode), 7360 ctx->opcode, ctx->base.pc_next - 4); 7361 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7362 ctx->base.is_jmp = DISAS_NORETURN; 7363 return; 7364 } 7365 } 7366 (*(handler->handler))(ctx); 7367 #if defined(DO_PPC_STATISTICS) 7368 handler->count++; 7369 #endif 7370 /* Check trace mode exceptions */ 7371 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 7372 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 7373 ctx->exception != POWERPC_SYSCALL && 7374 ctx->exception != POWERPC_EXCP_TRAP && 7375 ctx->exception != POWERPC_EXCP_BRANCH)) { 7376 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, ctx->base.pc_next); 7377 } 7378 7379 if (tcg_check_temp_count()) { 7380 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 7381 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 7382 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 7383 } 7384 7385 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 7386 DISAS_NEXT : DISAS_NORETURN; 7387 } 7388 7389 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7390 { 7391 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7392 7393 if (ctx->exception == POWERPC_EXCP_NONE) { 7394 gen_goto_tb(ctx, 0, ctx->base.pc_next); 7395 } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 7396 if (unlikely(ctx->base.singlestep_enabled)) { 7397 gen_debug_exception(ctx); 7398 } 7399 /* Generate the return instruction */ 7400 tcg_gen_exit_tb(NULL, 0); 7401 } 7402 } 7403 7404 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 7405 { 7406 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 7407 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 7408 } 7409 7410 static const TranslatorOps ppc_tr_ops = { 7411 .init_disas_context = ppc_tr_init_disas_context, 7412 .tb_start = ppc_tr_tb_start, 7413 .insn_start = ppc_tr_insn_start, 7414 .breakpoint_check = ppc_tr_breakpoint_check, 7415 .translate_insn = ppc_tr_translate_insn, 7416 .tb_stop = ppc_tr_tb_stop, 7417 .disas_log = ppc_tr_disas_log, 7418 }; 7419 7420 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 7421 { 7422 DisasContext ctx; 7423 7424 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); 7425 } 7426 7427 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7428 target_ulong *data) 7429 { 7430 env->nip = data[0]; 7431 } 7432