1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 #include "qemu/main-loop.h" 30 #include "exec/cpu_ldst.h" 31 32 #include "exec/helper-proto.h" 33 #include "exec/helper-gen.h" 34 35 #include "trace-tcg.h" 36 #include "exec/translator.h" 37 #include "exec/log.h" 38 #include "qemu/atomic128.h" 39 40 41 #define CPU_SINGLE_STEP 0x1 42 #define CPU_BRANCH_STEP 0x2 43 #define GDBSTUB_SINGLE_STEP 0x4 44 45 /* Include definitions for instructions classes and implementations flags */ 46 /* #define PPC_DEBUG_DISAS */ 47 /* #define DO_PPC_STATISTICS */ 48 49 #ifdef PPC_DEBUG_DISAS 50 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51 #else 52 # define LOG_DISAS(...) do { } while (0) 53 #endif 54 /*****************************************************************************/ 55 /* Code translation helpers */ 56 57 /* global register indexes */ 58 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59 + 10 * 4 + 22 * 5 /* SPE GPRh */ 60 + 8 * 5 /* CRF */]; 61 static TCGv cpu_gpr[32]; 62 static TCGv cpu_gprh[32]; 63 static TCGv_i32 cpu_crf[8]; 64 static TCGv cpu_nip; 65 static TCGv cpu_msr; 66 static TCGv cpu_ctr; 67 static TCGv cpu_lr; 68 #if defined(TARGET_PPC64) 69 static TCGv cpu_cfar; 70 #endif 71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72 static TCGv cpu_reserve; 73 static TCGv cpu_reserve_val; 74 static TCGv cpu_fpscr; 75 static TCGv_i32 cpu_access_type; 76 77 #include "exec/gen-icount.h" 78 79 void ppc_translate_init(void) 80 { 81 int i; 82 char *p; 83 size_t cpu_reg_names_size; 84 85 p = cpu_reg_names; 86 cpu_reg_names_size = sizeof(cpu_reg_names); 87 88 for (i = 0; i < 8; i++) { 89 snprintf(p, cpu_reg_names_size, "crf%d", i); 90 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91 offsetof(CPUPPCState, crf[i]), p); 92 p += 5; 93 cpu_reg_names_size -= 5; 94 } 95 96 for (i = 0; i < 32; i++) { 97 snprintf(p, cpu_reg_names_size, "r%d", i); 98 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99 offsetof(CPUPPCState, gpr[i]), p); 100 p += (i < 10) ? 3 : 4; 101 cpu_reg_names_size -= (i < 10) ? 3 : 4; 102 snprintf(p, cpu_reg_names_size, "r%dH", i); 103 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104 offsetof(CPUPPCState, gprh[i]), p); 105 p += (i < 10) ? 4 : 5; 106 cpu_reg_names_size -= (i < 10) ? 4 : 5; 107 } 108 109 cpu_nip = tcg_global_mem_new(cpu_env, 110 offsetof(CPUPPCState, nip), "nip"); 111 112 cpu_msr = tcg_global_mem_new(cpu_env, 113 offsetof(CPUPPCState, msr), "msr"); 114 115 cpu_ctr = tcg_global_mem_new(cpu_env, 116 offsetof(CPUPPCState, ctr), "ctr"); 117 118 cpu_lr = tcg_global_mem_new(cpu_env, 119 offsetof(CPUPPCState, lr), "lr"); 120 121 #if defined(TARGET_PPC64) 122 cpu_cfar = tcg_global_mem_new(cpu_env, 123 offsetof(CPUPPCState, cfar), "cfar"); 124 #endif 125 126 cpu_xer = tcg_global_mem_new(cpu_env, 127 offsetof(CPUPPCState, xer), "xer"); 128 cpu_so = tcg_global_mem_new(cpu_env, 129 offsetof(CPUPPCState, so), "SO"); 130 cpu_ov = tcg_global_mem_new(cpu_env, 131 offsetof(CPUPPCState, ov), "OV"); 132 cpu_ca = tcg_global_mem_new(cpu_env, 133 offsetof(CPUPPCState, ca), "CA"); 134 cpu_ov32 = tcg_global_mem_new(cpu_env, 135 offsetof(CPUPPCState, ov32), "OV32"); 136 cpu_ca32 = tcg_global_mem_new(cpu_env, 137 offsetof(CPUPPCState, ca32), "CA32"); 138 139 cpu_reserve = tcg_global_mem_new(cpu_env, 140 offsetof(CPUPPCState, reserve_addr), 141 "reserve_addr"); 142 cpu_reserve_val = tcg_global_mem_new(cpu_env, 143 offsetof(CPUPPCState, reserve_val), 144 "reserve_val"); 145 146 cpu_fpscr = tcg_global_mem_new(cpu_env, 147 offsetof(CPUPPCState, fpscr), "fpscr"); 148 149 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150 offsetof(CPUPPCState, access_type), 151 "access_type"); 152 } 153 154 /* internal defines */ 155 struct DisasContext { 156 DisasContextBase base; 157 uint32_t opcode; 158 uint32_t exception; 159 /* Routine used to access memory */ 160 bool pr, hv, dr, le_mode; 161 bool lazy_tlb_flush; 162 bool need_access_type; 163 int mem_idx; 164 int access_type; 165 /* Translation flags */ 166 MemOp default_tcg_memop_mask; 167 #if defined(TARGET_PPC64) 168 bool sf_mode; 169 bool has_cfar; 170 #endif 171 bool fpu_enabled; 172 bool altivec_enabled; 173 bool vsx_enabled; 174 bool spe_enabled; 175 bool tm_enabled; 176 bool gtse; 177 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 178 int singlestep_enabled; 179 uint32_t flags; 180 uint64_t insns_flags; 181 uint64_t insns_flags2; 182 }; 183 184 /* Return true iff byteswap is needed in a scalar memop */ 185 static inline bool need_byteswap(const DisasContext *ctx) 186 { 187 #if defined(TARGET_WORDS_BIGENDIAN) 188 return ctx->le_mode; 189 #else 190 return !ctx->le_mode; 191 #endif 192 } 193 194 /* True when active word size < size of target_long. */ 195 #ifdef TARGET_PPC64 196 # define NARROW_MODE(C) (!(C)->sf_mode) 197 #else 198 # define NARROW_MODE(C) 0 199 #endif 200 201 struct opc_handler_t { 202 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 203 uint32_t inval1; 204 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 205 uint32_t inval2; 206 /* instruction type */ 207 uint64_t type; 208 /* extended instruction type */ 209 uint64_t type2; 210 /* handler */ 211 void (*handler)(DisasContext *ctx); 212 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 213 const char *oname; 214 #endif 215 #if defined(DO_PPC_STATISTICS) 216 uint64_t count; 217 #endif 218 }; 219 220 /* SPR load/store helpers */ 221 static inline void gen_load_spr(TCGv t, int reg) 222 { 223 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 224 } 225 226 static inline void gen_store_spr(int reg, TCGv t) 227 { 228 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 229 } 230 231 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 232 { 233 if (ctx->need_access_type && ctx->access_type != access_type) { 234 tcg_gen_movi_i32(cpu_access_type, access_type); 235 ctx->access_type = access_type; 236 } 237 } 238 239 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 240 { 241 if (NARROW_MODE(ctx)) { 242 nip = (uint32_t)nip; 243 } 244 tcg_gen_movi_tl(cpu_nip, nip); 245 } 246 247 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 248 { 249 TCGv_i32 t0, t1; 250 251 /* 252 * These are all synchronous exceptions, we set the PC back to the 253 * faulting instruction 254 */ 255 if (ctx->exception == POWERPC_EXCP_NONE) { 256 gen_update_nip(ctx, ctx->base.pc_next - 4); 257 } 258 t0 = tcg_const_i32(excp); 259 t1 = tcg_const_i32(error); 260 gen_helper_raise_exception_err(cpu_env, t0, t1); 261 tcg_temp_free_i32(t0); 262 tcg_temp_free_i32(t1); 263 ctx->exception = (excp); 264 } 265 266 static void gen_exception(DisasContext *ctx, uint32_t excp) 267 { 268 TCGv_i32 t0; 269 270 /* 271 * These are all synchronous exceptions, we set the PC back to the 272 * faulting instruction 273 */ 274 if (ctx->exception == POWERPC_EXCP_NONE) { 275 gen_update_nip(ctx, ctx->base.pc_next - 4); 276 } 277 t0 = tcg_const_i32(excp); 278 gen_helper_raise_exception(cpu_env, t0); 279 tcg_temp_free_i32(t0); 280 ctx->exception = (excp); 281 } 282 283 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 284 target_ulong nip) 285 { 286 TCGv_i32 t0; 287 288 gen_update_nip(ctx, nip); 289 t0 = tcg_const_i32(excp); 290 gen_helper_raise_exception(cpu_env, t0); 291 tcg_temp_free_i32(t0); 292 ctx->exception = (excp); 293 } 294 295 /* 296 * Tells the caller what is the appropriate exception to generate and prepares 297 * SPR registers for this exception. 298 * 299 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 300 * POWERPC_EXCP_DEBUG (on BookE). 301 */ 302 static uint32_t gen_prep_dbgex(DisasContext *ctx) 303 { 304 if (ctx->flags & POWERPC_FLAG_DE) { 305 target_ulong dbsr = 0; 306 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 307 dbsr = DBCR0_ICMP; 308 } else { 309 /* Must have been branch */ 310 dbsr = DBCR0_BRT; 311 } 312 TCGv t0 = tcg_temp_new(); 313 gen_load_spr(t0, SPR_BOOKE_DBSR); 314 tcg_gen_ori_tl(t0, t0, dbsr); 315 gen_store_spr(SPR_BOOKE_DBSR, t0); 316 tcg_temp_free(t0); 317 return POWERPC_EXCP_DEBUG; 318 } else { 319 return POWERPC_EXCP_TRACE; 320 } 321 } 322 323 static void gen_debug_exception(DisasContext *ctx) 324 { 325 TCGv_i32 t0; 326 327 /* 328 * These are all synchronous exceptions, we set the PC back to the 329 * faulting instruction 330 */ 331 if ((ctx->exception != POWERPC_EXCP_BRANCH) && 332 (ctx->exception != POWERPC_EXCP_SYNC)) { 333 gen_update_nip(ctx, ctx->base.pc_next); 334 } 335 t0 = tcg_const_i32(EXCP_DEBUG); 336 gen_helper_raise_exception(cpu_env, t0); 337 tcg_temp_free_i32(t0); 338 } 339 340 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 341 { 342 /* Will be converted to program check if needed */ 343 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 344 } 345 346 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 347 { 348 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 349 } 350 351 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 352 { 353 /* Will be converted to program check if needed */ 354 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 355 } 356 357 /* Stop translation */ 358 static inline void gen_stop_exception(DisasContext *ctx) 359 { 360 gen_update_nip(ctx, ctx->base.pc_next); 361 ctx->exception = POWERPC_EXCP_STOP; 362 } 363 364 #ifndef CONFIG_USER_ONLY 365 /* No need to update nip here, as execution flow will change */ 366 static inline void gen_sync_exception(DisasContext *ctx) 367 { 368 ctx->exception = POWERPC_EXCP_SYNC; 369 } 370 #endif 371 372 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 373 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 374 375 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 376 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 377 378 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 379 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 380 381 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 382 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 383 384 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 385 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 386 387 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 388 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 389 390 typedef struct opcode_t { 391 unsigned char opc1, opc2, opc3, opc4; 392 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 393 unsigned char pad[4]; 394 #endif 395 opc_handler_t handler; 396 const char *oname; 397 } opcode_t; 398 399 /* Helpers for priv. check */ 400 #define GEN_PRIV \ 401 do { \ 402 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 403 } while (0) 404 405 #if defined(CONFIG_USER_ONLY) 406 #define CHK_HV GEN_PRIV 407 #define CHK_SV GEN_PRIV 408 #define CHK_HVRM GEN_PRIV 409 #else 410 #define CHK_HV \ 411 do { \ 412 if (unlikely(ctx->pr || !ctx->hv)) { \ 413 GEN_PRIV; \ 414 } \ 415 } while (0) 416 #define CHK_SV \ 417 do { \ 418 if (unlikely(ctx->pr)) { \ 419 GEN_PRIV; \ 420 } \ 421 } while (0) 422 #define CHK_HVRM \ 423 do { \ 424 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 425 GEN_PRIV; \ 426 } \ 427 } while (0) 428 #endif 429 430 #define CHK_NONE 431 432 /*****************************************************************************/ 433 /* PowerPC instructions table */ 434 435 #if defined(DO_PPC_STATISTICS) 436 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 437 { \ 438 .opc1 = op1, \ 439 .opc2 = op2, \ 440 .opc3 = op3, \ 441 .opc4 = 0xff, \ 442 .handler = { \ 443 .inval1 = invl, \ 444 .type = _typ, \ 445 .type2 = _typ2, \ 446 .handler = &gen_##name, \ 447 .oname = stringify(name), \ 448 }, \ 449 .oname = stringify(name), \ 450 } 451 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 452 { \ 453 .opc1 = op1, \ 454 .opc2 = op2, \ 455 .opc3 = op3, \ 456 .opc4 = 0xff, \ 457 .handler = { \ 458 .inval1 = invl1, \ 459 .inval2 = invl2, \ 460 .type = _typ, \ 461 .type2 = _typ2, \ 462 .handler = &gen_##name, \ 463 .oname = stringify(name), \ 464 }, \ 465 .oname = stringify(name), \ 466 } 467 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 468 { \ 469 .opc1 = op1, \ 470 .opc2 = op2, \ 471 .opc3 = op3, \ 472 .opc4 = 0xff, \ 473 .handler = { \ 474 .inval1 = invl, \ 475 .type = _typ, \ 476 .type2 = _typ2, \ 477 .handler = &gen_##name, \ 478 .oname = onam, \ 479 }, \ 480 .oname = onam, \ 481 } 482 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 483 { \ 484 .opc1 = op1, \ 485 .opc2 = op2, \ 486 .opc3 = op3, \ 487 .opc4 = op4, \ 488 .handler = { \ 489 .inval1 = invl, \ 490 .type = _typ, \ 491 .type2 = _typ2, \ 492 .handler = &gen_##name, \ 493 .oname = stringify(name), \ 494 }, \ 495 .oname = stringify(name), \ 496 } 497 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 498 { \ 499 .opc1 = op1, \ 500 .opc2 = op2, \ 501 .opc3 = op3, \ 502 .opc4 = op4, \ 503 .handler = { \ 504 .inval1 = invl, \ 505 .type = _typ, \ 506 .type2 = _typ2, \ 507 .handler = &gen_##name, \ 508 .oname = onam, \ 509 }, \ 510 .oname = onam, \ 511 } 512 #else 513 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 514 { \ 515 .opc1 = op1, \ 516 .opc2 = op2, \ 517 .opc3 = op3, \ 518 .opc4 = 0xff, \ 519 .handler = { \ 520 .inval1 = invl, \ 521 .type = _typ, \ 522 .type2 = _typ2, \ 523 .handler = &gen_##name, \ 524 }, \ 525 .oname = stringify(name), \ 526 } 527 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 528 { \ 529 .opc1 = op1, \ 530 .opc2 = op2, \ 531 .opc3 = op3, \ 532 .opc4 = 0xff, \ 533 .handler = { \ 534 .inval1 = invl1, \ 535 .inval2 = invl2, \ 536 .type = _typ, \ 537 .type2 = _typ2, \ 538 .handler = &gen_##name, \ 539 }, \ 540 .oname = stringify(name), \ 541 } 542 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 543 { \ 544 .opc1 = op1, \ 545 .opc2 = op2, \ 546 .opc3 = op3, \ 547 .opc4 = 0xff, \ 548 .handler = { \ 549 .inval1 = invl, \ 550 .type = _typ, \ 551 .type2 = _typ2, \ 552 .handler = &gen_##name, \ 553 }, \ 554 .oname = onam, \ 555 } 556 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 557 { \ 558 .opc1 = op1, \ 559 .opc2 = op2, \ 560 .opc3 = op3, \ 561 .opc4 = op4, \ 562 .handler = { \ 563 .inval1 = invl, \ 564 .type = _typ, \ 565 .type2 = _typ2, \ 566 .handler = &gen_##name, \ 567 }, \ 568 .oname = stringify(name), \ 569 } 570 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 571 { \ 572 .opc1 = op1, \ 573 .opc2 = op2, \ 574 .opc3 = op3, \ 575 .opc4 = op4, \ 576 .handler = { \ 577 .inval1 = invl, \ 578 .type = _typ, \ 579 .type2 = _typ2, \ 580 .handler = &gen_##name, \ 581 }, \ 582 .oname = onam, \ 583 } 584 #endif 585 586 /* Invalid instruction */ 587 static void gen_invalid(DisasContext *ctx) 588 { 589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 590 } 591 592 static opc_handler_t invalid_handler = { 593 .inval1 = 0xFFFFFFFF, 594 .inval2 = 0xFFFFFFFF, 595 .type = PPC_NONE, 596 .type2 = PPC_NONE, 597 .handler = gen_invalid, 598 }; 599 600 /*** Integer comparison ***/ 601 602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 603 { 604 TCGv t0 = tcg_temp_new(); 605 TCGv t1 = tcg_temp_new(); 606 TCGv_i32 t = tcg_temp_new_i32(); 607 608 tcg_gen_movi_tl(t0, CRF_EQ); 609 tcg_gen_movi_tl(t1, CRF_LT); 610 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 611 t0, arg0, arg1, t1, t0); 612 tcg_gen_movi_tl(t1, CRF_GT); 613 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 614 t0, arg0, arg1, t1, t0); 615 616 tcg_gen_trunc_tl_i32(t, t0); 617 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 618 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 619 620 tcg_temp_free(t0); 621 tcg_temp_free(t1); 622 tcg_temp_free_i32(t); 623 } 624 625 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 626 { 627 TCGv t0 = tcg_const_tl(arg1); 628 gen_op_cmp(arg0, t0, s, crf); 629 tcg_temp_free(t0); 630 } 631 632 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 633 { 634 TCGv t0, t1; 635 t0 = tcg_temp_new(); 636 t1 = tcg_temp_new(); 637 if (s) { 638 tcg_gen_ext32s_tl(t0, arg0); 639 tcg_gen_ext32s_tl(t1, arg1); 640 } else { 641 tcg_gen_ext32u_tl(t0, arg0); 642 tcg_gen_ext32u_tl(t1, arg1); 643 } 644 gen_op_cmp(t0, t1, s, crf); 645 tcg_temp_free(t1); 646 tcg_temp_free(t0); 647 } 648 649 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 650 { 651 TCGv t0 = tcg_const_tl(arg1); 652 gen_op_cmp32(arg0, t0, s, crf); 653 tcg_temp_free(t0); 654 } 655 656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 657 { 658 if (NARROW_MODE(ctx)) { 659 gen_op_cmpi32(reg, 0, 1, 0); 660 } else { 661 gen_op_cmpi(reg, 0, 1, 0); 662 } 663 } 664 665 /* cmp */ 666 static void gen_cmp(DisasContext *ctx) 667 { 668 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 669 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 670 1, crfD(ctx->opcode)); 671 } else { 672 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 673 1, crfD(ctx->opcode)); 674 } 675 } 676 677 /* cmpi */ 678 static void gen_cmpi(DisasContext *ctx) 679 { 680 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 681 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 682 1, crfD(ctx->opcode)); 683 } else { 684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 685 1, crfD(ctx->opcode)); 686 } 687 } 688 689 /* cmpl */ 690 static void gen_cmpl(DisasContext *ctx) 691 { 692 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 693 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 694 0, crfD(ctx->opcode)); 695 } else { 696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 697 0, crfD(ctx->opcode)); 698 } 699 } 700 701 /* cmpli */ 702 static void gen_cmpli(DisasContext *ctx) 703 { 704 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 705 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 706 0, crfD(ctx->opcode)); 707 } else { 708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 709 0, crfD(ctx->opcode)); 710 } 711 } 712 713 /* cmprb - range comparison: isupper, isaplha, islower*/ 714 static void gen_cmprb(DisasContext *ctx) 715 { 716 TCGv_i32 src1 = tcg_temp_new_i32(); 717 TCGv_i32 src2 = tcg_temp_new_i32(); 718 TCGv_i32 src2lo = tcg_temp_new_i32(); 719 TCGv_i32 src2hi = tcg_temp_new_i32(); 720 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 721 722 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 723 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 724 725 tcg_gen_andi_i32(src1, src1, 0xFF); 726 tcg_gen_ext8u_i32(src2lo, src2); 727 tcg_gen_shri_i32(src2, src2, 8); 728 tcg_gen_ext8u_i32(src2hi, src2); 729 730 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 731 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 732 tcg_gen_and_i32(crf, src2lo, src2hi); 733 734 if (ctx->opcode & 0x00200000) { 735 tcg_gen_shri_i32(src2, src2, 8); 736 tcg_gen_ext8u_i32(src2lo, src2); 737 tcg_gen_shri_i32(src2, src2, 8); 738 tcg_gen_ext8u_i32(src2hi, src2); 739 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 740 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 741 tcg_gen_and_i32(src2lo, src2lo, src2hi); 742 tcg_gen_or_i32(crf, crf, src2lo); 743 } 744 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 745 tcg_temp_free_i32(src1); 746 tcg_temp_free_i32(src2); 747 tcg_temp_free_i32(src2lo); 748 tcg_temp_free_i32(src2hi); 749 } 750 751 #if defined(TARGET_PPC64) 752 /* cmpeqb */ 753 static void gen_cmpeqb(DisasContext *ctx) 754 { 755 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 756 cpu_gpr[rB(ctx->opcode)]); 757 } 758 #endif 759 760 /* isel (PowerPC 2.03 specification) */ 761 static void gen_isel(DisasContext *ctx) 762 { 763 uint32_t bi = rC(ctx->opcode); 764 uint32_t mask = 0x08 >> (bi & 0x03); 765 TCGv t0 = tcg_temp_new(); 766 TCGv zr; 767 768 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 769 tcg_gen_andi_tl(t0, t0, mask); 770 771 zr = tcg_const_tl(0); 772 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 773 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 774 cpu_gpr[rB(ctx->opcode)]); 775 tcg_temp_free(zr); 776 tcg_temp_free(t0); 777 } 778 779 /* cmpb: PowerPC 2.05 specification */ 780 static void gen_cmpb(DisasContext *ctx) 781 { 782 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 783 cpu_gpr[rB(ctx->opcode)]); 784 } 785 786 /*** Integer arithmetic ***/ 787 788 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 789 TCGv arg1, TCGv arg2, int sub) 790 { 791 TCGv t0 = tcg_temp_new(); 792 793 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 794 tcg_gen_xor_tl(t0, arg1, arg2); 795 if (sub) { 796 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 797 } else { 798 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 799 } 800 tcg_temp_free(t0); 801 if (NARROW_MODE(ctx)) { 802 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 803 if (is_isa300(ctx)) { 804 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 805 } 806 } else { 807 if (is_isa300(ctx)) { 808 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 809 } 810 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 811 } 812 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 813 } 814 815 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 816 TCGv res, TCGv arg0, TCGv arg1, 817 TCGv ca32, int sub) 818 { 819 TCGv t0; 820 821 if (!is_isa300(ctx)) { 822 return; 823 } 824 825 t0 = tcg_temp_new(); 826 if (sub) { 827 tcg_gen_eqv_tl(t0, arg0, arg1); 828 } else { 829 tcg_gen_xor_tl(t0, arg0, arg1); 830 } 831 tcg_gen_xor_tl(t0, t0, res); 832 tcg_gen_extract_tl(ca32, t0, 32, 1); 833 tcg_temp_free(t0); 834 } 835 836 /* Common add function */ 837 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 838 TCGv arg2, TCGv ca, TCGv ca32, 839 bool add_ca, bool compute_ca, 840 bool compute_ov, bool compute_rc0) 841 { 842 TCGv t0 = ret; 843 844 if (compute_ca || compute_ov) { 845 t0 = tcg_temp_new(); 846 } 847 848 if (compute_ca) { 849 if (NARROW_MODE(ctx)) { 850 /* 851 * Caution: a non-obvious corner case of the spec is that 852 * we must produce the *entire* 64-bit addition, but 853 * produce the carry into bit 32. 854 */ 855 TCGv t1 = tcg_temp_new(); 856 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 857 tcg_gen_add_tl(t0, arg1, arg2); 858 if (add_ca) { 859 tcg_gen_add_tl(t0, t0, ca); 860 } 861 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 862 tcg_temp_free(t1); 863 tcg_gen_extract_tl(ca, ca, 32, 1); 864 if (is_isa300(ctx)) { 865 tcg_gen_mov_tl(ca32, ca); 866 } 867 } else { 868 TCGv zero = tcg_const_tl(0); 869 if (add_ca) { 870 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 871 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 872 } else { 873 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 874 } 875 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 876 tcg_temp_free(zero); 877 } 878 } else { 879 tcg_gen_add_tl(t0, arg1, arg2); 880 if (add_ca) { 881 tcg_gen_add_tl(t0, t0, ca); 882 } 883 } 884 885 if (compute_ov) { 886 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 887 } 888 if (unlikely(compute_rc0)) { 889 gen_set_Rc0(ctx, t0); 890 } 891 892 if (t0 != ret) { 893 tcg_gen_mov_tl(ret, t0); 894 tcg_temp_free(t0); 895 } 896 } 897 /* Add functions with two operands */ 898 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 899 static void glue(gen_, name)(DisasContext *ctx) \ 900 { \ 901 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 902 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 903 ca, glue(ca, 32), \ 904 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 905 } 906 /* Add functions with one operand and one immediate */ 907 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 908 add_ca, compute_ca, compute_ov) \ 909 static void glue(gen_, name)(DisasContext *ctx) \ 910 { \ 911 TCGv t0 = tcg_const_tl(const_val); \ 912 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 913 cpu_gpr[rA(ctx->opcode)], t0, \ 914 ca, glue(ca, 32), \ 915 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 916 tcg_temp_free(t0); \ 917 } 918 919 /* add add. addo addo. */ 920 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 921 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 922 /* addc addc. addco addco. */ 923 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 924 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 925 /* adde adde. addeo addeo. */ 926 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 927 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 928 /* addme addme. addmeo addmeo. */ 929 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 930 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 931 /* addex */ 932 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 933 /* addze addze. addzeo addzeo.*/ 934 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 935 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 936 /* addi */ 937 static void gen_addi(DisasContext *ctx) 938 { 939 target_long simm = SIMM(ctx->opcode); 940 941 if (rA(ctx->opcode) == 0) { 942 /* li case */ 943 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 944 } else { 945 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 946 cpu_gpr[rA(ctx->opcode)], simm); 947 } 948 } 949 /* addic addic.*/ 950 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 951 { 952 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 953 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 954 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 955 tcg_temp_free(c); 956 } 957 958 static void gen_addic(DisasContext *ctx) 959 { 960 gen_op_addic(ctx, 0); 961 } 962 963 static void gen_addic_(DisasContext *ctx) 964 { 965 gen_op_addic(ctx, 1); 966 } 967 968 /* addis */ 969 static void gen_addis(DisasContext *ctx) 970 { 971 target_long simm = SIMM(ctx->opcode); 972 973 if (rA(ctx->opcode) == 0) { 974 /* lis case */ 975 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 976 } else { 977 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 978 cpu_gpr[rA(ctx->opcode)], simm << 16); 979 } 980 } 981 982 /* addpcis */ 983 static void gen_addpcis(DisasContext *ctx) 984 { 985 target_long d = DX(ctx->opcode); 986 987 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 988 } 989 990 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 991 TCGv arg2, int sign, int compute_ov) 992 { 993 TCGv_i32 t0 = tcg_temp_new_i32(); 994 TCGv_i32 t1 = tcg_temp_new_i32(); 995 TCGv_i32 t2 = tcg_temp_new_i32(); 996 TCGv_i32 t3 = tcg_temp_new_i32(); 997 998 tcg_gen_trunc_tl_i32(t0, arg1); 999 tcg_gen_trunc_tl_i32(t1, arg2); 1000 if (sign) { 1001 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1002 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1003 tcg_gen_and_i32(t2, t2, t3); 1004 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1005 tcg_gen_or_i32(t2, t2, t3); 1006 tcg_gen_movi_i32(t3, 0); 1007 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1008 tcg_gen_div_i32(t3, t0, t1); 1009 tcg_gen_extu_i32_tl(ret, t3); 1010 } else { 1011 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1012 tcg_gen_movi_i32(t3, 0); 1013 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1014 tcg_gen_divu_i32(t3, t0, t1); 1015 tcg_gen_extu_i32_tl(ret, t3); 1016 } 1017 if (compute_ov) { 1018 tcg_gen_extu_i32_tl(cpu_ov, t2); 1019 if (is_isa300(ctx)) { 1020 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1021 } 1022 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1023 } 1024 tcg_temp_free_i32(t0); 1025 tcg_temp_free_i32(t1); 1026 tcg_temp_free_i32(t2); 1027 tcg_temp_free_i32(t3); 1028 1029 if (unlikely(Rc(ctx->opcode) != 0)) { 1030 gen_set_Rc0(ctx, ret); 1031 } 1032 } 1033 /* Div functions */ 1034 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1035 static void glue(gen_, name)(DisasContext *ctx) \ 1036 { \ 1037 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1038 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1039 sign, compute_ov); \ 1040 } 1041 /* divwu divwu. divwuo divwuo. */ 1042 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1043 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1044 /* divw divw. divwo divwo. */ 1045 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1046 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1047 1048 /* div[wd]eu[o][.] */ 1049 #define GEN_DIVE(name, hlpr, compute_ov) \ 1050 static void gen_##name(DisasContext *ctx) \ 1051 { \ 1052 TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1053 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1054 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1055 tcg_temp_free_i32(t0); \ 1056 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1057 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1058 } \ 1059 } 1060 1061 GEN_DIVE(divweu, divweu, 0); 1062 GEN_DIVE(divweuo, divweu, 1); 1063 GEN_DIVE(divwe, divwe, 0); 1064 GEN_DIVE(divweo, divwe, 1); 1065 1066 #if defined(TARGET_PPC64) 1067 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1068 TCGv arg2, int sign, int compute_ov) 1069 { 1070 TCGv_i64 t0 = tcg_temp_new_i64(); 1071 TCGv_i64 t1 = tcg_temp_new_i64(); 1072 TCGv_i64 t2 = tcg_temp_new_i64(); 1073 TCGv_i64 t3 = tcg_temp_new_i64(); 1074 1075 tcg_gen_mov_i64(t0, arg1); 1076 tcg_gen_mov_i64(t1, arg2); 1077 if (sign) { 1078 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1079 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1080 tcg_gen_and_i64(t2, t2, t3); 1081 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1082 tcg_gen_or_i64(t2, t2, t3); 1083 tcg_gen_movi_i64(t3, 0); 1084 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1085 tcg_gen_div_i64(ret, t0, t1); 1086 } else { 1087 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1088 tcg_gen_movi_i64(t3, 0); 1089 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1090 tcg_gen_divu_i64(ret, t0, t1); 1091 } 1092 if (compute_ov) { 1093 tcg_gen_mov_tl(cpu_ov, t2); 1094 if (is_isa300(ctx)) { 1095 tcg_gen_mov_tl(cpu_ov32, t2); 1096 } 1097 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1098 } 1099 tcg_temp_free_i64(t0); 1100 tcg_temp_free_i64(t1); 1101 tcg_temp_free_i64(t2); 1102 tcg_temp_free_i64(t3); 1103 1104 if (unlikely(Rc(ctx->opcode) != 0)) { 1105 gen_set_Rc0(ctx, ret); 1106 } 1107 } 1108 1109 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1110 static void glue(gen_, name)(DisasContext *ctx) \ 1111 { \ 1112 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1113 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1114 sign, compute_ov); \ 1115 } 1116 /* divdu divdu. divduo divduo. */ 1117 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1118 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1119 /* divd divd. divdo divdo. */ 1120 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1121 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1122 1123 GEN_DIVE(divdeu, divdeu, 0); 1124 GEN_DIVE(divdeuo, divdeu, 1); 1125 GEN_DIVE(divde, divde, 0); 1126 GEN_DIVE(divdeo, divde, 1); 1127 #endif 1128 1129 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1130 TCGv arg2, int sign) 1131 { 1132 TCGv_i32 t0 = tcg_temp_new_i32(); 1133 TCGv_i32 t1 = tcg_temp_new_i32(); 1134 1135 tcg_gen_trunc_tl_i32(t0, arg1); 1136 tcg_gen_trunc_tl_i32(t1, arg2); 1137 if (sign) { 1138 TCGv_i32 t2 = tcg_temp_new_i32(); 1139 TCGv_i32 t3 = tcg_temp_new_i32(); 1140 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1141 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1142 tcg_gen_and_i32(t2, t2, t3); 1143 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1144 tcg_gen_or_i32(t2, t2, t3); 1145 tcg_gen_movi_i32(t3, 0); 1146 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1147 tcg_gen_rem_i32(t3, t0, t1); 1148 tcg_gen_ext_i32_tl(ret, t3); 1149 tcg_temp_free_i32(t2); 1150 tcg_temp_free_i32(t3); 1151 } else { 1152 TCGv_i32 t2 = tcg_const_i32(1); 1153 TCGv_i32 t3 = tcg_const_i32(0); 1154 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1155 tcg_gen_remu_i32(t3, t0, t1); 1156 tcg_gen_extu_i32_tl(ret, t3); 1157 tcg_temp_free_i32(t2); 1158 tcg_temp_free_i32(t3); 1159 } 1160 tcg_temp_free_i32(t0); 1161 tcg_temp_free_i32(t1); 1162 } 1163 1164 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1165 static void glue(gen_, name)(DisasContext *ctx) \ 1166 { \ 1167 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1168 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1169 sign); \ 1170 } 1171 1172 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1173 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1174 1175 #if defined(TARGET_PPC64) 1176 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1177 TCGv arg2, int sign) 1178 { 1179 TCGv_i64 t0 = tcg_temp_new_i64(); 1180 TCGv_i64 t1 = tcg_temp_new_i64(); 1181 1182 tcg_gen_mov_i64(t0, arg1); 1183 tcg_gen_mov_i64(t1, arg2); 1184 if (sign) { 1185 TCGv_i64 t2 = tcg_temp_new_i64(); 1186 TCGv_i64 t3 = tcg_temp_new_i64(); 1187 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1188 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1189 tcg_gen_and_i64(t2, t2, t3); 1190 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1191 tcg_gen_or_i64(t2, t2, t3); 1192 tcg_gen_movi_i64(t3, 0); 1193 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1194 tcg_gen_rem_i64(ret, t0, t1); 1195 tcg_temp_free_i64(t2); 1196 tcg_temp_free_i64(t3); 1197 } else { 1198 TCGv_i64 t2 = tcg_const_i64(1); 1199 TCGv_i64 t3 = tcg_const_i64(0); 1200 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1201 tcg_gen_remu_i64(ret, t0, t1); 1202 tcg_temp_free_i64(t2); 1203 tcg_temp_free_i64(t3); 1204 } 1205 tcg_temp_free_i64(t0); 1206 tcg_temp_free_i64(t1); 1207 } 1208 1209 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1210 static void glue(gen_, name)(DisasContext *ctx) \ 1211 { \ 1212 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1213 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1214 sign); \ 1215 } 1216 1217 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1218 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1219 #endif 1220 1221 /* mulhw mulhw. */ 1222 static void gen_mulhw(DisasContext *ctx) 1223 { 1224 TCGv_i32 t0 = tcg_temp_new_i32(); 1225 TCGv_i32 t1 = tcg_temp_new_i32(); 1226 1227 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1228 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1229 tcg_gen_muls2_i32(t0, t1, t0, t1); 1230 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1231 tcg_temp_free_i32(t0); 1232 tcg_temp_free_i32(t1); 1233 if (unlikely(Rc(ctx->opcode) != 0)) { 1234 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1235 } 1236 } 1237 1238 /* mulhwu mulhwu. */ 1239 static void gen_mulhwu(DisasContext *ctx) 1240 { 1241 TCGv_i32 t0 = tcg_temp_new_i32(); 1242 TCGv_i32 t1 = tcg_temp_new_i32(); 1243 1244 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1245 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1246 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1247 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1248 tcg_temp_free_i32(t0); 1249 tcg_temp_free_i32(t1); 1250 if (unlikely(Rc(ctx->opcode) != 0)) { 1251 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1252 } 1253 } 1254 1255 /* mullw mullw. */ 1256 static void gen_mullw(DisasContext *ctx) 1257 { 1258 #if defined(TARGET_PPC64) 1259 TCGv_i64 t0, t1; 1260 t0 = tcg_temp_new_i64(); 1261 t1 = tcg_temp_new_i64(); 1262 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1263 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1264 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1265 tcg_temp_free(t0); 1266 tcg_temp_free(t1); 1267 #else 1268 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1269 cpu_gpr[rB(ctx->opcode)]); 1270 #endif 1271 if (unlikely(Rc(ctx->opcode) != 0)) { 1272 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1273 } 1274 } 1275 1276 /* mullwo mullwo. */ 1277 static void gen_mullwo(DisasContext *ctx) 1278 { 1279 TCGv_i32 t0 = tcg_temp_new_i32(); 1280 TCGv_i32 t1 = tcg_temp_new_i32(); 1281 1282 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1283 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1284 tcg_gen_muls2_i32(t0, t1, t0, t1); 1285 #if defined(TARGET_PPC64) 1286 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1287 #else 1288 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1289 #endif 1290 1291 tcg_gen_sari_i32(t0, t0, 31); 1292 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1293 tcg_gen_extu_i32_tl(cpu_ov, t0); 1294 if (is_isa300(ctx)) { 1295 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1296 } 1297 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1298 1299 tcg_temp_free_i32(t0); 1300 tcg_temp_free_i32(t1); 1301 if (unlikely(Rc(ctx->opcode) != 0)) { 1302 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1303 } 1304 } 1305 1306 /* mulli */ 1307 static void gen_mulli(DisasContext *ctx) 1308 { 1309 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1310 SIMM(ctx->opcode)); 1311 } 1312 1313 #if defined(TARGET_PPC64) 1314 /* mulhd mulhd. */ 1315 static void gen_mulhd(DisasContext *ctx) 1316 { 1317 TCGv lo = tcg_temp_new(); 1318 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1319 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1320 tcg_temp_free(lo); 1321 if (unlikely(Rc(ctx->opcode) != 0)) { 1322 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1323 } 1324 } 1325 1326 /* mulhdu mulhdu. */ 1327 static void gen_mulhdu(DisasContext *ctx) 1328 { 1329 TCGv lo = tcg_temp_new(); 1330 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1331 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1332 tcg_temp_free(lo); 1333 if (unlikely(Rc(ctx->opcode) != 0)) { 1334 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1335 } 1336 } 1337 1338 /* mulld mulld. */ 1339 static void gen_mulld(DisasContext *ctx) 1340 { 1341 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1342 cpu_gpr[rB(ctx->opcode)]); 1343 if (unlikely(Rc(ctx->opcode) != 0)) { 1344 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1345 } 1346 } 1347 1348 /* mulldo mulldo. */ 1349 static void gen_mulldo(DisasContext *ctx) 1350 { 1351 TCGv_i64 t0 = tcg_temp_new_i64(); 1352 TCGv_i64 t1 = tcg_temp_new_i64(); 1353 1354 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1355 cpu_gpr[rB(ctx->opcode)]); 1356 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1357 1358 tcg_gen_sari_i64(t0, t0, 63); 1359 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 1360 if (is_isa300(ctx)) { 1361 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1362 } 1363 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1364 1365 tcg_temp_free_i64(t0); 1366 tcg_temp_free_i64(t1); 1367 1368 if (unlikely(Rc(ctx->opcode) != 0)) { 1369 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1370 } 1371 } 1372 #endif 1373 1374 /* Common subf function */ 1375 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1376 TCGv arg2, bool add_ca, bool compute_ca, 1377 bool compute_ov, bool compute_rc0) 1378 { 1379 TCGv t0 = ret; 1380 1381 if (compute_ca || compute_ov) { 1382 t0 = tcg_temp_new(); 1383 } 1384 1385 if (compute_ca) { 1386 /* dest = ~arg1 + arg2 [+ ca]. */ 1387 if (NARROW_MODE(ctx)) { 1388 /* 1389 * Caution: a non-obvious corner case of the spec is that 1390 * we must produce the *entire* 64-bit addition, but 1391 * produce the carry into bit 32. 1392 */ 1393 TCGv inv1 = tcg_temp_new(); 1394 TCGv t1 = tcg_temp_new(); 1395 tcg_gen_not_tl(inv1, arg1); 1396 if (add_ca) { 1397 tcg_gen_add_tl(t0, arg2, cpu_ca); 1398 } else { 1399 tcg_gen_addi_tl(t0, arg2, 1); 1400 } 1401 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1402 tcg_gen_add_tl(t0, t0, inv1); 1403 tcg_temp_free(inv1); 1404 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1405 tcg_temp_free(t1); 1406 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 1407 if (is_isa300(ctx)) { 1408 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 1409 } 1410 } else if (add_ca) { 1411 TCGv zero, inv1 = tcg_temp_new(); 1412 tcg_gen_not_tl(inv1, arg1); 1413 zero = tcg_const_tl(0); 1414 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1415 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 1416 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 1417 tcg_temp_free(zero); 1418 tcg_temp_free(inv1); 1419 } else { 1420 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1421 tcg_gen_sub_tl(t0, arg2, arg1); 1422 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 1423 } 1424 } else if (add_ca) { 1425 /* 1426 * Since we're ignoring carry-out, we can simplify the 1427 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 1428 */ 1429 tcg_gen_sub_tl(t0, arg2, arg1); 1430 tcg_gen_add_tl(t0, t0, cpu_ca); 1431 tcg_gen_subi_tl(t0, t0, 1); 1432 } else { 1433 tcg_gen_sub_tl(t0, arg2, arg1); 1434 } 1435 1436 if (compute_ov) { 1437 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1438 } 1439 if (unlikely(compute_rc0)) { 1440 gen_set_Rc0(ctx, t0); 1441 } 1442 1443 if (t0 != ret) { 1444 tcg_gen_mov_tl(ret, t0); 1445 tcg_temp_free(t0); 1446 } 1447 } 1448 /* Sub functions with Two operands functions */ 1449 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1450 static void glue(gen_, name)(DisasContext *ctx) \ 1451 { \ 1452 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1453 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1454 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1455 } 1456 /* Sub functions with one operand and one immediate */ 1457 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1458 add_ca, compute_ca, compute_ov) \ 1459 static void glue(gen_, name)(DisasContext *ctx) \ 1460 { \ 1461 TCGv t0 = tcg_const_tl(const_val); \ 1462 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1463 cpu_gpr[rA(ctx->opcode)], t0, \ 1464 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1465 tcg_temp_free(t0); \ 1466 } 1467 /* subf subf. subfo subfo. */ 1468 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1469 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1470 /* subfc subfc. subfco subfco. */ 1471 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1472 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1473 /* subfe subfe. subfeo subfo. */ 1474 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1475 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1476 /* subfme subfme. subfmeo subfmeo. */ 1477 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1478 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1479 /* subfze subfze. subfzeo subfzeo.*/ 1480 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1481 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1482 1483 /* subfic */ 1484 static void gen_subfic(DisasContext *ctx) 1485 { 1486 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1487 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1488 c, 0, 1, 0, 0); 1489 tcg_temp_free(c); 1490 } 1491 1492 /* neg neg. nego nego. */ 1493 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1494 { 1495 TCGv zero = tcg_const_tl(0); 1496 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1497 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1498 tcg_temp_free(zero); 1499 } 1500 1501 static void gen_neg(DisasContext *ctx) 1502 { 1503 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 1504 if (unlikely(Rc(ctx->opcode))) { 1505 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1506 } 1507 } 1508 1509 static void gen_nego(DisasContext *ctx) 1510 { 1511 gen_op_arith_neg(ctx, 1); 1512 } 1513 1514 /*** Integer logical ***/ 1515 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1516 static void glue(gen_, name)(DisasContext *ctx) \ 1517 { \ 1518 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1519 cpu_gpr[rB(ctx->opcode)]); \ 1520 if (unlikely(Rc(ctx->opcode) != 0)) \ 1521 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1522 } 1523 1524 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1525 static void glue(gen_, name)(DisasContext *ctx) \ 1526 { \ 1527 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1528 if (unlikely(Rc(ctx->opcode) != 0)) \ 1529 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1530 } 1531 1532 /* and & and. */ 1533 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1534 /* andc & andc. */ 1535 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1536 1537 /* andi. */ 1538 static void gen_andi_(DisasContext *ctx) 1539 { 1540 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1541 UIMM(ctx->opcode)); 1542 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1543 } 1544 1545 /* andis. */ 1546 static void gen_andis_(DisasContext *ctx) 1547 { 1548 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1549 UIMM(ctx->opcode) << 16); 1550 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1551 } 1552 1553 /* cntlzw */ 1554 static void gen_cntlzw(DisasContext *ctx) 1555 { 1556 TCGv_i32 t = tcg_temp_new_i32(); 1557 1558 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1559 tcg_gen_clzi_i32(t, t, 32); 1560 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1561 tcg_temp_free_i32(t); 1562 1563 if (unlikely(Rc(ctx->opcode) != 0)) { 1564 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1565 } 1566 } 1567 1568 /* cnttzw */ 1569 static void gen_cnttzw(DisasContext *ctx) 1570 { 1571 TCGv_i32 t = tcg_temp_new_i32(); 1572 1573 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1574 tcg_gen_ctzi_i32(t, t, 32); 1575 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1576 tcg_temp_free_i32(t); 1577 1578 if (unlikely(Rc(ctx->opcode) != 0)) { 1579 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1580 } 1581 } 1582 1583 /* eqv & eqv. */ 1584 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1585 /* extsb & extsb. */ 1586 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1587 /* extsh & extsh. */ 1588 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1589 /* nand & nand. */ 1590 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1591 /* nor & nor. */ 1592 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1593 1594 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1595 static void gen_pause(DisasContext *ctx) 1596 { 1597 TCGv_i32 t0 = tcg_const_i32(0); 1598 tcg_gen_st_i32(t0, cpu_env, 1599 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1600 tcg_temp_free_i32(t0); 1601 1602 /* Stop translation, this gives other CPUs a chance to run */ 1603 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1604 } 1605 #endif /* defined(TARGET_PPC64) */ 1606 1607 /* or & or. */ 1608 static void gen_or(DisasContext *ctx) 1609 { 1610 int rs, ra, rb; 1611 1612 rs = rS(ctx->opcode); 1613 ra = rA(ctx->opcode); 1614 rb = rB(ctx->opcode); 1615 /* Optimisation for mr. ri case */ 1616 if (rs != ra || rs != rb) { 1617 if (rs != rb) { 1618 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1619 } else { 1620 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1621 } 1622 if (unlikely(Rc(ctx->opcode) != 0)) { 1623 gen_set_Rc0(ctx, cpu_gpr[ra]); 1624 } 1625 } else if (unlikely(Rc(ctx->opcode) != 0)) { 1626 gen_set_Rc0(ctx, cpu_gpr[rs]); 1627 #if defined(TARGET_PPC64) 1628 } else if (rs != 0) { /* 0 is nop */ 1629 int prio = 0; 1630 1631 switch (rs) { 1632 case 1: 1633 /* Set process priority to low */ 1634 prio = 2; 1635 break; 1636 case 6: 1637 /* Set process priority to medium-low */ 1638 prio = 3; 1639 break; 1640 case 2: 1641 /* Set process priority to normal */ 1642 prio = 4; 1643 break; 1644 #if !defined(CONFIG_USER_ONLY) 1645 case 31: 1646 if (!ctx->pr) { 1647 /* Set process priority to very low */ 1648 prio = 1; 1649 } 1650 break; 1651 case 5: 1652 if (!ctx->pr) { 1653 /* Set process priority to medium-hight */ 1654 prio = 5; 1655 } 1656 break; 1657 case 3: 1658 if (!ctx->pr) { 1659 /* Set process priority to high */ 1660 prio = 6; 1661 } 1662 break; 1663 case 7: 1664 if (ctx->hv && !ctx->pr) { 1665 /* Set process priority to very high */ 1666 prio = 7; 1667 } 1668 break; 1669 #endif 1670 default: 1671 break; 1672 } 1673 if (prio) { 1674 TCGv t0 = tcg_temp_new(); 1675 gen_load_spr(t0, SPR_PPR); 1676 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1677 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1678 gen_store_spr(SPR_PPR, t0); 1679 tcg_temp_free(t0); 1680 } 1681 #if !defined(CONFIG_USER_ONLY) 1682 /* 1683 * Pause out of TCG otherwise spin loops with smt_low eat too 1684 * much CPU and the kernel hangs. This applies to all 1685 * encodings other than no-op, e.g., miso(rs=26), yield(27), 1686 * mdoio(29), mdoom(30), and all currently undefined. 1687 */ 1688 gen_pause(ctx); 1689 #endif 1690 #endif 1691 } 1692 } 1693 /* orc & orc. */ 1694 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1695 1696 /* xor & xor. */ 1697 static void gen_xor(DisasContext *ctx) 1698 { 1699 /* Optimisation for "set to zero" case */ 1700 if (rS(ctx->opcode) != rB(ctx->opcode)) { 1701 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1702 cpu_gpr[rB(ctx->opcode)]); 1703 } else { 1704 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1705 } 1706 if (unlikely(Rc(ctx->opcode) != 0)) { 1707 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1708 } 1709 } 1710 1711 /* ori */ 1712 static void gen_ori(DisasContext *ctx) 1713 { 1714 target_ulong uimm = UIMM(ctx->opcode); 1715 1716 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1717 return; 1718 } 1719 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1720 } 1721 1722 /* oris */ 1723 static void gen_oris(DisasContext *ctx) 1724 { 1725 target_ulong uimm = UIMM(ctx->opcode); 1726 1727 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1728 /* NOP */ 1729 return; 1730 } 1731 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1732 uimm << 16); 1733 } 1734 1735 /* xori */ 1736 static void gen_xori(DisasContext *ctx) 1737 { 1738 target_ulong uimm = UIMM(ctx->opcode); 1739 1740 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1741 /* NOP */ 1742 return; 1743 } 1744 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1745 } 1746 1747 /* xoris */ 1748 static void gen_xoris(DisasContext *ctx) 1749 { 1750 target_ulong uimm = UIMM(ctx->opcode); 1751 1752 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1753 /* NOP */ 1754 return; 1755 } 1756 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1757 uimm << 16); 1758 } 1759 1760 /* popcntb : PowerPC 2.03 specification */ 1761 static void gen_popcntb(DisasContext *ctx) 1762 { 1763 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1764 } 1765 1766 static void gen_popcntw(DisasContext *ctx) 1767 { 1768 #if defined(TARGET_PPC64) 1769 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1770 #else 1771 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1772 #endif 1773 } 1774 1775 #if defined(TARGET_PPC64) 1776 /* popcntd: PowerPC 2.06 specification */ 1777 static void gen_popcntd(DisasContext *ctx) 1778 { 1779 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1780 } 1781 #endif 1782 1783 /* prtyw: PowerPC 2.05 specification */ 1784 static void gen_prtyw(DisasContext *ctx) 1785 { 1786 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1787 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1788 TCGv t0 = tcg_temp_new(); 1789 tcg_gen_shri_tl(t0, rs, 16); 1790 tcg_gen_xor_tl(ra, rs, t0); 1791 tcg_gen_shri_tl(t0, ra, 8); 1792 tcg_gen_xor_tl(ra, ra, t0); 1793 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1794 tcg_temp_free(t0); 1795 } 1796 1797 #if defined(TARGET_PPC64) 1798 /* prtyd: PowerPC 2.05 specification */ 1799 static void gen_prtyd(DisasContext *ctx) 1800 { 1801 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1802 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1803 TCGv t0 = tcg_temp_new(); 1804 tcg_gen_shri_tl(t0, rs, 32); 1805 tcg_gen_xor_tl(ra, rs, t0); 1806 tcg_gen_shri_tl(t0, ra, 16); 1807 tcg_gen_xor_tl(ra, ra, t0); 1808 tcg_gen_shri_tl(t0, ra, 8); 1809 tcg_gen_xor_tl(ra, ra, t0); 1810 tcg_gen_andi_tl(ra, ra, 1); 1811 tcg_temp_free(t0); 1812 } 1813 #endif 1814 1815 #if defined(TARGET_PPC64) 1816 /* bpermd */ 1817 static void gen_bpermd(DisasContext *ctx) 1818 { 1819 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1820 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1821 } 1822 #endif 1823 1824 #if defined(TARGET_PPC64) 1825 /* extsw & extsw. */ 1826 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1827 1828 /* cntlzd */ 1829 static void gen_cntlzd(DisasContext *ctx) 1830 { 1831 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1832 if (unlikely(Rc(ctx->opcode) != 0)) { 1833 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1834 } 1835 } 1836 1837 /* cnttzd */ 1838 static void gen_cnttzd(DisasContext *ctx) 1839 { 1840 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1841 if (unlikely(Rc(ctx->opcode) != 0)) { 1842 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1843 } 1844 } 1845 1846 /* darn */ 1847 static void gen_darn(DisasContext *ctx) 1848 { 1849 int l = L(ctx->opcode); 1850 1851 if (l > 2) { 1852 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1853 } else { 1854 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 1855 gen_io_start(); 1856 } 1857 if (l == 0) { 1858 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1859 } else { 1860 /* Return 64-bit random for both CRN and RRN */ 1861 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1862 } 1863 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 1864 gen_stop_exception(ctx); 1865 } 1866 } 1867 } 1868 #endif 1869 1870 /*** Integer rotate ***/ 1871 1872 /* rlwimi & rlwimi. */ 1873 static void gen_rlwimi(DisasContext *ctx) 1874 { 1875 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1876 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1877 uint32_t sh = SH(ctx->opcode); 1878 uint32_t mb = MB(ctx->opcode); 1879 uint32_t me = ME(ctx->opcode); 1880 1881 if (sh == (31 - me) && mb <= me) { 1882 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1883 } else { 1884 target_ulong mask; 1885 TCGv t1; 1886 1887 #if defined(TARGET_PPC64) 1888 mb += 32; 1889 me += 32; 1890 #endif 1891 mask = MASK(mb, me); 1892 1893 t1 = tcg_temp_new(); 1894 if (mask <= 0xffffffffu) { 1895 TCGv_i32 t0 = tcg_temp_new_i32(); 1896 tcg_gen_trunc_tl_i32(t0, t_rs); 1897 tcg_gen_rotli_i32(t0, t0, sh); 1898 tcg_gen_extu_i32_tl(t1, t0); 1899 tcg_temp_free_i32(t0); 1900 } else { 1901 #if defined(TARGET_PPC64) 1902 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1903 tcg_gen_rotli_i64(t1, t1, sh); 1904 #else 1905 g_assert_not_reached(); 1906 #endif 1907 } 1908 1909 tcg_gen_andi_tl(t1, t1, mask); 1910 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1911 tcg_gen_or_tl(t_ra, t_ra, t1); 1912 tcg_temp_free(t1); 1913 } 1914 if (unlikely(Rc(ctx->opcode) != 0)) { 1915 gen_set_Rc0(ctx, t_ra); 1916 } 1917 } 1918 1919 /* rlwinm & rlwinm. */ 1920 static void gen_rlwinm(DisasContext *ctx) 1921 { 1922 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1923 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1924 int sh = SH(ctx->opcode); 1925 int mb = MB(ctx->opcode); 1926 int me = ME(ctx->opcode); 1927 int len = me - mb + 1; 1928 int rsh = (32 - sh) & 31; 1929 1930 if (sh != 0 && len > 0 && me == (31 - sh)) { 1931 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 1932 } else if (me == 31 && rsh + len <= 32) { 1933 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1934 } else { 1935 target_ulong mask; 1936 #if defined(TARGET_PPC64) 1937 mb += 32; 1938 me += 32; 1939 #endif 1940 mask = MASK(mb, me); 1941 if (mask <= 0xffffffffu) { 1942 if (sh == 0) { 1943 tcg_gen_andi_tl(t_ra, t_rs, mask); 1944 } else { 1945 TCGv_i32 t0 = tcg_temp_new_i32(); 1946 tcg_gen_trunc_tl_i32(t0, t_rs); 1947 tcg_gen_rotli_i32(t0, t0, sh); 1948 tcg_gen_andi_i32(t0, t0, mask); 1949 tcg_gen_extu_i32_tl(t_ra, t0); 1950 tcg_temp_free_i32(t0); 1951 } 1952 } else { 1953 #if defined(TARGET_PPC64) 1954 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1955 tcg_gen_rotli_i64(t_ra, t_ra, sh); 1956 tcg_gen_andi_i64(t_ra, t_ra, mask); 1957 #else 1958 g_assert_not_reached(); 1959 #endif 1960 } 1961 } 1962 if (unlikely(Rc(ctx->opcode) != 0)) { 1963 gen_set_Rc0(ctx, t_ra); 1964 } 1965 } 1966 1967 /* rlwnm & rlwnm. */ 1968 static void gen_rlwnm(DisasContext *ctx) 1969 { 1970 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1971 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1972 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1973 uint32_t mb = MB(ctx->opcode); 1974 uint32_t me = ME(ctx->opcode); 1975 target_ulong mask; 1976 1977 #if defined(TARGET_PPC64) 1978 mb += 32; 1979 me += 32; 1980 #endif 1981 mask = MASK(mb, me); 1982 1983 if (mask <= 0xffffffffu) { 1984 TCGv_i32 t0 = tcg_temp_new_i32(); 1985 TCGv_i32 t1 = tcg_temp_new_i32(); 1986 tcg_gen_trunc_tl_i32(t0, t_rb); 1987 tcg_gen_trunc_tl_i32(t1, t_rs); 1988 tcg_gen_andi_i32(t0, t0, 0x1f); 1989 tcg_gen_rotl_i32(t1, t1, t0); 1990 tcg_gen_extu_i32_tl(t_ra, t1); 1991 tcg_temp_free_i32(t0); 1992 tcg_temp_free_i32(t1); 1993 } else { 1994 #if defined(TARGET_PPC64) 1995 TCGv_i64 t0 = tcg_temp_new_i64(); 1996 tcg_gen_andi_i64(t0, t_rb, 0x1f); 1997 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1998 tcg_gen_rotl_i64(t_ra, t_ra, t0); 1999 tcg_temp_free_i64(t0); 2000 #else 2001 g_assert_not_reached(); 2002 #endif 2003 } 2004 2005 tcg_gen_andi_tl(t_ra, t_ra, mask); 2006 2007 if (unlikely(Rc(ctx->opcode) != 0)) { 2008 gen_set_Rc0(ctx, t_ra); 2009 } 2010 } 2011 2012 #if defined(TARGET_PPC64) 2013 #define GEN_PPC64_R2(name, opc1, opc2) \ 2014 static void glue(gen_, name##0)(DisasContext *ctx) \ 2015 { \ 2016 gen_##name(ctx, 0); \ 2017 } \ 2018 \ 2019 static void glue(gen_, name##1)(DisasContext *ctx) \ 2020 { \ 2021 gen_##name(ctx, 1); \ 2022 } 2023 #define GEN_PPC64_R4(name, opc1, opc2) \ 2024 static void glue(gen_, name##0)(DisasContext *ctx) \ 2025 { \ 2026 gen_##name(ctx, 0, 0); \ 2027 } \ 2028 \ 2029 static void glue(gen_, name##1)(DisasContext *ctx) \ 2030 { \ 2031 gen_##name(ctx, 0, 1); \ 2032 } \ 2033 \ 2034 static void glue(gen_, name##2)(DisasContext *ctx) \ 2035 { \ 2036 gen_##name(ctx, 1, 0); \ 2037 } \ 2038 \ 2039 static void glue(gen_, name##3)(DisasContext *ctx) \ 2040 { \ 2041 gen_##name(ctx, 1, 1); \ 2042 } 2043 2044 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2045 { 2046 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2047 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2048 int len = me - mb + 1; 2049 int rsh = (64 - sh) & 63; 2050 2051 if (sh != 0 && len > 0 && me == (63 - sh)) { 2052 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2053 } else if (me == 63 && rsh + len <= 64) { 2054 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2055 } else { 2056 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2057 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2058 } 2059 if (unlikely(Rc(ctx->opcode) != 0)) { 2060 gen_set_Rc0(ctx, t_ra); 2061 } 2062 } 2063 2064 /* rldicl - rldicl. */ 2065 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2066 { 2067 uint32_t sh, mb; 2068 2069 sh = SH(ctx->opcode) | (shn << 5); 2070 mb = MB(ctx->opcode) | (mbn << 5); 2071 gen_rldinm(ctx, mb, 63, sh); 2072 } 2073 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2074 2075 /* rldicr - rldicr. */ 2076 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2077 { 2078 uint32_t sh, me; 2079 2080 sh = SH(ctx->opcode) | (shn << 5); 2081 me = MB(ctx->opcode) | (men << 5); 2082 gen_rldinm(ctx, 0, me, sh); 2083 } 2084 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2085 2086 /* rldic - rldic. */ 2087 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2088 { 2089 uint32_t sh, mb; 2090 2091 sh = SH(ctx->opcode) | (shn << 5); 2092 mb = MB(ctx->opcode) | (mbn << 5); 2093 gen_rldinm(ctx, mb, 63 - sh, sh); 2094 } 2095 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2096 2097 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2098 { 2099 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2100 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2101 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2102 TCGv t0; 2103 2104 t0 = tcg_temp_new(); 2105 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2106 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2107 tcg_temp_free(t0); 2108 2109 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2110 if (unlikely(Rc(ctx->opcode) != 0)) { 2111 gen_set_Rc0(ctx, t_ra); 2112 } 2113 } 2114 2115 /* rldcl - rldcl. */ 2116 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2117 { 2118 uint32_t mb; 2119 2120 mb = MB(ctx->opcode) | (mbn << 5); 2121 gen_rldnm(ctx, mb, 63); 2122 } 2123 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2124 2125 /* rldcr - rldcr. */ 2126 static inline void gen_rldcr(DisasContext *ctx, int men) 2127 { 2128 uint32_t me; 2129 2130 me = MB(ctx->opcode) | (men << 5); 2131 gen_rldnm(ctx, 0, me); 2132 } 2133 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2134 2135 /* rldimi - rldimi. */ 2136 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2137 { 2138 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2139 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2140 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2141 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2142 uint32_t me = 63 - sh; 2143 2144 if (mb <= me) { 2145 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2146 } else { 2147 target_ulong mask = MASK(mb, me); 2148 TCGv t1 = tcg_temp_new(); 2149 2150 tcg_gen_rotli_tl(t1, t_rs, sh); 2151 tcg_gen_andi_tl(t1, t1, mask); 2152 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2153 tcg_gen_or_tl(t_ra, t_ra, t1); 2154 tcg_temp_free(t1); 2155 } 2156 if (unlikely(Rc(ctx->opcode) != 0)) { 2157 gen_set_Rc0(ctx, t_ra); 2158 } 2159 } 2160 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2161 #endif 2162 2163 /*** Integer shift ***/ 2164 2165 /* slw & slw. */ 2166 static void gen_slw(DisasContext *ctx) 2167 { 2168 TCGv t0, t1; 2169 2170 t0 = tcg_temp_new(); 2171 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2172 #if defined(TARGET_PPC64) 2173 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2174 tcg_gen_sari_tl(t0, t0, 0x3f); 2175 #else 2176 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2177 tcg_gen_sari_tl(t0, t0, 0x1f); 2178 #endif 2179 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2180 t1 = tcg_temp_new(); 2181 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2182 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2183 tcg_temp_free(t1); 2184 tcg_temp_free(t0); 2185 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2186 if (unlikely(Rc(ctx->opcode) != 0)) { 2187 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2188 } 2189 } 2190 2191 /* sraw & sraw. */ 2192 static void gen_sraw(DisasContext *ctx) 2193 { 2194 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2195 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2196 if (unlikely(Rc(ctx->opcode) != 0)) { 2197 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2198 } 2199 } 2200 2201 /* srawi & srawi. */ 2202 static void gen_srawi(DisasContext *ctx) 2203 { 2204 int sh = SH(ctx->opcode); 2205 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2206 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2207 if (sh == 0) { 2208 tcg_gen_ext32s_tl(dst, src); 2209 tcg_gen_movi_tl(cpu_ca, 0); 2210 if (is_isa300(ctx)) { 2211 tcg_gen_movi_tl(cpu_ca32, 0); 2212 } 2213 } else { 2214 TCGv t0; 2215 tcg_gen_ext32s_tl(dst, src); 2216 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2217 t0 = tcg_temp_new(); 2218 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2219 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2220 tcg_temp_free(t0); 2221 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2222 if (is_isa300(ctx)) { 2223 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2224 } 2225 tcg_gen_sari_tl(dst, dst, sh); 2226 } 2227 if (unlikely(Rc(ctx->opcode) != 0)) { 2228 gen_set_Rc0(ctx, dst); 2229 } 2230 } 2231 2232 /* srw & srw. */ 2233 static void gen_srw(DisasContext *ctx) 2234 { 2235 TCGv t0, t1; 2236 2237 t0 = tcg_temp_new(); 2238 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2239 #if defined(TARGET_PPC64) 2240 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2241 tcg_gen_sari_tl(t0, t0, 0x3f); 2242 #else 2243 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2244 tcg_gen_sari_tl(t0, t0, 0x1f); 2245 #endif 2246 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2247 tcg_gen_ext32u_tl(t0, t0); 2248 t1 = tcg_temp_new(); 2249 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2250 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2251 tcg_temp_free(t1); 2252 tcg_temp_free(t0); 2253 if (unlikely(Rc(ctx->opcode) != 0)) { 2254 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2255 } 2256 } 2257 2258 #if defined(TARGET_PPC64) 2259 /* sld & sld. */ 2260 static void gen_sld(DisasContext *ctx) 2261 { 2262 TCGv t0, t1; 2263 2264 t0 = tcg_temp_new(); 2265 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2266 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2267 tcg_gen_sari_tl(t0, t0, 0x3f); 2268 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2269 t1 = tcg_temp_new(); 2270 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2271 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2272 tcg_temp_free(t1); 2273 tcg_temp_free(t0); 2274 if (unlikely(Rc(ctx->opcode) != 0)) { 2275 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2276 } 2277 } 2278 2279 /* srad & srad. */ 2280 static void gen_srad(DisasContext *ctx) 2281 { 2282 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2283 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2284 if (unlikely(Rc(ctx->opcode) != 0)) { 2285 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2286 } 2287 } 2288 /* sradi & sradi. */ 2289 static inline void gen_sradi(DisasContext *ctx, int n) 2290 { 2291 int sh = SH(ctx->opcode) + (n << 5); 2292 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2293 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2294 if (sh == 0) { 2295 tcg_gen_mov_tl(dst, src); 2296 tcg_gen_movi_tl(cpu_ca, 0); 2297 if (is_isa300(ctx)) { 2298 tcg_gen_movi_tl(cpu_ca32, 0); 2299 } 2300 } else { 2301 TCGv t0; 2302 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2303 t0 = tcg_temp_new(); 2304 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2305 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2306 tcg_temp_free(t0); 2307 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2308 if (is_isa300(ctx)) { 2309 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2310 } 2311 tcg_gen_sari_tl(dst, src, sh); 2312 } 2313 if (unlikely(Rc(ctx->opcode) != 0)) { 2314 gen_set_Rc0(ctx, dst); 2315 } 2316 } 2317 2318 static void gen_sradi0(DisasContext *ctx) 2319 { 2320 gen_sradi(ctx, 0); 2321 } 2322 2323 static void gen_sradi1(DisasContext *ctx) 2324 { 2325 gen_sradi(ctx, 1); 2326 } 2327 2328 /* extswsli & extswsli. */ 2329 static inline void gen_extswsli(DisasContext *ctx, int n) 2330 { 2331 int sh = SH(ctx->opcode) + (n << 5); 2332 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2333 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2334 2335 tcg_gen_ext32s_tl(dst, src); 2336 tcg_gen_shli_tl(dst, dst, sh); 2337 if (unlikely(Rc(ctx->opcode) != 0)) { 2338 gen_set_Rc0(ctx, dst); 2339 } 2340 } 2341 2342 static void gen_extswsli0(DisasContext *ctx) 2343 { 2344 gen_extswsli(ctx, 0); 2345 } 2346 2347 static void gen_extswsli1(DisasContext *ctx) 2348 { 2349 gen_extswsli(ctx, 1); 2350 } 2351 2352 /* srd & srd. */ 2353 static void gen_srd(DisasContext *ctx) 2354 { 2355 TCGv t0, t1; 2356 2357 t0 = tcg_temp_new(); 2358 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2359 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2360 tcg_gen_sari_tl(t0, t0, 0x3f); 2361 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2362 t1 = tcg_temp_new(); 2363 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2364 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2365 tcg_temp_free(t1); 2366 tcg_temp_free(t0); 2367 if (unlikely(Rc(ctx->opcode) != 0)) { 2368 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2369 } 2370 } 2371 #endif 2372 2373 /*** Addressing modes ***/ 2374 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2375 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2376 target_long maskl) 2377 { 2378 target_long simm = SIMM(ctx->opcode); 2379 2380 simm &= ~maskl; 2381 if (rA(ctx->opcode) == 0) { 2382 if (NARROW_MODE(ctx)) { 2383 simm = (uint32_t)simm; 2384 } 2385 tcg_gen_movi_tl(EA, simm); 2386 } else if (likely(simm != 0)) { 2387 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2388 if (NARROW_MODE(ctx)) { 2389 tcg_gen_ext32u_tl(EA, EA); 2390 } 2391 } else { 2392 if (NARROW_MODE(ctx)) { 2393 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2394 } else { 2395 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2396 } 2397 } 2398 } 2399 2400 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2401 { 2402 if (rA(ctx->opcode) == 0) { 2403 if (NARROW_MODE(ctx)) { 2404 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2405 } else { 2406 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2407 } 2408 } else { 2409 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2410 if (NARROW_MODE(ctx)) { 2411 tcg_gen_ext32u_tl(EA, EA); 2412 } 2413 } 2414 } 2415 2416 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2417 { 2418 if (rA(ctx->opcode) == 0) { 2419 tcg_gen_movi_tl(EA, 0); 2420 } else if (NARROW_MODE(ctx)) { 2421 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2422 } else { 2423 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2424 } 2425 } 2426 2427 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2428 target_long val) 2429 { 2430 tcg_gen_addi_tl(ret, arg1, val); 2431 if (NARROW_MODE(ctx)) { 2432 tcg_gen_ext32u_tl(ret, ret); 2433 } 2434 } 2435 2436 static inline void gen_align_no_le(DisasContext *ctx) 2437 { 2438 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2439 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2440 } 2441 2442 /*** Integer load ***/ 2443 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2444 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2445 2446 #define GEN_QEMU_LOAD_TL(ldop, op) \ 2447 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2448 TCGv val, \ 2449 TCGv addr) \ 2450 { \ 2451 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2452 } 2453 2454 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2455 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2456 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2457 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2458 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2459 2460 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2461 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2462 2463 #define GEN_QEMU_LOAD_64(ldop, op) \ 2464 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2465 TCGv_i64 val, \ 2466 TCGv addr) \ 2467 { \ 2468 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2469 } 2470 2471 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2472 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2473 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2474 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2475 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2476 2477 #if defined(TARGET_PPC64) 2478 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2479 #endif 2480 2481 #define GEN_QEMU_STORE_TL(stop, op) \ 2482 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2483 TCGv val, \ 2484 TCGv addr) \ 2485 { \ 2486 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2487 } 2488 2489 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2490 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2491 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2492 2493 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2494 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2495 2496 #define GEN_QEMU_STORE_64(stop, op) \ 2497 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2498 TCGv_i64 val, \ 2499 TCGv addr) \ 2500 { \ 2501 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2502 } 2503 2504 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2505 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2506 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2507 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2508 2509 #if defined(TARGET_PPC64) 2510 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2511 #endif 2512 2513 #define GEN_LD(name, ldop, opc, type) \ 2514 static void glue(gen_, name)(DisasContext *ctx) \ 2515 { \ 2516 TCGv EA; \ 2517 gen_set_access_type(ctx, ACCESS_INT); \ 2518 EA = tcg_temp_new(); \ 2519 gen_addr_imm_index(ctx, EA, 0); \ 2520 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2521 tcg_temp_free(EA); \ 2522 } 2523 2524 #define GEN_LDU(name, ldop, opc, type) \ 2525 static void glue(gen_, name##u)(DisasContext *ctx) \ 2526 { \ 2527 TCGv EA; \ 2528 if (unlikely(rA(ctx->opcode) == 0 || \ 2529 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2530 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2531 return; \ 2532 } \ 2533 gen_set_access_type(ctx, ACCESS_INT); \ 2534 EA = tcg_temp_new(); \ 2535 if (type == PPC_64B) \ 2536 gen_addr_imm_index(ctx, EA, 0x03); \ 2537 else \ 2538 gen_addr_imm_index(ctx, EA, 0); \ 2539 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2540 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2541 tcg_temp_free(EA); \ 2542 } 2543 2544 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2545 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2546 { \ 2547 TCGv EA; \ 2548 if (unlikely(rA(ctx->opcode) == 0 || \ 2549 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2550 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2551 return; \ 2552 } \ 2553 gen_set_access_type(ctx, ACCESS_INT); \ 2554 EA = tcg_temp_new(); \ 2555 gen_addr_reg_index(ctx, EA); \ 2556 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2557 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2558 tcg_temp_free(EA); \ 2559 } 2560 2561 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2562 static void glue(gen_, name##x)(DisasContext *ctx) \ 2563 { \ 2564 TCGv EA; \ 2565 chk; \ 2566 gen_set_access_type(ctx, ACCESS_INT); \ 2567 EA = tcg_temp_new(); \ 2568 gen_addr_reg_index(ctx, EA); \ 2569 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2570 tcg_temp_free(EA); \ 2571 } 2572 2573 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2574 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2575 2576 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2577 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2578 2579 #define GEN_LDS(name, ldop, op, type) \ 2580 GEN_LD(name, ldop, op | 0x20, type); \ 2581 GEN_LDU(name, ldop, op | 0x21, type); \ 2582 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2583 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2584 2585 /* lbz lbzu lbzux lbzx */ 2586 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2587 /* lha lhau lhaux lhax */ 2588 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2589 /* lhz lhzu lhzux lhzx */ 2590 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2591 /* lwz lwzu lwzux lwzx */ 2592 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2593 2594 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 2595 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2596 { \ 2597 TCGv EA; \ 2598 CHK_SV; \ 2599 gen_set_access_type(ctx, ACCESS_INT); \ 2600 EA = tcg_temp_new(); \ 2601 gen_addr_reg_index(ctx, EA); \ 2602 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 2603 tcg_temp_free(EA); \ 2604 } 2605 2606 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 2607 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 2608 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 2609 #if defined(TARGET_PPC64) 2610 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 2611 #endif 2612 2613 #if defined(TARGET_PPC64) 2614 /* lwaux */ 2615 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2616 /* lwax */ 2617 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2618 /* ldux */ 2619 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2620 /* ldx */ 2621 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2622 2623 /* CI load/store variants */ 2624 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2625 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2626 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2627 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2628 2629 static void gen_ld(DisasContext *ctx) 2630 { 2631 TCGv EA; 2632 if (Rc(ctx->opcode)) { 2633 if (unlikely(rA(ctx->opcode) == 0 || 2634 rA(ctx->opcode) == rD(ctx->opcode))) { 2635 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2636 return; 2637 } 2638 } 2639 gen_set_access_type(ctx, ACCESS_INT); 2640 EA = tcg_temp_new(); 2641 gen_addr_imm_index(ctx, EA, 0x03); 2642 if (ctx->opcode & 0x02) { 2643 /* lwa (lwau is undefined) */ 2644 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2645 } else { 2646 /* ld - ldu */ 2647 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2648 } 2649 if (Rc(ctx->opcode)) { 2650 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2651 } 2652 tcg_temp_free(EA); 2653 } 2654 2655 /* lq */ 2656 static void gen_lq(DisasContext *ctx) 2657 { 2658 int ra, rd; 2659 TCGv EA, hi, lo; 2660 2661 /* lq is a legal user mode instruction starting in ISA 2.07 */ 2662 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2663 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2664 2665 if (!legal_in_user_mode && ctx->pr) { 2666 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2667 return; 2668 } 2669 2670 if (!le_is_supported && ctx->le_mode) { 2671 gen_align_no_le(ctx); 2672 return; 2673 } 2674 ra = rA(ctx->opcode); 2675 rd = rD(ctx->opcode); 2676 if (unlikely((rd & 1) || rd == ra)) { 2677 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2678 return; 2679 } 2680 2681 gen_set_access_type(ctx, ACCESS_INT); 2682 EA = tcg_temp_new(); 2683 gen_addr_imm_index(ctx, EA, 0x0F); 2684 2685 /* Note that the low part is always in RD+1, even in LE mode. */ 2686 lo = cpu_gpr[rd + 1]; 2687 hi = cpu_gpr[rd]; 2688 2689 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2690 if (HAVE_ATOMIC128) { 2691 TCGv_i32 oi = tcg_temp_new_i32(); 2692 if (ctx->le_mode) { 2693 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2694 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 2695 } else { 2696 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2697 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 2698 } 2699 tcg_temp_free_i32(oi); 2700 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 2701 } else { 2702 /* Restart with exclusive lock. */ 2703 gen_helper_exit_atomic(cpu_env); 2704 ctx->base.is_jmp = DISAS_NORETURN; 2705 } 2706 } else if (ctx->le_mode) { 2707 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2708 gen_addr_add(ctx, EA, EA, 8); 2709 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2710 } else { 2711 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2712 gen_addr_add(ctx, EA, EA, 8); 2713 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2714 } 2715 tcg_temp_free(EA); 2716 } 2717 #endif 2718 2719 /*** Integer store ***/ 2720 #define GEN_ST(name, stop, opc, type) \ 2721 static void glue(gen_, name)(DisasContext *ctx) \ 2722 { \ 2723 TCGv EA; \ 2724 gen_set_access_type(ctx, ACCESS_INT); \ 2725 EA = tcg_temp_new(); \ 2726 gen_addr_imm_index(ctx, EA, 0); \ 2727 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2728 tcg_temp_free(EA); \ 2729 } 2730 2731 #define GEN_STU(name, stop, opc, type) \ 2732 static void glue(gen_, stop##u)(DisasContext *ctx) \ 2733 { \ 2734 TCGv EA; \ 2735 if (unlikely(rA(ctx->opcode) == 0)) { \ 2736 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2737 return; \ 2738 } \ 2739 gen_set_access_type(ctx, ACCESS_INT); \ 2740 EA = tcg_temp_new(); \ 2741 if (type == PPC_64B) \ 2742 gen_addr_imm_index(ctx, EA, 0x03); \ 2743 else \ 2744 gen_addr_imm_index(ctx, EA, 0); \ 2745 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2746 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2747 tcg_temp_free(EA); \ 2748 } 2749 2750 #define GEN_STUX(name, stop, opc2, opc3, type) \ 2751 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2752 { \ 2753 TCGv EA; \ 2754 if (unlikely(rA(ctx->opcode) == 0)) { \ 2755 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2756 return; \ 2757 } \ 2758 gen_set_access_type(ctx, ACCESS_INT); \ 2759 EA = tcg_temp_new(); \ 2760 gen_addr_reg_index(ctx, EA); \ 2761 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2762 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2763 tcg_temp_free(EA); \ 2764 } 2765 2766 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2767 static void glue(gen_, name##x)(DisasContext *ctx) \ 2768 { \ 2769 TCGv EA; \ 2770 chk; \ 2771 gen_set_access_type(ctx, ACCESS_INT); \ 2772 EA = tcg_temp_new(); \ 2773 gen_addr_reg_index(ctx, EA); \ 2774 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2775 tcg_temp_free(EA); \ 2776 } 2777 #define GEN_STX(name, stop, opc2, opc3, type) \ 2778 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2779 2780 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2781 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2782 2783 #define GEN_STS(name, stop, op, type) \ 2784 GEN_ST(name, stop, op | 0x20, type); \ 2785 GEN_STU(name, stop, op | 0x21, type); \ 2786 GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2787 GEN_STX(name, stop, 0x17, op | 0x00, type) 2788 2789 /* stb stbu stbux stbx */ 2790 GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2791 /* sth sthu sthux sthx */ 2792 GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2793 /* stw stwu stwux stwx */ 2794 GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2795 2796 #define GEN_STEPX(name, stop, opc2, opc3) \ 2797 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2798 { \ 2799 TCGv EA; \ 2800 CHK_SV; \ 2801 gen_set_access_type(ctx, ACCESS_INT); \ 2802 EA = tcg_temp_new(); \ 2803 gen_addr_reg_index(ctx, EA); \ 2804 tcg_gen_qemu_st_tl( \ 2805 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 2806 tcg_temp_free(EA); \ 2807 } 2808 2809 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 2810 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 2811 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 2812 #if defined(TARGET_PPC64) 2813 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 2814 #endif 2815 2816 #if defined(TARGET_PPC64) 2817 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2818 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2819 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2820 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2821 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2822 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2823 2824 static void gen_std(DisasContext *ctx) 2825 { 2826 int rs; 2827 TCGv EA; 2828 2829 rs = rS(ctx->opcode); 2830 if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2831 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2832 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2833 TCGv hi, lo; 2834 2835 if (!(ctx->insns_flags & PPC_64BX)) { 2836 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2837 } 2838 2839 if (!legal_in_user_mode && ctx->pr) { 2840 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2841 return; 2842 } 2843 2844 if (!le_is_supported && ctx->le_mode) { 2845 gen_align_no_le(ctx); 2846 return; 2847 } 2848 2849 if (unlikely(rs & 1)) { 2850 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2851 return; 2852 } 2853 gen_set_access_type(ctx, ACCESS_INT); 2854 EA = tcg_temp_new(); 2855 gen_addr_imm_index(ctx, EA, 0x03); 2856 2857 /* Note that the low part is always in RS+1, even in LE mode. */ 2858 lo = cpu_gpr[rs + 1]; 2859 hi = cpu_gpr[rs]; 2860 2861 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2862 if (HAVE_ATOMIC128) { 2863 TCGv_i32 oi = tcg_temp_new_i32(); 2864 if (ctx->le_mode) { 2865 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2866 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 2867 } else { 2868 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2869 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 2870 } 2871 tcg_temp_free_i32(oi); 2872 } else { 2873 /* Restart with exclusive lock. */ 2874 gen_helper_exit_atomic(cpu_env); 2875 ctx->base.is_jmp = DISAS_NORETURN; 2876 } 2877 } else if (ctx->le_mode) { 2878 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2879 gen_addr_add(ctx, EA, EA, 8); 2880 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2881 } else { 2882 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2883 gen_addr_add(ctx, EA, EA, 8); 2884 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2885 } 2886 tcg_temp_free(EA); 2887 } else { 2888 /* std / stdu */ 2889 if (Rc(ctx->opcode)) { 2890 if (unlikely(rA(ctx->opcode) == 0)) { 2891 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2892 return; 2893 } 2894 } 2895 gen_set_access_type(ctx, ACCESS_INT); 2896 EA = tcg_temp_new(); 2897 gen_addr_imm_index(ctx, EA, 0x03); 2898 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2899 if (Rc(ctx->opcode)) { 2900 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2901 } 2902 tcg_temp_free(EA); 2903 } 2904 } 2905 #endif 2906 /*** Integer load and store with byte reverse ***/ 2907 2908 /* lhbrx */ 2909 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2910 2911 /* lwbrx */ 2912 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2913 2914 #if defined(TARGET_PPC64) 2915 /* ldbrx */ 2916 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2917 /* stdbrx */ 2918 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2919 #endif /* TARGET_PPC64 */ 2920 2921 /* sthbrx */ 2922 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2923 /* stwbrx */ 2924 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2925 2926 /*** Integer load and store multiple ***/ 2927 2928 /* lmw */ 2929 static void gen_lmw(DisasContext *ctx) 2930 { 2931 TCGv t0; 2932 TCGv_i32 t1; 2933 2934 if (ctx->le_mode) { 2935 gen_align_no_le(ctx); 2936 return; 2937 } 2938 gen_set_access_type(ctx, ACCESS_INT); 2939 t0 = tcg_temp_new(); 2940 t1 = tcg_const_i32(rD(ctx->opcode)); 2941 gen_addr_imm_index(ctx, t0, 0); 2942 gen_helper_lmw(cpu_env, t0, t1); 2943 tcg_temp_free(t0); 2944 tcg_temp_free_i32(t1); 2945 } 2946 2947 /* stmw */ 2948 static void gen_stmw(DisasContext *ctx) 2949 { 2950 TCGv t0; 2951 TCGv_i32 t1; 2952 2953 if (ctx->le_mode) { 2954 gen_align_no_le(ctx); 2955 return; 2956 } 2957 gen_set_access_type(ctx, ACCESS_INT); 2958 t0 = tcg_temp_new(); 2959 t1 = tcg_const_i32(rS(ctx->opcode)); 2960 gen_addr_imm_index(ctx, t0, 0); 2961 gen_helper_stmw(cpu_env, t0, t1); 2962 tcg_temp_free(t0); 2963 tcg_temp_free_i32(t1); 2964 } 2965 2966 /*** Integer load and store strings ***/ 2967 2968 /* lswi */ 2969 /* 2970 * PowerPC32 specification says we must generate an exception if rA is 2971 * in the range of registers to be loaded. In an other hand, IBM says 2972 * this is valid, but rA won't be loaded. For now, I'll follow the 2973 * spec... 2974 */ 2975 static void gen_lswi(DisasContext *ctx) 2976 { 2977 TCGv t0; 2978 TCGv_i32 t1, t2; 2979 int nb = NB(ctx->opcode); 2980 int start = rD(ctx->opcode); 2981 int ra = rA(ctx->opcode); 2982 int nr; 2983 2984 if (ctx->le_mode) { 2985 gen_align_no_le(ctx); 2986 return; 2987 } 2988 if (nb == 0) { 2989 nb = 32; 2990 } 2991 nr = DIV_ROUND_UP(nb, 4); 2992 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2993 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2994 return; 2995 } 2996 gen_set_access_type(ctx, ACCESS_INT); 2997 t0 = tcg_temp_new(); 2998 gen_addr_register(ctx, t0); 2999 t1 = tcg_const_i32(nb); 3000 t2 = tcg_const_i32(start); 3001 gen_helper_lsw(cpu_env, t0, t1, t2); 3002 tcg_temp_free(t0); 3003 tcg_temp_free_i32(t1); 3004 tcg_temp_free_i32(t2); 3005 } 3006 3007 /* lswx */ 3008 static void gen_lswx(DisasContext *ctx) 3009 { 3010 TCGv t0; 3011 TCGv_i32 t1, t2, t3; 3012 3013 if (ctx->le_mode) { 3014 gen_align_no_le(ctx); 3015 return; 3016 } 3017 gen_set_access_type(ctx, ACCESS_INT); 3018 t0 = tcg_temp_new(); 3019 gen_addr_reg_index(ctx, t0); 3020 t1 = tcg_const_i32(rD(ctx->opcode)); 3021 t2 = tcg_const_i32(rA(ctx->opcode)); 3022 t3 = tcg_const_i32(rB(ctx->opcode)); 3023 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3024 tcg_temp_free(t0); 3025 tcg_temp_free_i32(t1); 3026 tcg_temp_free_i32(t2); 3027 tcg_temp_free_i32(t3); 3028 } 3029 3030 /* stswi */ 3031 static void gen_stswi(DisasContext *ctx) 3032 { 3033 TCGv t0; 3034 TCGv_i32 t1, t2; 3035 int nb = NB(ctx->opcode); 3036 3037 if (ctx->le_mode) { 3038 gen_align_no_le(ctx); 3039 return; 3040 } 3041 gen_set_access_type(ctx, ACCESS_INT); 3042 t0 = tcg_temp_new(); 3043 gen_addr_register(ctx, t0); 3044 if (nb == 0) { 3045 nb = 32; 3046 } 3047 t1 = tcg_const_i32(nb); 3048 t2 = tcg_const_i32(rS(ctx->opcode)); 3049 gen_helper_stsw(cpu_env, t0, t1, t2); 3050 tcg_temp_free(t0); 3051 tcg_temp_free_i32(t1); 3052 tcg_temp_free_i32(t2); 3053 } 3054 3055 /* stswx */ 3056 static void gen_stswx(DisasContext *ctx) 3057 { 3058 TCGv t0; 3059 TCGv_i32 t1, t2; 3060 3061 if (ctx->le_mode) { 3062 gen_align_no_le(ctx); 3063 return; 3064 } 3065 gen_set_access_type(ctx, ACCESS_INT); 3066 t0 = tcg_temp_new(); 3067 gen_addr_reg_index(ctx, t0); 3068 t1 = tcg_temp_new_i32(); 3069 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3070 tcg_gen_andi_i32(t1, t1, 0x7F); 3071 t2 = tcg_const_i32(rS(ctx->opcode)); 3072 gen_helper_stsw(cpu_env, t0, t1, t2); 3073 tcg_temp_free(t0); 3074 tcg_temp_free_i32(t1); 3075 tcg_temp_free_i32(t2); 3076 } 3077 3078 /*** Memory synchronisation ***/ 3079 /* eieio */ 3080 static void gen_eieio(DisasContext *ctx) 3081 { 3082 TCGBar bar = TCG_MO_LD_ST; 3083 3084 /* 3085 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3086 * tell the CPU it is a store-forwarding barrier. 3087 */ 3088 if (ctx->opcode & 0x2000000) { 3089 /* 3090 * ISA says that "Reserved fields in instructions are ignored 3091 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3092 * as this is not an instruction software should be using, 3093 * complain to the user. 3094 */ 3095 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3096 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3097 TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 3098 } else { 3099 bar = TCG_MO_ST_LD; 3100 } 3101 } 3102 3103 tcg_gen_mb(bar | TCG_BAR_SC); 3104 } 3105 3106 #if !defined(CONFIG_USER_ONLY) 3107 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3108 { 3109 TCGv_i32 t; 3110 TCGLabel *l; 3111 3112 if (!ctx->lazy_tlb_flush) { 3113 return; 3114 } 3115 l = gen_new_label(); 3116 t = tcg_temp_new_i32(); 3117 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3118 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3119 if (global) { 3120 gen_helper_check_tlb_flush_global(cpu_env); 3121 } else { 3122 gen_helper_check_tlb_flush_local(cpu_env); 3123 } 3124 gen_set_label(l); 3125 tcg_temp_free_i32(t); 3126 } 3127 #else 3128 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3129 #endif 3130 3131 /* isync */ 3132 static void gen_isync(DisasContext *ctx) 3133 { 3134 /* 3135 * We need to check for a pending TLB flush. This can only happen in 3136 * kernel mode however so check MSR_PR 3137 */ 3138 if (!ctx->pr) { 3139 gen_check_tlb_flush(ctx, false); 3140 } 3141 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3142 gen_stop_exception(ctx); 3143 } 3144 3145 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3146 3147 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3148 { 3149 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3150 TCGv t0 = tcg_temp_new(); 3151 3152 gen_set_access_type(ctx, ACCESS_RES); 3153 gen_addr_reg_index(ctx, t0); 3154 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3155 tcg_gen_mov_tl(cpu_reserve, t0); 3156 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3157 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 3158 tcg_temp_free(t0); 3159 } 3160 3161 #define LARX(name, memop) \ 3162 static void gen_##name(DisasContext *ctx) \ 3163 { \ 3164 gen_load_locked(ctx, memop); \ 3165 } 3166 3167 /* lwarx */ 3168 LARX(lbarx, DEF_MEMOP(MO_UB)) 3169 LARX(lharx, DEF_MEMOP(MO_UW)) 3170 LARX(lwarx, DEF_MEMOP(MO_UL)) 3171 3172 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3173 TCGv EA, TCGCond cond, int addend) 3174 { 3175 TCGv t = tcg_temp_new(); 3176 TCGv t2 = tcg_temp_new(); 3177 TCGv u = tcg_temp_new(); 3178 3179 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3180 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3181 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3182 tcg_gen_addi_tl(u, t, addend); 3183 3184 /* E.g. for fetch and increment bounded... */ 3185 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3186 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3187 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3188 3189 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3190 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3191 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3192 3193 tcg_temp_free(t); 3194 tcg_temp_free(t2); 3195 tcg_temp_free(u); 3196 } 3197 3198 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3199 { 3200 uint32_t gpr_FC = FC(ctx->opcode); 3201 TCGv EA = tcg_temp_new(); 3202 int rt = rD(ctx->opcode); 3203 bool need_serial; 3204 TCGv src, dst; 3205 3206 gen_addr_register(ctx, EA); 3207 dst = cpu_gpr[rt]; 3208 src = cpu_gpr[(rt + 1) & 31]; 3209 3210 need_serial = false; 3211 memop |= MO_ALIGN; 3212 switch (gpr_FC) { 3213 case 0: /* Fetch and add */ 3214 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3215 break; 3216 case 1: /* Fetch and xor */ 3217 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3218 break; 3219 case 2: /* Fetch and or */ 3220 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3221 break; 3222 case 3: /* Fetch and 'and' */ 3223 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3224 break; 3225 case 4: /* Fetch and max unsigned */ 3226 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3227 break; 3228 case 5: /* Fetch and max signed */ 3229 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3230 break; 3231 case 6: /* Fetch and min unsigned */ 3232 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3233 break; 3234 case 7: /* Fetch and min signed */ 3235 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3236 break; 3237 case 8: /* Swap */ 3238 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3239 break; 3240 3241 case 16: /* Compare and swap not equal */ 3242 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3243 need_serial = true; 3244 } else { 3245 TCGv t0 = tcg_temp_new(); 3246 TCGv t1 = tcg_temp_new(); 3247 3248 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3249 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3250 tcg_gen_mov_tl(t1, src); 3251 } else { 3252 tcg_gen_ext32u_tl(t1, src); 3253 } 3254 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3255 cpu_gpr[(rt + 2) & 31], t0); 3256 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3257 tcg_gen_mov_tl(dst, t0); 3258 3259 tcg_temp_free(t0); 3260 tcg_temp_free(t1); 3261 } 3262 break; 3263 3264 case 24: /* Fetch and increment bounded */ 3265 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3266 need_serial = true; 3267 } else { 3268 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3269 } 3270 break; 3271 case 25: /* Fetch and increment equal */ 3272 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3273 need_serial = true; 3274 } else { 3275 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3276 } 3277 break; 3278 case 28: /* Fetch and decrement bounded */ 3279 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3280 need_serial = true; 3281 } else { 3282 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3283 } 3284 break; 3285 3286 default: 3287 /* invoke data storage error handler */ 3288 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3289 } 3290 tcg_temp_free(EA); 3291 3292 if (need_serial) { 3293 /* Restart with exclusive lock. */ 3294 gen_helper_exit_atomic(cpu_env); 3295 ctx->base.is_jmp = DISAS_NORETURN; 3296 } 3297 } 3298 3299 static void gen_lwat(DisasContext *ctx) 3300 { 3301 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3302 } 3303 3304 #ifdef TARGET_PPC64 3305 static void gen_ldat(DisasContext *ctx) 3306 { 3307 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 3308 } 3309 #endif 3310 3311 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3312 { 3313 uint32_t gpr_FC = FC(ctx->opcode); 3314 TCGv EA = tcg_temp_new(); 3315 TCGv src, discard; 3316 3317 gen_addr_register(ctx, EA); 3318 src = cpu_gpr[rD(ctx->opcode)]; 3319 discard = tcg_temp_new(); 3320 3321 memop |= MO_ALIGN; 3322 switch (gpr_FC) { 3323 case 0: /* add and Store */ 3324 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3325 break; 3326 case 1: /* xor and Store */ 3327 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3328 break; 3329 case 2: /* Or and Store */ 3330 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3331 break; 3332 case 3: /* 'and' and Store */ 3333 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3334 break; 3335 case 4: /* Store max unsigned */ 3336 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3337 break; 3338 case 5: /* Store max signed */ 3339 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3340 break; 3341 case 6: /* Store min unsigned */ 3342 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3343 break; 3344 case 7: /* Store min signed */ 3345 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3346 break; 3347 case 24: /* Store twin */ 3348 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3349 /* Restart with exclusive lock. */ 3350 gen_helper_exit_atomic(cpu_env); 3351 ctx->base.is_jmp = DISAS_NORETURN; 3352 } else { 3353 TCGv t = tcg_temp_new(); 3354 TCGv t2 = tcg_temp_new(); 3355 TCGv s = tcg_temp_new(); 3356 TCGv s2 = tcg_temp_new(); 3357 TCGv ea_plus_s = tcg_temp_new(); 3358 3359 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3360 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3361 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3362 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3363 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3364 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3365 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3366 3367 tcg_temp_free(ea_plus_s); 3368 tcg_temp_free(s2); 3369 tcg_temp_free(s); 3370 tcg_temp_free(t2); 3371 tcg_temp_free(t); 3372 } 3373 break; 3374 default: 3375 /* invoke data storage error handler */ 3376 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3377 } 3378 tcg_temp_free(discard); 3379 tcg_temp_free(EA); 3380 } 3381 3382 static void gen_stwat(DisasContext *ctx) 3383 { 3384 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3385 } 3386 3387 #ifdef TARGET_PPC64 3388 static void gen_stdat(DisasContext *ctx) 3389 { 3390 gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 3391 } 3392 #endif 3393 3394 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3395 { 3396 TCGLabel *l1 = gen_new_label(); 3397 TCGLabel *l2 = gen_new_label(); 3398 TCGv t0 = tcg_temp_new(); 3399 int reg = rS(ctx->opcode); 3400 3401 gen_set_access_type(ctx, ACCESS_RES); 3402 gen_addr_reg_index(ctx, t0); 3403 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3404 tcg_temp_free(t0); 3405 3406 t0 = tcg_temp_new(); 3407 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3408 cpu_gpr[reg], ctx->mem_idx, 3409 DEF_MEMOP(memop) | MO_ALIGN); 3410 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3411 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3412 tcg_gen_or_tl(t0, t0, cpu_so); 3413 tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3414 tcg_temp_free(t0); 3415 tcg_gen_br(l2); 3416 3417 gen_set_label(l1); 3418 3419 /* 3420 * Address mismatch implies failure. But we still need to provide 3421 * the memory barrier semantics of the instruction. 3422 */ 3423 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3424 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3425 3426 gen_set_label(l2); 3427 tcg_gen_movi_tl(cpu_reserve, -1); 3428 } 3429 3430 #define STCX(name, memop) \ 3431 static void gen_##name(DisasContext *ctx) \ 3432 { \ 3433 gen_conditional_store(ctx, memop); \ 3434 } 3435 3436 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3437 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3438 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3439 3440 #if defined(TARGET_PPC64) 3441 /* ldarx */ 3442 LARX(ldarx, DEF_MEMOP(MO_Q)) 3443 /* stdcx. */ 3444 STCX(stdcx_, DEF_MEMOP(MO_Q)) 3445 3446 /* lqarx */ 3447 static void gen_lqarx(DisasContext *ctx) 3448 { 3449 int rd = rD(ctx->opcode); 3450 TCGv EA, hi, lo; 3451 3452 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3453 (rd == rB(ctx->opcode)))) { 3454 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3455 return; 3456 } 3457 3458 gen_set_access_type(ctx, ACCESS_RES); 3459 EA = tcg_temp_new(); 3460 gen_addr_reg_index(ctx, EA); 3461 3462 /* Note that the low part is always in RD+1, even in LE mode. */ 3463 lo = cpu_gpr[rd + 1]; 3464 hi = cpu_gpr[rd]; 3465 3466 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3467 if (HAVE_ATOMIC128) { 3468 TCGv_i32 oi = tcg_temp_new_i32(); 3469 if (ctx->le_mode) { 3470 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 3471 ctx->mem_idx)); 3472 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3473 } else { 3474 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 3475 ctx->mem_idx)); 3476 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3477 } 3478 tcg_temp_free_i32(oi); 3479 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3480 } else { 3481 /* Restart with exclusive lock. */ 3482 gen_helper_exit_atomic(cpu_env); 3483 ctx->base.is_jmp = DISAS_NORETURN; 3484 tcg_temp_free(EA); 3485 return; 3486 } 3487 } else if (ctx->le_mode) { 3488 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3489 tcg_gen_mov_tl(cpu_reserve, EA); 3490 gen_addr_add(ctx, EA, EA, 8); 3491 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3492 } else { 3493 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 3494 tcg_gen_mov_tl(cpu_reserve, EA); 3495 gen_addr_add(ctx, EA, EA, 8); 3496 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3497 } 3498 tcg_temp_free(EA); 3499 3500 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3501 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3502 } 3503 3504 /* stqcx. */ 3505 static void gen_stqcx_(DisasContext *ctx) 3506 { 3507 int rs = rS(ctx->opcode); 3508 TCGv EA, hi, lo; 3509 3510 if (unlikely(rs & 1)) { 3511 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3512 return; 3513 } 3514 3515 gen_set_access_type(ctx, ACCESS_RES); 3516 EA = tcg_temp_new(); 3517 gen_addr_reg_index(ctx, EA); 3518 3519 /* Note that the low part is always in RS+1, even in LE mode. */ 3520 lo = cpu_gpr[rs + 1]; 3521 hi = cpu_gpr[rs]; 3522 3523 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3524 if (HAVE_CMPXCHG128) { 3525 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 3526 if (ctx->le_mode) { 3527 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 3528 EA, lo, hi, oi); 3529 } else { 3530 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 3531 EA, lo, hi, oi); 3532 } 3533 tcg_temp_free_i32(oi); 3534 } else { 3535 /* Restart with exclusive lock. */ 3536 gen_helper_exit_atomic(cpu_env); 3537 ctx->base.is_jmp = DISAS_NORETURN; 3538 } 3539 tcg_temp_free(EA); 3540 } else { 3541 TCGLabel *lab_fail = gen_new_label(); 3542 TCGLabel *lab_over = gen_new_label(); 3543 TCGv_i64 t0 = tcg_temp_new_i64(); 3544 TCGv_i64 t1 = tcg_temp_new_i64(); 3545 3546 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 3547 tcg_temp_free(EA); 3548 3549 gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 3550 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 3551 ? offsetof(CPUPPCState, reserve_val2) 3552 : offsetof(CPUPPCState, reserve_val))); 3553 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 3554 3555 tcg_gen_addi_i64(t0, cpu_reserve, 8); 3556 gen_qemu_ld64_i64(ctx, t0, t0); 3557 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 3558 ? offsetof(CPUPPCState, reserve_val) 3559 : offsetof(CPUPPCState, reserve_val2))); 3560 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 3561 3562 /* Success */ 3563 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 3564 tcg_gen_addi_i64(t0, cpu_reserve, 8); 3565 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 3566 3567 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3568 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3569 tcg_gen_br(lab_over); 3570 3571 gen_set_label(lab_fail); 3572 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3573 3574 gen_set_label(lab_over); 3575 tcg_gen_movi_tl(cpu_reserve, -1); 3576 tcg_temp_free_i64(t0); 3577 tcg_temp_free_i64(t1); 3578 } 3579 } 3580 #endif /* defined(TARGET_PPC64) */ 3581 3582 /* sync */ 3583 static void gen_sync(DisasContext *ctx) 3584 { 3585 uint32_t l = (ctx->opcode >> 21) & 3; 3586 3587 /* 3588 * We may need to check for a pending TLB flush. 3589 * 3590 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3591 * 3592 * Additionally, this can only happen in kernel mode however so 3593 * check MSR_PR as well. 3594 */ 3595 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3596 gen_check_tlb_flush(ctx, true); 3597 } 3598 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3599 } 3600 3601 /* wait */ 3602 static void gen_wait(DisasContext *ctx) 3603 { 3604 TCGv_i32 t0 = tcg_const_i32(1); 3605 tcg_gen_st_i32(t0, cpu_env, 3606 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3607 tcg_temp_free_i32(t0); 3608 /* Stop translation, as the CPU is supposed to sleep from now */ 3609 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3610 } 3611 3612 #if defined(TARGET_PPC64) 3613 static void gen_doze(DisasContext *ctx) 3614 { 3615 #if defined(CONFIG_USER_ONLY) 3616 GEN_PRIV; 3617 #else 3618 TCGv_i32 t; 3619 3620 CHK_HV; 3621 t = tcg_const_i32(PPC_PM_DOZE); 3622 gen_helper_pminsn(cpu_env, t); 3623 tcg_temp_free_i32(t); 3624 /* Stop translation, as the CPU is supposed to sleep from now */ 3625 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3626 #endif /* defined(CONFIG_USER_ONLY) */ 3627 } 3628 3629 static void gen_nap(DisasContext *ctx) 3630 { 3631 #if defined(CONFIG_USER_ONLY) 3632 GEN_PRIV; 3633 #else 3634 TCGv_i32 t; 3635 3636 CHK_HV; 3637 t = tcg_const_i32(PPC_PM_NAP); 3638 gen_helper_pminsn(cpu_env, t); 3639 tcg_temp_free_i32(t); 3640 /* Stop translation, as the CPU is supposed to sleep from now */ 3641 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3642 #endif /* defined(CONFIG_USER_ONLY) */ 3643 } 3644 3645 static void gen_stop(DisasContext *ctx) 3646 { 3647 #if defined(CONFIG_USER_ONLY) 3648 GEN_PRIV; 3649 #else 3650 TCGv_i32 t; 3651 3652 CHK_HV; 3653 t = tcg_const_i32(PPC_PM_STOP); 3654 gen_helper_pminsn(cpu_env, t); 3655 tcg_temp_free_i32(t); 3656 /* Stop translation, as the CPU is supposed to sleep from now */ 3657 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3658 #endif /* defined(CONFIG_USER_ONLY) */ 3659 } 3660 3661 static void gen_sleep(DisasContext *ctx) 3662 { 3663 #if defined(CONFIG_USER_ONLY) 3664 GEN_PRIV; 3665 #else 3666 TCGv_i32 t; 3667 3668 CHK_HV; 3669 t = tcg_const_i32(PPC_PM_SLEEP); 3670 gen_helper_pminsn(cpu_env, t); 3671 tcg_temp_free_i32(t); 3672 /* Stop translation, as the CPU is supposed to sleep from now */ 3673 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3674 #endif /* defined(CONFIG_USER_ONLY) */ 3675 } 3676 3677 static void gen_rvwinkle(DisasContext *ctx) 3678 { 3679 #if defined(CONFIG_USER_ONLY) 3680 GEN_PRIV; 3681 #else 3682 TCGv_i32 t; 3683 3684 CHK_HV; 3685 t = tcg_const_i32(PPC_PM_RVWINKLE); 3686 gen_helper_pminsn(cpu_env, t); 3687 tcg_temp_free_i32(t); 3688 /* Stop translation, as the CPU is supposed to sleep from now */ 3689 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3690 #endif /* defined(CONFIG_USER_ONLY) */ 3691 } 3692 #endif /* #if defined(TARGET_PPC64) */ 3693 3694 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3695 { 3696 #if defined(TARGET_PPC64) 3697 if (ctx->has_cfar) { 3698 tcg_gen_movi_tl(cpu_cfar, nip); 3699 } 3700 #endif 3701 } 3702 3703 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3704 { 3705 if (unlikely(ctx->singlestep_enabled)) { 3706 return false; 3707 } 3708 3709 #ifndef CONFIG_USER_ONLY 3710 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3711 #else 3712 return true; 3713 #endif 3714 } 3715 3716 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 3717 { 3718 int sse = ctx->singlestep_enabled; 3719 if (unlikely(sse)) { 3720 if (sse & GDBSTUB_SINGLE_STEP) { 3721 gen_debug_exception(ctx); 3722 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 3723 uint32_t excp = gen_prep_dbgex(ctx); 3724 gen_exception(ctx, excp); 3725 } 3726 tcg_gen_exit_tb(NULL, 0); 3727 } else { 3728 tcg_gen_lookup_and_goto_ptr(); 3729 } 3730 } 3731 3732 /*** Branch ***/ 3733 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3734 { 3735 if (NARROW_MODE(ctx)) { 3736 dest = (uint32_t) dest; 3737 } 3738 if (use_goto_tb(ctx, dest)) { 3739 tcg_gen_goto_tb(n); 3740 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3741 tcg_gen_exit_tb(ctx->base.tb, n); 3742 } else { 3743 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3744 gen_lookup_and_goto_ptr(ctx); 3745 } 3746 } 3747 3748 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3749 { 3750 if (NARROW_MODE(ctx)) { 3751 nip = (uint32_t)nip; 3752 } 3753 tcg_gen_movi_tl(cpu_lr, nip); 3754 } 3755 3756 /* b ba bl bla */ 3757 static void gen_b(DisasContext *ctx) 3758 { 3759 target_ulong li, target; 3760 3761 ctx->exception = POWERPC_EXCP_BRANCH; 3762 /* sign extend LI */ 3763 li = LI(ctx->opcode); 3764 li = (li ^ 0x02000000) - 0x02000000; 3765 if (likely(AA(ctx->opcode) == 0)) { 3766 target = ctx->base.pc_next + li - 4; 3767 } else { 3768 target = li; 3769 } 3770 if (LK(ctx->opcode)) { 3771 gen_setlr(ctx, ctx->base.pc_next); 3772 } 3773 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3774 gen_goto_tb(ctx, 0, target); 3775 } 3776 3777 #define BCOND_IM 0 3778 #define BCOND_LR 1 3779 #define BCOND_CTR 2 3780 #define BCOND_TAR 3 3781 3782 static void gen_bcond(DisasContext *ctx, int type) 3783 { 3784 uint32_t bo = BO(ctx->opcode); 3785 TCGLabel *l1; 3786 TCGv target; 3787 ctx->exception = POWERPC_EXCP_BRANCH; 3788 3789 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3790 target = tcg_temp_local_new(); 3791 if (type == BCOND_CTR) { 3792 tcg_gen_mov_tl(target, cpu_ctr); 3793 } else if (type == BCOND_TAR) { 3794 gen_load_spr(target, SPR_TAR); 3795 } else { 3796 tcg_gen_mov_tl(target, cpu_lr); 3797 } 3798 } else { 3799 target = NULL; 3800 } 3801 if (LK(ctx->opcode)) { 3802 gen_setlr(ctx, ctx->base.pc_next); 3803 } 3804 l1 = gen_new_label(); 3805 if ((bo & 0x4) == 0) { 3806 /* Decrement and test CTR */ 3807 TCGv temp = tcg_temp_new(); 3808 3809 if (type == BCOND_CTR) { 3810 /* 3811 * All ISAs up to v3 describe this form of bcctr as invalid but 3812 * some processors, ie. 64-bit server processors compliant with 3813 * arch 2.x, do implement a "test and decrement" logic instead, 3814 * as described in their respective UMs. This logic involves CTR 3815 * to act as both the branch target and a counter, which makes 3816 * it basically useless and thus never used in real code. 3817 * 3818 * This form was hence chosen to trigger extra micro-architectural 3819 * side-effect on real HW needed for the Spectre v2 workaround. 3820 * It is up to guests that implement such workaround, ie. linux, to 3821 * use this form in a way it just triggers the side-effect without 3822 * doing anything else harmful. 3823 */ 3824 if (unlikely(!is_book3s_arch2x(ctx))) { 3825 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3826 tcg_temp_free(temp); 3827 tcg_temp_free(target); 3828 return; 3829 } 3830 3831 if (NARROW_MODE(ctx)) { 3832 tcg_gen_ext32u_tl(temp, cpu_ctr); 3833 } else { 3834 tcg_gen_mov_tl(temp, cpu_ctr); 3835 } 3836 if (bo & 0x2) { 3837 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3838 } else { 3839 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3840 } 3841 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3842 } else { 3843 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3844 if (NARROW_MODE(ctx)) { 3845 tcg_gen_ext32u_tl(temp, cpu_ctr); 3846 } else { 3847 tcg_gen_mov_tl(temp, cpu_ctr); 3848 } 3849 if (bo & 0x2) { 3850 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3851 } else { 3852 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3853 } 3854 } 3855 tcg_temp_free(temp); 3856 } 3857 if ((bo & 0x10) == 0) { 3858 /* Test CR */ 3859 uint32_t bi = BI(ctx->opcode); 3860 uint32_t mask = 0x08 >> (bi & 0x03); 3861 TCGv_i32 temp = tcg_temp_new_i32(); 3862 3863 if (bo & 0x8) { 3864 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3865 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3866 } else { 3867 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3868 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3869 } 3870 tcg_temp_free_i32(temp); 3871 } 3872 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3873 if (type == BCOND_IM) { 3874 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3875 if (likely(AA(ctx->opcode) == 0)) { 3876 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3877 } else { 3878 gen_goto_tb(ctx, 0, li); 3879 } 3880 } else { 3881 if (NARROW_MODE(ctx)) { 3882 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3883 } else { 3884 tcg_gen_andi_tl(cpu_nip, target, ~3); 3885 } 3886 gen_lookup_and_goto_ptr(ctx); 3887 tcg_temp_free(target); 3888 } 3889 if ((bo & 0x14) != 0x14) { 3890 /* fallthrough case */ 3891 gen_set_label(l1); 3892 gen_goto_tb(ctx, 1, ctx->base.pc_next); 3893 } 3894 } 3895 3896 static void gen_bc(DisasContext *ctx) 3897 { 3898 gen_bcond(ctx, BCOND_IM); 3899 } 3900 3901 static void gen_bcctr(DisasContext *ctx) 3902 { 3903 gen_bcond(ctx, BCOND_CTR); 3904 } 3905 3906 static void gen_bclr(DisasContext *ctx) 3907 { 3908 gen_bcond(ctx, BCOND_LR); 3909 } 3910 3911 static void gen_bctar(DisasContext *ctx) 3912 { 3913 gen_bcond(ctx, BCOND_TAR); 3914 } 3915 3916 /*** Condition register logical ***/ 3917 #define GEN_CRLOGIC(name, tcg_op, opc) \ 3918 static void glue(gen_, name)(DisasContext *ctx) \ 3919 { \ 3920 uint8_t bitmask; \ 3921 int sh; \ 3922 TCGv_i32 t0, t1; \ 3923 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3924 t0 = tcg_temp_new_i32(); \ 3925 if (sh > 0) \ 3926 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3927 else if (sh < 0) \ 3928 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3929 else \ 3930 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3931 t1 = tcg_temp_new_i32(); \ 3932 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3933 if (sh > 0) \ 3934 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3935 else if (sh < 0) \ 3936 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3937 else \ 3938 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3939 tcg_op(t0, t0, t1); \ 3940 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3941 tcg_gen_andi_i32(t0, t0, bitmask); \ 3942 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3943 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3944 tcg_temp_free_i32(t0); \ 3945 tcg_temp_free_i32(t1); \ 3946 } 3947 3948 /* crand */ 3949 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3950 /* crandc */ 3951 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3952 /* creqv */ 3953 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3954 /* crnand */ 3955 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3956 /* crnor */ 3957 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3958 /* cror */ 3959 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3960 /* crorc */ 3961 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3962 /* crxor */ 3963 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3964 3965 /* mcrf */ 3966 static void gen_mcrf(DisasContext *ctx) 3967 { 3968 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3969 } 3970 3971 /*** System linkage ***/ 3972 3973 /* rfi (supervisor only) */ 3974 static void gen_rfi(DisasContext *ctx) 3975 { 3976 #if defined(CONFIG_USER_ONLY) 3977 GEN_PRIV; 3978 #else 3979 /* 3980 * This instruction doesn't exist anymore on 64-bit server 3981 * processors compliant with arch 2.x 3982 */ 3983 if (is_book3s_arch2x(ctx)) { 3984 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3985 return; 3986 } 3987 /* Restore CPU state */ 3988 CHK_SV; 3989 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 3990 gen_io_start(); 3991 } 3992 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3993 gen_helper_rfi(cpu_env); 3994 gen_sync_exception(ctx); 3995 #endif 3996 } 3997 3998 #if defined(TARGET_PPC64) 3999 static void gen_rfid(DisasContext *ctx) 4000 { 4001 #if defined(CONFIG_USER_ONLY) 4002 GEN_PRIV; 4003 #else 4004 /* Restore CPU state */ 4005 CHK_SV; 4006 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4007 gen_io_start(); 4008 } 4009 gen_update_cfar(ctx, ctx->base.pc_next - 4); 4010 gen_helper_rfid(cpu_env); 4011 gen_sync_exception(ctx); 4012 #endif 4013 } 4014 4015 static void gen_hrfid(DisasContext *ctx) 4016 { 4017 #if defined(CONFIG_USER_ONLY) 4018 GEN_PRIV; 4019 #else 4020 /* Restore CPU state */ 4021 CHK_HV; 4022 gen_helper_hrfid(cpu_env); 4023 gen_sync_exception(ctx); 4024 #endif 4025 } 4026 #endif 4027 4028 /* sc */ 4029 #if defined(CONFIG_USER_ONLY) 4030 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4031 #else 4032 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4033 #endif 4034 static void gen_sc(DisasContext *ctx) 4035 { 4036 uint32_t lev; 4037 4038 lev = (ctx->opcode >> 5) & 0x7F; 4039 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4040 } 4041 4042 /*** Trap ***/ 4043 4044 /* Check for unconditional traps (always or never) */ 4045 static bool check_unconditional_trap(DisasContext *ctx) 4046 { 4047 /* Trap never */ 4048 if (TO(ctx->opcode) == 0) { 4049 return true; 4050 } 4051 /* Trap always */ 4052 if (TO(ctx->opcode) == 31) { 4053 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4054 return true; 4055 } 4056 return false; 4057 } 4058 4059 /* tw */ 4060 static void gen_tw(DisasContext *ctx) 4061 { 4062 TCGv_i32 t0; 4063 4064 if (check_unconditional_trap(ctx)) { 4065 return; 4066 } 4067 t0 = tcg_const_i32(TO(ctx->opcode)); 4068 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4069 t0); 4070 tcg_temp_free_i32(t0); 4071 } 4072 4073 /* twi */ 4074 static void gen_twi(DisasContext *ctx) 4075 { 4076 TCGv t0; 4077 TCGv_i32 t1; 4078 4079 if (check_unconditional_trap(ctx)) { 4080 return; 4081 } 4082 t0 = tcg_const_tl(SIMM(ctx->opcode)); 4083 t1 = tcg_const_i32(TO(ctx->opcode)); 4084 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4085 tcg_temp_free(t0); 4086 tcg_temp_free_i32(t1); 4087 } 4088 4089 #if defined(TARGET_PPC64) 4090 /* td */ 4091 static void gen_td(DisasContext *ctx) 4092 { 4093 TCGv_i32 t0; 4094 4095 if (check_unconditional_trap(ctx)) { 4096 return; 4097 } 4098 t0 = tcg_const_i32(TO(ctx->opcode)); 4099 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4100 t0); 4101 tcg_temp_free_i32(t0); 4102 } 4103 4104 /* tdi */ 4105 static void gen_tdi(DisasContext *ctx) 4106 { 4107 TCGv t0; 4108 TCGv_i32 t1; 4109 4110 if (check_unconditional_trap(ctx)) { 4111 return; 4112 } 4113 t0 = tcg_const_tl(SIMM(ctx->opcode)); 4114 t1 = tcg_const_i32(TO(ctx->opcode)); 4115 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4116 tcg_temp_free(t0); 4117 tcg_temp_free_i32(t1); 4118 } 4119 #endif 4120 4121 /*** Processor control ***/ 4122 4123 static void gen_read_xer(DisasContext *ctx, TCGv dst) 4124 { 4125 TCGv t0 = tcg_temp_new(); 4126 TCGv t1 = tcg_temp_new(); 4127 TCGv t2 = tcg_temp_new(); 4128 tcg_gen_mov_tl(dst, cpu_xer); 4129 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 4130 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 4131 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 4132 tcg_gen_or_tl(t0, t0, t1); 4133 tcg_gen_or_tl(dst, dst, t2); 4134 tcg_gen_or_tl(dst, dst, t0); 4135 if (is_isa300(ctx)) { 4136 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 4137 tcg_gen_or_tl(dst, dst, t0); 4138 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 4139 tcg_gen_or_tl(dst, dst, t0); 4140 } 4141 tcg_temp_free(t0); 4142 tcg_temp_free(t1); 4143 tcg_temp_free(t2); 4144 } 4145 4146 static void gen_write_xer(TCGv src) 4147 { 4148 /* Write all flags, while reading back check for isa300 */ 4149 tcg_gen_andi_tl(cpu_xer, src, 4150 ~((1u << XER_SO) | 4151 (1u << XER_OV) | (1u << XER_OV32) | 4152 (1u << XER_CA) | (1u << XER_CA32))); 4153 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 4154 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 4155 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 4156 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 4157 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 4158 } 4159 4160 /* mcrxr */ 4161 static void gen_mcrxr(DisasContext *ctx) 4162 { 4163 TCGv_i32 t0 = tcg_temp_new_i32(); 4164 TCGv_i32 t1 = tcg_temp_new_i32(); 4165 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4166 4167 tcg_gen_trunc_tl_i32(t0, cpu_so); 4168 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4169 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4170 tcg_gen_shli_i32(t0, t0, 3); 4171 tcg_gen_shli_i32(t1, t1, 2); 4172 tcg_gen_shli_i32(dst, dst, 1); 4173 tcg_gen_or_i32(dst, dst, t0); 4174 tcg_gen_or_i32(dst, dst, t1); 4175 tcg_temp_free_i32(t0); 4176 tcg_temp_free_i32(t1); 4177 4178 tcg_gen_movi_tl(cpu_so, 0); 4179 tcg_gen_movi_tl(cpu_ov, 0); 4180 tcg_gen_movi_tl(cpu_ca, 0); 4181 } 4182 4183 #ifdef TARGET_PPC64 4184 /* mcrxrx */ 4185 static void gen_mcrxrx(DisasContext *ctx) 4186 { 4187 TCGv t0 = tcg_temp_new(); 4188 TCGv t1 = tcg_temp_new(); 4189 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4190 4191 /* copy OV and OV32 */ 4192 tcg_gen_shli_tl(t0, cpu_ov, 1); 4193 tcg_gen_or_tl(t0, t0, cpu_ov32); 4194 tcg_gen_shli_tl(t0, t0, 2); 4195 /* copy CA and CA32 */ 4196 tcg_gen_shli_tl(t1, cpu_ca, 1); 4197 tcg_gen_or_tl(t1, t1, cpu_ca32); 4198 tcg_gen_or_tl(t0, t0, t1); 4199 tcg_gen_trunc_tl_i32(dst, t0); 4200 tcg_temp_free(t0); 4201 tcg_temp_free(t1); 4202 } 4203 #endif 4204 4205 /* mfcr mfocrf */ 4206 static void gen_mfcr(DisasContext *ctx) 4207 { 4208 uint32_t crm, crn; 4209 4210 if (likely(ctx->opcode & 0x00100000)) { 4211 crm = CRM(ctx->opcode); 4212 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4213 crn = ctz32(crm); 4214 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4215 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4216 cpu_gpr[rD(ctx->opcode)], crn * 4); 4217 } 4218 } else { 4219 TCGv_i32 t0 = tcg_temp_new_i32(); 4220 tcg_gen_mov_i32(t0, cpu_crf[0]); 4221 tcg_gen_shli_i32(t0, t0, 4); 4222 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4223 tcg_gen_shli_i32(t0, t0, 4); 4224 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4225 tcg_gen_shli_i32(t0, t0, 4); 4226 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4227 tcg_gen_shli_i32(t0, t0, 4); 4228 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4229 tcg_gen_shli_i32(t0, t0, 4); 4230 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4231 tcg_gen_shli_i32(t0, t0, 4); 4232 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4233 tcg_gen_shli_i32(t0, t0, 4); 4234 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4235 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4236 tcg_temp_free_i32(t0); 4237 } 4238 } 4239 4240 /* mfmsr */ 4241 static void gen_mfmsr(DisasContext *ctx) 4242 { 4243 CHK_SV; 4244 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4245 } 4246 4247 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 4248 { 4249 #if 0 4250 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 4251 printf("ERROR: try to access SPR %d !\n", sprn); 4252 #endif 4253 } 4254 #define SPR_NOACCESS (&spr_noaccess) 4255 4256 /* mfspr */ 4257 static inline void gen_op_mfspr(DisasContext *ctx) 4258 { 4259 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4260 uint32_t sprn = SPR(ctx->opcode); 4261 4262 #if defined(CONFIG_USER_ONLY) 4263 read_cb = ctx->spr_cb[sprn].uea_read; 4264 #else 4265 if (ctx->pr) { 4266 read_cb = ctx->spr_cb[sprn].uea_read; 4267 } else if (ctx->hv) { 4268 read_cb = ctx->spr_cb[sprn].hea_read; 4269 } else { 4270 read_cb = ctx->spr_cb[sprn].oea_read; 4271 } 4272 #endif 4273 if (likely(read_cb != NULL)) { 4274 if (likely(read_cb != SPR_NOACCESS)) { 4275 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4276 } else { 4277 /* Privilege exception */ 4278 /* 4279 * This is a hack to avoid warnings when running Linux: 4280 * this OS breaks the PowerPC virtualisation model, 4281 * allowing userland application to read the PVR 4282 */ 4283 if (sprn != SPR_PVR) { 4284 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4285 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4286 ctx->base.pc_next - 4); 4287 } 4288 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4289 } 4290 } else { 4291 /* ISA 2.07 defines these as no-ops */ 4292 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4293 (sprn >= 808 && sprn <= 811)) { 4294 /* This is a nop */ 4295 return; 4296 } 4297 /* Not defined */ 4298 qemu_log_mask(LOG_GUEST_ERROR, 4299 "Trying to read invalid spr %d (0x%03x) at " 4300 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4301 4302 /* 4303 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4304 * generate a priv, a hv emu or a no-op 4305 */ 4306 if (sprn & 0x10) { 4307 if (ctx->pr) { 4308 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4309 } 4310 } else { 4311 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4312 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4313 } 4314 } 4315 } 4316 } 4317 4318 static void gen_mfspr(DisasContext *ctx) 4319 { 4320 gen_op_mfspr(ctx); 4321 } 4322 4323 /* mftb */ 4324 static void gen_mftb(DisasContext *ctx) 4325 { 4326 gen_op_mfspr(ctx); 4327 } 4328 4329 /* mtcrf mtocrf*/ 4330 static void gen_mtcrf(DisasContext *ctx) 4331 { 4332 uint32_t crm, crn; 4333 4334 crm = CRM(ctx->opcode); 4335 if (likely((ctx->opcode & 0x00100000))) { 4336 if (crm && ((crm & (crm - 1)) == 0)) { 4337 TCGv_i32 temp = tcg_temp_new_i32(); 4338 crn = ctz32(crm); 4339 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4340 tcg_gen_shri_i32(temp, temp, crn * 4); 4341 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4342 tcg_temp_free_i32(temp); 4343 } 4344 } else { 4345 TCGv_i32 temp = tcg_temp_new_i32(); 4346 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4347 for (crn = 0 ; crn < 8 ; crn++) { 4348 if (crm & (1 << crn)) { 4349 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4350 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4351 } 4352 } 4353 tcg_temp_free_i32(temp); 4354 } 4355 } 4356 4357 /* mtmsr */ 4358 #if defined(TARGET_PPC64) 4359 static void gen_mtmsrd(DisasContext *ctx) 4360 { 4361 CHK_SV; 4362 4363 #if !defined(CONFIG_USER_ONLY) 4364 if (ctx->opcode & 0x00010000) { 4365 /* Special form that does not need any synchronisation */ 4366 TCGv t0 = tcg_temp_new(); 4367 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4368 (1 << MSR_RI) | (1 << MSR_EE)); 4369 tcg_gen_andi_tl(cpu_msr, cpu_msr, 4370 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4371 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4372 tcg_temp_free(t0); 4373 } else { 4374 /* 4375 * XXX: we need to update nip before the store if we enter 4376 * power saving mode, we will exit the loop directly from 4377 * ppc_store_msr 4378 */ 4379 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4380 gen_io_start(); 4381 } 4382 gen_update_nip(ctx, ctx->base.pc_next); 4383 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4384 /* Must stop the translation as machine state (may have) changed */ 4385 /* Note that mtmsr is not always defined as context-synchronizing */ 4386 gen_stop_exception(ctx); 4387 } 4388 #endif /* !defined(CONFIG_USER_ONLY) */ 4389 } 4390 #endif /* defined(TARGET_PPC64) */ 4391 4392 static void gen_mtmsr(DisasContext *ctx) 4393 { 4394 CHK_SV; 4395 4396 #if !defined(CONFIG_USER_ONLY) 4397 if (ctx->opcode & 0x00010000) { 4398 /* Special form that does not need any synchronisation */ 4399 TCGv t0 = tcg_temp_new(); 4400 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4401 (1 << MSR_RI) | (1 << MSR_EE)); 4402 tcg_gen_andi_tl(cpu_msr, cpu_msr, 4403 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4404 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4405 tcg_temp_free(t0); 4406 } else { 4407 TCGv msr = tcg_temp_new(); 4408 4409 /* 4410 * XXX: we need to update nip before the store if we enter 4411 * power saving mode, we will exit the loop directly from 4412 * ppc_store_msr 4413 */ 4414 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4415 gen_io_start(); 4416 } 4417 gen_update_nip(ctx, ctx->base.pc_next); 4418 #if defined(TARGET_PPC64) 4419 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4420 #else 4421 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4422 #endif 4423 gen_helper_store_msr(cpu_env, msr); 4424 tcg_temp_free(msr); 4425 /* Must stop the translation as machine state (may have) changed */ 4426 /* Note that mtmsr is not always defined as context-synchronizing */ 4427 gen_stop_exception(ctx); 4428 } 4429 #endif 4430 } 4431 4432 /* mtspr */ 4433 static void gen_mtspr(DisasContext *ctx) 4434 { 4435 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4436 uint32_t sprn = SPR(ctx->opcode); 4437 4438 #if defined(CONFIG_USER_ONLY) 4439 write_cb = ctx->spr_cb[sprn].uea_write; 4440 #else 4441 if (ctx->pr) { 4442 write_cb = ctx->spr_cb[sprn].uea_write; 4443 } else if (ctx->hv) { 4444 write_cb = ctx->spr_cb[sprn].hea_write; 4445 } else { 4446 write_cb = ctx->spr_cb[sprn].oea_write; 4447 } 4448 #endif 4449 if (likely(write_cb != NULL)) { 4450 if (likely(write_cb != SPR_NOACCESS)) { 4451 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4452 } else { 4453 /* Privilege exception */ 4454 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4455 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4456 ctx->base.pc_next - 4); 4457 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4458 } 4459 } else { 4460 /* ISA 2.07 defines these as no-ops */ 4461 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4462 (sprn >= 808 && sprn <= 811)) { 4463 /* This is a nop */ 4464 return; 4465 } 4466 4467 /* Not defined */ 4468 qemu_log_mask(LOG_GUEST_ERROR, 4469 "Trying to write invalid spr %d (0x%03x) at " 4470 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4471 4472 4473 /* 4474 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4475 * generate a priv, a hv emu or a no-op 4476 */ 4477 if (sprn & 0x10) { 4478 if (ctx->pr) { 4479 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4480 } 4481 } else { 4482 if (ctx->pr || sprn == 0) { 4483 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4484 } 4485 } 4486 } 4487 } 4488 4489 #if defined(TARGET_PPC64) 4490 /* setb */ 4491 static void gen_setb(DisasContext *ctx) 4492 { 4493 TCGv_i32 t0 = tcg_temp_new_i32(); 4494 TCGv_i32 t8 = tcg_temp_new_i32(); 4495 TCGv_i32 tm1 = tcg_temp_new_i32(); 4496 int crf = crfS(ctx->opcode); 4497 4498 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4499 tcg_gen_movi_i32(t8, 8); 4500 tcg_gen_movi_i32(tm1, -1); 4501 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4502 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4503 4504 tcg_temp_free_i32(t0); 4505 tcg_temp_free_i32(t8); 4506 tcg_temp_free_i32(tm1); 4507 } 4508 #endif 4509 4510 /*** Cache management ***/ 4511 4512 /* dcbf */ 4513 static void gen_dcbf(DisasContext *ctx) 4514 { 4515 /* XXX: specification says this is treated as a load by the MMU */ 4516 TCGv t0; 4517 gen_set_access_type(ctx, ACCESS_CACHE); 4518 t0 = tcg_temp_new(); 4519 gen_addr_reg_index(ctx, t0); 4520 gen_qemu_ld8u(ctx, t0, t0); 4521 tcg_temp_free(t0); 4522 } 4523 4524 /* dcbfep (external PID dcbf) */ 4525 static void gen_dcbfep(DisasContext *ctx) 4526 { 4527 /* XXX: specification says this is treated as a load by the MMU */ 4528 TCGv t0; 4529 CHK_SV; 4530 gen_set_access_type(ctx, ACCESS_CACHE); 4531 t0 = tcg_temp_new(); 4532 gen_addr_reg_index(ctx, t0); 4533 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4534 tcg_temp_free(t0); 4535 } 4536 4537 /* dcbi (Supervisor only) */ 4538 static void gen_dcbi(DisasContext *ctx) 4539 { 4540 #if defined(CONFIG_USER_ONLY) 4541 GEN_PRIV; 4542 #else 4543 TCGv EA, val; 4544 4545 CHK_SV; 4546 EA = tcg_temp_new(); 4547 gen_set_access_type(ctx, ACCESS_CACHE); 4548 gen_addr_reg_index(ctx, EA); 4549 val = tcg_temp_new(); 4550 /* XXX: specification says this should be treated as a store by the MMU */ 4551 gen_qemu_ld8u(ctx, val, EA); 4552 gen_qemu_st8(ctx, val, EA); 4553 tcg_temp_free(val); 4554 tcg_temp_free(EA); 4555 #endif /* defined(CONFIG_USER_ONLY) */ 4556 } 4557 4558 /* dcdst */ 4559 static void gen_dcbst(DisasContext *ctx) 4560 { 4561 /* XXX: specification say this is treated as a load by the MMU */ 4562 TCGv t0; 4563 gen_set_access_type(ctx, ACCESS_CACHE); 4564 t0 = tcg_temp_new(); 4565 gen_addr_reg_index(ctx, t0); 4566 gen_qemu_ld8u(ctx, t0, t0); 4567 tcg_temp_free(t0); 4568 } 4569 4570 /* dcbstep (dcbstep External PID version) */ 4571 static void gen_dcbstep(DisasContext *ctx) 4572 { 4573 /* XXX: specification say this is treated as a load by the MMU */ 4574 TCGv t0; 4575 gen_set_access_type(ctx, ACCESS_CACHE); 4576 t0 = tcg_temp_new(); 4577 gen_addr_reg_index(ctx, t0); 4578 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4579 tcg_temp_free(t0); 4580 } 4581 4582 /* dcbt */ 4583 static void gen_dcbt(DisasContext *ctx) 4584 { 4585 /* 4586 * interpreted as no-op 4587 * XXX: specification say this is treated as a load by the MMU but 4588 * does not generate any exception 4589 */ 4590 } 4591 4592 /* dcbtep */ 4593 static void gen_dcbtep(DisasContext *ctx) 4594 { 4595 /* 4596 * interpreted as no-op 4597 * XXX: specification say this is treated as a load by the MMU but 4598 * does not generate any exception 4599 */ 4600 } 4601 4602 /* dcbtst */ 4603 static void gen_dcbtst(DisasContext *ctx) 4604 { 4605 /* 4606 * interpreted as no-op 4607 * XXX: specification say this is treated as a load by the MMU but 4608 * does not generate any exception 4609 */ 4610 } 4611 4612 /* dcbtstep */ 4613 static void gen_dcbtstep(DisasContext *ctx) 4614 { 4615 /* 4616 * interpreted as no-op 4617 * XXX: specification say this is treated as a load by the MMU but 4618 * does not generate any exception 4619 */ 4620 } 4621 4622 /* dcbtls */ 4623 static void gen_dcbtls(DisasContext *ctx) 4624 { 4625 /* Always fails locking the cache */ 4626 TCGv t0 = tcg_temp_new(); 4627 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4628 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4629 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4630 tcg_temp_free(t0); 4631 } 4632 4633 /* dcbz */ 4634 static void gen_dcbz(DisasContext *ctx) 4635 { 4636 TCGv tcgv_addr; 4637 TCGv_i32 tcgv_op; 4638 4639 gen_set_access_type(ctx, ACCESS_CACHE); 4640 tcgv_addr = tcg_temp_new(); 4641 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4642 gen_addr_reg_index(ctx, tcgv_addr); 4643 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4644 tcg_temp_free(tcgv_addr); 4645 tcg_temp_free_i32(tcgv_op); 4646 } 4647 4648 /* dcbzep */ 4649 static void gen_dcbzep(DisasContext *ctx) 4650 { 4651 TCGv tcgv_addr; 4652 TCGv_i32 tcgv_op; 4653 4654 gen_set_access_type(ctx, ACCESS_CACHE); 4655 tcgv_addr = tcg_temp_new(); 4656 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4657 gen_addr_reg_index(ctx, tcgv_addr); 4658 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 4659 tcg_temp_free(tcgv_addr); 4660 tcg_temp_free_i32(tcgv_op); 4661 } 4662 4663 /* dst / dstt */ 4664 static void gen_dst(DisasContext *ctx) 4665 { 4666 if (rA(ctx->opcode) == 0) { 4667 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4668 } else { 4669 /* interpreted as no-op */ 4670 } 4671 } 4672 4673 /* dstst /dststt */ 4674 static void gen_dstst(DisasContext *ctx) 4675 { 4676 if (rA(ctx->opcode) == 0) { 4677 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4678 } else { 4679 /* interpreted as no-op */ 4680 } 4681 4682 } 4683 4684 /* dss / dssall */ 4685 static void gen_dss(DisasContext *ctx) 4686 { 4687 /* interpreted as no-op */ 4688 } 4689 4690 /* icbi */ 4691 static void gen_icbi(DisasContext *ctx) 4692 { 4693 TCGv t0; 4694 gen_set_access_type(ctx, ACCESS_CACHE); 4695 t0 = tcg_temp_new(); 4696 gen_addr_reg_index(ctx, t0); 4697 gen_helper_icbi(cpu_env, t0); 4698 tcg_temp_free(t0); 4699 } 4700 4701 /* icbiep */ 4702 static void gen_icbiep(DisasContext *ctx) 4703 { 4704 TCGv t0; 4705 gen_set_access_type(ctx, ACCESS_CACHE); 4706 t0 = tcg_temp_new(); 4707 gen_addr_reg_index(ctx, t0); 4708 gen_helper_icbiep(cpu_env, t0); 4709 tcg_temp_free(t0); 4710 } 4711 4712 /* Optional: */ 4713 /* dcba */ 4714 static void gen_dcba(DisasContext *ctx) 4715 { 4716 /* 4717 * interpreted as no-op 4718 * XXX: specification say this is treated as a store by the MMU 4719 * but does not generate any exception 4720 */ 4721 } 4722 4723 /*** Segment register manipulation ***/ 4724 /* Supervisor only: */ 4725 4726 /* mfsr */ 4727 static void gen_mfsr(DisasContext *ctx) 4728 { 4729 #if defined(CONFIG_USER_ONLY) 4730 GEN_PRIV; 4731 #else 4732 TCGv t0; 4733 4734 CHK_SV; 4735 t0 = tcg_const_tl(SR(ctx->opcode)); 4736 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4737 tcg_temp_free(t0); 4738 #endif /* defined(CONFIG_USER_ONLY) */ 4739 } 4740 4741 /* mfsrin */ 4742 static void gen_mfsrin(DisasContext *ctx) 4743 { 4744 #if defined(CONFIG_USER_ONLY) 4745 GEN_PRIV; 4746 #else 4747 TCGv t0; 4748 4749 CHK_SV; 4750 t0 = tcg_temp_new(); 4751 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4752 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4753 tcg_temp_free(t0); 4754 #endif /* defined(CONFIG_USER_ONLY) */ 4755 } 4756 4757 /* mtsr */ 4758 static void gen_mtsr(DisasContext *ctx) 4759 { 4760 #if defined(CONFIG_USER_ONLY) 4761 GEN_PRIV; 4762 #else 4763 TCGv t0; 4764 4765 CHK_SV; 4766 t0 = tcg_const_tl(SR(ctx->opcode)); 4767 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4768 tcg_temp_free(t0); 4769 #endif /* defined(CONFIG_USER_ONLY) */ 4770 } 4771 4772 /* mtsrin */ 4773 static void gen_mtsrin(DisasContext *ctx) 4774 { 4775 #if defined(CONFIG_USER_ONLY) 4776 GEN_PRIV; 4777 #else 4778 TCGv t0; 4779 CHK_SV; 4780 4781 t0 = tcg_temp_new(); 4782 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4783 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4784 tcg_temp_free(t0); 4785 #endif /* defined(CONFIG_USER_ONLY) */ 4786 } 4787 4788 #if defined(TARGET_PPC64) 4789 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4790 4791 /* mfsr */ 4792 static void gen_mfsr_64b(DisasContext *ctx) 4793 { 4794 #if defined(CONFIG_USER_ONLY) 4795 GEN_PRIV; 4796 #else 4797 TCGv t0; 4798 4799 CHK_SV; 4800 t0 = tcg_const_tl(SR(ctx->opcode)); 4801 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4802 tcg_temp_free(t0); 4803 #endif /* defined(CONFIG_USER_ONLY) */ 4804 } 4805 4806 /* mfsrin */ 4807 static void gen_mfsrin_64b(DisasContext *ctx) 4808 { 4809 #if defined(CONFIG_USER_ONLY) 4810 GEN_PRIV; 4811 #else 4812 TCGv t0; 4813 4814 CHK_SV; 4815 t0 = tcg_temp_new(); 4816 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4817 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4818 tcg_temp_free(t0); 4819 #endif /* defined(CONFIG_USER_ONLY) */ 4820 } 4821 4822 /* mtsr */ 4823 static void gen_mtsr_64b(DisasContext *ctx) 4824 { 4825 #if defined(CONFIG_USER_ONLY) 4826 GEN_PRIV; 4827 #else 4828 TCGv t0; 4829 4830 CHK_SV; 4831 t0 = tcg_const_tl(SR(ctx->opcode)); 4832 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4833 tcg_temp_free(t0); 4834 #endif /* defined(CONFIG_USER_ONLY) */ 4835 } 4836 4837 /* mtsrin */ 4838 static void gen_mtsrin_64b(DisasContext *ctx) 4839 { 4840 #if defined(CONFIG_USER_ONLY) 4841 GEN_PRIV; 4842 #else 4843 TCGv t0; 4844 4845 CHK_SV; 4846 t0 = tcg_temp_new(); 4847 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4848 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4849 tcg_temp_free(t0); 4850 #endif /* defined(CONFIG_USER_ONLY) */ 4851 } 4852 4853 /* slbmte */ 4854 static void gen_slbmte(DisasContext *ctx) 4855 { 4856 #if defined(CONFIG_USER_ONLY) 4857 GEN_PRIV; 4858 #else 4859 CHK_SV; 4860 4861 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4862 cpu_gpr[rS(ctx->opcode)]); 4863 #endif /* defined(CONFIG_USER_ONLY) */ 4864 } 4865 4866 static void gen_slbmfee(DisasContext *ctx) 4867 { 4868 #if defined(CONFIG_USER_ONLY) 4869 GEN_PRIV; 4870 #else 4871 CHK_SV; 4872 4873 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4874 cpu_gpr[rB(ctx->opcode)]); 4875 #endif /* defined(CONFIG_USER_ONLY) */ 4876 } 4877 4878 static void gen_slbmfev(DisasContext *ctx) 4879 { 4880 #if defined(CONFIG_USER_ONLY) 4881 GEN_PRIV; 4882 #else 4883 CHK_SV; 4884 4885 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4886 cpu_gpr[rB(ctx->opcode)]); 4887 #endif /* defined(CONFIG_USER_ONLY) */ 4888 } 4889 4890 static void gen_slbfee_(DisasContext *ctx) 4891 { 4892 #if defined(CONFIG_USER_ONLY) 4893 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4894 #else 4895 TCGLabel *l1, *l2; 4896 4897 if (unlikely(ctx->pr)) { 4898 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4899 return; 4900 } 4901 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4902 cpu_gpr[rB(ctx->opcode)]); 4903 l1 = gen_new_label(); 4904 l2 = gen_new_label(); 4905 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4906 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4907 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4908 tcg_gen_br(l2); 4909 gen_set_label(l1); 4910 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4911 gen_set_label(l2); 4912 #endif 4913 } 4914 #endif /* defined(TARGET_PPC64) */ 4915 4916 /*** Lookaside buffer management ***/ 4917 /* Optional & supervisor only: */ 4918 4919 /* tlbia */ 4920 static void gen_tlbia(DisasContext *ctx) 4921 { 4922 #if defined(CONFIG_USER_ONLY) 4923 GEN_PRIV; 4924 #else 4925 CHK_HV; 4926 4927 gen_helper_tlbia(cpu_env); 4928 #endif /* defined(CONFIG_USER_ONLY) */ 4929 } 4930 4931 /* tlbiel */ 4932 static void gen_tlbiel(DisasContext *ctx) 4933 { 4934 #if defined(CONFIG_USER_ONLY) 4935 GEN_PRIV; 4936 #else 4937 CHK_SV; 4938 4939 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4940 #endif /* defined(CONFIG_USER_ONLY) */ 4941 } 4942 4943 /* tlbie */ 4944 static void gen_tlbie(DisasContext *ctx) 4945 { 4946 #if defined(CONFIG_USER_ONLY) 4947 GEN_PRIV; 4948 #else 4949 TCGv_i32 t1; 4950 4951 if (ctx->gtse) { 4952 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 4953 } else { 4954 CHK_HV; /* Else hypervisor privileged */ 4955 } 4956 4957 if (NARROW_MODE(ctx)) { 4958 TCGv t0 = tcg_temp_new(); 4959 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4960 gen_helper_tlbie(cpu_env, t0); 4961 tcg_temp_free(t0); 4962 } else { 4963 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4964 } 4965 t1 = tcg_temp_new_i32(); 4966 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4967 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4968 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4969 tcg_temp_free_i32(t1); 4970 #endif /* defined(CONFIG_USER_ONLY) */ 4971 } 4972 4973 /* tlbsync */ 4974 static void gen_tlbsync(DisasContext *ctx) 4975 { 4976 #if defined(CONFIG_USER_ONLY) 4977 GEN_PRIV; 4978 #else 4979 4980 if (ctx->gtse) { 4981 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 4982 } else { 4983 CHK_HV; /* Else hypervisor privileged */ 4984 } 4985 4986 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4987 if (ctx->insns_flags & PPC_BOOKE) { 4988 gen_check_tlb_flush(ctx, true); 4989 } 4990 #endif /* defined(CONFIG_USER_ONLY) */ 4991 } 4992 4993 #if defined(TARGET_PPC64) 4994 /* slbia */ 4995 static void gen_slbia(DisasContext *ctx) 4996 { 4997 #if defined(CONFIG_USER_ONLY) 4998 GEN_PRIV; 4999 #else 5000 CHK_SV; 5001 5002 gen_helper_slbia(cpu_env); 5003 #endif /* defined(CONFIG_USER_ONLY) */ 5004 } 5005 5006 /* slbie */ 5007 static void gen_slbie(DisasContext *ctx) 5008 { 5009 #if defined(CONFIG_USER_ONLY) 5010 GEN_PRIV; 5011 #else 5012 CHK_SV; 5013 5014 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5015 #endif /* defined(CONFIG_USER_ONLY) */ 5016 } 5017 5018 /* slbieg */ 5019 static void gen_slbieg(DisasContext *ctx) 5020 { 5021 #if defined(CONFIG_USER_ONLY) 5022 GEN_PRIV; 5023 #else 5024 CHK_SV; 5025 5026 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5027 #endif /* defined(CONFIG_USER_ONLY) */ 5028 } 5029 5030 /* slbsync */ 5031 static void gen_slbsync(DisasContext *ctx) 5032 { 5033 #if defined(CONFIG_USER_ONLY) 5034 GEN_PRIV; 5035 #else 5036 CHK_SV; 5037 gen_check_tlb_flush(ctx, true); 5038 #endif /* defined(CONFIG_USER_ONLY) */ 5039 } 5040 5041 #endif /* defined(TARGET_PPC64) */ 5042 5043 /*** External control ***/ 5044 /* Optional: */ 5045 5046 /* eciwx */ 5047 static void gen_eciwx(DisasContext *ctx) 5048 { 5049 TCGv t0; 5050 /* Should check EAR[E] ! */ 5051 gen_set_access_type(ctx, ACCESS_EXT); 5052 t0 = tcg_temp_new(); 5053 gen_addr_reg_index(ctx, t0); 5054 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5055 DEF_MEMOP(MO_UL | MO_ALIGN)); 5056 tcg_temp_free(t0); 5057 } 5058 5059 /* ecowx */ 5060 static void gen_ecowx(DisasContext *ctx) 5061 { 5062 TCGv t0; 5063 /* Should check EAR[E] ! */ 5064 gen_set_access_type(ctx, ACCESS_EXT); 5065 t0 = tcg_temp_new(); 5066 gen_addr_reg_index(ctx, t0); 5067 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5068 DEF_MEMOP(MO_UL | MO_ALIGN)); 5069 tcg_temp_free(t0); 5070 } 5071 5072 /* PowerPC 601 specific instructions */ 5073 5074 /* abs - abs. */ 5075 static void gen_abs(DisasContext *ctx) 5076 { 5077 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5078 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5079 5080 tcg_gen_abs_tl(d, a); 5081 if (unlikely(Rc(ctx->opcode) != 0)) { 5082 gen_set_Rc0(ctx, d); 5083 } 5084 } 5085 5086 /* abso - abso. */ 5087 static void gen_abso(DisasContext *ctx) 5088 { 5089 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5090 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5091 5092 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5093 tcg_gen_abs_tl(d, a); 5094 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5095 if (unlikely(Rc(ctx->opcode) != 0)) { 5096 gen_set_Rc0(ctx, d); 5097 } 5098 } 5099 5100 /* clcs */ 5101 static void gen_clcs(DisasContext *ctx) 5102 { 5103 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5104 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5105 tcg_temp_free_i32(t0); 5106 /* Rc=1 sets CR0 to an undefined state */ 5107 } 5108 5109 /* div - div. */ 5110 static void gen_div(DisasContext *ctx) 5111 { 5112 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5113 cpu_gpr[rB(ctx->opcode)]); 5114 if (unlikely(Rc(ctx->opcode) != 0)) { 5115 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5116 } 5117 } 5118 5119 /* divo - divo. */ 5120 static void gen_divo(DisasContext *ctx) 5121 { 5122 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5123 cpu_gpr[rB(ctx->opcode)]); 5124 if (unlikely(Rc(ctx->opcode) != 0)) { 5125 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5126 } 5127 } 5128 5129 /* divs - divs. */ 5130 static void gen_divs(DisasContext *ctx) 5131 { 5132 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5133 cpu_gpr[rB(ctx->opcode)]); 5134 if (unlikely(Rc(ctx->opcode) != 0)) { 5135 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5136 } 5137 } 5138 5139 /* divso - divso. */ 5140 static void gen_divso(DisasContext *ctx) 5141 { 5142 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5143 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5144 if (unlikely(Rc(ctx->opcode) != 0)) { 5145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5146 } 5147 } 5148 5149 /* doz - doz. */ 5150 static void gen_doz(DisasContext *ctx) 5151 { 5152 TCGLabel *l1 = gen_new_label(); 5153 TCGLabel *l2 = gen_new_label(); 5154 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5155 cpu_gpr[rA(ctx->opcode)], l1); 5156 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5157 cpu_gpr[rA(ctx->opcode)]); 5158 tcg_gen_br(l2); 5159 gen_set_label(l1); 5160 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5161 gen_set_label(l2); 5162 if (unlikely(Rc(ctx->opcode) != 0)) { 5163 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5164 } 5165 } 5166 5167 /* dozo - dozo. */ 5168 static void gen_dozo(DisasContext *ctx) 5169 { 5170 TCGLabel *l1 = gen_new_label(); 5171 TCGLabel *l2 = gen_new_label(); 5172 TCGv t0 = tcg_temp_new(); 5173 TCGv t1 = tcg_temp_new(); 5174 TCGv t2 = tcg_temp_new(); 5175 /* Start with XER OV disabled, the most likely case */ 5176 tcg_gen_movi_tl(cpu_ov, 0); 5177 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5178 cpu_gpr[rA(ctx->opcode)], l1); 5179 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5180 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5181 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5182 tcg_gen_andc_tl(t1, t1, t2); 5183 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5184 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5185 tcg_gen_movi_tl(cpu_ov, 1); 5186 tcg_gen_movi_tl(cpu_so, 1); 5187 tcg_gen_br(l2); 5188 gen_set_label(l1); 5189 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5190 gen_set_label(l2); 5191 tcg_temp_free(t0); 5192 tcg_temp_free(t1); 5193 tcg_temp_free(t2); 5194 if (unlikely(Rc(ctx->opcode) != 0)) { 5195 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5196 } 5197 } 5198 5199 /* dozi */ 5200 static void gen_dozi(DisasContext *ctx) 5201 { 5202 target_long simm = SIMM(ctx->opcode); 5203 TCGLabel *l1 = gen_new_label(); 5204 TCGLabel *l2 = gen_new_label(); 5205 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5206 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5207 tcg_gen_br(l2); 5208 gen_set_label(l1); 5209 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5210 gen_set_label(l2); 5211 if (unlikely(Rc(ctx->opcode) != 0)) { 5212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5213 } 5214 } 5215 5216 /* lscbx - lscbx. */ 5217 static void gen_lscbx(DisasContext *ctx) 5218 { 5219 TCGv t0 = tcg_temp_new(); 5220 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5221 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5222 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5223 5224 gen_addr_reg_index(ctx, t0); 5225 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5226 tcg_temp_free_i32(t1); 5227 tcg_temp_free_i32(t2); 5228 tcg_temp_free_i32(t3); 5229 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5230 tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5231 if (unlikely(Rc(ctx->opcode) != 0)) { 5232 gen_set_Rc0(ctx, t0); 5233 } 5234 tcg_temp_free(t0); 5235 } 5236 5237 /* maskg - maskg. */ 5238 static void gen_maskg(DisasContext *ctx) 5239 { 5240 TCGLabel *l1 = gen_new_label(); 5241 TCGv t0 = tcg_temp_new(); 5242 TCGv t1 = tcg_temp_new(); 5243 TCGv t2 = tcg_temp_new(); 5244 TCGv t3 = tcg_temp_new(); 5245 tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5246 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5247 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5248 tcg_gen_addi_tl(t2, t0, 1); 5249 tcg_gen_shr_tl(t2, t3, t2); 5250 tcg_gen_shr_tl(t3, t3, t1); 5251 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5252 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5253 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5254 gen_set_label(l1); 5255 tcg_temp_free(t0); 5256 tcg_temp_free(t1); 5257 tcg_temp_free(t2); 5258 tcg_temp_free(t3); 5259 if (unlikely(Rc(ctx->opcode) != 0)) { 5260 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5261 } 5262 } 5263 5264 /* maskir - maskir. */ 5265 static void gen_maskir(DisasContext *ctx) 5266 { 5267 TCGv t0 = tcg_temp_new(); 5268 TCGv t1 = tcg_temp_new(); 5269 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5270 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5271 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5272 tcg_temp_free(t0); 5273 tcg_temp_free(t1); 5274 if (unlikely(Rc(ctx->opcode) != 0)) { 5275 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5276 } 5277 } 5278 5279 /* mul - mul. */ 5280 static void gen_mul(DisasContext *ctx) 5281 { 5282 TCGv_i64 t0 = tcg_temp_new_i64(); 5283 TCGv_i64 t1 = tcg_temp_new_i64(); 5284 TCGv t2 = tcg_temp_new(); 5285 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5286 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5287 tcg_gen_mul_i64(t0, t0, t1); 5288 tcg_gen_trunc_i64_tl(t2, t0); 5289 gen_store_spr(SPR_MQ, t2); 5290 tcg_gen_shri_i64(t1, t0, 32); 5291 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5292 tcg_temp_free_i64(t0); 5293 tcg_temp_free_i64(t1); 5294 tcg_temp_free(t2); 5295 if (unlikely(Rc(ctx->opcode) != 0)) { 5296 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5297 } 5298 } 5299 5300 /* mulo - mulo. */ 5301 static void gen_mulo(DisasContext *ctx) 5302 { 5303 TCGLabel *l1 = gen_new_label(); 5304 TCGv_i64 t0 = tcg_temp_new_i64(); 5305 TCGv_i64 t1 = tcg_temp_new_i64(); 5306 TCGv t2 = tcg_temp_new(); 5307 /* Start with XER OV disabled, the most likely case */ 5308 tcg_gen_movi_tl(cpu_ov, 0); 5309 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5310 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5311 tcg_gen_mul_i64(t0, t0, t1); 5312 tcg_gen_trunc_i64_tl(t2, t0); 5313 gen_store_spr(SPR_MQ, t2); 5314 tcg_gen_shri_i64(t1, t0, 32); 5315 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5316 tcg_gen_ext32s_i64(t1, t0); 5317 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5318 tcg_gen_movi_tl(cpu_ov, 1); 5319 tcg_gen_movi_tl(cpu_so, 1); 5320 gen_set_label(l1); 5321 tcg_temp_free_i64(t0); 5322 tcg_temp_free_i64(t1); 5323 tcg_temp_free(t2); 5324 if (unlikely(Rc(ctx->opcode) != 0)) { 5325 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5326 } 5327 } 5328 5329 /* nabs - nabs. */ 5330 static void gen_nabs(DisasContext *ctx) 5331 { 5332 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5333 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5334 5335 tcg_gen_abs_tl(d, a); 5336 tcg_gen_neg_tl(d, d); 5337 if (unlikely(Rc(ctx->opcode) != 0)) { 5338 gen_set_Rc0(ctx, d); 5339 } 5340 } 5341 5342 /* nabso - nabso. */ 5343 static void gen_nabso(DisasContext *ctx) 5344 { 5345 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5346 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5347 5348 tcg_gen_abs_tl(d, a); 5349 tcg_gen_neg_tl(d, d); 5350 /* nabs never overflows */ 5351 tcg_gen_movi_tl(cpu_ov, 0); 5352 if (unlikely(Rc(ctx->opcode) != 0)) { 5353 gen_set_Rc0(ctx, d); 5354 } 5355 } 5356 5357 /* rlmi - rlmi. */ 5358 static void gen_rlmi(DisasContext *ctx) 5359 { 5360 uint32_t mb = MB(ctx->opcode); 5361 uint32_t me = ME(ctx->opcode); 5362 TCGv t0 = tcg_temp_new(); 5363 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5364 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5365 tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5366 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5367 ~MASK(mb, me)); 5368 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5369 tcg_temp_free(t0); 5370 if (unlikely(Rc(ctx->opcode) != 0)) { 5371 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5372 } 5373 } 5374 5375 /* rrib - rrib. */ 5376 static void gen_rrib(DisasContext *ctx) 5377 { 5378 TCGv t0 = tcg_temp_new(); 5379 TCGv t1 = tcg_temp_new(); 5380 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5381 tcg_gen_movi_tl(t1, 0x80000000); 5382 tcg_gen_shr_tl(t1, t1, t0); 5383 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5384 tcg_gen_and_tl(t0, t0, t1); 5385 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5386 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5387 tcg_temp_free(t0); 5388 tcg_temp_free(t1); 5389 if (unlikely(Rc(ctx->opcode) != 0)) { 5390 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5391 } 5392 } 5393 5394 /* sle - sle. */ 5395 static void gen_sle(DisasContext *ctx) 5396 { 5397 TCGv t0 = tcg_temp_new(); 5398 TCGv t1 = tcg_temp_new(); 5399 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5400 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5401 tcg_gen_subfi_tl(t1, 32, t1); 5402 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5403 tcg_gen_or_tl(t1, t0, t1); 5404 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5405 gen_store_spr(SPR_MQ, t1); 5406 tcg_temp_free(t0); 5407 tcg_temp_free(t1); 5408 if (unlikely(Rc(ctx->opcode) != 0)) { 5409 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5410 } 5411 } 5412 5413 /* sleq - sleq. */ 5414 static void gen_sleq(DisasContext *ctx) 5415 { 5416 TCGv t0 = tcg_temp_new(); 5417 TCGv t1 = tcg_temp_new(); 5418 TCGv t2 = tcg_temp_new(); 5419 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5420 tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5421 tcg_gen_shl_tl(t2, t2, t0); 5422 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5423 gen_load_spr(t1, SPR_MQ); 5424 gen_store_spr(SPR_MQ, t0); 5425 tcg_gen_and_tl(t0, t0, t2); 5426 tcg_gen_andc_tl(t1, t1, t2); 5427 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5428 tcg_temp_free(t0); 5429 tcg_temp_free(t1); 5430 tcg_temp_free(t2); 5431 if (unlikely(Rc(ctx->opcode) != 0)) { 5432 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5433 } 5434 } 5435 5436 /* sliq - sliq. */ 5437 static void gen_sliq(DisasContext *ctx) 5438 { 5439 int sh = SH(ctx->opcode); 5440 TCGv t0 = tcg_temp_new(); 5441 TCGv t1 = tcg_temp_new(); 5442 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5443 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5444 tcg_gen_or_tl(t1, t0, t1); 5445 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5446 gen_store_spr(SPR_MQ, t1); 5447 tcg_temp_free(t0); 5448 tcg_temp_free(t1); 5449 if (unlikely(Rc(ctx->opcode) != 0)) { 5450 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5451 } 5452 } 5453 5454 /* slliq - slliq. */ 5455 static void gen_slliq(DisasContext *ctx) 5456 { 5457 int sh = SH(ctx->opcode); 5458 TCGv t0 = tcg_temp_new(); 5459 TCGv t1 = tcg_temp_new(); 5460 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5461 gen_load_spr(t1, SPR_MQ); 5462 gen_store_spr(SPR_MQ, t0); 5463 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5464 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5465 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5466 tcg_temp_free(t0); 5467 tcg_temp_free(t1); 5468 if (unlikely(Rc(ctx->opcode) != 0)) { 5469 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5470 } 5471 } 5472 5473 /* sllq - sllq. */ 5474 static void gen_sllq(DisasContext *ctx) 5475 { 5476 TCGLabel *l1 = gen_new_label(); 5477 TCGLabel *l2 = gen_new_label(); 5478 TCGv t0 = tcg_temp_local_new(); 5479 TCGv t1 = tcg_temp_local_new(); 5480 TCGv t2 = tcg_temp_local_new(); 5481 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5482 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5483 tcg_gen_shl_tl(t1, t1, t2); 5484 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5485 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5486 gen_load_spr(t0, SPR_MQ); 5487 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5488 tcg_gen_br(l2); 5489 gen_set_label(l1); 5490 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5491 gen_load_spr(t2, SPR_MQ); 5492 tcg_gen_andc_tl(t1, t2, t1); 5493 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5494 gen_set_label(l2); 5495 tcg_temp_free(t0); 5496 tcg_temp_free(t1); 5497 tcg_temp_free(t2); 5498 if (unlikely(Rc(ctx->opcode) != 0)) { 5499 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5500 } 5501 } 5502 5503 /* slq - slq. */ 5504 static void gen_slq(DisasContext *ctx) 5505 { 5506 TCGLabel *l1 = gen_new_label(); 5507 TCGv t0 = tcg_temp_new(); 5508 TCGv t1 = tcg_temp_new(); 5509 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5510 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5511 tcg_gen_subfi_tl(t1, 32, t1); 5512 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5513 tcg_gen_or_tl(t1, t0, t1); 5514 gen_store_spr(SPR_MQ, t1); 5515 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5516 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5517 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5518 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5519 gen_set_label(l1); 5520 tcg_temp_free(t0); 5521 tcg_temp_free(t1); 5522 if (unlikely(Rc(ctx->opcode) != 0)) { 5523 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5524 } 5525 } 5526 5527 /* sraiq - sraiq. */ 5528 static void gen_sraiq(DisasContext *ctx) 5529 { 5530 int sh = SH(ctx->opcode); 5531 TCGLabel *l1 = gen_new_label(); 5532 TCGv t0 = tcg_temp_new(); 5533 TCGv t1 = tcg_temp_new(); 5534 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5535 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5536 tcg_gen_or_tl(t0, t0, t1); 5537 gen_store_spr(SPR_MQ, t0); 5538 tcg_gen_movi_tl(cpu_ca, 0); 5539 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5540 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5541 tcg_gen_movi_tl(cpu_ca, 1); 5542 gen_set_label(l1); 5543 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5544 tcg_temp_free(t0); 5545 tcg_temp_free(t1); 5546 if (unlikely(Rc(ctx->opcode) != 0)) { 5547 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5548 } 5549 } 5550 5551 /* sraq - sraq. */ 5552 static void gen_sraq(DisasContext *ctx) 5553 { 5554 TCGLabel *l1 = gen_new_label(); 5555 TCGLabel *l2 = gen_new_label(); 5556 TCGv t0 = tcg_temp_new(); 5557 TCGv t1 = tcg_temp_local_new(); 5558 TCGv t2 = tcg_temp_local_new(); 5559 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5560 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5561 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5562 tcg_gen_subfi_tl(t2, 32, t2); 5563 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5564 tcg_gen_or_tl(t0, t0, t2); 5565 gen_store_spr(SPR_MQ, t0); 5566 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5567 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5568 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5569 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5570 gen_set_label(l1); 5571 tcg_temp_free(t0); 5572 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5573 tcg_gen_movi_tl(cpu_ca, 0); 5574 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5575 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5576 tcg_gen_movi_tl(cpu_ca, 1); 5577 gen_set_label(l2); 5578 tcg_temp_free(t1); 5579 tcg_temp_free(t2); 5580 if (unlikely(Rc(ctx->opcode) != 0)) { 5581 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5582 } 5583 } 5584 5585 /* sre - sre. */ 5586 static void gen_sre(DisasContext *ctx) 5587 { 5588 TCGv t0 = tcg_temp_new(); 5589 TCGv t1 = tcg_temp_new(); 5590 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5591 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5592 tcg_gen_subfi_tl(t1, 32, t1); 5593 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5594 tcg_gen_or_tl(t1, t0, t1); 5595 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5596 gen_store_spr(SPR_MQ, t1); 5597 tcg_temp_free(t0); 5598 tcg_temp_free(t1); 5599 if (unlikely(Rc(ctx->opcode) != 0)) { 5600 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5601 } 5602 } 5603 5604 /* srea - srea. */ 5605 static void gen_srea(DisasContext *ctx) 5606 { 5607 TCGv t0 = tcg_temp_new(); 5608 TCGv t1 = tcg_temp_new(); 5609 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5610 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5611 gen_store_spr(SPR_MQ, t0); 5612 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5613 tcg_temp_free(t0); 5614 tcg_temp_free(t1); 5615 if (unlikely(Rc(ctx->opcode) != 0)) { 5616 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5617 } 5618 } 5619 5620 /* sreq */ 5621 static void gen_sreq(DisasContext *ctx) 5622 { 5623 TCGv t0 = tcg_temp_new(); 5624 TCGv t1 = tcg_temp_new(); 5625 TCGv t2 = tcg_temp_new(); 5626 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5627 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5628 tcg_gen_shr_tl(t1, t1, t0); 5629 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5630 gen_load_spr(t2, SPR_MQ); 5631 gen_store_spr(SPR_MQ, t0); 5632 tcg_gen_and_tl(t0, t0, t1); 5633 tcg_gen_andc_tl(t2, t2, t1); 5634 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5635 tcg_temp_free(t0); 5636 tcg_temp_free(t1); 5637 tcg_temp_free(t2); 5638 if (unlikely(Rc(ctx->opcode) != 0)) { 5639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5640 } 5641 } 5642 5643 /* sriq */ 5644 static void gen_sriq(DisasContext *ctx) 5645 { 5646 int sh = SH(ctx->opcode); 5647 TCGv t0 = tcg_temp_new(); 5648 TCGv t1 = tcg_temp_new(); 5649 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5650 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5651 tcg_gen_or_tl(t1, t0, t1); 5652 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5653 gen_store_spr(SPR_MQ, t1); 5654 tcg_temp_free(t0); 5655 tcg_temp_free(t1); 5656 if (unlikely(Rc(ctx->opcode) != 0)) { 5657 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5658 } 5659 } 5660 5661 /* srliq */ 5662 static void gen_srliq(DisasContext *ctx) 5663 { 5664 int sh = SH(ctx->opcode); 5665 TCGv t0 = tcg_temp_new(); 5666 TCGv t1 = tcg_temp_new(); 5667 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5668 gen_load_spr(t1, SPR_MQ); 5669 gen_store_spr(SPR_MQ, t0); 5670 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5671 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5672 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5673 tcg_temp_free(t0); 5674 tcg_temp_free(t1); 5675 if (unlikely(Rc(ctx->opcode) != 0)) { 5676 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5677 } 5678 } 5679 5680 /* srlq */ 5681 static void gen_srlq(DisasContext *ctx) 5682 { 5683 TCGLabel *l1 = gen_new_label(); 5684 TCGLabel *l2 = gen_new_label(); 5685 TCGv t0 = tcg_temp_local_new(); 5686 TCGv t1 = tcg_temp_local_new(); 5687 TCGv t2 = tcg_temp_local_new(); 5688 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5689 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5690 tcg_gen_shr_tl(t2, t1, t2); 5691 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5692 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5693 gen_load_spr(t0, SPR_MQ); 5694 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5695 tcg_gen_br(l2); 5696 gen_set_label(l1); 5697 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5698 tcg_gen_and_tl(t0, t0, t2); 5699 gen_load_spr(t1, SPR_MQ); 5700 tcg_gen_andc_tl(t1, t1, t2); 5701 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5702 gen_set_label(l2); 5703 tcg_temp_free(t0); 5704 tcg_temp_free(t1); 5705 tcg_temp_free(t2); 5706 if (unlikely(Rc(ctx->opcode) != 0)) { 5707 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5708 } 5709 } 5710 5711 /* srq */ 5712 static void gen_srq(DisasContext *ctx) 5713 { 5714 TCGLabel *l1 = gen_new_label(); 5715 TCGv t0 = tcg_temp_new(); 5716 TCGv t1 = tcg_temp_new(); 5717 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5718 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5719 tcg_gen_subfi_tl(t1, 32, t1); 5720 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5721 tcg_gen_or_tl(t1, t0, t1); 5722 gen_store_spr(SPR_MQ, t1); 5723 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5724 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5725 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5726 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5727 gen_set_label(l1); 5728 tcg_temp_free(t0); 5729 tcg_temp_free(t1); 5730 if (unlikely(Rc(ctx->opcode) != 0)) { 5731 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5732 } 5733 } 5734 5735 /* PowerPC 602 specific instructions */ 5736 5737 /* dsa */ 5738 static void gen_dsa(DisasContext *ctx) 5739 { 5740 /* XXX: TODO */ 5741 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5742 } 5743 5744 /* esa */ 5745 static void gen_esa(DisasContext *ctx) 5746 { 5747 /* XXX: TODO */ 5748 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5749 } 5750 5751 /* mfrom */ 5752 static void gen_mfrom(DisasContext *ctx) 5753 { 5754 #if defined(CONFIG_USER_ONLY) 5755 GEN_PRIV; 5756 #else 5757 CHK_SV; 5758 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5759 #endif /* defined(CONFIG_USER_ONLY) */ 5760 } 5761 5762 /* 602 - 603 - G2 TLB management */ 5763 5764 /* tlbld */ 5765 static void gen_tlbld_6xx(DisasContext *ctx) 5766 { 5767 #if defined(CONFIG_USER_ONLY) 5768 GEN_PRIV; 5769 #else 5770 CHK_SV; 5771 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5772 #endif /* defined(CONFIG_USER_ONLY) */ 5773 } 5774 5775 /* tlbli */ 5776 static void gen_tlbli_6xx(DisasContext *ctx) 5777 { 5778 #if defined(CONFIG_USER_ONLY) 5779 GEN_PRIV; 5780 #else 5781 CHK_SV; 5782 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5783 #endif /* defined(CONFIG_USER_ONLY) */ 5784 } 5785 5786 /* 74xx TLB management */ 5787 5788 /* tlbld */ 5789 static void gen_tlbld_74xx(DisasContext *ctx) 5790 { 5791 #if defined(CONFIG_USER_ONLY) 5792 GEN_PRIV; 5793 #else 5794 CHK_SV; 5795 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5796 #endif /* defined(CONFIG_USER_ONLY) */ 5797 } 5798 5799 /* tlbli */ 5800 static void gen_tlbli_74xx(DisasContext *ctx) 5801 { 5802 #if defined(CONFIG_USER_ONLY) 5803 GEN_PRIV; 5804 #else 5805 CHK_SV; 5806 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5807 #endif /* defined(CONFIG_USER_ONLY) */ 5808 } 5809 5810 /* POWER instructions not in PowerPC 601 */ 5811 5812 /* clf */ 5813 static void gen_clf(DisasContext *ctx) 5814 { 5815 /* Cache line flush: implemented as no-op */ 5816 } 5817 5818 /* cli */ 5819 static void gen_cli(DisasContext *ctx) 5820 { 5821 #if defined(CONFIG_USER_ONLY) 5822 GEN_PRIV; 5823 #else 5824 /* Cache line invalidate: privileged and treated as no-op */ 5825 CHK_SV; 5826 #endif /* defined(CONFIG_USER_ONLY) */ 5827 } 5828 5829 /* dclst */ 5830 static void gen_dclst(DisasContext *ctx) 5831 { 5832 /* Data cache line store: treated as no-op */ 5833 } 5834 5835 static void gen_mfsri(DisasContext *ctx) 5836 { 5837 #if defined(CONFIG_USER_ONLY) 5838 GEN_PRIV; 5839 #else 5840 int ra = rA(ctx->opcode); 5841 int rd = rD(ctx->opcode); 5842 TCGv t0; 5843 5844 CHK_SV; 5845 t0 = tcg_temp_new(); 5846 gen_addr_reg_index(ctx, t0); 5847 tcg_gen_extract_tl(t0, t0, 28, 4); 5848 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5849 tcg_temp_free(t0); 5850 if (ra != 0 && ra != rd) { 5851 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5852 } 5853 #endif /* defined(CONFIG_USER_ONLY) */ 5854 } 5855 5856 static void gen_rac(DisasContext *ctx) 5857 { 5858 #if defined(CONFIG_USER_ONLY) 5859 GEN_PRIV; 5860 #else 5861 TCGv t0; 5862 5863 CHK_SV; 5864 t0 = tcg_temp_new(); 5865 gen_addr_reg_index(ctx, t0); 5866 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5867 tcg_temp_free(t0); 5868 #endif /* defined(CONFIG_USER_ONLY) */ 5869 } 5870 5871 static void gen_rfsvc(DisasContext *ctx) 5872 { 5873 #if defined(CONFIG_USER_ONLY) 5874 GEN_PRIV; 5875 #else 5876 CHK_SV; 5877 5878 gen_helper_rfsvc(cpu_env); 5879 gen_sync_exception(ctx); 5880 #endif /* defined(CONFIG_USER_ONLY) */ 5881 } 5882 5883 /* svc is not implemented for now */ 5884 5885 /* BookE specific instructions */ 5886 5887 /* XXX: not implemented on 440 ? */ 5888 static void gen_mfapidi(DisasContext *ctx) 5889 { 5890 /* XXX: TODO */ 5891 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5892 } 5893 5894 /* XXX: not implemented on 440 ? */ 5895 static void gen_tlbiva(DisasContext *ctx) 5896 { 5897 #if defined(CONFIG_USER_ONLY) 5898 GEN_PRIV; 5899 #else 5900 TCGv t0; 5901 5902 CHK_SV; 5903 t0 = tcg_temp_new(); 5904 gen_addr_reg_index(ctx, t0); 5905 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5906 tcg_temp_free(t0); 5907 #endif /* defined(CONFIG_USER_ONLY) */ 5908 } 5909 5910 /* All 405 MAC instructions are translated here */ 5911 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5912 int ra, int rb, int rt, int Rc) 5913 { 5914 TCGv t0, t1; 5915 5916 t0 = tcg_temp_local_new(); 5917 t1 = tcg_temp_local_new(); 5918 5919 switch (opc3 & 0x0D) { 5920 case 0x05: 5921 /* macchw - macchw. - macchwo - macchwo. */ 5922 /* macchws - macchws. - macchwso - macchwso. */ 5923 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5924 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5925 /* mulchw - mulchw. */ 5926 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5927 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5928 tcg_gen_ext16s_tl(t1, t1); 5929 break; 5930 case 0x04: 5931 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5932 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5933 /* mulchwu - mulchwu. */ 5934 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5935 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5936 tcg_gen_ext16u_tl(t1, t1); 5937 break; 5938 case 0x01: 5939 /* machhw - machhw. - machhwo - machhwo. */ 5940 /* machhws - machhws. - machhwso - machhwso. */ 5941 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5942 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5943 /* mulhhw - mulhhw. */ 5944 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5945 tcg_gen_ext16s_tl(t0, t0); 5946 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5947 tcg_gen_ext16s_tl(t1, t1); 5948 break; 5949 case 0x00: 5950 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5951 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5952 /* mulhhwu - mulhhwu. */ 5953 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5954 tcg_gen_ext16u_tl(t0, t0); 5955 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5956 tcg_gen_ext16u_tl(t1, t1); 5957 break; 5958 case 0x0D: 5959 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5960 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5961 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5962 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5963 /* mullhw - mullhw. */ 5964 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5965 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5966 break; 5967 case 0x0C: 5968 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5969 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5970 /* mullhwu - mullhwu. */ 5971 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5972 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5973 break; 5974 } 5975 if (opc2 & 0x04) { 5976 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5977 tcg_gen_mul_tl(t1, t0, t1); 5978 if (opc2 & 0x02) { 5979 /* nmultiply-and-accumulate (0x0E) */ 5980 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5981 } else { 5982 /* multiply-and-accumulate (0x0C) */ 5983 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5984 } 5985 5986 if (opc3 & 0x12) { 5987 /* Check overflow and/or saturate */ 5988 TCGLabel *l1 = gen_new_label(); 5989 5990 if (opc3 & 0x10) { 5991 /* Start with XER OV disabled, the most likely case */ 5992 tcg_gen_movi_tl(cpu_ov, 0); 5993 } 5994 if (opc3 & 0x01) { 5995 /* Signed */ 5996 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5997 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5998 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5999 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6000 if (opc3 & 0x02) { 6001 /* Saturate */ 6002 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6003 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6004 } 6005 } else { 6006 /* Unsigned */ 6007 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6008 if (opc3 & 0x02) { 6009 /* Saturate */ 6010 tcg_gen_movi_tl(t0, UINT32_MAX); 6011 } 6012 } 6013 if (opc3 & 0x10) { 6014 /* Check overflow */ 6015 tcg_gen_movi_tl(cpu_ov, 1); 6016 tcg_gen_movi_tl(cpu_so, 1); 6017 } 6018 gen_set_label(l1); 6019 tcg_gen_mov_tl(cpu_gpr[rt], t0); 6020 } 6021 } else { 6022 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6023 } 6024 tcg_temp_free(t0); 6025 tcg_temp_free(t1); 6026 if (unlikely(Rc) != 0) { 6027 /* Update Rc0 */ 6028 gen_set_Rc0(ctx, cpu_gpr[rt]); 6029 } 6030 } 6031 6032 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6033 static void glue(gen_, name)(DisasContext *ctx) \ 6034 { \ 6035 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6036 rD(ctx->opcode), Rc(ctx->opcode)); \ 6037 } 6038 6039 /* macchw - macchw. */ 6040 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6041 /* macchwo - macchwo. */ 6042 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6043 /* macchws - macchws. */ 6044 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6045 /* macchwso - macchwso. */ 6046 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6047 /* macchwsu - macchwsu. */ 6048 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6049 /* macchwsuo - macchwsuo. */ 6050 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6051 /* macchwu - macchwu. */ 6052 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6053 /* macchwuo - macchwuo. */ 6054 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6055 /* machhw - machhw. */ 6056 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6057 /* machhwo - machhwo. */ 6058 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6059 /* machhws - machhws. */ 6060 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6061 /* machhwso - machhwso. */ 6062 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6063 /* machhwsu - machhwsu. */ 6064 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6065 /* machhwsuo - machhwsuo. */ 6066 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6067 /* machhwu - machhwu. */ 6068 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6069 /* machhwuo - machhwuo. */ 6070 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6071 /* maclhw - maclhw. */ 6072 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6073 /* maclhwo - maclhwo. */ 6074 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6075 /* maclhws - maclhws. */ 6076 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6077 /* maclhwso - maclhwso. */ 6078 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6079 /* maclhwu - maclhwu. */ 6080 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6081 /* maclhwuo - maclhwuo. */ 6082 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6083 /* maclhwsu - maclhwsu. */ 6084 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6085 /* maclhwsuo - maclhwsuo. */ 6086 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6087 /* nmacchw - nmacchw. */ 6088 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6089 /* nmacchwo - nmacchwo. */ 6090 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6091 /* nmacchws - nmacchws. */ 6092 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6093 /* nmacchwso - nmacchwso. */ 6094 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6095 /* nmachhw - nmachhw. */ 6096 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6097 /* nmachhwo - nmachhwo. */ 6098 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6099 /* nmachhws - nmachhws. */ 6100 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6101 /* nmachhwso - nmachhwso. */ 6102 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6103 /* nmaclhw - nmaclhw. */ 6104 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6105 /* nmaclhwo - nmaclhwo. */ 6106 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6107 /* nmaclhws - nmaclhws. */ 6108 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6109 /* nmaclhwso - nmaclhwso. */ 6110 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6111 6112 /* mulchw - mulchw. */ 6113 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6114 /* mulchwu - mulchwu. */ 6115 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6116 /* mulhhw - mulhhw. */ 6117 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6118 /* mulhhwu - mulhhwu. */ 6119 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6120 /* mullhw - mullhw. */ 6121 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6122 /* mullhwu - mullhwu. */ 6123 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6124 6125 /* mfdcr */ 6126 static void gen_mfdcr(DisasContext *ctx) 6127 { 6128 #if defined(CONFIG_USER_ONLY) 6129 GEN_PRIV; 6130 #else 6131 TCGv dcrn; 6132 6133 CHK_SV; 6134 dcrn = tcg_const_tl(SPR(ctx->opcode)); 6135 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6136 tcg_temp_free(dcrn); 6137 #endif /* defined(CONFIG_USER_ONLY) */ 6138 } 6139 6140 /* mtdcr */ 6141 static void gen_mtdcr(DisasContext *ctx) 6142 { 6143 #if defined(CONFIG_USER_ONLY) 6144 GEN_PRIV; 6145 #else 6146 TCGv dcrn; 6147 6148 CHK_SV; 6149 dcrn = tcg_const_tl(SPR(ctx->opcode)); 6150 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6151 tcg_temp_free(dcrn); 6152 #endif /* defined(CONFIG_USER_ONLY) */ 6153 } 6154 6155 /* mfdcrx */ 6156 /* XXX: not implemented on 440 ? */ 6157 static void gen_mfdcrx(DisasContext *ctx) 6158 { 6159 #if defined(CONFIG_USER_ONLY) 6160 GEN_PRIV; 6161 #else 6162 CHK_SV; 6163 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6164 cpu_gpr[rA(ctx->opcode)]); 6165 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6166 #endif /* defined(CONFIG_USER_ONLY) */ 6167 } 6168 6169 /* mtdcrx */ 6170 /* XXX: not implemented on 440 ? */ 6171 static void gen_mtdcrx(DisasContext *ctx) 6172 { 6173 #if defined(CONFIG_USER_ONLY) 6174 GEN_PRIV; 6175 #else 6176 CHK_SV; 6177 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6178 cpu_gpr[rS(ctx->opcode)]); 6179 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6180 #endif /* defined(CONFIG_USER_ONLY) */ 6181 } 6182 6183 /* mfdcrux (PPC 460) : user-mode access to DCR */ 6184 static void gen_mfdcrux(DisasContext *ctx) 6185 { 6186 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6187 cpu_gpr[rA(ctx->opcode)]); 6188 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6189 } 6190 6191 /* mtdcrux (PPC 460) : user-mode access to DCR */ 6192 static void gen_mtdcrux(DisasContext *ctx) 6193 { 6194 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6195 cpu_gpr[rS(ctx->opcode)]); 6196 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6197 } 6198 6199 /* dccci */ 6200 static void gen_dccci(DisasContext *ctx) 6201 { 6202 CHK_SV; 6203 /* interpreted as no-op */ 6204 } 6205 6206 /* dcread */ 6207 static void gen_dcread(DisasContext *ctx) 6208 { 6209 #if defined(CONFIG_USER_ONLY) 6210 GEN_PRIV; 6211 #else 6212 TCGv EA, val; 6213 6214 CHK_SV; 6215 gen_set_access_type(ctx, ACCESS_CACHE); 6216 EA = tcg_temp_new(); 6217 gen_addr_reg_index(ctx, EA); 6218 val = tcg_temp_new(); 6219 gen_qemu_ld32u(ctx, val, EA); 6220 tcg_temp_free(val); 6221 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6222 tcg_temp_free(EA); 6223 #endif /* defined(CONFIG_USER_ONLY) */ 6224 } 6225 6226 /* icbt */ 6227 static void gen_icbt_40x(DisasContext *ctx) 6228 { 6229 /* 6230 * interpreted as no-op 6231 * XXX: specification say this is treated as a load by the MMU but 6232 * does not generate any exception 6233 */ 6234 } 6235 6236 /* iccci */ 6237 static void gen_iccci(DisasContext *ctx) 6238 { 6239 CHK_SV; 6240 /* interpreted as no-op */ 6241 } 6242 6243 /* icread */ 6244 static void gen_icread(DisasContext *ctx) 6245 { 6246 CHK_SV; 6247 /* interpreted as no-op */ 6248 } 6249 6250 /* rfci (supervisor only) */ 6251 static void gen_rfci_40x(DisasContext *ctx) 6252 { 6253 #if defined(CONFIG_USER_ONLY) 6254 GEN_PRIV; 6255 #else 6256 CHK_SV; 6257 /* Restore CPU state */ 6258 gen_helper_40x_rfci(cpu_env); 6259 gen_sync_exception(ctx); 6260 #endif /* defined(CONFIG_USER_ONLY) */ 6261 } 6262 6263 static void gen_rfci(DisasContext *ctx) 6264 { 6265 #if defined(CONFIG_USER_ONLY) 6266 GEN_PRIV; 6267 #else 6268 CHK_SV; 6269 /* Restore CPU state */ 6270 gen_helper_rfci(cpu_env); 6271 gen_sync_exception(ctx); 6272 #endif /* defined(CONFIG_USER_ONLY) */ 6273 } 6274 6275 /* BookE specific */ 6276 6277 /* XXX: not implemented on 440 ? */ 6278 static void gen_rfdi(DisasContext *ctx) 6279 { 6280 #if defined(CONFIG_USER_ONLY) 6281 GEN_PRIV; 6282 #else 6283 CHK_SV; 6284 /* Restore CPU state */ 6285 gen_helper_rfdi(cpu_env); 6286 gen_sync_exception(ctx); 6287 #endif /* defined(CONFIG_USER_ONLY) */ 6288 } 6289 6290 /* XXX: not implemented on 440 ? */ 6291 static void gen_rfmci(DisasContext *ctx) 6292 { 6293 #if defined(CONFIG_USER_ONLY) 6294 GEN_PRIV; 6295 #else 6296 CHK_SV; 6297 /* Restore CPU state */ 6298 gen_helper_rfmci(cpu_env); 6299 gen_sync_exception(ctx); 6300 #endif /* defined(CONFIG_USER_ONLY) */ 6301 } 6302 6303 /* TLB management - PowerPC 405 implementation */ 6304 6305 /* tlbre */ 6306 static void gen_tlbre_40x(DisasContext *ctx) 6307 { 6308 #if defined(CONFIG_USER_ONLY) 6309 GEN_PRIV; 6310 #else 6311 CHK_SV; 6312 switch (rB(ctx->opcode)) { 6313 case 0: 6314 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6315 cpu_gpr[rA(ctx->opcode)]); 6316 break; 6317 case 1: 6318 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6319 cpu_gpr[rA(ctx->opcode)]); 6320 break; 6321 default: 6322 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6323 break; 6324 } 6325 #endif /* defined(CONFIG_USER_ONLY) */ 6326 } 6327 6328 /* tlbsx - tlbsx. */ 6329 static void gen_tlbsx_40x(DisasContext *ctx) 6330 { 6331 #if defined(CONFIG_USER_ONLY) 6332 GEN_PRIV; 6333 #else 6334 TCGv t0; 6335 6336 CHK_SV; 6337 t0 = tcg_temp_new(); 6338 gen_addr_reg_index(ctx, t0); 6339 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6340 tcg_temp_free(t0); 6341 if (Rc(ctx->opcode)) { 6342 TCGLabel *l1 = gen_new_label(); 6343 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6344 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6345 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6346 gen_set_label(l1); 6347 } 6348 #endif /* defined(CONFIG_USER_ONLY) */ 6349 } 6350 6351 /* tlbwe */ 6352 static void gen_tlbwe_40x(DisasContext *ctx) 6353 { 6354 #if defined(CONFIG_USER_ONLY) 6355 GEN_PRIV; 6356 #else 6357 CHK_SV; 6358 6359 switch (rB(ctx->opcode)) { 6360 case 0: 6361 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6362 cpu_gpr[rS(ctx->opcode)]); 6363 break; 6364 case 1: 6365 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6366 cpu_gpr[rS(ctx->opcode)]); 6367 break; 6368 default: 6369 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6370 break; 6371 } 6372 #endif /* defined(CONFIG_USER_ONLY) */ 6373 } 6374 6375 /* TLB management - PowerPC 440 implementation */ 6376 6377 /* tlbre */ 6378 static void gen_tlbre_440(DisasContext *ctx) 6379 { 6380 #if defined(CONFIG_USER_ONLY) 6381 GEN_PRIV; 6382 #else 6383 CHK_SV; 6384 6385 switch (rB(ctx->opcode)) { 6386 case 0: 6387 case 1: 6388 case 2: 6389 { 6390 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6391 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6392 t0, cpu_gpr[rA(ctx->opcode)]); 6393 tcg_temp_free_i32(t0); 6394 } 6395 break; 6396 default: 6397 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6398 break; 6399 } 6400 #endif /* defined(CONFIG_USER_ONLY) */ 6401 } 6402 6403 /* tlbsx - tlbsx. */ 6404 static void gen_tlbsx_440(DisasContext *ctx) 6405 { 6406 #if defined(CONFIG_USER_ONLY) 6407 GEN_PRIV; 6408 #else 6409 TCGv t0; 6410 6411 CHK_SV; 6412 t0 = tcg_temp_new(); 6413 gen_addr_reg_index(ctx, t0); 6414 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6415 tcg_temp_free(t0); 6416 if (Rc(ctx->opcode)) { 6417 TCGLabel *l1 = gen_new_label(); 6418 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6419 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6420 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6421 gen_set_label(l1); 6422 } 6423 #endif /* defined(CONFIG_USER_ONLY) */ 6424 } 6425 6426 /* tlbwe */ 6427 static void gen_tlbwe_440(DisasContext *ctx) 6428 { 6429 #if defined(CONFIG_USER_ONLY) 6430 GEN_PRIV; 6431 #else 6432 CHK_SV; 6433 switch (rB(ctx->opcode)) { 6434 case 0: 6435 case 1: 6436 case 2: 6437 { 6438 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6439 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6440 cpu_gpr[rS(ctx->opcode)]); 6441 tcg_temp_free_i32(t0); 6442 } 6443 break; 6444 default: 6445 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6446 break; 6447 } 6448 #endif /* defined(CONFIG_USER_ONLY) */ 6449 } 6450 6451 /* TLB management - PowerPC BookE 2.06 implementation */ 6452 6453 /* tlbre */ 6454 static void gen_tlbre_booke206(DisasContext *ctx) 6455 { 6456 #if defined(CONFIG_USER_ONLY) 6457 GEN_PRIV; 6458 #else 6459 CHK_SV; 6460 gen_helper_booke206_tlbre(cpu_env); 6461 #endif /* defined(CONFIG_USER_ONLY) */ 6462 } 6463 6464 /* tlbsx - tlbsx. */ 6465 static void gen_tlbsx_booke206(DisasContext *ctx) 6466 { 6467 #if defined(CONFIG_USER_ONLY) 6468 GEN_PRIV; 6469 #else 6470 TCGv t0; 6471 6472 CHK_SV; 6473 if (rA(ctx->opcode)) { 6474 t0 = tcg_temp_new(); 6475 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6476 } else { 6477 t0 = tcg_const_tl(0); 6478 } 6479 6480 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6481 gen_helper_booke206_tlbsx(cpu_env, t0); 6482 tcg_temp_free(t0); 6483 #endif /* defined(CONFIG_USER_ONLY) */ 6484 } 6485 6486 /* tlbwe */ 6487 static void gen_tlbwe_booke206(DisasContext *ctx) 6488 { 6489 #if defined(CONFIG_USER_ONLY) 6490 GEN_PRIV; 6491 #else 6492 CHK_SV; 6493 gen_helper_booke206_tlbwe(cpu_env); 6494 #endif /* defined(CONFIG_USER_ONLY) */ 6495 } 6496 6497 static void gen_tlbivax_booke206(DisasContext *ctx) 6498 { 6499 #if defined(CONFIG_USER_ONLY) 6500 GEN_PRIV; 6501 #else 6502 TCGv t0; 6503 6504 CHK_SV; 6505 t0 = tcg_temp_new(); 6506 gen_addr_reg_index(ctx, t0); 6507 gen_helper_booke206_tlbivax(cpu_env, t0); 6508 tcg_temp_free(t0); 6509 #endif /* defined(CONFIG_USER_ONLY) */ 6510 } 6511 6512 static void gen_tlbilx_booke206(DisasContext *ctx) 6513 { 6514 #if defined(CONFIG_USER_ONLY) 6515 GEN_PRIV; 6516 #else 6517 TCGv t0; 6518 6519 CHK_SV; 6520 t0 = tcg_temp_new(); 6521 gen_addr_reg_index(ctx, t0); 6522 6523 switch ((ctx->opcode >> 21) & 0x3) { 6524 case 0: 6525 gen_helper_booke206_tlbilx0(cpu_env, t0); 6526 break; 6527 case 1: 6528 gen_helper_booke206_tlbilx1(cpu_env, t0); 6529 break; 6530 case 3: 6531 gen_helper_booke206_tlbilx3(cpu_env, t0); 6532 break; 6533 default: 6534 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6535 break; 6536 } 6537 6538 tcg_temp_free(t0); 6539 #endif /* defined(CONFIG_USER_ONLY) */ 6540 } 6541 6542 6543 /* wrtee */ 6544 static void gen_wrtee(DisasContext *ctx) 6545 { 6546 #if defined(CONFIG_USER_ONLY) 6547 GEN_PRIV; 6548 #else 6549 TCGv t0; 6550 6551 CHK_SV; 6552 t0 = tcg_temp_new(); 6553 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6554 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6555 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6556 tcg_temp_free(t0); 6557 /* 6558 * Stop translation to have a chance to raise an exception if we 6559 * just set msr_ee to 1 6560 */ 6561 gen_stop_exception(ctx); 6562 #endif /* defined(CONFIG_USER_ONLY) */ 6563 } 6564 6565 /* wrteei */ 6566 static void gen_wrteei(DisasContext *ctx) 6567 { 6568 #if defined(CONFIG_USER_ONLY) 6569 GEN_PRIV; 6570 #else 6571 CHK_SV; 6572 if (ctx->opcode & 0x00008000) { 6573 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6574 /* Stop translation to have a chance to raise an exception */ 6575 gen_stop_exception(ctx); 6576 } else { 6577 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6578 } 6579 #endif /* defined(CONFIG_USER_ONLY) */ 6580 } 6581 6582 /* PowerPC 440 specific instructions */ 6583 6584 /* dlmzb */ 6585 static void gen_dlmzb(DisasContext *ctx) 6586 { 6587 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6588 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6589 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6590 tcg_temp_free_i32(t0); 6591 } 6592 6593 /* mbar replaces eieio on 440 */ 6594 static void gen_mbar(DisasContext *ctx) 6595 { 6596 /* interpreted as no-op */ 6597 } 6598 6599 /* msync replaces sync on 440 */ 6600 static void gen_msync_4xx(DisasContext *ctx) 6601 { 6602 /* Only e500 seems to treat reserved bits as invalid */ 6603 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 6604 (ctx->opcode & 0x03FFF801)) { 6605 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6606 } 6607 /* otherwise interpreted as no-op */ 6608 } 6609 6610 /* icbt */ 6611 static void gen_icbt_440(DisasContext *ctx) 6612 { 6613 /* 6614 * interpreted as no-op 6615 * XXX: specification say this is treated as a load by the MMU but 6616 * does not generate any exception 6617 */ 6618 } 6619 6620 /* Embedded.Processor Control */ 6621 6622 static void gen_msgclr(DisasContext *ctx) 6623 { 6624 #if defined(CONFIG_USER_ONLY) 6625 GEN_PRIV; 6626 #else 6627 CHK_HV; 6628 if (is_book3s_arch2x(ctx)) { 6629 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6630 } else { 6631 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6632 } 6633 #endif /* defined(CONFIG_USER_ONLY) */ 6634 } 6635 6636 static void gen_msgsnd(DisasContext *ctx) 6637 { 6638 #if defined(CONFIG_USER_ONLY) 6639 GEN_PRIV; 6640 #else 6641 CHK_HV; 6642 if (is_book3s_arch2x(ctx)) { 6643 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6644 } else { 6645 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6646 } 6647 #endif /* defined(CONFIG_USER_ONLY) */ 6648 } 6649 6650 #if defined(TARGET_PPC64) 6651 static void gen_msgclrp(DisasContext *ctx) 6652 { 6653 #if defined(CONFIG_USER_ONLY) 6654 GEN_PRIV; 6655 #else 6656 CHK_SV; 6657 gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6658 #endif /* defined(CONFIG_USER_ONLY) */ 6659 } 6660 6661 static void gen_msgsndp(DisasContext *ctx) 6662 { 6663 #if defined(CONFIG_USER_ONLY) 6664 GEN_PRIV; 6665 #else 6666 CHK_SV; 6667 gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6668 #endif /* defined(CONFIG_USER_ONLY) */ 6669 } 6670 #endif 6671 6672 static void gen_msgsync(DisasContext *ctx) 6673 { 6674 #if defined(CONFIG_USER_ONLY) 6675 GEN_PRIV; 6676 #else 6677 CHK_HV; 6678 #endif /* defined(CONFIG_USER_ONLY) */ 6679 /* interpreted as no-op */ 6680 } 6681 6682 #if defined(TARGET_PPC64) 6683 static void gen_maddld(DisasContext *ctx) 6684 { 6685 TCGv_i64 t1 = tcg_temp_new_i64(); 6686 6687 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6688 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6689 tcg_temp_free_i64(t1); 6690 } 6691 6692 /* maddhd maddhdu */ 6693 static void gen_maddhd_maddhdu(DisasContext *ctx) 6694 { 6695 TCGv_i64 lo = tcg_temp_new_i64(); 6696 TCGv_i64 hi = tcg_temp_new_i64(); 6697 TCGv_i64 t1 = tcg_temp_new_i64(); 6698 6699 if (Rc(ctx->opcode)) { 6700 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6701 cpu_gpr[rB(ctx->opcode)]); 6702 tcg_gen_movi_i64(t1, 0); 6703 } else { 6704 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6705 cpu_gpr[rB(ctx->opcode)]); 6706 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6707 } 6708 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6709 cpu_gpr[rC(ctx->opcode)], t1); 6710 tcg_temp_free_i64(lo); 6711 tcg_temp_free_i64(hi); 6712 tcg_temp_free_i64(t1); 6713 } 6714 #endif /* defined(TARGET_PPC64) */ 6715 6716 static void gen_tbegin(DisasContext *ctx) 6717 { 6718 if (unlikely(!ctx->tm_enabled)) { 6719 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6720 return; 6721 } 6722 gen_helper_tbegin(cpu_env); 6723 } 6724 6725 #define GEN_TM_NOOP(name) \ 6726 static inline void gen_##name(DisasContext *ctx) \ 6727 { \ 6728 if (unlikely(!ctx->tm_enabled)) { \ 6729 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6730 return; \ 6731 } \ 6732 /* \ 6733 * Because tbegin always fails in QEMU, these user \ 6734 * space instructions all have a simple implementation: \ 6735 * \ 6736 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6737 * = 0b0 || 0b00 || 0b0 \ 6738 */ \ 6739 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6740 } 6741 6742 GEN_TM_NOOP(tend); 6743 GEN_TM_NOOP(tabort); 6744 GEN_TM_NOOP(tabortwc); 6745 GEN_TM_NOOP(tabortwci); 6746 GEN_TM_NOOP(tabortdc); 6747 GEN_TM_NOOP(tabortdci); 6748 GEN_TM_NOOP(tsr); 6749 6750 static inline void gen_cp_abort(DisasContext *ctx) 6751 { 6752 /* Do Nothing */ 6753 } 6754 6755 #define GEN_CP_PASTE_NOOP(name) \ 6756 static inline void gen_##name(DisasContext *ctx) \ 6757 { \ 6758 /* \ 6759 * Generate invalid exception until we have an \ 6760 * implementation of the copy paste facility \ 6761 */ \ 6762 gen_invalid(ctx); \ 6763 } 6764 6765 GEN_CP_PASTE_NOOP(copy) 6766 GEN_CP_PASTE_NOOP(paste) 6767 6768 static void gen_tcheck(DisasContext *ctx) 6769 { 6770 if (unlikely(!ctx->tm_enabled)) { 6771 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6772 return; 6773 } 6774 /* 6775 * Because tbegin always fails, the tcheck implementation is 6776 * simple: 6777 * 6778 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6779 * = 0b1 || 0b00 || 0b0 6780 */ 6781 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6782 } 6783 6784 #if defined(CONFIG_USER_ONLY) 6785 #define GEN_TM_PRIV_NOOP(name) \ 6786 static inline void gen_##name(DisasContext *ctx) \ 6787 { \ 6788 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6789 } 6790 6791 #else 6792 6793 #define GEN_TM_PRIV_NOOP(name) \ 6794 static inline void gen_##name(DisasContext *ctx) \ 6795 { \ 6796 CHK_SV; \ 6797 if (unlikely(!ctx->tm_enabled)) { \ 6798 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6799 return; \ 6800 } \ 6801 /* \ 6802 * Because tbegin always fails, the implementation is \ 6803 * simple: \ 6804 * \ 6805 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6806 * = 0b0 || 0b00 | 0b0 \ 6807 */ \ 6808 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6809 } 6810 6811 #endif 6812 6813 GEN_TM_PRIV_NOOP(treclaim); 6814 GEN_TM_PRIV_NOOP(trechkpt); 6815 6816 static inline void get_fpr(TCGv_i64 dst, int regno) 6817 { 6818 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 6819 } 6820 6821 static inline void set_fpr(int regno, TCGv_i64 src) 6822 { 6823 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 6824 } 6825 6826 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6827 { 6828 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6829 } 6830 6831 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6832 { 6833 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6834 } 6835 6836 #include "translate/fp-impl.inc.c" 6837 6838 #include "translate/vmx-impl.inc.c" 6839 6840 #include "translate/vsx-impl.inc.c" 6841 6842 #include "translate/dfp-impl.inc.c" 6843 6844 #include "translate/spe-impl.inc.c" 6845 6846 /* Handles lfdp, lxsd, lxssp */ 6847 static void gen_dform39(DisasContext *ctx) 6848 { 6849 switch (ctx->opcode & 0x3) { 6850 case 0: /* lfdp */ 6851 if (ctx->insns_flags2 & PPC2_ISA205) { 6852 return gen_lfdp(ctx); 6853 } 6854 break; 6855 case 2: /* lxsd */ 6856 if (ctx->insns_flags2 & PPC2_ISA300) { 6857 return gen_lxsd(ctx); 6858 } 6859 break; 6860 case 3: /* lxssp */ 6861 if (ctx->insns_flags2 & PPC2_ISA300) { 6862 return gen_lxssp(ctx); 6863 } 6864 break; 6865 } 6866 return gen_invalid(ctx); 6867 } 6868 6869 /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6870 static void gen_dform3D(DisasContext *ctx) 6871 { 6872 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6873 switch (ctx->opcode & 0x7) { 6874 case 1: /* lxv */ 6875 if (ctx->insns_flags2 & PPC2_ISA300) { 6876 return gen_lxv(ctx); 6877 } 6878 break; 6879 case 5: /* stxv */ 6880 if (ctx->insns_flags2 & PPC2_ISA300) { 6881 return gen_stxv(ctx); 6882 } 6883 break; 6884 } 6885 } else { /* DS-FORM */ 6886 switch (ctx->opcode & 0x3) { 6887 case 0: /* stfdp */ 6888 if (ctx->insns_flags2 & PPC2_ISA205) { 6889 return gen_stfdp(ctx); 6890 } 6891 break; 6892 case 2: /* stxsd */ 6893 if (ctx->insns_flags2 & PPC2_ISA300) { 6894 return gen_stxsd(ctx); 6895 } 6896 break; 6897 case 3: /* stxssp */ 6898 if (ctx->insns_flags2 & PPC2_ISA300) { 6899 return gen_stxssp(ctx); 6900 } 6901 break; 6902 } 6903 } 6904 return gen_invalid(ctx); 6905 } 6906 6907 static opcode_t opcodes[] = { 6908 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6909 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6910 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6911 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6912 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6913 #if defined(TARGET_PPC64) 6914 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6915 #endif 6916 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6917 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6918 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6919 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6920 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6921 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6922 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6923 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6924 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6925 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6926 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6927 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6928 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6929 #if defined(TARGET_PPC64) 6930 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6931 #endif 6932 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6933 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6934 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6935 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6936 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6937 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6938 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6939 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6940 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6941 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6942 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6943 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6944 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6945 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6946 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6947 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6948 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6949 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6950 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6951 #if defined(TARGET_PPC64) 6952 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6953 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6954 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6955 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6956 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6957 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6958 #endif 6959 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6960 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6961 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6962 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6963 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6964 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6965 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6966 #if defined(TARGET_PPC64) 6967 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6968 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6969 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6970 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6971 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6972 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6973 PPC_NONE, PPC2_ISA300), 6974 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6975 PPC_NONE, PPC2_ISA300), 6976 #endif 6977 #if defined(TARGET_PPC64) 6978 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6979 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6980 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6981 #endif 6982 /* handles lfdp, lxsd, lxssp */ 6983 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6984 /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6985 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6986 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6987 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6988 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6989 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6990 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6991 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6992 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6993 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6994 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6995 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6996 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6997 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6998 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6999 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7000 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7001 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7002 #if defined(TARGET_PPC64) 7003 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7004 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7005 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7006 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7007 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7008 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7009 #endif 7010 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7011 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7012 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7013 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7014 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7015 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7016 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7017 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7018 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7019 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7020 #if defined(TARGET_PPC64) 7021 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 7022 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7023 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7024 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7025 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7026 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7027 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7028 #endif 7029 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 7030 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7031 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7032 #if defined(TARGET_PPC64) 7033 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7034 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7035 #endif 7036 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7037 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7038 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7039 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7040 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7041 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7042 #if defined(TARGET_PPC64) 7043 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7044 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7045 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7046 #endif 7047 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7048 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7049 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 7050 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7051 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7052 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 7053 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7054 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 7055 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7056 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 7057 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7058 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7059 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 7060 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7061 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 7062 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7063 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7064 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 7065 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7066 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7067 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7068 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7069 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7070 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7071 #if defined(TARGET_PPC64) 7072 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7073 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7074 PPC_SEGMENT_64B), 7075 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7076 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7077 PPC_SEGMENT_64B), 7078 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7079 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7080 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7081 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7082 #endif 7083 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7084 /* 7085 * XXX Those instructions will need to be handled differently for 7086 * different ISA versions 7087 */ 7088 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7089 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7090 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7091 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7092 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7093 #if defined(TARGET_PPC64) 7094 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7095 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7096 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 7097 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7098 #endif 7099 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7100 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7101 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7102 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7103 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7104 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7105 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7106 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7107 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7108 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7109 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7110 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7111 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7112 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7113 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7114 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7115 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7116 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7117 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7118 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7119 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7120 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7121 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7122 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7123 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7124 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7125 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7126 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7127 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7128 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7129 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7130 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7131 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7132 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7133 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7134 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7135 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7136 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7137 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7138 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7139 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7140 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7141 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7142 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7143 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7144 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7145 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7146 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7147 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7148 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7149 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7150 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7151 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7152 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7153 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7154 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7155 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7156 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7157 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7158 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7159 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7160 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7161 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7162 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7163 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7164 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7165 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7166 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7167 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7168 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7169 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7170 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7171 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7172 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7173 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7174 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7175 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7176 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7177 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7178 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7179 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7180 PPC_NONE, PPC2_BOOKE206), 7181 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7182 PPC_NONE, PPC2_BOOKE206), 7183 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7184 PPC_NONE, PPC2_BOOKE206), 7185 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7186 PPC_NONE, PPC2_BOOKE206), 7187 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7188 PPC_NONE, PPC2_BOOKE206), 7189 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7190 PPC_NONE, PPC2_PRCNTL), 7191 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7192 PPC_NONE, PPC2_PRCNTL), 7193 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 7194 PPC_NONE, PPC2_PRCNTL), 7195 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7196 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7197 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7198 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7199 PPC_BOOKE, PPC2_BOOKE206), 7200 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7201 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7202 PPC_BOOKE, PPC2_BOOKE206), 7203 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 7204 PPC_440_SPEC), 7205 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7206 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7207 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7208 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7209 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7210 #if defined(TARGET_PPC64) 7211 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7212 PPC2_ISA300), 7213 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7214 GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 7215 PPC_NONE, PPC2_ISA207S), 7216 GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 7217 PPC_NONE, PPC2_ISA207S), 7218 #endif 7219 7220 #undef GEN_INT_ARITH_ADD 7221 #undef GEN_INT_ARITH_ADD_CONST 7222 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7223 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7224 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7225 add_ca, compute_ca, compute_ov) \ 7226 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7227 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7228 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7229 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7230 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7231 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7232 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7233 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7234 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 7235 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7236 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7237 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7238 7239 #undef GEN_INT_ARITH_DIVW 7240 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7241 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7242 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7243 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7244 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7245 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7246 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7247 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7248 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7249 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7250 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7251 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7252 7253 #if defined(TARGET_PPC64) 7254 #undef GEN_INT_ARITH_DIVD 7255 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7256 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7257 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7258 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7259 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7260 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7261 7262 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7263 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7264 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7265 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7266 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7267 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7268 7269 #undef GEN_INT_ARITH_MUL_HELPER 7270 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7271 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7272 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7273 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7274 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7275 #endif 7276 7277 #undef GEN_INT_ARITH_SUBF 7278 #undef GEN_INT_ARITH_SUBF_CONST 7279 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7280 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7281 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7282 add_ca, compute_ca, compute_ov) \ 7283 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7284 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7285 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7286 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7287 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7288 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7289 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7290 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7291 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7292 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7293 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7294 7295 #undef GEN_LOGICAL1 7296 #undef GEN_LOGICAL2 7297 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7298 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7299 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7300 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7301 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7302 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7303 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7304 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7305 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7306 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7307 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7308 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7309 #if defined(TARGET_PPC64) 7310 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7311 #endif 7312 7313 #if defined(TARGET_PPC64) 7314 #undef GEN_PPC64_R2 7315 #undef GEN_PPC64_R4 7316 #define GEN_PPC64_R2(name, opc1, opc2) \ 7317 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7318 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7319 PPC_64B) 7320 #define GEN_PPC64_R4(name, opc1, opc2) \ 7321 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7322 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7323 PPC_64B), \ 7324 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7325 PPC_64B), \ 7326 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7327 PPC_64B) 7328 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7329 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7330 GEN_PPC64_R4(rldic, 0x1E, 0x04), 7331 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7332 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7333 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7334 #endif 7335 7336 #undef GEN_LD 7337 #undef GEN_LDU 7338 #undef GEN_LDUX 7339 #undef GEN_LDX_E 7340 #undef GEN_LDS 7341 #define GEN_LD(name, ldop, opc, type) \ 7342 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7343 #define GEN_LDU(name, ldop, opc, type) \ 7344 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 7345 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 7346 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7347 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7348 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7349 #define GEN_LDS(name, ldop, op, type) \ 7350 GEN_LD(name, ldop, op | 0x20, type) \ 7351 GEN_LDU(name, ldop, op | 0x21, type) \ 7352 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 7353 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 7354 7355 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 7356 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 7357 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 7358 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 7359 #if defined(TARGET_PPC64) 7360 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 7361 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 7362 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 7363 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 7364 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7365 7366 /* HV/P7 and later only */ 7367 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7368 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7369 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7370 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7371 #endif 7372 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7373 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7374 7375 /* External PID based load */ 7376 #undef GEN_LDEPX 7377 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 7378 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 7379 0x00000001, PPC_NONE, PPC2_BOOKE206), 7380 7381 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 7382 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 7383 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 7384 #if defined(TARGET_PPC64) 7385 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 7386 #endif 7387 7388 #undef GEN_ST 7389 #undef GEN_STU 7390 #undef GEN_STUX 7391 #undef GEN_STX_E 7392 #undef GEN_STS 7393 #define GEN_ST(name, stop, opc, type) \ 7394 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7395 #define GEN_STU(name, stop, opc, type) \ 7396 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 7397 #define GEN_STUX(name, stop, opc2, opc3, type) \ 7398 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7399 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 7400 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7401 #define GEN_STS(name, stop, op, type) \ 7402 GEN_ST(name, stop, op | 0x20, type) \ 7403 GEN_STU(name, stop, op | 0x21, type) \ 7404 GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 7405 GEN_STX(name, stop, 0x17, op | 0x00, type) 7406 7407 GEN_STS(stb, st8, 0x06, PPC_INTEGER) 7408 GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 7409 GEN_STS(stw, st32, 0x04, PPC_INTEGER) 7410 #if defined(TARGET_PPC64) 7411 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 7412 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 7413 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7414 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7415 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7416 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7417 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7418 #endif 7419 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7420 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7421 7422 #undef GEN_STEPX 7423 #define GEN_STEPX(name, ldop, opc2, opc3) \ 7424 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 7425 0x00000001, PPC_NONE, PPC2_BOOKE206), 7426 7427 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 7428 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 7429 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 7430 #if defined(TARGET_PPC64) 7431 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 7432 #endif 7433 7434 #undef GEN_CRLOGIC 7435 #define GEN_CRLOGIC(name, tcg_op, opc) \ 7436 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7437 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7438 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7439 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7440 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7441 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7442 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7443 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7444 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7445 7446 #undef GEN_MAC_HANDLER 7447 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7448 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7449 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7450 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7451 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7452 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7453 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7454 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7455 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7456 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7457 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7458 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7459 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7460 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7461 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7462 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7463 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7464 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7465 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7466 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7467 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7468 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7469 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7470 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7471 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7472 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7473 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7474 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7475 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7476 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7477 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7478 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7479 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7480 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7481 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7482 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7483 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7484 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7485 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7486 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7487 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7488 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7489 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7490 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7491 7492 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7493 PPC_NONE, PPC2_TM), 7494 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7495 PPC_NONE, PPC2_TM), 7496 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7497 PPC_NONE, PPC2_TM), 7498 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7499 PPC_NONE, PPC2_TM), 7500 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7501 PPC_NONE, PPC2_TM), 7502 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7503 PPC_NONE, PPC2_TM), 7504 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7505 PPC_NONE, PPC2_TM), 7506 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7507 PPC_NONE, PPC2_TM), 7508 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7509 PPC_NONE, PPC2_TM), 7510 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7511 PPC_NONE, PPC2_TM), 7512 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7513 PPC_NONE, PPC2_TM), 7514 7515 #include "translate/fp-ops.inc.c" 7516 7517 #include "translate/vmx-ops.inc.c" 7518 7519 #include "translate/vsx-ops.inc.c" 7520 7521 #include "translate/dfp-ops.inc.c" 7522 7523 #include "translate/spe-ops.inc.c" 7524 }; 7525 7526 #include "helper_regs.h" 7527 #include "translate_init.inc.c" 7528 7529 /*****************************************************************************/ 7530 /* Misc PowerPC helpers */ 7531 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7532 { 7533 #define RGPL 4 7534 #define RFPL 4 7535 7536 PowerPCCPU *cpu = POWERPC_CPU(cs); 7537 CPUPPCState *env = &cpu->env; 7538 int i; 7539 7540 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7541 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7542 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7543 cs->cpu_index); 7544 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7545 TARGET_FMT_lx " iidx %d didx %d\n", 7546 env->msr, env->spr[SPR_HID0], 7547 env->hflags, env->immu_idx, env->dmmu_idx); 7548 #if !defined(NO_TIMER_DUMP) 7549 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7550 #if !defined(CONFIG_USER_ONLY) 7551 " DECR " TARGET_FMT_lu 7552 #endif 7553 "\n", 7554 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7555 #if !defined(CONFIG_USER_ONLY) 7556 , cpu_ppc_load_decr(env) 7557 #endif 7558 ); 7559 #endif 7560 for (i = 0; i < 32; i++) { 7561 if ((i & (RGPL - 1)) == 0) { 7562 qemu_fprintf(f, "GPR%02d", i); 7563 } 7564 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7565 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7566 qemu_fprintf(f, "\n"); 7567 } 7568 } 7569 qemu_fprintf(f, "CR "); 7570 for (i = 0; i < 8; i++) 7571 qemu_fprintf(f, "%01x", env->crf[i]); 7572 qemu_fprintf(f, " ["); 7573 for (i = 0; i < 8; i++) { 7574 char a = '-'; 7575 if (env->crf[i] & 0x08) { 7576 a = 'L'; 7577 } else if (env->crf[i] & 0x04) { 7578 a = 'G'; 7579 } else if (env->crf[i] & 0x02) { 7580 a = 'E'; 7581 } 7582 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7583 } 7584 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7585 env->reserve_addr); 7586 7587 if (flags & CPU_DUMP_FPU) { 7588 for (i = 0; i < 32; i++) { 7589 if ((i & (RFPL - 1)) == 0) { 7590 qemu_fprintf(f, "FPR%02d", i); 7591 } 7592 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7593 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7594 qemu_fprintf(f, "\n"); 7595 } 7596 } 7597 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7598 } 7599 7600 #if !defined(CONFIG_USER_ONLY) 7601 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7602 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7603 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7604 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7605 7606 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7607 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7608 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7609 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7610 7611 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7612 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7613 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7614 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7615 7616 #if defined(TARGET_PPC64) 7617 if (env->excp_model == POWERPC_EXCP_POWER7 || 7618 env->excp_model == POWERPC_EXCP_POWER8 || 7619 env->excp_model == POWERPC_EXCP_POWER9) { 7620 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7621 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7622 } 7623 #endif 7624 if (env->excp_model == POWERPC_EXCP_BOOKE) { 7625 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7626 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7627 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7628 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7629 7630 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7631 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7632 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7633 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7634 7635 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7636 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7637 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7638 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7639 7640 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7641 " EPR " TARGET_FMT_lx "\n", 7642 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7643 env->spr[SPR_BOOKE_EPR]); 7644 7645 /* FSL-specific */ 7646 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7647 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7648 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7649 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7650 7651 /* 7652 * IVORs are left out as they are large and do not change often -- 7653 * they can be read with "p $ivor0", "p $ivor1", etc. 7654 */ 7655 } 7656 7657 #if defined(TARGET_PPC64) 7658 if (env->flags & POWERPC_FLAG_CFAR) { 7659 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7660 } 7661 #endif 7662 7663 if (env->spr_cb[SPR_LPCR].name) { 7664 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7665 } 7666 7667 switch (env->mmu_model) { 7668 case POWERPC_MMU_32B: 7669 case POWERPC_MMU_601: 7670 case POWERPC_MMU_SOFT_6xx: 7671 case POWERPC_MMU_SOFT_74xx: 7672 #if defined(TARGET_PPC64) 7673 case POWERPC_MMU_64B: 7674 case POWERPC_MMU_2_03: 7675 case POWERPC_MMU_2_06: 7676 case POWERPC_MMU_2_07: 7677 case POWERPC_MMU_3_00: 7678 #endif 7679 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7680 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7681 } 7682 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7683 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7684 } 7685 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7686 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7687 break; 7688 case POWERPC_MMU_BOOKE206: 7689 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7690 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7691 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7692 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7693 7694 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7695 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7696 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7697 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7698 7699 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7700 " TLB1CFG " TARGET_FMT_lx "\n", 7701 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7702 env->spr[SPR_BOOKE_TLB1CFG]); 7703 break; 7704 default: 7705 break; 7706 } 7707 #endif 7708 7709 #undef RGPL 7710 #undef RFPL 7711 } 7712 7713 void ppc_cpu_dump_statistics(CPUState *cs, int flags) 7714 { 7715 #if defined(DO_PPC_STATISTICS) 7716 PowerPCCPU *cpu = POWERPC_CPU(cs); 7717 opc_handler_t **t1, **t2, **t3, *handler; 7718 int op1, op2, op3; 7719 7720 t1 = cpu->env.opcodes; 7721 for (op1 = 0; op1 < 64; op1++) { 7722 handler = t1[op1]; 7723 if (is_indirect_opcode(handler)) { 7724 t2 = ind_table(handler); 7725 for (op2 = 0; op2 < 32; op2++) { 7726 handler = t2[op2]; 7727 if (is_indirect_opcode(handler)) { 7728 t3 = ind_table(handler); 7729 for (op3 = 0; op3 < 32; op3++) { 7730 handler = t3[op3]; 7731 if (handler->count == 0) { 7732 continue; 7733 } 7734 qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 7735 "%016" PRIx64 " %" PRId64 "\n", 7736 op1, op2, op3, op1, (op3 << 5) | op2, 7737 handler->oname, 7738 handler->count, handler->count); 7739 } 7740 } else { 7741 if (handler->count == 0) { 7742 continue; 7743 } 7744 qemu_printf("%02x %02x (%02x %04d) %16s: " 7745 "%016" PRIx64 " %" PRId64 "\n", 7746 op1, op2, op1, op2, handler->oname, 7747 handler->count, handler->count); 7748 } 7749 } 7750 } else { 7751 if (handler->count == 0) { 7752 continue; 7753 } 7754 qemu_printf("%02x (%02x ) %16s: %016" PRIx64 7755 " %" PRId64 "\n", 7756 op1, op1, handler->oname, 7757 handler->count, handler->count); 7758 } 7759 } 7760 #endif 7761 } 7762 7763 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7764 { 7765 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7766 CPUPPCState *env = cs->env_ptr; 7767 int bound; 7768 7769 ctx->exception = POWERPC_EXCP_NONE; 7770 ctx->spr_cb = env->spr_cb; 7771 ctx->pr = msr_pr; 7772 ctx->mem_idx = env->dmmu_idx; 7773 ctx->dr = msr_dr; 7774 #if !defined(CONFIG_USER_ONLY) 7775 ctx->hv = msr_hv || !env->has_hv_mode; 7776 #endif 7777 ctx->insns_flags = env->insns_flags; 7778 ctx->insns_flags2 = env->insns_flags2; 7779 ctx->access_type = -1; 7780 ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7781 ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); 7782 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7783 ctx->flags = env->flags; 7784 #if defined(TARGET_PPC64) 7785 ctx->sf_mode = msr_is_64bit(env, env->msr); 7786 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7787 #endif 7788 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7789 || env->mmu_model == POWERPC_MMU_601 7790 || (env->mmu_model & POWERPC_MMU_64B); 7791 7792 ctx->fpu_enabled = !!msr_fp; 7793 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { 7794 ctx->spe_enabled = !!msr_spe; 7795 } else { 7796 ctx->spe_enabled = false; 7797 } 7798 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) { 7799 ctx->altivec_enabled = !!msr_vr; 7800 } else { 7801 ctx->altivec_enabled = false; 7802 } 7803 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7804 ctx->vsx_enabled = !!msr_vsx; 7805 } else { 7806 ctx->vsx_enabled = false; 7807 } 7808 #if defined(TARGET_PPC64) 7809 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7810 ctx->tm_enabled = !!msr_tm; 7811 } else { 7812 ctx->tm_enabled = false; 7813 } 7814 #endif 7815 ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7816 if ((env->flags & POWERPC_FLAG_SE) && msr_se) { 7817 ctx->singlestep_enabled = CPU_SINGLE_STEP; 7818 } else { 7819 ctx->singlestep_enabled = 0; 7820 } 7821 if ((env->flags & POWERPC_FLAG_BE) && msr_be) { 7822 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7823 } 7824 if ((env->flags & POWERPC_FLAG_DE) && msr_de) { 7825 ctx->singlestep_enabled = 0; 7826 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 7827 if (dbcr0 & DBCR0_ICMP) { 7828 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7829 } 7830 if (dbcr0 & DBCR0_BRT) { 7831 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7832 } 7833 7834 } 7835 if (unlikely(ctx->base.singlestep_enabled)) { 7836 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7837 } 7838 #if defined(DO_SINGLE_STEP) && 0 7839 /* Single step trace mode */ 7840 msr_se = 1; 7841 #endif 7842 7843 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 7844 ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 7845 } 7846 7847 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7848 { 7849 } 7850 7851 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7852 { 7853 tcg_gen_insn_start(dcbase->pc_next); 7854 } 7855 7856 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 7857 const CPUBreakpoint *bp) 7858 { 7859 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7860 7861 gen_debug_exception(ctx); 7862 dcbase->is_jmp = DISAS_NORETURN; 7863 /* 7864 * The address covered by the breakpoint must be included in 7865 * [tb->pc, tb->pc + tb->size) in order to for it to be properly 7866 * cleared -- thus we increment the PC here so that the logic 7867 * setting tb->size below does the right thing. 7868 */ 7869 ctx->base.pc_next += 4; 7870 return true; 7871 } 7872 7873 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7874 { 7875 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7876 PowerPCCPU *cpu = POWERPC_CPU(cs); 7877 CPUPPCState *env = cs->env_ptr; 7878 opc_handler_t **table, *handler; 7879 7880 LOG_DISAS("----------------\n"); 7881 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7882 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7883 7884 ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next, 7885 need_byteswap(ctx)); 7886 7887 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7888 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 7889 opc3(ctx->opcode), opc4(ctx->opcode), 7890 ctx->le_mode ? "little" : "big"); 7891 ctx->base.pc_next += 4; 7892 table = cpu->opcodes; 7893 handler = table[opc1(ctx->opcode)]; 7894 if (is_indirect_opcode(handler)) { 7895 table = ind_table(handler); 7896 handler = table[opc2(ctx->opcode)]; 7897 if (is_indirect_opcode(handler)) { 7898 table = ind_table(handler); 7899 handler = table[opc3(ctx->opcode)]; 7900 if (is_indirect_opcode(handler)) { 7901 table = ind_table(handler); 7902 handler = table[opc4(ctx->opcode)]; 7903 } 7904 } 7905 } 7906 /* Is opcode *REALLY* valid ? */ 7907 if (unlikely(handler->handler == &gen_invalid)) { 7908 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7909 "%02x - %02x - %02x - %02x (%08x) " 7910 TARGET_FMT_lx " %d\n", 7911 opc1(ctx->opcode), opc2(ctx->opcode), 7912 opc3(ctx->opcode), opc4(ctx->opcode), 7913 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 7914 } else { 7915 uint32_t inval; 7916 7917 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7918 && Rc(ctx->opcode))) { 7919 inval = handler->inval2; 7920 } else { 7921 inval = handler->inval1; 7922 } 7923 7924 if (unlikely((ctx->opcode & inval) != 0)) { 7925 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7926 "%02x - %02x - %02x - %02x (%08x) " 7927 TARGET_FMT_lx "\n", ctx->opcode & inval, 7928 opc1(ctx->opcode), opc2(ctx->opcode), 7929 opc3(ctx->opcode), opc4(ctx->opcode), 7930 ctx->opcode, ctx->base.pc_next - 4); 7931 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7932 ctx->base.is_jmp = DISAS_NORETURN; 7933 return; 7934 } 7935 } 7936 (*(handler->handler))(ctx); 7937 #if defined(DO_PPC_STATISTICS) 7938 handler->count++; 7939 #endif 7940 /* Check trace mode exceptions */ 7941 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 7942 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 7943 ctx->exception != POWERPC_SYSCALL && 7944 ctx->exception != POWERPC_EXCP_TRAP && 7945 ctx->exception != POWERPC_EXCP_BRANCH)) { 7946 uint32_t excp = gen_prep_dbgex(ctx); 7947 gen_exception_nip(ctx, excp, ctx->base.pc_next); 7948 } 7949 7950 if (tcg_check_temp_count()) { 7951 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 7952 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 7953 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 7954 } 7955 7956 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 7957 DISAS_NEXT : DISAS_NORETURN; 7958 } 7959 7960 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7961 { 7962 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7963 7964 if (ctx->exception == POWERPC_EXCP_NONE) { 7965 gen_goto_tb(ctx, 0, ctx->base.pc_next); 7966 } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 7967 if (unlikely(ctx->base.singlestep_enabled)) { 7968 gen_debug_exception(ctx); 7969 } 7970 /* Generate the return instruction */ 7971 tcg_gen_exit_tb(NULL, 0); 7972 } 7973 } 7974 7975 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 7976 { 7977 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 7978 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 7979 } 7980 7981 static const TranslatorOps ppc_tr_ops = { 7982 .init_disas_context = ppc_tr_init_disas_context, 7983 .tb_start = ppc_tr_tb_start, 7984 .insn_start = ppc_tr_insn_start, 7985 .breakpoint_check = ppc_tr_breakpoint_check, 7986 .translate_insn = ppc_tr_translate_insn, 7987 .tb_stop = ppc_tr_tb_stop, 7988 .disas_log = ppc_tr_disas_log, 7989 }; 7990 7991 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 7992 { 7993 DisasContext ctx; 7994 7995 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 7996 } 7997 7998 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7999 target_ulong *data) 8000 { 8001 env->nip = data[0]; 8002 } 8003