1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 #include "qemu/main-loop.h" 30 #include "exec/cpu_ldst.h" 31 32 #include "exec/helper-proto.h" 33 #include "exec/helper-gen.h" 34 35 #include "exec/translator.h" 36 #include "exec/log.h" 37 #include "qemu/atomic128.h" 38 #include "spr_common.h" 39 #include "power8-pmu.h" 40 41 #include "qemu/qemu-print.h" 42 #include "qapi/error.h" 43 44 #define HELPER_H "helper.h" 45 #include "exec/helper-info.c.inc" 46 #undef HELPER_H 47 48 #define CPU_SINGLE_STEP 0x1 49 #define CPU_BRANCH_STEP 0x2 50 51 /* Include definitions for instructions classes and implementations flags */ 52 /* #define PPC_DEBUG_DISAS */ 53 54 #ifdef PPC_DEBUG_DISAS 55 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 56 #else 57 # define LOG_DISAS(...) do { } while (0) 58 #endif 59 /*****************************************************************************/ 60 /* Code translation helpers */ 61 62 /* global register indexes */ 63 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 64 + 10 * 4 + 22 * 5 /* SPE GPRh */ 65 + 8 * 5 /* CRF */]; 66 static TCGv cpu_gpr[32]; 67 static TCGv cpu_gprh[32]; 68 static TCGv_i32 cpu_crf[8]; 69 static TCGv cpu_nip; 70 static TCGv cpu_msr; 71 static TCGv cpu_ctr; 72 static TCGv cpu_lr; 73 #if defined(TARGET_PPC64) 74 static TCGv cpu_cfar; 75 #endif 76 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 77 static TCGv cpu_reserve; 78 static TCGv cpu_reserve_length; 79 static TCGv cpu_reserve_val; 80 static TCGv cpu_reserve_val2; 81 static TCGv cpu_fpscr; 82 static TCGv_i32 cpu_access_type; 83 84 void ppc_translate_init(void) 85 { 86 int i; 87 char *p; 88 size_t cpu_reg_names_size; 89 90 p = cpu_reg_names; 91 cpu_reg_names_size = sizeof(cpu_reg_names); 92 93 for (i = 0; i < 8; i++) { 94 snprintf(p, cpu_reg_names_size, "crf%d", i); 95 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 96 offsetof(CPUPPCState, crf[i]), p); 97 p += 5; 98 cpu_reg_names_size -= 5; 99 } 100 101 for (i = 0; i < 32; i++) { 102 snprintf(p, cpu_reg_names_size, "r%d", i); 103 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 104 offsetof(CPUPPCState, gpr[i]), p); 105 p += (i < 10) ? 3 : 4; 106 cpu_reg_names_size -= (i < 10) ? 3 : 4; 107 snprintf(p, cpu_reg_names_size, "r%dH", i); 108 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 109 offsetof(CPUPPCState, gprh[i]), p); 110 p += (i < 10) ? 4 : 5; 111 cpu_reg_names_size -= (i < 10) ? 4 : 5; 112 } 113 114 cpu_nip = tcg_global_mem_new(cpu_env, 115 offsetof(CPUPPCState, nip), "nip"); 116 117 cpu_msr = tcg_global_mem_new(cpu_env, 118 offsetof(CPUPPCState, msr), "msr"); 119 120 cpu_ctr = tcg_global_mem_new(cpu_env, 121 offsetof(CPUPPCState, ctr), "ctr"); 122 123 cpu_lr = tcg_global_mem_new(cpu_env, 124 offsetof(CPUPPCState, lr), "lr"); 125 126 #if defined(TARGET_PPC64) 127 cpu_cfar = tcg_global_mem_new(cpu_env, 128 offsetof(CPUPPCState, cfar), "cfar"); 129 #endif 130 131 cpu_xer = tcg_global_mem_new(cpu_env, 132 offsetof(CPUPPCState, xer), "xer"); 133 cpu_so = tcg_global_mem_new(cpu_env, 134 offsetof(CPUPPCState, so), "SO"); 135 cpu_ov = tcg_global_mem_new(cpu_env, 136 offsetof(CPUPPCState, ov), "OV"); 137 cpu_ca = tcg_global_mem_new(cpu_env, 138 offsetof(CPUPPCState, ca), "CA"); 139 cpu_ov32 = tcg_global_mem_new(cpu_env, 140 offsetof(CPUPPCState, ov32), "OV32"); 141 cpu_ca32 = tcg_global_mem_new(cpu_env, 142 offsetof(CPUPPCState, ca32), "CA32"); 143 144 cpu_reserve = tcg_global_mem_new(cpu_env, 145 offsetof(CPUPPCState, reserve_addr), 146 "reserve_addr"); 147 cpu_reserve_length = tcg_global_mem_new(cpu_env, 148 offsetof(CPUPPCState, 149 reserve_length), 150 "reserve_length"); 151 cpu_reserve_val = tcg_global_mem_new(cpu_env, 152 offsetof(CPUPPCState, reserve_val), 153 "reserve_val"); 154 cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 155 offsetof(CPUPPCState, reserve_val2), 156 "reserve_val2"); 157 158 cpu_fpscr = tcg_global_mem_new(cpu_env, 159 offsetof(CPUPPCState, fpscr), "fpscr"); 160 161 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 162 offsetof(CPUPPCState, access_type), 163 "access_type"); 164 } 165 166 /* internal defines */ 167 struct DisasContext { 168 DisasContextBase base; 169 target_ulong cia; /* current instruction address */ 170 uint32_t opcode; 171 /* Routine used to access memory */ 172 bool pr, hv, dr, le_mode; 173 bool lazy_tlb_flush; 174 bool need_access_type; 175 int mem_idx; 176 int access_type; 177 /* Translation flags */ 178 MemOp default_tcg_memop_mask; 179 #if defined(TARGET_PPC64) 180 bool sf_mode; 181 bool has_cfar; 182 #endif 183 bool fpu_enabled; 184 bool altivec_enabled; 185 bool vsx_enabled; 186 bool spe_enabled; 187 bool tm_enabled; 188 bool gtse; 189 bool hr; 190 bool mmcr0_pmcc0; 191 bool mmcr0_pmcc1; 192 bool mmcr0_pmcjce; 193 bool pmc_other; 194 bool pmu_insn_cnt; 195 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 196 int singlestep_enabled; 197 uint32_t flags; 198 uint64_t insns_flags; 199 uint64_t insns_flags2; 200 }; 201 202 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 203 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 204 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 205 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 206 207 /* Return true iff byteswap is needed in a scalar memop */ 208 static inline bool need_byteswap(const DisasContext *ctx) 209 { 210 #if TARGET_BIG_ENDIAN 211 return ctx->le_mode; 212 #else 213 return !ctx->le_mode; 214 #endif 215 } 216 217 /* True when active word size < size of target_long. */ 218 #ifdef TARGET_PPC64 219 # define NARROW_MODE(C) (!(C)->sf_mode) 220 #else 221 # define NARROW_MODE(C) 0 222 #endif 223 224 struct opc_handler_t { 225 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 226 uint32_t inval1; 227 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 228 uint32_t inval2; 229 /* instruction type */ 230 uint64_t type; 231 /* extended instruction type */ 232 uint64_t type2; 233 /* handler */ 234 void (*handler)(DisasContext *ctx); 235 }; 236 237 /* SPR load/store helpers */ 238 static inline void gen_load_spr(TCGv t, int reg) 239 { 240 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 241 } 242 243 static inline void gen_store_spr(int reg, TCGv t) 244 { 245 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 246 } 247 248 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 249 { 250 if (ctx->need_access_type && ctx->access_type != access_type) { 251 tcg_gen_movi_i32(cpu_access_type, access_type); 252 ctx->access_type = access_type; 253 } 254 } 255 256 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 257 { 258 if (NARROW_MODE(ctx)) { 259 nip = (uint32_t)nip; 260 } 261 tcg_gen_movi_tl(cpu_nip, nip); 262 } 263 264 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 265 { 266 TCGv_i32 t0, t1; 267 268 /* 269 * These are all synchronous exceptions, we set the PC back to the 270 * faulting instruction 271 */ 272 gen_update_nip(ctx, ctx->cia); 273 t0 = tcg_constant_i32(excp); 274 t1 = tcg_constant_i32(error); 275 gen_helper_raise_exception_err(cpu_env, t0, t1); 276 ctx->base.is_jmp = DISAS_NORETURN; 277 } 278 279 static void gen_exception(DisasContext *ctx, uint32_t excp) 280 { 281 TCGv_i32 t0; 282 283 /* 284 * These are all synchronous exceptions, we set the PC back to the 285 * faulting instruction 286 */ 287 gen_update_nip(ctx, ctx->cia); 288 t0 = tcg_constant_i32(excp); 289 gen_helper_raise_exception(cpu_env, t0); 290 ctx->base.is_jmp = DISAS_NORETURN; 291 } 292 293 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 294 target_ulong nip) 295 { 296 TCGv_i32 t0; 297 298 gen_update_nip(ctx, nip); 299 t0 = tcg_constant_i32(excp); 300 gen_helper_raise_exception(cpu_env, t0); 301 ctx->base.is_jmp = DISAS_NORETURN; 302 } 303 304 #if !defined(CONFIG_USER_ONLY) 305 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 306 { 307 translator_io_start(&ctx->base); 308 gen_helper_ppc_maybe_interrupt(cpu_env); 309 } 310 #endif 311 312 /* 313 * Tells the caller what is the appropriate exception to generate and prepares 314 * SPR registers for this exception. 315 * 316 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 317 * POWERPC_EXCP_DEBUG (on BookE). 318 */ 319 static uint32_t gen_prep_dbgex(DisasContext *ctx) 320 { 321 if (ctx->flags & POWERPC_FLAG_DE) { 322 target_ulong dbsr = 0; 323 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 324 dbsr = DBCR0_ICMP; 325 } else { 326 /* Must have been branch */ 327 dbsr = DBCR0_BRT; 328 } 329 TCGv t0 = tcg_temp_new(); 330 gen_load_spr(t0, SPR_BOOKE_DBSR); 331 tcg_gen_ori_tl(t0, t0, dbsr); 332 gen_store_spr(SPR_BOOKE_DBSR, t0); 333 return POWERPC_EXCP_DEBUG; 334 } else { 335 return POWERPC_EXCP_TRACE; 336 } 337 } 338 339 static void gen_debug_exception(DisasContext *ctx) 340 { 341 gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 342 ctx->base.is_jmp = DISAS_NORETURN; 343 } 344 345 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 346 { 347 /* Will be converted to program check if needed */ 348 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 349 } 350 351 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 352 { 353 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 354 } 355 356 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 357 { 358 /* Will be converted to program check if needed */ 359 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 360 } 361 362 /*****************************************************************************/ 363 /* SPR READ/WRITE CALLBACKS */ 364 365 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 366 { 367 #if 0 368 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 369 printf("ERROR: try to access SPR %d !\n", sprn); 370 #endif 371 } 372 373 /* #define PPC_DUMP_SPR_ACCESSES */ 374 375 /* 376 * Generic callbacks: 377 * do nothing but store/retrieve spr value 378 */ 379 static void spr_load_dump_spr(int sprn) 380 { 381 #ifdef PPC_DUMP_SPR_ACCESSES 382 TCGv_i32 t0 = tcg_constant_i32(sprn); 383 gen_helper_load_dump_spr(cpu_env, t0); 384 #endif 385 } 386 387 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 388 { 389 gen_load_spr(cpu_gpr[gprn], sprn); 390 spr_load_dump_spr(sprn); 391 } 392 393 static void spr_store_dump_spr(int sprn) 394 { 395 #ifdef PPC_DUMP_SPR_ACCESSES 396 TCGv_i32 t0 = tcg_constant_i32(sprn); 397 gen_helper_store_dump_spr(cpu_env, t0); 398 #endif 399 } 400 401 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 402 { 403 gen_store_spr(sprn, cpu_gpr[gprn]); 404 spr_store_dump_spr(sprn); 405 } 406 407 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 408 { 409 #ifdef TARGET_PPC64 410 TCGv t0 = tcg_temp_new(); 411 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 412 gen_store_spr(sprn, t0); 413 spr_store_dump_spr(sprn); 414 #else 415 spr_write_generic(ctx, sprn, gprn); 416 #endif 417 } 418 419 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 420 { 421 spr_write_generic32(ctx, sprn, gprn); 422 423 /* 424 * SPR_CTRL writes must force a new translation block, 425 * allowing the PMU to calculate the run latch events with 426 * more accuracy. 427 */ 428 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 429 } 430 431 #if !defined(CONFIG_USER_ONLY) 432 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 433 { 434 TCGv t0 = tcg_temp_new(); 435 TCGv t1 = tcg_temp_new(); 436 gen_load_spr(t0, sprn); 437 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 438 tcg_gen_and_tl(t0, t0, t1); 439 gen_store_spr(sprn, t0); 440 } 441 442 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 443 { 444 } 445 446 #endif 447 448 /* SPR common to all PowerPC */ 449 /* XER */ 450 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 451 { 452 TCGv dst = cpu_gpr[gprn]; 453 TCGv t0 = tcg_temp_new(); 454 TCGv t1 = tcg_temp_new(); 455 TCGv t2 = tcg_temp_new(); 456 tcg_gen_mov_tl(dst, cpu_xer); 457 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 458 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 459 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 460 tcg_gen_or_tl(t0, t0, t1); 461 tcg_gen_or_tl(dst, dst, t2); 462 tcg_gen_or_tl(dst, dst, t0); 463 if (is_isa300(ctx)) { 464 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 465 tcg_gen_or_tl(dst, dst, t0); 466 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 467 tcg_gen_or_tl(dst, dst, t0); 468 } 469 } 470 471 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 472 { 473 TCGv src = cpu_gpr[gprn]; 474 /* Write all flags, while reading back check for isa300 */ 475 tcg_gen_andi_tl(cpu_xer, src, 476 ~((1u << XER_SO) | 477 (1u << XER_OV) | (1u << XER_OV32) | 478 (1u << XER_CA) | (1u << XER_CA32))); 479 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 480 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 481 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 482 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 483 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 484 } 485 486 /* LR */ 487 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 488 { 489 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 490 } 491 492 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 493 { 494 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 495 } 496 497 /* CFAR */ 498 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 499 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 500 { 501 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 502 } 503 504 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 505 { 506 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 507 } 508 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 509 510 /* CTR */ 511 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 512 { 513 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 514 } 515 516 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 517 { 518 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 519 } 520 521 /* User read access to SPR */ 522 /* USPRx */ 523 /* UMMCRx */ 524 /* UPMCx */ 525 /* USIA */ 526 /* UDECR */ 527 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 528 { 529 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 530 } 531 532 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 533 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 534 { 535 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 536 } 537 #endif 538 539 /* SPR common to all non-embedded PowerPC */ 540 /* DECR */ 541 #if !defined(CONFIG_USER_ONLY) 542 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 543 { 544 translator_io_start(&ctx->base); 545 gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 546 } 547 548 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 549 { 550 translator_io_start(&ctx->base); 551 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 552 } 553 #endif 554 555 /* SPR common to all non-embedded PowerPC, except 601 */ 556 /* Time base */ 557 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 558 { 559 translator_io_start(&ctx->base); 560 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 561 } 562 563 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 564 { 565 translator_io_start(&ctx->base); 566 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 567 } 568 569 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 570 { 571 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 572 } 573 574 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 575 { 576 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 577 } 578 579 #if !defined(CONFIG_USER_ONLY) 580 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 581 { 582 translator_io_start(&ctx->base); 583 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 584 } 585 586 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 587 { 588 translator_io_start(&ctx->base); 589 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 590 } 591 592 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 593 { 594 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 595 } 596 597 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 598 { 599 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 600 } 601 602 #if defined(TARGET_PPC64) 603 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 604 { 605 translator_io_start(&ctx->base); 606 gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 607 } 608 609 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 610 { 611 translator_io_start(&ctx->base); 612 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 613 } 614 615 /* HDECR */ 616 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 617 { 618 translator_io_start(&ctx->base); 619 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 620 } 621 622 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 623 { 624 translator_io_start(&ctx->base); 625 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 626 } 627 628 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 629 { 630 translator_io_start(&ctx->base); 631 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 632 } 633 634 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 635 { 636 translator_io_start(&ctx->base); 637 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 638 } 639 640 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 641 { 642 translator_io_start(&ctx->base); 643 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 644 } 645 646 #endif 647 #endif 648 649 #if !defined(CONFIG_USER_ONLY) 650 /* IBAT0U...IBAT0U */ 651 /* IBAT0L...IBAT7L */ 652 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 653 { 654 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 655 offsetof(CPUPPCState, 656 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 657 } 658 659 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 660 { 661 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 662 offsetof(CPUPPCState, 663 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 664 } 665 666 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 667 { 668 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 669 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 670 } 671 672 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 673 { 674 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 675 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 676 } 677 678 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 679 { 680 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 681 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 682 } 683 684 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 685 { 686 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 687 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 688 } 689 690 /* DBAT0U...DBAT7U */ 691 /* DBAT0L...DBAT7L */ 692 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 693 { 694 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 695 offsetof(CPUPPCState, 696 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 697 } 698 699 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 700 { 701 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 702 offsetof(CPUPPCState, 703 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 704 } 705 706 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 707 { 708 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 709 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 710 } 711 712 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 713 { 714 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 715 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 716 } 717 718 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 719 { 720 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 721 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 722 } 723 724 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 725 { 726 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 727 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 728 } 729 730 /* SDR1 */ 731 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 732 { 733 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 734 } 735 736 #if defined(TARGET_PPC64) 737 /* 64 bits PowerPC specific SPRs */ 738 /* PIDR */ 739 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 740 { 741 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 742 } 743 744 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 745 { 746 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 747 } 748 749 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 750 { 751 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 752 } 753 754 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 755 { 756 TCGv t0 = tcg_temp_new(); 757 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 758 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 759 } 760 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 761 { 762 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 763 } 764 765 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 766 { 767 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 768 } 769 770 /* DPDES */ 771 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 772 { 773 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 774 } 775 776 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 777 { 778 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 779 } 780 #endif 781 #endif 782 783 /* PowerPC 40x specific registers */ 784 #if !defined(CONFIG_USER_ONLY) 785 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 786 { 787 translator_io_start(&ctx->base); 788 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 789 } 790 791 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 792 { 793 translator_io_start(&ctx->base); 794 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 795 } 796 797 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 798 { 799 translator_io_start(&ctx->base); 800 gen_store_spr(sprn, cpu_gpr[gprn]); 801 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 802 /* We must stop translation as we may have rebooted */ 803 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 804 } 805 806 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 807 { 808 translator_io_start(&ctx->base); 809 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 810 } 811 812 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 813 { 814 translator_io_start(&ctx->base); 815 gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 816 } 817 818 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 819 { 820 translator_io_start(&ctx->base); 821 gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 822 } 823 824 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 825 { 826 TCGv t0 = tcg_temp_new(); 827 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 828 gen_helper_store_40x_pid(cpu_env, t0); 829 } 830 831 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 832 { 833 translator_io_start(&ctx->base); 834 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 835 } 836 837 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 838 { 839 translator_io_start(&ctx->base); 840 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 841 } 842 #endif 843 844 /* PIR */ 845 #if !defined(CONFIG_USER_ONLY) 846 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 847 { 848 TCGv t0 = tcg_temp_new(); 849 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 850 gen_store_spr(SPR_PIR, t0); 851 } 852 #endif 853 854 /* SPE specific registers */ 855 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 856 { 857 TCGv_i32 t0 = tcg_temp_new_i32(); 858 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 859 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 860 } 861 862 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 863 { 864 TCGv_i32 t0 = tcg_temp_new_i32(); 865 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 866 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 867 } 868 869 #if !defined(CONFIG_USER_ONLY) 870 /* Callback used to write the exception vector base */ 871 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 872 { 873 TCGv t0 = tcg_temp_new(); 874 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 875 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 876 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 877 gen_store_spr(sprn, t0); 878 } 879 880 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 881 { 882 int sprn_offs; 883 884 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 885 sprn_offs = sprn - SPR_BOOKE_IVOR0; 886 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 887 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 888 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 889 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 890 } else { 891 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 892 " vector 0x%03x\n", sprn); 893 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 894 return; 895 } 896 897 TCGv t0 = tcg_temp_new(); 898 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 899 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 900 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 901 gen_store_spr(sprn, t0); 902 } 903 #endif 904 905 #ifdef TARGET_PPC64 906 #ifndef CONFIG_USER_ONLY 907 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 908 { 909 TCGv t0 = tcg_temp_new(); 910 TCGv t1 = tcg_temp_new(); 911 TCGv t2 = tcg_temp_new(); 912 913 /* 914 * Note, the HV=1 PR=0 case is handled earlier by simply using 915 * spr_write_generic for HV mode in the SPR table 916 */ 917 918 /* Build insertion mask into t1 based on context */ 919 if (ctx->pr) { 920 gen_load_spr(t1, SPR_UAMOR); 921 } else { 922 gen_load_spr(t1, SPR_AMOR); 923 } 924 925 /* Mask new bits into t2 */ 926 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 927 928 /* Load AMR and clear new bits in t0 */ 929 gen_load_spr(t0, SPR_AMR); 930 tcg_gen_andc_tl(t0, t0, t1); 931 932 /* Or'in new bits and write it out */ 933 tcg_gen_or_tl(t0, t0, t2); 934 gen_store_spr(SPR_AMR, t0); 935 spr_store_dump_spr(SPR_AMR); 936 } 937 938 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 939 { 940 TCGv t0 = tcg_temp_new(); 941 TCGv t1 = tcg_temp_new(); 942 TCGv t2 = tcg_temp_new(); 943 944 /* 945 * Note, the HV=1 case is handled earlier by simply using 946 * spr_write_generic for HV mode in the SPR table 947 */ 948 949 /* Build insertion mask into t1 based on context */ 950 gen_load_spr(t1, SPR_AMOR); 951 952 /* Mask new bits into t2 */ 953 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 954 955 /* Load AMR and clear new bits in t0 */ 956 gen_load_spr(t0, SPR_UAMOR); 957 tcg_gen_andc_tl(t0, t0, t1); 958 959 /* Or'in new bits and write it out */ 960 tcg_gen_or_tl(t0, t0, t2); 961 gen_store_spr(SPR_UAMOR, t0); 962 spr_store_dump_spr(SPR_UAMOR); 963 } 964 965 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 966 { 967 TCGv t0 = tcg_temp_new(); 968 TCGv t1 = tcg_temp_new(); 969 TCGv t2 = tcg_temp_new(); 970 971 /* 972 * Note, the HV=1 case is handled earlier by simply using 973 * spr_write_generic for HV mode in the SPR table 974 */ 975 976 /* Build insertion mask into t1 based on context */ 977 gen_load_spr(t1, SPR_AMOR); 978 979 /* Mask new bits into t2 */ 980 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 981 982 /* Load AMR and clear new bits in t0 */ 983 gen_load_spr(t0, SPR_IAMR); 984 tcg_gen_andc_tl(t0, t0, t1); 985 986 /* Or'in new bits and write it out */ 987 tcg_gen_or_tl(t0, t0, t2); 988 gen_store_spr(SPR_IAMR, t0); 989 spr_store_dump_spr(SPR_IAMR); 990 } 991 #endif 992 #endif 993 994 #ifndef CONFIG_USER_ONLY 995 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 996 { 997 gen_helper_fixup_thrm(cpu_env); 998 gen_load_spr(cpu_gpr[gprn], sprn); 999 spr_load_dump_spr(sprn); 1000 } 1001 #endif /* !CONFIG_USER_ONLY */ 1002 1003 #if !defined(CONFIG_USER_ONLY) 1004 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1005 { 1006 TCGv t0 = tcg_temp_new(); 1007 1008 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1009 gen_store_spr(sprn, t0); 1010 } 1011 1012 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1013 { 1014 TCGv t0 = tcg_temp_new(); 1015 1016 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1017 gen_store_spr(sprn, t0); 1018 } 1019 1020 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1021 { 1022 TCGv t0 = tcg_temp_new(); 1023 1024 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1025 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1026 gen_store_spr(sprn, t0); 1027 } 1028 1029 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1030 { 1031 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1032 } 1033 1034 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1035 { 1036 TCGv_i32 t0 = tcg_constant_i32(sprn); 1037 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1038 } 1039 1040 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1041 { 1042 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1043 } 1044 1045 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1046 { 1047 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1048 } 1049 1050 #endif 1051 1052 #if !defined(CONFIG_USER_ONLY) 1053 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1054 { 1055 TCGv val = tcg_temp_new(); 1056 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1057 gen_store_spr(SPR_BOOKE_MAS3, val); 1058 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1059 gen_store_spr(SPR_BOOKE_MAS7, val); 1060 } 1061 1062 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1063 { 1064 TCGv mas7 = tcg_temp_new(); 1065 TCGv mas3 = tcg_temp_new(); 1066 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1067 tcg_gen_shli_tl(mas7, mas7, 32); 1068 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1069 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1070 } 1071 1072 #endif 1073 1074 #ifdef TARGET_PPC64 1075 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1076 int bit, int sprn, int cause) 1077 { 1078 TCGv_i32 t1 = tcg_constant_i32(bit); 1079 TCGv_i32 t2 = tcg_constant_i32(sprn); 1080 TCGv_i32 t3 = tcg_constant_i32(cause); 1081 1082 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 1083 } 1084 1085 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1086 int bit, int sprn, int cause) 1087 { 1088 TCGv_i32 t1 = tcg_constant_i32(bit); 1089 TCGv_i32 t2 = tcg_constant_i32(sprn); 1090 TCGv_i32 t3 = tcg_constant_i32(cause); 1091 1092 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 1093 } 1094 1095 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1096 { 1097 TCGv spr_up = tcg_temp_new(); 1098 TCGv spr = tcg_temp_new(); 1099 1100 gen_load_spr(spr, sprn - 1); 1101 tcg_gen_shri_tl(spr_up, spr, 32); 1102 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1103 } 1104 1105 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1106 { 1107 TCGv spr = tcg_temp_new(); 1108 1109 gen_load_spr(spr, sprn - 1); 1110 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1111 gen_store_spr(sprn - 1, spr); 1112 } 1113 1114 #if !defined(CONFIG_USER_ONLY) 1115 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1116 { 1117 TCGv hmer = tcg_temp_new(); 1118 1119 gen_load_spr(hmer, sprn); 1120 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1121 gen_store_spr(sprn, hmer); 1122 spr_store_dump_spr(sprn); 1123 } 1124 1125 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1126 { 1127 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 1128 } 1129 #endif /* !defined(CONFIG_USER_ONLY) */ 1130 1131 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1132 { 1133 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1134 spr_read_generic(ctx, gprn, sprn); 1135 } 1136 1137 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1138 { 1139 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1140 spr_write_generic(ctx, sprn, gprn); 1141 } 1142 1143 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1144 { 1145 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1146 spr_read_generic(ctx, gprn, sprn); 1147 } 1148 1149 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1150 { 1151 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1152 spr_write_generic(ctx, sprn, gprn); 1153 } 1154 1155 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1156 { 1157 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1158 spr_read_prev_upper32(ctx, gprn, sprn); 1159 } 1160 1161 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1162 { 1163 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1164 spr_write_prev_upper32(ctx, sprn, gprn); 1165 } 1166 1167 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1168 { 1169 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1170 spr_read_generic(ctx, gprn, sprn); 1171 } 1172 1173 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1174 { 1175 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1176 spr_write_generic(ctx, sprn, gprn); 1177 } 1178 1179 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1180 { 1181 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1182 spr_read_prev_upper32(ctx, gprn, sprn); 1183 } 1184 1185 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1186 { 1187 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1188 spr_write_prev_upper32(ctx, sprn, gprn); 1189 } 1190 1191 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1192 { 1193 TCGv t0 = tcg_temp_new(); 1194 1195 /* 1196 * Access to the (H)DEXCR in problem state is done using separated 1197 * SPR indexes which are 16 below the SPR indexes which have full 1198 * access to the (H)DEXCR in privileged state. Problem state can 1199 * only read bits 32:63, bits 0:31 return 0. 1200 * 1201 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1202 */ 1203 1204 gen_load_spr(t0, sprn + 16); 1205 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1206 } 1207 #endif 1208 1209 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1210 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1211 1212 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1213 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1214 1215 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1216 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1217 1218 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1219 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1220 1221 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1222 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1223 1224 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1225 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1226 1227 typedef struct opcode_t { 1228 unsigned char opc1, opc2, opc3, opc4; 1229 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1230 unsigned char pad[4]; 1231 #endif 1232 opc_handler_t handler; 1233 const char *oname; 1234 } opcode_t; 1235 1236 static void gen_priv_opc(DisasContext *ctx) 1237 { 1238 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1239 } 1240 1241 /* Helpers for priv. check */ 1242 #define GEN_PRIV(CTX) \ 1243 do { \ 1244 gen_priv_opc(CTX); return; \ 1245 } while (0) 1246 1247 #if defined(CONFIG_USER_ONLY) 1248 #define CHK_HV(CTX) GEN_PRIV(CTX) 1249 #define CHK_SV(CTX) GEN_PRIV(CTX) 1250 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1251 #else 1252 #define CHK_HV(CTX) \ 1253 do { \ 1254 if (unlikely(ctx->pr || !ctx->hv)) {\ 1255 GEN_PRIV(CTX); \ 1256 } \ 1257 } while (0) 1258 #define CHK_SV(CTX) \ 1259 do { \ 1260 if (unlikely(ctx->pr)) { \ 1261 GEN_PRIV(CTX); \ 1262 } \ 1263 } while (0) 1264 #define CHK_HVRM(CTX) \ 1265 do { \ 1266 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1267 GEN_PRIV(CTX); \ 1268 } \ 1269 } while (0) 1270 #endif 1271 1272 #define CHK_NONE(CTX) 1273 1274 /*****************************************************************************/ 1275 /* PowerPC instructions table */ 1276 1277 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1278 { \ 1279 .opc1 = op1, \ 1280 .opc2 = op2, \ 1281 .opc3 = op3, \ 1282 .opc4 = 0xff, \ 1283 .handler = { \ 1284 .inval1 = invl, \ 1285 .type = _typ, \ 1286 .type2 = _typ2, \ 1287 .handler = &gen_##name, \ 1288 }, \ 1289 .oname = stringify(name), \ 1290 } 1291 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1292 { \ 1293 .opc1 = op1, \ 1294 .opc2 = op2, \ 1295 .opc3 = op3, \ 1296 .opc4 = 0xff, \ 1297 .handler = { \ 1298 .inval1 = invl1, \ 1299 .inval2 = invl2, \ 1300 .type = _typ, \ 1301 .type2 = _typ2, \ 1302 .handler = &gen_##name, \ 1303 }, \ 1304 .oname = stringify(name), \ 1305 } 1306 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1307 { \ 1308 .opc1 = op1, \ 1309 .opc2 = op2, \ 1310 .opc3 = op3, \ 1311 .opc4 = 0xff, \ 1312 .handler = { \ 1313 .inval1 = invl, \ 1314 .type = _typ, \ 1315 .type2 = _typ2, \ 1316 .handler = &gen_##name, \ 1317 }, \ 1318 .oname = onam, \ 1319 } 1320 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1321 { \ 1322 .opc1 = op1, \ 1323 .opc2 = op2, \ 1324 .opc3 = op3, \ 1325 .opc4 = op4, \ 1326 .handler = { \ 1327 .inval1 = invl, \ 1328 .type = _typ, \ 1329 .type2 = _typ2, \ 1330 .handler = &gen_##name, \ 1331 }, \ 1332 .oname = stringify(name), \ 1333 } 1334 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1335 { \ 1336 .opc1 = op1, \ 1337 .opc2 = op2, \ 1338 .opc3 = op3, \ 1339 .opc4 = op4, \ 1340 .handler = { \ 1341 .inval1 = invl, \ 1342 .type = _typ, \ 1343 .type2 = _typ2, \ 1344 .handler = &gen_##name, \ 1345 }, \ 1346 .oname = onam, \ 1347 } 1348 1349 /* Invalid instruction */ 1350 static void gen_invalid(DisasContext *ctx) 1351 { 1352 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1353 } 1354 1355 static opc_handler_t invalid_handler = { 1356 .inval1 = 0xFFFFFFFF, 1357 .inval2 = 0xFFFFFFFF, 1358 .type = PPC_NONE, 1359 .type2 = PPC_NONE, 1360 .handler = gen_invalid, 1361 }; 1362 1363 /*** Integer comparison ***/ 1364 1365 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1366 { 1367 TCGv t0 = tcg_temp_new(); 1368 TCGv t1 = tcg_temp_new(); 1369 TCGv_i32 t = tcg_temp_new_i32(); 1370 1371 tcg_gen_movi_tl(t0, CRF_EQ); 1372 tcg_gen_movi_tl(t1, CRF_LT); 1373 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1374 t0, arg0, arg1, t1, t0); 1375 tcg_gen_movi_tl(t1, CRF_GT); 1376 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1377 t0, arg0, arg1, t1, t0); 1378 1379 tcg_gen_trunc_tl_i32(t, t0); 1380 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1381 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1382 } 1383 1384 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1385 { 1386 TCGv t0 = tcg_constant_tl(arg1); 1387 gen_op_cmp(arg0, t0, s, crf); 1388 } 1389 1390 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1391 { 1392 TCGv t0, t1; 1393 t0 = tcg_temp_new(); 1394 t1 = tcg_temp_new(); 1395 if (s) { 1396 tcg_gen_ext32s_tl(t0, arg0); 1397 tcg_gen_ext32s_tl(t1, arg1); 1398 } else { 1399 tcg_gen_ext32u_tl(t0, arg0); 1400 tcg_gen_ext32u_tl(t1, arg1); 1401 } 1402 gen_op_cmp(t0, t1, s, crf); 1403 } 1404 1405 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1406 { 1407 TCGv t0 = tcg_constant_tl(arg1); 1408 gen_op_cmp32(arg0, t0, s, crf); 1409 } 1410 1411 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1412 { 1413 if (NARROW_MODE(ctx)) { 1414 gen_op_cmpi32(reg, 0, 1, 0); 1415 } else { 1416 gen_op_cmpi(reg, 0, 1, 0); 1417 } 1418 } 1419 1420 /* cmprb - range comparison: isupper, isaplha, islower*/ 1421 static void gen_cmprb(DisasContext *ctx) 1422 { 1423 TCGv_i32 src1 = tcg_temp_new_i32(); 1424 TCGv_i32 src2 = tcg_temp_new_i32(); 1425 TCGv_i32 src2lo = tcg_temp_new_i32(); 1426 TCGv_i32 src2hi = tcg_temp_new_i32(); 1427 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1428 1429 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1430 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1431 1432 tcg_gen_andi_i32(src1, src1, 0xFF); 1433 tcg_gen_ext8u_i32(src2lo, src2); 1434 tcg_gen_shri_i32(src2, src2, 8); 1435 tcg_gen_ext8u_i32(src2hi, src2); 1436 1437 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1438 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1439 tcg_gen_and_i32(crf, src2lo, src2hi); 1440 1441 if (ctx->opcode & 0x00200000) { 1442 tcg_gen_shri_i32(src2, src2, 8); 1443 tcg_gen_ext8u_i32(src2lo, src2); 1444 tcg_gen_shri_i32(src2, src2, 8); 1445 tcg_gen_ext8u_i32(src2hi, src2); 1446 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1447 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1448 tcg_gen_and_i32(src2lo, src2lo, src2hi); 1449 tcg_gen_or_i32(crf, crf, src2lo); 1450 } 1451 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1452 } 1453 1454 #if defined(TARGET_PPC64) 1455 /* cmpeqb */ 1456 static void gen_cmpeqb(DisasContext *ctx) 1457 { 1458 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1459 cpu_gpr[rB(ctx->opcode)]); 1460 } 1461 #endif 1462 1463 /* isel (PowerPC 2.03 specification) */ 1464 static void gen_isel(DisasContext *ctx) 1465 { 1466 uint32_t bi = rC(ctx->opcode); 1467 uint32_t mask = 0x08 >> (bi & 0x03); 1468 TCGv t0 = tcg_temp_new(); 1469 TCGv zr; 1470 1471 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1472 tcg_gen_andi_tl(t0, t0, mask); 1473 1474 zr = tcg_constant_tl(0); 1475 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1476 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1477 cpu_gpr[rB(ctx->opcode)]); 1478 } 1479 1480 /* cmpb: PowerPC 2.05 specification */ 1481 static void gen_cmpb(DisasContext *ctx) 1482 { 1483 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1484 cpu_gpr[rB(ctx->opcode)]); 1485 } 1486 1487 /*** Integer arithmetic ***/ 1488 1489 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1490 TCGv arg1, TCGv arg2, int sub) 1491 { 1492 TCGv t0 = tcg_temp_new(); 1493 1494 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1495 tcg_gen_xor_tl(t0, arg1, arg2); 1496 if (sub) { 1497 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1498 } else { 1499 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1500 } 1501 if (NARROW_MODE(ctx)) { 1502 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1503 if (is_isa300(ctx)) { 1504 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1505 } 1506 } else { 1507 if (is_isa300(ctx)) { 1508 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1509 } 1510 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1511 } 1512 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1513 } 1514 1515 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1516 TCGv res, TCGv arg0, TCGv arg1, 1517 TCGv ca32, int sub) 1518 { 1519 TCGv t0; 1520 1521 if (!is_isa300(ctx)) { 1522 return; 1523 } 1524 1525 t0 = tcg_temp_new(); 1526 if (sub) { 1527 tcg_gen_eqv_tl(t0, arg0, arg1); 1528 } else { 1529 tcg_gen_xor_tl(t0, arg0, arg1); 1530 } 1531 tcg_gen_xor_tl(t0, t0, res); 1532 tcg_gen_extract_tl(ca32, t0, 32, 1); 1533 } 1534 1535 /* Common add function */ 1536 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1537 TCGv arg2, TCGv ca, TCGv ca32, 1538 bool add_ca, bool compute_ca, 1539 bool compute_ov, bool compute_rc0) 1540 { 1541 TCGv t0 = ret; 1542 1543 if (compute_ca || compute_ov) { 1544 t0 = tcg_temp_new(); 1545 } 1546 1547 if (compute_ca) { 1548 if (NARROW_MODE(ctx)) { 1549 /* 1550 * Caution: a non-obvious corner case of the spec is that 1551 * we must produce the *entire* 64-bit addition, but 1552 * produce the carry into bit 32. 1553 */ 1554 TCGv t1 = tcg_temp_new(); 1555 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1556 tcg_gen_add_tl(t0, arg1, arg2); 1557 if (add_ca) { 1558 tcg_gen_add_tl(t0, t0, ca); 1559 } 1560 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1561 tcg_gen_extract_tl(ca, ca, 32, 1); 1562 if (is_isa300(ctx)) { 1563 tcg_gen_mov_tl(ca32, ca); 1564 } 1565 } else { 1566 TCGv zero = tcg_constant_tl(0); 1567 if (add_ca) { 1568 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1569 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1570 } else { 1571 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1572 } 1573 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1574 } 1575 } else { 1576 tcg_gen_add_tl(t0, arg1, arg2); 1577 if (add_ca) { 1578 tcg_gen_add_tl(t0, t0, ca); 1579 } 1580 } 1581 1582 if (compute_ov) { 1583 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1584 } 1585 if (unlikely(compute_rc0)) { 1586 gen_set_Rc0(ctx, t0); 1587 } 1588 1589 if (t0 != ret) { 1590 tcg_gen_mov_tl(ret, t0); 1591 } 1592 } 1593 /* Add functions with two operands */ 1594 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1595 static void glue(gen_, name)(DisasContext *ctx) \ 1596 { \ 1597 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1598 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1599 ca, glue(ca, 32), \ 1600 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1601 } 1602 /* Add functions with one operand and one immediate */ 1603 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1604 add_ca, compute_ca, compute_ov) \ 1605 static void glue(gen_, name)(DisasContext *ctx) \ 1606 { \ 1607 TCGv t0 = tcg_constant_tl(const_val); \ 1608 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1609 cpu_gpr[rA(ctx->opcode)], t0, \ 1610 ca, glue(ca, 32), \ 1611 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1612 } 1613 1614 /* add add. addo addo. */ 1615 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 1616 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1617 /* addc addc. addco addco. */ 1618 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 1619 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1620 /* adde adde. addeo addeo. */ 1621 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 1622 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1623 /* addme addme. addmeo addmeo. */ 1624 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 1625 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 1626 /* addex */ 1627 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1628 /* addze addze. addzeo addzeo.*/ 1629 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 1630 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1631 /* addic addic.*/ 1632 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1633 { 1634 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1635 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1636 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1637 } 1638 1639 static void gen_addic(DisasContext *ctx) 1640 { 1641 gen_op_addic(ctx, 0); 1642 } 1643 1644 static void gen_addic_(DisasContext *ctx) 1645 { 1646 gen_op_addic(ctx, 1); 1647 } 1648 1649 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1650 TCGv arg2, int sign, int compute_ov) 1651 { 1652 TCGv_i32 t0 = tcg_temp_new_i32(); 1653 TCGv_i32 t1 = tcg_temp_new_i32(); 1654 TCGv_i32 t2 = tcg_temp_new_i32(); 1655 TCGv_i32 t3 = tcg_temp_new_i32(); 1656 1657 tcg_gen_trunc_tl_i32(t0, arg1); 1658 tcg_gen_trunc_tl_i32(t1, arg2); 1659 if (sign) { 1660 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1661 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1662 tcg_gen_and_i32(t2, t2, t3); 1663 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1664 tcg_gen_or_i32(t2, t2, t3); 1665 tcg_gen_movi_i32(t3, 0); 1666 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1667 tcg_gen_div_i32(t3, t0, t1); 1668 tcg_gen_extu_i32_tl(ret, t3); 1669 } else { 1670 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1671 tcg_gen_movi_i32(t3, 0); 1672 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1673 tcg_gen_divu_i32(t3, t0, t1); 1674 tcg_gen_extu_i32_tl(ret, t3); 1675 } 1676 if (compute_ov) { 1677 tcg_gen_extu_i32_tl(cpu_ov, t2); 1678 if (is_isa300(ctx)) { 1679 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1680 } 1681 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1682 } 1683 1684 if (unlikely(Rc(ctx->opcode) != 0)) { 1685 gen_set_Rc0(ctx, ret); 1686 } 1687 } 1688 /* Div functions */ 1689 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1690 static void glue(gen_, name)(DisasContext *ctx) \ 1691 { \ 1692 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1693 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1694 sign, compute_ov); \ 1695 } 1696 /* divwu divwu. divwuo divwuo. */ 1697 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1698 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1699 /* divw divw. divwo divwo. */ 1700 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1701 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1702 1703 /* div[wd]eu[o][.] */ 1704 #define GEN_DIVE(name, hlpr, compute_ov) \ 1705 static void gen_##name(DisasContext *ctx) \ 1706 { \ 1707 TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1708 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1709 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1710 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1711 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1712 } \ 1713 } 1714 1715 GEN_DIVE(divweu, divweu, 0); 1716 GEN_DIVE(divweuo, divweu, 1); 1717 GEN_DIVE(divwe, divwe, 0); 1718 GEN_DIVE(divweo, divwe, 1); 1719 1720 #if defined(TARGET_PPC64) 1721 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1722 TCGv arg2, int sign, int compute_ov) 1723 { 1724 TCGv_i64 t0 = tcg_temp_new_i64(); 1725 TCGv_i64 t1 = tcg_temp_new_i64(); 1726 TCGv_i64 t2 = tcg_temp_new_i64(); 1727 TCGv_i64 t3 = tcg_temp_new_i64(); 1728 1729 tcg_gen_mov_i64(t0, arg1); 1730 tcg_gen_mov_i64(t1, arg2); 1731 if (sign) { 1732 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1733 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1734 tcg_gen_and_i64(t2, t2, t3); 1735 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1736 tcg_gen_or_i64(t2, t2, t3); 1737 tcg_gen_movi_i64(t3, 0); 1738 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1739 tcg_gen_div_i64(ret, t0, t1); 1740 } else { 1741 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1742 tcg_gen_movi_i64(t3, 0); 1743 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1744 tcg_gen_divu_i64(ret, t0, t1); 1745 } 1746 if (compute_ov) { 1747 tcg_gen_mov_tl(cpu_ov, t2); 1748 if (is_isa300(ctx)) { 1749 tcg_gen_mov_tl(cpu_ov32, t2); 1750 } 1751 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1752 } 1753 1754 if (unlikely(Rc(ctx->opcode) != 0)) { 1755 gen_set_Rc0(ctx, ret); 1756 } 1757 } 1758 1759 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1760 static void glue(gen_, name)(DisasContext *ctx) \ 1761 { \ 1762 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1763 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1764 sign, compute_ov); \ 1765 } 1766 /* divdu divdu. divduo divduo. */ 1767 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1768 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1769 /* divd divd. divdo divdo. */ 1770 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1771 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1772 1773 GEN_DIVE(divdeu, divdeu, 0); 1774 GEN_DIVE(divdeuo, divdeu, 1); 1775 GEN_DIVE(divde, divde, 0); 1776 GEN_DIVE(divdeo, divde, 1); 1777 #endif 1778 1779 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1780 TCGv arg2, int sign) 1781 { 1782 TCGv_i32 t0 = tcg_temp_new_i32(); 1783 TCGv_i32 t1 = tcg_temp_new_i32(); 1784 1785 tcg_gen_trunc_tl_i32(t0, arg1); 1786 tcg_gen_trunc_tl_i32(t1, arg2); 1787 if (sign) { 1788 TCGv_i32 t2 = tcg_temp_new_i32(); 1789 TCGv_i32 t3 = tcg_temp_new_i32(); 1790 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1791 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1792 tcg_gen_and_i32(t2, t2, t3); 1793 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1794 tcg_gen_or_i32(t2, t2, t3); 1795 tcg_gen_movi_i32(t3, 0); 1796 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1797 tcg_gen_rem_i32(t3, t0, t1); 1798 tcg_gen_ext_i32_tl(ret, t3); 1799 } else { 1800 TCGv_i32 t2 = tcg_constant_i32(1); 1801 TCGv_i32 t3 = tcg_constant_i32(0); 1802 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1803 tcg_gen_remu_i32(t0, t0, t1); 1804 tcg_gen_extu_i32_tl(ret, t0); 1805 } 1806 } 1807 1808 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1809 static void glue(gen_, name)(DisasContext *ctx) \ 1810 { \ 1811 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1812 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1813 sign); \ 1814 } 1815 1816 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1817 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1818 1819 #if defined(TARGET_PPC64) 1820 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1821 TCGv arg2, int sign) 1822 { 1823 TCGv_i64 t0 = tcg_temp_new_i64(); 1824 TCGv_i64 t1 = tcg_temp_new_i64(); 1825 1826 tcg_gen_mov_i64(t0, arg1); 1827 tcg_gen_mov_i64(t1, arg2); 1828 if (sign) { 1829 TCGv_i64 t2 = tcg_temp_new_i64(); 1830 TCGv_i64 t3 = tcg_temp_new_i64(); 1831 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1832 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1833 tcg_gen_and_i64(t2, t2, t3); 1834 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1835 tcg_gen_or_i64(t2, t2, t3); 1836 tcg_gen_movi_i64(t3, 0); 1837 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1838 tcg_gen_rem_i64(ret, t0, t1); 1839 } else { 1840 TCGv_i64 t2 = tcg_constant_i64(1); 1841 TCGv_i64 t3 = tcg_constant_i64(0); 1842 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1843 tcg_gen_remu_i64(ret, t0, t1); 1844 } 1845 } 1846 1847 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1848 static void glue(gen_, name)(DisasContext *ctx) \ 1849 { \ 1850 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1851 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1852 sign); \ 1853 } 1854 1855 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1856 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1857 #endif 1858 1859 /* mulhw mulhw. */ 1860 static void gen_mulhw(DisasContext *ctx) 1861 { 1862 TCGv_i32 t0 = tcg_temp_new_i32(); 1863 TCGv_i32 t1 = tcg_temp_new_i32(); 1864 1865 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1866 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1867 tcg_gen_muls2_i32(t0, t1, t0, t1); 1868 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1869 if (unlikely(Rc(ctx->opcode) != 0)) { 1870 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1871 } 1872 } 1873 1874 /* mulhwu mulhwu. */ 1875 static void gen_mulhwu(DisasContext *ctx) 1876 { 1877 TCGv_i32 t0 = tcg_temp_new_i32(); 1878 TCGv_i32 t1 = tcg_temp_new_i32(); 1879 1880 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1881 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1882 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1883 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1884 if (unlikely(Rc(ctx->opcode) != 0)) { 1885 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1886 } 1887 } 1888 1889 /* mullw mullw. */ 1890 static void gen_mullw(DisasContext *ctx) 1891 { 1892 #if defined(TARGET_PPC64) 1893 TCGv_i64 t0, t1; 1894 t0 = tcg_temp_new_i64(); 1895 t1 = tcg_temp_new_i64(); 1896 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1897 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1898 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1899 #else 1900 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1901 cpu_gpr[rB(ctx->opcode)]); 1902 #endif 1903 if (unlikely(Rc(ctx->opcode) != 0)) { 1904 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1905 } 1906 } 1907 1908 /* mullwo mullwo. */ 1909 static void gen_mullwo(DisasContext *ctx) 1910 { 1911 TCGv_i32 t0 = tcg_temp_new_i32(); 1912 TCGv_i32 t1 = tcg_temp_new_i32(); 1913 1914 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1915 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1916 tcg_gen_muls2_i32(t0, t1, t0, t1); 1917 #if defined(TARGET_PPC64) 1918 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1919 #else 1920 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1921 #endif 1922 1923 tcg_gen_sari_i32(t0, t0, 31); 1924 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1925 tcg_gen_extu_i32_tl(cpu_ov, t0); 1926 if (is_isa300(ctx)) { 1927 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1928 } 1929 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1930 1931 if (unlikely(Rc(ctx->opcode) != 0)) { 1932 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1933 } 1934 } 1935 1936 /* mulli */ 1937 static void gen_mulli(DisasContext *ctx) 1938 { 1939 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1940 SIMM(ctx->opcode)); 1941 } 1942 1943 #if defined(TARGET_PPC64) 1944 /* mulhd mulhd. */ 1945 static void gen_mulhd(DisasContext *ctx) 1946 { 1947 TCGv lo = tcg_temp_new(); 1948 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1949 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1950 if (unlikely(Rc(ctx->opcode) != 0)) { 1951 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1952 } 1953 } 1954 1955 /* mulhdu mulhdu. */ 1956 static void gen_mulhdu(DisasContext *ctx) 1957 { 1958 TCGv lo = tcg_temp_new(); 1959 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1960 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1961 if (unlikely(Rc(ctx->opcode) != 0)) { 1962 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1963 } 1964 } 1965 1966 /* mulld mulld. */ 1967 static void gen_mulld(DisasContext *ctx) 1968 { 1969 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1970 cpu_gpr[rB(ctx->opcode)]); 1971 if (unlikely(Rc(ctx->opcode) != 0)) { 1972 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1973 } 1974 } 1975 1976 /* mulldo mulldo. */ 1977 static void gen_mulldo(DisasContext *ctx) 1978 { 1979 TCGv_i64 t0 = tcg_temp_new_i64(); 1980 TCGv_i64 t1 = tcg_temp_new_i64(); 1981 1982 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1983 cpu_gpr[rB(ctx->opcode)]); 1984 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1985 1986 tcg_gen_sari_i64(t0, t0, 63); 1987 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 1988 if (is_isa300(ctx)) { 1989 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1990 } 1991 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1992 1993 if (unlikely(Rc(ctx->opcode) != 0)) { 1994 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1995 } 1996 } 1997 #endif 1998 1999 /* Common subf function */ 2000 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2001 TCGv arg2, bool add_ca, bool compute_ca, 2002 bool compute_ov, bool compute_rc0) 2003 { 2004 TCGv t0 = ret; 2005 2006 if (compute_ca || compute_ov) { 2007 t0 = tcg_temp_new(); 2008 } 2009 2010 if (compute_ca) { 2011 /* dest = ~arg1 + arg2 [+ ca]. */ 2012 if (NARROW_MODE(ctx)) { 2013 /* 2014 * Caution: a non-obvious corner case of the spec is that 2015 * we must produce the *entire* 64-bit addition, but 2016 * produce the carry into bit 32. 2017 */ 2018 TCGv inv1 = tcg_temp_new(); 2019 TCGv t1 = tcg_temp_new(); 2020 tcg_gen_not_tl(inv1, arg1); 2021 if (add_ca) { 2022 tcg_gen_add_tl(t0, arg2, cpu_ca); 2023 } else { 2024 tcg_gen_addi_tl(t0, arg2, 1); 2025 } 2026 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2027 tcg_gen_add_tl(t0, t0, inv1); 2028 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2029 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 2030 if (is_isa300(ctx)) { 2031 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2032 } 2033 } else if (add_ca) { 2034 TCGv zero, inv1 = tcg_temp_new(); 2035 tcg_gen_not_tl(inv1, arg1); 2036 zero = tcg_constant_tl(0); 2037 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2038 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 2039 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2040 } else { 2041 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2042 tcg_gen_sub_tl(t0, arg2, arg1); 2043 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2044 } 2045 } else if (add_ca) { 2046 /* 2047 * Since we're ignoring carry-out, we can simplify the 2048 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2049 */ 2050 tcg_gen_sub_tl(t0, arg2, arg1); 2051 tcg_gen_add_tl(t0, t0, cpu_ca); 2052 tcg_gen_subi_tl(t0, t0, 1); 2053 } else { 2054 tcg_gen_sub_tl(t0, arg2, arg1); 2055 } 2056 2057 if (compute_ov) { 2058 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2059 } 2060 if (unlikely(compute_rc0)) { 2061 gen_set_Rc0(ctx, t0); 2062 } 2063 2064 if (t0 != ret) { 2065 tcg_gen_mov_tl(ret, t0); 2066 } 2067 } 2068 /* Sub functions with Two operands functions */ 2069 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2070 static void glue(gen_, name)(DisasContext *ctx) \ 2071 { \ 2072 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2073 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2074 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2075 } 2076 /* Sub functions with one operand and one immediate */ 2077 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2078 add_ca, compute_ca, compute_ov) \ 2079 static void glue(gen_, name)(DisasContext *ctx) \ 2080 { \ 2081 TCGv t0 = tcg_constant_tl(const_val); \ 2082 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2083 cpu_gpr[rA(ctx->opcode)], t0, \ 2084 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2085 } 2086 /* subf subf. subfo subfo. */ 2087 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2088 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2089 /* subfc subfc. subfco subfco. */ 2090 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2091 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2092 /* subfe subfe. subfeo subfo. */ 2093 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2094 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2095 /* subfme subfme. subfmeo subfmeo. */ 2096 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2097 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2098 /* subfze subfze. subfzeo subfzeo.*/ 2099 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2100 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2101 2102 /* subfic */ 2103 static void gen_subfic(DisasContext *ctx) 2104 { 2105 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2106 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2107 c, 0, 1, 0, 0); 2108 } 2109 2110 /* neg neg. nego nego. */ 2111 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2112 { 2113 TCGv zero = tcg_constant_tl(0); 2114 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2115 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2116 } 2117 2118 static void gen_neg(DisasContext *ctx) 2119 { 2120 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2121 if (unlikely(Rc(ctx->opcode))) { 2122 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2123 } 2124 } 2125 2126 static void gen_nego(DisasContext *ctx) 2127 { 2128 gen_op_arith_neg(ctx, 1); 2129 } 2130 2131 /*** Integer logical ***/ 2132 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2133 static void glue(gen_, name)(DisasContext *ctx) \ 2134 { \ 2135 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2136 cpu_gpr[rB(ctx->opcode)]); \ 2137 if (unlikely(Rc(ctx->opcode) != 0)) \ 2138 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2139 } 2140 2141 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2142 static void glue(gen_, name)(DisasContext *ctx) \ 2143 { \ 2144 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2145 if (unlikely(Rc(ctx->opcode) != 0)) \ 2146 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2147 } 2148 2149 /* and & and. */ 2150 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2151 /* andc & andc. */ 2152 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2153 2154 /* andi. */ 2155 static void gen_andi_(DisasContext *ctx) 2156 { 2157 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2158 UIMM(ctx->opcode)); 2159 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2160 } 2161 2162 /* andis. */ 2163 static void gen_andis_(DisasContext *ctx) 2164 { 2165 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2166 UIMM(ctx->opcode) << 16); 2167 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2168 } 2169 2170 /* cntlzw */ 2171 static void gen_cntlzw(DisasContext *ctx) 2172 { 2173 TCGv_i32 t = tcg_temp_new_i32(); 2174 2175 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2176 tcg_gen_clzi_i32(t, t, 32); 2177 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2178 2179 if (unlikely(Rc(ctx->opcode) != 0)) { 2180 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2181 } 2182 } 2183 2184 /* cnttzw */ 2185 static void gen_cnttzw(DisasContext *ctx) 2186 { 2187 TCGv_i32 t = tcg_temp_new_i32(); 2188 2189 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2190 tcg_gen_ctzi_i32(t, t, 32); 2191 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2192 2193 if (unlikely(Rc(ctx->opcode) != 0)) { 2194 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2195 } 2196 } 2197 2198 /* eqv & eqv. */ 2199 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2200 /* extsb & extsb. */ 2201 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2202 /* extsh & extsh. */ 2203 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2204 /* nand & nand. */ 2205 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2206 /* nor & nor. */ 2207 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2208 2209 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2210 static void gen_pause(DisasContext *ctx) 2211 { 2212 TCGv_i32 t0 = tcg_constant_i32(0); 2213 tcg_gen_st_i32(t0, cpu_env, 2214 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2215 2216 /* Stop translation, this gives other CPUs a chance to run */ 2217 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2218 } 2219 #endif /* defined(TARGET_PPC64) */ 2220 2221 /* or & or. */ 2222 static void gen_or(DisasContext *ctx) 2223 { 2224 int rs, ra, rb; 2225 2226 rs = rS(ctx->opcode); 2227 ra = rA(ctx->opcode); 2228 rb = rB(ctx->opcode); 2229 /* Optimisation for mr. ri case */ 2230 if (rs != ra || rs != rb) { 2231 if (rs != rb) { 2232 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2233 } else { 2234 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2235 } 2236 if (unlikely(Rc(ctx->opcode) != 0)) { 2237 gen_set_Rc0(ctx, cpu_gpr[ra]); 2238 } 2239 } else if (unlikely(Rc(ctx->opcode) != 0)) { 2240 gen_set_Rc0(ctx, cpu_gpr[rs]); 2241 #if defined(TARGET_PPC64) 2242 } else if (rs != 0) { /* 0 is nop */ 2243 int prio = 0; 2244 2245 switch (rs) { 2246 case 1: 2247 /* Set process priority to low */ 2248 prio = 2; 2249 break; 2250 case 6: 2251 /* Set process priority to medium-low */ 2252 prio = 3; 2253 break; 2254 case 2: 2255 /* Set process priority to normal */ 2256 prio = 4; 2257 break; 2258 #if !defined(CONFIG_USER_ONLY) 2259 case 31: 2260 if (!ctx->pr) { 2261 /* Set process priority to very low */ 2262 prio = 1; 2263 } 2264 break; 2265 case 5: 2266 if (!ctx->pr) { 2267 /* Set process priority to medium-hight */ 2268 prio = 5; 2269 } 2270 break; 2271 case 3: 2272 if (!ctx->pr) { 2273 /* Set process priority to high */ 2274 prio = 6; 2275 } 2276 break; 2277 case 7: 2278 if (ctx->hv && !ctx->pr) { 2279 /* Set process priority to very high */ 2280 prio = 7; 2281 } 2282 break; 2283 #endif 2284 default: 2285 break; 2286 } 2287 if (prio) { 2288 TCGv t0 = tcg_temp_new(); 2289 gen_load_spr(t0, SPR_PPR); 2290 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2291 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2292 gen_store_spr(SPR_PPR, t0); 2293 } 2294 #if !defined(CONFIG_USER_ONLY) 2295 /* 2296 * Pause out of TCG otherwise spin loops with smt_low eat too 2297 * much CPU and the kernel hangs. This applies to all 2298 * encodings other than no-op, e.g., miso(rs=26), yield(27), 2299 * mdoio(29), mdoom(30), and all currently undefined. 2300 */ 2301 gen_pause(ctx); 2302 #endif 2303 #endif 2304 } 2305 } 2306 /* orc & orc. */ 2307 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2308 2309 /* xor & xor. */ 2310 static void gen_xor(DisasContext *ctx) 2311 { 2312 /* Optimisation for "set to zero" case */ 2313 if (rS(ctx->opcode) != rB(ctx->opcode)) { 2314 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2315 cpu_gpr[rB(ctx->opcode)]); 2316 } else { 2317 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2318 } 2319 if (unlikely(Rc(ctx->opcode) != 0)) { 2320 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2321 } 2322 } 2323 2324 /* ori */ 2325 static void gen_ori(DisasContext *ctx) 2326 { 2327 target_ulong uimm = UIMM(ctx->opcode); 2328 2329 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2330 return; 2331 } 2332 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2333 } 2334 2335 /* oris */ 2336 static void gen_oris(DisasContext *ctx) 2337 { 2338 target_ulong uimm = UIMM(ctx->opcode); 2339 2340 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2341 /* NOP */ 2342 return; 2343 } 2344 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2345 uimm << 16); 2346 } 2347 2348 /* xori */ 2349 static void gen_xori(DisasContext *ctx) 2350 { 2351 target_ulong uimm = UIMM(ctx->opcode); 2352 2353 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2354 /* NOP */ 2355 return; 2356 } 2357 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2358 } 2359 2360 /* xoris */ 2361 static void gen_xoris(DisasContext *ctx) 2362 { 2363 target_ulong uimm = UIMM(ctx->opcode); 2364 2365 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2366 /* NOP */ 2367 return; 2368 } 2369 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2370 uimm << 16); 2371 } 2372 2373 /* popcntb : PowerPC 2.03 specification */ 2374 static void gen_popcntb(DisasContext *ctx) 2375 { 2376 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2377 } 2378 2379 static void gen_popcntw(DisasContext *ctx) 2380 { 2381 #if defined(TARGET_PPC64) 2382 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2383 #else 2384 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2385 #endif 2386 } 2387 2388 #if defined(TARGET_PPC64) 2389 /* popcntd: PowerPC 2.06 specification */ 2390 static void gen_popcntd(DisasContext *ctx) 2391 { 2392 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2393 } 2394 #endif 2395 2396 /* prtyw: PowerPC 2.05 specification */ 2397 static void gen_prtyw(DisasContext *ctx) 2398 { 2399 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2400 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2401 TCGv t0 = tcg_temp_new(); 2402 tcg_gen_shri_tl(t0, rs, 16); 2403 tcg_gen_xor_tl(ra, rs, t0); 2404 tcg_gen_shri_tl(t0, ra, 8); 2405 tcg_gen_xor_tl(ra, ra, t0); 2406 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2407 } 2408 2409 #if defined(TARGET_PPC64) 2410 /* prtyd: PowerPC 2.05 specification */ 2411 static void gen_prtyd(DisasContext *ctx) 2412 { 2413 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2414 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2415 TCGv t0 = tcg_temp_new(); 2416 tcg_gen_shri_tl(t0, rs, 32); 2417 tcg_gen_xor_tl(ra, rs, t0); 2418 tcg_gen_shri_tl(t0, ra, 16); 2419 tcg_gen_xor_tl(ra, ra, t0); 2420 tcg_gen_shri_tl(t0, ra, 8); 2421 tcg_gen_xor_tl(ra, ra, t0); 2422 tcg_gen_andi_tl(ra, ra, 1); 2423 } 2424 #endif 2425 2426 #if defined(TARGET_PPC64) 2427 /* bpermd */ 2428 static void gen_bpermd(DisasContext *ctx) 2429 { 2430 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2431 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2432 } 2433 #endif 2434 2435 #if defined(TARGET_PPC64) 2436 /* extsw & extsw. */ 2437 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2438 2439 /* cntlzd */ 2440 static void gen_cntlzd(DisasContext *ctx) 2441 { 2442 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2443 if (unlikely(Rc(ctx->opcode) != 0)) { 2444 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2445 } 2446 } 2447 2448 /* cnttzd */ 2449 static void gen_cnttzd(DisasContext *ctx) 2450 { 2451 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2452 if (unlikely(Rc(ctx->opcode) != 0)) { 2453 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2454 } 2455 } 2456 2457 /* darn */ 2458 static void gen_darn(DisasContext *ctx) 2459 { 2460 int l = L(ctx->opcode); 2461 2462 if (l > 2) { 2463 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 2464 } else { 2465 translator_io_start(&ctx->base); 2466 if (l == 0) { 2467 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 2468 } else { 2469 /* Return 64-bit random for both CRN and RRN */ 2470 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 2471 } 2472 } 2473 } 2474 #endif 2475 2476 /*** Integer rotate ***/ 2477 2478 /* rlwimi & rlwimi. */ 2479 static void gen_rlwimi(DisasContext *ctx) 2480 { 2481 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2482 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2483 uint32_t sh = SH(ctx->opcode); 2484 uint32_t mb = MB(ctx->opcode); 2485 uint32_t me = ME(ctx->opcode); 2486 2487 if (sh == (31 - me) && mb <= me) { 2488 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2489 } else { 2490 target_ulong mask; 2491 bool mask_in_32b = true; 2492 TCGv t1; 2493 2494 #if defined(TARGET_PPC64) 2495 mb += 32; 2496 me += 32; 2497 #endif 2498 mask = MASK(mb, me); 2499 2500 #if defined(TARGET_PPC64) 2501 if (mask > 0xffffffffu) { 2502 mask_in_32b = false; 2503 } 2504 #endif 2505 t1 = tcg_temp_new(); 2506 if (mask_in_32b) { 2507 TCGv_i32 t0 = tcg_temp_new_i32(); 2508 tcg_gen_trunc_tl_i32(t0, t_rs); 2509 tcg_gen_rotli_i32(t0, t0, sh); 2510 tcg_gen_extu_i32_tl(t1, t0); 2511 } else { 2512 #if defined(TARGET_PPC64) 2513 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2514 tcg_gen_rotli_i64(t1, t1, sh); 2515 #else 2516 g_assert_not_reached(); 2517 #endif 2518 } 2519 2520 tcg_gen_andi_tl(t1, t1, mask); 2521 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2522 tcg_gen_or_tl(t_ra, t_ra, t1); 2523 } 2524 if (unlikely(Rc(ctx->opcode) != 0)) { 2525 gen_set_Rc0(ctx, t_ra); 2526 } 2527 } 2528 2529 /* rlwinm & rlwinm. */ 2530 static void gen_rlwinm(DisasContext *ctx) 2531 { 2532 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2533 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2534 int sh = SH(ctx->opcode); 2535 int mb = MB(ctx->opcode); 2536 int me = ME(ctx->opcode); 2537 int len = me - mb + 1; 2538 int rsh = (32 - sh) & 31; 2539 2540 if (sh != 0 && len > 0 && me == (31 - sh)) { 2541 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2542 } else if (me == 31 && rsh + len <= 32) { 2543 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2544 } else { 2545 target_ulong mask; 2546 bool mask_in_32b = true; 2547 #if defined(TARGET_PPC64) 2548 mb += 32; 2549 me += 32; 2550 #endif 2551 mask = MASK(mb, me); 2552 #if defined(TARGET_PPC64) 2553 if (mask > 0xffffffffu) { 2554 mask_in_32b = false; 2555 } 2556 #endif 2557 if (mask_in_32b) { 2558 if (sh == 0) { 2559 tcg_gen_andi_tl(t_ra, t_rs, mask); 2560 } else { 2561 TCGv_i32 t0 = tcg_temp_new_i32(); 2562 tcg_gen_trunc_tl_i32(t0, t_rs); 2563 tcg_gen_rotli_i32(t0, t0, sh); 2564 tcg_gen_andi_i32(t0, t0, mask); 2565 tcg_gen_extu_i32_tl(t_ra, t0); 2566 } 2567 } else { 2568 #if defined(TARGET_PPC64) 2569 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2570 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2571 tcg_gen_andi_i64(t_ra, t_ra, mask); 2572 #else 2573 g_assert_not_reached(); 2574 #endif 2575 } 2576 } 2577 if (unlikely(Rc(ctx->opcode) != 0)) { 2578 gen_set_Rc0(ctx, t_ra); 2579 } 2580 } 2581 2582 /* rlwnm & rlwnm. */ 2583 static void gen_rlwnm(DisasContext *ctx) 2584 { 2585 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2586 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2587 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2588 uint32_t mb = MB(ctx->opcode); 2589 uint32_t me = ME(ctx->opcode); 2590 target_ulong mask; 2591 bool mask_in_32b = true; 2592 2593 #if defined(TARGET_PPC64) 2594 mb += 32; 2595 me += 32; 2596 #endif 2597 mask = MASK(mb, me); 2598 2599 #if defined(TARGET_PPC64) 2600 if (mask > 0xffffffffu) { 2601 mask_in_32b = false; 2602 } 2603 #endif 2604 if (mask_in_32b) { 2605 TCGv_i32 t0 = tcg_temp_new_i32(); 2606 TCGv_i32 t1 = tcg_temp_new_i32(); 2607 tcg_gen_trunc_tl_i32(t0, t_rb); 2608 tcg_gen_trunc_tl_i32(t1, t_rs); 2609 tcg_gen_andi_i32(t0, t0, 0x1f); 2610 tcg_gen_rotl_i32(t1, t1, t0); 2611 tcg_gen_extu_i32_tl(t_ra, t1); 2612 } else { 2613 #if defined(TARGET_PPC64) 2614 TCGv_i64 t0 = tcg_temp_new_i64(); 2615 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2616 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2617 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2618 #else 2619 g_assert_not_reached(); 2620 #endif 2621 } 2622 2623 tcg_gen_andi_tl(t_ra, t_ra, mask); 2624 2625 if (unlikely(Rc(ctx->opcode) != 0)) { 2626 gen_set_Rc0(ctx, t_ra); 2627 } 2628 } 2629 2630 #if defined(TARGET_PPC64) 2631 #define GEN_PPC64_R2(name, opc1, opc2) \ 2632 static void glue(gen_, name##0)(DisasContext *ctx) \ 2633 { \ 2634 gen_##name(ctx, 0); \ 2635 } \ 2636 \ 2637 static void glue(gen_, name##1)(DisasContext *ctx) \ 2638 { \ 2639 gen_##name(ctx, 1); \ 2640 } 2641 #define GEN_PPC64_R4(name, opc1, opc2) \ 2642 static void glue(gen_, name##0)(DisasContext *ctx) \ 2643 { \ 2644 gen_##name(ctx, 0, 0); \ 2645 } \ 2646 \ 2647 static void glue(gen_, name##1)(DisasContext *ctx) \ 2648 { \ 2649 gen_##name(ctx, 0, 1); \ 2650 } \ 2651 \ 2652 static void glue(gen_, name##2)(DisasContext *ctx) \ 2653 { \ 2654 gen_##name(ctx, 1, 0); \ 2655 } \ 2656 \ 2657 static void glue(gen_, name##3)(DisasContext *ctx) \ 2658 { \ 2659 gen_##name(ctx, 1, 1); \ 2660 } 2661 2662 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2663 { 2664 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2665 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2666 int len = me - mb + 1; 2667 int rsh = (64 - sh) & 63; 2668 2669 if (sh != 0 && len > 0 && me == (63 - sh)) { 2670 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2671 } else if (me == 63 && rsh + len <= 64) { 2672 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2673 } else { 2674 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2675 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2676 } 2677 if (unlikely(Rc(ctx->opcode) != 0)) { 2678 gen_set_Rc0(ctx, t_ra); 2679 } 2680 } 2681 2682 /* rldicl - rldicl. */ 2683 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2684 { 2685 uint32_t sh, mb; 2686 2687 sh = SH(ctx->opcode) | (shn << 5); 2688 mb = MB(ctx->opcode) | (mbn << 5); 2689 gen_rldinm(ctx, mb, 63, sh); 2690 } 2691 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2692 2693 /* rldicr - rldicr. */ 2694 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2695 { 2696 uint32_t sh, me; 2697 2698 sh = SH(ctx->opcode) | (shn << 5); 2699 me = MB(ctx->opcode) | (men << 5); 2700 gen_rldinm(ctx, 0, me, sh); 2701 } 2702 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2703 2704 /* rldic - rldic. */ 2705 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2706 { 2707 uint32_t sh, mb; 2708 2709 sh = SH(ctx->opcode) | (shn << 5); 2710 mb = MB(ctx->opcode) | (mbn << 5); 2711 gen_rldinm(ctx, mb, 63 - sh, sh); 2712 } 2713 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2714 2715 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2716 { 2717 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2718 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2719 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2720 TCGv t0; 2721 2722 t0 = tcg_temp_new(); 2723 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2724 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2725 2726 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2727 if (unlikely(Rc(ctx->opcode) != 0)) { 2728 gen_set_Rc0(ctx, t_ra); 2729 } 2730 } 2731 2732 /* rldcl - rldcl. */ 2733 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2734 { 2735 uint32_t mb; 2736 2737 mb = MB(ctx->opcode) | (mbn << 5); 2738 gen_rldnm(ctx, mb, 63); 2739 } 2740 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2741 2742 /* rldcr - rldcr. */ 2743 static inline void gen_rldcr(DisasContext *ctx, int men) 2744 { 2745 uint32_t me; 2746 2747 me = MB(ctx->opcode) | (men << 5); 2748 gen_rldnm(ctx, 0, me); 2749 } 2750 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2751 2752 /* rldimi - rldimi. */ 2753 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2754 { 2755 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2756 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2757 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2758 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2759 uint32_t me = 63 - sh; 2760 2761 if (mb <= me) { 2762 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2763 } else { 2764 target_ulong mask = MASK(mb, me); 2765 TCGv t1 = tcg_temp_new(); 2766 2767 tcg_gen_rotli_tl(t1, t_rs, sh); 2768 tcg_gen_andi_tl(t1, t1, mask); 2769 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2770 tcg_gen_or_tl(t_ra, t_ra, t1); 2771 } 2772 if (unlikely(Rc(ctx->opcode) != 0)) { 2773 gen_set_Rc0(ctx, t_ra); 2774 } 2775 } 2776 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2777 #endif 2778 2779 /*** Integer shift ***/ 2780 2781 /* slw & slw. */ 2782 static void gen_slw(DisasContext *ctx) 2783 { 2784 TCGv t0, t1; 2785 2786 t0 = tcg_temp_new(); 2787 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2788 #if defined(TARGET_PPC64) 2789 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2790 tcg_gen_sari_tl(t0, t0, 0x3f); 2791 #else 2792 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2793 tcg_gen_sari_tl(t0, t0, 0x1f); 2794 #endif 2795 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2796 t1 = tcg_temp_new(); 2797 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2798 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2799 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2800 if (unlikely(Rc(ctx->opcode) != 0)) { 2801 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2802 } 2803 } 2804 2805 /* sraw & sraw. */ 2806 static void gen_sraw(DisasContext *ctx) 2807 { 2808 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2809 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2810 if (unlikely(Rc(ctx->opcode) != 0)) { 2811 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2812 } 2813 } 2814 2815 /* srawi & srawi. */ 2816 static void gen_srawi(DisasContext *ctx) 2817 { 2818 int sh = SH(ctx->opcode); 2819 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2820 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2821 if (sh == 0) { 2822 tcg_gen_ext32s_tl(dst, src); 2823 tcg_gen_movi_tl(cpu_ca, 0); 2824 if (is_isa300(ctx)) { 2825 tcg_gen_movi_tl(cpu_ca32, 0); 2826 } 2827 } else { 2828 TCGv t0; 2829 tcg_gen_ext32s_tl(dst, src); 2830 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2831 t0 = tcg_temp_new(); 2832 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2833 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2834 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2835 if (is_isa300(ctx)) { 2836 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2837 } 2838 tcg_gen_sari_tl(dst, dst, sh); 2839 } 2840 if (unlikely(Rc(ctx->opcode) != 0)) { 2841 gen_set_Rc0(ctx, dst); 2842 } 2843 } 2844 2845 /* srw & srw. */ 2846 static void gen_srw(DisasContext *ctx) 2847 { 2848 TCGv t0, t1; 2849 2850 t0 = tcg_temp_new(); 2851 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2852 #if defined(TARGET_PPC64) 2853 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2854 tcg_gen_sari_tl(t0, t0, 0x3f); 2855 #else 2856 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2857 tcg_gen_sari_tl(t0, t0, 0x1f); 2858 #endif 2859 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2860 tcg_gen_ext32u_tl(t0, t0); 2861 t1 = tcg_temp_new(); 2862 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2863 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2864 if (unlikely(Rc(ctx->opcode) != 0)) { 2865 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2866 } 2867 } 2868 2869 #if defined(TARGET_PPC64) 2870 /* sld & sld. */ 2871 static void gen_sld(DisasContext *ctx) 2872 { 2873 TCGv t0, t1; 2874 2875 t0 = tcg_temp_new(); 2876 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2877 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2878 tcg_gen_sari_tl(t0, t0, 0x3f); 2879 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2880 t1 = tcg_temp_new(); 2881 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2882 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2883 if (unlikely(Rc(ctx->opcode) != 0)) { 2884 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2885 } 2886 } 2887 2888 /* srad & srad. */ 2889 static void gen_srad(DisasContext *ctx) 2890 { 2891 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2892 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2893 if (unlikely(Rc(ctx->opcode) != 0)) { 2894 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2895 } 2896 } 2897 /* sradi & sradi. */ 2898 static inline void gen_sradi(DisasContext *ctx, int n) 2899 { 2900 int sh = SH(ctx->opcode) + (n << 5); 2901 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2902 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2903 if (sh == 0) { 2904 tcg_gen_mov_tl(dst, src); 2905 tcg_gen_movi_tl(cpu_ca, 0); 2906 if (is_isa300(ctx)) { 2907 tcg_gen_movi_tl(cpu_ca32, 0); 2908 } 2909 } else { 2910 TCGv t0; 2911 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2912 t0 = tcg_temp_new(); 2913 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2914 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2915 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2916 if (is_isa300(ctx)) { 2917 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2918 } 2919 tcg_gen_sari_tl(dst, src, sh); 2920 } 2921 if (unlikely(Rc(ctx->opcode) != 0)) { 2922 gen_set_Rc0(ctx, dst); 2923 } 2924 } 2925 2926 static void gen_sradi0(DisasContext *ctx) 2927 { 2928 gen_sradi(ctx, 0); 2929 } 2930 2931 static void gen_sradi1(DisasContext *ctx) 2932 { 2933 gen_sradi(ctx, 1); 2934 } 2935 2936 /* extswsli & extswsli. */ 2937 static inline void gen_extswsli(DisasContext *ctx, int n) 2938 { 2939 int sh = SH(ctx->opcode) + (n << 5); 2940 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2941 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2942 2943 tcg_gen_ext32s_tl(dst, src); 2944 tcg_gen_shli_tl(dst, dst, sh); 2945 if (unlikely(Rc(ctx->opcode) != 0)) { 2946 gen_set_Rc0(ctx, dst); 2947 } 2948 } 2949 2950 static void gen_extswsli0(DisasContext *ctx) 2951 { 2952 gen_extswsli(ctx, 0); 2953 } 2954 2955 static void gen_extswsli1(DisasContext *ctx) 2956 { 2957 gen_extswsli(ctx, 1); 2958 } 2959 2960 /* srd & srd. */ 2961 static void gen_srd(DisasContext *ctx) 2962 { 2963 TCGv t0, t1; 2964 2965 t0 = tcg_temp_new(); 2966 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2967 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2968 tcg_gen_sari_tl(t0, t0, 0x3f); 2969 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2970 t1 = tcg_temp_new(); 2971 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2972 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2973 if (unlikely(Rc(ctx->opcode) != 0)) { 2974 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2975 } 2976 } 2977 #endif 2978 2979 /*** Addressing modes ***/ 2980 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2981 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2982 target_long maskl) 2983 { 2984 target_long simm = SIMM(ctx->opcode); 2985 2986 simm &= ~maskl; 2987 if (rA(ctx->opcode) == 0) { 2988 if (NARROW_MODE(ctx)) { 2989 simm = (uint32_t)simm; 2990 } 2991 tcg_gen_movi_tl(EA, simm); 2992 } else if (likely(simm != 0)) { 2993 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2994 if (NARROW_MODE(ctx)) { 2995 tcg_gen_ext32u_tl(EA, EA); 2996 } 2997 } else { 2998 if (NARROW_MODE(ctx)) { 2999 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3000 } else { 3001 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3002 } 3003 } 3004 } 3005 3006 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3007 { 3008 if (rA(ctx->opcode) == 0) { 3009 if (NARROW_MODE(ctx)) { 3010 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3011 } else { 3012 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3013 } 3014 } else { 3015 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3016 if (NARROW_MODE(ctx)) { 3017 tcg_gen_ext32u_tl(EA, EA); 3018 } 3019 } 3020 } 3021 3022 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3023 { 3024 if (rA(ctx->opcode) == 0) { 3025 tcg_gen_movi_tl(EA, 0); 3026 } else if (NARROW_MODE(ctx)) { 3027 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3028 } else { 3029 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3030 } 3031 } 3032 3033 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3034 target_long val) 3035 { 3036 tcg_gen_addi_tl(ret, arg1, val); 3037 if (NARROW_MODE(ctx)) { 3038 tcg_gen_ext32u_tl(ret, ret); 3039 } 3040 } 3041 3042 static inline void gen_align_no_le(DisasContext *ctx) 3043 { 3044 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3045 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3046 } 3047 3048 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3049 { 3050 TCGv ea = tcg_temp_new(); 3051 if (ra) { 3052 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3053 } else { 3054 tcg_gen_mov_tl(ea, displ); 3055 } 3056 if (NARROW_MODE(ctx)) { 3057 tcg_gen_ext32u_tl(ea, ea); 3058 } 3059 return ea; 3060 } 3061 3062 /*** Integer load ***/ 3063 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3064 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3065 3066 #define GEN_QEMU_LOAD_TL(ldop, op) \ 3067 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3068 TCGv val, \ 3069 TCGv addr) \ 3070 { \ 3071 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3072 } 3073 3074 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3075 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3076 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3077 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3078 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3079 3080 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3081 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3082 3083 #define GEN_QEMU_LOAD_64(ldop, op) \ 3084 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3085 TCGv_i64 val, \ 3086 TCGv addr) \ 3087 { \ 3088 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3089 } 3090 3091 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3092 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3093 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3094 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3095 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3096 3097 #if defined(TARGET_PPC64) 3098 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3099 #endif 3100 3101 #define GEN_QEMU_STORE_TL(stop, op) \ 3102 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3103 TCGv val, \ 3104 TCGv addr) \ 3105 { \ 3106 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3107 } 3108 3109 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3110 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3111 #endif 3112 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3113 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3114 3115 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3116 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3117 3118 #define GEN_QEMU_STORE_64(stop, op) \ 3119 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3120 TCGv_i64 val, \ 3121 TCGv addr) \ 3122 { \ 3123 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3124 } 3125 3126 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3127 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3128 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3129 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3130 3131 #if defined(TARGET_PPC64) 3132 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3133 #endif 3134 3135 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3136 static void glue(gen_, name##x)(DisasContext *ctx) \ 3137 { \ 3138 TCGv EA; \ 3139 chk(ctx); \ 3140 gen_set_access_type(ctx, ACCESS_INT); \ 3141 EA = tcg_temp_new(); \ 3142 gen_addr_reg_index(ctx, EA); \ 3143 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3144 } 3145 3146 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3147 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3148 3149 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3150 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3151 3152 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 3153 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3154 { \ 3155 TCGv EA; \ 3156 CHK_SV(ctx); \ 3157 gen_set_access_type(ctx, ACCESS_INT); \ 3158 EA = tcg_temp_new(); \ 3159 gen_addr_reg_index(ctx, EA); \ 3160 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 3161 } 3162 3163 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 3164 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 3165 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 3166 #if defined(TARGET_PPC64) 3167 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 3168 #endif 3169 3170 #if defined(TARGET_PPC64) 3171 /* CI load/store variants */ 3172 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3173 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3174 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3175 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3176 #endif 3177 3178 /*** Integer store ***/ 3179 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3180 static void glue(gen_, name##x)(DisasContext *ctx) \ 3181 { \ 3182 TCGv EA; \ 3183 chk(ctx); \ 3184 gen_set_access_type(ctx, ACCESS_INT); \ 3185 EA = tcg_temp_new(); \ 3186 gen_addr_reg_index(ctx, EA); \ 3187 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3188 } 3189 #define GEN_STX(name, stop, opc2, opc3, type) \ 3190 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3191 3192 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3193 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3194 3195 #define GEN_STEPX(name, stop, opc2, opc3) \ 3196 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3197 { \ 3198 TCGv EA; \ 3199 CHK_SV(ctx); \ 3200 gen_set_access_type(ctx, ACCESS_INT); \ 3201 EA = tcg_temp_new(); \ 3202 gen_addr_reg_index(ctx, EA); \ 3203 tcg_gen_qemu_st_tl( \ 3204 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 3205 } 3206 3207 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 3208 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 3209 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 3210 #if defined(TARGET_PPC64) 3211 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 3212 #endif 3213 3214 #if defined(TARGET_PPC64) 3215 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3216 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3217 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3218 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3219 #endif 3220 /*** Integer load and store with byte reverse ***/ 3221 3222 /* lhbrx */ 3223 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3224 3225 /* lwbrx */ 3226 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3227 3228 #if defined(TARGET_PPC64) 3229 /* ldbrx */ 3230 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3231 /* stdbrx */ 3232 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3233 #endif /* TARGET_PPC64 */ 3234 3235 /* sthbrx */ 3236 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3237 /* stwbrx */ 3238 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3239 3240 /*** Integer load and store multiple ***/ 3241 3242 /* lmw */ 3243 static void gen_lmw(DisasContext *ctx) 3244 { 3245 TCGv t0; 3246 TCGv_i32 t1; 3247 3248 if (ctx->le_mode) { 3249 gen_align_no_le(ctx); 3250 return; 3251 } 3252 gen_set_access_type(ctx, ACCESS_INT); 3253 t0 = tcg_temp_new(); 3254 t1 = tcg_constant_i32(rD(ctx->opcode)); 3255 gen_addr_imm_index(ctx, t0, 0); 3256 gen_helper_lmw(cpu_env, t0, t1); 3257 } 3258 3259 /* stmw */ 3260 static void gen_stmw(DisasContext *ctx) 3261 { 3262 TCGv t0; 3263 TCGv_i32 t1; 3264 3265 if (ctx->le_mode) { 3266 gen_align_no_le(ctx); 3267 return; 3268 } 3269 gen_set_access_type(ctx, ACCESS_INT); 3270 t0 = tcg_temp_new(); 3271 t1 = tcg_constant_i32(rS(ctx->opcode)); 3272 gen_addr_imm_index(ctx, t0, 0); 3273 gen_helper_stmw(cpu_env, t0, t1); 3274 } 3275 3276 /*** Integer load and store strings ***/ 3277 3278 /* lswi */ 3279 /* 3280 * PowerPC32 specification says we must generate an exception if rA is 3281 * in the range of registers to be loaded. In an other hand, IBM says 3282 * this is valid, but rA won't be loaded. For now, I'll follow the 3283 * spec... 3284 */ 3285 static void gen_lswi(DisasContext *ctx) 3286 { 3287 TCGv t0; 3288 TCGv_i32 t1, t2; 3289 int nb = NB(ctx->opcode); 3290 int start = rD(ctx->opcode); 3291 int ra = rA(ctx->opcode); 3292 int nr; 3293 3294 if (ctx->le_mode) { 3295 gen_align_no_le(ctx); 3296 return; 3297 } 3298 if (nb == 0) { 3299 nb = 32; 3300 } 3301 nr = DIV_ROUND_UP(nb, 4); 3302 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3303 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3304 return; 3305 } 3306 gen_set_access_type(ctx, ACCESS_INT); 3307 t0 = tcg_temp_new(); 3308 gen_addr_register(ctx, t0); 3309 t1 = tcg_constant_i32(nb); 3310 t2 = tcg_constant_i32(start); 3311 gen_helper_lsw(cpu_env, t0, t1, t2); 3312 } 3313 3314 /* lswx */ 3315 static void gen_lswx(DisasContext *ctx) 3316 { 3317 TCGv t0; 3318 TCGv_i32 t1, t2, t3; 3319 3320 if (ctx->le_mode) { 3321 gen_align_no_le(ctx); 3322 return; 3323 } 3324 gen_set_access_type(ctx, ACCESS_INT); 3325 t0 = tcg_temp_new(); 3326 gen_addr_reg_index(ctx, t0); 3327 t1 = tcg_constant_i32(rD(ctx->opcode)); 3328 t2 = tcg_constant_i32(rA(ctx->opcode)); 3329 t3 = tcg_constant_i32(rB(ctx->opcode)); 3330 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3331 } 3332 3333 /* stswi */ 3334 static void gen_stswi(DisasContext *ctx) 3335 { 3336 TCGv t0; 3337 TCGv_i32 t1, t2; 3338 int nb = NB(ctx->opcode); 3339 3340 if (ctx->le_mode) { 3341 gen_align_no_le(ctx); 3342 return; 3343 } 3344 gen_set_access_type(ctx, ACCESS_INT); 3345 t0 = tcg_temp_new(); 3346 gen_addr_register(ctx, t0); 3347 if (nb == 0) { 3348 nb = 32; 3349 } 3350 t1 = tcg_constant_i32(nb); 3351 t2 = tcg_constant_i32(rS(ctx->opcode)); 3352 gen_helper_stsw(cpu_env, t0, t1, t2); 3353 } 3354 3355 /* stswx */ 3356 static void gen_stswx(DisasContext *ctx) 3357 { 3358 TCGv t0; 3359 TCGv_i32 t1, t2; 3360 3361 if (ctx->le_mode) { 3362 gen_align_no_le(ctx); 3363 return; 3364 } 3365 gen_set_access_type(ctx, ACCESS_INT); 3366 t0 = tcg_temp_new(); 3367 gen_addr_reg_index(ctx, t0); 3368 t1 = tcg_temp_new_i32(); 3369 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3370 tcg_gen_andi_i32(t1, t1, 0x7F); 3371 t2 = tcg_constant_i32(rS(ctx->opcode)); 3372 gen_helper_stsw(cpu_env, t0, t1, t2); 3373 } 3374 3375 /*** Memory synchronisation ***/ 3376 /* eieio */ 3377 static void gen_eieio(DisasContext *ctx) 3378 { 3379 TCGBar bar = TCG_MO_ALL; 3380 3381 /* 3382 * eieio has complex semanitcs. It provides memory ordering between 3383 * operations in the set: 3384 * - loads from CI memory. 3385 * - stores to CI memory. 3386 * - stores to WT memory. 3387 * 3388 * It separately also orders memory for operations in the set: 3389 * - stores to cacheble memory. 3390 * 3391 * It also serializes instructions: 3392 * - dcbt and dcbst. 3393 * 3394 * It separately serializes: 3395 * - tlbie and tlbsync. 3396 * 3397 * And separately serializes: 3398 * - slbieg, slbiag, and slbsync. 3399 * 3400 * The end result is that CI memory ordering requires TCG_MO_ALL 3401 * and it is not possible to special-case more relaxed ordering for 3402 * cacheable accesses. TCG_BAR_SC is required to provide this 3403 * serialization. 3404 */ 3405 3406 /* 3407 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3408 * tell the CPU it is a store-forwarding barrier. 3409 */ 3410 if (ctx->opcode & 0x2000000) { 3411 /* 3412 * ISA says that "Reserved fields in instructions are ignored 3413 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3414 * as this is not an instruction software should be using, 3415 * complain to the user. 3416 */ 3417 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3418 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3419 TARGET_FMT_lx "\n", ctx->cia); 3420 } else { 3421 bar = TCG_MO_ST_LD; 3422 } 3423 } 3424 3425 tcg_gen_mb(bar | TCG_BAR_SC); 3426 } 3427 3428 #if !defined(CONFIG_USER_ONLY) 3429 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3430 { 3431 TCGv_i32 t; 3432 TCGLabel *l; 3433 3434 if (!ctx->lazy_tlb_flush) { 3435 return; 3436 } 3437 l = gen_new_label(); 3438 t = tcg_temp_new_i32(); 3439 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3440 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3441 if (global) { 3442 gen_helper_check_tlb_flush_global(cpu_env); 3443 } else { 3444 gen_helper_check_tlb_flush_local(cpu_env); 3445 } 3446 gen_set_label(l); 3447 } 3448 #else 3449 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3450 #endif 3451 3452 /* isync */ 3453 static void gen_isync(DisasContext *ctx) 3454 { 3455 /* 3456 * We need to check for a pending TLB flush. This can only happen in 3457 * kernel mode however so check MSR_PR 3458 */ 3459 if (!ctx->pr) { 3460 gen_check_tlb_flush(ctx, false); 3461 } 3462 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3463 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3464 } 3465 3466 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3467 3468 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3469 { 3470 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3471 TCGv t0 = tcg_temp_new(); 3472 3473 gen_set_access_type(ctx, ACCESS_RES); 3474 gen_addr_reg_index(ctx, t0); 3475 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3476 tcg_gen_mov_tl(cpu_reserve, t0); 3477 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 3478 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3479 } 3480 3481 #define LARX(name, memop) \ 3482 static void gen_##name(DisasContext *ctx) \ 3483 { \ 3484 gen_load_locked(ctx, memop); \ 3485 } 3486 3487 /* lwarx */ 3488 LARX(lbarx, DEF_MEMOP(MO_UB)) 3489 LARX(lharx, DEF_MEMOP(MO_UW)) 3490 LARX(lwarx, DEF_MEMOP(MO_UL)) 3491 3492 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3493 TCGv EA, TCGCond cond, int addend) 3494 { 3495 TCGv t = tcg_temp_new(); 3496 TCGv t2 = tcg_temp_new(); 3497 TCGv u = tcg_temp_new(); 3498 3499 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3500 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3501 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3502 tcg_gen_addi_tl(u, t, addend); 3503 3504 /* E.g. for fetch and increment bounded... */ 3505 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3506 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3507 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3508 3509 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3510 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3511 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3512 } 3513 3514 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3515 { 3516 uint32_t gpr_FC = FC(ctx->opcode); 3517 TCGv EA = tcg_temp_new(); 3518 int rt = rD(ctx->opcode); 3519 bool need_serial; 3520 TCGv src, dst; 3521 3522 gen_addr_register(ctx, EA); 3523 dst = cpu_gpr[rt]; 3524 src = cpu_gpr[(rt + 1) & 31]; 3525 3526 need_serial = false; 3527 memop |= MO_ALIGN; 3528 switch (gpr_FC) { 3529 case 0: /* Fetch and add */ 3530 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3531 break; 3532 case 1: /* Fetch and xor */ 3533 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3534 break; 3535 case 2: /* Fetch and or */ 3536 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3537 break; 3538 case 3: /* Fetch and 'and' */ 3539 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3540 break; 3541 case 4: /* Fetch and max unsigned */ 3542 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3543 break; 3544 case 5: /* Fetch and max signed */ 3545 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3546 break; 3547 case 6: /* Fetch and min unsigned */ 3548 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3549 break; 3550 case 7: /* Fetch and min signed */ 3551 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3552 break; 3553 case 8: /* Swap */ 3554 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3555 break; 3556 3557 case 16: /* Compare and swap not equal */ 3558 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3559 need_serial = true; 3560 } else { 3561 TCGv t0 = tcg_temp_new(); 3562 TCGv t1 = tcg_temp_new(); 3563 3564 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3565 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3566 tcg_gen_mov_tl(t1, src); 3567 } else { 3568 tcg_gen_ext32u_tl(t1, src); 3569 } 3570 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3571 cpu_gpr[(rt + 2) & 31], t0); 3572 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3573 tcg_gen_mov_tl(dst, t0); 3574 } 3575 break; 3576 3577 case 24: /* Fetch and increment bounded */ 3578 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3579 need_serial = true; 3580 } else { 3581 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3582 } 3583 break; 3584 case 25: /* Fetch and increment equal */ 3585 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3586 need_serial = true; 3587 } else { 3588 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3589 } 3590 break; 3591 case 28: /* Fetch and decrement bounded */ 3592 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3593 need_serial = true; 3594 } else { 3595 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3596 } 3597 break; 3598 3599 default: 3600 /* invoke data storage error handler */ 3601 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3602 } 3603 3604 if (need_serial) { 3605 /* Restart with exclusive lock. */ 3606 gen_helper_exit_atomic(cpu_env); 3607 ctx->base.is_jmp = DISAS_NORETURN; 3608 } 3609 } 3610 3611 static void gen_lwat(DisasContext *ctx) 3612 { 3613 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3614 } 3615 3616 #ifdef TARGET_PPC64 3617 static void gen_ldat(DisasContext *ctx) 3618 { 3619 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3620 } 3621 #endif 3622 3623 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3624 { 3625 uint32_t gpr_FC = FC(ctx->opcode); 3626 TCGv EA = tcg_temp_new(); 3627 TCGv src, discard; 3628 3629 gen_addr_register(ctx, EA); 3630 src = cpu_gpr[rD(ctx->opcode)]; 3631 discard = tcg_temp_new(); 3632 3633 memop |= MO_ALIGN; 3634 switch (gpr_FC) { 3635 case 0: /* add and Store */ 3636 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3637 break; 3638 case 1: /* xor and Store */ 3639 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3640 break; 3641 case 2: /* Or and Store */ 3642 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3643 break; 3644 case 3: /* 'and' and Store */ 3645 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3646 break; 3647 case 4: /* Store max unsigned */ 3648 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3649 break; 3650 case 5: /* Store max signed */ 3651 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3652 break; 3653 case 6: /* Store min unsigned */ 3654 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3655 break; 3656 case 7: /* Store min signed */ 3657 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3658 break; 3659 case 24: /* Store twin */ 3660 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3661 /* Restart with exclusive lock. */ 3662 gen_helper_exit_atomic(cpu_env); 3663 ctx->base.is_jmp = DISAS_NORETURN; 3664 } else { 3665 TCGv t = tcg_temp_new(); 3666 TCGv t2 = tcg_temp_new(); 3667 TCGv s = tcg_temp_new(); 3668 TCGv s2 = tcg_temp_new(); 3669 TCGv ea_plus_s = tcg_temp_new(); 3670 3671 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3672 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3673 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3674 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3675 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3676 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3677 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3678 } 3679 break; 3680 default: 3681 /* invoke data storage error handler */ 3682 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3683 } 3684 } 3685 3686 static void gen_stwat(DisasContext *ctx) 3687 { 3688 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3689 } 3690 3691 #ifdef TARGET_PPC64 3692 static void gen_stdat(DisasContext *ctx) 3693 { 3694 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3695 } 3696 #endif 3697 3698 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3699 { 3700 TCGLabel *lfail; 3701 TCGv EA; 3702 TCGv cr0; 3703 TCGv t0; 3704 int rs = rS(ctx->opcode); 3705 3706 lfail = gen_new_label(); 3707 EA = tcg_temp_new(); 3708 cr0 = tcg_temp_new(); 3709 t0 = tcg_temp_new(); 3710 3711 tcg_gen_mov_tl(cr0, cpu_so); 3712 gen_set_access_type(ctx, ACCESS_RES); 3713 gen_addr_reg_index(ctx, EA); 3714 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3715 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 3716 3717 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3718 cpu_gpr[rs], ctx->mem_idx, 3719 DEF_MEMOP(memop) | MO_ALIGN); 3720 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3721 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3722 tcg_gen_or_tl(cr0, cr0, t0); 3723 3724 gen_set_label(lfail); 3725 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3726 tcg_gen_movi_tl(cpu_reserve, -1); 3727 } 3728 3729 #define STCX(name, memop) \ 3730 static void gen_##name(DisasContext *ctx) \ 3731 { \ 3732 gen_conditional_store(ctx, memop); \ 3733 } 3734 3735 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3736 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3737 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3738 3739 #if defined(TARGET_PPC64) 3740 /* ldarx */ 3741 LARX(ldarx, DEF_MEMOP(MO_UQ)) 3742 /* stdcx. */ 3743 STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3744 3745 /* lqarx */ 3746 static void gen_lqarx(DisasContext *ctx) 3747 { 3748 int rd = rD(ctx->opcode); 3749 TCGv EA, hi, lo; 3750 TCGv_i128 t16; 3751 3752 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3753 (rd == rB(ctx->opcode)))) { 3754 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3755 return; 3756 } 3757 3758 gen_set_access_type(ctx, ACCESS_RES); 3759 EA = tcg_temp_new(); 3760 gen_addr_reg_index(ctx, EA); 3761 3762 /* Note that the low part is always in RD+1, even in LE mode. */ 3763 lo = cpu_gpr[rd + 1]; 3764 hi = cpu_gpr[rd]; 3765 3766 t16 = tcg_temp_new_i128(); 3767 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3768 tcg_gen_extr_i128_i64(lo, hi, t16); 3769 3770 tcg_gen_mov_tl(cpu_reserve, EA); 3771 tcg_gen_movi_tl(cpu_reserve_length, 16); 3772 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3773 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3774 } 3775 3776 /* stqcx. */ 3777 static void gen_stqcx_(DisasContext *ctx) 3778 { 3779 TCGLabel *lfail; 3780 TCGv EA, t0, t1; 3781 TCGv cr0; 3782 TCGv_i128 cmp, val; 3783 int rs = rS(ctx->opcode); 3784 3785 if (unlikely(rs & 1)) { 3786 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3787 return; 3788 } 3789 3790 lfail = gen_new_label(); 3791 EA = tcg_temp_new(); 3792 cr0 = tcg_temp_new(); 3793 3794 tcg_gen_mov_tl(cr0, cpu_so); 3795 gen_set_access_type(ctx, ACCESS_RES); 3796 gen_addr_reg_index(ctx, EA); 3797 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3798 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 3799 3800 cmp = tcg_temp_new_i128(); 3801 val = tcg_temp_new_i128(); 3802 3803 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3804 3805 /* Note that the low part is always in RS+1, even in LE mode. */ 3806 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3807 3808 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3809 DEF_MEMOP(MO_128 | MO_ALIGN)); 3810 3811 t0 = tcg_temp_new(); 3812 t1 = tcg_temp_new(); 3813 tcg_gen_extr_i128_i64(t1, t0, val); 3814 3815 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3816 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3817 tcg_gen_or_tl(t0, t0, t1); 3818 3819 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3820 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3821 tcg_gen_or_tl(cr0, cr0, t0); 3822 3823 gen_set_label(lfail); 3824 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3825 tcg_gen_movi_tl(cpu_reserve, -1); 3826 } 3827 #endif /* defined(TARGET_PPC64) */ 3828 3829 /* sync */ 3830 static void gen_sync(DisasContext *ctx) 3831 { 3832 TCGBar bar = TCG_MO_ALL; 3833 uint32_t l = (ctx->opcode >> 21) & 3; 3834 3835 if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 3836 bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 3837 } 3838 3839 /* 3840 * We may need to check for a pending TLB flush. 3841 * 3842 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3843 * 3844 * Additionally, this can only happen in kernel mode however so 3845 * check MSR_PR as well. 3846 */ 3847 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3848 gen_check_tlb_flush(ctx, true); 3849 } 3850 3851 tcg_gen_mb(bar | TCG_BAR_SC); 3852 } 3853 3854 /* wait */ 3855 static void gen_wait(DisasContext *ctx) 3856 { 3857 uint32_t wc; 3858 3859 if (ctx->insns_flags & PPC_WAIT) { 3860 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3861 3862 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3863 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3864 wc = WC(ctx->opcode); 3865 } else { 3866 wc = 0; 3867 } 3868 3869 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3870 /* v3.0 defines a new 'wait' encoding. */ 3871 wc = WC(ctx->opcode); 3872 if (ctx->insns_flags2 & PPC2_ISA310) { 3873 uint32_t pl = PL(ctx->opcode); 3874 3875 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3876 if (wc == 3) { 3877 gen_invalid(ctx); 3878 return; 3879 } 3880 3881 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3882 if (pl > 0 && wc != 2) { 3883 gen_invalid(ctx); 3884 return; 3885 } 3886 3887 } else { /* ISA300 */ 3888 /* WC 1-3 are reserved */ 3889 if (wc > 0) { 3890 gen_invalid(ctx); 3891 return; 3892 } 3893 } 3894 3895 } else { 3896 warn_report("wait instruction decoded with wrong ISA flags."); 3897 gen_invalid(ctx); 3898 return; 3899 } 3900 3901 /* 3902 * wait without WC field or with WC=0 waits for an exception / interrupt 3903 * to occur. 3904 */ 3905 if (wc == 0) { 3906 TCGv_i32 t0 = tcg_constant_i32(1); 3907 tcg_gen_st_i32(t0, cpu_env, 3908 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3909 /* Stop translation, as the CPU is supposed to sleep from now */ 3910 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3911 } 3912 3913 /* 3914 * Other wait types must not just wait until an exception occurs because 3915 * ignoring their other wake-up conditions could cause a hang. 3916 * 3917 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3918 * no-ops. 3919 * 3920 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 3921 * 3922 * wc=2 waits for an implementation-specific condition, such could be 3923 * always true, so it can be implemented as a no-op. 3924 * 3925 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 3926 * 3927 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 3928 * Reservation-loss may have implementation-specific conditions, so it 3929 * can be implemented as a no-op. 3930 * 3931 * wc=2 waits for an exception or an amount of time to pass. This 3932 * amount is implementation-specific so it can be implemented as a 3933 * no-op. 3934 * 3935 * ISA v3.1 allows for execution to resume "in the rare case of 3936 * an implementation-dependent event", so in any case software must 3937 * not depend on the architected resumption condition to become 3938 * true, so no-op implementations should be architecturally correct 3939 * (if suboptimal). 3940 */ 3941 } 3942 3943 #if defined(TARGET_PPC64) 3944 static void gen_doze(DisasContext *ctx) 3945 { 3946 #if defined(CONFIG_USER_ONLY) 3947 GEN_PRIV(ctx); 3948 #else 3949 TCGv_i32 t; 3950 3951 CHK_HV(ctx); 3952 t = tcg_constant_i32(PPC_PM_DOZE); 3953 gen_helper_pminsn(cpu_env, t); 3954 /* Stop translation, as the CPU is supposed to sleep from now */ 3955 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3956 #endif /* defined(CONFIG_USER_ONLY) */ 3957 } 3958 3959 static void gen_nap(DisasContext *ctx) 3960 { 3961 #if defined(CONFIG_USER_ONLY) 3962 GEN_PRIV(ctx); 3963 #else 3964 TCGv_i32 t; 3965 3966 CHK_HV(ctx); 3967 t = tcg_constant_i32(PPC_PM_NAP); 3968 gen_helper_pminsn(cpu_env, t); 3969 /* Stop translation, as the CPU is supposed to sleep from now */ 3970 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3971 #endif /* defined(CONFIG_USER_ONLY) */ 3972 } 3973 3974 static void gen_stop(DisasContext *ctx) 3975 { 3976 #if defined(CONFIG_USER_ONLY) 3977 GEN_PRIV(ctx); 3978 #else 3979 TCGv_i32 t; 3980 3981 CHK_HV(ctx); 3982 t = tcg_constant_i32(PPC_PM_STOP); 3983 gen_helper_pminsn(cpu_env, t); 3984 /* Stop translation, as the CPU is supposed to sleep from now */ 3985 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3986 #endif /* defined(CONFIG_USER_ONLY) */ 3987 } 3988 3989 static void gen_sleep(DisasContext *ctx) 3990 { 3991 #if defined(CONFIG_USER_ONLY) 3992 GEN_PRIV(ctx); 3993 #else 3994 TCGv_i32 t; 3995 3996 CHK_HV(ctx); 3997 t = tcg_constant_i32(PPC_PM_SLEEP); 3998 gen_helper_pminsn(cpu_env, t); 3999 /* Stop translation, as the CPU is supposed to sleep from now */ 4000 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4001 #endif /* defined(CONFIG_USER_ONLY) */ 4002 } 4003 4004 static void gen_rvwinkle(DisasContext *ctx) 4005 { 4006 #if defined(CONFIG_USER_ONLY) 4007 GEN_PRIV(ctx); 4008 #else 4009 TCGv_i32 t; 4010 4011 CHK_HV(ctx); 4012 t = tcg_constant_i32(PPC_PM_RVWINKLE); 4013 gen_helper_pminsn(cpu_env, t); 4014 /* Stop translation, as the CPU is supposed to sleep from now */ 4015 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4016 #endif /* defined(CONFIG_USER_ONLY) */ 4017 } 4018 #endif /* #if defined(TARGET_PPC64) */ 4019 4020 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4021 { 4022 #if defined(TARGET_PPC64) 4023 if (ctx->has_cfar) { 4024 tcg_gen_movi_tl(cpu_cfar, nip); 4025 } 4026 #endif 4027 } 4028 4029 #if defined(TARGET_PPC64) 4030 static void pmu_count_insns(DisasContext *ctx) 4031 { 4032 /* 4033 * Do not bother calling the helper if the PMU isn't counting 4034 * instructions. 4035 */ 4036 if (!ctx->pmu_insn_cnt) { 4037 return; 4038 } 4039 4040 #if !defined(CONFIG_USER_ONLY) 4041 TCGLabel *l; 4042 TCGv t0; 4043 4044 /* 4045 * The PMU insns_inc() helper stops the internal PMU timer if a 4046 * counter overflows happens. In that case, if the guest is 4047 * running with icount and we do not handle it beforehand, 4048 * the helper can trigger a 'bad icount read'. 4049 */ 4050 translator_io_start(&ctx->base); 4051 4052 /* Avoid helper calls when only PMC5-6 are enabled. */ 4053 if (!ctx->pmc_other) { 4054 l = gen_new_label(); 4055 t0 = tcg_temp_new(); 4056 4057 gen_load_spr(t0, SPR_POWER_PMC5); 4058 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4059 gen_store_spr(SPR_POWER_PMC5, t0); 4060 /* Check for overflow, if it's enabled */ 4061 if (ctx->mmcr0_pmcjce) { 4062 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4063 gen_helper_handle_pmc5_overflow(cpu_env); 4064 } 4065 4066 gen_set_label(l); 4067 } else { 4068 gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4069 } 4070 #else 4071 /* 4072 * User mode can read (but not write) PMC5 and start/stop 4073 * the PMU via MMCR0_FC. In this case just increment 4074 * PMC5 with base.num_insns. 4075 */ 4076 TCGv t0 = tcg_temp_new(); 4077 4078 gen_load_spr(t0, SPR_POWER_PMC5); 4079 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4080 gen_store_spr(SPR_POWER_PMC5, t0); 4081 #endif /* #if !defined(CONFIG_USER_ONLY) */ 4082 } 4083 #else 4084 static void pmu_count_insns(DisasContext *ctx) 4085 { 4086 return; 4087 } 4088 #endif /* #if defined(TARGET_PPC64) */ 4089 4090 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4091 { 4092 return translator_use_goto_tb(&ctx->base, dest); 4093 } 4094 4095 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 4096 { 4097 if (unlikely(ctx->singlestep_enabled)) { 4098 gen_debug_exception(ctx); 4099 } else { 4100 /* 4101 * tcg_gen_lookup_and_goto_ptr will exit the TB if 4102 * CF_NO_GOTO_PTR is set. Count insns now. 4103 */ 4104 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 4105 pmu_count_insns(ctx); 4106 } 4107 4108 tcg_gen_lookup_and_goto_ptr(); 4109 } 4110 } 4111 4112 /*** Branch ***/ 4113 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4114 { 4115 if (NARROW_MODE(ctx)) { 4116 dest = (uint32_t) dest; 4117 } 4118 if (use_goto_tb(ctx, dest)) { 4119 pmu_count_insns(ctx); 4120 tcg_gen_goto_tb(n); 4121 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4122 tcg_gen_exit_tb(ctx->base.tb, n); 4123 } else { 4124 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4125 gen_lookup_and_goto_ptr(ctx); 4126 } 4127 } 4128 4129 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4130 { 4131 if (NARROW_MODE(ctx)) { 4132 nip = (uint32_t)nip; 4133 } 4134 tcg_gen_movi_tl(cpu_lr, nip); 4135 } 4136 4137 /* b ba bl bla */ 4138 static void gen_b(DisasContext *ctx) 4139 { 4140 target_ulong li, target; 4141 4142 /* sign extend LI */ 4143 li = LI(ctx->opcode); 4144 li = (li ^ 0x02000000) - 0x02000000; 4145 if (likely(AA(ctx->opcode) == 0)) { 4146 target = ctx->cia + li; 4147 } else { 4148 target = li; 4149 } 4150 if (LK(ctx->opcode)) { 4151 gen_setlr(ctx, ctx->base.pc_next); 4152 } 4153 gen_update_cfar(ctx, ctx->cia); 4154 gen_goto_tb(ctx, 0, target); 4155 ctx->base.is_jmp = DISAS_NORETURN; 4156 } 4157 4158 #define BCOND_IM 0 4159 #define BCOND_LR 1 4160 #define BCOND_CTR 2 4161 #define BCOND_TAR 3 4162 4163 static void gen_bcond(DisasContext *ctx, int type) 4164 { 4165 uint32_t bo = BO(ctx->opcode); 4166 TCGLabel *l1; 4167 TCGv target; 4168 4169 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4170 target = tcg_temp_new(); 4171 if (type == BCOND_CTR) { 4172 tcg_gen_mov_tl(target, cpu_ctr); 4173 } else if (type == BCOND_TAR) { 4174 gen_load_spr(target, SPR_TAR); 4175 } else { 4176 tcg_gen_mov_tl(target, cpu_lr); 4177 } 4178 } else { 4179 target = NULL; 4180 } 4181 if (LK(ctx->opcode)) { 4182 gen_setlr(ctx, ctx->base.pc_next); 4183 } 4184 l1 = gen_new_label(); 4185 if ((bo & 0x4) == 0) { 4186 /* Decrement and test CTR */ 4187 TCGv temp = tcg_temp_new(); 4188 4189 if (type == BCOND_CTR) { 4190 /* 4191 * All ISAs up to v3 describe this form of bcctr as invalid but 4192 * some processors, ie. 64-bit server processors compliant with 4193 * arch 2.x, do implement a "test and decrement" logic instead, 4194 * as described in their respective UMs. This logic involves CTR 4195 * to act as both the branch target and a counter, which makes 4196 * it basically useless and thus never used in real code. 4197 * 4198 * This form was hence chosen to trigger extra micro-architectural 4199 * side-effect on real HW needed for the Spectre v2 workaround. 4200 * It is up to guests that implement such workaround, ie. linux, to 4201 * use this form in a way it just triggers the side-effect without 4202 * doing anything else harmful. 4203 */ 4204 if (unlikely(!is_book3s_arch2x(ctx))) { 4205 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4206 return; 4207 } 4208 4209 if (NARROW_MODE(ctx)) { 4210 tcg_gen_ext32u_tl(temp, cpu_ctr); 4211 } else { 4212 tcg_gen_mov_tl(temp, cpu_ctr); 4213 } 4214 if (bo & 0x2) { 4215 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4216 } else { 4217 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4218 } 4219 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4220 } else { 4221 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4222 if (NARROW_MODE(ctx)) { 4223 tcg_gen_ext32u_tl(temp, cpu_ctr); 4224 } else { 4225 tcg_gen_mov_tl(temp, cpu_ctr); 4226 } 4227 if (bo & 0x2) { 4228 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4229 } else { 4230 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4231 } 4232 } 4233 } 4234 if ((bo & 0x10) == 0) { 4235 /* Test CR */ 4236 uint32_t bi = BI(ctx->opcode); 4237 uint32_t mask = 0x08 >> (bi & 0x03); 4238 TCGv_i32 temp = tcg_temp_new_i32(); 4239 4240 if (bo & 0x8) { 4241 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4242 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4243 } else { 4244 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4245 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4246 } 4247 } 4248 gen_update_cfar(ctx, ctx->cia); 4249 if (type == BCOND_IM) { 4250 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4251 if (likely(AA(ctx->opcode) == 0)) { 4252 gen_goto_tb(ctx, 0, ctx->cia + li); 4253 } else { 4254 gen_goto_tb(ctx, 0, li); 4255 } 4256 } else { 4257 if (NARROW_MODE(ctx)) { 4258 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4259 } else { 4260 tcg_gen_andi_tl(cpu_nip, target, ~3); 4261 } 4262 gen_lookup_and_goto_ptr(ctx); 4263 } 4264 if ((bo & 0x14) != 0x14) { 4265 /* fallthrough case */ 4266 gen_set_label(l1); 4267 gen_goto_tb(ctx, 1, ctx->base.pc_next); 4268 } 4269 ctx->base.is_jmp = DISAS_NORETURN; 4270 } 4271 4272 static void gen_bc(DisasContext *ctx) 4273 { 4274 gen_bcond(ctx, BCOND_IM); 4275 } 4276 4277 static void gen_bcctr(DisasContext *ctx) 4278 { 4279 gen_bcond(ctx, BCOND_CTR); 4280 } 4281 4282 static void gen_bclr(DisasContext *ctx) 4283 { 4284 gen_bcond(ctx, BCOND_LR); 4285 } 4286 4287 static void gen_bctar(DisasContext *ctx) 4288 { 4289 gen_bcond(ctx, BCOND_TAR); 4290 } 4291 4292 /*** Condition register logical ***/ 4293 #define GEN_CRLOGIC(name, tcg_op, opc) \ 4294 static void glue(gen_, name)(DisasContext *ctx) \ 4295 { \ 4296 uint8_t bitmask; \ 4297 int sh; \ 4298 TCGv_i32 t0, t1; \ 4299 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4300 t0 = tcg_temp_new_i32(); \ 4301 if (sh > 0) \ 4302 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4303 else if (sh < 0) \ 4304 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4305 else \ 4306 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4307 t1 = tcg_temp_new_i32(); \ 4308 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4309 if (sh > 0) \ 4310 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4311 else if (sh < 0) \ 4312 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4313 else \ 4314 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4315 tcg_op(t0, t0, t1); \ 4316 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4317 tcg_gen_andi_i32(t0, t0, bitmask); \ 4318 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4319 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4320 } 4321 4322 /* crand */ 4323 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4324 /* crandc */ 4325 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4326 /* creqv */ 4327 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4328 /* crnand */ 4329 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4330 /* crnor */ 4331 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4332 /* cror */ 4333 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4334 /* crorc */ 4335 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4336 /* crxor */ 4337 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4338 4339 /* mcrf */ 4340 static void gen_mcrf(DisasContext *ctx) 4341 { 4342 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4343 } 4344 4345 /*** System linkage ***/ 4346 4347 /* rfi (supervisor only) */ 4348 static void gen_rfi(DisasContext *ctx) 4349 { 4350 #if defined(CONFIG_USER_ONLY) 4351 GEN_PRIV(ctx); 4352 #else 4353 /* 4354 * This instruction doesn't exist anymore on 64-bit server 4355 * processors compliant with arch 2.x 4356 */ 4357 if (is_book3s_arch2x(ctx)) { 4358 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4359 return; 4360 } 4361 /* Restore CPU state */ 4362 CHK_SV(ctx); 4363 translator_io_start(&ctx->base); 4364 gen_update_cfar(ctx, ctx->cia); 4365 gen_helper_rfi(cpu_env); 4366 ctx->base.is_jmp = DISAS_EXIT; 4367 #endif 4368 } 4369 4370 #if defined(TARGET_PPC64) 4371 static void gen_rfid(DisasContext *ctx) 4372 { 4373 #if defined(CONFIG_USER_ONLY) 4374 GEN_PRIV(ctx); 4375 #else 4376 /* Restore CPU state */ 4377 CHK_SV(ctx); 4378 translator_io_start(&ctx->base); 4379 gen_update_cfar(ctx, ctx->cia); 4380 gen_helper_rfid(cpu_env); 4381 ctx->base.is_jmp = DISAS_EXIT; 4382 #endif 4383 } 4384 4385 #if !defined(CONFIG_USER_ONLY) 4386 static void gen_rfscv(DisasContext *ctx) 4387 { 4388 #if defined(CONFIG_USER_ONLY) 4389 GEN_PRIV(ctx); 4390 #else 4391 /* Restore CPU state */ 4392 CHK_SV(ctx); 4393 translator_io_start(&ctx->base); 4394 gen_update_cfar(ctx, ctx->cia); 4395 gen_helper_rfscv(cpu_env); 4396 ctx->base.is_jmp = DISAS_EXIT; 4397 #endif 4398 } 4399 #endif 4400 4401 static void gen_hrfid(DisasContext *ctx) 4402 { 4403 #if defined(CONFIG_USER_ONLY) 4404 GEN_PRIV(ctx); 4405 #else 4406 /* Restore CPU state */ 4407 CHK_HV(ctx); 4408 gen_helper_hrfid(cpu_env); 4409 ctx->base.is_jmp = DISAS_EXIT; 4410 #endif 4411 } 4412 #endif 4413 4414 /* sc */ 4415 #if defined(CONFIG_USER_ONLY) 4416 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4417 #else 4418 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4419 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4420 #endif 4421 static void gen_sc(DisasContext *ctx) 4422 { 4423 uint32_t lev; 4424 4425 lev = (ctx->opcode >> 5) & 0x7F; 4426 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4427 } 4428 4429 #if defined(TARGET_PPC64) 4430 #if !defined(CONFIG_USER_ONLY) 4431 static void gen_scv(DisasContext *ctx) 4432 { 4433 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 4434 4435 /* Set the PC back to the faulting instruction. */ 4436 gen_update_nip(ctx, ctx->cia); 4437 gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 4438 4439 ctx->base.is_jmp = DISAS_NORETURN; 4440 } 4441 #endif 4442 #endif 4443 4444 /*** Trap ***/ 4445 4446 /* Check for unconditional traps (always or never) */ 4447 static bool check_unconditional_trap(DisasContext *ctx) 4448 { 4449 /* Trap never */ 4450 if (TO(ctx->opcode) == 0) { 4451 return true; 4452 } 4453 /* Trap always */ 4454 if (TO(ctx->opcode) == 31) { 4455 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4456 return true; 4457 } 4458 return false; 4459 } 4460 4461 /* tw */ 4462 static void gen_tw(DisasContext *ctx) 4463 { 4464 TCGv_i32 t0; 4465 4466 if (check_unconditional_trap(ctx)) { 4467 return; 4468 } 4469 t0 = tcg_constant_i32(TO(ctx->opcode)); 4470 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4471 t0); 4472 } 4473 4474 /* twi */ 4475 static void gen_twi(DisasContext *ctx) 4476 { 4477 TCGv t0; 4478 TCGv_i32 t1; 4479 4480 if (check_unconditional_trap(ctx)) { 4481 return; 4482 } 4483 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4484 t1 = tcg_constant_i32(TO(ctx->opcode)); 4485 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4486 } 4487 4488 #if defined(TARGET_PPC64) 4489 /* td */ 4490 static void gen_td(DisasContext *ctx) 4491 { 4492 TCGv_i32 t0; 4493 4494 if (check_unconditional_trap(ctx)) { 4495 return; 4496 } 4497 t0 = tcg_constant_i32(TO(ctx->opcode)); 4498 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4499 t0); 4500 } 4501 4502 /* tdi */ 4503 static void gen_tdi(DisasContext *ctx) 4504 { 4505 TCGv t0; 4506 TCGv_i32 t1; 4507 4508 if (check_unconditional_trap(ctx)) { 4509 return; 4510 } 4511 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4512 t1 = tcg_constant_i32(TO(ctx->opcode)); 4513 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4514 } 4515 #endif 4516 4517 /*** Processor control ***/ 4518 4519 /* mcrxr */ 4520 static void gen_mcrxr(DisasContext *ctx) 4521 { 4522 TCGv_i32 t0 = tcg_temp_new_i32(); 4523 TCGv_i32 t1 = tcg_temp_new_i32(); 4524 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4525 4526 tcg_gen_trunc_tl_i32(t0, cpu_so); 4527 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4528 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4529 tcg_gen_shli_i32(t0, t0, 3); 4530 tcg_gen_shli_i32(t1, t1, 2); 4531 tcg_gen_shli_i32(dst, dst, 1); 4532 tcg_gen_or_i32(dst, dst, t0); 4533 tcg_gen_or_i32(dst, dst, t1); 4534 4535 tcg_gen_movi_tl(cpu_so, 0); 4536 tcg_gen_movi_tl(cpu_ov, 0); 4537 tcg_gen_movi_tl(cpu_ca, 0); 4538 } 4539 4540 #ifdef TARGET_PPC64 4541 /* mcrxrx */ 4542 static void gen_mcrxrx(DisasContext *ctx) 4543 { 4544 TCGv t0 = tcg_temp_new(); 4545 TCGv t1 = tcg_temp_new(); 4546 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4547 4548 /* copy OV and OV32 */ 4549 tcg_gen_shli_tl(t0, cpu_ov, 1); 4550 tcg_gen_or_tl(t0, t0, cpu_ov32); 4551 tcg_gen_shli_tl(t0, t0, 2); 4552 /* copy CA and CA32 */ 4553 tcg_gen_shli_tl(t1, cpu_ca, 1); 4554 tcg_gen_or_tl(t1, t1, cpu_ca32); 4555 tcg_gen_or_tl(t0, t0, t1); 4556 tcg_gen_trunc_tl_i32(dst, t0); 4557 } 4558 #endif 4559 4560 /* mfcr mfocrf */ 4561 static void gen_mfcr(DisasContext *ctx) 4562 { 4563 uint32_t crm, crn; 4564 4565 if (likely(ctx->opcode & 0x00100000)) { 4566 crm = CRM(ctx->opcode); 4567 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4568 crn = ctz32(crm); 4569 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4570 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4571 cpu_gpr[rD(ctx->opcode)], crn * 4); 4572 } 4573 } else { 4574 TCGv_i32 t0 = tcg_temp_new_i32(); 4575 tcg_gen_mov_i32(t0, cpu_crf[0]); 4576 tcg_gen_shli_i32(t0, t0, 4); 4577 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4578 tcg_gen_shli_i32(t0, t0, 4); 4579 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4580 tcg_gen_shli_i32(t0, t0, 4); 4581 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4582 tcg_gen_shli_i32(t0, t0, 4); 4583 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4584 tcg_gen_shli_i32(t0, t0, 4); 4585 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4586 tcg_gen_shli_i32(t0, t0, 4); 4587 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4588 tcg_gen_shli_i32(t0, t0, 4); 4589 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4590 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4591 } 4592 } 4593 4594 /* mfmsr */ 4595 static void gen_mfmsr(DisasContext *ctx) 4596 { 4597 CHK_SV(ctx); 4598 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4599 } 4600 4601 /* mfspr */ 4602 static inline void gen_op_mfspr(DisasContext *ctx) 4603 { 4604 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4605 uint32_t sprn = SPR(ctx->opcode); 4606 4607 #if defined(CONFIG_USER_ONLY) 4608 read_cb = ctx->spr_cb[sprn].uea_read; 4609 #else 4610 if (ctx->pr) { 4611 read_cb = ctx->spr_cb[sprn].uea_read; 4612 } else if (ctx->hv) { 4613 read_cb = ctx->spr_cb[sprn].hea_read; 4614 } else { 4615 read_cb = ctx->spr_cb[sprn].oea_read; 4616 } 4617 #endif 4618 if (likely(read_cb != NULL)) { 4619 if (likely(read_cb != SPR_NOACCESS)) { 4620 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4621 } else { 4622 /* Privilege exception */ 4623 /* 4624 * This is a hack to avoid warnings when running Linux: 4625 * this OS breaks the PowerPC virtualisation model, 4626 * allowing userland application to read the PVR 4627 */ 4628 if (sprn != SPR_PVR) { 4629 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4630 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4631 ctx->cia); 4632 } 4633 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4634 } 4635 } else { 4636 /* ISA 2.07 defines these as no-ops */ 4637 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4638 (sprn >= 808 && sprn <= 811)) { 4639 /* This is a nop */ 4640 return; 4641 } 4642 /* Not defined */ 4643 qemu_log_mask(LOG_GUEST_ERROR, 4644 "Trying to read invalid spr %d (0x%03x) at " 4645 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4646 4647 /* 4648 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4649 * generate a priv, a hv emu or a no-op 4650 */ 4651 if (sprn & 0x10) { 4652 if (ctx->pr) { 4653 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4654 } 4655 } else { 4656 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4657 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4658 } 4659 } 4660 } 4661 } 4662 4663 static void gen_mfspr(DisasContext *ctx) 4664 { 4665 gen_op_mfspr(ctx); 4666 } 4667 4668 /* mftb */ 4669 static void gen_mftb(DisasContext *ctx) 4670 { 4671 gen_op_mfspr(ctx); 4672 } 4673 4674 /* mtcrf mtocrf*/ 4675 static void gen_mtcrf(DisasContext *ctx) 4676 { 4677 uint32_t crm, crn; 4678 4679 crm = CRM(ctx->opcode); 4680 if (likely((ctx->opcode & 0x00100000))) { 4681 if (crm && ((crm & (crm - 1)) == 0)) { 4682 TCGv_i32 temp = tcg_temp_new_i32(); 4683 crn = ctz32(crm); 4684 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4685 tcg_gen_shri_i32(temp, temp, crn * 4); 4686 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4687 } 4688 } else { 4689 TCGv_i32 temp = tcg_temp_new_i32(); 4690 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4691 for (crn = 0 ; crn < 8 ; crn++) { 4692 if (crm & (1 << crn)) { 4693 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4694 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4695 } 4696 } 4697 } 4698 } 4699 4700 /* mtmsr */ 4701 #if defined(TARGET_PPC64) 4702 static void gen_mtmsrd(DisasContext *ctx) 4703 { 4704 if (unlikely(!is_book3s_arch2x(ctx))) { 4705 gen_invalid(ctx); 4706 return; 4707 } 4708 4709 CHK_SV(ctx); 4710 4711 #if !defined(CONFIG_USER_ONLY) 4712 TCGv t0, t1; 4713 target_ulong mask; 4714 4715 t0 = tcg_temp_new(); 4716 t1 = tcg_temp_new(); 4717 4718 translator_io_start(&ctx->base); 4719 4720 if (ctx->opcode & 0x00010000) { 4721 /* L=1 form only updates EE and RI */ 4722 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4723 } else { 4724 /* mtmsrd does not alter HV, S, ME, or LE */ 4725 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4726 (1ULL << MSR_HV)); 4727 /* 4728 * XXX: we need to update nip before the store if we enter 4729 * power saving mode, we will exit the loop directly from 4730 * ppc_store_msr 4731 */ 4732 gen_update_nip(ctx, ctx->base.pc_next); 4733 } 4734 4735 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4736 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4737 tcg_gen_or_tl(t0, t0, t1); 4738 4739 gen_helper_store_msr(cpu_env, t0); 4740 4741 /* Must stop the translation as machine state (may have) changed */ 4742 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4743 #endif /* !defined(CONFIG_USER_ONLY) */ 4744 } 4745 #endif /* defined(TARGET_PPC64) */ 4746 4747 static void gen_mtmsr(DisasContext *ctx) 4748 { 4749 CHK_SV(ctx); 4750 4751 #if !defined(CONFIG_USER_ONLY) 4752 TCGv t0, t1; 4753 target_ulong mask = 0xFFFFFFFF; 4754 4755 t0 = tcg_temp_new(); 4756 t1 = tcg_temp_new(); 4757 4758 translator_io_start(&ctx->base); 4759 if (ctx->opcode & 0x00010000) { 4760 /* L=1 form only updates EE and RI */ 4761 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4762 } else { 4763 /* mtmsr does not alter S, ME, or LE */ 4764 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4765 4766 /* 4767 * XXX: we need to update nip before the store if we enter 4768 * power saving mode, we will exit the loop directly from 4769 * ppc_store_msr 4770 */ 4771 gen_update_nip(ctx, ctx->base.pc_next); 4772 } 4773 4774 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4775 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4776 tcg_gen_or_tl(t0, t0, t1); 4777 4778 gen_helper_store_msr(cpu_env, t0); 4779 4780 /* Must stop the translation as machine state (may have) changed */ 4781 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4782 #endif 4783 } 4784 4785 /* mtspr */ 4786 static void gen_mtspr(DisasContext *ctx) 4787 { 4788 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4789 uint32_t sprn = SPR(ctx->opcode); 4790 4791 #if defined(CONFIG_USER_ONLY) 4792 write_cb = ctx->spr_cb[sprn].uea_write; 4793 #else 4794 if (ctx->pr) { 4795 write_cb = ctx->spr_cb[sprn].uea_write; 4796 } else if (ctx->hv) { 4797 write_cb = ctx->spr_cb[sprn].hea_write; 4798 } else { 4799 write_cb = ctx->spr_cb[sprn].oea_write; 4800 } 4801 #endif 4802 if (likely(write_cb != NULL)) { 4803 if (likely(write_cb != SPR_NOACCESS)) { 4804 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4805 } else { 4806 /* Privilege exception */ 4807 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4808 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4809 ctx->cia); 4810 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4811 } 4812 } else { 4813 /* ISA 2.07 defines these as no-ops */ 4814 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4815 (sprn >= 808 && sprn <= 811)) { 4816 /* This is a nop */ 4817 return; 4818 } 4819 4820 /* Not defined */ 4821 qemu_log_mask(LOG_GUEST_ERROR, 4822 "Trying to write invalid spr %d (0x%03x) at " 4823 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4824 4825 4826 /* 4827 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4828 * generate a priv, a hv emu or a no-op 4829 */ 4830 if (sprn & 0x10) { 4831 if (ctx->pr) { 4832 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4833 } 4834 } else { 4835 if (ctx->pr || sprn == 0) { 4836 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4837 } 4838 } 4839 } 4840 } 4841 4842 #if defined(TARGET_PPC64) 4843 /* setb */ 4844 static void gen_setb(DisasContext *ctx) 4845 { 4846 TCGv_i32 t0 = tcg_temp_new_i32(); 4847 TCGv_i32 t8 = tcg_constant_i32(8); 4848 TCGv_i32 tm1 = tcg_constant_i32(-1); 4849 int crf = crfS(ctx->opcode); 4850 4851 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4852 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4853 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4854 } 4855 #endif 4856 4857 /*** Cache management ***/ 4858 4859 /* dcbf */ 4860 static void gen_dcbf(DisasContext *ctx) 4861 { 4862 /* XXX: specification says this is treated as a load by the MMU */ 4863 TCGv t0; 4864 gen_set_access_type(ctx, ACCESS_CACHE); 4865 t0 = tcg_temp_new(); 4866 gen_addr_reg_index(ctx, t0); 4867 gen_qemu_ld8u(ctx, t0, t0); 4868 } 4869 4870 /* dcbfep (external PID dcbf) */ 4871 static void gen_dcbfep(DisasContext *ctx) 4872 { 4873 /* XXX: specification says this is treated as a load by the MMU */ 4874 TCGv t0; 4875 CHK_SV(ctx); 4876 gen_set_access_type(ctx, ACCESS_CACHE); 4877 t0 = tcg_temp_new(); 4878 gen_addr_reg_index(ctx, t0); 4879 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4880 } 4881 4882 /* dcbi (Supervisor only) */ 4883 static void gen_dcbi(DisasContext *ctx) 4884 { 4885 #if defined(CONFIG_USER_ONLY) 4886 GEN_PRIV(ctx); 4887 #else 4888 TCGv EA, val; 4889 4890 CHK_SV(ctx); 4891 EA = tcg_temp_new(); 4892 gen_set_access_type(ctx, ACCESS_CACHE); 4893 gen_addr_reg_index(ctx, EA); 4894 val = tcg_temp_new(); 4895 /* XXX: specification says this should be treated as a store by the MMU */ 4896 gen_qemu_ld8u(ctx, val, EA); 4897 gen_qemu_st8(ctx, val, EA); 4898 #endif /* defined(CONFIG_USER_ONLY) */ 4899 } 4900 4901 /* dcdst */ 4902 static void gen_dcbst(DisasContext *ctx) 4903 { 4904 /* XXX: specification say this is treated as a load by the MMU */ 4905 TCGv t0; 4906 gen_set_access_type(ctx, ACCESS_CACHE); 4907 t0 = tcg_temp_new(); 4908 gen_addr_reg_index(ctx, t0); 4909 gen_qemu_ld8u(ctx, t0, t0); 4910 } 4911 4912 /* dcbstep (dcbstep External PID version) */ 4913 static void gen_dcbstep(DisasContext *ctx) 4914 { 4915 /* XXX: specification say this is treated as a load by the MMU */ 4916 TCGv t0; 4917 gen_set_access_type(ctx, ACCESS_CACHE); 4918 t0 = tcg_temp_new(); 4919 gen_addr_reg_index(ctx, t0); 4920 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4921 } 4922 4923 /* dcbt */ 4924 static void gen_dcbt(DisasContext *ctx) 4925 { 4926 /* 4927 * interpreted as no-op 4928 * XXX: specification say this is treated as a load by the MMU but 4929 * does not generate any exception 4930 */ 4931 } 4932 4933 /* dcbtep */ 4934 static void gen_dcbtep(DisasContext *ctx) 4935 { 4936 /* 4937 * interpreted as no-op 4938 * XXX: specification say this is treated as a load by the MMU but 4939 * does not generate any exception 4940 */ 4941 } 4942 4943 /* dcbtst */ 4944 static void gen_dcbtst(DisasContext *ctx) 4945 { 4946 /* 4947 * interpreted as no-op 4948 * XXX: specification say this is treated as a load by the MMU but 4949 * does not generate any exception 4950 */ 4951 } 4952 4953 /* dcbtstep */ 4954 static void gen_dcbtstep(DisasContext *ctx) 4955 { 4956 /* 4957 * interpreted as no-op 4958 * XXX: specification say this is treated as a load by the MMU but 4959 * does not generate any exception 4960 */ 4961 } 4962 4963 /* dcbtls */ 4964 static void gen_dcbtls(DisasContext *ctx) 4965 { 4966 /* Always fails locking the cache */ 4967 TCGv t0 = tcg_temp_new(); 4968 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4969 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4970 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4971 } 4972 4973 /* dcblc */ 4974 static void gen_dcblc(DisasContext *ctx) 4975 { 4976 /* 4977 * interpreted as no-op 4978 */ 4979 } 4980 4981 /* dcbz */ 4982 static void gen_dcbz(DisasContext *ctx) 4983 { 4984 TCGv tcgv_addr; 4985 TCGv_i32 tcgv_op; 4986 4987 gen_set_access_type(ctx, ACCESS_CACHE); 4988 tcgv_addr = tcg_temp_new(); 4989 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 4990 gen_addr_reg_index(ctx, tcgv_addr); 4991 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4992 } 4993 4994 /* dcbzep */ 4995 static void gen_dcbzep(DisasContext *ctx) 4996 { 4997 TCGv tcgv_addr; 4998 TCGv_i32 tcgv_op; 4999 5000 gen_set_access_type(ctx, ACCESS_CACHE); 5001 tcgv_addr = tcg_temp_new(); 5002 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5003 gen_addr_reg_index(ctx, tcgv_addr); 5004 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 5005 } 5006 5007 /* dst / dstt */ 5008 static void gen_dst(DisasContext *ctx) 5009 { 5010 if (rA(ctx->opcode) == 0) { 5011 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5012 } else { 5013 /* interpreted as no-op */ 5014 } 5015 } 5016 5017 /* dstst /dststt */ 5018 static void gen_dstst(DisasContext *ctx) 5019 { 5020 if (rA(ctx->opcode) == 0) { 5021 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5022 } else { 5023 /* interpreted as no-op */ 5024 } 5025 5026 } 5027 5028 /* dss / dssall */ 5029 static void gen_dss(DisasContext *ctx) 5030 { 5031 /* interpreted as no-op */ 5032 } 5033 5034 /* icbi */ 5035 static void gen_icbi(DisasContext *ctx) 5036 { 5037 TCGv t0; 5038 gen_set_access_type(ctx, ACCESS_CACHE); 5039 t0 = tcg_temp_new(); 5040 gen_addr_reg_index(ctx, t0); 5041 gen_helper_icbi(cpu_env, t0); 5042 } 5043 5044 /* icbiep */ 5045 static void gen_icbiep(DisasContext *ctx) 5046 { 5047 TCGv t0; 5048 gen_set_access_type(ctx, ACCESS_CACHE); 5049 t0 = tcg_temp_new(); 5050 gen_addr_reg_index(ctx, t0); 5051 gen_helper_icbiep(cpu_env, t0); 5052 } 5053 5054 /* Optional: */ 5055 /* dcba */ 5056 static void gen_dcba(DisasContext *ctx) 5057 { 5058 /* 5059 * interpreted as no-op 5060 * XXX: specification say this is treated as a store by the MMU 5061 * but does not generate any exception 5062 */ 5063 } 5064 5065 /*** Segment register manipulation ***/ 5066 /* Supervisor only: */ 5067 5068 /* mfsr */ 5069 static void gen_mfsr(DisasContext *ctx) 5070 { 5071 #if defined(CONFIG_USER_ONLY) 5072 GEN_PRIV(ctx); 5073 #else 5074 TCGv t0; 5075 5076 CHK_SV(ctx); 5077 t0 = tcg_constant_tl(SR(ctx->opcode)); 5078 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5079 #endif /* defined(CONFIG_USER_ONLY) */ 5080 } 5081 5082 /* mfsrin */ 5083 static void gen_mfsrin(DisasContext *ctx) 5084 { 5085 #if defined(CONFIG_USER_ONLY) 5086 GEN_PRIV(ctx); 5087 #else 5088 TCGv t0; 5089 5090 CHK_SV(ctx); 5091 t0 = tcg_temp_new(); 5092 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5093 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5094 #endif /* defined(CONFIG_USER_ONLY) */ 5095 } 5096 5097 /* mtsr */ 5098 static void gen_mtsr(DisasContext *ctx) 5099 { 5100 #if defined(CONFIG_USER_ONLY) 5101 GEN_PRIV(ctx); 5102 #else 5103 TCGv t0; 5104 5105 CHK_SV(ctx); 5106 t0 = tcg_constant_tl(SR(ctx->opcode)); 5107 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5108 #endif /* defined(CONFIG_USER_ONLY) */ 5109 } 5110 5111 /* mtsrin */ 5112 static void gen_mtsrin(DisasContext *ctx) 5113 { 5114 #if defined(CONFIG_USER_ONLY) 5115 GEN_PRIV(ctx); 5116 #else 5117 TCGv t0; 5118 CHK_SV(ctx); 5119 5120 t0 = tcg_temp_new(); 5121 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5122 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5123 #endif /* defined(CONFIG_USER_ONLY) */ 5124 } 5125 5126 #if defined(TARGET_PPC64) 5127 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5128 5129 /* mfsr */ 5130 static void gen_mfsr_64b(DisasContext *ctx) 5131 { 5132 #if defined(CONFIG_USER_ONLY) 5133 GEN_PRIV(ctx); 5134 #else 5135 TCGv t0; 5136 5137 CHK_SV(ctx); 5138 t0 = tcg_constant_tl(SR(ctx->opcode)); 5139 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5140 #endif /* defined(CONFIG_USER_ONLY) */ 5141 } 5142 5143 /* mfsrin */ 5144 static void gen_mfsrin_64b(DisasContext *ctx) 5145 { 5146 #if defined(CONFIG_USER_ONLY) 5147 GEN_PRIV(ctx); 5148 #else 5149 TCGv t0; 5150 5151 CHK_SV(ctx); 5152 t0 = tcg_temp_new(); 5153 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5154 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5155 #endif /* defined(CONFIG_USER_ONLY) */ 5156 } 5157 5158 /* mtsr */ 5159 static void gen_mtsr_64b(DisasContext *ctx) 5160 { 5161 #if defined(CONFIG_USER_ONLY) 5162 GEN_PRIV(ctx); 5163 #else 5164 TCGv t0; 5165 5166 CHK_SV(ctx); 5167 t0 = tcg_constant_tl(SR(ctx->opcode)); 5168 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5169 #endif /* defined(CONFIG_USER_ONLY) */ 5170 } 5171 5172 /* mtsrin */ 5173 static void gen_mtsrin_64b(DisasContext *ctx) 5174 { 5175 #if defined(CONFIG_USER_ONLY) 5176 GEN_PRIV(ctx); 5177 #else 5178 TCGv t0; 5179 5180 CHK_SV(ctx); 5181 t0 = tcg_temp_new(); 5182 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5183 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5184 #endif /* defined(CONFIG_USER_ONLY) */ 5185 } 5186 5187 #endif /* defined(TARGET_PPC64) */ 5188 5189 /*** Lookaside buffer management ***/ 5190 /* Optional & supervisor only: */ 5191 5192 /* tlbia */ 5193 static void gen_tlbia(DisasContext *ctx) 5194 { 5195 #if defined(CONFIG_USER_ONLY) 5196 GEN_PRIV(ctx); 5197 #else 5198 CHK_HV(ctx); 5199 5200 gen_helper_tlbia(cpu_env); 5201 #endif /* defined(CONFIG_USER_ONLY) */ 5202 } 5203 5204 /* tlbsync */ 5205 static void gen_tlbsync(DisasContext *ctx) 5206 { 5207 #if defined(CONFIG_USER_ONLY) 5208 GEN_PRIV(ctx); 5209 #else 5210 5211 if (ctx->gtse) { 5212 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 5213 } else { 5214 CHK_HV(ctx); /* Else hypervisor privileged */ 5215 } 5216 5217 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5218 if (ctx->insns_flags & PPC_BOOKE) { 5219 gen_check_tlb_flush(ctx, true); 5220 } 5221 #endif /* defined(CONFIG_USER_ONLY) */ 5222 } 5223 5224 /*** External control ***/ 5225 /* Optional: */ 5226 5227 /* eciwx */ 5228 static void gen_eciwx(DisasContext *ctx) 5229 { 5230 TCGv t0; 5231 /* Should check EAR[E] ! */ 5232 gen_set_access_type(ctx, ACCESS_EXT); 5233 t0 = tcg_temp_new(); 5234 gen_addr_reg_index(ctx, t0); 5235 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5236 DEF_MEMOP(MO_UL | MO_ALIGN)); 5237 } 5238 5239 /* ecowx */ 5240 static void gen_ecowx(DisasContext *ctx) 5241 { 5242 TCGv t0; 5243 /* Should check EAR[E] ! */ 5244 gen_set_access_type(ctx, ACCESS_EXT); 5245 t0 = tcg_temp_new(); 5246 gen_addr_reg_index(ctx, t0); 5247 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5248 DEF_MEMOP(MO_UL | MO_ALIGN)); 5249 } 5250 5251 /* 602 - 603 - G2 TLB management */ 5252 5253 /* tlbld */ 5254 static void gen_tlbld_6xx(DisasContext *ctx) 5255 { 5256 #if defined(CONFIG_USER_ONLY) 5257 GEN_PRIV(ctx); 5258 #else 5259 CHK_SV(ctx); 5260 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5261 #endif /* defined(CONFIG_USER_ONLY) */ 5262 } 5263 5264 /* tlbli */ 5265 static void gen_tlbli_6xx(DisasContext *ctx) 5266 { 5267 #if defined(CONFIG_USER_ONLY) 5268 GEN_PRIV(ctx); 5269 #else 5270 CHK_SV(ctx); 5271 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5272 #endif /* defined(CONFIG_USER_ONLY) */ 5273 } 5274 5275 /* BookE specific instructions */ 5276 5277 /* XXX: not implemented on 440 ? */ 5278 static void gen_mfapidi(DisasContext *ctx) 5279 { 5280 /* XXX: TODO */ 5281 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5282 } 5283 5284 /* XXX: not implemented on 440 ? */ 5285 static void gen_tlbiva(DisasContext *ctx) 5286 { 5287 #if defined(CONFIG_USER_ONLY) 5288 GEN_PRIV(ctx); 5289 #else 5290 TCGv t0; 5291 5292 CHK_SV(ctx); 5293 t0 = tcg_temp_new(); 5294 gen_addr_reg_index(ctx, t0); 5295 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5296 #endif /* defined(CONFIG_USER_ONLY) */ 5297 } 5298 5299 /* All 405 MAC instructions are translated here */ 5300 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5301 int ra, int rb, int rt, int Rc) 5302 { 5303 TCGv t0, t1; 5304 5305 t0 = tcg_temp_new(); 5306 t1 = tcg_temp_new(); 5307 5308 switch (opc3 & 0x0D) { 5309 case 0x05: 5310 /* macchw - macchw. - macchwo - macchwo. */ 5311 /* macchws - macchws. - macchwso - macchwso. */ 5312 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5313 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5314 /* mulchw - mulchw. */ 5315 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5316 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5317 tcg_gen_ext16s_tl(t1, t1); 5318 break; 5319 case 0x04: 5320 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5321 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5322 /* mulchwu - mulchwu. */ 5323 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5324 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5325 tcg_gen_ext16u_tl(t1, t1); 5326 break; 5327 case 0x01: 5328 /* machhw - machhw. - machhwo - machhwo. */ 5329 /* machhws - machhws. - machhwso - machhwso. */ 5330 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5331 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5332 /* mulhhw - mulhhw. */ 5333 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5334 tcg_gen_ext16s_tl(t0, t0); 5335 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5336 tcg_gen_ext16s_tl(t1, t1); 5337 break; 5338 case 0x00: 5339 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5340 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5341 /* mulhhwu - mulhhwu. */ 5342 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5343 tcg_gen_ext16u_tl(t0, t0); 5344 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5345 tcg_gen_ext16u_tl(t1, t1); 5346 break; 5347 case 0x0D: 5348 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5349 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5350 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5351 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5352 /* mullhw - mullhw. */ 5353 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5354 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5355 break; 5356 case 0x0C: 5357 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5358 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5359 /* mullhwu - mullhwu. */ 5360 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5361 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5362 break; 5363 } 5364 if (opc2 & 0x04) { 5365 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5366 tcg_gen_mul_tl(t1, t0, t1); 5367 if (opc2 & 0x02) { 5368 /* nmultiply-and-accumulate (0x0E) */ 5369 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5370 } else { 5371 /* multiply-and-accumulate (0x0C) */ 5372 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5373 } 5374 5375 if (opc3 & 0x12) { 5376 /* Check overflow and/or saturate */ 5377 TCGLabel *l1 = gen_new_label(); 5378 5379 if (opc3 & 0x10) { 5380 /* Start with XER OV disabled, the most likely case */ 5381 tcg_gen_movi_tl(cpu_ov, 0); 5382 } 5383 if (opc3 & 0x01) { 5384 /* Signed */ 5385 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5386 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5387 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5388 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5389 if (opc3 & 0x02) { 5390 /* Saturate */ 5391 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5392 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5393 } 5394 } else { 5395 /* Unsigned */ 5396 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5397 if (opc3 & 0x02) { 5398 /* Saturate */ 5399 tcg_gen_movi_tl(t0, UINT32_MAX); 5400 } 5401 } 5402 if (opc3 & 0x10) { 5403 /* Check overflow */ 5404 tcg_gen_movi_tl(cpu_ov, 1); 5405 tcg_gen_movi_tl(cpu_so, 1); 5406 } 5407 gen_set_label(l1); 5408 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5409 } 5410 } else { 5411 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5412 } 5413 if (unlikely(Rc) != 0) { 5414 /* Update Rc0 */ 5415 gen_set_Rc0(ctx, cpu_gpr[rt]); 5416 } 5417 } 5418 5419 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5420 static void glue(gen_, name)(DisasContext *ctx) \ 5421 { \ 5422 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5423 rD(ctx->opcode), Rc(ctx->opcode)); \ 5424 } 5425 5426 /* macchw - macchw. */ 5427 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5428 /* macchwo - macchwo. */ 5429 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5430 /* macchws - macchws. */ 5431 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5432 /* macchwso - macchwso. */ 5433 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5434 /* macchwsu - macchwsu. */ 5435 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5436 /* macchwsuo - macchwsuo. */ 5437 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5438 /* macchwu - macchwu. */ 5439 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5440 /* macchwuo - macchwuo. */ 5441 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5442 /* machhw - machhw. */ 5443 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5444 /* machhwo - machhwo. */ 5445 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5446 /* machhws - machhws. */ 5447 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5448 /* machhwso - machhwso. */ 5449 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5450 /* machhwsu - machhwsu. */ 5451 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5452 /* machhwsuo - machhwsuo. */ 5453 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5454 /* machhwu - machhwu. */ 5455 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5456 /* machhwuo - machhwuo. */ 5457 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5458 /* maclhw - maclhw. */ 5459 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5460 /* maclhwo - maclhwo. */ 5461 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5462 /* maclhws - maclhws. */ 5463 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5464 /* maclhwso - maclhwso. */ 5465 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5466 /* maclhwu - maclhwu. */ 5467 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5468 /* maclhwuo - maclhwuo. */ 5469 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5470 /* maclhwsu - maclhwsu. */ 5471 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5472 /* maclhwsuo - maclhwsuo. */ 5473 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5474 /* nmacchw - nmacchw. */ 5475 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5476 /* nmacchwo - nmacchwo. */ 5477 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5478 /* nmacchws - nmacchws. */ 5479 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5480 /* nmacchwso - nmacchwso. */ 5481 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5482 /* nmachhw - nmachhw. */ 5483 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5484 /* nmachhwo - nmachhwo. */ 5485 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5486 /* nmachhws - nmachhws. */ 5487 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5488 /* nmachhwso - nmachhwso. */ 5489 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5490 /* nmaclhw - nmaclhw. */ 5491 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5492 /* nmaclhwo - nmaclhwo. */ 5493 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5494 /* nmaclhws - nmaclhws. */ 5495 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5496 /* nmaclhwso - nmaclhwso. */ 5497 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5498 5499 /* mulchw - mulchw. */ 5500 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5501 /* mulchwu - mulchwu. */ 5502 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5503 /* mulhhw - mulhhw. */ 5504 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5505 /* mulhhwu - mulhhwu. */ 5506 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5507 /* mullhw - mullhw. */ 5508 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5509 /* mullhwu - mullhwu. */ 5510 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5511 5512 /* mfdcr */ 5513 static void gen_mfdcr(DisasContext *ctx) 5514 { 5515 #if defined(CONFIG_USER_ONLY) 5516 GEN_PRIV(ctx); 5517 #else 5518 TCGv dcrn; 5519 5520 CHK_SV(ctx); 5521 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5522 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5523 #endif /* defined(CONFIG_USER_ONLY) */ 5524 } 5525 5526 /* mtdcr */ 5527 static void gen_mtdcr(DisasContext *ctx) 5528 { 5529 #if defined(CONFIG_USER_ONLY) 5530 GEN_PRIV(ctx); 5531 #else 5532 TCGv dcrn; 5533 5534 CHK_SV(ctx); 5535 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5536 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5537 #endif /* defined(CONFIG_USER_ONLY) */ 5538 } 5539 5540 /* mfdcrx */ 5541 /* XXX: not implemented on 440 ? */ 5542 static void gen_mfdcrx(DisasContext *ctx) 5543 { 5544 #if defined(CONFIG_USER_ONLY) 5545 GEN_PRIV(ctx); 5546 #else 5547 CHK_SV(ctx); 5548 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5549 cpu_gpr[rA(ctx->opcode)]); 5550 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5551 #endif /* defined(CONFIG_USER_ONLY) */ 5552 } 5553 5554 /* mtdcrx */ 5555 /* XXX: not implemented on 440 ? */ 5556 static void gen_mtdcrx(DisasContext *ctx) 5557 { 5558 #if defined(CONFIG_USER_ONLY) 5559 GEN_PRIV(ctx); 5560 #else 5561 CHK_SV(ctx); 5562 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5563 cpu_gpr[rS(ctx->opcode)]); 5564 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5565 #endif /* defined(CONFIG_USER_ONLY) */ 5566 } 5567 5568 /* dccci */ 5569 static void gen_dccci(DisasContext *ctx) 5570 { 5571 CHK_SV(ctx); 5572 /* interpreted as no-op */ 5573 } 5574 5575 /* dcread */ 5576 static void gen_dcread(DisasContext *ctx) 5577 { 5578 #if defined(CONFIG_USER_ONLY) 5579 GEN_PRIV(ctx); 5580 #else 5581 TCGv EA, val; 5582 5583 CHK_SV(ctx); 5584 gen_set_access_type(ctx, ACCESS_CACHE); 5585 EA = tcg_temp_new(); 5586 gen_addr_reg_index(ctx, EA); 5587 val = tcg_temp_new(); 5588 gen_qemu_ld32u(ctx, val, EA); 5589 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5590 #endif /* defined(CONFIG_USER_ONLY) */ 5591 } 5592 5593 /* icbt */ 5594 static void gen_icbt_40x(DisasContext *ctx) 5595 { 5596 /* 5597 * interpreted as no-op 5598 * XXX: specification say this is treated as a load by the MMU but 5599 * does not generate any exception 5600 */ 5601 } 5602 5603 /* iccci */ 5604 static void gen_iccci(DisasContext *ctx) 5605 { 5606 CHK_SV(ctx); 5607 /* interpreted as no-op */ 5608 } 5609 5610 /* icread */ 5611 static void gen_icread(DisasContext *ctx) 5612 { 5613 CHK_SV(ctx); 5614 /* interpreted as no-op */ 5615 } 5616 5617 /* rfci (supervisor only) */ 5618 static void gen_rfci_40x(DisasContext *ctx) 5619 { 5620 #if defined(CONFIG_USER_ONLY) 5621 GEN_PRIV(ctx); 5622 #else 5623 CHK_SV(ctx); 5624 /* Restore CPU state */ 5625 gen_helper_40x_rfci(cpu_env); 5626 ctx->base.is_jmp = DISAS_EXIT; 5627 #endif /* defined(CONFIG_USER_ONLY) */ 5628 } 5629 5630 static void gen_rfci(DisasContext *ctx) 5631 { 5632 #if defined(CONFIG_USER_ONLY) 5633 GEN_PRIV(ctx); 5634 #else 5635 CHK_SV(ctx); 5636 /* Restore CPU state */ 5637 gen_helper_rfci(cpu_env); 5638 ctx->base.is_jmp = DISAS_EXIT; 5639 #endif /* defined(CONFIG_USER_ONLY) */ 5640 } 5641 5642 /* BookE specific */ 5643 5644 /* XXX: not implemented on 440 ? */ 5645 static void gen_rfdi(DisasContext *ctx) 5646 { 5647 #if defined(CONFIG_USER_ONLY) 5648 GEN_PRIV(ctx); 5649 #else 5650 CHK_SV(ctx); 5651 /* Restore CPU state */ 5652 gen_helper_rfdi(cpu_env); 5653 ctx->base.is_jmp = DISAS_EXIT; 5654 #endif /* defined(CONFIG_USER_ONLY) */ 5655 } 5656 5657 /* XXX: not implemented on 440 ? */ 5658 static void gen_rfmci(DisasContext *ctx) 5659 { 5660 #if defined(CONFIG_USER_ONLY) 5661 GEN_PRIV(ctx); 5662 #else 5663 CHK_SV(ctx); 5664 /* Restore CPU state */ 5665 gen_helper_rfmci(cpu_env); 5666 ctx->base.is_jmp = DISAS_EXIT; 5667 #endif /* defined(CONFIG_USER_ONLY) */ 5668 } 5669 5670 /* TLB management - PowerPC 405 implementation */ 5671 5672 /* tlbre */ 5673 static void gen_tlbre_40x(DisasContext *ctx) 5674 { 5675 #if defined(CONFIG_USER_ONLY) 5676 GEN_PRIV(ctx); 5677 #else 5678 CHK_SV(ctx); 5679 switch (rB(ctx->opcode)) { 5680 case 0: 5681 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5682 cpu_gpr[rA(ctx->opcode)]); 5683 break; 5684 case 1: 5685 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5686 cpu_gpr[rA(ctx->opcode)]); 5687 break; 5688 default: 5689 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5690 break; 5691 } 5692 #endif /* defined(CONFIG_USER_ONLY) */ 5693 } 5694 5695 /* tlbsx - tlbsx. */ 5696 static void gen_tlbsx_40x(DisasContext *ctx) 5697 { 5698 #if defined(CONFIG_USER_ONLY) 5699 GEN_PRIV(ctx); 5700 #else 5701 TCGv t0; 5702 5703 CHK_SV(ctx); 5704 t0 = tcg_temp_new(); 5705 gen_addr_reg_index(ctx, t0); 5706 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5707 if (Rc(ctx->opcode)) { 5708 TCGLabel *l1 = gen_new_label(); 5709 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5710 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5711 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5712 gen_set_label(l1); 5713 } 5714 #endif /* defined(CONFIG_USER_ONLY) */ 5715 } 5716 5717 /* tlbwe */ 5718 static void gen_tlbwe_40x(DisasContext *ctx) 5719 { 5720 #if defined(CONFIG_USER_ONLY) 5721 GEN_PRIV(ctx); 5722 #else 5723 CHK_SV(ctx); 5724 5725 switch (rB(ctx->opcode)) { 5726 case 0: 5727 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5728 cpu_gpr[rS(ctx->opcode)]); 5729 break; 5730 case 1: 5731 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5732 cpu_gpr[rS(ctx->opcode)]); 5733 break; 5734 default: 5735 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5736 break; 5737 } 5738 #endif /* defined(CONFIG_USER_ONLY) */ 5739 } 5740 5741 /* TLB management - PowerPC 440 implementation */ 5742 5743 /* tlbre */ 5744 static void gen_tlbre_440(DisasContext *ctx) 5745 { 5746 #if defined(CONFIG_USER_ONLY) 5747 GEN_PRIV(ctx); 5748 #else 5749 CHK_SV(ctx); 5750 5751 switch (rB(ctx->opcode)) { 5752 case 0: 5753 case 1: 5754 case 2: 5755 { 5756 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5757 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5758 t0, cpu_gpr[rA(ctx->opcode)]); 5759 } 5760 break; 5761 default: 5762 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5763 break; 5764 } 5765 #endif /* defined(CONFIG_USER_ONLY) */ 5766 } 5767 5768 /* tlbsx - tlbsx. */ 5769 static void gen_tlbsx_440(DisasContext *ctx) 5770 { 5771 #if defined(CONFIG_USER_ONLY) 5772 GEN_PRIV(ctx); 5773 #else 5774 TCGv t0; 5775 5776 CHK_SV(ctx); 5777 t0 = tcg_temp_new(); 5778 gen_addr_reg_index(ctx, t0); 5779 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5780 if (Rc(ctx->opcode)) { 5781 TCGLabel *l1 = gen_new_label(); 5782 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5783 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5784 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5785 gen_set_label(l1); 5786 } 5787 #endif /* defined(CONFIG_USER_ONLY) */ 5788 } 5789 5790 /* tlbwe */ 5791 static void gen_tlbwe_440(DisasContext *ctx) 5792 { 5793 #if defined(CONFIG_USER_ONLY) 5794 GEN_PRIV(ctx); 5795 #else 5796 CHK_SV(ctx); 5797 switch (rB(ctx->opcode)) { 5798 case 0: 5799 case 1: 5800 case 2: 5801 { 5802 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5803 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5804 cpu_gpr[rS(ctx->opcode)]); 5805 } 5806 break; 5807 default: 5808 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5809 break; 5810 } 5811 #endif /* defined(CONFIG_USER_ONLY) */ 5812 } 5813 5814 /* TLB management - PowerPC BookE 2.06 implementation */ 5815 5816 /* tlbre */ 5817 static void gen_tlbre_booke206(DisasContext *ctx) 5818 { 5819 #if defined(CONFIG_USER_ONLY) 5820 GEN_PRIV(ctx); 5821 #else 5822 CHK_SV(ctx); 5823 gen_helper_booke206_tlbre(cpu_env); 5824 #endif /* defined(CONFIG_USER_ONLY) */ 5825 } 5826 5827 /* tlbsx - tlbsx. */ 5828 static void gen_tlbsx_booke206(DisasContext *ctx) 5829 { 5830 #if defined(CONFIG_USER_ONLY) 5831 GEN_PRIV(ctx); 5832 #else 5833 TCGv t0; 5834 5835 CHK_SV(ctx); 5836 if (rA(ctx->opcode)) { 5837 t0 = tcg_temp_new(); 5838 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5839 } else { 5840 t0 = cpu_gpr[rB(ctx->opcode)]; 5841 } 5842 gen_helper_booke206_tlbsx(cpu_env, t0); 5843 #endif /* defined(CONFIG_USER_ONLY) */ 5844 } 5845 5846 /* tlbwe */ 5847 static void gen_tlbwe_booke206(DisasContext *ctx) 5848 { 5849 #if defined(CONFIG_USER_ONLY) 5850 GEN_PRIV(ctx); 5851 #else 5852 CHK_SV(ctx); 5853 gen_helper_booke206_tlbwe(cpu_env); 5854 #endif /* defined(CONFIG_USER_ONLY) */ 5855 } 5856 5857 static void gen_tlbivax_booke206(DisasContext *ctx) 5858 { 5859 #if defined(CONFIG_USER_ONLY) 5860 GEN_PRIV(ctx); 5861 #else 5862 TCGv t0; 5863 5864 CHK_SV(ctx); 5865 t0 = tcg_temp_new(); 5866 gen_addr_reg_index(ctx, t0); 5867 gen_helper_booke206_tlbivax(cpu_env, t0); 5868 #endif /* defined(CONFIG_USER_ONLY) */ 5869 } 5870 5871 static void gen_tlbilx_booke206(DisasContext *ctx) 5872 { 5873 #if defined(CONFIG_USER_ONLY) 5874 GEN_PRIV(ctx); 5875 #else 5876 TCGv t0; 5877 5878 CHK_SV(ctx); 5879 t0 = tcg_temp_new(); 5880 gen_addr_reg_index(ctx, t0); 5881 5882 switch ((ctx->opcode >> 21) & 0x3) { 5883 case 0: 5884 gen_helper_booke206_tlbilx0(cpu_env, t0); 5885 break; 5886 case 1: 5887 gen_helper_booke206_tlbilx1(cpu_env, t0); 5888 break; 5889 case 3: 5890 gen_helper_booke206_tlbilx3(cpu_env, t0); 5891 break; 5892 default: 5893 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5894 break; 5895 } 5896 #endif /* defined(CONFIG_USER_ONLY) */ 5897 } 5898 5899 /* wrtee */ 5900 static void gen_wrtee(DisasContext *ctx) 5901 { 5902 #if defined(CONFIG_USER_ONLY) 5903 GEN_PRIV(ctx); 5904 #else 5905 TCGv t0; 5906 5907 CHK_SV(ctx); 5908 t0 = tcg_temp_new(); 5909 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5910 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5911 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 5912 gen_ppc_maybe_interrupt(ctx); 5913 /* 5914 * Stop translation to have a chance to raise an exception if we 5915 * just set msr_ee to 1 5916 */ 5917 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5918 #endif /* defined(CONFIG_USER_ONLY) */ 5919 } 5920 5921 /* wrteei */ 5922 static void gen_wrteei(DisasContext *ctx) 5923 { 5924 #if defined(CONFIG_USER_ONLY) 5925 GEN_PRIV(ctx); 5926 #else 5927 CHK_SV(ctx); 5928 if (ctx->opcode & 0x00008000) { 5929 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 5930 gen_ppc_maybe_interrupt(ctx); 5931 /* Stop translation to have a chance to raise an exception */ 5932 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5933 } else { 5934 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5935 } 5936 #endif /* defined(CONFIG_USER_ONLY) */ 5937 } 5938 5939 /* PowerPC 440 specific instructions */ 5940 5941 /* dlmzb */ 5942 static void gen_dlmzb(DisasContext *ctx) 5943 { 5944 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 5945 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 5946 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 5947 } 5948 5949 /* mbar replaces eieio on 440 */ 5950 static void gen_mbar(DisasContext *ctx) 5951 { 5952 /* interpreted as no-op */ 5953 } 5954 5955 /* msync replaces sync on 440 */ 5956 static void gen_msync_4xx(DisasContext *ctx) 5957 { 5958 /* Only e500 seems to treat reserved bits as invalid */ 5959 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 5960 (ctx->opcode & 0x03FFF801)) { 5961 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5962 } 5963 /* otherwise interpreted as no-op */ 5964 } 5965 5966 /* icbt */ 5967 static void gen_icbt_440(DisasContext *ctx) 5968 { 5969 /* 5970 * interpreted as no-op 5971 * XXX: specification say this is treated as a load by the MMU but 5972 * does not generate any exception 5973 */ 5974 } 5975 5976 #if defined(TARGET_PPC64) 5977 static void gen_maddld(DisasContext *ctx) 5978 { 5979 TCGv_i64 t1 = tcg_temp_new_i64(); 5980 5981 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5982 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 5983 } 5984 5985 /* maddhd maddhdu */ 5986 static void gen_maddhd_maddhdu(DisasContext *ctx) 5987 { 5988 TCGv_i64 lo = tcg_temp_new_i64(); 5989 TCGv_i64 hi = tcg_temp_new_i64(); 5990 TCGv_i64 t1 = tcg_temp_new_i64(); 5991 5992 if (Rc(ctx->opcode)) { 5993 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 5994 cpu_gpr[rB(ctx->opcode)]); 5995 tcg_gen_movi_i64(t1, 0); 5996 } else { 5997 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 5998 cpu_gpr[rB(ctx->opcode)]); 5999 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6000 } 6001 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6002 cpu_gpr[rC(ctx->opcode)], t1); 6003 } 6004 #endif /* defined(TARGET_PPC64) */ 6005 6006 static void gen_tbegin(DisasContext *ctx) 6007 { 6008 if (unlikely(!ctx->tm_enabled)) { 6009 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6010 return; 6011 } 6012 gen_helper_tbegin(cpu_env); 6013 } 6014 6015 #define GEN_TM_NOOP(name) \ 6016 static inline void gen_##name(DisasContext *ctx) \ 6017 { \ 6018 if (unlikely(!ctx->tm_enabled)) { \ 6019 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6020 return; \ 6021 } \ 6022 /* \ 6023 * Because tbegin always fails in QEMU, these user \ 6024 * space instructions all have a simple implementation: \ 6025 * \ 6026 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6027 * = 0b0 || 0b00 || 0b0 \ 6028 */ \ 6029 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6030 } 6031 6032 GEN_TM_NOOP(tend); 6033 GEN_TM_NOOP(tabort); 6034 GEN_TM_NOOP(tabortwc); 6035 GEN_TM_NOOP(tabortwci); 6036 GEN_TM_NOOP(tabortdc); 6037 GEN_TM_NOOP(tabortdci); 6038 GEN_TM_NOOP(tsr); 6039 6040 static inline void gen_cp_abort(DisasContext *ctx) 6041 { 6042 /* Do Nothing */ 6043 } 6044 6045 #define GEN_CP_PASTE_NOOP(name) \ 6046 static inline void gen_##name(DisasContext *ctx) \ 6047 { \ 6048 /* \ 6049 * Generate invalid exception until we have an \ 6050 * implementation of the copy paste facility \ 6051 */ \ 6052 gen_invalid(ctx); \ 6053 } 6054 6055 GEN_CP_PASTE_NOOP(copy) 6056 GEN_CP_PASTE_NOOP(paste) 6057 6058 static void gen_tcheck(DisasContext *ctx) 6059 { 6060 if (unlikely(!ctx->tm_enabled)) { 6061 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6062 return; 6063 } 6064 /* 6065 * Because tbegin always fails, the tcheck implementation is 6066 * simple: 6067 * 6068 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6069 * = 0b1 || 0b00 || 0b0 6070 */ 6071 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6072 } 6073 6074 #if defined(CONFIG_USER_ONLY) 6075 #define GEN_TM_PRIV_NOOP(name) \ 6076 static inline void gen_##name(DisasContext *ctx) \ 6077 { \ 6078 gen_priv_opc(ctx); \ 6079 } 6080 6081 #else 6082 6083 #define GEN_TM_PRIV_NOOP(name) \ 6084 static inline void gen_##name(DisasContext *ctx) \ 6085 { \ 6086 CHK_SV(ctx); \ 6087 if (unlikely(!ctx->tm_enabled)) { \ 6088 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6089 return; \ 6090 } \ 6091 /* \ 6092 * Because tbegin always fails, the implementation is \ 6093 * simple: \ 6094 * \ 6095 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6096 * = 0b0 || 0b00 | 0b0 \ 6097 */ \ 6098 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6099 } 6100 6101 #endif 6102 6103 GEN_TM_PRIV_NOOP(treclaim); 6104 GEN_TM_PRIV_NOOP(trechkpt); 6105 6106 static inline void get_fpr(TCGv_i64 dst, int regno) 6107 { 6108 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 6109 } 6110 6111 static inline void set_fpr(int regno, TCGv_i64 src) 6112 { 6113 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 6114 /* 6115 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 6116 * corresponding to the target FPR was undefined. However, 6117 * most (if not all) real hardware were setting the result to 0. 6118 * Starting at ISA v3.1, the result for doubleword 1 is now defined 6119 * to be 0. 6120 */ 6121 tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 6122 } 6123 6124 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6125 { 6126 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6127 } 6128 6129 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6130 { 6131 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6132 } 6133 6134 /* 6135 * Helpers for decodetree used by !function for decoding arguments. 6136 */ 6137 static int times_2(DisasContext *ctx, int x) 6138 { 6139 return x * 2; 6140 } 6141 6142 static int times_4(DisasContext *ctx, int x) 6143 { 6144 return x * 4; 6145 } 6146 6147 static int times_16(DisasContext *ctx, int x) 6148 { 6149 return x * 16; 6150 } 6151 6152 static int64_t dw_compose_ea(DisasContext *ctx, int x) 6153 { 6154 return deposit64(0xfffffffffffffe00, 3, 6, x); 6155 } 6156 6157 /* 6158 * Helpers for trans_* functions to check for specific insns flags. 6159 * Use token pasting to ensure that we use the proper flag with the 6160 * proper variable. 6161 */ 6162 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6163 do { \ 6164 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6165 return false; \ 6166 } \ 6167 } while (0) 6168 6169 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6170 do { \ 6171 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6172 return false; \ 6173 } \ 6174 } while (0) 6175 6176 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6177 #if TARGET_LONG_BITS == 32 6178 # define REQUIRE_64BIT(CTX) return false 6179 #else 6180 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6181 #endif 6182 6183 #define REQUIRE_VECTOR(CTX) \ 6184 do { \ 6185 if (unlikely(!(CTX)->altivec_enabled)) { \ 6186 gen_exception((CTX), POWERPC_EXCP_VPU); \ 6187 return true; \ 6188 } \ 6189 } while (0) 6190 6191 #define REQUIRE_VSX(CTX) \ 6192 do { \ 6193 if (unlikely(!(CTX)->vsx_enabled)) { \ 6194 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 6195 return true; \ 6196 } \ 6197 } while (0) 6198 6199 #define REQUIRE_FPU(ctx) \ 6200 do { \ 6201 if (unlikely(!(ctx)->fpu_enabled)) { \ 6202 gen_exception((ctx), POWERPC_EXCP_FPU); \ 6203 return true; \ 6204 } \ 6205 } while (0) 6206 6207 #if !defined(CONFIG_USER_ONLY) 6208 #define REQUIRE_SV(CTX) \ 6209 do { \ 6210 if (unlikely((CTX)->pr)) { \ 6211 gen_priv_opc(CTX); \ 6212 return true; \ 6213 } \ 6214 } while (0) 6215 6216 #define REQUIRE_HV(CTX) \ 6217 do { \ 6218 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6219 gen_priv_opc(CTX); \ 6220 return true; \ 6221 } \ 6222 } while (0) 6223 #else 6224 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6225 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6226 #endif 6227 6228 /* 6229 * Helpers for implementing sets of trans_* functions. 6230 * Defer the implementation of NAME to FUNC, with optional extra arguments. 6231 */ 6232 #define TRANS(NAME, FUNC, ...) \ 6233 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6234 { return FUNC(ctx, a, __VA_ARGS__); } 6235 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 6236 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6237 { \ 6238 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 6239 return FUNC(ctx, a, __VA_ARGS__); \ 6240 } 6241 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6242 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6243 { \ 6244 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6245 return FUNC(ctx, a, __VA_ARGS__); \ 6246 } 6247 6248 #define TRANS64(NAME, FUNC, ...) \ 6249 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6250 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 6251 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6252 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6253 { \ 6254 REQUIRE_64BIT(ctx); \ 6255 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6256 return FUNC(ctx, a, __VA_ARGS__); \ 6257 } 6258 6259 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6260 6261 6262 #include "decode-insn32.c.inc" 6263 #include "decode-insn64.c.inc" 6264 #include "power8-pmu-regs.c.inc" 6265 6266 /* 6267 * Incorporate CIA into the constant when R=1. 6268 * Validate that when R=1, RA=0. 6269 */ 6270 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6271 { 6272 d->rt = a->rt; 6273 d->ra = a->ra; 6274 d->si = a->si; 6275 if (a->r) { 6276 if (unlikely(a->ra != 0)) { 6277 gen_invalid(ctx); 6278 return false; 6279 } 6280 d->si += ctx->cia; 6281 } 6282 return true; 6283 } 6284 6285 #include "translate/fixedpoint-impl.c.inc" 6286 6287 #include "translate/fp-impl.c.inc" 6288 6289 #include "translate/vmx-impl.c.inc" 6290 6291 #include "translate/vsx-impl.c.inc" 6292 6293 #include "translate/dfp-impl.c.inc" 6294 6295 #include "translate/spe-impl.c.inc" 6296 6297 #include "translate/branch-impl.c.inc" 6298 6299 #include "translate/processor-ctrl-impl.c.inc" 6300 6301 #include "translate/storage-ctrl-impl.c.inc" 6302 6303 /* Handles lfdp */ 6304 static void gen_dform39(DisasContext *ctx) 6305 { 6306 if ((ctx->opcode & 0x3) == 0) { 6307 if (ctx->insns_flags2 & PPC2_ISA205) { 6308 return gen_lfdp(ctx); 6309 } 6310 } 6311 return gen_invalid(ctx); 6312 } 6313 6314 /* Handles stfdp */ 6315 static void gen_dform3D(DisasContext *ctx) 6316 { 6317 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 6318 /* stfdp */ 6319 if (ctx->insns_flags2 & PPC2_ISA205) { 6320 return gen_stfdp(ctx); 6321 } 6322 } 6323 return gen_invalid(ctx); 6324 } 6325 6326 #if defined(TARGET_PPC64) 6327 /* brd */ 6328 static void gen_brd(DisasContext *ctx) 6329 { 6330 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6331 } 6332 6333 /* brw */ 6334 static void gen_brw(DisasContext *ctx) 6335 { 6336 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6337 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 6338 6339 } 6340 6341 /* brh */ 6342 static void gen_brh(DisasContext *ctx) 6343 { 6344 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 6345 TCGv_i64 t1 = tcg_temp_new_i64(); 6346 TCGv_i64 t2 = tcg_temp_new_i64(); 6347 6348 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6349 tcg_gen_and_i64(t2, t1, mask); 6350 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 6351 tcg_gen_shli_i64(t1, t1, 8); 6352 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 6353 } 6354 #endif 6355 6356 static opcode_t opcodes[] = { 6357 #if defined(TARGET_PPC64) 6358 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 6359 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 6360 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 6361 #endif 6362 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6363 #if defined(TARGET_PPC64) 6364 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6365 #endif 6366 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6367 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6368 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6369 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6370 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6371 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6372 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6373 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6374 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6375 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6376 #if defined(TARGET_PPC64) 6377 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6378 #endif 6379 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6380 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6381 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6382 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6383 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6384 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6385 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6386 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6387 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6388 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6389 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6390 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6391 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6392 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6393 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6394 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6395 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6396 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6397 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6398 #if defined(TARGET_PPC64) 6399 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6400 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6401 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6402 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6403 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6404 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6405 #endif 6406 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6407 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6408 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6409 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6410 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6411 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6412 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6413 #if defined(TARGET_PPC64) 6414 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6415 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6416 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6417 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6418 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6419 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6420 PPC_NONE, PPC2_ISA300), 6421 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6422 PPC_NONE, PPC2_ISA300), 6423 #endif 6424 /* handles lfdp, lxsd, lxssp */ 6425 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6426 /* handles stfdp, stxsd, stxssp */ 6427 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6428 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6429 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6430 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6431 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6432 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6433 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6434 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6435 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6436 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6437 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6438 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6439 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6440 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6441 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6442 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6443 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6444 #if defined(TARGET_PPC64) 6445 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6446 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6447 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6448 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6449 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6450 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6451 #endif 6452 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6453 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 6454 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 6455 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6456 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6457 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6458 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6459 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6460 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6461 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6462 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6463 #if defined(TARGET_PPC64) 6464 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6465 #if !defined(CONFIG_USER_ONLY) 6466 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6467 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6468 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6469 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 6470 #endif 6471 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6472 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6473 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6474 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6475 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6476 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6477 #endif 6478 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6479 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 6480 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6481 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6482 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6483 #if defined(TARGET_PPC64) 6484 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6485 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6486 #endif 6487 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6488 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6489 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6490 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6491 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6492 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6493 #if defined(TARGET_PPC64) 6494 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6495 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6496 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6497 #endif 6498 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6499 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6500 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6501 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6502 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6503 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6504 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6505 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6506 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6507 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6508 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6509 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6510 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6511 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6512 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6513 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6514 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6515 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6516 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6517 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6518 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6519 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6520 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6521 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6522 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6523 #if defined(TARGET_PPC64) 6524 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6525 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6526 PPC_SEGMENT_64B), 6527 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6528 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6529 PPC_SEGMENT_64B), 6530 #endif 6531 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6532 /* 6533 * XXX Those instructions will need to be handled differently for 6534 * different ISA versions 6535 */ 6536 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6537 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6538 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6539 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6540 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6541 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6542 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6543 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6544 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6545 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6546 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6547 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6548 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6549 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6550 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6551 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6552 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6553 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6554 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6555 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6556 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6557 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6558 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6559 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6560 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6561 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6562 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6563 PPC_NONE, PPC2_BOOKE206), 6564 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6565 PPC_NONE, PPC2_BOOKE206), 6566 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6567 PPC_NONE, PPC2_BOOKE206), 6568 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6569 PPC_NONE, PPC2_BOOKE206), 6570 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6571 PPC_NONE, PPC2_BOOKE206), 6572 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6573 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6574 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6575 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6576 PPC_BOOKE, PPC2_BOOKE206), 6577 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6578 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6579 PPC_BOOKE, PPC2_BOOKE206), 6580 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 6581 PPC_440_SPEC), 6582 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6583 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6584 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6585 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6586 #if defined(TARGET_PPC64) 6587 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6588 PPC2_ISA300), 6589 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6590 #endif 6591 6592 #undef GEN_INT_ARITH_ADD 6593 #undef GEN_INT_ARITH_ADD_CONST 6594 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6595 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6596 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6597 add_ca, compute_ca, compute_ov) \ 6598 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6599 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6600 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6601 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6602 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6603 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6604 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6605 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6606 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6607 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6608 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6609 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6610 6611 #undef GEN_INT_ARITH_DIVW 6612 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6613 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6614 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6615 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6616 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6617 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6618 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6619 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6620 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6621 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6622 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6623 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6624 6625 #if defined(TARGET_PPC64) 6626 #undef GEN_INT_ARITH_DIVD 6627 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6628 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6629 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6630 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6631 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6632 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6633 6634 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6635 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6636 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6637 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6638 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6639 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6640 6641 #undef GEN_INT_ARITH_MUL_HELPER 6642 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6643 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6644 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6645 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6646 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6647 #endif 6648 6649 #undef GEN_INT_ARITH_SUBF 6650 #undef GEN_INT_ARITH_SUBF_CONST 6651 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6652 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6653 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6654 add_ca, compute_ca, compute_ov) \ 6655 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6656 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6657 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6658 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6659 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6660 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6661 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6662 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6663 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6664 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6665 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6666 6667 #undef GEN_LOGICAL1 6668 #undef GEN_LOGICAL2 6669 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6670 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6671 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6672 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6673 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6674 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6675 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6676 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6677 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6678 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6679 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6680 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6681 #if defined(TARGET_PPC64) 6682 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6683 #endif 6684 6685 #if defined(TARGET_PPC64) 6686 #undef GEN_PPC64_R2 6687 #undef GEN_PPC64_R4 6688 #define GEN_PPC64_R2(name, opc1, opc2) \ 6689 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6690 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6691 PPC_64B) 6692 #define GEN_PPC64_R4(name, opc1, opc2) \ 6693 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6694 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6695 PPC_64B), \ 6696 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6697 PPC_64B), \ 6698 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6699 PPC_64B) 6700 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6701 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6702 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6703 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6704 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6705 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6706 #endif 6707 6708 #undef GEN_LDX_E 6709 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6710 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6711 6712 #if defined(TARGET_PPC64) 6713 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6714 6715 /* HV/P7 and later only */ 6716 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6717 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6718 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6719 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6720 #endif 6721 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6722 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6723 6724 /* External PID based load */ 6725 #undef GEN_LDEPX 6726 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6727 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6728 0x00000001, PPC_NONE, PPC2_BOOKE206), 6729 6730 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6731 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6732 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6733 #if defined(TARGET_PPC64) 6734 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6735 #endif 6736 6737 #undef GEN_STX_E 6738 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6739 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6740 6741 #if defined(TARGET_PPC64) 6742 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6743 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6744 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6745 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6746 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6747 #endif 6748 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6749 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6750 6751 #undef GEN_STEPX 6752 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6753 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6754 0x00000001, PPC_NONE, PPC2_BOOKE206), 6755 6756 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6757 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6758 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6759 #if defined(TARGET_PPC64) 6760 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6761 #endif 6762 6763 #undef GEN_CRLOGIC 6764 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6765 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6766 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6767 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6768 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6769 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6770 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6771 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6772 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6773 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6774 6775 #undef GEN_MAC_HANDLER 6776 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6777 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6778 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6779 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6780 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6781 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6782 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6783 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6784 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6785 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6786 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6787 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6788 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6789 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6790 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6791 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6792 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6793 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6794 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6795 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6796 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6797 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6798 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6799 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6800 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6801 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6802 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6803 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6804 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6805 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6806 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6807 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6808 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6809 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6810 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6811 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6812 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6813 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6814 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6815 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6816 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6817 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6818 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6819 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6820 6821 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6822 PPC_NONE, PPC2_TM), 6823 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6824 PPC_NONE, PPC2_TM), 6825 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6826 PPC_NONE, PPC2_TM), 6827 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6828 PPC_NONE, PPC2_TM), 6829 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6830 PPC_NONE, PPC2_TM), 6831 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6832 PPC_NONE, PPC2_TM), 6833 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6834 PPC_NONE, PPC2_TM), 6835 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6836 PPC_NONE, PPC2_TM), 6837 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6838 PPC_NONE, PPC2_TM), 6839 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6840 PPC_NONE, PPC2_TM), 6841 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6842 PPC_NONE, PPC2_TM), 6843 6844 #include "translate/fp-ops.c.inc" 6845 6846 #include "translate/vmx-ops.c.inc" 6847 6848 #include "translate/vsx-ops.c.inc" 6849 6850 #include "translate/spe-ops.c.inc" 6851 }; 6852 6853 /*****************************************************************************/ 6854 /* Opcode types */ 6855 enum { 6856 PPC_DIRECT = 0, /* Opcode routine */ 6857 PPC_INDIRECT = 1, /* Indirect opcode table */ 6858 }; 6859 6860 #define PPC_OPCODE_MASK 0x3 6861 6862 static inline int is_indirect_opcode(void *handler) 6863 { 6864 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6865 } 6866 6867 static inline opc_handler_t **ind_table(void *handler) 6868 { 6869 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6870 } 6871 6872 /* Instruction table creation */ 6873 /* Opcodes tables creation */ 6874 static void fill_new_table(opc_handler_t **table, int len) 6875 { 6876 int i; 6877 6878 for (i = 0; i < len; i++) { 6879 table[i] = &invalid_handler; 6880 } 6881 } 6882 6883 static int create_new_table(opc_handler_t **table, unsigned char idx) 6884 { 6885 opc_handler_t **tmp; 6886 6887 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6888 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6889 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6890 6891 return 0; 6892 } 6893 6894 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6895 opc_handler_t *handler) 6896 { 6897 if (table[idx] != &invalid_handler) { 6898 return -1; 6899 } 6900 table[idx] = handler; 6901 6902 return 0; 6903 } 6904 6905 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6906 unsigned char idx, opc_handler_t *handler) 6907 { 6908 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 6909 printf("*** ERROR: opcode %02x already assigned in main " 6910 "opcode table\n", idx); 6911 return -1; 6912 } 6913 6914 return 0; 6915 } 6916 6917 static int register_ind_in_table(opc_handler_t **table, 6918 unsigned char idx1, unsigned char idx2, 6919 opc_handler_t *handler) 6920 { 6921 if (table[idx1] == &invalid_handler) { 6922 if (create_new_table(table, idx1) < 0) { 6923 printf("*** ERROR: unable to create indirect table " 6924 "idx=%02x\n", idx1); 6925 return -1; 6926 } 6927 } else { 6928 if (!is_indirect_opcode(table[idx1])) { 6929 printf("*** ERROR: idx %02x already assigned to a direct " 6930 "opcode\n", idx1); 6931 return -1; 6932 } 6933 } 6934 if (handler != NULL && 6935 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 6936 printf("*** ERROR: opcode %02x already assigned in " 6937 "opcode table %02x\n", idx2, idx1); 6938 return -1; 6939 } 6940 6941 return 0; 6942 } 6943 6944 static int register_ind_insn(opc_handler_t **ppc_opcodes, 6945 unsigned char idx1, unsigned char idx2, 6946 opc_handler_t *handler) 6947 { 6948 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 6949 } 6950 6951 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 6952 unsigned char idx1, unsigned char idx2, 6953 unsigned char idx3, opc_handler_t *handler) 6954 { 6955 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6956 printf("*** ERROR: unable to join indirect table idx " 6957 "[%02x-%02x]\n", idx1, idx2); 6958 return -1; 6959 } 6960 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 6961 handler) < 0) { 6962 printf("*** ERROR: unable to insert opcode " 6963 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6964 return -1; 6965 } 6966 6967 return 0; 6968 } 6969 6970 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 6971 unsigned char idx1, unsigned char idx2, 6972 unsigned char idx3, unsigned char idx4, 6973 opc_handler_t *handler) 6974 { 6975 opc_handler_t **table; 6976 6977 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6978 printf("*** ERROR: unable to join indirect table idx " 6979 "[%02x-%02x]\n", idx1, idx2); 6980 return -1; 6981 } 6982 table = ind_table(ppc_opcodes[idx1]); 6983 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 6984 printf("*** ERROR: unable to join 2nd-level indirect table idx " 6985 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6986 return -1; 6987 } 6988 table = ind_table(table[idx2]); 6989 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 6990 printf("*** ERROR: unable to insert opcode " 6991 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 6992 return -1; 6993 } 6994 return 0; 6995 } 6996 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 6997 { 6998 if (insn->opc2 != 0xFF) { 6999 if (insn->opc3 != 0xFF) { 7000 if (insn->opc4 != 0xFF) { 7001 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7002 insn->opc3, insn->opc4, 7003 &insn->handler) < 0) { 7004 return -1; 7005 } 7006 } else { 7007 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7008 insn->opc3, &insn->handler) < 0) { 7009 return -1; 7010 } 7011 } 7012 } else { 7013 if (register_ind_insn(ppc_opcodes, insn->opc1, 7014 insn->opc2, &insn->handler) < 0) { 7015 return -1; 7016 } 7017 } 7018 } else { 7019 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 7020 return -1; 7021 } 7022 } 7023 7024 return 0; 7025 } 7026 7027 static int test_opcode_table(opc_handler_t **table, int len) 7028 { 7029 int i, count, tmp; 7030 7031 for (i = 0, count = 0; i < len; i++) { 7032 /* Consistency fixup */ 7033 if (table[i] == NULL) { 7034 table[i] = &invalid_handler; 7035 } 7036 if (table[i] != &invalid_handler) { 7037 if (is_indirect_opcode(table[i])) { 7038 tmp = test_opcode_table(ind_table(table[i]), 7039 PPC_CPU_INDIRECT_OPCODES_LEN); 7040 if (tmp == 0) { 7041 free(table[i]); 7042 table[i] = &invalid_handler; 7043 } else { 7044 count++; 7045 } 7046 } else { 7047 count++; 7048 } 7049 } 7050 } 7051 7052 return count; 7053 } 7054 7055 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 7056 { 7057 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 7058 printf("*** WARNING: no opcode defined !\n"); 7059 } 7060 } 7061 7062 /*****************************************************************************/ 7063 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 7064 { 7065 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7066 opcode_t *opc; 7067 7068 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 7069 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 7070 if (((opc->handler.type & pcc->insns_flags) != 0) || 7071 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 7072 if (register_insn(cpu->opcodes, opc) < 0) { 7073 error_setg(errp, "ERROR initializing PowerPC instruction " 7074 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 7075 opc->opc3); 7076 return; 7077 } 7078 } 7079 } 7080 fix_opcode_tables(cpu->opcodes); 7081 fflush(stdout); 7082 fflush(stderr); 7083 } 7084 7085 void destroy_ppc_opcodes(PowerPCCPU *cpu) 7086 { 7087 opc_handler_t **table, **table_2; 7088 int i, j, k; 7089 7090 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 7091 if (cpu->opcodes[i] == &invalid_handler) { 7092 continue; 7093 } 7094 if (is_indirect_opcode(cpu->opcodes[i])) { 7095 table = ind_table(cpu->opcodes[i]); 7096 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 7097 if (table[j] == &invalid_handler) { 7098 continue; 7099 } 7100 if (is_indirect_opcode(table[j])) { 7101 table_2 = ind_table(table[j]); 7102 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 7103 if (table_2[k] != &invalid_handler && 7104 is_indirect_opcode(table_2[k])) { 7105 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 7106 ~PPC_INDIRECT)); 7107 } 7108 } 7109 g_free((opc_handler_t *)((uintptr_t)table[j] & 7110 ~PPC_INDIRECT)); 7111 } 7112 } 7113 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 7114 ~PPC_INDIRECT)); 7115 } 7116 } 7117 } 7118 7119 int ppc_fixup_cpu(PowerPCCPU *cpu) 7120 { 7121 CPUPPCState *env = &cpu->env; 7122 7123 /* 7124 * TCG doesn't (yet) emulate some groups of instructions that are 7125 * implemented on some otherwise supported CPUs (e.g. VSX and 7126 * decimal floating point instructions on POWER7). We remove 7127 * unsupported instruction groups from the cpu state's instruction 7128 * masks and hope the guest can cope. For at least the pseries 7129 * machine, the unavailability of these instructions can be 7130 * advertised to the guest via the device tree. 7131 */ 7132 if ((env->insns_flags & ~PPC_TCG_INSNS) 7133 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 7134 warn_report("Disabling some instructions which are not " 7135 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 7136 env->insns_flags & ~PPC_TCG_INSNS, 7137 env->insns_flags2 & ~PPC_TCG_INSNS2); 7138 } 7139 env->insns_flags &= PPC_TCG_INSNS; 7140 env->insns_flags2 &= PPC_TCG_INSNS2; 7141 return 0; 7142 } 7143 7144 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7145 { 7146 opc_handler_t **table, *handler; 7147 uint32_t inval; 7148 7149 ctx->opcode = insn; 7150 7151 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7152 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7153 ctx->le_mode ? "little" : "big"); 7154 7155 table = cpu->opcodes; 7156 handler = table[opc1(insn)]; 7157 if (is_indirect_opcode(handler)) { 7158 table = ind_table(handler); 7159 handler = table[opc2(insn)]; 7160 if (is_indirect_opcode(handler)) { 7161 table = ind_table(handler); 7162 handler = table[opc3(insn)]; 7163 if (is_indirect_opcode(handler)) { 7164 table = ind_table(handler); 7165 handler = table[opc4(insn)]; 7166 } 7167 } 7168 } 7169 7170 /* Is opcode *REALLY* valid ? */ 7171 if (unlikely(handler->handler == &gen_invalid)) { 7172 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7173 "%02x - %02x - %02x - %02x (%08x) " 7174 TARGET_FMT_lx "\n", 7175 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7176 insn, ctx->cia); 7177 return false; 7178 } 7179 7180 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7181 && Rc(insn))) { 7182 inval = handler->inval2; 7183 } else { 7184 inval = handler->inval1; 7185 } 7186 7187 if (unlikely((insn & inval) != 0)) { 7188 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7189 "%02x - %02x - %02x - %02x (%08x) " 7190 TARGET_FMT_lx "\n", insn & inval, 7191 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7192 insn, ctx->cia); 7193 return false; 7194 } 7195 7196 handler->handler(ctx); 7197 return true; 7198 } 7199 7200 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7201 { 7202 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7203 CPUPPCState *env = cs->env_ptr; 7204 uint32_t hflags = ctx->base.tb->flags; 7205 7206 ctx->spr_cb = env->spr_cb; 7207 ctx->pr = (hflags >> HFLAGS_PR) & 1; 7208 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 7209 ctx->dr = (hflags >> HFLAGS_DR) & 1; 7210 ctx->hv = (hflags >> HFLAGS_HV) & 1; 7211 ctx->insns_flags = env->insns_flags; 7212 ctx->insns_flags2 = env->insns_flags2; 7213 ctx->access_type = -1; 7214 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 7215 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7216 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7217 ctx->flags = env->flags; 7218 #if defined(TARGET_PPC64) 7219 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7220 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7221 #endif 7222 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7223 || env->mmu_model & POWERPC_MMU_64; 7224 7225 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 7226 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 7227 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 7228 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 7229 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7230 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 7231 ctx->hr = (hflags >> HFLAGS_HR) & 1; 7232 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7233 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 7234 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 7235 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 7236 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 7237 7238 ctx->singlestep_enabled = 0; 7239 if ((hflags >> HFLAGS_SE) & 1) { 7240 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7241 ctx->base.max_insns = 1; 7242 } 7243 if ((hflags >> HFLAGS_BE) & 1) { 7244 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7245 } 7246 } 7247 7248 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7249 { 7250 } 7251 7252 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7253 { 7254 tcg_gen_insn_start(dcbase->pc_next); 7255 } 7256 7257 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 7258 { 7259 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 7260 return opc1(insn) == 1; 7261 } 7262 7263 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7264 { 7265 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7266 PowerPCCPU *cpu = POWERPC_CPU(cs); 7267 CPUPPCState *env = cs->env_ptr; 7268 target_ulong pc; 7269 uint32_t insn; 7270 bool ok; 7271 7272 LOG_DISAS("----------------\n"); 7273 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7274 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7275 7276 ctx->cia = pc = ctx->base.pc_next; 7277 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 7278 ctx->base.pc_next = pc += 4; 7279 7280 if (!is_prefix_insn(ctx, insn)) { 7281 ok = (decode_insn32(ctx, insn) || 7282 decode_legacy(cpu, ctx, insn)); 7283 } else if ((pc & 63) == 0) { 7284 /* 7285 * Power v3.1, section 1.9 Exceptions: 7286 * attempt to execute a prefixed instruction that crosses a 7287 * 64-byte address boundary (system alignment error). 7288 */ 7289 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 7290 ok = true; 7291 } else { 7292 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 7293 need_byteswap(ctx)); 7294 ctx->base.pc_next = pc += 4; 7295 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 7296 } 7297 if (!ok) { 7298 gen_invalid(ctx); 7299 } 7300 7301 /* End the TB when crossing a page boundary. */ 7302 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 7303 ctx->base.is_jmp = DISAS_TOO_MANY; 7304 } 7305 } 7306 7307 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7308 { 7309 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7310 DisasJumpType is_jmp = ctx->base.is_jmp; 7311 target_ulong nip = ctx->base.pc_next; 7312 7313 if (is_jmp == DISAS_NORETURN) { 7314 /* We have already exited the TB. */ 7315 return; 7316 } 7317 7318 /* Honor single stepping. */ 7319 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 7320 && (nip <= 0x100 || nip > 0xf00)) { 7321 switch (is_jmp) { 7322 case DISAS_TOO_MANY: 7323 case DISAS_EXIT_UPDATE: 7324 case DISAS_CHAIN_UPDATE: 7325 gen_update_nip(ctx, nip); 7326 break; 7327 case DISAS_EXIT: 7328 case DISAS_CHAIN: 7329 break; 7330 default: 7331 g_assert_not_reached(); 7332 } 7333 7334 gen_debug_exception(ctx); 7335 return; 7336 } 7337 7338 switch (is_jmp) { 7339 case DISAS_TOO_MANY: 7340 if (use_goto_tb(ctx, nip)) { 7341 pmu_count_insns(ctx); 7342 tcg_gen_goto_tb(0); 7343 gen_update_nip(ctx, nip); 7344 tcg_gen_exit_tb(ctx->base.tb, 0); 7345 break; 7346 } 7347 /* fall through */ 7348 case DISAS_CHAIN_UPDATE: 7349 gen_update_nip(ctx, nip); 7350 /* fall through */ 7351 case DISAS_CHAIN: 7352 /* 7353 * tcg_gen_lookup_and_goto_ptr will exit the TB if 7354 * CF_NO_GOTO_PTR is set. Count insns now. 7355 */ 7356 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 7357 pmu_count_insns(ctx); 7358 } 7359 7360 tcg_gen_lookup_and_goto_ptr(); 7361 break; 7362 7363 case DISAS_EXIT_UPDATE: 7364 gen_update_nip(ctx, nip); 7365 /* fall through */ 7366 case DISAS_EXIT: 7367 pmu_count_insns(ctx); 7368 tcg_gen_exit_tb(NULL, 0); 7369 break; 7370 7371 default: 7372 g_assert_not_reached(); 7373 } 7374 } 7375 7376 static void ppc_tr_disas_log(const DisasContextBase *dcbase, 7377 CPUState *cs, FILE *logfile) 7378 { 7379 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 7380 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7381 } 7382 7383 static const TranslatorOps ppc_tr_ops = { 7384 .init_disas_context = ppc_tr_init_disas_context, 7385 .tb_start = ppc_tr_tb_start, 7386 .insn_start = ppc_tr_insn_start, 7387 .translate_insn = ppc_tr_translate_insn, 7388 .tb_stop = ppc_tr_tb_stop, 7389 .disas_log = ppc_tr_disas_log, 7390 }; 7391 7392 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7393 target_ulong pc, void *host_pc) 7394 { 7395 DisasContext ctx; 7396 7397 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7398 } 7399