1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "exec/exec-all.h" 25 #include "exec/target_page.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 30 #include "exec/helper-proto.h" 31 #include "exec/helper-gen.h" 32 33 #include "exec/translator.h" 34 #include "exec/translation-block.h" 35 #include "exec/log.h" 36 #include "qemu/atomic128.h" 37 #include "spr_common.h" 38 #include "power8-pmu.h" 39 40 #include "qemu/qemu-print.h" 41 #include "qapi/error.h" 42 43 #define HELPER_H "helper.h" 44 #include "exec/helper-info.c.inc" 45 #undef HELPER_H 46 47 #define CPU_SINGLE_STEP 0x1 48 #define CPU_BRANCH_STEP 0x2 49 50 /* Include definitions for instructions classes and implementations flags */ 51 /* #define PPC_DEBUG_DISAS */ 52 53 #ifdef PPC_DEBUG_DISAS 54 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 55 #else 56 # define LOG_DISAS(...) do { } while (0) 57 #endif 58 /*****************************************************************************/ 59 /* Code translation helpers */ 60 61 /* global register indexes */ 62 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 63 + 10 * 4 + 22 * 5 /* SPE GPRh */ 64 + 8 * 5 /* CRF */]; 65 static TCGv cpu_gpr[32]; 66 static TCGv cpu_gprh[32]; 67 static TCGv_i32 cpu_crf[8]; 68 static TCGv cpu_nip; 69 static TCGv cpu_msr; 70 static TCGv cpu_ctr; 71 static TCGv cpu_lr; 72 #if defined(TARGET_PPC64) 73 static TCGv cpu_cfar; 74 #endif 75 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 76 static TCGv cpu_reserve; 77 static TCGv cpu_reserve_length; 78 static TCGv cpu_reserve_val; 79 #if defined(TARGET_PPC64) 80 static TCGv cpu_reserve_val2; 81 #endif 82 static TCGv cpu_fpscr; 83 static TCGv_i32 cpu_access_type; 84 85 void ppc_translate_init(void) 86 { 87 int i; 88 char *p; 89 size_t cpu_reg_names_size; 90 91 p = cpu_reg_names; 92 cpu_reg_names_size = sizeof(cpu_reg_names); 93 94 for (i = 0; i < 8; i++) { 95 snprintf(p, cpu_reg_names_size, "crf%d", i); 96 cpu_crf[i] = tcg_global_mem_new_i32(tcg_env, 97 offsetof(CPUPPCState, crf[i]), p); 98 p += 5; 99 cpu_reg_names_size -= 5; 100 } 101 102 for (i = 0; i < 32; i++) { 103 snprintf(p, cpu_reg_names_size, "r%d", i); 104 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 105 offsetof(CPUPPCState, gpr[i]), p); 106 p += (i < 10) ? 3 : 4; 107 cpu_reg_names_size -= (i < 10) ? 3 : 4; 108 snprintf(p, cpu_reg_names_size, "r%dH", i); 109 cpu_gprh[i] = tcg_global_mem_new(tcg_env, 110 offsetof(CPUPPCState, gprh[i]), p); 111 p += (i < 10) ? 4 : 5; 112 cpu_reg_names_size -= (i < 10) ? 4 : 5; 113 } 114 115 cpu_nip = tcg_global_mem_new(tcg_env, 116 offsetof(CPUPPCState, nip), "nip"); 117 118 cpu_msr = tcg_global_mem_new(tcg_env, 119 offsetof(CPUPPCState, msr), "msr"); 120 121 cpu_ctr = tcg_global_mem_new(tcg_env, 122 offsetof(CPUPPCState, ctr), "ctr"); 123 124 cpu_lr = tcg_global_mem_new(tcg_env, 125 offsetof(CPUPPCState, lr), "lr"); 126 127 #if defined(TARGET_PPC64) 128 cpu_cfar = tcg_global_mem_new(tcg_env, 129 offsetof(CPUPPCState, cfar), "cfar"); 130 #endif 131 132 cpu_xer = tcg_global_mem_new(tcg_env, 133 offsetof(CPUPPCState, xer), "xer"); 134 cpu_so = tcg_global_mem_new(tcg_env, 135 offsetof(CPUPPCState, so), "SO"); 136 cpu_ov = tcg_global_mem_new(tcg_env, 137 offsetof(CPUPPCState, ov), "OV"); 138 cpu_ca = tcg_global_mem_new(tcg_env, 139 offsetof(CPUPPCState, ca), "CA"); 140 cpu_ov32 = tcg_global_mem_new(tcg_env, 141 offsetof(CPUPPCState, ov32), "OV32"); 142 cpu_ca32 = tcg_global_mem_new(tcg_env, 143 offsetof(CPUPPCState, ca32), "CA32"); 144 145 cpu_reserve = tcg_global_mem_new(tcg_env, 146 offsetof(CPUPPCState, reserve_addr), 147 "reserve_addr"); 148 cpu_reserve_length = tcg_global_mem_new(tcg_env, 149 offsetof(CPUPPCState, 150 reserve_length), 151 "reserve_length"); 152 cpu_reserve_val = tcg_global_mem_new(tcg_env, 153 offsetof(CPUPPCState, reserve_val), 154 "reserve_val"); 155 #if defined(TARGET_PPC64) 156 cpu_reserve_val2 = tcg_global_mem_new(tcg_env, 157 offsetof(CPUPPCState, reserve_val2), 158 "reserve_val2"); 159 #endif 160 161 cpu_fpscr = tcg_global_mem_new(tcg_env, 162 offsetof(CPUPPCState, fpscr), "fpscr"); 163 164 cpu_access_type = tcg_global_mem_new_i32(tcg_env, 165 offsetof(CPUPPCState, access_type), 166 "access_type"); 167 } 168 169 /* internal defines */ 170 struct DisasContext { 171 DisasContextBase base; 172 target_ulong cia; /* current instruction address */ 173 uint32_t opcode; 174 /* Routine used to access memory */ 175 bool pr, hv, dr, le_mode; 176 bool lazy_tlb_flush; 177 bool need_access_type; 178 int mem_idx; 179 int access_type; 180 /* Translation flags */ 181 MemOp default_tcg_memop_mask; 182 #if defined(TARGET_PPC64) 183 powerpc_excp_t excp_model; 184 bool sf_mode; 185 bool has_cfar; 186 bool has_bhrb; 187 #endif 188 bool fpu_enabled; 189 bool altivec_enabled; 190 bool vsx_enabled; 191 bool spe_enabled; 192 bool tm_enabled; 193 bool gtse; 194 bool hr; 195 bool mmcr0_pmcc0; 196 bool mmcr0_pmcc1; 197 bool mmcr0_pmcjce; 198 bool pmc_other; 199 bool pmu_insn_cnt; 200 bool bhrb_enable; 201 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 202 int singlestep_enabled; 203 uint32_t flags; 204 uint64_t insns_flags; 205 uint64_t insns_flags2; 206 }; 207 208 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 209 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 210 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 211 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 212 213 /* Return true iff byteswap is needed in a scalar memop */ 214 static inline bool need_byteswap(const DisasContext *ctx) 215 { 216 #if TARGET_BIG_ENDIAN 217 return ctx->le_mode; 218 #else 219 return !ctx->le_mode; 220 #endif 221 } 222 223 /* True when active word size < size of target_long. */ 224 #ifdef TARGET_PPC64 225 # define NARROW_MODE(C) (!(C)->sf_mode) 226 #else 227 # define NARROW_MODE(C) 0 228 #endif 229 230 struct opc_handler_t { 231 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 232 uint32_t inval1; 233 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 234 uint32_t inval2; 235 /* instruction type */ 236 uint64_t type; 237 /* extended instruction type */ 238 uint64_t type2; 239 /* handler */ 240 void (*handler)(DisasContext *ctx); 241 }; 242 243 static inline bool gen_serialize(DisasContext *ctx) 244 { 245 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 246 /* Restart with exclusive lock. */ 247 gen_helper_exit_atomic(tcg_env); 248 ctx->base.is_jmp = DISAS_NORETURN; 249 return false; 250 } 251 return true; 252 } 253 254 #if !defined(CONFIG_USER_ONLY) 255 #if defined(TARGET_PPC64) 256 static inline bool gen_serialize_core(DisasContext *ctx) 257 { 258 if (ctx->flags & POWERPC_FLAG_SMT) { 259 return gen_serialize(ctx); 260 } 261 return true; 262 } 263 #endif 264 265 static inline bool gen_serialize_core_lpar(DisasContext *ctx) 266 { 267 #if defined(TARGET_PPC64) 268 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 269 return gen_serialize(ctx); 270 } 271 #endif 272 return true; 273 } 274 #endif 275 276 /* SPR load/store helpers */ 277 static inline void gen_load_spr(TCGv t, int reg) 278 { 279 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); 280 } 281 282 static inline void gen_store_spr(int reg, TCGv t) 283 { 284 tcg_gen_st_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); 285 } 286 287 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 288 { 289 if (ctx->need_access_type && ctx->access_type != access_type) { 290 tcg_gen_movi_i32(cpu_access_type, access_type); 291 ctx->access_type = access_type; 292 } 293 } 294 295 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 296 { 297 if (NARROW_MODE(ctx)) { 298 nip = (uint32_t)nip; 299 } 300 tcg_gen_movi_tl(cpu_nip, nip); 301 } 302 303 static void gen_exception_err_nip(DisasContext *ctx, uint32_t excp, 304 uint32_t error, target_ulong nip) 305 { 306 TCGv_i32 t0, t1; 307 308 gen_update_nip(ctx, nip); 309 t0 = tcg_constant_i32(excp); 310 t1 = tcg_constant_i32(error); 311 gen_helper_raise_exception_err(tcg_env, t0, t1); 312 ctx->base.is_jmp = DISAS_NORETURN; 313 } 314 315 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, 316 uint32_t error) 317 { 318 /* 319 * These are all synchronous exceptions, we set the PC back to the 320 * faulting instruction 321 */ 322 gen_exception_err_nip(ctx, excp, error, ctx->cia); 323 } 324 325 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 326 target_ulong nip) 327 { 328 TCGv_i32 t0; 329 330 gen_update_nip(ctx, nip); 331 t0 = tcg_constant_i32(excp); 332 gen_helper_raise_exception(tcg_env, t0); 333 ctx->base.is_jmp = DISAS_NORETURN; 334 } 335 336 static inline void gen_exception(DisasContext *ctx, uint32_t excp) 337 { 338 /* 339 * These are all synchronous exceptions, we set the PC back to the 340 * faulting instruction 341 */ 342 gen_exception_nip(ctx, excp, ctx->cia); 343 } 344 345 #if !defined(CONFIG_USER_ONLY) 346 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 347 { 348 translator_io_start(&ctx->base); 349 gen_helper_ppc_maybe_interrupt(tcg_env); 350 } 351 #endif 352 353 /* 354 * Tells the caller what is the appropriate exception to generate and prepares 355 * SPR registers for this exception. 356 * 357 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 358 * POWERPC_EXCP_DEBUG (on BookE). 359 */ 360 static void gen_debug_exception(DisasContext *ctx, bool rfi_type) 361 { 362 #if !defined(CONFIG_USER_ONLY) 363 if (ctx->flags & POWERPC_FLAG_DE) { 364 target_ulong dbsr = 0; 365 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 366 dbsr = DBCR0_ICMP; 367 } else { 368 /* Must have been branch */ 369 dbsr = DBCR0_BRT; 370 } 371 TCGv t0 = tcg_temp_new(); 372 gen_load_spr(t0, SPR_BOOKE_DBSR); 373 tcg_gen_ori_tl(t0, t0, dbsr); 374 gen_store_spr(SPR_BOOKE_DBSR, t0); 375 gen_helper_raise_exception(tcg_env, 376 tcg_constant_i32(POWERPC_EXCP_DEBUG)); 377 ctx->base.is_jmp = DISAS_NORETURN; 378 } else { 379 if (!rfi_type) { /* BookS does not single step rfi type instructions */ 380 TCGv t0 = tcg_temp_new(); 381 tcg_gen_movi_tl(t0, ctx->cia); 382 gen_helper_book3s_trace(tcg_env, t0); 383 ctx->base.is_jmp = DISAS_NORETURN; 384 } 385 } 386 #endif 387 } 388 389 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 390 { 391 /* Will be converted to program check if needed */ 392 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 393 } 394 395 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 396 { 397 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 398 } 399 400 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 401 { 402 /* Will be converted to program check if needed */ 403 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 404 } 405 406 /*****************************************************************************/ 407 /* SPR READ/WRITE CALLBACKS */ 408 409 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 410 { 411 #if 0 412 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 413 printf("ERROR: try to access SPR %d !\n", sprn); 414 #endif 415 } 416 417 /* #define PPC_DUMP_SPR_ACCESSES */ 418 419 /* 420 * Generic callbacks: 421 * do nothing but store/retrieve spr value 422 */ 423 static void spr_load_dump_spr(int sprn) 424 { 425 #ifdef PPC_DUMP_SPR_ACCESSES 426 TCGv_i32 t0 = tcg_constant_i32(sprn); 427 gen_helper_load_dump_spr(tcg_env, t0); 428 #endif 429 } 430 431 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 432 { 433 gen_load_spr(cpu_gpr[gprn], sprn); 434 spr_load_dump_spr(sprn); 435 } 436 437 static void spr_store_dump_spr(int sprn) 438 { 439 #ifdef PPC_DUMP_SPR_ACCESSES 440 TCGv_i32 t0 = tcg_constant_i32(sprn); 441 gen_helper_store_dump_spr(tcg_env, t0); 442 #endif 443 } 444 445 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 446 { 447 gen_store_spr(sprn, cpu_gpr[gprn]); 448 spr_store_dump_spr(sprn); 449 } 450 451 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 452 { 453 #ifdef TARGET_PPC64 454 TCGv t0 = tcg_temp_new(); 455 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 456 gen_store_spr(sprn, t0); 457 spr_store_dump_spr(sprn); 458 #else 459 spr_write_generic(ctx, sprn, gprn); 460 #endif 461 } 462 463 void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) 464 { 465 if (!(ctx->flags & POWERPC_FLAG_SMT)) { 466 spr_write_generic(ctx, sprn, gprn); 467 return; 468 } 469 470 if (!gen_serialize(ctx)) { 471 return; 472 } 473 474 gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), 475 cpu_gpr[gprn]); 476 spr_store_dump_spr(sprn); 477 } 478 479 void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn) 480 { 481 TCGv t0; 482 483 if (!(ctx->flags & POWERPC_FLAG_SMT)) { 484 spr_write_generic32(ctx, sprn, gprn); 485 return; 486 } 487 488 if (!gen_serialize(ctx)) { 489 return; 490 } 491 492 t0 = tcg_temp_new(); 493 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 494 gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), t0); 495 spr_store_dump_spr(sprn); 496 } 497 498 void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn) 499 { 500 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 501 spr_core_write_generic(ctx, sprn, gprn); 502 } else { 503 spr_write_generic(ctx, sprn, gprn); 504 } 505 } 506 507 static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 508 { 509 /* This does not implement >1 thread */ 510 TCGv t0 = tcg_temp_new(); 511 TCGv t1 = tcg_temp_new(); 512 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 513 tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 514 tcg_gen_or_tl(t1, t1, t0); 515 gen_store_spr(sprn, t1); 516 } 517 518 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 519 { 520 if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { 521 /* CTRL behaves as 1-thread in LPAR-per-thread mode */ 522 spr_write_CTRL_ST(ctx, sprn, gprn); 523 goto out; 524 } 525 526 if (!gen_serialize(ctx)) { 527 return; 528 } 529 530 gen_helper_spr_write_CTRL(tcg_env, tcg_constant_i32(sprn), 531 cpu_gpr[gprn]); 532 out: 533 spr_store_dump_spr(sprn); 534 535 /* 536 * SPR_CTRL writes must force a new translation block, 537 * allowing the PMU to calculate the run latch events with 538 * more accuracy. 539 */ 540 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 541 } 542 543 #if !defined(CONFIG_USER_ONLY) 544 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 545 { 546 TCGv t0 = tcg_temp_new(); 547 TCGv t1 = tcg_temp_new(); 548 gen_load_spr(t0, sprn); 549 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 550 tcg_gen_and_tl(t0, t0, t1); 551 gen_store_spr(sprn, t0); 552 } 553 554 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 555 { 556 } 557 558 #endif 559 560 /* SPR common to all PowerPC */ 561 /* XER */ 562 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 563 { 564 TCGv dst = cpu_gpr[gprn]; 565 TCGv t0 = tcg_temp_new(); 566 TCGv t1 = tcg_temp_new(); 567 TCGv t2 = tcg_temp_new(); 568 tcg_gen_mov_tl(dst, cpu_xer); 569 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 570 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 571 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 572 tcg_gen_or_tl(t0, t0, t1); 573 tcg_gen_or_tl(dst, dst, t2); 574 tcg_gen_or_tl(dst, dst, t0); 575 if (is_isa300(ctx)) { 576 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 577 tcg_gen_or_tl(dst, dst, t0); 578 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 579 tcg_gen_or_tl(dst, dst, t0); 580 } 581 } 582 583 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 584 { 585 TCGv src = cpu_gpr[gprn]; 586 /* Write all flags, while reading back check for isa300 */ 587 tcg_gen_andi_tl(cpu_xer, src, 588 ~((1u << XER_SO) | 589 (1u << XER_OV) | (1u << XER_OV32) | 590 (1u << XER_CA) | (1u << XER_CA32))); 591 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 592 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 593 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 594 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 595 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 596 } 597 598 /* LR */ 599 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 600 { 601 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 602 } 603 604 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 605 { 606 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 607 } 608 609 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 610 /* Debug facilities */ 611 /* CFAR */ 612 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 613 { 614 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 615 } 616 617 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 618 { 619 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 620 } 621 622 /* Breakpoint */ 623 void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn) 624 { 625 translator_io_start(&ctx->base); 626 gen_helper_store_ciabr(tcg_env, cpu_gpr[gprn]); 627 } 628 629 /* Watchpoint */ 630 void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn) 631 { 632 translator_io_start(&ctx->base); 633 gen_helper_store_dawr0(tcg_env, cpu_gpr[gprn]); 634 } 635 636 void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn) 637 { 638 translator_io_start(&ctx->base); 639 gen_helper_store_dawrx0(tcg_env, cpu_gpr[gprn]); 640 } 641 642 void spr_write_dawr1(DisasContext *ctx, int sprn, int gprn) 643 { 644 translator_io_start(&ctx->base); 645 gen_helper_store_dawr1(tcg_env, cpu_gpr[gprn]); 646 } 647 648 void spr_write_dawrx1(DisasContext *ctx, int sprn, int gprn) 649 { 650 translator_io_start(&ctx->base); 651 gen_helper_store_dawrx1(tcg_env, cpu_gpr[gprn]); 652 } 653 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 654 655 /* CTR */ 656 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 657 { 658 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 659 } 660 661 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 662 { 663 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 664 } 665 666 /* User read access to SPR */ 667 /* USPRx */ 668 /* UMMCRx */ 669 /* UPMCx */ 670 /* USIA */ 671 /* UDECR */ 672 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 673 { 674 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 675 } 676 677 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 678 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 679 { 680 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 681 } 682 #endif 683 684 /* SPR common to all non-embedded PowerPC */ 685 /* DECR */ 686 #if !defined(CONFIG_USER_ONLY) 687 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 688 { 689 translator_io_start(&ctx->base); 690 gen_helper_load_decr(cpu_gpr[gprn], tcg_env); 691 } 692 693 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 694 { 695 translator_io_start(&ctx->base); 696 gen_helper_store_decr(tcg_env, cpu_gpr[gprn]); 697 } 698 #endif 699 700 /* SPR common to all non-embedded PowerPC, except 601 */ 701 /* Time base */ 702 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 703 { 704 translator_io_start(&ctx->base); 705 gen_helper_load_tbl(cpu_gpr[gprn], tcg_env); 706 } 707 708 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 709 { 710 translator_io_start(&ctx->base); 711 gen_helper_load_tbu(cpu_gpr[gprn], tcg_env); 712 } 713 714 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 715 { 716 gen_helper_load_atbl(cpu_gpr[gprn], tcg_env); 717 } 718 719 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 720 { 721 gen_helper_load_atbu(cpu_gpr[gprn], tcg_env); 722 } 723 724 #if !defined(CONFIG_USER_ONLY) 725 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 726 { 727 if (!gen_serialize_core_lpar(ctx)) { 728 return; 729 } 730 731 translator_io_start(&ctx->base); 732 gen_helper_store_tbl(tcg_env, cpu_gpr[gprn]); 733 } 734 735 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 736 { 737 if (!gen_serialize_core_lpar(ctx)) { 738 return; 739 } 740 741 translator_io_start(&ctx->base); 742 gen_helper_store_tbu(tcg_env, cpu_gpr[gprn]); 743 } 744 745 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 746 { 747 gen_helper_store_atbl(tcg_env, cpu_gpr[gprn]); 748 } 749 750 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 751 { 752 gen_helper_store_atbu(tcg_env, cpu_gpr[gprn]); 753 } 754 755 #if defined(TARGET_PPC64) 756 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 757 { 758 translator_io_start(&ctx->base); 759 gen_helper_load_purr(cpu_gpr[gprn], tcg_env); 760 } 761 762 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 763 { 764 if (!gen_serialize_core_lpar(ctx)) { 765 return; 766 } 767 translator_io_start(&ctx->base); 768 gen_helper_store_purr(tcg_env, cpu_gpr[gprn]); 769 } 770 771 /* HDECR */ 772 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 773 { 774 translator_io_start(&ctx->base); 775 gen_helper_load_hdecr(cpu_gpr[gprn], tcg_env); 776 } 777 778 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 779 { 780 if (!gen_serialize_core_lpar(ctx)) { 781 return; 782 } 783 translator_io_start(&ctx->base); 784 gen_helper_store_hdecr(tcg_env, cpu_gpr[gprn]); 785 } 786 787 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 788 { 789 translator_io_start(&ctx->base); 790 gen_helper_load_vtb(cpu_gpr[gprn], tcg_env); 791 } 792 793 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 794 { 795 if (!gen_serialize_core_lpar(ctx)) { 796 return; 797 } 798 translator_io_start(&ctx->base); 799 gen_helper_store_vtb(tcg_env, cpu_gpr[gprn]); 800 } 801 802 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 803 { 804 if (!gen_serialize_core_lpar(ctx)) { 805 return; 806 } 807 translator_io_start(&ctx->base); 808 gen_helper_store_tbu40(tcg_env, cpu_gpr[gprn]); 809 } 810 811 #endif 812 #endif 813 814 #if !defined(CONFIG_USER_ONLY) 815 /* IBAT0U...IBAT0U */ 816 /* IBAT0L...IBAT7L */ 817 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 818 { 819 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 820 offsetof(CPUPPCState, 821 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 822 } 823 824 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 825 { 826 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 827 offsetof(CPUPPCState, 828 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 829 } 830 831 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 832 { 833 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 834 gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); 835 } 836 837 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 838 { 839 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 840 gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); 841 } 842 843 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 844 { 845 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 846 gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); 847 } 848 849 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 850 { 851 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 852 gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); 853 } 854 855 /* DBAT0U...DBAT7U */ 856 /* DBAT0L...DBAT7L */ 857 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 858 { 859 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 860 offsetof(CPUPPCState, 861 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 862 } 863 864 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 865 { 866 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 867 offsetof(CPUPPCState, 868 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 869 } 870 871 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 872 { 873 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 874 gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); 875 } 876 877 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 878 { 879 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 880 gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); 881 } 882 883 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 884 { 885 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 886 gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); 887 } 888 889 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 890 { 891 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 892 gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); 893 } 894 895 /* SDR1 */ 896 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 897 { 898 gen_helper_store_sdr1(tcg_env, cpu_gpr[gprn]); 899 } 900 901 #if defined(TARGET_PPC64) 902 /* 64 bits PowerPC specific SPRs */ 903 /* PIDR */ 904 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 905 { 906 gen_helper_store_pidr(tcg_env, cpu_gpr[gprn]); 907 } 908 909 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 910 { 911 gen_helper_store_lpidr(tcg_env, cpu_gpr[gprn]); 912 } 913 914 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 915 { 916 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, excp_prefix)); 917 } 918 919 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 920 { 921 TCGv t0 = tcg_temp_new(); 922 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 923 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); 924 } 925 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 926 { 927 if (!gen_serialize_core(ctx)) { 928 return; 929 } 930 931 gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]); 932 } 933 934 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 935 { 936 gen_helper_store_pcr(tcg_env, cpu_gpr[gprn]); 937 } 938 939 /* DPDES */ 940 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 941 { 942 if (!gen_serialize_core_lpar(ctx)) { 943 return; 944 } 945 946 gen_helper_load_dpdes(cpu_gpr[gprn], tcg_env); 947 } 948 949 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 950 { 951 if (!gen_serialize_core_lpar(ctx)) { 952 return; 953 } 954 955 gen_helper_store_dpdes(tcg_env, cpu_gpr[gprn]); 956 } 957 #endif 958 #endif 959 960 /* PowerPC 40x specific registers */ 961 #if !defined(CONFIG_USER_ONLY) 962 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 963 { 964 translator_io_start(&ctx->base); 965 gen_helper_load_40x_pit(cpu_gpr[gprn], tcg_env); 966 } 967 968 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 969 { 970 translator_io_start(&ctx->base); 971 gen_helper_store_40x_pit(tcg_env, cpu_gpr[gprn]); 972 } 973 974 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 975 { 976 translator_io_start(&ctx->base); 977 gen_store_spr(sprn, cpu_gpr[gprn]); 978 gen_helper_store_40x_dbcr0(tcg_env, cpu_gpr[gprn]); 979 /* We must stop translation as we may have rebooted */ 980 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 981 } 982 983 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 984 { 985 translator_io_start(&ctx->base); 986 gen_helper_store_40x_sler(tcg_env, cpu_gpr[gprn]); 987 } 988 989 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 990 { 991 translator_io_start(&ctx->base); 992 gen_helper_store_40x_tcr(tcg_env, cpu_gpr[gprn]); 993 } 994 995 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 996 { 997 translator_io_start(&ctx->base); 998 gen_helper_store_40x_tsr(tcg_env, cpu_gpr[gprn]); 999 } 1000 1001 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 1002 { 1003 TCGv t0 = tcg_temp_new(); 1004 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 1005 gen_helper_store_40x_pid(tcg_env, t0); 1006 } 1007 1008 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 1009 { 1010 translator_io_start(&ctx->base); 1011 gen_helper_store_booke_tcr(tcg_env, cpu_gpr[gprn]); 1012 } 1013 1014 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 1015 { 1016 translator_io_start(&ctx->base); 1017 gen_helper_store_booke_tsr(tcg_env, cpu_gpr[gprn]); 1018 } 1019 #endif 1020 1021 /* PIR */ 1022 #if !defined(CONFIG_USER_ONLY) 1023 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 1024 { 1025 TCGv t0 = tcg_temp_new(); 1026 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 1027 gen_store_spr(SPR_PIR, t0); 1028 } 1029 #endif 1030 1031 /* SPE specific registers */ 1032 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 1033 { 1034 TCGv_i32 t0 = tcg_temp_new_i32(); 1035 tcg_gen_ld_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); 1036 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 1037 } 1038 1039 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 1040 { 1041 TCGv_i32 t0 = tcg_temp_new_i32(); 1042 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 1043 tcg_gen_st_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); 1044 } 1045 1046 #if !defined(CONFIG_USER_ONLY) 1047 /* Callback used to write the exception vector base */ 1048 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 1049 { 1050 TCGv t0 = tcg_temp_new(); 1051 tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivpr_mask)); 1052 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 1053 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); 1054 gen_store_spr(sprn, t0); 1055 } 1056 1057 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 1058 { 1059 int sprn_offs; 1060 1061 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 1062 sprn_offs = sprn - SPR_BOOKE_IVOR0; 1063 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 1064 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 1065 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 1066 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 1067 } else { 1068 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 1069 " vector 0x%03x\n", sprn); 1070 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1071 return; 1072 } 1073 1074 TCGv t0 = tcg_temp_new(); 1075 tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivor_mask)); 1076 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 1077 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 1078 gen_store_spr(sprn, t0); 1079 } 1080 #endif 1081 1082 #ifdef TARGET_PPC64 1083 #ifndef CONFIG_USER_ONLY 1084 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 1085 { 1086 TCGv t0 = tcg_temp_new(); 1087 TCGv t1 = tcg_temp_new(); 1088 TCGv t2 = tcg_temp_new(); 1089 1090 /* 1091 * Note, the HV=1 PR=0 case is handled earlier by simply using 1092 * spr_write_generic for HV mode in the SPR table 1093 */ 1094 1095 /* Build insertion mask into t1 based on context */ 1096 if (ctx->pr) { 1097 gen_load_spr(t1, SPR_UAMOR); 1098 } else { 1099 gen_load_spr(t1, SPR_AMOR); 1100 } 1101 1102 /* Mask new bits into t2 */ 1103 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1104 1105 /* Load AMR and clear new bits in t0 */ 1106 gen_load_spr(t0, SPR_AMR); 1107 tcg_gen_andc_tl(t0, t0, t1); 1108 1109 /* Or'in new bits and write it out */ 1110 tcg_gen_or_tl(t0, t0, t2); 1111 gen_store_spr(SPR_AMR, t0); 1112 spr_store_dump_spr(SPR_AMR); 1113 } 1114 1115 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 1116 { 1117 TCGv t0 = tcg_temp_new(); 1118 TCGv t1 = tcg_temp_new(); 1119 TCGv t2 = tcg_temp_new(); 1120 1121 /* 1122 * Note, the HV=1 case is handled earlier by simply using 1123 * spr_write_generic for HV mode in the SPR table 1124 */ 1125 1126 /* Build insertion mask into t1 based on context */ 1127 gen_load_spr(t1, SPR_AMOR); 1128 1129 /* Mask new bits into t2 */ 1130 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1131 1132 /* Load AMR and clear new bits in t0 */ 1133 gen_load_spr(t0, SPR_UAMOR); 1134 tcg_gen_andc_tl(t0, t0, t1); 1135 1136 /* Or'in new bits and write it out */ 1137 tcg_gen_or_tl(t0, t0, t2); 1138 gen_store_spr(SPR_UAMOR, t0); 1139 spr_store_dump_spr(SPR_UAMOR); 1140 } 1141 1142 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1143 { 1144 TCGv t0 = tcg_temp_new(); 1145 TCGv t1 = tcg_temp_new(); 1146 TCGv t2 = tcg_temp_new(); 1147 1148 /* 1149 * Note, the HV=1 case is handled earlier by simply using 1150 * spr_write_generic for HV mode in the SPR table 1151 */ 1152 1153 /* Build insertion mask into t1 based on context */ 1154 gen_load_spr(t1, SPR_AMOR); 1155 1156 /* Mask new bits into t2 */ 1157 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1158 1159 /* Load AMR and clear new bits in t0 */ 1160 gen_load_spr(t0, SPR_IAMR); 1161 tcg_gen_andc_tl(t0, t0, t1); 1162 1163 /* Or'in new bits and write it out */ 1164 tcg_gen_or_tl(t0, t0, t2); 1165 gen_store_spr(SPR_IAMR, t0); 1166 spr_store_dump_spr(SPR_IAMR); 1167 } 1168 #endif 1169 #endif 1170 1171 #ifndef CONFIG_USER_ONLY 1172 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1173 { 1174 gen_helper_fixup_thrm(tcg_env); 1175 gen_load_spr(cpu_gpr[gprn], sprn); 1176 spr_load_dump_spr(sprn); 1177 } 1178 #endif /* !CONFIG_USER_ONLY */ 1179 1180 #if !defined(CONFIG_USER_ONLY) 1181 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1182 { 1183 TCGv t0 = tcg_temp_new(); 1184 1185 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1186 gen_store_spr(sprn, t0); 1187 } 1188 1189 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1190 { 1191 TCGv t0 = tcg_temp_new(); 1192 1193 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1194 gen_store_spr(sprn, t0); 1195 } 1196 1197 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1198 { 1199 TCGv t0 = tcg_temp_new(); 1200 1201 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1202 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1203 gen_store_spr(sprn, t0); 1204 } 1205 1206 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1207 { 1208 gen_helper_booke206_tlbflush(tcg_env, cpu_gpr[gprn]); 1209 } 1210 1211 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1212 { 1213 TCGv_i32 t0 = tcg_constant_i32(sprn); 1214 gen_helper_booke_setpid(tcg_env, t0, cpu_gpr[gprn]); 1215 } 1216 1217 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1218 { 1219 gen_helper_booke_set_eplc(tcg_env, cpu_gpr[gprn]); 1220 } 1221 1222 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1223 { 1224 gen_helper_booke_set_epsc(tcg_env, cpu_gpr[gprn]); 1225 } 1226 1227 #endif 1228 1229 #if !defined(CONFIG_USER_ONLY) 1230 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1231 { 1232 TCGv val = tcg_temp_new(); 1233 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1234 gen_store_spr(SPR_BOOKE_MAS3, val); 1235 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1236 gen_store_spr(SPR_BOOKE_MAS7, val); 1237 } 1238 1239 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1240 { 1241 TCGv mas7 = tcg_temp_new(); 1242 TCGv mas3 = tcg_temp_new(); 1243 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1244 tcg_gen_shli_tl(mas7, mas7, 32); 1245 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1246 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1247 } 1248 1249 #endif 1250 1251 #ifdef TARGET_PPC64 1252 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1253 int bit, int sprn, int cause) 1254 { 1255 TCGv_i32 t1 = tcg_constant_i32(bit); 1256 TCGv_i32 t2 = tcg_constant_i32(sprn); 1257 TCGv_i32 t3 = tcg_constant_i32(cause); 1258 1259 gen_helper_fscr_facility_check(tcg_env, t1, t2, t3); 1260 } 1261 1262 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1263 int bit, int sprn, int cause) 1264 { 1265 TCGv_i32 t1 = tcg_constant_i32(bit); 1266 TCGv_i32 t2 = tcg_constant_i32(sprn); 1267 TCGv_i32 t3 = tcg_constant_i32(cause); 1268 1269 gen_helper_msr_facility_check(tcg_env, t1, t2, t3); 1270 } 1271 1272 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1273 { 1274 TCGv spr_up = tcg_temp_new(); 1275 TCGv spr = tcg_temp_new(); 1276 1277 gen_load_spr(spr, sprn - 1); 1278 tcg_gen_shri_tl(spr_up, spr, 32); 1279 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1280 } 1281 1282 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1283 { 1284 TCGv spr = tcg_temp_new(); 1285 1286 gen_load_spr(spr, sprn - 1); 1287 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1288 gen_store_spr(sprn - 1, spr); 1289 } 1290 1291 #if !defined(CONFIG_USER_ONLY) 1292 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1293 { 1294 TCGv hmer = tcg_temp_new(); 1295 1296 gen_load_spr(hmer, sprn); 1297 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1298 gen_store_spr(sprn, hmer); 1299 spr_store_dump_spr(sprn); 1300 } 1301 1302 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1303 { 1304 /* Reading TFMR can cause it to be updated, so serialize threads here too */ 1305 if (!gen_serialize_core(ctx)) { 1306 return; 1307 } 1308 gen_helper_load_tfmr(cpu_gpr[gprn], tcg_env); 1309 } 1310 1311 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1312 { 1313 if (!gen_serialize_core(ctx)) { 1314 return; 1315 } 1316 gen_helper_store_tfmr(tcg_env, cpu_gpr[gprn]); 1317 } 1318 1319 void spr_write_sprc(DisasContext *ctx, int sprn, int gprn) 1320 { 1321 gen_helper_store_sprc(tcg_env, cpu_gpr[gprn]); 1322 } 1323 1324 void spr_read_sprd(DisasContext *ctx, int gprn, int sprn) 1325 { 1326 gen_helper_load_sprd(cpu_gpr[gprn], tcg_env); 1327 } 1328 1329 void spr_write_sprd(DisasContext *ctx, int sprn, int gprn) 1330 { 1331 if (!gen_serialize_core(ctx)) { 1332 return; 1333 } 1334 gen_helper_store_sprd(tcg_env, cpu_gpr[gprn]); 1335 } 1336 1337 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1338 { 1339 translator_io_start(&ctx->base); 1340 gen_helper_store_lpcr(tcg_env, cpu_gpr[gprn]); 1341 } 1342 1343 void spr_read_pmsr(DisasContext *ctx, int gprn, int sprn) 1344 { 1345 translator_io_start(&ctx->base); 1346 gen_helper_load_pmsr(cpu_gpr[gprn], tcg_env); 1347 } 1348 1349 void spr_write_pmcr(DisasContext *ctx, int sprn, int gprn) 1350 { 1351 if (!gen_serialize_core_lpar(ctx)) { 1352 return; 1353 } 1354 translator_io_start(&ctx->base); 1355 gen_helper_store_pmcr(tcg_env, cpu_gpr[gprn]); 1356 } 1357 1358 #endif /* !defined(CONFIG_USER_ONLY) */ 1359 1360 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1361 { 1362 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1363 spr_read_generic(ctx, gprn, sprn); 1364 } 1365 1366 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1367 { 1368 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1369 spr_write_generic(ctx, sprn, gprn); 1370 } 1371 1372 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1373 { 1374 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1375 spr_read_generic(ctx, gprn, sprn); 1376 } 1377 1378 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1379 { 1380 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1381 spr_write_generic(ctx, sprn, gprn); 1382 } 1383 1384 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1385 { 1386 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1387 spr_read_prev_upper32(ctx, gprn, sprn); 1388 } 1389 1390 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1391 { 1392 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1393 spr_write_prev_upper32(ctx, sprn, gprn); 1394 } 1395 1396 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1397 { 1398 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1399 spr_read_generic(ctx, gprn, sprn); 1400 } 1401 1402 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1403 { 1404 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1405 spr_write_generic(ctx, sprn, gprn); 1406 } 1407 1408 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1409 { 1410 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1411 spr_read_prev_upper32(ctx, gprn, sprn); 1412 } 1413 1414 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1415 { 1416 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1417 spr_write_prev_upper32(ctx, sprn, gprn); 1418 } 1419 1420 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1421 { 1422 TCGv t0 = tcg_temp_new(); 1423 1424 /* 1425 * Access to the (H)DEXCR in problem state is done using separated 1426 * SPR indexes which are 16 below the SPR indexes which have full 1427 * access to the (H)DEXCR in privileged state. Problem state can 1428 * only read bits 32:63, bits 0:31 return 0. 1429 * 1430 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1431 */ 1432 1433 gen_load_spr(t0, sprn + 16); 1434 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1435 } 1436 1437 /* The PPR32 SPR accesses the upper 32-bits of PPR */ 1438 void spr_read_ppr32(DisasContext *ctx, int gprn, int sprn) 1439 { 1440 gen_load_spr(cpu_gpr[gprn], SPR_PPR); 1441 tcg_gen_shri_tl(cpu_gpr[gprn], cpu_gpr[gprn], 32); 1442 spr_load_dump_spr(SPR_PPR); 1443 } 1444 1445 void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn) 1446 { 1447 TCGv t0 = tcg_temp_new(); 1448 1449 /* 1450 * Don't clobber the low 32-bits of the PPR. These are all reserved bits 1451 * but TCG does implement them, so it would be surprising to zero them 1452 * here. "Priority nops" are similarly careful not to clobber reserved 1453 * bits. 1454 */ 1455 gen_load_spr(t0, SPR_PPR); 1456 tcg_gen_deposit_tl(t0, t0, cpu_gpr[gprn], 32, 32); 1457 gen_store_spr(SPR_PPR, t0); 1458 spr_store_dump_spr(SPR_PPR); 1459 } 1460 #endif 1461 1462 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1463 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1464 1465 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1466 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1467 1468 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1469 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1470 1471 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1472 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1473 1474 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1475 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1476 1477 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1478 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1479 1480 typedef struct opcode_t { 1481 unsigned char opc1, opc2, opc3, opc4; 1482 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1483 unsigned char pad[4]; 1484 #endif 1485 opc_handler_t handler; 1486 const char *oname; 1487 } opcode_t; 1488 1489 static void gen_priv_opc(DisasContext *ctx) 1490 { 1491 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1492 } 1493 1494 /* Helpers for priv. check */ 1495 #define GEN_PRIV(CTX) \ 1496 do { \ 1497 gen_priv_opc(CTX); return; \ 1498 } while (0) 1499 1500 #if defined(CONFIG_USER_ONLY) 1501 #define CHK_HV(CTX) GEN_PRIV(CTX) 1502 #define CHK_SV(CTX) GEN_PRIV(CTX) 1503 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1504 #else 1505 #define CHK_HV(CTX) \ 1506 do { \ 1507 if (unlikely(ctx->pr || !ctx->hv)) {\ 1508 GEN_PRIV(CTX); \ 1509 } \ 1510 } while (0) 1511 #define CHK_SV(CTX) \ 1512 do { \ 1513 if (unlikely(ctx->pr)) { \ 1514 GEN_PRIV(CTX); \ 1515 } \ 1516 } while (0) 1517 #define CHK_HVRM(CTX) \ 1518 do { \ 1519 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1520 GEN_PRIV(CTX); \ 1521 } \ 1522 } while (0) 1523 #endif 1524 1525 #define CHK_NONE(CTX) 1526 1527 /*****************************************************************************/ 1528 /* PowerPC instructions table */ 1529 1530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1531 { \ 1532 .opc1 = op1, \ 1533 .opc2 = op2, \ 1534 .opc3 = op3, \ 1535 .opc4 = 0xff, \ 1536 .handler = { \ 1537 .inval1 = invl, \ 1538 .type = _typ, \ 1539 .type2 = _typ2, \ 1540 .handler = &gen_##name, \ 1541 }, \ 1542 .oname = stringify(name), \ 1543 } 1544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1545 { \ 1546 .opc1 = op1, \ 1547 .opc2 = op2, \ 1548 .opc3 = op3, \ 1549 .opc4 = 0xff, \ 1550 .handler = { \ 1551 .inval1 = invl1, \ 1552 .inval2 = invl2, \ 1553 .type = _typ, \ 1554 .type2 = _typ2, \ 1555 .handler = &gen_##name, \ 1556 }, \ 1557 .oname = stringify(name), \ 1558 } 1559 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1560 { \ 1561 .opc1 = op1, \ 1562 .opc2 = op2, \ 1563 .opc3 = op3, \ 1564 .opc4 = 0xff, \ 1565 .handler = { \ 1566 .inval1 = invl, \ 1567 .type = _typ, \ 1568 .type2 = _typ2, \ 1569 .handler = &gen_##name, \ 1570 }, \ 1571 .oname = onam, \ 1572 } 1573 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1574 { \ 1575 .opc1 = op1, \ 1576 .opc2 = op2, \ 1577 .opc3 = op3, \ 1578 .opc4 = op4, \ 1579 .handler = { \ 1580 .inval1 = invl, \ 1581 .type = _typ, \ 1582 .type2 = _typ2, \ 1583 .handler = &gen_##name, \ 1584 }, \ 1585 .oname = stringify(name), \ 1586 } 1587 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1588 { \ 1589 .opc1 = op1, \ 1590 .opc2 = op2, \ 1591 .opc3 = op3, \ 1592 .opc4 = op4, \ 1593 .handler = { \ 1594 .inval1 = invl, \ 1595 .type = _typ, \ 1596 .type2 = _typ2, \ 1597 .handler = &gen_##name, \ 1598 }, \ 1599 .oname = onam, \ 1600 } 1601 1602 /* Invalid instruction */ 1603 static void gen_invalid(DisasContext *ctx) 1604 { 1605 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1606 } 1607 1608 static opc_handler_t invalid_handler = { 1609 .inval1 = 0xFFFFFFFF, 1610 .inval2 = 0xFFFFFFFF, 1611 .type = PPC_NONE, 1612 .type2 = PPC_NONE, 1613 .handler = gen_invalid, 1614 }; 1615 1616 /*** Integer comparison ***/ 1617 1618 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1619 { 1620 TCGv t0 = tcg_temp_new(); 1621 TCGv_i32 t = tcg_temp_new_i32(); 1622 1623 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1624 t0, arg0, arg1, 1625 tcg_constant_tl(CRF_LT), tcg_constant_tl(CRF_EQ)); 1626 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1627 t0, arg0, arg1, tcg_constant_tl(CRF_GT), t0); 1628 1629 tcg_gen_trunc_tl_i32(t, t0); 1630 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1631 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1632 } 1633 1634 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1635 { 1636 TCGv t0 = tcg_constant_tl(arg1); 1637 gen_op_cmp(arg0, t0, s, crf); 1638 } 1639 1640 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1641 { 1642 TCGv t0, t1; 1643 t0 = tcg_temp_new(); 1644 t1 = tcg_temp_new(); 1645 if (s) { 1646 tcg_gen_ext32s_tl(t0, arg0); 1647 tcg_gen_ext32s_tl(t1, arg1); 1648 } else { 1649 tcg_gen_ext32u_tl(t0, arg0); 1650 tcg_gen_ext32u_tl(t1, arg1); 1651 } 1652 gen_op_cmp(t0, t1, s, crf); 1653 } 1654 1655 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1656 { 1657 TCGv t0 = tcg_constant_tl(arg1); 1658 gen_op_cmp32(arg0, t0, s, crf); 1659 } 1660 1661 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1662 { 1663 if (NARROW_MODE(ctx)) { 1664 gen_op_cmpi32(reg, 0, 1, 0); 1665 } else { 1666 gen_op_cmpi(reg, 0, 1, 0); 1667 } 1668 } 1669 1670 /*** Integer arithmetic ***/ 1671 1672 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1673 TCGv arg1, TCGv arg2, int sub) 1674 { 1675 TCGv t0 = tcg_temp_new(); 1676 1677 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1678 tcg_gen_xor_tl(t0, arg1, arg2); 1679 if (sub) { 1680 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1681 } else { 1682 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1683 } 1684 if (NARROW_MODE(ctx)) { 1685 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1686 if (is_isa300(ctx)) { 1687 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1688 } 1689 } else { 1690 if (is_isa300(ctx)) { 1691 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1692 } 1693 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1694 } 1695 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1696 } 1697 1698 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1699 TCGv res, TCGv arg0, TCGv arg1, 1700 TCGv ca32, int sub) 1701 { 1702 TCGv t0; 1703 1704 if (!is_isa300(ctx)) { 1705 return; 1706 } 1707 1708 t0 = tcg_temp_new(); 1709 if (sub) { 1710 tcg_gen_eqv_tl(t0, arg0, arg1); 1711 } else { 1712 tcg_gen_xor_tl(t0, arg0, arg1); 1713 } 1714 tcg_gen_xor_tl(t0, t0, res); 1715 tcg_gen_extract_tl(ca32, t0, 32, 1); 1716 } 1717 1718 /* Common add function */ 1719 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1720 TCGv arg2, TCGv ca, TCGv ca32, 1721 bool add_ca, bool compute_ca, 1722 bool compute_ov, bool compute_rc0) 1723 { 1724 TCGv t0 = ret; 1725 1726 if (compute_ca || compute_ov) { 1727 t0 = tcg_temp_new(); 1728 } 1729 1730 if (compute_ca) { 1731 if (NARROW_MODE(ctx)) { 1732 /* 1733 * Caution: a non-obvious corner case of the spec is that 1734 * we must produce the *entire* 64-bit addition, but 1735 * produce the carry into bit 32. 1736 */ 1737 TCGv t1 = tcg_temp_new(); 1738 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1739 tcg_gen_add_tl(t0, arg1, arg2); 1740 if (add_ca) { 1741 tcg_gen_add_tl(t0, t0, ca); 1742 } 1743 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1744 tcg_gen_extract_tl(ca, ca, 32, 1); 1745 if (is_isa300(ctx)) { 1746 tcg_gen_mov_tl(ca32, ca); 1747 } 1748 } else { 1749 TCGv zero = tcg_constant_tl(0); 1750 if (add_ca) { 1751 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1752 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1753 } else { 1754 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1755 } 1756 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1757 } 1758 } else { 1759 tcg_gen_add_tl(t0, arg1, arg2); 1760 if (add_ca) { 1761 tcg_gen_add_tl(t0, t0, ca); 1762 } 1763 } 1764 1765 if (compute_ov) { 1766 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1767 } 1768 if (unlikely(compute_rc0)) { 1769 gen_set_Rc0(ctx, t0); 1770 } 1771 1772 if (t0 != ret) { 1773 tcg_gen_mov_tl(ret, t0); 1774 } 1775 } 1776 1777 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, 1778 TCGv arg1, TCGv arg2, bool sign, 1779 bool compute_ov, bool compute_rc0) 1780 { 1781 TCGv_i32 t0 = tcg_temp_new_i32(); 1782 TCGv_i32 t1 = tcg_temp_new_i32(); 1783 TCGv_i32 t2 = tcg_temp_new_i32(); 1784 TCGv_i32 t3 = tcg_temp_new_i32(); 1785 1786 tcg_gen_trunc_tl_i32(t0, arg1); 1787 tcg_gen_trunc_tl_i32(t1, arg2); 1788 if (sign) { 1789 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1790 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1791 tcg_gen_and_i32(t2, t2, t3); 1792 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1793 tcg_gen_or_i32(t2, t2, t3); 1794 tcg_gen_movi_i32(t3, 0); 1795 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1796 tcg_gen_div_i32(t3, t0, t1); 1797 tcg_gen_extu_i32_tl(ret, t3); 1798 } else { 1799 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1800 tcg_gen_movi_i32(t3, 0); 1801 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1802 tcg_gen_divu_i32(t3, t0, t1); 1803 tcg_gen_extu_i32_tl(ret, t3); 1804 } 1805 if (compute_ov) { 1806 tcg_gen_extu_i32_tl(cpu_ov, t2); 1807 if (is_isa300(ctx)) { 1808 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1809 } 1810 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1811 } 1812 1813 if (unlikely(compute_rc0)) { 1814 gen_set_Rc0(ctx, ret); 1815 } 1816 } 1817 1818 #if defined(TARGET_PPC64) 1819 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, 1820 TCGv arg1, TCGv arg2, bool sign, 1821 bool compute_ov, bool compute_rc0) 1822 { 1823 TCGv_i64 t0 = tcg_temp_new_i64(); 1824 TCGv_i64 t1 = tcg_temp_new_i64(); 1825 TCGv_i64 t2 = tcg_temp_new_i64(); 1826 TCGv_i64 t3 = tcg_temp_new_i64(); 1827 1828 tcg_gen_mov_i64(t0, arg1); 1829 tcg_gen_mov_i64(t1, arg2); 1830 if (sign) { 1831 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1832 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1833 tcg_gen_and_i64(t2, t2, t3); 1834 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1835 tcg_gen_or_i64(t2, t2, t3); 1836 tcg_gen_movi_i64(t3, 0); 1837 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1838 tcg_gen_div_i64(ret, t0, t1); 1839 } else { 1840 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1841 tcg_gen_movi_i64(t3, 0); 1842 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1843 tcg_gen_divu_i64(ret, t0, t1); 1844 } 1845 if (compute_ov) { 1846 tcg_gen_mov_tl(cpu_ov, t2); 1847 if (is_isa300(ctx)) { 1848 tcg_gen_mov_tl(cpu_ov32, t2); 1849 } 1850 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1851 } 1852 1853 if (unlikely(compute_rc0)) { 1854 gen_set_Rc0(ctx, ret); 1855 } 1856 } 1857 #endif 1858 1859 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1860 TCGv arg2, int sign) 1861 { 1862 TCGv_i32 t0 = tcg_temp_new_i32(); 1863 TCGv_i32 t1 = tcg_temp_new_i32(); 1864 1865 tcg_gen_trunc_tl_i32(t0, arg1); 1866 tcg_gen_trunc_tl_i32(t1, arg2); 1867 if (sign) { 1868 TCGv_i32 t2 = tcg_temp_new_i32(); 1869 TCGv_i32 t3 = tcg_temp_new_i32(); 1870 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1871 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1872 tcg_gen_and_i32(t2, t2, t3); 1873 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1874 tcg_gen_or_i32(t2, t2, t3); 1875 tcg_gen_movi_i32(t3, 0); 1876 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1877 tcg_gen_rem_i32(t3, t0, t1); 1878 tcg_gen_ext_i32_tl(ret, t3); 1879 } else { 1880 TCGv_i32 t2 = tcg_constant_i32(1); 1881 TCGv_i32 t3 = tcg_constant_i32(0); 1882 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1883 tcg_gen_remu_i32(t0, t0, t1); 1884 tcg_gen_extu_i32_tl(ret, t0); 1885 } 1886 } 1887 1888 #if defined(TARGET_PPC64) 1889 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1890 TCGv arg2, int sign) 1891 { 1892 TCGv_i64 t0 = tcg_temp_new_i64(); 1893 TCGv_i64 t1 = tcg_temp_new_i64(); 1894 1895 tcg_gen_mov_i64(t0, arg1); 1896 tcg_gen_mov_i64(t1, arg2); 1897 if (sign) { 1898 TCGv_i64 t2 = tcg_temp_new_i64(); 1899 TCGv_i64 t3 = tcg_temp_new_i64(); 1900 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1901 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1902 tcg_gen_and_i64(t2, t2, t3); 1903 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1904 tcg_gen_or_i64(t2, t2, t3); 1905 tcg_gen_movi_i64(t3, 0); 1906 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1907 tcg_gen_rem_i64(ret, t0, t1); 1908 } else { 1909 TCGv_i64 t2 = tcg_constant_i64(1); 1910 TCGv_i64 t3 = tcg_constant_i64(0); 1911 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1912 tcg_gen_remu_i64(ret, t0, t1); 1913 } 1914 } 1915 #endif 1916 1917 /* Common subf function */ 1918 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1919 TCGv arg2, bool add_ca, bool compute_ca, 1920 bool compute_ov, bool compute_rc0) 1921 { 1922 TCGv t0 = ret; 1923 1924 if (compute_ca || compute_ov) { 1925 t0 = tcg_temp_new(); 1926 } 1927 1928 if (compute_ca) { 1929 /* dest = ~arg1 + arg2 [+ ca]. */ 1930 if (NARROW_MODE(ctx)) { 1931 /* 1932 * Caution: a non-obvious corner case of the spec is that 1933 * we must produce the *entire* 64-bit addition, but 1934 * produce the carry into bit 32. 1935 */ 1936 TCGv inv1 = tcg_temp_new(); 1937 TCGv t1 = tcg_temp_new(); 1938 tcg_gen_not_tl(inv1, arg1); 1939 if (add_ca) { 1940 tcg_gen_add_tl(t0, arg2, cpu_ca); 1941 } else { 1942 tcg_gen_addi_tl(t0, arg2, 1); 1943 } 1944 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1945 tcg_gen_add_tl(t0, t0, inv1); 1946 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1947 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 1948 if (is_isa300(ctx)) { 1949 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 1950 } 1951 } else if (add_ca) { 1952 TCGv zero, inv1 = tcg_temp_new(); 1953 tcg_gen_not_tl(inv1, arg1); 1954 zero = tcg_constant_tl(0); 1955 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1956 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 1957 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 1958 } else { 1959 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1960 tcg_gen_sub_tl(t0, arg2, arg1); 1961 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 1962 } 1963 } else if (add_ca) { 1964 /* 1965 * Since we're ignoring carry-out, we can simplify the 1966 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 1967 */ 1968 tcg_gen_sub_tl(t0, arg2, arg1); 1969 tcg_gen_add_tl(t0, t0, cpu_ca); 1970 tcg_gen_subi_tl(t0, t0, 1); 1971 } else { 1972 tcg_gen_sub_tl(t0, arg2, arg1); 1973 } 1974 1975 if (compute_ov) { 1976 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1977 } 1978 if (unlikely(compute_rc0)) { 1979 gen_set_Rc0(ctx, t0); 1980 } 1981 1982 if (t0 != ret) { 1983 tcg_gen_mov_tl(ret, t0); 1984 } 1985 } 1986 1987 /*** Integer logical ***/ 1988 1989 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1990 static void gen_pause(DisasContext *ctx) 1991 { 1992 TCGv_i32 t0 = tcg_constant_i32(0); 1993 tcg_gen_st_i32(t0, tcg_env, 1994 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1995 1996 /* Stop translation, this gives other CPUs a chance to run */ 1997 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1998 } 1999 #endif /* defined(TARGET_PPC64) */ 2000 2001 /*** Integer rotate ***/ 2002 2003 /* rlwimi & rlwimi. */ 2004 static void gen_rlwimi(DisasContext *ctx) 2005 { 2006 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2007 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2008 uint32_t sh = SH(ctx->opcode); 2009 uint32_t mb = MB(ctx->opcode); 2010 uint32_t me = ME(ctx->opcode); 2011 2012 if (sh == (31 - me) && mb <= me) { 2013 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2014 } else { 2015 target_ulong mask; 2016 bool mask_in_32b = true; 2017 TCGv t1; 2018 2019 #if defined(TARGET_PPC64) 2020 mb += 32; 2021 me += 32; 2022 #endif 2023 mask = MASK(mb, me); 2024 2025 #if defined(TARGET_PPC64) 2026 if (mask > 0xffffffffu) { 2027 mask_in_32b = false; 2028 } 2029 #endif 2030 t1 = tcg_temp_new(); 2031 if (mask_in_32b) { 2032 TCGv_i32 t0 = tcg_temp_new_i32(); 2033 tcg_gen_trunc_tl_i32(t0, t_rs); 2034 tcg_gen_rotli_i32(t0, t0, sh); 2035 tcg_gen_extu_i32_tl(t1, t0); 2036 } else { 2037 #if defined(TARGET_PPC64) 2038 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2039 tcg_gen_rotli_i64(t1, t1, sh); 2040 #else 2041 g_assert_not_reached(); 2042 #endif 2043 } 2044 2045 tcg_gen_andi_tl(t1, t1, mask); 2046 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2047 tcg_gen_or_tl(t_ra, t_ra, t1); 2048 } 2049 if (unlikely(Rc(ctx->opcode) != 0)) { 2050 gen_set_Rc0(ctx, t_ra); 2051 } 2052 } 2053 2054 /* rlwinm & rlwinm. */ 2055 static void gen_rlwinm(DisasContext *ctx) 2056 { 2057 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2058 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2059 int sh = SH(ctx->opcode); 2060 int mb = MB(ctx->opcode); 2061 int me = ME(ctx->opcode); 2062 int len = me - mb + 1; 2063 int rsh = (32 - sh) & 31; 2064 2065 if (sh != 0 && len > 0 && me == (31 - sh)) { 2066 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2067 } else if (me == 31 && rsh + len <= 32) { 2068 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2069 } else { 2070 target_ulong mask; 2071 bool mask_in_32b = true; 2072 #if defined(TARGET_PPC64) 2073 mb += 32; 2074 me += 32; 2075 #endif 2076 mask = MASK(mb, me); 2077 #if defined(TARGET_PPC64) 2078 if (mask > 0xffffffffu) { 2079 mask_in_32b = false; 2080 } 2081 #endif 2082 if (mask_in_32b) { 2083 if (sh == 0) { 2084 tcg_gen_andi_tl(t_ra, t_rs, mask); 2085 } else { 2086 TCGv_i32 t0 = tcg_temp_new_i32(); 2087 tcg_gen_trunc_tl_i32(t0, t_rs); 2088 tcg_gen_rotli_i32(t0, t0, sh); 2089 tcg_gen_andi_i32(t0, t0, mask); 2090 tcg_gen_extu_i32_tl(t_ra, t0); 2091 } 2092 } else { 2093 #if defined(TARGET_PPC64) 2094 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2095 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2096 tcg_gen_andi_i64(t_ra, t_ra, mask); 2097 #else 2098 g_assert_not_reached(); 2099 #endif 2100 } 2101 } 2102 if (unlikely(Rc(ctx->opcode) != 0)) { 2103 gen_set_Rc0(ctx, t_ra); 2104 } 2105 } 2106 2107 /* rlwnm & rlwnm. */ 2108 static void gen_rlwnm(DisasContext *ctx) 2109 { 2110 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2111 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2112 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2113 uint32_t mb = MB(ctx->opcode); 2114 uint32_t me = ME(ctx->opcode); 2115 target_ulong mask; 2116 bool mask_in_32b = true; 2117 2118 #if defined(TARGET_PPC64) 2119 mb += 32; 2120 me += 32; 2121 #endif 2122 mask = MASK(mb, me); 2123 2124 #if defined(TARGET_PPC64) 2125 if (mask > 0xffffffffu) { 2126 mask_in_32b = false; 2127 } 2128 #endif 2129 if (mask_in_32b) { 2130 TCGv_i32 t0 = tcg_temp_new_i32(); 2131 TCGv_i32 t1 = tcg_temp_new_i32(); 2132 tcg_gen_trunc_tl_i32(t0, t_rb); 2133 tcg_gen_trunc_tl_i32(t1, t_rs); 2134 tcg_gen_andi_i32(t0, t0, 0x1f); 2135 tcg_gen_rotl_i32(t1, t1, t0); 2136 tcg_gen_extu_i32_tl(t_ra, t1); 2137 } else { 2138 #if defined(TARGET_PPC64) 2139 TCGv_i64 t0 = tcg_temp_new_i64(); 2140 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2141 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2142 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2143 #else 2144 g_assert_not_reached(); 2145 #endif 2146 } 2147 2148 tcg_gen_andi_tl(t_ra, t_ra, mask); 2149 2150 if (unlikely(Rc(ctx->opcode) != 0)) { 2151 gen_set_Rc0(ctx, t_ra); 2152 } 2153 } 2154 2155 #if defined(TARGET_PPC64) 2156 #define GEN_PPC64_R2(name, opc1, opc2) \ 2157 static void glue(gen_, name##0)(DisasContext *ctx) \ 2158 { \ 2159 gen_##name(ctx, 0); \ 2160 } \ 2161 \ 2162 static void glue(gen_, name##1)(DisasContext *ctx) \ 2163 { \ 2164 gen_##name(ctx, 1); \ 2165 } 2166 #define GEN_PPC64_R4(name, opc1, opc2) \ 2167 static void glue(gen_, name##0)(DisasContext *ctx) \ 2168 { \ 2169 gen_##name(ctx, 0, 0); \ 2170 } \ 2171 \ 2172 static void glue(gen_, name##1)(DisasContext *ctx) \ 2173 { \ 2174 gen_##name(ctx, 0, 1); \ 2175 } \ 2176 \ 2177 static void glue(gen_, name##2)(DisasContext *ctx) \ 2178 { \ 2179 gen_##name(ctx, 1, 0); \ 2180 } \ 2181 \ 2182 static void glue(gen_, name##3)(DisasContext *ctx) \ 2183 { \ 2184 gen_##name(ctx, 1, 1); \ 2185 } 2186 2187 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2188 { 2189 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2190 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2191 int len = me - mb + 1; 2192 int rsh = (64 - sh) & 63; 2193 2194 if (sh != 0 && len > 0 && me == (63 - sh)) { 2195 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2196 } else if (me == 63 && rsh + len <= 64) { 2197 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2198 } else { 2199 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2200 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2201 } 2202 if (unlikely(Rc(ctx->opcode) != 0)) { 2203 gen_set_Rc0(ctx, t_ra); 2204 } 2205 } 2206 2207 /* rldicl - rldicl. */ 2208 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2209 { 2210 uint32_t sh, mb; 2211 2212 sh = SH(ctx->opcode) | (shn << 5); 2213 mb = MB(ctx->opcode) | (mbn << 5); 2214 gen_rldinm(ctx, mb, 63, sh); 2215 } 2216 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2217 2218 /* rldicr - rldicr. */ 2219 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2220 { 2221 uint32_t sh, me; 2222 2223 sh = SH(ctx->opcode) | (shn << 5); 2224 me = MB(ctx->opcode) | (men << 5); 2225 gen_rldinm(ctx, 0, me, sh); 2226 } 2227 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2228 2229 /* rldic - rldic. */ 2230 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2231 { 2232 uint32_t sh, mb; 2233 2234 sh = SH(ctx->opcode) | (shn << 5); 2235 mb = MB(ctx->opcode) | (mbn << 5); 2236 gen_rldinm(ctx, mb, 63 - sh, sh); 2237 } 2238 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2239 2240 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2241 { 2242 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2243 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2244 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2245 TCGv t0; 2246 2247 t0 = tcg_temp_new(); 2248 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2249 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2250 2251 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2252 if (unlikely(Rc(ctx->opcode) != 0)) { 2253 gen_set_Rc0(ctx, t_ra); 2254 } 2255 } 2256 2257 /* rldcl - rldcl. */ 2258 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2259 { 2260 uint32_t mb; 2261 2262 mb = MB(ctx->opcode) | (mbn << 5); 2263 gen_rldnm(ctx, mb, 63); 2264 } 2265 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2266 2267 /* rldcr - rldcr. */ 2268 static inline void gen_rldcr(DisasContext *ctx, int men) 2269 { 2270 uint32_t me; 2271 2272 me = MB(ctx->opcode) | (men << 5); 2273 gen_rldnm(ctx, 0, me); 2274 } 2275 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2276 2277 /* rldimi - rldimi. */ 2278 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2279 { 2280 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2281 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2282 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2283 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2284 uint32_t me = 63 - sh; 2285 2286 if (mb <= me) { 2287 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2288 } else { 2289 target_ulong mask = MASK(mb, me); 2290 TCGv t1 = tcg_temp_new(); 2291 2292 tcg_gen_rotli_tl(t1, t_rs, sh); 2293 tcg_gen_andi_tl(t1, t1, mask); 2294 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2295 tcg_gen_or_tl(t_ra, t_ra, t1); 2296 } 2297 if (unlikely(Rc(ctx->opcode) != 0)) { 2298 gen_set_Rc0(ctx, t_ra); 2299 } 2300 } 2301 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2302 #endif 2303 2304 /*** Integer shift ***/ 2305 2306 /* slw & slw. */ 2307 static void gen_slw(DisasContext *ctx) 2308 { 2309 TCGv t0, t1; 2310 2311 t0 = tcg_temp_new(); 2312 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2313 #if defined(TARGET_PPC64) 2314 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2315 tcg_gen_sari_tl(t0, t0, 0x3f); 2316 #else 2317 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2318 tcg_gen_sari_tl(t0, t0, 0x1f); 2319 #endif 2320 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2321 t1 = tcg_temp_new(); 2322 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2323 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2324 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2325 if (unlikely(Rc(ctx->opcode) != 0)) { 2326 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2327 } 2328 } 2329 2330 /* sraw & sraw. */ 2331 static void gen_sraw(DisasContext *ctx) 2332 { 2333 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env, 2334 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2335 if (unlikely(Rc(ctx->opcode) != 0)) { 2336 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2337 } 2338 } 2339 2340 /* srawi & srawi. */ 2341 static void gen_srawi(DisasContext *ctx) 2342 { 2343 int sh = SH(ctx->opcode); 2344 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2345 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2346 if (sh == 0) { 2347 tcg_gen_ext32s_tl(dst, src); 2348 tcg_gen_movi_tl(cpu_ca, 0); 2349 if (is_isa300(ctx)) { 2350 tcg_gen_movi_tl(cpu_ca32, 0); 2351 } 2352 } else { 2353 TCGv t0; 2354 tcg_gen_ext32s_tl(dst, src); 2355 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2356 t0 = tcg_temp_new(); 2357 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2358 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2359 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2360 if (is_isa300(ctx)) { 2361 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2362 } 2363 tcg_gen_sari_tl(dst, dst, sh); 2364 } 2365 if (unlikely(Rc(ctx->opcode) != 0)) { 2366 gen_set_Rc0(ctx, dst); 2367 } 2368 } 2369 2370 /* srw & srw. */ 2371 static void gen_srw(DisasContext *ctx) 2372 { 2373 TCGv t0, t1; 2374 2375 t0 = tcg_temp_new(); 2376 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2377 #if defined(TARGET_PPC64) 2378 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2379 tcg_gen_sari_tl(t0, t0, 0x3f); 2380 #else 2381 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2382 tcg_gen_sari_tl(t0, t0, 0x1f); 2383 #endif 2384 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2385 tcg_gen_ext32u_tl(t0, t0); 2386 t1 = tcg_temp_new(); 2387 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2388 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2389 if (unlikely(Rc(ctx->opcode) != 0)) { 2390 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2391 } 2392 } 2393 2394 #if defined(TARGET_PPC64) 2395 /* sld & sld. */ 2396 static void gen_sld(DisasContext *ctx) 2397 { 2398 TCGv t0, t1; 2399 2400 t0 = tcg_temp_new(); 2401 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2402 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2403 tcg_gen_sari_tl(t0, t0, 0x3f); 2404 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2405 t1 = tcg_temp_new(); 2406 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2407 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2408 if (unlikely(Rc(ctx->opcode) != 0)) { 2409 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2410 } 2411 } 2412 2413 /* srad & srad. */ 2414 static void gen_srad(DisasContext *ctx) 2415 { 2416 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env, 2417 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2418 if (unlikely(Rc(ctx->opcode) != 0)) { 2419 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2420 } 2421 } 2422 /* sradi & sradi. */ 2423 static inline void gen_sradi(DisasContext *ctx, int n) 2424 { 2425 int sh = SH(ctx->opcode) + (n << 5); 2426 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2427 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2428 if (sh == 0) { 2429 tcg_gen_mov_tl(dst, src); 2430 tcg_gen_movi_tl(cpu_ca, 0); 2431 if (is_isa300(ctx)) { 2432 tcg_gen_movi_tl(cpu_ca32, 0); 2433 } 2434 } else { 2435 TCGv t0; 2436 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2437 t0 = tcg_temp_new(); 2438 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2439 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2440 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2441 if (is_isa300(ctx)) { 2442 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2443 } 2444 tcg_gen_sari_tl(dst, src, sh); 2445 } 2446 if (unlikely(Rc(ctx->opcode) != 0)) { 2447 gen_set_Rc0(ctx, dst); 2448 } 2449 } 2450 2451 static void gen_sradi0(DisasContext *ctx) 2452 { 2453 gen_sradi(ctx, 0); 2454 } 2455 2456 static void gen_sradi1(DisasContext *ctx) 2457 { 2458 gen_sradi(ctx, 1); 2459 } 2460 2461 /* extswsli & extswsli. */ 2462 static inline void gen_extswsli(DisasContext *ctx, int n) 2463 { 2464 int sh = SH(ctx->opcode) + (n << 5); 2465 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2466 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2467 2468 tcg_gen_ext32s_tl(dst, src); 2469 tcg_gen_shli_tl(dst, dst, sh); 2470 if (unlikely(Rc(ctx->opcode) != 0)) { 2471 gen_set_Rc0(ctx, dst); 2472 } 2473 } 2474 2475 static void gen_extswsli0(DisasContext *ctx) 2476 { 2477 gen_extswsli(ctx, 0); 2478 } 2479 2480 static void gen_extswsli1(DisasContext *ctx) 2481 { 2482 gen_extswsli(ctx, 1); 2483 } 2484 2485 /* srd & srd. */ 2486 static void gen_srd(DisasContext *ctx) 2487 { 2488 TCGv t0, t1; 2489 2490 t0 = tcg_temp_new(); 2491 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2492 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2493 tcg_gen_sari_tl(t0, t0, 0x3f); 2494 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2495 t1 = tcg_temp_new(); 2496 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2497 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2498 if (unlikely(Rc(ctx->opcode) != 0)) { 2499 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2500 } 2501 } 2502 #endif 2503 2504 /*** Addressing modes ***/ 2505 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2506 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2507 target_long maskl) 2508 { 2509 target_long simm = SIMM(ctx->opcode); 2510 2511 simm &= ~maskl; 2512 if (rA(ctx->opcode) == 0) { 2513 if (NARROW_MODE(ctx)) { 2514 simm = (uint32_t)simm; 2515 } 2516 tcg_gen_movi_tl(EA, simm); 2517 } else if (likely(simm != 0)) { 2518 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2519 if (NARROW_MODE(ctx)) { 2520 tcg_gen_ext32u_tl(EA, EA); 2521 } 2522 } else { 2523 if (NARROW_MODE(ctx)) { 2524 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2525 } else { 2526 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2527 } 2528 } 2529 } 2530 2531 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2532 { 2533 if (rA(ctx->opcode) == 0) { 2534 if (NARROW_MODE(ctx)) { 2535 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2536 } else { 2537 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2538 } 2539 } else { 2540 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2541 if (NARROW_MODE(ctx)) { 2542 tcg_gen_ext32u_tl(EA, EA); 2543 } 2544 } 2545 } 2546 2547 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2548 { 2549 if (rA(ctx->opcode) == 0) { 2550 tcg_gen_movi_tl(EA, 0); 2551 } else if (NARROW_MODE(ctx)) { 2552 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2553 } else { 2554 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2555 } 2556 } 2557 2558 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2559 target_long val) 2560 { 2561 tcg_gen_addi_tl(ret, arg1, val); 2562 if (NARROW_MODE(ctx)) { 2563 tcg_gen_ext32u_tl(ret, ret); 2564 } 2565 } 2566 2567 static inline void gen_align_no_le(DisasContext *ctx) 2568 { 2569 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2570 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2571 } 2572 2573 /* EA <- {(ra == 0) ? 0 : GPR[ra]} + displ */ 2574 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 2575 { 2576 TCGv ea = tcg_temp_new(); 2577 if (ra) { 2578 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 2579 } else { 2580 tcg_gen_mov_tl(ea, displ); 2581 } 2582 if (NARROW_MODE(ctx)) { 2583 tcg_gen_ext32u_tl(ea, ea); 2584 } 2585 return ea; 2586 } 2587 2588 #if defined(TARGET_PPC64) 2589 /* EA <- (ra == 0) ? 0 : GPR[ra] */ 2590 static TCGv do_ea_calc_ra(DisasContext *ctx, int ra) 2591 { 2592 TCGv EA = tcg_temp_new(); 2593 if (!ra) { 2594 tcg_gen_movi_tl(EA, 0); 2595 } else if (NARROW_MODE(ctx)) { 2596 tcg_gen_ext32u_tl(EA, cpu_gpr[ra]); 2597 } else { 2598 tcg_gen_mov_tl(EA, cpu_gpr[ra]); 2599 } 2600 return EA; 2601 } 2602 #endif 2603 2604 /*** Integer load ***/ 2605 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2606 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2607 2608 #define GEN_QEMU_LOAD_TL(ldop, op) \ 2609 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2610 TCGv val, \ 2611 TCGv addr) \ 2612 { \ 2613 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2614 } 2615 2616 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2617 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2618 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2619 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2620 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2621 2622 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2623 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2624 2625 #define GEN_QEMU_LOAD_64(ldop, op) \ 2626 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2627 TCGv_i64 val, \ 2628 TCGv addr) \ 2629 { \ 2630 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2631 } 2632 2633 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2634 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2635 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2636 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2637 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 2638 2639 #if defined(TARGET_PPC64) 2640 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 2641 #endif 2642 2643 #define GEN_QEMU_STORE_TL(stop, op) \ 2644 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2645 TCGv val, \ 2646 TCGv addr) \ 2647 { \ 2648 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2649 } 2650 2651 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 2652 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2653 #endif 2654 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2655 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2656 2657 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2658 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2659 2660 #define GEN_QEMU_STORE_64(stop, op) \ 2661 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2662 TCGv_i64 val, \ 2663 TCGv addr) \ 2664 { \ 2665 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2666 } 2667 2668 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2669 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2670 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2671 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 2672 2673 #if defined(TARGET_PPC64) 2674 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 2675 #endif 2676 2677 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2678 static void glue(gen_, name##x)(DisasContext *ctx) \ 2679 { \ 2680 TCGv EA; \ 2681 chk(ctx); \ 2682 gen_set_access_type(ctx, ACCESS_INT); \ 2683 EA = tcg_temp_new(); \ 2684 gen_addr_reg_index(ctx, EA); \ 2685 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2686 } 2687 2688 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2689 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2690 2691 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2692 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2693 2694 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 2695 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2696 { \ 2697 TCGv EA; \ 2698 CHK_SV(ctx); \ 2699 gen_set_access_type(ctx, ACCESS_INT); \ 2700 EA = tcg_temp_new(); \ 2701 gen_addr_reg_index(ctx, EA); \ 2702 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 2703 } 2704 2705 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 2706 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 2707 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 2708 #if defined(TARGET_PPC64) 2709 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 2710 #endif 2711 2712 #if defined(TARGET_PPC64) 2713 /* CI load/store variants */ 2714 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2715 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2716 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2717 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2718 #endif 2719 2720 /*** Integer store ***/ 2721 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2722 static void glue(gen_, name##x)(DisasContext *ctx) \ 2723 { \ 2724 TCGv EA; \ 2725 chk(ctx); \ 2726 gen_set_access_type(ctx, ACCESS_INT); \ 2727 EA = tcg_temp_new(); \ 2728 gen_addr_reg_index(ctx, EA); \ 2729 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2730 } 2731 #define GEN_STX(name, stop, opc2, opc3, type) \ 2732 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2733 2734 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2735 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2736 2737 #define GEN_STEPX(name, stop, opc2, opc3) \ 2738 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2739 { \ 2740 TCGv EA; \ 2741 CHK_SV(ctx); \ 2742 gen_set_access_type(ctx, ACCESS_INT); \ 2743 EA = tcg_temp_new(); \ 2744 gen_addr_reg_index(ctx, EA); \ 2745 tcg_gen_qemu_st_tl( \ 2746 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 2747 } 2748 2749 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 2750 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 2751 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 2752 #if defined(TARGET_PPC64) 2753 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 2754 #endif 2755 2756 #if defined(TARGET_PPC64) 2757 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2758 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2759 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2760 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2761 #endif 2762 /*** Integer load and store with byte reverse ***/ 2763 2764 /* lhbrx */ 2765 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2766 2767 /* lwbrx */ 2768 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2769 2770 #if defined(TARGET_PPC64) 2771 /* ldbrx */ 2772 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2773 /* stdbrx */ 2774 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2775 #endif /* TARGET_PPC64 */ 2776 2777 /* sthbrx */ 2778 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2779 /* stwbrx */ 2780 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2781 2782 /*** Integer load and store multiple ***/ 2783 2784 /* lmw */ 2785 static void gen_lmw(DisasContext *ctx) 2786 { 2787 TCGv t0; 2788 TCGv_i32 t1; 2789 2790 if (ctx->le_mode) { 2791 gen_align_no_le(ctx); 2792 return; 2793 } 2794 gen_set_access_type(ctx, ACCESS_INT); 2795 t0 = tcg_temp_new(); 2796 t1 = tcg_constant_i32(rD(ctx->opcode)); 2797 gen_addr_imm_index(ctx, t0, 0); 2798 gen_helper_lmw(tcg_env, t0, t1); 2799 } 2800 2801 /* stmw */ 2802 static void gen_stmw(DisasContext *ctx) 2803 { 2804 TCGv t0; 2805 TCGv_i32 t1; 2806 2807 if (ctx->le_mode) { 2808 gen_align_no_le(ctx); 2809 return; 2810 } 2811 gen_set_access_type(ctx, ACCESS_INT); 2812 t0 = tcg_temp_new(); 2813 t1 = tcg_constant_i32(rS(ctx->opcode)); 2814 gen_addr_imm_index(ctx, t0, 0); 2815 gen_helper_stmw(tcg_env, t0, t1); 2816 } 2817 2818 /*** Integer load and store strings ***/ 2819 2820 /* lswi */ 2821 /* 2822 * PowerPC32 specification says we must generate an exception if rA is 2823 * in the range of registers to be loaded. In an other hand, IBM says 2824 * this is valid, but rA won't be loaded. For now, I'll follow the 2825 * spec... 2826 */ 2827 static void gen_lswi(DisasContext *ctx) 2828 { 2829 TCGv t0; 2830 TCGv_i32 t1, t2; 2831 int nb = NB(ctx->opcode); 2832 int start = rD(ctx->opcode); 2833 int ra = rA(ctx->opcode); 2834 int nr; 2835 2836 if (ctx->le_mode) { 2837 gen_align_no_le(ctx); 2838 return; 2839 } 2840 if (nb == 0) { 2841 nb = 32; 2842 } 2843 nr = DIV_ROUND_UP(nb, 4); 2844 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2845 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2846 return; 2847 } 2848 gen_set_access_type(ctx, ACCESS_INT); 2849 t0 = tcg_temp_new(); 2850 gen_addr_register(ctx, t0); 2851 t1 = tcg_constant_i32(nb); 2852 t2 = tcg_constant_i32(start); 2853 gen_helper_lsw(tcg_env, t0, t1, t2); 2854 } 2855 2856 /* lswx */ 2857 static void gen_lswx(DisasContext *ctx) 2858 { 2859 TCGv t0; 2860 TCGv_i32 t1, t2, t3; 2861 2862 if (ctx->le_mode) { 2863 gen_align_no_le(ctx); 2864 return; 2865 } 2866 gen_set_access_type(ctx, ACCESS_INT); 2867 t0 = tcg_temp_new(); 2868 gen_addr_reg_index(ctx, t0); 2869 t1 = tcg_constant_i32(rD(ctx->opcode)); 2870 t2 = tcg_constant_i32(rA(ctx->opcode)); 2871 t3 = tcg_constant_i32(rB(ctx->opcode)); 2872 gen_helper_lswx(tcg_env, t0, t1, t2, t3); 2873 } 2874 2875 /* stswi */ 2876 static void gen_stswi(DisasContext *ctx) 2877 { 2878 TCGv t0; 2879 TCGv_i32 t1, t2; 2880 int nb = NB(ctx->opcode); 2881 2882 if (ctx->le_mode) { 2883 gen_align_no_le(ctx); 2884 return; 2885 } 2886 gen_set_access_type(ctx, ACCESS_INT); 2887 t0 = tcg_temp_new(); 2888 gen_addr_register(ctx, t0); 2889 if (nb == 0) { 2890 nb = 32; 2891 } 2892 t1 = tcg_constant_i32(nb); 2893 t2 = tcg_constant_i32(rS(ctx->opcode)); 2894 gen_helper_stsw(tcg_env, t0, t1, t2); 2895 } 2896 2897 /* stswx */ 2898 static void gen_stswx(DisasContext *ctx) 2899 { 2900 TCGv t0; 2901 TCGv_i32 t1, t2; 2902 2903 if (ctx->le_mode) { 2904 gen_align_no_le(ctx); 2905 return; 2906 } 2907 gen_set_access_type(ctx, ACCESS_INT); 2908 t0 = tcg_temp_new(); 2909 gen_addr_reg_index(ctx, t0); 2910 t1 = tcg_temp_new_i32(); 2911 tcg_gen_trunc_tl_i32(t1, cpu_xer); 2912 tcg_gen_andi_i32(t1, t1, 0x7F); 2913 t2 = tcg_constant_i32(rS(ctx->opcode)); 2914 gen_helper_stsw(tcg_env, t0, t1, t2); 2915 } 2916 2917 #if !defined(CONFIG_USER_ONLY) 2918 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 2919 { 2920 TCGv_i32 t; 2921 TCGLabel *l; 2922 2923 if (!ctx->lazy_tlb_flush) { 2924 return; 2925 } 2926 l = gen_new_label(); 2927 t = tcg_temp_new_i32(); 2928 tcg_gen_ld_i32(t, tcg_env, offsetof(CPUPPCState, tlb_need_flush)); 2929 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 2930 if (global) { 2931 gen_helper_check_tlb_flush_global(tcg_env); 2932 } else { 2933 gen_helper_check_tlb_flush_local(tcg_env); 2934 } 2935 gen_set_label(l); 2936 if (global) { 2937 /* 2938 * Global TLB flush uses async-work which must run before the 2939 * next instruction, so this must be the last in the TB. 2940 */ 2941 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 2942 } 2943 } 2944 #else 2945 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 2946 #endif 2947 2948 /* isync */ 2949 static void gen_isync(DisasContext *ctx) 2950 { 2951 /* 2952 * We need to check for a pending TLB flush. This can only happen in 2953 * kernel mode however so check MSR_PR 2954 */ 2955 if (!ctx->pr) { 2956 gen_check_tlb_flush(ctx, false); 2957 } 2958 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 2959 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 2960 } 2961 2962 static void gen_load_locked(DisasContext *ctx, MemOp memop) 2963 { 2964 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 2965 TCGv t0 = tcg_temp_new(); 2966 2967 gen_set_access_type(ctx, ACCESS_RES); 2968 gen_addr_reg_index(ctx, t0); 2969 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN); 2970 tcg_gen_mov_tl(cpu_reserve, t0); 2971 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 2972 tcg_gen_mov_tl(cpu_reserve_val, gpr); 2973 } 2974 2975 #define LARX(name, memop) \ 2976 static void gen_##name(DisasContext *ctx) \ 2977 { \ 2978 gen_load_locked(ctx, memop); \ 2979 } 2980 2981 /* lwarx */ 2982 LARX(lbarx, MO_UB) 2983 LARX(lharx, MO_UW) 2984 LARX(lwarx, MO_UL) 2985 2986 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 2987 TCGv EA, TCGCond cond, int addend) 2988 { 2989 TCGv t = tcg_temp_new(); 2990 TCGv t2 = tcg_temp_new(); 2991 TCGv u = tcg_temp_new(); 2992 2993 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 2994 tcg_gen_addi_tl(t2, EA, memop_size(memop)); 2995 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 2996 tcg_gen_addi_tl(u, t, addend); 2997 2998 /* E.g. for fetch and increment bounded... */ 2999 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3000 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3001 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3002 3003 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3004 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, 3005 tcg_constant_tl(1 << (memop_size(memop) * 8 - 1))); 3006 } 3007 3008 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3009 { 3010 uint32_t gpr_FC = FC(ctx->opcode); 3011 TCGv EA = tcg_temp_new(); 3012 int rt = rD(ctx->opcode); 3013 bool need_serial; 3014 TCGv src, dst; 3015 3016 gen_addr_register(ctx, EA); 3017 dst = cpu_gpr[rt]; 3018 src = cpu_gpr[(rt + 1) & 31]; 3019 3020 need_serial = false; 3021 memop |= MO_ALIGN; 3022 switch (gpr_FC) { 3023 case 0: /* Fetch and add */ 3024 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3025 break; 3026 case 1: /* Fetch and xor */ 3027 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3028 break; 3029 case 2: /* Fetch and or */ 3030 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3031 break; 3032 case 3: /* Fetch and 'and' */ 3033 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3034 break; 3035 case 4: /* Fetch and max unsigned */ 3036 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3037 break; 3038 case 5: /* Fetch and max signed */ 3039 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3040 break; 3041 case 6: /* Fetch and min unsigned */ 3042 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3043 break; 3044 case 7: /* Fetch and min signed */ 3045 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3046 break; 3047 case 8: /* Swap */ 3048 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3049 break; 3050 3051 case 16: /* Compare and swap not equal */ 3052 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3053 need_serial = true; 3054 } else { 3055 TCGv t0 = tcg_temp_new(); 3056 TCGv t1 = tcg_temp_new(); 3057 3058 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3059 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3060 tcg_gen_mov_tl(t1, src); 3061 } else { 3062 tcg_gen_ext32u_tl(t1, src); 3063 } 3064 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3065 cpu_gpr[(rt + 2) & 31], t0); 3066 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3067 tcg_gen_mov_tl(dst, t0); 3068 } 3069 break; 3070 3071 case 24: /* Fetch and increment bounded */ 3072 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3073 need_serial = true; 3074 } else { 3075 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3076 } 3077 break; 3078 case 25: /* Fetch and increment equal */ 3079 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3080 need_serial = true; 3081 } else { 3082 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3083 } 3084 break; 3085 case 28: /* Fetch and decrement bounded */ 3086 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3087 need_serial = true; 3088 } else { 3089 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3090 } 3091 break; 3092 3093 default: 3094 /* invoke data storage error handler */ 3095 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3096 } 3097 3098 if (need_serial) { 3099 /* Restart with exclusive lock. */ 3100 gen_helper_exit_atomic(tcg_env); 3101 ctx->base.is_jmp = DISAS_NORETURN; 3102 } 3103 } 3104 3105 static void gen_lwat(DisasContext *ctx) 3106 { 3107 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3108 } 3109 3110 #ifdef TARGET_PPC64 3111 static void gen_ldat(DisasContext *ctx) 3112 { 3113 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3114 } 3115 #endif 3116 3117 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3118 { 3119 uint32_t gpr_FC = FC(ctx->opcode); 3120 TCGv EA = tcg_temp_new(); 3121 TCGv src, discard; 3122 3123 gen_addr_register(ctx, EA); 3124 src = cpu_gpr[rD(ctx->opcode)]; 3125 discard = tcg_temp_new(); 3126 3127 memop |= MO_ALIGN; 3128 switch (gpr_FC) { 3129 case 0: /* add and Store */ 3130 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3131 break; 3132 case 1: /* xor and Store */ 3133 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3134 break; 3135 case 2: /* Or and Store */ 3136 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3137 break; 3138 case 3: /* 'and' and Store */ 3139 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3140 break; 3141 case 4: /* Store max unsigned */ 3142 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3143 break; 3144 case 5: /* Store max signed */ 3145 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3146 break; 3147 case 6: /* Store min unsigned */ 3148 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3149 break; 3150 case 7: /* Store min signed */ 3151 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3152 break; 3153 case 24: /* Store twin */ 3154 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3155 /* Restart with exclusive lock. */ 3156 gen_helper_exit_atomic(tcg_env); 3157 ctx->base.is_jmp = DISAS_NORETURN; 3158 } else { 3159 TCGv t = tcg_temp_new(); 3160 TCGv t2 = tcg_temp_new(); 3161 TCGv s = tcg_temp_new(); 3162 TCGv s2 = tcg_temp_new(); 3163 TCGv ea_plus_s = tcg_temp_new(); 3164 3165 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3166 tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop)); 3167 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3168 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3169 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3170 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3171 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3172 } 3173 break; 3174 default: 3175 /* invoke data storage error handler */ 3176 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3177 } 3178 } 3179 3180 static void gen_stwat(DisasContext *ctx) 3181 { 3182 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3183 } 3184 3185 #ifdef TARGET_PPC64 3186 static void gen_stdat(DisasContext *ctx) 3187 { 3188 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3189 } 3190 #endif 3191 3192 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3193 { 3194 TCGLabel *lfail; 3195 TCGv EA; 3196 TCGv cr0; 3197 TCGv t0; 3198 int rs = rS(ctx->opcode); 3199 3200 lfail = gen_new_label(); 3201 EA = tcg_temp_new(); 3202 cr0 = tcg_temp_new(); 3203 t0 = tcg_temp_new(); 3204 3205 tcg_gen_mov_tl(cr0, cpu_so); 3206 gen_set_access_type(ctx, ACCESS_RES); 3207 gen_addr_reg_index(ctx, EA); 3208 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3209 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 3210 3211 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3212 cpu_gpr[rs], ctx->mem_idx, 3213 DEF_MEMOP(memop) | MO_ALIGN); 3214 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3215 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3216 tcg_gen_or_tl(cr0, cr0, t0); 3217 3218 gen_set_label(lfail); 3219 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3220 tcg_gen_movi_tl(cpu_reserve, -1); 3221 } 3222 3223 #define STCX(name, memop) \ 3224 static void gen_##name(DisasContext *ctx) \ 3225 { \ 3226 gen_conditional_store(ctx, memop); \ 3227 } 3228 3229 STCX(stbcx_, MO_UB) 3230 STCX(sthcx_, MO_UW) 3231 STCX(stwcx_, MO_UL) 3232 3233 #if defined(TARGET_PPC64) 3234 /* ldarx */ 3235 LARX(ldarx, MO_UQ) 3236 /* stdcx. */ 3237 STCX(stdcx_, MO_UQ) 3238 3239 /* lqarx */ 3240 static void gen_lqarx(DisasContext *ctx) 3241 { 3242 int rd = rD(ctx->opcode); 3243 TCGv EA, hi, lo; 3244 TCGv_i128 t16; 3245 3246 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3247 (rd == rB(ctx->opcode)))) { 3248 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3249 return; 3250 } 3251 3252 gen_set_access_type(ctx, ACCESS_RES); 3253 EA = tcg_temp_new(); 3254 gen_addr_reg_index(ctx, EA); 3255 3256 /* Note that the low part is always in RD+1, even in LE mode. */ 3257 lo = cpu_gpr[rd + 1]; 3258 hi = cpu_gpr[rd]; 3259 3260 t16 = tcg_temp_new_i128(); 3261 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3262 tcg_gen_extr_i128_i64(lo, hi, t16); 3263 3264 tcg_gen_mov_tl(cpu_reserve, EA); 3265 tcg_gen_movi_tl(cpu_reserve_length, 16); 3266 tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val)); 3267 tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2)); 3268 } 3269 3270 /* stqcx. */ 3271 static void gen_stqcx_(DisasContext *ctx) 3272 { 3273 TCGLabel *lfail; 3274 TCGv EA, t0, t1; 3275 TCGv cr0; 3276 TCGv_i128 cmp, val; 3277 int rs = rS(ctx->opcode); 3278 3279 if (unlikely(rs & 1)) { 3280 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3281 return; 3282 } 3283 3284 lfail = gen_new_label(); 3285 EA = tcg_temp_new(); 3286 cr0 = tcg_temp_new(); 3287 3288 tcg_gen_mov_tl(cr0, cpu_so); 3289 gen_set_access_type(ctx, ACCESS_RES); 3290 gen_addr_reg_index(ctx, EA); 3291 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3292 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 3293 3294 cmp = tcg_temp_new_i128(); 3295 val = tcg_temp_new_i128(); 3296 3297 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3298 3299 /* Note that the low part is always in RS+1, even in LE mode. */ 3300 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3301 3302 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3303 DEF_MEMOP(MO_128 | MO_ALIGN)); 3304 3305 t0 = tcg_temp_new(); 3306 t1 = tcg_temp_new(); 3307 tcg_gen_extr_i128_i64(t1, t0, val); 3308 3309 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3310 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3311 tcg_gen_or_tl(t0, t0, t1); 3312 3313 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3314 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3315 tcg_gen_or_tl(cr0, cr0, t0); 3316 3317 gen_set_label(lfail); 3318 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3319 tcg_gen_movi_tl(cpu_reserve, -1); 3320 } 3321 #endif /* defined(TARGET_PPC64) */ 3322 3323 /* wait */ 3324 static void gen_wait(DisasContext *ctx) 3325 { 3326 uint32_t wc; 3327 3328 if (ctx->insns_flags & PPC_WAIT) { 3329 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3330 3331 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3332 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3333 wc = WC(ctx->opcode); 3334 } else { 3335 wc = 0; 3336 } 3337 3338 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3339 /* v3.0 defines a new 'wait' encoding. */ 3340 wc = WC(ctx->opcode); 3341 if (ctx->insns_flags2 & PPC2_ISA310) { 3342 uint32_t pl = PL(ctx->opcode); 3343 3344 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3345 if (wc == 3) { 3346 gen_invalid(ctx); 3347 return; 3348 } 3349 3350 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3351 if (pl > 0 && wc != 2) { 3352 gen_invalid(ctx); 3353 return; 3354 } 3355 3356 } else { /* ISA300 */ 3357 /* WC 1-3 are reserved */ 3358 if (wc > 0) { 3359 gen_invalid(ctx); 3360 return; 3361 } 3362 } 3363 3364 } else { 3365 warn_report("wait instruction decoded with wrong ISA flags."); 3366 gen_invalid(ctx); 3367 return; 3368 } 3369 3370 /* 3371 * wait without WC field or with WC=0 waits for an exception / interrupt 3372 * to occur. 3373 */ 3374 if (wc == 0) { 3375 TCGv_i32 t0 = tcg_constant_i32(1); 3376 tcg_gen_st_i32(t0, tcg_env, 3377 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3378 /* Stop translation, as the CPU is supposed to sleep from now */ 3379 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3380 } 3381 3382 /* 3383 * Other wait types must not just wait until an exception occurs because 3384 * ignoring their other wake-up conditions could cause a hang. 3385 * 3386 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3387 * no-ops. 3388 * 3389 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 3390 * 3391 * wc=2 waits for an implementation-specific condition, such could be 3392 * always true, so it can be implemented as a no-op. 3393 * 3394 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 3395 * 3396 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 3397 * Reservation-loss may have implementation-specific conditions, so it 3398 * can be implemented as a no-op. 3399 * 3400 * wc=2 waits for an exception or an amount of time to pass. This 3401 * amount is implementation-specific so it can be implemented as a 3402 * no-op. 3403 * 3404 * ISA v3.1 allows for execution to resume "in the rare case of 3405 * an implementation-dependent event", so in any case software must 3406 * not depend on the architected resumption condition to become 3407 * true, so no-op implementations should be architecturally correct 3408 * (if suboptimal). 3409 */ 3410 } 3411 3412 #if defined(TARGET_PPC64) 3413 static void gen_doze(DisasContext *ctx) 3414 { 3415 #if defined(CONFIG_USER_ONLY) 3416 GEN_PRIV(ctx); 3417 #else 3418 TCGv_i32 t; 3419 3420 CHK_HV(ctx); 3421 translator_io_start(&ctx->base); 3422 t = tcg_constant_i32(PPC_PM_DOZE); 3423 gen_helper_pminsn(tcg_env, t); 3424 /* Stop translation, as the CPU is supposed to sleep from now */ 3425 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3426 #endif /* defined(CONFIG_USER_ONLY) */ 3427 } 3428 3429 static void gen_nap(DisasContext *ctx) 3430 { 3431 #if defined(CONFIG_USER_ONLY) 3432 GEN_PRIV(ctx); 3433 #else 3434 TCGv_i32 t; 3435 3436 CHK_HV(ctx); 3437 translator_io_start(&ctx->base); 3438 t = tcg_constant_i32(PPC_PM_NAP); 3439 gen_helper_pminsn(tcg_env, t); 3440 /* Stop translation, as the CPU is supposed to sleep from now */ 3441 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3442 #endif /* defined(CONFIG_USER_ONLY) */ 3443 } 3444 3445 static void gen_stop(DisasContext *ctx) 3446 { 3447 #if defined(CONFIG_USER_ONLY) 3448 GEN_PRIV(ctx); 3449 #else 3450 TCGv_i32 t; 3451 3452 CHK_HV(ctx); 3453 translator_io_start(&ctx->base); 3454 t = tcg_constant_i32(PPC_PM_STOP); 3455 gen_helper_pminsn(tcg_env, t); 3456 /* Stop translation, as the CPU is supposed to sleep from now */ 3457 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3458 #endif /* defined(CONFIG_USER_ONLY) */ 3459 } 3460 3461 static void gen_sleep(DisasContext *ctx) 3462 { 3463 #if defined(CONFIG_USER_ONLY) 3464 GEN_PRIV(ctx); 3465 #else 3466 TCGv_i32 t; 3467 3468 CHK_HV(ctx); 3469 translator_io_start(&ctx->base); 3470 t = tcg_constant_i32(PPC_PM_SLEEP); 3471 gen_helper_pminsn(tcg_env, t); 3472 /* Stop translation, as the CPU is supposed to sleep from now */ 3473 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3474 #endif /* defined(CONFIG_USER_ONLY) */ 3475 } 3476 3477 static void gen_rvwinkle(DisasContext *ctx) 3478 { 3479 #if defined(CONFIG_USER_ONLY) 3480 GEN_PRIV(ctx); 3481 #else 3482 TCGv_i32 t; 3483 3484 CHK_HV(ctx); 3485 translator_io_start(&ctx->base); 3486 t = tcg_constant_i32(PPC_PM_RVWINKLE); 3487 gen_helper_pminsn(tcg_env, t); 3488 /* Stop translation, as the CPU is supposed to sleep from now */ 3489 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3490 #endif /* defined(CONFIG_USER_ONLY) */ 3491 } 3492 3493 static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv value) 3494 { 3495 TCGv_ptr tmp = tcg_temp_new_ptr(); 3496 3497 /* add base and offset to get address of bhrb entry */ 3498 tcg_gen_add_ptr(tmp, base, (TCGv_ptr)offset); 3499 3500 /* store value into bhrb at bhrb_offset */ 3501 tcg_gen_st_i64(value, tmp, 0); 3502 3503 /* add 8 to current bhrb_offset */ 3504 tcg_gen_addi_tl(offset, offset, 8); 3505 3506 /* apply offset mask */ 3507 tcg_gen_and_tl(offset, offset, mask); 3508 3509 return offset; 3510 } 3511 #endif /* #if defined(TARGET_PPC64) */ 3512 3513 static inline void gen_update_branch_history(DisasContext *ctx, 3514 target_ulong nip, 3515 TCGv target, 3516 target_long inst_type) 3517 { 3518 #if defined(TARGET_PPC64) 3519 TCGv_ptr base; 3520 TCGv tmp; 3521 TCGv offset; 3522 TCGv mask; 3523 TCGLabel *no_update; 3524 3525 if (ctx->has_cfar) { 3526 tcg_gen_movi_tl(cpu_cfar, nip); 3527 } 3528 3529 if (!ctx->has_bhrb || 3530 !ctx->bhrb_enable || 3531 inst_type == BHRB_TYPE_NORECORD) { 3532 return; 3533 } 3534 3535 tmp = tcg_temp_new(); 3536 no_update = gen_new_label(); 3537 3538 /* check for bhrb filtering */ 3539 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter)); 3540 tcg_gen_andi_tl(tmp, tmp, inst_type); 3541 tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, no_update); 3542 3543 base = tcg_temp_new_ptr(); 3544 offset = tcg_temp_new(); 3545 mask = tcg_temp_new(); 3546 3547 /* load bhrb base address */ 3548 tcg_gen_ld_ptr(base, tcg_env, offsetof(CPUPPCState, bhrb_base)); 3549 3550 /* load current bhrb_offset */ 3551 tcg_gen_ld_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset)); 3552 3553 /* load a BHRB offset mask */ 3554 tcg_gen_ld_tl(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask)); 3555 3556 offset = gen_write_bhrb(base, offset, mask, tcg_constant_i64(nip)); 3557 3558 /* Also record the target address for XL-Form branches */ 3559 if (inst_type & BHRB_TYPE_XL_FORM) { 3560 3561 /* Set the 'T' bit for target entries */ 3562 tcg_gen_ori_tl(tmp, target, 0x2); 3563 3564 offset = gen_write_bhrb(base, offset, mask, tmp); 3565 } 3566 3567 /* save updated bhrb_offset for next time */ 3568 tcg_gen_st_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset)); 3569 3570 gen_set_label(no_update); 3571 #endif 3572 } 3573 3574 #if defined(TARGET_PPC64) 3575 static void pmu_count_insns(DisasContext *ctx) 3576 { 3577 /* 3578 * Do not bother calling the helper if the PMU isn't counting 3579 * instructions. 3580 */ 3581 if (!ctx->pmu_insn_cnt) { 3582 return; 3583 } 3584 3585 #if !defined(CONFIG_USER_ONLY) 3586 TCGLabel *l; 3587 TCGv t0; 3588 3589 /* 3590 * The PMU insns_inc() helper stops the internal PMU timer if a 3591 * counter overflows happens. In that case, if the guest is 3592 * running with icount and we do not handle it beforehand, 3593 * the helper can trigger a 'bad icount read'. 3594 */ 3595 translator_io_start(&ctx->base); 3596 3597 /* Avoid helper calls when only PMC5-6 are enabled. */ 3598 if (!ctx->pmc_other) { 3599 l = gen_new_label(); 3600 t0 = tcg_temp_new(); 3601 3602 gen_load_spr(t0, SPR_POWER_PMC5); 3603 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 3604 gen_store_spr(SPR_POWER_PMC5, t0); 3605 /* Check for overflow, if it's enabled */ 3606 if (ctx->mmcr0_pmcjce) { 3607 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 3608 gen_helper_handle_pmc5_overflow(tcg_env); 3609 } 3610 3611 gen_set_label(l); 3612 } else { 3613 gen_helper_insns_inc(tcg_env, tcg_constant_i32(ctx->base.num_insns)); 3614 } 3615 #else 3616 /* 3617 * User mode can read (but not write) PMC5 and start/stop 3618 * the PMU via MMCR0_FC. In this case just increment 3619 * PMC5 with base.num_insns. 3620 */ 3621 TCGv t0 = tcg_temp_new(); 3622 3623 gen_load_spr(t0, SPR_POWER_PMC5); 3624 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 3625 gen_store_spr(SPR_POWER_PMC5, t0); 3626 #endif /* #if !defined(CONFIG_USER_ONLY) */ 3627 } 3628 #else 3629 static void pmu_count_insns(DisasContext *ctx) 3630 { 3631 return; 3632 } 3633 #endif /* #if defined(TARGET_PPC64) */ 3634 3635 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3636 { 3637 if (unlikely(ctx->singlestep_enabled)) { 3638 return false; 3639 } 3640 return translator_use_goto_tb(&ctx->base, dest); 3641 } 3642 3643 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 3644 { 3645 if (unlikely(ctx->singlestep_enabled)) { 3646 gen_debug_exception(ctx, false); 3647 } else { 3648 /* 3649 * tcg_gen_lookup_and_goto_ptr will exit the TB if 3650 * CF_NO_GOTO_PTR is set. Count insns now. 3651 */ 3652 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 3653 pmu_count_insns(ctx); 3654 } 3655 3656 tcg_gen_lookup_and_goto_ptr(); 3657 } 3658 } 3659 3660 /*** Branch ***/ 3661 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3662 { 3663 if (NARROW_MODE(ctx)) { 3664 dest = (uint32_t) dest; 3665 } 3666 if (use_goto_tb(ctx, dest)) { 3667 pmu_count_insns(ctx); 3668 tcg_gen_goto_tb(n); 3669 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3670 tcg_gen_exit_tb(ctx->base.tb, n); 3671 } else { 3672 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3673 gen_lookup_and_goto_ptr(ctx); 3674 } 3675 } 3676 3677 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3678 { 3679 if (NARROW_MODE(ctx)) { 3680 nip = (uint32_t)nip; 3681 } 3682 tcg_gen_movi_tl(cpu_lr, nip); 3683 } 3684 3685 /* b ba bl bla */ 3686 static void gen_b(DisasContext *ctx) 3687 { 3688 target_ulong li, target; 3689 3690 /* sign extend LI */ 3691 li = LI(ctx->opcode); 3692 li = (li ^ 0x02000000) - 0x02000000; 3693 if (likely(AA(ctx->opcode) == 0)) { 3694 target = ctx->cia + li; 3695 } else { 3696 target = li; 3697 } 3698 if (LK(ctx->opcode)) { 3699 gen_setlr(ctx, ctx->base.pc_next); 3700 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL); 3701 } else { 3702 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER); 3703 } 3704 gen_goto_tb(ctx, 0, target); 3705 ctx->base.is_jmp = DISAS_NORETURN; 3706 } 3707 3708 #define BCOND_IM 0 3709 #define BCOND_LR 1 3710 #define BCOND_CTR 2 3711 #define BCOND_TAR 3 3712 3713 static void gen_bcond(DisasContext *ctx, int type) 3714 { 3715 uint32_t bo = BO(ctx->opcode); 3716 TCGLabel *l1; 3717 TCGv target; 3718 target_long bhrb_type = BHRB_TYPE_OTHER; 3719 3720 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3721 target = tcg_temp_new(); 3722 if (type == BCOND_CTR) { 3723 tcg_gen_mov_tl(target, cpu_ctr); 3724 } else if (type == BCOND_TAR) { 3725 gen_load_spr(target, SPR_TAR); 3726 } else { 3727 tcg_gen_mov_tl(target, cpu_lr); 3728 } 3729 if (!LK(ctx->opcode)) { 3730 bhrb_type |= BHRB_TYPE_INDIRECT; 3731 } 3732 bhrb_type |= BHRB_TYPE_XL_FORM; 3733 } else { 3734 target = NULL; 3735 } 3736 if (LK(ctx->opcode)) { 3737 gen_setlr(ctx, ctx->base.pc_next); 3738 bhrb_type |= BHRB_TYPE_CALL; 3739 } 3740 l1 = gen_new_label(); 3741 if ((bo & 0x4) == 0) { 3742 /* Decrement and test CTR */ 3743 TCGv temp = tcg_temp_new(); 3744 3745 if (type == BCOND_CTR) { 3746 /* 3747 * All ISAs up to v3 describe this form of bcctr as invalid but 3748 * some processors, ie. 64-bit server processors compliant with 3749 * arch 2.x, do implement a "test and decrement" logic instead, 3750 * as described in their respective UMs. This logic involves CTR 3751 * to act as both the branch target and a counter, which makes 3752 * it basically useless and thus never used in real code. 3753 * 3754 * This form was hence chosen to trigger extra micro-architectural 3755 * side-effect on real HW needed for the Spectre v2 workaround. 3756 * It is up to guests that implement such workaround, ie. linux, to 3757 * use this form in a way it just triggers the side-effect without 3758 * doing anything else harmful. 3759 */ 3760 if (unlikely(!is_book3s_arch2x(ctx))) { 3761 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3762 return; 3763 } 3764 3765 if (NARROW_MODE(ctx)) { 3766 tcg_gen_ext32u_tl(temp, cpu_ctr); 3767 } else { 3768 tcg_gen_mov_tl(temp, cpu_ctr); 3769 } 3770 if (bo & 0x2) { 3771 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3772 } else { 3773 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3774 } 3775 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3776 } else { 3777 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3778 if (NARROW_MODE(ctx)) { 3779 tcg_gen_ext32u_tl(temp, cpu_ctr); 3780 } else { 3781 tcg_gen_mov_tl(temp, cpu_ctr); 3782 } 3783 if (bo & 0x2) { 3784 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3785 } else { 3786 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3787 } 3788 } 3789 bhrb_type |= BHRB_TYPE_COND; 3790 } 3791 if ((bo & 0x10) == 0) { 3792 /* Test CR */ 3793 uint32_t bi = BI(ctx->opcode); 3794 uint32_t mask = 0x08 >> (bi & 0x03); 3795 TCGv_i32 temp = tcg_temp_new_i32(); 3796 3797 if (bo & 0x8) { 3798 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3799 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3800 } else { 3801 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3802 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3803 } 3804 bhrb_type |= BHRB_TYPE_COND; 3805 } 3806 3807 gen_update_branch_history(ctx, ctx->cia, target, bhrb_type); 3808 3809 if (type == BCOND_IM) { 3810 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3811 if (likely(AA(ctx->opcode) == 0)) { 3812 gen_goto_tb(ctx, 0, ctx->cia + li); 3813 } else { 3814 gen_goto_tb(ctx, 0, li); 3815 } 3816 } else { 3817 if (NARROW_MODE(ctx)) { 3818 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3819 } else { 3820 tcg_gen_andi_tl(cpu_nip, target, ~3); 3821 } 3822 gen_lookup_and_goto_ptr(ctx); 3823 } 3824 if ((bo & 0x14) != 0x14) { 3825 /* fallthrough case */ 3826 gen_set_label(l1); 3827 gen_goto_tb(ctx, 1, ctx->base.pc_next); 3828 } 3829 ctx->base.is_jmp = DISAS_NORETURN; 3830 } 3831 3832 static void gen_bc(DisasContext *ctx) 3833 { 3834 gen_bcond(ctx, BCOND_IM); 3835 } 3836 3837 static void gen_bcctr(DisasContext *ctx) 3838 { 3839 gen_bcond(ctx, BCOND_CTR); 3840 } 3841 3842 static void gen_bclr(DisasContext *ctx) 3843 { 3844 gen_bcond(ctx, BCOND_LR); 3845 } 3846 3847 static void gen_bctar(DisasContext *ctx) 3848 { 3849 gen_bcond(ctx, BCOND_TAR); 3850 } 3851 3852 /*** Condition register logical ***/ 3853 #define GEN_CRLOGIC(name, tcg_op, opc) \ 3854 static void glue(gen_, name)(DisasContext *ctx) \ 3855 { \ 3856 uint8_t bitmask; \ 3857 int sh; \ 3858 TCGv_i32 t0, t1; \ 3859 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3860 t0 = tcg_temp_new_i32(); \ 3861 if (sh > 0) \ 3862 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3863 else if (sh < 0) \ 3864 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3865 else \ 3866 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3867 t1 = tcg_temp_new_i32(); \ 3868 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3869 if (sh > 0) \ 3870 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3871 else if (sh < 0) \ 3872 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3873 else \ 3874 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3875 tcg_op(t0, t0, t1); \ 3876 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3877 tcg_gen_andi_i32(t0, t0, bitmask); \ 3878 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3879 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3880 } 3881 3882 /* crand */ 3883 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3884 /* crandc */ 3885 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3886 /* creqv */ 3887 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3888 /* crnand */ 3889 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3890 /* crnor */ 3891 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3892 /* cror */ 3893 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3894 /* crorc */ 3895 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3896 /* crxor */ 3897 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3898 3899 /* mcrf */ 3900 static void gen_mcrf(DisasContext *ctx) 3901 { 3902 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3903 } 3904 3905 /*** System linkage ***/ 3906 3907 /* rfi (supervisor only) */ 3908 static void gen_rfi(DisasContext *ctx) 3909 { 3910 #if defined(CONFIG_USER_ONLY) 3911 GEN_PRIV(ctx); 3912 #else 3913 /* 3914 * This instruction doesn't exist anymore on 64-bit server 3915 * processors compliant with arch 2.x 3916 */ 3917 if (is_book3s_arch2x(ctx)) { 3918 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3919 return; 3920 } 3921 /* Restore CPU state */ 3922 CHK_SV(ctx); 3923 translator_io_start(&ctx->base); 3924 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); 3925 gen_helper_rfi(tcg_env); 3926 ctx->base.is_jmp = DISAS_EXIT; 3927 #endif 3928 } 3929 3930 #if defined(TARGET_PPC64) 3931 static void gen_rfid(DisasContext *ctx) 3932 { 3933 #if defined(CONFIG_USER_ONLY) 3934 GEN_PRIV(ctx); 3935 #else 3936 /* Restore CPU state */ 3937 CHK_SV(ctx); 3938 translator_io_start(&ctx->base); 3939 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); 3940 gen_helper_rfid(tcg_env); 3941 ctx->base.is_jmp = DISAS_EXIT; 3942 #endif 3943 } 3944 3945 #if !defined(CONFIG_USER_ONLY) 3946 static void gen_rfscv(DisasContext *ctx) 3947 { 3948 #if defined(CONFIG_USER_ONLY) 3949 GEN_PRIV(ctx); 3950 #else 3951 /* Restore CPU state */ 3952 CHK_SV(ctx); 3953 translator_io_start(&ctx->base); 3954 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); 3955 gen_helper_rfscv(tcg_env); 3956 ctx->base.is_jmp = DISAS_EXIT; 3957 #endif 3958 } 3959 #endif 3960 3961 static void gen_hrfid(DisasContext *ctx) 3962 { 3963 #if defined(CONFIG_USER_ONLY) 3964 GEN_PRIV(ctx); 3965 #else 3966 /* Restore CPU state */ 3967 CHK_HV(ctx); 3968 translator_io_start(&ctx->base); 3969 gen_helper_hrfid(tcg_env); 3970 ctx->base.is_jmp = DISAS_EXIT; 3971 #endif 3972 } 3973 #endif 3974 3975 /* sc */ 3976 #if defined(CONFIG_USER_ONLY) 3977 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3978 #else 3979 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3980 #endif 3981 static void gen_sc(DisasContext *ctx) 3982 { 3983 uint32_t lev; 3984 3985 /* 3986 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 3987 * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 3988 * for Ultravisor which TCG does not support, so just ignore the top 6. 3989 */ 3990 lev = (ctx->opcode >> 5) & 0x1; 3991 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3992 } 3993 3994 #if defined(TARGET_PPC64) 3995 #if !defined(CONFIG_USER_ONLY) 3996 static void gen_scv(DisasContext *ctx) 3997 { 3998 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 3999 4000 /* Set the PC back to the faulting instruction. */ 4001 gen_update_nip(ctx, ctx->cia); 4002 gen_helper_scv(tcg_env, tcg_constant_i32(lev)); 4003 4004 ctx->base.is_jmp = DISAS_NORETURN; 4005 } 4006 #endif 4007 #endif 4008 4009 /*** Trap ***/ 4010 4011 /* Check for unconditional traps (always or never) */ 4012 static bool check_unconditional_trap(DisasContext *ctx, int to) 4013 { 4014 /* Trap never */ 4015 if (to == 0) { 4016 return true; 4017 } 4018 /* Trap always */ 4019 if (to == 31) { 4020 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4021 return true; 4022 } 4023 return false; 4024 } 4025 4026 /*** Processor control ***/ 4027 4028 /* mcrxr */ 4029 static void gen_mcrxr(DisasContext *ctx) 4030 { 4031 TCGv_i32 t0 = tcg_temp_new_i32(); 4032 TCGv_i32 t1 = tcg_temp_new_i32(); 4033 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4034 4035 tcg_gen_trunc_tl_i32(t0, cpu_so); 4036 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4037 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4038 tcg_gen_shli_i32(t0, t0, 3); 4039 tcg_gen_shli_i32(t1, t1, 2); 4040 tcg_gen_shli_i32(dst, dst, 1); 4041 tcg_gen_or_i32(dst, dst, t0); 4042 tcg_gen_or_i32(dst, dst, t1); 4043 4044 tcg_gen_movi_tl(cpu_so, 0); 4045 tcg_gen_movi_tl(cpu_ov, 0); 4046 tcg_gen_movi_tl(cpu_ca, 0); 4047 } 4048 4049 #ifdef TARGET_PPC64 4050 /* mcrxrx */ 4051 static void gen_mcrxrx(DisasContext *ctx) 4052 { 4053 TCGv t0 = tcg_temp_new(); 4054 TCGv t1 = tcg_temp_new(); 4055 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4056 4057 /* copy OV and OV32 */ 4058 tcg_gen_shli_tl(t0, cpu_ov, 1); 4059 tcg_gen_or_tl(t0, t0, cpu_ov32); 4060 tcg_gen_shli_tl(t0, t0, 2); 4061 /* copy CA and CA32 */ 4062 tcg_gen_shli_tl(t1, cpu_ca, 1); 4063 tcg_gen_or_tl(t1, t1, cpu_ca32); 4064 tcg_gen_or_tl(t0, t0, t1); 4065 tcg_gen_trunc_tl_i32(dst, t0); 4066 } 4067 #endif 4068 4069 /* mfcr mfocrf */ 4070 static void gen_mfcr(DisasContext *ctx) 4071 { 4072 uint32_t crm, crn; 4073 4074 if (likely(ctx->opcode & 0x00100000)) { 4075 crm = CRM(ctx->opcode); 4076 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4077 crn = ctz32(crm); 4078 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4079 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4080 cpu_gpr[rD(ctx->opcode)], crn * 4); 4081 } 4082 } else { 4083 TCGv_i32 t0 = tcg_temp_new_i32(); 4084 tcg_gen_mov_i32(t0, cpu_crf[0]); 4085 tcg_gen_shli_i32(t0, t0, 4); 4086 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4087 tcg_gen_shli_i32(t0, t0, 4); 4088 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4089 tcg_gen_shli_i32(t0, t0, 4); 4090 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4091 tcg_gen_shli_i32(t0, t0, 4); 4092 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4093 tcg_gen_shli_i32(t0, t0, 4); 4094 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4095 tcg_gen_shli_i32(t0, t0, 4); 4096 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4097 tcg_gen_shli_i32(t0, t0, 4); 4098 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4099 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4100 } 4101 } 4102 4103 /* mfmsr */ 4104 static void gen_mfmsr(DisasContext *ctx) 4105 { 4106 CHK_SV(ctx); 4107 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4108 } 4109 4110 /* mfspr */ 4111 static inline void gen_op_mfspr(DisasContext *ctx) 4112 { 4113 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4114 uint32_t sprn = SPR(ctx->opcode); 4115 4116 #if defined(CONFIG_USER_ONLY) 4117 read_cb = ctx->spr_cb[sprn].uea_read; 4118 #else 4119 if (ctx->pr) { 4120 read_cb = ctx->spr_cb[sprn].uea_read; 4121 } else if (ctx->hv) { 4122 read_cb = ctx->spr_cb[sprn].hea_read; 4123 } else { 4124 read_cb = ctx->spr_cb[sprn].oea_read; 4125 } 4126 #endif 4127 if (likely(read_cb != NULL)) { 4128 if (likely(read_cb != SPR_NOACCESS)) { 4129 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4130 } else { 4131 /* Privilege exception */ 4132 /* 4133 * This is a hack to avoid warnings when running Linux: 4134 * this OS breaks the PowerPC virtualisation model, 4135 * allowing userland application to read the PVR 4136 */ 4137 if (sprn != SPR_PVR) { 4138 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4139 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4140 ctx->cia); 4141 } 4142 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4143 } 4144 } else { 4145 /* ISA 2.07 defines these as no-ops */ 4146 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4147 (sprn >= 808 && sprn <= 811)) { 4148 /* This is a nop */ 4149 return; 4150 } 4151 /* Not defined */ 4152 qemu_log_mask(LOG_GUEST_ERROR, 4153 "Trying to read invalid spr %d (0x%03x) at " 4154 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4155 4156 /* 4157 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4158 * generate a priv, a hv emu or a no-op 4159 */ 4160 if (sprn & 0x10) { 4161 if (ctx->pr) { 4162 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4163 } 4164 } else { 4165 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4166 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4167 } 4168 } 4169 } 4170 } 4171 4172 static void gen_mfspr(DisasContext *ctx) 4173 { 4174 gen_op_mfspr(ctx); 4175 } 4176 4177 /* mftb */ 4178 static void gen_mftb(DisasContext *ctx) 4179 { 4180 gen_op_mfspr(ctx); 4181 } 4182 4183 /* mtcrf mtocrf*/ 4184 static void gen_mtcrf(DisasContext *ctx) 4185 { 4186 uint32_t crm, crn; 4187 4188 crm = CRM(ctx->opcode); 4189 if (likely((ctx->opcode & 0x00100000))) { 4190 if (crm && ((crm & (crm - 1)) == 0)) { 4191 TCGv_i32 temp = tcg_temp_new_i32(); 4192 crn = ctz32(crm); 4193 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4194 tcg_gen_shri_i32(temp, temp, crn * 4); 4195 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4196 } 4197 } else { 4198 TCGv_i32 temp = tcg_temp_new_i32(); 4199 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4200 for (crn = 0 ; crn < 8 ; crn++) { 4201 if (crm & (1 << crn)) { 4202 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4203 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4204 } 4205 } 4206 } 4207 } 4208 4209 /* mtmsr */ 4210 #if defined(TARGET_PPC64) 4211 static void gen_mtmsrd(DisasContext *ctx) 4212 { 4213 if (unlikely(!is_book3s_arch2x(ctx))) { 4214 gen_invalid(ctx); 4215 return; 4216 } 4217 4218 CHK_SV(ctx); 4219 4220 #if !defined(CONFIG_USER_ONLY) 4221 TCGv t0, t1; 4222 target_ulong mask; 4223 4224 t0 = tcg_temp_new(); 4225 t1 = tcg_temp_new(); 4226 4227 translator_io_start(&ctx->base); 4228 4229 if (ctx->opcode & 0x00010000) { 4230 /* L=1 form only updates EE and RI */ 4231 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4232 } else { 4233 /* mtmsrd does not alter HV, S, ME, or LE */ 4234 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4235 (1ULL << MSR_HV)); 4236 /* 4237 * XXX: we need to update nip before the store if we enter 4238 * power saving mode, we will exit the loop directly from 4239 * ppc_store_msr 4240 */ 4241 gen_update_nip(ctx, ctx->base.pc_next); 4242 } 4243 4244 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4245 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4246 tcg_gen_or_tl(t0, t0, t1); 4247 4248 gen_helper_store_msr(tcg_env, t0); 4249 4250 /* Must stop the translation as machine state (may have) changed */ 4251 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4252 #endif /* !defined(CONFIG_USER_ONLY) */ 4253 } 4254 #endif /* defined(TARGET_PPC64) */ 4255 4256 static void gen_mtmsr(DisasContext *ctx) 4257 { 4258 CHK_SV(ctx); 4259 4260 #if !defined(CONFIG_USER_ONLY) 4261 TCGv t0, t1; 4262 target_ulong mask = 0xFFFFFFFF; 4263 4264 t0 = tcg_temp_new(); 4265 t1 = tcg_temp_new(); 4266 4267 translator_io_start(&ctx->base); 4268 if (ctx->opcode & 0x00010000) { 4269 /* L=1 form only updates EE and RI */ 4270 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4271 } else { 4272 /* mtmsr does not alter S, ME, or LE */ 4273 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4274 4275 /* 4276 * XXX: we need to update nip before the store if we enter 4277 * power saving mode, we will exit the loop directly from 4278 * ppc_store_msr 4279 */ 4280 gen_update_nip(ctx, ctx->base.pc_next); 4281 } 4282 4283 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4284 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4285 tcg_gen_or_tl(t0, t0, t1); 4286 4287 gen_helper_store_msr(tcg_env, t0); 4288 4289 /* Must stop the translation as machine state (may have) changed */ 4290 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4291 #endif 4292 } 4293 4294 /* mtspr */ 4295 static void gen_mtspr(DisasContext *ctx) 4296 { 4297 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4298 uint32_t sprn = SPR(ctx->opcode); 4299 4300 #if defined(CONFIG_USER_ONLY) 4301 write_cb = ctx->spr_cb[sprn].uea_write; 4302 #else 4303 if (ctx->pr) { 4304 write_cb = ctx->spr_cb[sprn].uea_write; 4305 } else if (ctx->hv) { 4306 write_cb = ctx->spr_cb[sprn].hea_write; 4307 } else { 4308 write_cb = ctx->spr_cb[sprn].oea_write; 4309 } 4310 #endif 4311 if (likely(write_cb != NULL)) { 4312 if (likely(write_cb != SPR_NOACCESS)) { 4313 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4314 } else { 4315 /* Privilege exception */ 4316 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4317 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4318 ctx->cia); 4319 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4320 } 4321 } else { 4322 /* ISA 2.07 defines these as no-ops */ 4323 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4324 (sprn >= 808 && sprn <= 811)) { 4325 /* This is a nop */ 4326 return; 4327 } 4328 4329 /* Not defined */ 4330 qemu_log_mask(LOG_GUEST_ERROR, 4331 "Trying to write invalid spr %d (0x%03x) at " 4332 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4333 4334 4335 /* 4336 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4337 * generate a priv, a hv emu or a no-op 4338 */ 4339 if (sprn & 0x10) { 4340 if (ctx->pr) { 4341 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4342 } 4343 } else { 4344 if (ctx->pr || sprn == 0) { 4345 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4346 } 4347 } 4348 } 4349 } 4350 4351 #if defined(TARGET_PPC64) 4352 /* setb */ 4353 static void gen_setb(DisasContext *ctx) 4354 { 4355 TCGv_i32 t0 = tcg_temp_new_i32(); 4356 TCGv_i32 t8 = tcg_constant_i32(8); 4357 TCGv_i32 tm1 = tcg_constant_i32(-1); 4358 int crf = crfS(ctx->opcode); 4359 4360 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4361 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4362 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4363 } 4364 #endif 4365 4366 /*** Cache management ***/ 4367 4368 /* dcbf */ 4369 static void gen_dcbf(DisasContext *ctx) 4370 { 4371 /* XXX: specification says this is treated as a load by the MMU */ 4372 TCGv t0; 4373 gen_set_access_type(ctx, ACCESS_CACHE); 4374 t0 = tcg_temp_new(); 4375 gen_addr_reg_index(ctx, t0); 4376 gen_qemu_ld8u(ctx, t0, t0); 4377 } 4378 4379 /* dcbfep (external PID dcbf) */ 4380 static void gen_dcbfep(DisasContext *ctx) 4381 { 4382 /* XXX: specification says this is treated as a load by the MMU */ 4383 TCGv t0; 4384 CHK_SV(ctx); 4385 gen_set_access_type(ctx, ACCESS_CACHE); 4386 t0 = tcg_temp_new(); 4387 gen_addr_reg_index(ctx, t0); 4388 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4389 } 4390 4391 /* dcbi (Supervisor only) */ 4392 static void gen_dcbi(DisasContext *ctx) 4393 { 4394 #if defined(CONFIG_USER_ONLY) 4395 GEN_PRIV(ctx); 4396 #else 4397 TCGv EA, val; 4398 4399 CHK_SV(ctx); 4400 EA = tcg_temp_new(); 4401 gen_set_access_type(ctx, ACCESS_CACHE); 4402 gen_addr_reg_index(ctx, EA); 4403 val = tcg_temp_new(); 4404 /* XXX: specification says this should be treated as a store by the MMU */ 4405 gen_qemu_ld8u(ctx, val, EA); 4406 gen_qemu_st8(ctx, val, EA); 4407 #endif /* defined(CONFIG_USER_ONLY) */ 4408 } 4409 4410 /* dcdst */ 4411 static void gen_dcbst(DisasContext *ctx) 4412 { 4413 /* XXX: specification say this is treated as a load by the MMU */ 4414 TCGv t0; 4415 gen_set_access_type(ctx, ACCESS_CACHE); 4416 t0 = tcg_temp_new(); 4417 gen_addr_reg_index(ctx, t0); 4418 gen_qemu_ld8u(ctx, t0, t0); 4419 } 4420 4421 /* dcbstep (dcbstep External PID version) */ 4422 static void gen_dcbstep(DisasContext *ctx) 4423 { 4424 /* XXX: specification say this is treated as a load by the MMU */ 4425 TCGv t0; 4426 gen_set_access_type(ctx, ACCESS_CACHE); 4427 t0 = tcg_temp_new(); 4428 gen_addr_reg_index(ctx, t0); 4429 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4430 } 4431 4432 /* dcbt */ 4433 static void gen_dcbt(DisasContext *ctx) 4434 { 4435 /* 4436 * interpreted as no-op 4437 * XXX: specification say this is treated as a load by the MMU but 4438 * does not generate any exception 4439 */ 4440 } 4441 4442 /* dcbtep */ 4443 static void gen_dcbtep(DisasContext *ctx) 4444 { 4445 /* 4446 * interpreted as no-op 4447 * XXX: specification say this is treated as a load by the MMU but 4448 * does not generate any exception 4449 */ 4450 } 4451 4452 /* dcbtst */ 4453 static void gen_dcbtst(DisasContext *ctx) 4454 { 4455 /* 4456 * interpreted as no-op 4457 * XXX: specification say this is treated as a load by the MMU but 4458 * does not generate any exception 4459 */ 4460 } 4461 4462 /* dcbtstep */ 4463 static void gen_dcbtstep(DisasContext *ctx) 4464 { 4465 /* 4466 * interpreted as no-op 4467 * XXX: specification say this is treated as a load by the MMU but 4468 * does not generate any exception 4469 */ 4470 } 4471 4472 /* dcbtls */ 4473 static void gen_dcbtls(DisasContext *ctx) 4474 { 4475 /* Always fails locking the cache */ 4476 TCGv t0 = tcg_temp_new(); 4477 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4478 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4479 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4480 } 4481 4482 /* dcblc */ 4483 static void gen_dcblc(DisasContext *ctx) 4484 { 4485 /* 4486 * interpreted as no-op 4487 */ 4488 } 4489 4490 /* dcbz */ 4491 static void gen_dcbz(DisasContext *ctx) 4492 { 4493 TCGv tcgv_addr = tcg_temp_new(); 4494 4495 gen_set_access_type(ctx, ACCESS_CACHE); 4496 gen_addr_reg_index(ctx, tcgv_addr); 4497 4498 #ifdef TARGET_PPC64 4499 if (ctx->excp_model == POWERPC_EXCP_970 && !(ctx->opcode & 0x00200000)) { 4500 gen_helper_dcbzl(tcg_env, tcgv_addr); 4501 return; 4502 } 4503 #endif 4504 4505 gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(ctx->mem_idx)); 4506 } 4507 4508 /* dcbzep */ 4509 static void gen_dcbzep(DisasContext *ctx) 4510 { 4511 TCGv tcgv_addr = tcg_temp_new(); 4512 4513 gen_set_access_type(ctx, ACCESS_CACHE); 4514 gen_addr_reg_index(ctx, tcgv_addr); 4515 gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(PPC_TLB_EPID_STORE)); 4516 } 4517 4518 /* dst / dstt */ 4519 static void gen_dst(DisasContext *ctx) 4520 { 4521 if (rA(ctx->opcode) == 0) { 4522 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4523 } else { 4524 /* interpreted as no-op */ 4525 } 4526 } 4527 4528 /* dstst /dststt */ 4529 static void gen_dstst(DisasContext *ctx) 4530 { 4531 if (rA(ctx->opcode) == 0) { 4532 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4533 } else { 4534 /* interpreted as no-op */ 4535 } 4536 4537 } 4538 4539 /* dss / dssall */ 4540 static void gen_dss(DisasContext *ctx) 4541 { 4542 /* interpreted as no-op */ 4543 } 4544 4545 /* icbi */ 4546 static void gen_icbi(DisasContext *ctx) 4547 { 4548 TCGv t0; 4549 gen_set_access_type(ctx, ACCESS_CACHE); 4550 t0 = tcg_temp_new(); 4551 gen_addr_reg_index(ctx, t0); 4552 gen_helper_icbi(tcg_env, t0); 4553 } 4554 4555 /* icbiep */ 4556 static void gen_icbiep(DisasContext *ctx) 4557 { 4558 TCGv t0; 4559 gen_set_access_type(ctx, ACCESS_CACHE); 4560 t0 = tcg_temp_new(); 4561 gen_addr_reg_index(ctx, t0); 4562 gen_helper_icbiep(tcg_env, t0); 4563 } 4564 4565 /* Optional: */ 4566 /* dcba */ 4567 static void gen_dcba(DisasContext *ctx) 4568 { 4569 /* 4570 * interpreted as no-op 4571 * XXX: specification say this is treated as a store by the MMU 4572 * but does not generate any exception 4573 */ 4574 } 4575 4576 /*** Segment register manipulation ***/ 4577 /* Supervisor only: */ 4578 4579 /* mfsr */ 4580 static void gen_mfsr(DisasContext *ctx) 4581 { 4582 #if defined(CONFIG_USER_ONLY) 4583 GEN_PRIV(ctx); 4584 #else 4585 TCGv t0; 4586 4587 CHK_SV(ctx); 4588 t0 = tcg_constant_tl(SR(ctx->opcode)); 4589 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4590 #endif /* defined(CONFIG_USER_ONLY) */ 4591 } 4592 4593 /* mfsrin */ 4594 static void gen_mfsrin(DisasContext *ctx) 4595 { 4596 #if defined(CONFIG_USER_ONLY) 4597 GEN_PRIV(ctx); 4598 #else 4599 TCGv t0; 4600 4601 CHK_SV(ctx); 4602 t0 = tcg_temp_new(); 4603 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4604 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4605 #endif /* defined(CONFIG_USER_ONLY) */ 4606 } 4607 4608 /* mtsr */ 4609 static void gen_mtsr(DisasContext *ctx) 4610 { 4611 #if defined(CONFIG_USER_ONLY) 4612 GEN_PRIV(ctx); 4613 #else 4614 TCGv t0; 4615 4616 CHK_SV(ctx); 4617 t0 = tcg_constant_tl(SR(ctx->opcode)); 4618 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 4619 #endif /* defined(CONFIG_USER_ONLY) */ 4620 } 4621 4622 /* mtsrin */ 4623 static void gen_mtsrin(DisasContext *ctx) 4624 { 4625 #if defined(CONFIG_USER_ONLY) 4626 GEN_PRIV(ctx); 4627 #else 4628 TCGv t0; 4629 CHK_SV(ctx); 4630 4631 t0 = tcg_temp_new(); 4632 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4633 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rD(ctx->opcode)]); 4634 #endif /* defined(CONFIG_USER_ONLY) */ 4635 } 4636 4637 #if defined(TARGET_PPC64) 4638 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4639 4640 /* mfsr */ 4641 static void gen_mfsr_64b(DisasContext *ctx) 4642 { 4643 #if defined(CONFIG_USER_ONLY) 4644 GEN_PRIV(ctx); 4645 #else 4646 TCGv t0; 4647 4648 CHK_SV(ctx); 4649 t0 = tcg_constant_tl(SR(ctx->opcode)); 4650 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4651 #endif /* defined(CONFIG_USER_ONLY) */ 4652 } 4653 4654 /* mfsrin */ 4655 static void gen_mfsrin_64b(DisasContext *ctx) 4656 { 4657 #if defined(CONFIG_USER_ONLY) 4658 GEN_PRIV(ctx); 4659 #else 4660 TCGv t0; 4661 4662 CHK_SV(ctx); 4663 t0 = tcg_temp_new(); 4664 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4665 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4666 #endif /* defined(CONFIG_USER_ONLY) */ 4667 } 4668 4669 /* mtsr */ 4670 static void gen_mtsr_64b(DisasContext *ctx) 4671 { 4672 #if defined(CONFIG_USER_ONLY) 4673 GEN_PRIV(ctx); 4674 #else 4675 TCGv t0; 4676 4677 CHK_SV(ctx); 4678 t0 = tcg_constant_tl(SR(ctx->opcode)); 4679 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 4680 #endif /* defined(CONFIG_USER_ONLY) */ 4681 } 4682 4683 /* mtsrin */ 4684 static void gen_mtsrin_64b(DisasContext *ctx) 4685 { 4686 #if defined(CONFIG_USER_ONLY) 4687 GEN_PRIV(ctx); 4688 #else 4689 TCGv t0; 4690 4691 CHK_SV(ctx); 4692 t0 = tcg_temp_new(); 4693 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4694 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 4695 #endif /* defined(CONFIG_USER_ONLY) */ 4696 } 4697 4698 #endif /* defined(TARGET_PPC64) */ 4699 4700 /*** Lookaside buffer management ***/ 4701 /* Optional & supervisor only: */ 4702 4703 /* tlbia */ 4704 static void gen_tlbia(DisasContext *ctx) 4705 { 4706 #if defined(CONFIG_USER_ONLY) 4707 GEN_PRIV(ctx); 4708 #else 4709 CHK_HV(ctx); 4710 4711 gen_helper_tlbia(tcg_env); 4712 #endif /* defined(CONFIG_USER_ONLY) */ 4713 } 4714 4715 /* tlbsync */ 4716 static void gen_tlbsync(DisasContext *ctx) 4717 { 4718 #if defined(CONFIG_USER_ONLY) 4719 GEN_PRIV(ctx); 4720 #else 4721 4722 if (ctx->gtse) { 4723 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 4724 } else { 4725 CHK_HV(ctx); /* Else hypervisor privileged */ 4726 } 4727 4728 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4729 if (ctx->insns_flags & PPC_BOOKE) { 4730 gen_check_tlb_flush(ctx, true); 4731 } 4732 #endif /* defined(CONFIG_USER_ONLY) */ 4733 } 4734 4735 /*** External control ***/ 4736 /* Optional: */ 4737 4738 /* eciwx */ 4739 static void gen_eciwx(DisasContext *ctx) 4740 { 4741 TCGv t0; 4742 /* Should check EAR[E] ! */ 4743 gen_set_access_type(ctx, ACCESS_EXT); 4744 t0 = tcg_temp_new(); 4745 gen_addr_reg_index(ctx, t0); 4746 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4747 DEF_MEMOP(MO_UL | MO_ALIGN)); 4748 } 4749 4750 /* ecowx */ 4751 static void gen_ecowx(DisasContext *ctx) 4752 { 4753 TCGv t0; 4754 /* Should check EAR[E] ! */ 4755 gen_set_access_type(ctx, ACCESS_EXT); 4756 t0 = tcg_temp_new(); 4757 gen_addr_reg_index(ctx, t0); 4758 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4759 DEF_MEMOP(MO_UL | MO_ALIGN)); 4760 } 4761 4762 /* 602 - 603 - G2 TLB management */ 4763 4764 /* tlbld */ 4765 static void gen_tlbld_6xx(DisasContext *ctx) 4766 { 4767 #if defined(CONFIG_USER_ONLY) 4768 GEN_PRIV(ctx); 4769 #else 4770 CHK_SV(ctx); 4771 gen_helper_6xx_tlbd(tcg_env, cpu_gpr[rB(ctx->opcode)]); 4772 #endif /* defined(CONFIG_USER_ONLY) */ 4773 } 4774 4775 /* tlbli */ 4776 static void gen_tlbli_6xx(DisasContext *ctx) 4777 { 4778 #if defined(CONFIG_USER_ONLY) 4779 GEN_PRIV(ctx); 4780 #else 4781 CHK_SV(ctx); 4782 gen_helper_6xx_tlbi(tcg_env, cpu_gpr[rB(ctx->opcode)]); 4783 #endif /* defined(CONFIG_USER_ONLY) */ 4784 } 4785 4786 /* BookE specific instructions */ 4787 4788 /* XXX: not implemented on 440 ? */ 4789 static void gen_mfapidi(DisasContext *ctx) 4790 { 4791 /* XXX: TODO */ 4792 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4793 } 4794 4795 /* XXX: not implemented on 440 ? */ 4796 static void gen_tlbiva(DisasContext *ctx) 4797 { 4798 #if defined(CONFIG_USER_ONLY) 4799 GEN_PRIV(ctx); 4800 #else 4801 TCGv t0; 4802 4803 CHK_SV(ctx); 4804 t0 = tcg_temp_new(); 4805 gen_addr_reg_index(ctx, t0); 4806 gen_helper_tlbiva(tcg_env, cpu_gpr[rB(ctx->opcode)]); 4807 #endif /* defined(CONFIG_USER_ONLY) */ 4808 } 4809 4810 /* All 405 MAC instructions are translated here */ 4811 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 4812 int ra, int rb, int rt, int Rc) 4813 { 4814 TCGv t0, t1; 4815 4816 t0 = tcg_temp_new(); 4817 t1 = tcg_temp_new(); 4818 4819 switch (opc3 & 0x0D) { 4820 case 0x05: 4821 /* macchw - macchw. - macchwo - macchwo. */ 4822 /* macchws - macchws. - macchwso - macchwso. */ 4823 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 4824 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 4825 /* mulchw - mulchw. */ 4826 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 4827 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 4828 tcg_gen_ext16s_tl(t1, t1); 4829 break; 4830 case 0x04: 4831 /* macchwu - macchwu. - macchwuo - macchwuo. */ 4832 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 4833 /* mulchwu - mulchwu. */ 4834 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 4835 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 4836 tcg_gen_ext16u_tl(t1, t1); 4837 break; 4838 case 0x01: 4839 /* machhw - machhw. - machhwo - machhwo. */ 4840 /* machhws - machhws. - machhwso - machhwso. */ 4841 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 4842 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 4843 /* mulhhw - mulhhw. */ 4844 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 4845 tcg_gen_ext16s_tl(t0, t0); 4846 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 4847 tcg_gen_ext16s_tl(t1, t1); 4848 break; 4849 case 0x00: 4850 /* machhwu - machhwu. - machhwuo - machhwuo. */ 4851 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 4852 /* mulhhwu - mulhhwu. */ 4853 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 4854 tcg_gen_ext16u_tl(t0, t0); 4855 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 4856 tcg_gen_ext16u_tl(t1, t1); 4857 break; 4858 case 0x0D: 4859 /* maclhw - maclhw. - maclhwo - maclhwo. */ 4860 /* maclhws - maclhws. - maclhwso - maclhwso. */ 4861 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 4862 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 4863 /* mullhw - mullhw. */ 4864 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 4865 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 4866 break; 4867 case 0x0C: 4868 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 4869 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 4870 /* mullhwu - mullhwu. */ 4871 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 4872 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 4873 break; 4874 } 4875 if (opc2 & 0x04) { 4876 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 4877 tcg_gen_mul_tl(t1, t0, t1); 4878 if (opc2 & 0x02) { 4879 /* nmultiply-and-accumulate (0x0E) */ 4880 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 4881 } else { 4882 /* multiply-and-accumulate (0x0C) */ 4883 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 4884 } 4885 4886 if (opc3 & 0x12) { 4887 /* Check overflow and/or saturate */ 4888 TCGLabel *l1 = gen_new_label(); 4889 4890 if (opc3 & 0x10) { 4891 /* Start with XER OV disabled, the most likely case */ 4892 tcg_gen_movi_tl(cpu_ov, 0); 4893 } 4894 if (opc3 & 0x01) { 4895 /* Signed */ 4896 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 4897 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 4898 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 4899 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 4900 if (opc3 & 0x02) { 4901 /* Saturate */ 4902 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 4903 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 4904 } 4905 } else { 4906 /* Unsigned */ 4907 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 4908 if (opc3 & 0x02) { 4909 /* Saturate */ 4910 tcg_gen_movi_tl(t0, UINT32_MAX); 4911 } 4912 } 4913 if (opc3 & 0x10) { 4914 /* Check overflow */ 4915 tcg_gen_movi_tl(cpu_ov, 1); 4916 tcg_gen_movi_tl(cpu_so, 1); 4917 } 4918 gen_set_label(l1); 4919 tcg_gen_mov_tl(cpu_gpr[rt], t0); 4920 } 4921 } else { 4922 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 4923 } 4924 if (unlikely(Rc) != 0) { 4925 /* Update Rc0 */ 4926 gen_set_Rc0(ctx, cpu_gpr[rt]); 4927 } 4928 } 4929 4930 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 4931 static void glue(gen_, name)(DisasContext *ctx) \ 4932 { \ 4933 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 4934 rD(ctx->opcode), Rc(ctx->opcode)); \ 4935 } 4936 4937 /* macchw - macchw. */ 4938 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 4939 /* macchwo - macchwo. */ 4940 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 4941 /* macchws - macchws. */ 4942 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 4943 /* macchwso - macchwso. */ 4944 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 4945 /* macchwsu - macchwsu. */ 4946 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 4947 /* macchwsuo - macchwsuo. */ 4948 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 4949 /* macchwu - macchwu. */ 4950 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 4951 /* macchwuo - macchwuo. */ 4952 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 4953 /* machhw - machhw. */ 4954 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 4955 /* machhwo - machhwo. */ 4956 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 4957 /* machhws - machhws. */ 4958 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 4959 /* machhwso - machhwso. */ 4960 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 4961 /* machhwsu - machhwsu. */ 4962 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 4963 /* machhwsuo - machhwsuo. */ 4964 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 4965 /* machhwu - machhwu. */ 4966 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 4967 /* machhwuo - machhwuo. */ 4968 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 4969 /* maclhw - maclhw. */ 4970 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 4971 /* maclhwo - maclhwo. */ 4972 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 4973 /* maclhws - maclhws. */ 4974 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 4975 /* maclhwso - maclhwso. */ 4976 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 4977 /* maclhwu - maclhwu. */ 4978 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 4979 /* maclhwuo - maclhwuo. */ 4980 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 4981 /* maclhwsu - maclhwsu. */ 4982 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 4983 /* maclhwsuo - maclhwsuo. */ 4984 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 4985 /* nmacchw - nmacchw. */ 4986 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 4987 /* nmacchwo - nmacchwo. */ 4988 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 4989 /* nmacchws - nmacchws. */ 4990 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 4991 /* nmacchwso - nmacchwso. */ 4992 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 4993 /* nmachhw - nmachhw. */ 4994 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 4995 /* nmachhwo - nmachhwo. */ 4996 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 4997 /* nmachhws - nmachhws. */ 4998 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 4999 /* nmachhwso - nmachhwso. */ 5000 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5001 /* nmaclhw - nmaclhw. */ 5002 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5003 /* nmaclhwo - nmaclhwo. */ 5004 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5005 /* nmaclhws - nmaclhws. */ 5006 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5007 /* nmaclhwso - nmaclhwso. */ 5008 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5009 5010 /* mulchw - mulchw. */ 5011 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5012 /* mulchwu - mulchwu. */ 5013 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5014 /* mulhhw - mulhhw. */ 5015 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5016 /* mulhhwu - mulhhwu. */ 5017 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5018 /* mullhw - mullhw. */ 5019 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5020 /* mullhwu - mullhwu. */ 5021 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5022 5023 /* mfdcr */ 5024 static void gen_mfdcr(DisasContext *ctx) 5025 { 5026 #if defined(CONFIG_USER_ONLY) 5027 GEN_PRIV(ctx); 5028 #else 5029 TCGv dcrn; 5030 5031 CHK_SV(ctx); 5032 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5033 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, dcrn); 5034 #endif /* defined(CONFIG_USER_ONLY) */ 5035 } 5036 5037 /* mtdcr */ 5038 static void gen_mtdcr(DisasContext *ctx) 5039 { 5040 #if defined(CONFIG_USER_ONLY) 5041 GEN_PRIV(ctx); 5042 #else 5043 TCGv dcrn; 5044 5045 CHK_SV(ctx); 5046 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5047 gen_helper_store_dcr(tcg_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5048 #endif /* defined(CONFIG_USER_ONLY) */ 5049 } 5050 5051 /* mfdcrx */ 5052 /* XXX: not implemented on 440 ? */ 5053 static void gen_mfdcrx(DisasContext *ctx) 5054 { 5055 #if defined(CONFIG_USER_ONLY) 5056 GEN_PRIV(ctx); 5057 #else 5058 CHK_SV(ctx); 5059 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, 5060 cpu_gpr[rA(ctx->opcode)]); 5061 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5062 #endif /* defined(CONFIG_USER_ONLY) */ 5063 } 5064 5065 /* mtdcrx */ 5066 /* XXX: not implemented on 440 ? */ 5067 static void gen_mtdcrx(DisasContext *ctx) 5068 { 5069 #if defined(CONFIG_USER_ONLY) 5070 GEN_PRIV(ctx); 5071 #else 5072 CHK_SV(ctx); 5073 gen_helper_store_dcr(tcg_env, cpu_gpr[rA(ctx->opcode)], 5074 cpu_gpr[rS(ctx->opcode)]); 5075 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5076 #endif /* defined(CONFIG_USER_ONLY) */ 5077 } 5078 5079 /* dccci */ 5080 static void gen_dccci(DisasContext *ctx) 5081 { 5082 CHK_SV(ctx); 5083 /* interpreted as no-op */ 5084 } 5085 5086 /* dcread */ 5087 static void gen_dcread(DisasContext *ctx) 5088 { 5089 #if defined(CONFIG_USER_ONLY) 5090 GEN_PRIV(ctx); 5091 #else 5092 TCGv EA, val; 5093 5094 CHK_SV(ctx); 5095 gen_set_access_type(ctx, ACCESS_CACHE); 5096 EA = tcg_temp_new(); 5097 gen_addr_reg_index(ctx, EA); 5098 val = tcg_temp_new(); 5099 gen_qemu_ld32u(ctx, val, EA); 5100 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5101 #endif /* defined(CONFIG_USER_ONLY) */ 5102 } 5103 5104 /* icbt */ 5105 static void gen_icbt_40x(DisasContext *ctx) 5106 { 5107 /* 5108 * interpreted as no-op 5109 * XXX: specification say this is treated as a load by the MMU but 5110 * does not generate any exception 5111 */ 5112 } 5113 5114 /* iccci */ 5115 static void gen_iccci(DisasContext *ctx) 5116 { 5117 CHK_SV(ctx); 5118 /* interpreted as no-op */ 5119 } 5120 5121 /* icread */ 5122 static void gen_icread(DisasContext *ctx) 5123 { 5124 CHK_SV(ctx); 5125 /* interpreted as no-op */ 5126 } 5127 5128 /* rfci (supervisor only) */ 5129 static void gen_rfci_40x(DisasContext *ctx) 5130 { 5131 #if defined(CONFIG_USER_ONLY) 5132 GEN_PRIV(ctx); 5133 #else 5134 CHK_SV(ctx); 5135 /* Restore CPU state */ 5136 gen_helper_40x_rfci(tcg_env); 5137 ctx->base.is_jmp = DISAS_EXIT; 5138 #endif /* defined(CONFIG_USER_ONLY) */ 5139 } 5140 5141 static void gen_rfci(DisasContext *ctx) 5142 { 5143 #if defined(CONFIG_USER_ONLY) 5144 GEN_PRIV(ctx); 5145 #else 5146 CHK_SV(ctx); 5147 /* Restore CPU state */ 5148 gen_helper_rfci(tcg_env); 5149 ctx->base.is_jmp = DISAS_EXIT; 5150 #endif /* defined(CONFIG_USER_ONLY) */ 5151 } 5152 5153 /* BookE specific */ 5154 5155 /* XXX: not implemented on 440 ? */ 5156 static void gen_rfdi(DisasContext *ctx) 5157 { 5158 #if defined(CONFIG_USER_ONLY) 5159 GEN_PRIV(ctx); 5160 #else 5161 CHK_SV(ctx); 5162 /* Restore CPU state */ 5163 gen_helper_rfdi(tcg_env); 5164 ctx->base.is_jmp = DISAS_EXIT; 5165 #endif /* defined(CONFIG_USER_ONLY) */ 5166 } 5167 5168 /* XXX: not implemented on 440 ? */ 5169 static void gen_rfmci(DisasContext *ctx) 5170 { 5171 #if defined(CONFIG_USER_ONLY) 5172 GEN_PRIV(ctx); 5173 #else 5174 CHK_SV(ctx); 5175 /* Restore CPU state */ 5176 gen_helper_rfmci(tcg_env); 5177 ctx->base.is_jmp = DISAS_EXIT; 5178 #endif /* defined(CONFIG_USER_ONLY) */ 5179 } 5180 5181 /* TLB management - PowerPC 405 implementation */ 5182 5183 /* tlbre */ 5184 static void gen_tlbre_40x(DisasContext *ctx) 5185 { 5186 #if defined(CONFIG_USER_ONLY) 5187 GEN_PRIV(ctx); 5188 #else 5189 CHK_SV(ctx); 5190 switch (rB(ctx->opcode)) { 5191 case 0: 5192 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], tcg_env, 5193 cpu_gpr[rA(ctx->opcode)]); 5194 break; 5195 case 1: 5196 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], tcg_env, 5197 cpu_gpr[rA(ctx->opcode)]); 5198 break; 5199 default: 5200 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5201 break; 5202 } 5203 #endif /* defined(CONFIG_USER_ONLY) */ 5204 } 5205 5206 /* tlbsx - tlbsx. */ 5207 static void gen_tlbsx_40x(DisasContext *ctx) 5208 { 5209 #if defined(CONFIG_USER_ONLY) 5210 GEN_PRIV(ctx); 5211 #else 5212 TCGv t0; 5213 5214 CHK_SV(ctx); 5215 t0 = tcg_temp_new(); 5216 gen_addr_reg_index(ctx, t0); 5217 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5218 if (Rc(ctx->opcode)) { 5219 TCGLabel *l1 = gen_new_label(); 5220 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5221 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5222 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5223 gen_set_label(l1); 5224 } 5225 #endif /* defined(CONFIG_USER_ONLY) */ 5226 } 5227 5228 /* tlbwe */ 5229 static void gen_tlbwe_40x(DisasContext *ctx) 5230 { 5231 #if defined(CONFIG_USER_ONLY) 5232 GEN_PRIV(ctx); 5233 #else 5234 CHK_SV(ctx); 5235 5236 switch (rB(ctx->opcode)) { 5237 case 0: 5238 gen_helper_4xx_tlbwe_hi(tcg_env, cpu_gpr[rA(ctx->opcode)], 5239 cpu_gpr[rS(ctx->opcode)]); 5240 break; 5241 case 1: 5242 gen_helper_4xx_tlbwe_lo(tcg_env, cpu_gpr[rA(ctx->opcode)], 5243 cpu_gpr[rS(ctx->opcode)]); 5244 break; 5245 default: 5246 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5247 break; 5248 } 5249 #endif /* defined(CONFIG_USER_ONLY) */ 5250 } 5251 5252 /* TLB management - PowerPC 440 implementation */ 5253 5254 /* tlbre */ 5255 static void gen_tlbre_440(DisasContext *ctx) 5256 { 5257 #if defined(CONFIG_USER_ONLY) 5258 GEN_PRIV(ctx); 5259 #else 5260 CHK_SV(ctx); 5261 5262 switch (rB(ctx->opcode)) { 5263 case 0: 5264 case 1: 5265 case 2: 5266 { 5267 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5268 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], tcg_env, 5269 t0, cpu_gpr[rA(ctx->opcode)]); 5270 } 5271 break; 5272 default: 5273 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5274 break; 5275 } 5276 #endif /* defined(CONFIG_USER_ONLY) */ 5277 } 5278 5279 /* tlbsx - tlbsx. */ 5280 static void gen_tlbsx_440(DisasContext *ctx) 5281 { 5282 #if defined(CONFIG_USER_ONLY) 5283 GEN_PRIV(ctx); 5284 #else 5285 TCGv t0; 5286 5287 CHK_SV(ctx); 5288 t0 = tcg_temp_new(); 5289 gen_addr_reg_index(ctx, t0); 5290 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5291 if (Rc(ctx->opcode)) { 5292 TCGLabel *l1 = gen_new_label(); 5293 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5294 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5295 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5296 gen_set_label(l1); 5297 } 5298 #endif /* defined(CONFIG_USER_ONLY) */ 5299 } 5300 5301 /* tlbwe */ 5302 static void gen_tlbwe_440(DisasContext *ctx) 5303 { 5304 #if defined(CONFIG_USER_ONLY) 5305 GEN_PRIV(ctx); 5306 #else 5307 CHK_SV(ctx); 5308 switch (rB(ctx->opcode)) { 5309 case 0: 5310 case 1: 5311 case 2: 5312 { 5313 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5314 gen_helper_440_tlbwe(tcg_env, t0, cpu_gpr[rA(ctx->opcode)], 5315 cpu_gpr[rS(ctx->opcode)]); 5316 } 5317 break; 5318 default: 5319 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5320 break; 5321 } 5322 #endif /* defined(CONFIG_USER_ONLY) */ 5323 } 5324 5325 /* TLB management - PowerPC BookE 2.06 implementation */ 5326 5327 /* tlbre */ 5328 static void gen_tlbre_booke206(DisasContext *ctx) 5329 { 5330 #if defined(CONFIG_USER_ONLY) 5331 GEN_PRIV(ctx); 5332 #else 5333 CHK_SV(ctx); 5334 gen_helper_booke206_tlbre(tcg_env); 5335 #endif /* defined(CONFIG_USER_ONLY) */ 5336 } 5337 5338 /* tlbsx - tlbsx. */ 5339 static void gen_tlbsx_booke206(DisasContext *ctx) 5340 { 5341 #if defined(CONFIG_USER_ONLY) 5342 GEN_PRIV(ctx); 5343 #else 5344 TCGv t0; 5345 5346 CHK_SV(ctx); 5347 if (rA(ctx->opcode)) { 5348 t0 = tcg_temp_new(); 5349 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5350 } else { 5351 t0 = cpu_gpr[rB(ctx->opcode)]; 5352 } 5353 gen_helper_booke206_tlbsx(tcg_env, t0); 5354 #endif /* defined(CONFIG_USER_ONLY) */ 5355 } 5356 5357 /* tlbwe */ 5358 static void gen_tlbwe_booke206(DisasContext *ctx) 5359 { 5360 #if defined(CONFIG_USER_ONLY) 5361 GEN_PRIV(ctx); 5362 #else 5363 CHK_SV(ctx); 5364 gen_helper_booke206_tlbwe(tcg_env); 5365 #endif /* defined(CONFIG_USER_ONLY) */ 5366 } 5367 5368 static void gen_tlbivax_booke206(DisasContext *ctx) 5369 { 5370 #if defined(CONFIG_USER_ONLY) 5371 GEN_PRIV(ctx); 5372 #else 5373 TCGv t0; 5374 5375 CHK_SV(ctx); 5376 t0 = tcg_temp_new(); 5377 gen_addr_reg_index(ctx, t0); 5378 gen_helper_booke206_tlbivax(tcg_env, t0); 5379 #endif /* defined(CONFIG_USER_ONLY) */ 5380 } 5381 5382 static void gen_tlbilx_booke206(DisasContext *ctx) 5383 { 5384 #if defined(CONFIG_USER_ONLY) 5385 GEN_PRIV(ctx); 5386 #else 5387 TCGv t0; 5388 5389 CHK_SV(ctx); 5390 t0 = tcg_temp_new(); 5391 gen_addr_reg_index(ctx, t0); 5392 5393 switch ((ctx->opcode >> 21) & 0x3) { 5394 case 0: 5395 gen_helper_booke206_tlbilx0(tcg_env, t0); 5396 break; 5397 case 1: 5398 gen_helper_booke206_tlbilx1(tcg_env, t0); 5399 break; 5400 case 3: 5401 gen_helper_booke206_tlbilx3(tcg_env, t0); 5402 break; 5403 default: 5404 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5405 break; 5406 } 5407 #endif /* defined(CONFIG_USER_ONLY) */ 5408 } 5409 5410 /* wrtee */ 5411 static void gen_wrtee(DisasContext *ctx) 5412 { 5413 #if defined(CONFIG_USER_ONLY) 5414 GEN_PRIV(ctx); 5415 #else 5416 TCGv t0; 5417 5418 CHK_SV(ctx); 5419 t0 = tcg_temp_new(); 5420 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5421 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5422 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 5423 gen_ppc_maybe_interrupt(ctx); 5424 /* 5425 * Stop translation to have a chance to raise an exception if we 5426 * just set msr_ee to 1 5427 */ 5428 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5429 #endif /* defined(CONFIG_USER_ONLY) */ 5430 } 5431 5432 /* wrteei */ 5433 static void gen_wrteei(DisasContext *ctx) 5434 { 5435 #if defined(CONFIG_USER_ONLY) 5436 GEN_PRIV(ctx); 5437 #else 5438 CHK_SV(ctx); 5439 if (ctx->opcode & 0x00008000) { 5440 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 5441 gen_ppc_maybe_interrupt(ctx); 5442 /* Stop translation to have a chance to raise an exception */ 5443 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5444 } else { 5445 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5446 } 5447 #endif /* defined(CONFIG_USER_ONLY) */ 5448 } 5449 5450 /* PowerPC 440 specific instructions */ 5451 5452 /* dlmzb */ 5453 static void gen_dlmzb(DisasContext *ctx) 5454 { 5455 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 5456 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], tcg_env, 5457 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 5458 } 5459 5460 /* icbt */ 5461 static void gen_icbt_440(DisasContext *ctx) 5462 { 5463 /* 5464 * interpreted as no-op 5465 * XXX: specification say this is treated as a load by the MMU but 5466 * does not generate any exception 5467 */ 5468 } 5469 5470 static void gen_tbegin(DisasContext *ctx) 5471 { 5472 if (unlikely(!ctx->tm_enabled)) { 5473 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 5474 return; 5475 } 5476 gen_helper_tbegin(tcg_env); 5477 } 5478 5479 #define GEN_TM_NOOP(name) \ 5480 static inline void gen_##name(DisasContext *ctx) \ 5481 { \ 5482 if (unlikely(!ctx->tm_enabled)) { \ 5483 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 5484 return; \ 5485 } \ 5486 /* \ 5487 * Because tbegin always fails in QEMU, these user \ 5488 * space instructions all have a simple implementation: \ 5489 * \ 5490 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 5491 * = 0b0 || 0b00 || 0b0 \ 5492 */ \ 5493 tcg_gen_movi_i32(cpu_crf[0], 0); \ 5494 } 5495 5496 GEN_TM_NOOP(tend); 5497 GEN_TM_NOOP(tabort); 5498 GEN_TM_NOOP(tabortwc); 5499 GEN_TM_NOOP(tabortwci); 5500 GEN_TM_NOOP(tabortdc); 5501 GEN_TM_NOOP(tabortdci); 5502 GEN_TM_NOOP(tsr); 5503 5504 static inline void gen_cp_abort(DisasContext *ctx) 5505 { 5506 /* Do Nothing */ 5507 } 5508 5509 #define GEN_CP_PASTE_NOOP(name) \ 5510 static inline void gen_##name(DisasContext *ctx) \ 5511 { \ 5512 /* \ 5513 * Generate invalid exception until we have an \ 5514 * implementation of the copy paste facility \ 5515 */ \ 5516 gen_invalid(ctx); \ 5517 } 5518 5519 GEN_CP_PASTE_NOOP(copy) 5520 GEN_CP_PASTE_NOOP(paste) 5521 5522 static void gen_tcheck(DisasContext *ctx) 5523 { 5524 if (unlikely(!ctx->tm_enabled)) { 5525 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 5526 return; 5527 } 5528 /* 5529 * Because tbegin always fails, the tcheck implementation is 5530 * simple: 5531 * 5532 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 5533 * = 0b1 || 0b00 || 0b0 5534 */ 5535 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 5536 } 5537 5538 #if defined(CONFIG_USER_ONLY) 5539 #define GEN_TM_PRIV_NOOP(name) \ 5540 static inline void gen_##name(DisasContext *ctx) \ 5541 { \ 5542 gen_priv_opc(ctx); \ 5543 } 5544 5545 #else 5546 5547 #define GEN_TM_PRIV_NOOP(name) \ 5548 static inline void gen_##name(DisasContext *ctx) \ 5549 { \ 5550 CHK_SV(ctx); \ 5551 if (unlikely(!ctx->tm_enabled)) { \ 5552 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 5553 return; \ 5554 } \ 5555 /* \ 5556 * Because tbegin always fails, the implementation is \ 5557 * simple: \ 5558 * \ 5559 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 5560 * = 0b0 || 0b00 | 0b0 \ 5561 */ \ 5562 tcg_gen_movi_i32(cpu_crf[0], 0); \ 5563 } 5564 5565 #endif 5566 5567 GEN_TM_PRIV_NOOP(treclaim); 5568 GEN_TM_PRIV_NOOP(trechkpt); 5569 5570 static inline void get_fpr(TCGv_i64 dst, int regno) 5571 { 5572 tcg_gen_ld_i64(dst, tcg_env, fpr_offset(regno)); 5573 } 5574 5575 static inline void set_fpr(int regno, TCGv_i64 src) 5576 { 5577 tcg_gen_st_i64(src, tcg_env, fpr_offset(regno)); 5578 /* 5579 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 5580 * corresponding to the target FPR was undefined. However, 5581 * most (if not all) real hardware were setting the result to 0. 5582 * Starting at ISA v3.1, the result for doubleword 1 is now defined 5583 * to be 0. 5584 */ 5585 tcg_gen_st_i64(tcg_constant_i64(0), tcg_env, vsr64_offset(regno, false)); 5586 } 5587 5588 /* 5589 * Helpers for decodetree used by !function for decoding arguments. 5590 */ 5591 static int times_2(DisasContext *ctx, int x) 5592 { 5593 return x * 2; 5594 } 5595 5596 static int times_4(DisasContext *ctx, int x) 5597 { 5598 return x * 4; 5599 } 5600 5601 static int times_16(DisasContext *ctx, int x) 5602 { 5603 return x * 16; 5604 } 5605 5606 static int64_t dw_compose_ea(DisasContext *ctx, int x) 5607 { 5608 return deposit64(0xfffffffffffffe00, 3, 6, x); 5609 } 5610 5611 /* 5612 * Helpers for trans_* functions to check for specific insns flags. 5613 * Use token pasting to ensure that we use the proper flag with the 5614 * proper variable. 5615 */ 5616 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 5617 do { \ 5618 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 5619 return false; \ 5620 } \ 5621 } while (0) 5622 5623 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 5624 do { \ 5625 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 5626 return false; \ 5627 } \ 5628 } while (0) 5629 5630 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 5631 #if TARGET_LONG_BITS == 32 5632 # define REQUIRE_64BIT(CTX) return false 5633 #else 5634 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 5635 #endif 5636 5637 #define REQUIRE_VECTOR(CTX) \ 5638 do { \ 5639 if (unlikely(!(CTX)->altivec_enabled)) { \ 5640 gen_exception((CTX), POWERPC_EXCP_VPU); \ 5641 return true; \ 5642 } \ 5643 } while (0) 5644 5645 #define REQUIRE_VSX(CTX) \ 5646 do { \ 5647 if (unlikely(!(CTX)->vsx_enabled)) { \ 5648 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 5649 return true; \ 5650 } \ 5651 } while (0) 5652 5653 #define REQUIRE_FPU(ctx) \ 5654 do { \ 5655 if (unlikely(!(ctx)->fpu_enabled)) { \ 5656 gen_exception((ctx), POWERPC_EXCP_FPU); \ 5657 return true; \ 5658 } \ 5659 } while (0) 5660 5661 #if !defined(CONFIG_USER_ONLY) 5662 #define REQUIRE_SV(CTX) \ 5663 do { \ 5664 if (unlikely((CTX)->pr)) { \ 5665 gen_priv_opc(CTX); \ 5666 return true; \ 5667 } \ 5668 } while (0) 5669 5670 #define REQUIRE_HV(CTX) \ 5671 do { \ 5672 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 5673 gen_priv_opc(CTX); \ 5674 return true; \ 5675 } \ 5676 } while (0) 5677 #else 5678 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 5679 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 5680 #endif 5681 5682 /* 5683 * Helpers for implementing sets of trans_* functions. 5684 * Defer the implementation of NAME to FUNC, with optional extra arguments. 5685 */ 5686 #define TRANS(NAME, FUNC, ...) \ 5687 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5688 { return FUNC(ctx, a, __VA_ARGS__); } 5689 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 5690 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5691 { \ 5692 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 5693 return FUNC(ctx, a, __VA_ARGS__); \ 5694 } 5695 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 5696 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5697 { \ 5698 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 5699 return FUNC(ctx, a, __VA_ARGS__); \ 5700 } 5701 5702 #define TRANS64(NAME, FUNC, ...) \ 5703 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5704 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 5705 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 5706 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5707 { \ 5708 REQUIRE_64BIT(ctx); \ 5709 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 5710 return FUNC(ctx, a, __VA_ARGS__); \ 5711 } 5712 5713 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 5714 5715 5716 #include "decode-insn32.c.inc" 5717 #include "decode-insn64.c.inc" 5718 #include "power8-pmu-regs.c.inc" 5719 5720 /* 5721 * Incorporate CIA into the constant when R=1. 5722 * Validate that when R=1, RA=0. 5723 */ 5724 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 5725 { 5726 d->rt = a->rt; 5727 d->ra = a->ra; 5728 d->si = a->si; 5729 if (a->r) { 5730 if (unlikely(a->ra != 0)) { 5731 gen_invalid(ctx); 5732 return false; 5733 } 5734 d->si += ctx->cia; 5735 } 5736 return true; 5737 } 5738 5739 #include "translate/fixedpoint-impl.c.inc" 5740 5741 #include "translate/fp-impl.c.inc" 5742 5743 #include "translate/vmx-impl.c.inc" 5744 5745 #include "translate/vsx-impl.c.inc" 5746 5747 #include "translate/dfp-impl.c.inc" 5748 5749 #include "translate/spe-impl.c.inc" 5750 5751 #include "translate/branch-impl.c.inc" 5752 5753 #include "translate/processor-ctrl-impl.c.inc" 5754 5755 #include "translate/storage-ctrl-impl.c.inc" 5756 5757 #include "translate/misc-impl.c.inc" 5758 5759 #include "translate/bhrb-impl.c.inc" 5760 5761 /* Handles lfdp */ 5762 static void gen_dform39(DisasContext *ctx) 5763 { 5764 if ((ctx->opcode & 0x3) == 0) { 5765 if (ctx->insns_flags2 & PPC2_ISA205) { 5766 return gen_lfdp(ctx); 5767 } 5768 } 5769 return gen_invalid(ctx); 5770 } 5771 5772 /* Handles stfdp */ 5773 static void gen_dform3D(DisasContext *ctx) 5774 { 5775 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 5776 /* stfdp */ 5777 if (ctx->insns_flags2 & PPC2_ISA205) { 5778 return gen_stfdp(ctx); 5779 } 5780 } 5781 return gen_invalid(ctx); 5782 } 5783 5784 #if defined(TARGET_PPC64) 5785 /* brd */ 5786 static void gen_brd(DisasContext *ctx) 5787 { 5788 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 5789 } 5790 5791 /* brw */ 5792 static void gen_brw(DisasContext *ctx) 5793 { 5794 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 5795 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 5796 5797 } 5798 5799 /* brh */ 5800 static void gen_brh(DisasContext *ctx) 5801 { 5802 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 5803 TCGv_i64 t1 = tcg_temp_new_i64(); 5804 TCGv_i64 t2 = tcg_temp_new_i64(); 5805 5806 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 5807 tcg_gen_and_i64(t2, t1, mask); 5808 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 5809 tcg_gen_shli_i64(t1, t1, 8); 5810 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 5811 } 5812 #endif 5813 5814 static opcode_t opcodes[] = { 5815 #if defined(TARGET_PPC64) 5816 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 5817 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 5818 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 5819 #endif 5820 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 5821 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 5822 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 5823 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 5824 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5825 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5826 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5827 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 5828 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 5829 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 5830 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 5831 #if defined(TARGET_PPC64) 5832 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 5833 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 5834 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 5835 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 5836 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 5837 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 5838 PPC_NONE, PPC2_ISA300), 5839 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 5840 PPC_NONE, PPC2_ISA300), 5841 #endif 5842 /* handles lfdp, lxsd, lxssp */ 5843 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 5844 /* handles stfdp, stxsd, stxssp */ 5845 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 5846 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5847 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5848 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 5849 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 5850 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 5851 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 5852 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 5853 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5854 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5855 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 5856 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 5857 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 5858 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5859 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5860 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 5861 #if defined(TARGET_PPC64) 5862 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 5863 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 5864 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 5865 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 5866 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 5867 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 5868 #endif 5869 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 5870 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 5871 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 5872 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 5873 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 5874 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 5875 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 5876 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 5877 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 5878 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 5879 #if defined(TARGET_PPC64) 5880 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 5881 #if !defined(CONFIG_USER_ONLY) 5882 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 5883 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 5884 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 5885 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 5886 #endif 5887 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 5888 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5889 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5890 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5891 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5892 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 5893 #endif 5894 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 5895 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 5896 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 5897 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 5898 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 5899 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 5900 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 5901 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 5902 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 5903 #if defined(TARGET_PPC64) 5904 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 5905 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 5906 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 5907 #endif 5908 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 5909 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 5910 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 5911 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 5912 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 5913 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 5914 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 5915 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 5916 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 5917 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 5918 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 5919 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 5920 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 5921 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 5922 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 5923 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 5924 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 5925 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 5926 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 5927 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 5928 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 5929 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 5930 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 5931 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 5932 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 5933 #if defined(TARGET_PPC64) 5934 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 5935 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 5936 PPC_SEGMENT_64B), 5937 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 5938 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 5939 PPC_SEGMENT_64B), 5940 #endif 5941 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 5942 /* 5943 * XXX Those instructions will need to be handled differently for 5944 * different ISA versions 5945 */ 5946 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 5947 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 5948 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 5949 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 5950 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 5951 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 5952 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 5953 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 5954 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 5955 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 5956 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 5957 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 5958 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 5959 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 5960 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 5961 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 5962 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 5963 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 5964 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 5965 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 5966 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 5967 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 5968 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 5969 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 5970 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 5971 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 5972 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 5973 PPC_NONE, PPC2_BOOKE206), 5974 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 5975 PPC_NONE, PPC2_BOOKE206), 5976 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 5977 PPC_NONE, PPC2_BOOKE206), 5978 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 5979 PPC_NONE, PPC2_BOOKE206), 5980 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 5981 PPC_NONE, PPC2_BOOKE206), 5982 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 5983 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 5984 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 5985 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 5986 PPC_BOOKE, PPC2_BOOKE206), 5987 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 5988 PPC_440_SPEC), 5989 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 5990 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 5991 5992 #if defined(TARGET_PPC64) 5993 #undef GEN_PPC64_R2 5994 #undef GEN_PPC64_R4 5995 #define GEN_PPC64_R2(name, opc1, opc2) \ 5996 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 5997 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 5998 PPC_64B) 5999 #define GEN_PPC64_R4(name, opc1, opc2) \ 6000 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6001 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6002 PPC_64B), \ 6003 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6004 PPC_64B), \ 6005 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6006 PPC_64B) 6007 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6008 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6009 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6010 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6011 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6012 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6013 #endif 6014 6015 #undef GEN_LDX_E 6016 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6017 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6018 6019 #if defined(TARGET_PPC64) 6020 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6021 6022 /* HV/P7 and later only */ 6023 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6024 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6025 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6026 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6027 #endif 6028 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6029 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6030 6031 /* External PID based load */ 6032 #undef GEN_LDEPX 6033 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6034 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6035 0x00000001, PPC_NONE, PPC2_BOOKE206), 6036 6037 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6038 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6039 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6040 #if defined(TARGET_PPC64) 6041 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6042 #endif 6043 6044 #undef GEN_STX_E 6045 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6046 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6047 6048 #if defined(TARGET_PPC64) 6049 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6050 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6051 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6052 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6053 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6054 #endif 6055 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6056 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6057 6058 #undef GEN_STEPX 6059 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6060 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6061 0x00000001, PPC_NONE, PPC2_BOOKE206), 6062 6063 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6064 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6065 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6066 #if defined(TARGET_PPC64) 6067 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6068 #endif 6069 6070 #undef GEN_CRLOGIC 6071 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6072 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6073 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6074 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6075 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6076 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6077 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6078 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6079 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6080 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6081 6082 #undef GEN_MAC_HANDLER 6083 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6084 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6085 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6086 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6087 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6088 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6089 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6090 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6091 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6092 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6093 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6094 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6095 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6096 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6097 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6098 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6099 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6100 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6101 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6102 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6103 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6104 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6105 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6106 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6107 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6108 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6109 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6110 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6111 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6112 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6113 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6114 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6115 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6116 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6117 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6118 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6119 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6120 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6121 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6122 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6123 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6124 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6125 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6126 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6127 6128 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6129 PPC_NONE, PPC2_TM), 6130 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6131 PPC_NONE, PPC2_TM), 6132 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6133 PPC_NONE, PPC2_TM), 6134 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6135 PPC_NONE, PPC2_TM), 6136 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6137 PPC_NONE, PPC2_TM), 6138 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6139 PPC_NONE, PPC2_TM), 6140 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6141 PPC_NONE, PPC2_TM), 6142 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6143 PPC_NONE, PPC2_TM), 6144 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6145 PPC_NONE, PPC2_TM), 6146 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6147 PPC_NONE, PPC2_TM), 6148 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6149 PPC_NONE, PPC2_TM), 6150 6151 #include "translate/fp-ops.c.inc" 6152 6153 #include "translate/vmx-ops.c.inc" 6154 6155 #include "translate/vsx-ops.c.inc" 6156 6157 #include "translate/spe-ops.c.inc" 6158 }; 6159 6160 /*****************************************************************************/ 6161 /* Opcode types */ 6162 enum { 6163 PPC_DIRECT = 0, /* Opcode routine */ 6164 PPC_INDIRECT = 1, /* Indirect opcode table */ 6165 }; 6166 6167 #define PPC_OPCODE_MASK 0x3 6168 6169 static inline int is_indirect_opcode(void *handler) 6170 { 6171 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6172 } 6173 6174 static inline opc_handler_t **ind_table(void *handler) 6175 { 6176 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6177 } 6178 6179 /* Instruction table creation */ 6180 /* Opcodes tables creation */ 6181 static void fill_new_table(opc_handler_t **table, int len) 6182 { 6183 int i; 6184 6185 for (i = 0; i < len; i++) { 6186 table[i] = &invalid_handler; 6187 } 6188 } 6189 6190 static int create_new_table(opc_handler_t **table, unsigned char idx) 6191 { 6192 opc_handler_t **tmp; 6193 6194 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6195 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6196 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6197 6198 return 0; 6199 } 6200 6201 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6202 opc_handler_t *handler) 6203 { 6204 if (table[idx] != &invalid_handler) { 6205 return -1; 6206 } 6207 table[idx] = handler; 6208 6209 return 0; 6210 } 6211 6212 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6213 unsigned char idx, opc_handler_t *handler) 6214 { 6215 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 6216 printf("*** ERROR: opcode %02x already assigned in main " 6217 "opcode table\n", idx); 6218 return -1; 6219 } 6220 6221 return 0; 6222 } 6223 6224 static int register_ind_in_table(opc_handler_t **table, 6225 unsigned char idx1, unsigned char idx2, 6226 opc_handler_t *handler) 6227 { 6228 if (table[idx1] == &invalid_handler) { 6229 if (create_new_table(table, idx1) < 0) { 6230 printf("*** ERROR: unable to create indirect table " 6231 "idx=%02x\n", idx1); 6232 return -1; 6233 } 6234 } else { 6235 if (!is_indirect_opcode(table[idx1])) { 6236 printf("*** ERROR: idx %02x already assigned to a direct " 6237 "opcode\n", idx1); 6238 return -1; 6239 } 6240 } 6241 if (handler != NULL && 6242 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 6243 printf("*** ERROR: opcode %02x already assigned in " 6244 "opcode table %02x\n", idx2, idx1); 6245 return -1; 6246 } 6247 6248 return 0; 6249 } 6250 6251 static int register_ind_insn(opc_handler_t **ppc_opcodes, 6252 unsigned char idx1, unsigned char idx2, 6253 opc_handler_t *handler) 6254 { 6255 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 6256 } 6257 6258 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 6259 unsigned char idx1, unsigned char idx2, 6260 unsigned char idx3, opc_handler_t *handler) 6261 { 6262 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6263 printf("*** ERROR: unable to join indirect table idx " 6264 "[%02x-%02x]\n", idx1, idx2); 6265 return -1; 6266 } 6267 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 6268 handler) < 0) { 6269 printf("*** ERROR: unable to insert opcode " 6270 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6271 return -1; 6272 } 6273 6274 return 0; 6275 } 6276 6277 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 6278 unsigned char idx1, unsigned char idx2, 6279 unsigned char idx3, unsigned char idx4, 6280 opc_handler_t *handler) 6281 { 6282 opc_handler_t **table; 6283 6284 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6285 printf("*** ERROR: unable to join indirect table idx " 6286 "[%02x-%02x]\n", idx1, idx2); 6287 return -1; 6288 } 6289 table = ind_table(ppc_opcodes[idx1]); 6290 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 6291 printf("*** ERROR: unable to join 2nd-level indirect table idx " 6292 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6293 return -1; 6294 } 6295 table = ind_table(table[idx2]); 6296 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 6297 printf("*** ERROR: unable to insert opcode " 6298 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 6299 return -1; 6300 } 6301 return 0; 6302 } 6303 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 6304 { 6305 if (insn->opc2 != 0xFF) { 6306 if (insn->opc3 != 0xFF) { 6307 if (insn->opc4 != 0xFF) { 6308 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 6309 insn->opc3, insn->opc4, 6310 &insn->handler) < 0) { 6311 return -1; 6312 } 6313 } else { 6314 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 6315 insn->opc3, &insn->handler) < 0) { 6316 return -1; 6317 } 6318 } 6319 } else { 6320 if (register_ind_insn(ppc_opcodes, insn->opc1, 6321 insn->opc2, &insn->handler) < 0) { 6322 return -1; 6323 } 6324 } 6325 } else { 6326 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 6327 return -1; 6328 } 6329 } 6330 6331 return 0; 6332 } 6333 6334 static int test_opcode_table(opc_handler_t **table, int len) 6335 { 6336 int i, count, tmp; 6337 6338 for (i = 0, count = 0; i < len; i++) { 6339 /* Consistency fixup */ 6340 if (table[i] == NULL) { 6341 table[i] = &invalid_handler; 6342 } 6343 if (table[i] != &invalid_handler) { 6344 if (is_indirect_opcode(table[i])) { 6345 tmp = test_opcode_table(ind_table(table[i]), 6346 PPC_CPU_INDIRECT_OPCODES_LEN); 6347 if (tmp == 0) { 6348 g_free(table[i]); 6349 table[i] = &invalid_handler; 6350 } else { 6351 count++; 6352 } 6353 } else { 6354 count++; 6355 } 6356 } 6357 } 6358 6359 return count; 6360 } 6361 6362 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 6363 { 6364 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 6365 printf("*** WARNING: no opcode defined !\n"); 6366 } 6367 } 6368 6369 /*****************************************************************************/ 6370 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 6371 { 6372 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6373 opcode_t *opc; 6374 6375 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 6376 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 6377 if (((opc->handler.type & pcc->insns_flags) != 0) || 6378 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 6379 if (register_insn(cpu->opcodes, opc) < 0) { 6380 error_setg(errp, "ERROR initializing PowerPC instruction " 6381 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 6382 opc->opc3); 6383 return; 6384 } 6385 } 6386 } 6387 fix_opcode_tables(cpu->opcodes); 6388 fflush(stdout); 6389 fflush(stderr); 6390 } 6391 6392 void destroy_ppc_opcodes(PowerPCCPU *cpu) 6393 { 6394 opc_handler_t **table, **table_2; 6395 int i, j, k; 6396 6397 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 6398 if (cpu->opcodes[i] == &invalid_handler) { 6399 continue; 6400 } 6401 if (is_indirect_opcode(cpu->opcodes[i])) { 6402 table = ind_table(cpu->opcodes[i]); 6403 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 6404 if (table[j] == &invalid_handler) { 6405 continue; 6406 } 6407 if (is_indirect_opcode(table[j])) { 6408 table_2 = ind_table(table[j]); 6409 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 6410 if (table_2[k] != &invalid_handler && 6411 is_indirect_opcode(table_2[k])) { 6412 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 6413 ~PPC_INDIRECT)); 6414 } 6415 } 6416 g_free((opc_handler_t *)((uintptr_t)table[j] & 6417 ~PPC_INDIRECT)); 6418 } 6419 } 6420 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 6421 ~PPC_INDIRECT)); 6422 } 6423 } 6424 } 6425 6426 int ppc_fixup_cpu(PowerPCCPU *cpu) 6427 { 6428 CPUPPCState *env = &cpu->env; 6429 6430 /* 6431 * TCG doesn't (yet) emulate some groups of instructions that are 6432 * implemented on some otherwise supported CPUs (e.g. VSX and 6433 * decimal floating point instructions on POWER7). We remove 6434 * unsupported instruction groups from the cpu state's instruction 6435 * masks and hope the guest can cope. For at least the pseries 6436 * machine, the unavailability of these instructions can be 6437 * advertised to the guest via the device tree. 6438 */ 6439 if ((env->insns_flags & ~PPC_TCG_INSNS) 6440 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 6441 warn_report("Disabling some instructions which are not " 6442 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 6443 env->insns_flags & ~PPC_TCG_INSNS, 6444 env->insns_flags2 & ~PPC_TCG_INSNS2); 6445 } 6446 env->insns_flags &= PPC_TCG_INSNS; 6447 env->insns_flags2 &= PPC_TCG_INSNS2; 6448 return 0; 6449 } 6450 6451 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 6452 { 6453 opc_handler_t **table, *handler; 6454 uint32_t inval; 6455 6456 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 6457 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 6458 ctx->le_mode ? "little" : "big"); 6459 6460 table = cpu->opcodes; 6461 handler = table[opc1(insn)]; 6462 if (is_indirect_opcode(handler)) { 6463 table = ind_table(handler); 6464 handler = table[opc2(insn)]; 6465 if (is_indirect_opcode(handler)) { 6466 table = ind_table(handler); 6467 handler = table[opc3(insn)]; 6468 if (is_indirect_opcode(handler)) { 6469 table = ind_table(handler); 6470 handler = table[opc4(insn)]; 6471 } 6472 } 6473 } 6474 6475 /* Is opcode *REALLY* valid ? */ 6476 if (unlikely(handler->handler == &gen_invalid)) { 6477 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 6478 "%02x - %02x - %02x - %02x (%08x) " 6479 TARGET_FMT_lx "\n", 6480 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 6481 insn, ctx->cia); 6482 return false; 6483 } 6484 6485 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 6486 && Rc(insn))) { 6487 inval = handler->inval2; 6488 } else { 6489 inval = handler->inval1; 6490 } 6491 6492 if (unlikely((insn & inval) != 0)) { 6493 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 6494 "%02x - %02x - %02x - %02x (%08x) " 6495 TARGET_FMT_lx "\n", insn & inval, 6496 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 6497 insn, ctx->cia); 6498 return false; 6499 } 6500 6501 handler->handler(ctx); 6502 return true; 6503 } 6504 6505 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 6506 { 6507 DisasContext *ctx = container_of(dcbase, DisasContext, base); 6508 CPUPPCState *env = cpu_env(cs); 6509 uint32_t hflags = ctx->base.tb->flags; 6510 6511 ctx->spr_cb = env->spr_cb; 6512 ctx->pr = (hflags >> HFLAGS_PR) & 1; 6513 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 6514 ctx->dr = (hflags >> HFLAGS_DR) & 1; 6515 ctx->hv = (hflags >> HFLAGS_HV) & 1; 6516 ctx->insns_flags = env->insns_flags; 6517 ctx->insns_flags2 = env->insns_flags2; 6518 ctx->access_type = -1; 6519 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 6520 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 6521 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 6522 ctx->flags = env->flags; 6523 #if defined(TARGET_PPC64) 6524 ctx->excp_model = env->excp_model; 6525 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 6526 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 6527 ctx->has_bhrb = !!(env->flags & POWERPC_FLAG_BHRB); 6528 #endif 6529 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 6530 || env->mmu_model & POWERPC_MMU_64; 6531 6532 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 6533 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 6534 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 6535 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 6536 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 6537 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 6538 ctx->hr = (hflags >> HFLAGS_HR) & 1; 6539 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 6540 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 6541 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 6542 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 6543 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 6544 ctx->bhrb_enable = (hflags >> HFLAGS_BHRB_ENABLE) & 1; 6545 6546 ctx->singlestep_enabled = 0; 6547 if ((hflags >> HFLAGS_SE) & 1) { 6548 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 6549 ctx->base.max_insns = 1; 6550 } 6551 if ((hflags >> HFLAGS_BE) & 1) { 6552 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 6553 } 6554 } 6555 6556 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 6557 { 6558 } 6559 6560 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 6561 { 6562 tcg_gen_insn_start(dcbase->pc_next); 6563 } 6564 6565 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 6566 { 6567 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 6568 return opc1(insn) == 1; 6569 } 6570 6571 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 6572 { 6573 DisasContext *ctx = container_of(dcbase, DisasContext, base); 6574 PowerPCCPU *cpu = POWERPC_CPU(cs); 6575 CPUPPCState *env = cpu_env(cs); 6576 target_ulong pc; 6577 uint32_t insn; 6578 bool ok; 6579 6580 LOG_DISAS("----------------\n"); 6581 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 6582 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 6583 6584 ctx->cia = pc = ctx->base.pc_next; 6585 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 6586 ctx->base.pc_next = pc += 4; 6587 6588 if (!is_prefix_insn(ctx, insn)) { 6589 ctx->opcode = insn; 6590 ok = (decode_insn32(ctx, insn) || 6591 decode_legacy(cpu, ctx, insn)); 6592 } else if ((pc & 63) == 0) { 6593 /* 6594 * Power v3.1, section 1.9 Exceptions: 6595 * attempt to execute a prefixed instruction that crosses a 6596 * 64-byte address boundary (system alignment error). 6597 */ 6598 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 6599 ok = true; 6600 } else { 6601 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 6602 need_byteswap(ctx)); 6603 ctx->base.pc_next = pc += 4; 6604 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 6605 } 6606 if (!ok) { 6607 gen_invalid(ctx); 6608 } 6609 6610 /* End the TB when crossing a page boundary. */ 6611 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 6612 ctx->base.is_jmp = DISAS_TOO_MANY; 6613 } 6614 } 6615 6616 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 6617 { 6618 DisasContext *ctx = container_of(dcbase, DisasContext, base); 6619 DisasJumpType is_jmp = ctx->base.is_jmp; 6620 target_ulong nip = ctx->base.pc_next; 6621 6622 if (is_jmp == DISAS_NORETURN) { 6623 /* We have already exited the TB. */ 6624 return; 6625 } 6626 6627 /* Honor single stepping. */ 6628 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { 6629 bool rfi_type = false; 6630 6631 switch (is_jmp) { 6632 case DISAS_TOO_MANY: 6633 case DISAS_EXIT_UPDATE: 6634 case DISAS_CHAIN_UPDATE: 6635 gen_update_nip(ctx, nip); 6636 break; 6637 case DISAS_EXIT: 6638 case DISAS_CHAIN: 6639 /* 6640 * This is a heuristic, to put it kindly. The rfi class of 6641 * instructions are among the few outside branches that change 6642 * NIP without taking an interrupt. Single step trace interrupts 6643 * do not fire on completion of these instructions. 6644 */ 6645 rfi_type = true; 6646 break; 6647 default: 6648 g_assert_not_reached(); 6649 } 6650 6651 gen_debug_exception(ctx, rfi_type); 6652 return; 6653 } 6654 6655 switch (is_jmp) { 6656 case DISAS_TOO_MANY: 6657 if (use_goto_tb(ctx, nip)) { 6658 pmu_count_insns(ctx); 6659 tcg_gen_goto_tb(0); 6660 gen_update_nip(ctx, nip); 6661 tcg_gen_exit_tb(ctx->base.tb, 0); 6662 break; 6663 } 6664 /* fall through */ 6665 case DISAS_CHAIN_UPDATE: 6666 gen_update_nip(ctx, nip); 6667 /* fall through */ 6668 case DISAS_CHAIN: 6669 /* 6670 * tcg_gen_lookup_and_goto_ptr will exit the TB if 6671 * CF_NO_GOTO_PTR is set. Count insns now. 6672 */ 6673 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 6674 pmu_count_insns(ctx); 6675 } 6676 6677 tcg_gen_lookup_and_goto_ptr(); 6678 break; 6679 6680 case DISAS_EXIT_UPDATE: 6681 gen_update_nip(ctx, nip); 6682 /* fall through */ 6683 case DISAS_EXIT: 6684 pmu_count_insns(ctx); 6685 tcg_gen_exit_tb(NULL, 0); 6686 break; 6687 6688 default: 6689 g_assert_not_reached(); 6690 } 6691 } 6692 6693 static const TranslatorOps ppc_tr_ops = { 6694 .init_disas_context = ppc_tr_init_disas_context, 6695 .tb_start = ppc_tr_tb_start, 6696 .insn_start = ppc_tr_insn_start, 6697 .translate_insn = ppc_tr_translate_insn, 6698 .tb_stop = ppc_tr_tb_stop, 6699 }; 6700 6701 void ppc_translate_code(CPUState *cs, TranslationBlock *tb, 6702 int *max_insns, vaddr pc, void *host_pc) 6703 { 6704 DisasContext ctx; 6705 6706 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 6707 } 6708