1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 38a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 39fcf5ef2aSThomas Huth 403e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 413e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 44fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 47efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51fcf5ef2aSThomas Huth #else 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 53fcf5ef2aSThomas Huth #endif 54fcf5ef2aSThomas Huth /*****************************************************************************/ 55fcf5ef2aSThomas Huth /* Code translation helpers */ 56fcf5ef2aSThomas Huth 57fcf5ef2aSThomas Huth /* global register indexes */ 58fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 60fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 64fcf5ef2aSThomas Huth static TCGv cpu_nip; 65fcf5ef2aSThomas Huth static TCGv cpu_msr; 66fcf5ef2aSThomas Huth static TCGv cpu_ctr; 67fcf5ef2aSThomas Huth static TCGv cpu_lr; 68fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 69fcf5ef2aSThomas Huth static TCGv cpu_cfar; 70fcf5ef2aSThomas Huth #endif 71dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72fcf5ef2aSThomas Huth static TCGv cpu_reserve; 73253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 74fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 75fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth void ppc_translate_init(void) 80fcf5ef2aSThomas Huth { 81fcf5ef2aSThomas Huth int i; 82fcf5ef2aSThomas Huth char *p; 83fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth p = cpu_reg_names; 86fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 89fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 90fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 92fcf5ef2aSThomas Huth p += 5; 93fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 94fcf5ef2aSThomas Huth } 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 97fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 98fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 100fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 101fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 103fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 110fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 122fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 128fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 130fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 132fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 134dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 135dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 136dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 138fcf5ef2aSThomas Huth 139fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 141fcf5ef2aSThomas Huth "reserve_addr"); 142253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 143253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 144253ce7b2SNikunj A Dadhania "reserve_val"); 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 151efe843d8SDavid Gibson "access_type"); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth /* internal defines */ 155fcf5ef2aSThomas Huth struct DisasContext { 156b6bac4bcSEmilio G. Cota DisasContextBase base; 1572c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 158fcf5ef2aSThomas Huth uint32_t opcode; 159fcf5ef2aSThomas Huth /* Routine used to access memory */ 160fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 161fcf5ef2aSThomas Huth bool lazy_tlb_flush; 162fcf5ef2aSThomas Huth bool need_access_type; 163fcf5ef2aSThomas Huth int mem_idx; 164fcf5ef2aSThomas Huth int access_type; 165fcf5ef2aSThomas Huth /* Translation flags */ 16614776ab5STony Nguyen MemOp default_tcg_memop_mask; 167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 168fcf5ef2aSThomas Huth bool sf_mode; 169fcf5ef2aSThomas Huth bool has_cfar; 170fcf5ef2aSThomas Huth #endif 171fcf5ef2aSThomas Huth bool fpu_enabled; 172fcf5ef2aSThomas Huth bool altivec_enabled; 173fcf5ef2aSThomas Huth bool vsx_enabled; 174fcf5ef2aSThomas Huth bool spe_enabled; 175fcf5ef2aSThomas Huth bool tm_enabled; 176c6fd28fdSSuraj Jitindar Singh bool gtse; 1771db3632aSMatheus Ferst bool hr; 178f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 179f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 18046d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 181fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 182fcf5ef2aSThomas Huth int singlestep_enabled; 1830e3bf489SRoman Kapl uint32_t flags; 184fcf5ef2aSThomas Huth uint64_t insns_flags; 185fcf5ef2aSThomas Huth uint64_t insns_flags2; 186fcf5ef2aSThomas Huth }; 187fcf5ef2aSThomas Huth 188a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 189a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 190a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 191a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 192a9b5b3d0SRichard Henderson 193fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 194fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 195fcf5ef2aSThomas Huth { 196fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 197fcf5ef2aSThomas Huth return ctx->le_mode; 198fcf5ef2aSThomas Huth #else 199fcf5ef2aSThomas Huth return !ctx->le_mode; 200fcf5ef2aSThomas Huth #endif 201fcf5ef2aSThomas Huth } 202fcf5ef2aSThomas Huth 203fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 204fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 205fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 206fcf5ef2aSThomas Huth #else 207fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 208fcf5ef2aSThomas Huth #endif 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth struct opc_handler_t { 211fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 212fcf5ef2aSThomas Huth uint32_t inval1; 213fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 214fcf5ef2aSThomas Huth uint32_t inval2; 215fcf5ef2aSThomas Huth /* instruction type */ 216fcf5ef2aSThomas Huth uint64_t type; 217fcf5ef2aSThomas Huth /* extended instruction type */ 218fcf5ef2aSThomas Huth uint64_t type2; 219fcf5ef2aSThomas Huth /* handler */ 220fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 221fcf5ef2aSThomas Huth }; 222fcf5ef2aSThomas Huth 2230e3bf489SRoman Kapl /* SPR load/store helpers */ 2240e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2250e3bf489SRoman Kapl { 2260e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2270e3bf489SRoman Kapl } 2280e3bf489SRoman Kapl 2290e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2300e3bf489SRoman Kapl { 2310e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2320e3bf489SRoman Kapl } 2330e3bf489SRoman Kapl 234fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 235fcf5ef2aSThomas Huth { 236fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 237fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 238fcf5ef2aSThomas Huth ctx->access_type = access_type; 239fcf5ef2aSThomas Huth } 240fcf5ef2aSThomas Huth } 241fcf5ef2aSThomas Huth 242fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 243fcf5ef2aSThomas Huth { 244fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 245fcf5ef2aSThomas Huth nip = (uint32_t)nip; 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 248fcf5ef2aSThomas Huth } 249fcf5ef2aSThomas Huth 250fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 251fcf5ef2aSThomas Huth { 252fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 253fcf5ef2aSThomas Huth 254efe843d8SDavid Gibson /* 255efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 256efe843d8SDavid Gibson * faulting instruction 257fcf5ef2aSThomas Huth */ 2582c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 259fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 260fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 261fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 262fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 263fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2643d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 265fcf5ef2aSThomas Huth } 266fcf5ef2aSThomas Huth 267fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 268fcf5ef2aSThomas Huth { 269fcf5ef2aSThomas Huth TCGv_i32 t0; 270fcf5ef2aSThomas Huth 271efe843d8SDavid Gibson /* 272efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 273efe843d8SDavid Gibson * faulting instruction 274fcf5ef2aSThomas Huth */ 2752c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 276fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 277fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 278fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2793d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 280fcf5ef2aSThomas Huth } 281fcf5ef2aSThomas Huth 282fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 283fcf5ef2aSThomas Huth target_ulong nip) 284fcf5ef2aSThomas Huth { 285fcf5ef2aSThomas Huth TCGv_i32 t0; 286fcf5ef2aSThomas Huth 287fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 288fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 289fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 290fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2913d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 292fcf5ef2aSThomas Huth } 293fcf5ef2aSThomas Huth 294f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 295f5b6daacSRichard Henderson { 296f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 297f5b6daacSRichard Henderson gen_io_start(); 298f5b6daacSRichard Henderson /* 299f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 300f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 301f5b6daacSRichard Henderson * decide if we need to return to the main loop. 302f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 303f5b6daacSRichard Henderson */ 304f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 305f5b6daacSRichard Henderson } 306f5b6daacSRichard Henderson } 307f5b6daacSRichard Henderson 308e150ac89SRoman Kapl /* 309e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 310e150ac89SRoman Kapl * SPR registers for this exception. 311e150ac89SRoman Kapl * 312e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 313e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3140e3bf489SRoman Kapl */ 315e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3160e3bf489SRoman Kapl { 3170e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3180e3bf489SRoman Kapl target_ulong dbsr = 0; 319e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3200e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 321e150ac89SRoman Kapl } else { 322e150ac89SRoman Kapl /* Must have been branch */ 3230e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3240e3bf489SRoman Kapl } 3250e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3260e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3270e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3280e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3290e3bf489SRoman Kapl tcg_temp_free(t0); 3300e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3310e3bf489SRoman Kapl } else { 332e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3330e3bf489SRoman Kapl } 3340e3bf489SRoman Kapl } 3350e3bf489SRoman Kapl 336fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 337fcf5ef2aSThomas Huth { 3389498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3393d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 340fcf5ef2aSThomas Huth } 341fcf5ef2aSThomas Huth 342fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 343fcf5ef2aSThomas Huth { 344fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 345fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 346fcf5ef2aSThomas Huth } 347fcf5ef2aSThomas Huth 348fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 349fcf5ef2aSThomas Huth { 350fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 351fcf5ef2aSThomas Huth } 352fcf5ef2aSThomas Huth 353fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 354fcf5ef2aSThomas Huth { 355fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 356fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 357fcf5ef2aSThomas Huth } 358fcf5ef2aSThomas Huth 35937f219c8SBruno Larsen (billionai) /*****************************************************************************/ 36037f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 36137f219c8SBruno Larsen (billionai) 362a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 36337f219c8SBruno Larsen (billionai) { 36437f219c8SBruno Larsen (billionai) #if 0 36537f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 36637f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 36737f219c8SBruno Larsen (billionai) #endif 36837f219c8SBruno Larsen (billionai) } 36937f219c8SBruno Larsen (billionai) 37037f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 37137f219c8SBruno Larsen (billionai) 37237f219c8SBruno Larsen (billionai) /* 37337f219c8SBruno Larsen (billionai) * Generic callbacks: 37437f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 37537f219c8SBruno Larsen (billionai) */ 37637f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 37737f219c8SBruno Larsen (billionai) { 37837f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 37937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 38037f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 38137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 38237f219c8SBruno Larsen (billionai) #endif 38337f219c8SBruno Larsen (billionai) } 38437f219c8SBruno Larsen (billionai) 385a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 38637f219c8SBruno Larsen (billionai) { 38737f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 38837f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 38937f219c8SBruno Larsen (billionai) } 39037f219c8SBruno Larsen (billionai) 39137f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 39237f219c8SBruno Larsen (billionai) { 39337f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39537f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 39637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39737f219c8SBruno Larsen (billionai) #endif 39837f219c8SBruno Larsen (billionai) } 39937f219c8SBruno Larsen (billionai) 400a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 40137f219c8SBruno Larsen (billionai) { 40237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 40337f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 40437f219c8SBruno Larsen (billionai) } 40537f219c8SBruno Larsen (billionai) 4067aeac354SDaniel Henrique Barboza void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 4077aeac354SDaniel Henrique Barboza { 4087aeac354SDaniel Henrique Barboza spr_write_generic(ctx, sprn, gprn); 4097aeac354SDaniel Henrique Barboza 4107aeac354SDaniel Henrique Barboza /* 4117aeac354SDaniel Henrique Barboza * SPR_CTRL writes must force a new translation block, 4127aeac354SDaniel Henrique Barboza * allowing the PMU to calculate the run latch events with 4137aeac354SDaniel Henrique Barboza * more accuracy. 4147aeac354SDaniel Henrique Barboza */ 4157aeac354SDaniel Henrique Barboza ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4167aeac354SDaniel Henrique Barboza } 4177aeac354SDaniel Henrique Barboza 41837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 419a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 42037f219c8SBruno Larsen (billionai) { 42137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 42237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42337f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 42437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42737f219c8SBruno Larsen (billionai) #else 42837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 42937f219c8SBruno Larsen (billionai) #endif 43037f219c8SBruno Larsen (billionai) } 43137f219c8SBruno Larsen (billionai) 432a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 43337f219c8SBruno Larsen (billionai) { 43437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 43637f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 43737f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 43837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 43937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 44037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 44137f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 44237f219c8SBruno Larsen (billionai) } 44337f219c8SBruno Larsen (billionai) 444a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 44537f219c8SBruno Larsen (billionai) { 44637f219c8SBruno Larsen (billionai) } 44737f219c8SBruno Larsen (billionai) 44837f219c8SBruno Larsen (billionai) #endif 44937f219c8SBruno Larsen (billionai) 45037f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 45137f219c8SBruno Larsen (billionai) /* XER */ 452a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 45337f219c8SBruno Larsen (billionai) { 45437f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 45537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 45637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 45737f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 45837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 45937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 46037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 46137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 46237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 46337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 46437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46537f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 46637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 46737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 46937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47037f219c8SBruno Larsen (billionai) } 47137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 47237f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 47337f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 47437f219c8SBruno Larsen (billionai) } 47537f219c8SBruno Larsen (billionai) 476a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 47737f219c8SBruno Larsen (billionai) { 47837f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 47937f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 48037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 48137f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 48237f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 48337f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 48437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 48537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 48637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 48737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 48837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 48937f219c8SBruno Larsen (billionai) } 49037f219c8SBruno Larsen (billionai) 49137f219c8SBruno Larsen (billionai) /* LR */ 492a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 49337f219c8SBruno Larsen (billionai) { 49437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 49537f219c8SBruno Larsen (billionai) } 49637f219c8SBruno Larsen (billionai) 497a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 49837f219c8SBruno Larsen (billionai) { 49937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 50037f219c8SBruno Larsen (billionai) } 50137f219c8SBruno Larsen (billionai) 50237f219c8SBruno Larsen (billionai) /* CFAR */ 50337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 504a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 50537f219c8SBruno Larsen (billionai) { 50637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 50737f219c8SBruno Larsen (billionai) } 50837f219c8SBruno Larsen (billionai) 509a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 51037f219c8SBruno Larsen (billionai) { 51137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 51237f219c8SBruno Larsen (billionai) } 51337f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 51437f219c8SBruno Larsen (billionai) 51537f219c8SBruno Larsen (billionai) /* CTR */ 516a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 51737f219c8SBruno Larsen (billionai) { 51837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 51937f219c8SBruno Larsen (billionai) } 52037f219c8SBruno Larsen (billionai) 521a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 52237f219c8SBruno Larsen (billionai) { 52337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 52437f219c8SBruno Larsen (billionai) } 52537f219c8SBruno Larsen (billionai) 52637f219c8SBruno Larsen (billionai) /* User read access to SPR */ 52737f219c8SBruno Larsen (billionai) /* USPRx */ 52837f219c8SBruno Larsen (billionai) /* UMMCRx */ 52937f219c8SBruno Larsen (billionai) /* UPMCx */ 53037f219c8SBruno Larsen (billionai) /* USIA */ 53137f219c8SBruno Larsen (billionai) /* UDECR */ 532a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 53337f219c8SBruno Larsen (billionai) { 53437f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 53537f219c8SBruno Larsen (billionai) } 53637f219c8SBruno Larsen (billionai) 53737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 538a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 53937f219c8SBruno Larsen (billionai) { 54037f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 54137f219c8SBruno Larsen (billionai) } 54237f219c8SBruno Larsen (billionai) #endif 54337f219c8SBruno Larsen (billionai) 54437f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 54537f219c8SBruno Larsen (billionai) /* DECR */ 54637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 547a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 54837f219c8SBruno Larsen (billionai) { 549f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55037f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 55137f219c8SBruno Larsen (billionai) } 55237f219c8SBruno Larsen (billionai) 553a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 55437f219c8SBruno Larsen (billionai) { 555f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55637f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 55737f219c8SBruno Larsen (billionai) } 55837f219c8SBruno Larsen (billionai) #endif 55937f219c8SBruno Larsen (billionai) 56037f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 56137f219c8SBruno Larsen (billionai) /* Time base */ 562a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 56337f219c8SBruno Larsen (billionai) { 564f5b6daacSRichard Henderson gen_icount_io_start(ctx); 56537f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 56637f219c8SBruno Larsen (billionai) } 56737f219c8SBruno Larsen (billionai) 568a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 56937f219c8SBruno Larsen (billionai) { 570f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57137f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 57237f219c8SBruno Larsen (billionai) } 57337f219c8SBruno Larsen (billionai) 574a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 57537f219c8SBruno Larsen (billionai) { 57637f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 57737f219c8SBruno Larsen (billionai) } 57837f219c8SBruno Larsen (billionai) 579a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 58037f219c8SBruno Larsen (billionai) { 58137f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 58237f219c8SBruno Larsen (billionai) } 58337f219c8SBruno Larsen (billionai) 58437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 585a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 58637f219c8SBruno Larsen (billionai) { 587f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58837f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 58937f219c8SBruno Larsen (billionai) } 59037f219c8SBruno Larsen (billionai) 591a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 59237f219c8SBruno Larsen (billionai) { 593f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59437f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 59537f219c8SBruno Larsen (billionai) } 59637f219c8SBruno Larsen (billionai) 597a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 59837f219c8SBruno Larsen (billionai) { 59937f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 60037f219c8SBruno Larsen (billionai) } 60137f219c8SBruno Larsen (billionai) 602a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 60337f219c8SBruno Larsen (billionai) { 60437f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 60537f219c8SBruno Larsen (billionai) } 60637f219c8SBruno Larsen (billionai) 60737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 608a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 60937f219c8SBruno Larsen (billionai) { 610f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61137f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 61237f219c8SBruno Larsen (billionai) } 61337f219c8SBruno Larsen (billionai) 614a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 61537f219c8SBruno Larsen (billionai) { 616f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61737f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 61837f219c8SBruno Larsen (billionai) } 61937f219c8SBruno Larsen (billionai) 62037f219c8SBruno Larsen (billionai) /* HDECR */ 621a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 62237f219c8SBruno Larsen (billionai) { 623f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62437f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 62537f219c8SBruno Larsen (billionai) } 62637f219c8SBruno Larsen (billionai) 627a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 62837f219c8SBruno Larsen (billionai) { 629f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63037f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 63137f219c8SBruno Larsen (billionai) } 63237f219c8SBruno Larsen (billionai) 633a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 63437f219c8SBruno Larsen (billionai) { 635f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63637f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 63737f219c8SBruno Larsen (billionai) } 63837f219c8SBruno Larsen (billionai) 639a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 64037f219c8SBruno Larsen (billionai) { 641f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64237f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 64337f219c8SBruno Larsen (billionai) } 64437f219c8SBruno Larsen (billionai) 645a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 64637f219c8SBruno Larsen (billionai) { 647f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64837f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 64937f219c8SBruno Larsen (billionai) } 65037f219c8SBruno Larsen (billionai) 65137f219c8SBruno Larsen (billionai) #endif 65237f219c8SBruno Larsen (billionai) #endif 65337f219c8SBruno Larsen (billionai) 65437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 65537f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 65637f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 657a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 65837f219c8SBruno Larsen (billionai) { 65937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 66037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 66137f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 66237f219c8SBruno Larsen (billionai) } 66337f219c8SBruno Larsen (billionai) 664a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 66537f219c8SBruno Larsen (billionai) { 66637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 66737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 66837f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 66937f219c8SBruno Larsen (billionai) } 67037f219c8SBruno Larsen (billionai) 671a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 67237f219c8SBruno Larsen (billionai) { 67337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 67437f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 67537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67637f219c8SBruno Larsen (billionai) } 67737f219c8SBruno Larsen (billionai) 678a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 67937f219c8SBruno Larsen (billionai) { 68037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 68137f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 68237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) 685a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 68637f219c8SBruno Larsen (billionai) { 68737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 68837f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69037f219c8SBruno Larsen (billionai) } 69137f219c8SBruno Larsen (billionai) 692a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 69337f219c8SBruno Larsen (billionai) { 69437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 69537f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 69637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69737f219c8SBruno Larsen (billionai) } 69837f219c8SBruno Larsen (billionai) 69937f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 70037f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 701a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 70237f219c8SBruno Larsen (billionai) { 70337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70437f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70537f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 70637f219c8SBruno Larsen (billionai) } 70737f219c8SBruno Larsen (billionai) 708a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 70937f219c8SBruno Larsen (billionai) { 71037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 71137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 71237f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 71337f219c8SBruno Larsen (billionai) } 71437f219c8SBruno Larsen (billionai) 715a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 71637f219c8SBruno Larsen (billionai) { 71737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 71837f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72037f219c8SBruno Larsen (billionai) } 72137f219c8SBruno Larsen (billionai) 722a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 72337f219c8SBruno Larsen (billionai) { 72437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 72537f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 72637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72737f219c8SBruno Larsen (billionai) } 72837f219c8SBruno Larsen (billionai) 729a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 73037f219c8SBruno Larsen (billionai) { 73137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 73237f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 73337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 73437f219c8SBruno Larsen (billionai) } 73537f219c8SBruno Larsen (billionai) 736a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 73737f219c8SBruno Larsen (billionai) { 73837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 73937f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 74037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 74137f219c8SBruno Larsen (billionai) } 74237f219c8SBruno Larsen (billionai) 74337f219c8SBruno Larsen (billionai) /* SDR1 */ 744a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 74537f219c8SBruno Larsen (billionai) { 74637f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 74737f219c8SBruno Larsen (billionai) } 74837f219c8SBruno Larsen (billionai) 74937f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 75037f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 75137f219c8SBruno Larsen (billionai) /* PIDR */ 752a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 75337f219c8SBruno Larsen (billionai) { 75437f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 75537f219c8SBruno Larsen (billionai) } 75637f219c8SBruno Larsen (billionai) 757a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 75837f219c8SBruno Larsen (billionai) { 75937f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 76037f219c8SBruno Larsen (billionai) } 76137f219c8SBruno Larsen (billionai) 762a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 76337f219c8SBruno Larsen (billionai) { 76437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 76537f219c8SBruno Larsen (billionai) } 76637f219c8SBruno Larsen (billionai) 767a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 76837f219c8SBruno Larsen (billionai) { 76937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 77037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 77137f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 77237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 77337f219c8SBruno Larsen (billionai) } 774a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 77537f219c8SBruno Larsen (billionai) { 77637f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 77737f219c8SBruno Larsen (billionai) } 77837f219c8SBruno Larsen (billionai) 779a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 78037f219c8SBruno Larsen (billionai) { 78137f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 78237f219c8SBruno Larsen (billionai) } 78337f219c8SBruno Larsen (billionai) 78437f219c8SBruno Larsen (billionai) /* DPDES */ 785a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 78637f219c8SBruno Larsen (billionai) { 78737f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 78837f219c8SBruno Larsen (billionai) } 78937f219c8SBruno Larsen (billionai) 790a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 79137f219c8SBruno Larsen (billionai) { 79237f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 79337f219c8SBruno Larsen (billionai) } 79437f219c8SBruno Larsen (billionai) #endif 79537f219c8SBruno Larsen (billionai) #endif 79637f219c8SBruno Larsen (billionai) 79737f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 79837f219c8SBruno Larsen (billionai) /* RTC */ 799a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 80037f219c8SBruno Larsen (billionai) { 80137f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 80237f219c8SBruno Larsen (billionai) } 80337f219c8SBruno Larsen (billionai) 804a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 80537f219c8SBruno Larsen (billionai) { 80637f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 80737f219c8SBruno Larsen (billionai) } 80837f219c8SBruno Larsen (billionai) 80937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 810a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 81137f219c8SBruno Larsen (billionai) { 81237f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 81337f219c8SBruno Larsen (billionai) } 81437f219c8SBruno Larsen (billionai) 815a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 81637f219c8SBruno Larsen (billionai) { 81737f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 81837f219c8SBruno Larsen (billionai) } 81937f219c8SBruno Larsen (billionai) 820a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 82137f219c8SBruno Larsen (billionai) { 82237f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 82337f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 824d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 82537f219c8SBruno Larsen (billionai) } 82637f219c8SBruno Larsen (billionai) #endif 82737f219c8SBruno Larsen (billionai) 82837f219c8SBruno Larsen (billionai) /* Unified bats */ 82937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 830a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 83137f219c8SBruno Larsen (billionai) { 83237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 83337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 83437f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 83537f219c8SBruno Larsen (billionai) } 83637f219c8SBruno Larsen (billionai) 837a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 83837f219c8SBruno Larsen (billionai) { 83937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 84037f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 84137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 84237f219c8SBruno Larsen (billionai) } 84337f219c8SBruno Larsen (billionai) 844a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 84537f219c8SBruno Larsen (billionai) { 84637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 84737f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 84837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 84937f219c8SBruno Larsen (billionai) } 85037f219c8SBruno Larsen (billionai) #endif 85137f219c8SBruno Larsen (billionai) 85237f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 85337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 854a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 85537f219c8SBruno Larsen (billionai) { 856f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85737f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 85837f219c8SBruno Larsen (billionai) } 85937f219c8SBruno Larsen (billionai) 860a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 86137f219c8SBruno Larsen (billionai) { 862f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86337f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 86437f219c8SBruno Larsen (billionai) } 86537f219c8SBruno Larsen (billionai) 866a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 86737f219c8SBruno Larsen (billionai) { 868f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 87037f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 87137f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 872d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 87337f219c8SBruno Larsen (billionai) } 87437f219c8SBruno Larsen (billionai) 875a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 87637f219c8SBruno Larsen (billionai) { 877f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87837f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 87937f219c8SBruno Larsen (billionai) } 88037f219c8SBruno Larsen (billionai) 881cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 882cbd8f17dSCédric Le Goater { 883cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 884cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 885cbd8f17dSCédric Le Goater } 886cbd8f17dSCédric Le Goater 887cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 888cbd8f17dSCédric Le Goater { 889cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 890cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 891cbd8f17dSCédric Le Goater } 892cbd8f17dSCédric Le Goater 893dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 894dd69d140SCédric Le Goater { 895dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 896dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 897dd69d140SCédric Le Goater gen_store_spr(SPR_40x_PID, t0); 898dd69d140SCédric Le Goater tcg_temp_free(t0); 899dd69d140SCédric Le Goater } 900dd69d140SCédric Le Goater 901a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 90237f219c8SBruno Larsen (billionai) { 903f5b6daacSRichard Henderson gen_icount_io_start(ctx); 90437f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 90537f219c8SBruno Larsen (billionai) } 90637f219c8SBruno Larsen (billionai) 907a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 90837f219c8SBruno Larsen (billionai) { 909f5b6daacSRichard Henderson gen_icount_io_start(ctx); 91037f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 91137f219c8SBruno Larsen (billionai) } 91237f219c8SBruno Larsen (billionai) #endif 91337f219c8SBruno Larsen (billionai) 91437f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 91537f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 91637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 917a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 91837f219c8SBruno Larsen (billionai) { 91937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 92037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 92137f219c8SBruno Larsen (billionai) } 92237f219c8SBruno Larsen (billionai) 923a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 92437f219c8SBruno Larsen (billionai) { 92537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 92637f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 92737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92837f219c8SBruno Larsen (billionai) } 92937f219c8SBruno Larsen (billionai) 930a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 93137f219c8SBruno Larsen (billionai) { 93237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 93337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 93437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 93537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 93637f219c8SBruno Larsen (billionai) } 93737f219c8SBruno Larsen (billionai) #endif 93837f219c8SBruno Larsen (billionai) 93937f219c8SBruno Larsen (billionai) /* SPE specific registers */ 940a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 94137f219c8SBruno Larsen (billionai) { 94237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 94337f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 94437f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 94537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 94637f219c8SBruno Larsen (billionai) } 94737f219c8SBruno Larsen (billionai) 948a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 94937f219c8SBruno Larsen (billionai) { 95037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 95137f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 95237f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 95337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 95437f219c8SBruno Larsen (billionai) } 95537f219c8SBruno Larsen (billionai) 95637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 95737f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 958a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 95937f219c8SBruno Larsen (billionai) { 96037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 96237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 96337f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 96437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 96537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 96637f219c8SBruno Larsen (billionai) } 96737f219c8SBruno Larsen (billionai) 968a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 96937f219c8SBruno Larsen (billionai) { 97037f219c8SBruno Larsen (billionai) int sprn_offs; 97137f219c8SBruno Larsen (billionai) 97237f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 97337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 97437f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 97537f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 97637f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 97737f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 97837f219c8SBruno Larsen (billionai) } else { 97937f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 98037f219c8SBruno Larsen (billionai) sprn, sprn); 98137f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 98237f219c8SBruno Larsen (billionai) return; 98337f219c8SBruno Larsen (billionai) } 98437f219c8SBruno Larsen (billionai) 98537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 98637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 98737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 98837f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 98937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 99037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 99137f219c8SBruno Larsen (billionai) } 99237f219c8SBruno Larsen (billionai) #endif 99337f219c8SBruno Larsen (billionai) 99437f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 99537f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 996a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 99737f219c8SBruno Larsen (billionai) { 99837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 99937f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 100037f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 100137f219c8SBruno Larsen (billionai) 100237f219c8SBruno Larsen (billionai) /* 100337f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 100437f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100537f219c8SBruno Larsen (billionai) */ 100637f219c8SBruno Larsen (billionai) 100737f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 100837f219c8SBruno Larsen (billionai) if (ctx->pr) { 100937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 101037f219c8SBruno Larsen (billionai) } else { 101137f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 101237f219c8SBruno Larsen (billionai) } 101337f219c8SBruno Larsen (billionai) 101437f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 101537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 101637f219c8SBruno Larsen (billionai) 101737f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 101837f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 101937f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 102037f219c8SBruno Larsen (billionai) 102137f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 102237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 102337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 102437f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 102537f219c8SBruno Larsen (billionai) 102637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 102737f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 102837f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 102937f219c8SBruno Larsen (billionai) } 103037f219c8SBruno Larsen (billionai) 1031a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 103237f219c8SBruno Larsen (billionai) { 103337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 103537f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 103637f219c8SBruno Larsen (billionai) 103737f219c8SBruno Larsen (billionai) /* 103837f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 103937f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 104037f219c8SBruno Larsen (billionai) */ 104137f219c8SBruno Larsen (billionai) 104237f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 104337f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 104437f219c8SBruno Larsen (billionai) 104537f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 104637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 104737f219c8SBruno Larsen (billionai) 104837f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 104937f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 105037f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 105137f219c8SBruno Larsen (billionai) 105237f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 105337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 105437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 105537f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 105637f219c8SBruno Larsen (billionai) 105737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105837f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 105937f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 106037f219c8SBruno Larsen (billionai) } 106137f219c8SBruno Larsen (billionai) 1062a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 106337f219c8SBruno Larsen (billionai) { 106437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 106637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 106737f219c8SBruno Larsen (billionai) 106837f219c8SBruno Larsen (billionai) /* 106937f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 107037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 107137f219c8SBruno Larsen (billionai) */ 107237f219c8SBruno Larsen (billionai) 107337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 107437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 107537f219c8SBruno Larsen (billionai) 107637f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 107737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 107837f219c8SBruno Larsen (billionai) 107937f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 108037f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 108137f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 108237f219c8SBruno Larsen (billionai) 108337f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 108437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 108537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 108637f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 108737f219c8SBruno Larsen (billionai) 108837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 108937f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 109037f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 109137f219c8SBruno Larsen (billionai) } 109237f219c8SBruno Larsen (billionai) #endif 109337f219c8SBruno Larsen (billionai) #endif 109437f219c8SBruno Larsen (billionai) 109537f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1096a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 109737f219c8SBruno Larsen (billionai) { 109837f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 109937f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 110037f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 110137f219c8SBruno Larsen (billionai) } 110237f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 110337f219c8SBruno Larsen (billionai) 110437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1105a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 110637f219c8SBruno Larsen (billionai) { 110737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 110837f219c8SBruno Larsen (billionai) 110937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 111037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 111137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 111237f219c8SBruno Larsen (billionai) } 111337f219c8SBruno Larsen (billionai) 1114a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 111537f219c8SBruno Larsen (billionai) { 111637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 111737f219c8SBruno Larsen (billionai) 111837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 111937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 112037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 112137f219c8SBruno Larsen (billionai) } 112237f219c8SBruno Larsen (billionai) 1123a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 112437f219c8SBruno Larsen (billionai) { 112537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 112637f219c8SBruno Larsen (billionai) 112737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 112837f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 112937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 113037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 113137f219c8SBruno Larsen (billionai) } 113237f219c8SBruno Larsen (billionai) 1133a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 113437f219c8SBruno Larsen (billionai) { 113537f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 113637f219c8SBruno Larsen (billionai) } 113737f219c8SBruno Larsen (billionai) 1138a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 113937f219c8SBruno Larsen (billionai) { 114037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 114137f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 114237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 114337f219c8SBruno Larsen (billionai) } 1144a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 114537f219c8SBruno Larsen (billionai) { 114637f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 114737f219c8SBruno Larsen (billionai) } 1148a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 114937f219c8SBruno Larsen (billionai) { 115037f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 115137f219c8SBruno Larsen (billionai) } 115237f219c8SBruno Larsen (billionai) 115337f219c8SBruno Larsen (billionai) #endif 115437f219c8SBruno Larsen (billionai) 115537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1156a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 115737f219c8SBruno Larsen (billionai) { 115837f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 115937f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 116037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 116137f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 116237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 116337f219c8SBruno Larsen (billionai) tcg_temp_free(val); 116437f219c8SBruno Larsen (billionai) } 116537f219c8SBruno Larsen (billionai) 1166a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 116737f219c8SBruno Larsen (billionai) { 116837f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 116937f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 117037f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 117137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 117237f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 117337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 117437f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 117537f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 117637f219c8SBruno Larsen (billionai) } 117737f219c8SBruno Larsen (billionai) 117837f219c8SBruno Larsen (billionai) #endif 117937f219c8SBruno Larsen (billionai) 118037f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 118137f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 118237f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 118337f219c8SBruno Larsen (billionai) { 118437f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 118537f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 118637f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 118737f219c8SBruno Larsen (billionai) 118837f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 118937f219c8SBruno Larsen (billionai) 119037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 119137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 119237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 119337f219c8SBruno Larsen (billionai) } 119437f219c8SBruno Larsen (billionai) 119537f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 119637f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 119737f219c8SBruno Larsen (billionai) { 119837f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 119937f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 120037f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 120137f219c8SBruno Larsen (billionai) 120237f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 120337f219c8SBruno Larsen (billionai) 120437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 120537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 120637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 120737f219c8SBruno Larsen (billionai) } 120837f219c8SBruno Larsen (billionai) 1209a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 121037f219c8SBruno Larsen (billionai) { 121137f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 121237f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 121337f219c8SBruno Larsen (billionai) 121437f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 121537f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 121637f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 121737f219c8SBruno Larsen (billionai) 121837f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 121937f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 122037f219c8SBruno Larsen (billionai) } 122137f219c8SBruno Larsen (billionai) 1222a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 122337f219c8SBruno Larsen (billionai) { 122437f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 122537f219c8SBruno Larsen (billionai) 122637f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 122737f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 122837f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 122937f219c8SBruno Larsen (billionai) 123037f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 123137f219c8SBruno Larsen (billionai) } 123237f219c8SBruno Larsen (billionai) 123337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1234a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 123537f219c8SBruno Larsen (billionai) { 123637f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 123737f219c8SBruno Larsen (billionai) 123837f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 123937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 124037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 124137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 124237f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 124337f219c8SBruno Larsen (billionai) } 124437f219c8SBruno Larsen (billionai) 1245a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 124637f219c8SBruno Larsen (billionai) { 124737f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 124837f219c8SBruno Larsen (billionai) } 124937f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 125037f219c8SBruno Larsen (billionai) 1251a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 125237f219c8SBruno Larsen (billionai) { 125337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 125437f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 125537f219c8SBruno Larsen (billionai) } 125637f219c8SBruno Larsen (billionai) 1257a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 125837f219c8SBruno Larsen (billionai) { 125937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 126037f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 126137f219c8SBruno Larsen (billionai) } 126237f219c8SBruno Larsen (billionai) 1263a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 126437f219c8SBruno Larsen (billionai) { 126537f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 126637f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 126737f219c8SBruno Larsen (billionai) } 126837f219c8SBruno Larsen (billionai) 1269a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 127037f219c8SBruno Larsen (billionai) { 127137f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 127237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 127337f219c8SBruno Larsen (billionai) } 127437f219c8SBruno Larsen (billionai) 1275a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 127637f219c8SBruno Larsen (billionai) { 127737f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 127837f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 127937f219c8SBruno Larsen (billionai) } 128037f219c8SBruno Larsen (billionai) 1281a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 128237f219c8SBruno Larsen (billionai) { 128337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 128437f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 128537f219c8SBruno Larsen (billionai) } 128637f219c8SBruno Larsen (billionai) 1287a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 128837f219c8SBruno Larsen (billionai) { 128937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 129037f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 129137f219c8SBruno Larsen (billionai) } 129237f219c8SBruno Larsen (billionai) 1293a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 129437f219c8SBruno Larsen (billionai) { 129537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 129637f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 129737f219c8SBruno Larsen (billionai) } 129837f219c8SBruno Larsen (billionai) 1299a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 130037f219c8SBruno Larsen (billionai) { 130137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 130237f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 130337f219c8SBruno Larsen (billionai) } 130437f219c8SBruno Larsen (billionai) 1305a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 130637f219c8SBruno Larsen (billionai) { 130737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 130837f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 130937f219c8SBruno Larsen (billionai) } 131037f219c8SBruno Larsen (billionai) #endif 131137f219c8SBruno Larsen (billionai) 1312fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1313fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1314fcf5ef2aSThomas Huth 1315fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1316fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1317fcf5ef2aSThomas Huth 1318fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1319fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1320fcf5ef2aSThomas Huth 1321fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1322fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1323fcf5ef2aSThomas Huth 1324fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1325fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1326fcf5ef2aSThomas Huth 1327fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1328fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1329fcf5ef2aSThomas Huth 1330fcf5ef2aSThomas Huth typedef struct opcode_t { 1331fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1332fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1333fcf5ef2aSThomas Huth unsigned char pad[4]; 1334fcf5ef2aSThomas Huth #endif 1335fcf5ef2aSThomas Huth opc_handler_t handler; 1336fcf5ef2aSThomas Huth const char *oname; 1337fcf5ef2aSThomas Huth } opcode_t; 1338fcf5ef2aSThomas Huth 1339fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1340fcf5ef2aSThomas Huth #define GEN_PRIV \ 1341fcf5ef2aSThomas Huth do { \ 1342fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1343fcf5ef2aSThomas Huth } while (0) 1344fcf5ef2aSThomas Huth 1345fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1346fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1347fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1348fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1349fcf5ef2aSThomas Huth #else 1350fcf5ef2aSThomas Huth #define CHK_HV \ 1351fcf5ef2aSThomas Huth do { \ 1352fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1353fcf5ef2aSThomas Huth GEN_PRIV; \ 1354fcf5ef2aSThomas Huth } \ 1355fcf5ef2aSThomas Huth } while (0) 1356fcf5ef2aSThomas Huth #define CHK_SV \ 1357fcf5ef2aSThomas Huth do { \ 1358fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1359fcf5ef2aSThomas Huth GEN_PRIV; \ 1360fcf5ef2aSThomas Huth } \ 1361fcf5ef2aSThomas Huth } while (0) 1362fcf5ef2aSThomas Huth #define CHK_HVRM \ 1363fcf5ef2aSThomas Huth do { \ 1364fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1365fcf5ef2aSThomas Huth GEN_PRIV; \ 1366fcf5ef2aSThomas Huth } \ 1367fcf5ef2aSThomas Huth } while (0) 1368fcf5ef2aSThomas Huth #endif 1369fcf5ef2aSThomas Huth 1370fcf5ef2aSThomas Huth #define CHK_NONE 1371fcf5ef2aSThomas Huth 1372fcf5ef2aSThomas Huth /*****************************************************************************/ 1373fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1374fcf5ef2aSThomas Huth 1375fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1376fcf5ef2aSThomas Huth { \ 1377fcf5ef2aSThomas Huth .opc1 = op1, \ 1378fcf5ef2aSThomas Huth .opc2 = op2, \ 1379fcf5ef2aSThomas Huth .opc3 = op3, \ 1380fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1381fcf5ef2aSThomas Huth .handler = { \ 1382fcf5ef2aSThomas Huth .inval1 = invl, \ 1383fcf5ef2aSThomas Huth .type = _typ, \ 1384fcf5ef2aSThomas Huth .type2 = _typ2, \ 1385fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1386fcf5ef2aSThomas Huth }, \ 1387fcf5ef2aSThomas Huth .oname = stringify(name), \ 1388fcf5ef2aSThomas Huth } 1389fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1390fcf5ef2aSThomas Huth { \ 1391fcf5ef2aSThomas Huth .opc1 = op1, \ 1392fcf5ef2aSThomas Huth .opc2 = op2, \ 1393fcf5ef2aSThomas Huth .opc3 = op3, \ 1394fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1395fcf5ef2aSThomas Huth .handler = { \ 1396fcf5ef2aSThomas Huth .inval1 = invl1, \ 1397fcf5ef2aSThomas Huth .inval2 = invl2, \ 1398fcf5ef2aSThomas Huth .type = _typ, \ 1399fcf5ef2aSThomas Huth .type2 = _typ2, \ 1400fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1401fcf5ef2aSThomas Huth }, \ 1402fcf5ef2aSThomas Huth .oname = stringify(name), \ 1403fcf5ef2aSThomas Huth } 1404fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1405fcf5ef2aSThomas Huth { \ 1406fcf5ef2aSThomas Huth .opc1 = op1, \ 1407fcf5ef2aSThomas Huth .opc2 = op2, \ 1408fcf5ef2aSThomas Huth .opc3 = op3, \ 1409fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1410fcf5ef2aSThomas Huth .handler = { \ 1411fcf5ef2aSThomas Huth .inval1 = invl, \ 1412fcf5ef2aSThomas Huth .type = _typ, \ 1413fcf5ef2aSThomas Huth .type2 = _typ2, \ 1414fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1415fcf5ef2aSThomas Huth }, \ 1416fcf5ef2aSThomas Huth .oname = onam, \ 1417fcf5ef2aSThomas Huth } 1418fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1419fcf5ef2aSThomas Huth { \ 1420fcf5ef2aSThomas Huth .opc1 = op1, \ 1421fcf5ef2aSThomas Huth .opc2 = op2, \ 1422fcf5ef2aSThomas Huth .opc3 = op3, \ 1423fcf5ef2aSThomas Huth .opc4 = op4, \ 1424fcf5ef2aSThomas Huth .handler = { \ 1425fcf5ef2aSThomas Huth .inval1 = invl, \ 1426fcf5ef2aSThomas Huth .type = _typ, \ 1427fcf5ef2aSThomas Huth .type2 = _typ2, \ 1428fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1429fcf5ef2aSThomas Huth }, \ 1430fcf5ef2aSThomas Huth .oname = stringify(name), \ 1431fcf5ef2aSThomas Huth } 1432fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1433fcf5ef2aSThomas Huth { \ 1434fcf5ef2aSThomas Huth .opc1 = op1, \ 1435fcf5ef2aSThomas Huth .opc2 = op2, \ 1436fcf5ef2aSThomas Huth .opc3 = op3, \ 1437fcf5ef2aSThomas Huth .opc4 = op4, \ 1438fcf5ef2aSThomas Huth .handler = { \ 1439fcf5ef2aSThomas Huth .inval1 = invl, \ 1440fcf5ef2aSThomas Huth .type = _typ, \ 1441fcf5ef2aSThomas Huth .type2 = _typ2, \ 1442fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1443fcf5ef2aSThomas Huth }, \ 1444fcf5ef2aSThomas Huth .oname = onam, \ 1445fcf5ef2aSThomas Huth } 1446fcf5ef2aSThomas Huth 1447fcf5ef2aSThomas Huth /* Invalid instruction */ 1448fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1449fcf5ef2aSThomas Huth { 1450fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1451fcf5ef2aSThomas Huth } 1452fcf5ef2aSThomas Huth 1453fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1454fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1455fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1456fcf5ef2aSThomas Huth .type = PPC_NONE, 1457fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1458fcf5ef2aSThomas Huth .handler = gen_invalid, 1459fcf5ef2aSThomas Huth }; 1460fcf5ef2aSThomas Huth 1461fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1462fcf5ef2aSThomas Huth 1463fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1464fcf5ef2aSThomas Huth { 1465fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1466b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1467b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1468fcf5ef2aSThomas Huth 1469b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1470b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1471efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1472efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1473b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1474efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1475efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1476b62b3686Spbonzini@redhat.com 1477b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1478fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1479b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1480fcf5ef2aSThomas Huth 1481fcf5ef2aSThomas Huth tcg_temp_free(t0); 1482b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1483b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1484fcf5ef2aSThomas Huth } 1485fcf5ef2aSThomas Huth 1486fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1487fcf5ef2aSThomas Huth { 1488fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1489fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1490fcf5ef2aSThomas Huth tcg_temp_free(t0); 1491fcf5ef2aSThomas Huth } 1492fcf5ef2aSThomas Huth 1493fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1494fcf5ef2aSThomas Huth { 1495fcf5ef2aSThomas Huth TCGv t0, t1; 1496fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1497fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1498fcf5ef2aSThomas Huth if (s) { 1499fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1500fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1501fcf5ef2aSThomas Huth } else { 1502fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1503fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1504fcf5ef2aSThomas Huth } 1505fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1506fcf5ef2aSThomas Huth tcg_temp_free(t1); 1507fcf5ef2aSThomas Huth tcg_temp_free(t0); 1508fcf5ef2aSThomas Huth } 1509fcf5ef2aSThomas Huth 1510fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1511fcf5ef2aSThomas Huth { 1512fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1513fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1514fcf5ef2aSThomas Huth tcg_temp_free(t0); 1515fcf5ef2aSThomas Huth } 1516fcf5ef2aSThomas Huth 1517fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1518fcf5ef2aSThomas Huth { 1519fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1520fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1521fcf5ef2aSThomas Huth } else { 1522fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1523fcf5ef2aSThomas Huth } 1524fcf5ef2aSThomas Huth } 1525fcf5ef2aSThomas Huth 1526fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1527fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1528fcf5ef2aSThomas Huth { 1529fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1530fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1531fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1532fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1533fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1534fcf5ef2aSThomas Huth 1535fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1536fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1537fcf5ef2aSThomas Huth 1538fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1539fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1540fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1541fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1542fcf5ef2aSThomas Huth 1543fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1544fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1545fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1546fcf5ef2aSThomas Huth 1547fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1548fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1549fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1550fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1551fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1552fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1553fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1554fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1555fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1556fcf5ef2aSThomas Huth } 1557efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1558fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1559fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1560fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1561fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1562fcf5ef2aSThomas Huth } 1563fcf5ef2aSThomas Huth 1564fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1565fcf5ef2aSThomas Huth /* cmpeqb */ 1566fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1567fcf5ef2aSThomas Huth { 1568fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1569fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1570fcf5ef2aSThomas Huth } 1571fcf5ef2aSThomas Huth #endif 1572fcf5ef2aSThomas Huth 1573fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1574fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1575fcf5ef2aSThomas Huth { 1576fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1577fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1578fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1579fcf5ef2aSThomas Huth TCGv zr; 1580fcf5ef2aSThomas Huth 1581fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1582fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1583fcf5ef2aSThomas Huth 1584fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1585fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1586fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1587fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1588fcf5ef2aSThomas Huth tcg_temp_free(zr); 1589fcf5ef2aSThomas Huth tcg_temp_free(t0); 1590fcf5ef2aSThomas Huth } 1591fcf5ef2aSThomas Huth 1592fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1593fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1594fcf5ef2aSThomas Huth { 1595fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1596fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1597fcf5ef2aSThomas Huth } 1598fcf5ef2aSThomas Huth 1599fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1600fcf5ef2aSThomas Huth 1601fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1602fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1603fcf5ef2aSThomas Huth { 1604fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1605fcf5ef2aSThomas Huth 1606fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1607fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1608fcf5ef2aSThomas Huth if (sub) { 1609fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1610fcf5ef2aSThomas Huth } else { 1611fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1612fcf5ef2aSThomas Huth } 1613fcf5ef2aSThomas Huth tcg_temp_free(t0); 1614fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1615dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1616dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1617dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1618fcf5ef2aSThomas Huth } 1619dc0ad844SNikunj A Dadhania } else { 1620dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1621dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1622dc0ad844SNikunj A Dadhania } 162338a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1624dc0ad844SNikunj A Dadhania } 1625fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1626fcf5ef2aSThomas Huth } 1627fcf5ef2aSThomas Huth 16286b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 16296b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 16304c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 16316b10d008SNikunj A Dadhania { 16326b10d008SNikunj A Dadhania TCGv t0; 16336b10d008SNikunj A Dadhania 16346b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16356b10d008SNikunj A Dadhania return; 16366b10d008SNikunj A Dadhania } 16376b10d008SNikunj A Dadhania 16386b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 163933903d0aSNikunj A Dadhania if (sub) { 164033903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 164133903d0aSNikunj A Dadhania } else { 16426b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 164333903d0aSNikunj A Dadhania } 16446b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16454c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16466b10d008SNikunj A Dadhania tcg_temp_free(t0); 16476b10d008SNikunj A Dadhania } 16486b10d008SNikunj A Dadhania 1649fcf5ef2aSThomas Huth /* Common add function */ 1650fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16514c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16524c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1653fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1654fcf5ef2aSThomas Huth { 1655fcf5ef2aSThomas Huth TCGv t0 = ret; 1656fcf5ef2aSThomas Huth 1657fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1658fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1659fcf5ef2aSThomas Huth } 1660fcf5ef2aSThomas Huth 1661fcf5ef2aSThomas Huth if (compute_ca) { 1662fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1663efe843d8SDavid Gibson /* 1664efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1665efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1666efe843d8SDavid Gibson * produce the carry into bit 32. 1667efe843d8SDavid Gibson */ 1668fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1669fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1670fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1671fcf5ef2aSThomas Huth if (add_ca) { 16724c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1673fcf5ef2aSThomas Huth } 16744c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1675fcf5ef2aSThomas Huth tcg_temp_free(t1); 16764c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16776b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16784c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16796b10d008SNikunj A Dadhania } 1680fcf5ef2aSThomas Huth } else { 1681fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1682fcf5ef2aSThomas Huth if (add_ca) { 16834c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16844c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1685fcf5ef2aSThomas Huth } else { 16864c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1687fcf5ef2aSThomas Huth } 16884c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1689fcf5ef2aSThomas Huth tcg_temp_free(zero); 1690fcf5ef2aSThomas Huth } 1691fcf5ef2aSThomas Huth } else { 1692fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1693fcf5ef2aSThomas Huth if (add_ca) { 16944c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1695fcf5ef2aSThomas Huth } 1696fcf5ef2aSThomas Huth } 1697fcf5ef2aSThomas Huth 1698fcf5ef2aSThomas Huth if (compute_ov) { 1699fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1700fcf5ef2aSThomas Huth } 1701fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1702fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1703fcf5ef2aSThomas Huth } 1704fcf5ef2aSThomas Huth 170511f4e8f8SRichard Henderson if (t0 != ret) { 1706fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1707fcf5ef2aSThomas Huth tcg_temp_free(t0); 1708fcf5ef2aSThomas Huth } 1709fcf5ef2aSThomas Huth } 1710fcf5ef2aSThomas Huth /* Add functions with two operands */ 17114c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1712fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1713fcf5ef2aSThomas Huth { \ 1714fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1715fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 17164c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1717fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1718fcf5ef2aSThomas Huth } 1719fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 17204c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1721fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1722fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1723fcf5ef2aSThomas Huth { \ 1724fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1725fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1726fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 17274c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1728fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1729fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1730fcf5ef2aSThomas Huth } 1731fcf5ef2aSThomas Huth 1732fcf5ef2aSThomas Huth /* add add. addo addo. */ 17334c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 17344c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1735fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 17364c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 17374c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1738fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17394c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17404c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1741fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17424c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17434c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17444c5920afSSuraj Jitindar Singh /* addex */ 17454c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1746fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17474c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17484c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1749fcf5ef2aSThomas Huth /* addic addic.*/ 1750fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1751fcf5ef2aSThomas Huth { 1752fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1753fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17544c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1755fcf5ef2aSThomas Huth tcg_temp_free(c); 1756fcf5ef2aSThomas Huth } 1757fcf5ef2aSThomas Huth 1758fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1759fcf5ef2aSThomas Huth { 1760fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1761fcf5ef2aSThomas Huth } 1762fcf5ef2aSThomas Huth 1763fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1764fcf5ef2aSThomas Huth { 1765fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1766fcf5ef2aSThomas Huth } 1767fcf5ef2aSThomas Huth 1768fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1769fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1770fcf5ef2aSThomas Huth { 1771fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1772fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1773fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1774fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1775fcf5ef2aSThomas Huth 1776fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1777fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1778fcf5ef2aSThomas Huth if (sign) { 1779fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1780fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1781fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1782fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1783fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1784fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1785fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1786fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1787fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1788fcf5ef2aSThomas Huth } else { 1789fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1790fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1791fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1792fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1793fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1794fcf5ef2aSThomas Huth } 1795fcf5ef2aSThomas Huth if (compute_ov) { 1796fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1797c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1798c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1799c44027ffSNikunj A Dadhania } 1800fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1801fcf5ef2aSThomas Huth } 1802fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1803fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1804fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1805fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1806fcf5ef2aSThomas Huth 1807efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1808fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1809fcf5ef2aSThomas Huth } 1810efe843d8SDavid Gibson } 1811fcf5ef2aSThomas Huth /* Div functions */ 1812fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1813fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1814fcf5ef2aSThomas Huth { \ 1815fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1816fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1817fcf5ef2aSThomas Huth sign, compute_ov); \ 1818fcf5ef2aSThomas Huth } 1819fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1820fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1821fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1822fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1823fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1824fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1825fcf5ef2aSThomas Huth 1826fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1827fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1828fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1829fcf5ef2aSThomas Huth { \ 1830fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1831fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1832fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1833fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1834fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1835fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1836fcf5ef2aSThomas Huth } \ 1837fcf5ef2aSThomas Huth } 1838fcf5ef2aSThomas Huth 1839fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1840fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1841fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1842fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1843fcf5ef2aSThomas Huth 1844fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1845fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1846fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1847fcf5ef2aSThomas Huth { 1848fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1849fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1850fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1851fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1852fcf5ef2aSThomas Huth 1853fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1854fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1855fcf5ef2aSThomas Huth if (sign) { 1856fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1857fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1858fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1859fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1860fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1861fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1862fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1863fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1864fcf5ef2aSThomas Huth } else { 1865fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1866fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1867fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1868fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1869fcf5ef2aSThomas Huth } 1870fcf5ef2aSThomas Huth if (compute_ov) { 1871fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1872c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1873c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1874c44027ffSNikunj A Dadhania } 1875fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1876fcf5ef2aSThomas Huth } 1877fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1878fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1879fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1880fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1881fcf5ef2aSThomas Huth 1882efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1883fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1884fcf5ef2aSThomas Huth } 1885efe843d8SDavid Gibson } 1886fcf5ef2aSThomas Huth 1887fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1888fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1889fcf5ef2aSThomas Huth { \ 1890fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1891fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1892fcf5ef2aSThomas Huth sign, compute_ov); \ 1893fcf5ef2aSThomas Huth } 1894c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1895fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1896fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1897c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1898fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1899fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1900fcf5ef2aSThomas Huth 1901fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1902fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1903fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1904fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1905fcf5ef2aSThomas Huth #endif 1906fcf5ef2aSThomas Huth 1907fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1908fcf5ef2aSThomas Huth TCGv arg2, int sign) 1909fcf5ef2aSThomas Huth { 1910fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1911fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1912fcf5ef2aSThomas Huth 1913fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1914fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1915fcf5ef2aSThomas Huth if (sign) { 1916fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1917fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1918fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1919fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1920fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1921fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1922fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1923fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1924fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1925fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1926fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1927fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1928fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1929fcf5ef2aSThomas Huth } else { 1930fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1931fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1932fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1933fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1934fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1935fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1936fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1937fcf5ef2aSThomas Huth } 1938fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1939fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1940fcf5ef2aSThomas Huth } 1941fcf5ef2aSThomas Huth 1942fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1943fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1944fcf5ef2aSThomas Huth { \ 1945fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1946fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1947fcf5ef2aSThomas Huth sign); \ 1948fcf5ef2aSThomas Huth } 1949fcf5ef2aSThomas Huth 1950fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1951fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1952fcf5ef2aSThomas Huth 1953fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1954fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1955fcf5ef2aSThomas Huth TCGv arg2, int sign) 1956fcf5ef2aSThomas Huth { 1957fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1958fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1959fcf5ef2aSThomas Huth 1960fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1961fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1962fcf5ef2aSThomas Huth if (sign) { 1963fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1964fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1965fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1966fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1967fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1968fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1969fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1970fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1971fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1972fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1973fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1974fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1975fcf5ef2aSThomas Huth } else { 1976fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1977fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1978fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1979fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1980fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1981fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1982fcf5ef2aSThomas Huth } 1983fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1984fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1985fcf5ef2aSThomas Huth } 1986fcf5ef2aSThomas Huth 1987fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1988fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1989fcf5ef2aSThomas Huth { \ 1990fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1991fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1992fcf5ef2aSThomas Huth sign); \ 1993fcf5ef2aSThomas Huth } 1994fcf5ef2aSThomas Huth 1995fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1996fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1997fcf5ef2aSThomas Huth #endif 1998fcf5ef2aSThomas Huth 1999fcf5ef2aSThomas Huth /* mulhw mulhw. */ 2000fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 2001fcf5ef2aSThomas Huth { 2002fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2003fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2004fcf5ef2aSThomas Huth 2005fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2006fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2007fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2008fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2009fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2010fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2011efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2012fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2013fcf5ef2aSThomas Huth } 2014efe843d8SDavid Gibson } 2015fcf5ef2aSThomas Huth 2016fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 2017fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 2018fcf5ef2aSThomas Huth { 2019fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2020fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2021fcf5ef2aSThomas Huth 2022fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2023fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2024fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 2025fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2026fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2027fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2028efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2029fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2030fcf5ef2aSThomas Huth } 2031efe843d8SDavid Gibson } 2032fcf5ef2aSThomas Huth 2033fcf5ef2aSThomas Huth /* mullw mullw. */ 2034fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2035fcf5ef2aSThomas Huth { 2036fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2037fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2038fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2039fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2040fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2041fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2042fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2043fcf5ef2aSThomas Huth tcg_temp_free(t0); 2044fcf5ef2aSThomas Huth tcg_temp_free(t1); 2045fcf5ef2aSThomas Huth #else 2046fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2047fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2048fcf5ef2aSThomas Huth #endif 2049efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2050fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2051fcf5ef2aSThomas Huth } 2052efe843d8SDavid Gibson } 2053fcf5ef2aSThomas Huth 2054fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2055fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2056fcf5ef2aSThomas Huth { 2057fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2058fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2059fcf5ef2aSThomas Huth 2060fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2061fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2062fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2063fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2064fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2065fcf5ef2aSThomas Huth #else 2066fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2067fcf5ef2aSThomas Huth #endif 2068fcf5ef2aSThomas Huth 2069fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2070fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2071fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 207261aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 207361aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 207461aa9a69SNikunj A Dadhania } 2075fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2076fcf5ef2aSThomas Huth 2077fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2078fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2079efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2080fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2081fcf5ef2aSThomas Huth } 2082efe843d8SDavid Gibson } 2083fcf5ef2aSThomas Huth 2084fcf5ef2aSThomas Huth /* mulli */ 2085fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2086fcf5ef2aSThomas Huth { 2087fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2088fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2089fcf5ef2aSThomas Huth } 2090fcf5ef2aSThomas Huth 2091fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2092fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2093fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2094fcf5ef2aSThomas Huth { 2095fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2096fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2097fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2098fcf5ef2aSThomas Huth tcg_temp_free(lo); 2099fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2100fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2101fcf5ef2aSThomas Huth } 2102fcf5ef2aSThomas Huth } 2103fcf5ef2aSThomas Huth 2104fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2105fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2106fcf5ef2aSThomas Huth { 2107fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2108fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2109fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2110fcf5ef2aSThomas Huth tcg_temp_free(lo); 2111fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2112fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2113fcf5ef2aSThomas Huth } 2114fcf5ef2aSThomas Huth } 2115fcf5ef2aSThomas Huth 2116fcf5ef2aSThomas Huth /* mulld mulld. */ 2117fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2118fcf5ef2aSThomas Huth { 2119fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2120fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2121efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2122fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2123fcf5ef2aSThomas Huth } 2124efe843d8SDavid Gibson } 2125fcf5ef2aSThomas Huth 2126fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2127fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2128fcf5ef2aSThomas Huth { 2129fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2130fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2131fcf5ef2aSThomas Huth 2132fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2133fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2134fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2135fcf5ef2aSThomas Huth 2136fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2137fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 213861aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 213961aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 214061aa9a69SNikunj A Dadhania } 2141fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2142fcf5ef2aSThomas Huth 2143fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2144fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2145fcf5ef2aSThomas Huth 2146fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2147fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2148fcf5ef2aSThomas Huth } 2149fcf5ef2aSThomas Huth } 2150fcf5ef2aSThomas Huth #endif 2151fcf5ef2aSThomas Huth 2152fcf5ef2aSThomas Huth /* Common subf function */ 2153fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2154fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2155fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2156fcf5ef2aSThomas Huth { 2157fcf5ef2aSThomas Huth TCGv t0 = ret; 2158fcf5ef2aSThomas Huth 2159fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2160fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2161fcf5ef2aSThomas Huth } 2162fcf5ef2aSThomas Huth 2163fcf5ef2aSThomas Huth if (compute_ca) { 2164fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2165fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2166efe843d8SDavid Gibson /* 2167efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2168efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2169efe843d8SDavid Gibson * produce the carry into bit 32. 2170efe843d8SDavid Gibson */ 2171fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2172fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2173fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2174fcf5ef2aSThomas Huth if (add_ca) { 2175fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2176fcf5ef2aSThomas Huth } else { 2177fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2178fcf5ef2aSThomas Huth } 2179fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2180fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2181fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2182fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2183fcf5ef2aSThomas Huth tcg_temp_free(t1); 2184e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 218533903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 218633903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 218733903d0aSNikunj A Dadhania } 2188fcf5ef2aSThomas Huth } else if (add_ca) { 2189fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2190fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2191fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2192fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2193fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21944c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2195fcf5ef2aSThomas Huth tcg_temp_free(zero); 2196fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2197fcf5ef2aSThomas Huth } else { 2198fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2199fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 22004c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2201fcf5ef2aSThomas Huth } 2202fcf5ef2aSThomas Huth } else if (add_ca) { 2203efe843d8SDavid Gibson /* 2204efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2205efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2206efe843d8SDavid Gibson */ 2207fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2208fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2209fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2210fcf5ef2aSThomas Huth } else { 2211fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2212fcf5ef2aSThomas Huth } 2213fcf5ef2aSThomas Huth 2214fcf5ef2aSThomas Huth if (compute_ov) { 2215fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2216fcf5ef2aSThomas Huth } 2217fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2218fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2219fcf5ef2aSThomas Huth } 2220fcf5ef2aSThomas Huth 222111f4e8f8SRichard Henderson if (t0 != ret) { 2222fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2223fcf5ef2aSThomas Huth tcg_temp_free(t0); 2224fcf5ef2aSThomas Huth } 2225fcf5ef2aSThomas Huth } 2226fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2227fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2228fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2229fcf5ef2aSThomas Huth { \ 2230fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2231fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2232fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2233fcf5ef2aSThomas Huth } 2234fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2235fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2236fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2237fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2238fcf5ef2aSThomas Huth { \ 2239fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2240fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2241fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2242fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2243fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2244fcf5ef2aSThomas Huth } 2245fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2246fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2247fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2248fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2249fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2250fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2251fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2252fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2253fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2254fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2255fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2256fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2257fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2258fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2259fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2260fcf5ef2aSThomas Huth 2261fcf5ef2aSThomas Huth /* subfic */ 2262fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2263fcf5ef2aSThomas Huth { 2264fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2265fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2266fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2267fcf5ef2aSThomas Huth tcg_temp_free(c); 2268fcf5ef2aSThomas Huth } 2269fcf5ef2aSThomas Huth 2270fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2271fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2272fcf5ef2aSThomas Huth { 2273fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2274fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2275fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2276fcf5ef2aSThomas Huth tcg_temp_free(zero); 2277fcf5ef2aSThomas Huth } 2278fcf5ef2aSThomas Huth 2279fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2280fcf5ef2aSThomas Huth { 22811480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22821480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22831480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22841480d71cSNikunj A Dadhania } 2285fcf5ef2aSThomas Huth } 2286fcf5ef2aSThomas Huth 2287fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2288fcf5ef2aSThomas Huth { 2289fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2290fcf5ef2aSThomas Huth } 2291fcf5ef2aSThomas Huth 2292fcf5ef2aSThomas Huth /*** Integer logical ***/ 2293fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2294fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2295fcf5ef2aSThomas Huth { \ 2296fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2297fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2298fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2299fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2300fcf5ef2aSThomas Huth } 2301fcf5ef2aSThomas Huth 2302fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2303fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2304fcf5ef2aSThomas Huth { \ 2305fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2306fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2307fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2308fcf5ef2aSThomas Huth } 2309fcf5ef2aSThomas Huth 2310fcf5ef2aSThomas Huth /* and & and. */ 2311fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2312fcf5ef2aSThomas Huth /* andc & andc. */ 2313fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2314fcf5ef2aSThomas Huth 2315fcf5ef2aSThomas Huth /* andi. */ 2316fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2317fcf5ef2aSThomas Huth { 2318efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2319efe843d8SDavid Gibson UIMM(ctx->opcode)); 2320fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2321fcf5ef2aSThomas Huth } 2322fcf5ef2aSThomas Huth 2323fcf5ef2aSThomas Huth /* andis. */ 2324fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2325fcf5ef2aSThomas Huth { 2326efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2327efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2328fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2329fcf5ef2aSThomas Huth } 2330fcf5ef2aSThomas Huth 2331fcf5ef2aSThomas Huth /* cntlzw */ 2332fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2333fcf5ef2aSThomas Huth { 23349b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23359b8514e5SRichard Henderson 23369b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23379b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 23389b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23399b8514e5SRichard Henderson tcg_temp_free_i32(t); 23409b8514e5SRichard Henderson 2341efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2342fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2343fcf5ef2aSThomas Huth } 2344efe843d8SDavid Gibson } 2345fcf5ef2aSThomas Huth 2346fcf5ef2aSThomas Huth /* cnttzw */ 2347fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2348fcf5ef2aSThomas Huth { 23499b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23509b8514e5SRichard Henderson 23519b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23529b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 23539b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23549b8514e5SRichard Henderson tcg_temp_free_i32(t); 23559b8514e5SRichard Henderson 2356fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2357fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2358fcf5ef2aSThomas Huth } 2359fcf5ef2aSThomas Huth } 2360fcf5ef2aSThomas Huth 2361fcf5ef2aSThomas Huth /* eqv & eqv. */ 2362fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2363fcf5ef2aSThomas Huth /* extsb & extsb. */ 2364fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2365fcf5ef2aSThomas Huth /* extsh & extsh. */ 2366fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2367fcf5ef2aSThomas Huth /* nand & nand. */ 2368fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2369fcf5ef2aSThomas Huth /* nor & nor. */ 2370fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2371fcf5ef2aSThomas Huth 2372fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2373fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2374fcf5ef2aSThomas Huth { 2375fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2376fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2377fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2378fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2379fcf5ef2aSThomas Huth 2380fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2381b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2382fcf5ef2aSThomas Huth } 2383fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2384fcf5ef2aSThomas Huth 2385fcf5ef2aSThomas Huth /* or & or. */ 2386fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2387fcf5ef2aSThomas Huth { 2388fcf5ef2aSThomas Huth int rs, ra, rb; 2389fcf5ef2aSThomas Huth 2390fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2391fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2392fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2393fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2394fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2395efe843d8SDavid Gibson if (rs != rb) { 2396fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2397efe843d8SDavid Gibson } else { 2398fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2399efe843d8SDavid Gibson } 2400efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2401fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2402efe843d8SDavid Gibson } 2403fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2404fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2405fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2406fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2407fcf5ef2aSThomas Huth int prio = 0; 2408fcf5ef2aSThomas Huth 2409fcf5ef2aSThomas Huth switch (rs) { 2410fcf5ef2aSThomas Huth case 1: 2411fcf5ef2aSThomas Huth /* Set process priority to low */ 2412fcf5ef2aSThomas Huth prio = 2; 2413fcf5ef2aSThomas Huth break; 2414fcf5ef2aSThomas Huth case 6: 2415fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2416fcf5ef2aSThomas Huth prio = 3; 2417fcf5ef2aSThomas Huth break; 2418fcf5ef2aSThomas Huth case 2: 2419fcf5ef2aSThomas Huth /* Set process priority to normal */ 2420fcf5ef2aSThomas Huth prio = 4; 2421fcf5ef2aSThomas Huth break; 2422fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2423fcf5ef2aSThomas Huth case 31: 2424fcf5ef2aSThomas Huth if (!ctx->pr) { 2425fcf5ef2aSThomas Huth /* Set process priority to very low */ 2426fcf5ef2aSThomas Huth prio = 1; 2427fcf5ef2aSThomas Huth } 2428fcf5ef2aSThomas Huth break; 2429fcf5ef2aSThomas Huth case 5: 2430fcf5ef2aSThomas Huth if (!ctx->pr) { 2431fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2432fcf5ef2aSThomas Huth prio = 5; 2433fcf5ef2aSThomas Huth } 2434fcf5ef2aSThomas Huth break; 2435fcf5ef2aSThomas Huth case 3: 2436fcf5ef2aSThomas Huth if (!ctx->pr) { 2437fcf5ef2aSThomas Huth /* Set process priority to high */ 2438fcf5ef2aSThomas Huth prio = 6; 2439fcf5ef2aSThomas Huth } 2440fcf5ef2aSThomas Huth break; 2441fcf5ef2aSThomas Huth case 7: 2442fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2443fcf5ef2aSThomas Huth /* Set process priority to very high */ 2444fcf5ef2aSThomas Huth prio = 7; 2445fcf5ef2aSThomas Huth } 2446fcf5ef2aSThomas Huth break; 2447fcf5ef2aSThomas Huth #endif 2448fcf5ef2aSThomas Huth default: 2449fcf5ef2aSThomas Huth break; 2450fcf5ef2aSThomas Huth } 2451fcf5ef2aSThomas Huth if (prio) { 2452fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2453fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2454fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2455fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2456fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2457fcf5ef2aSThomas Huth tcg_temp_free(t0); 2458fcf5ef2aSThomas Huth } 2459fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2460efe843d8SDavid Gibson /* 2461efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2462efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2463efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2464efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2465fcf5ef2aSThomas Huth */ 2466fcf5ef2aSThomas Huth gen_pause(ctx); 2467fcf5ef2aSThomas Huth #endif 2468fcf5ef2aSThomas Huth #endif 2469fcf5ef2aSThomas Huth } 2470fcf5ef2aSThomas Huth } 2471fcf5ef2aSThomas Huth /* orc & orc. */ 2472fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2473fcf5ef2aSThomas Huth 2474fcf5ef2aSThomas Huth /* xor & xor. */ 2475fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2476fcf5ef2aSThomas Huth { 2477fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2478efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2479efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2480efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2481efe843d8SDavid Gibson } else { 2482fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2483efe843d8SDavid Gibson } 2484efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2485fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2486fcf5ef2aSThomas Huth } 2487efe843d8SDavid Gibson } 2488fcf5ef2aSThomas Huth 2489fcf5ef2aSThomas Huth /* ori */ 2490fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2491fcf5ef2aSThomas Huth { 2492fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2493fcf5ef2aSThomas Huth 2494fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2495fcf5ef2aSThomas Huth return; 2496fcf5ef2aSThomas Huth } 2497fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2498fcf5ef2aSThomas Huth } 2499fcf5ef2aSThomas Huth 2500fcf5ef2aSThomas Huth /* oris */ 2501fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2502fcf5ef2aSThomas Huth { 2503fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2504fcf5ef2aSThomas Huth 2505fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2506fcf5ef2aSThomas Huth /* NOP */ 2507fcf5ef2aSThomas Huth return; 2508fcf5ef2aSThomas Huth } 2509efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2510efe843d8SDavid Gibson uimm << 16); 2511fcf5ef2aSThomas Huth } 2512fcf5ef2aSThomas Huth 2513fcf5ef2aSThomas Huth /* xori */ 2514fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2515fcf5ef2aSThomas Huth { 2516fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2517fcf5ef2aSThomas Huth 2518fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2519fcf5ef2aSThomas Huth /* NOP */ 2520fcf5ef2aSThomas Huth return; 2521fcf5ef2aSThomas Huth } 2522fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2523fcf5ef2aSThomas Huth } 2524fcf5ef2aSThomas Huth 2525fcf5ef2aSThomas Huth /* xoris */ 2526fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2527fcf5ef2aSThomas Huth { 2528fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2529fcf5ef2aSThomas Huth 2530fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2531fcf5ef2aSThomas Huth /* NOP */ 2532fcf5ef2aSThomas Huth return; 2533fcf5ef2aSThomas Huth } 2534efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2535efe843d8SDavid Gibson uimm << 16); 2536fcf5ef2aSThomas Huth } 2537fcf5ef2aSThomas Huth 2538fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2539fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2540fcf5ef2aSThomas Huth { 2541fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2542fcf5ef2aSThomas Huth } 2543fcf5ef2aSThomas Huth 2544fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2545fcf5ef2aSThomas Huth { 254679770002SRichard Henderson #if defined(TARGET_PPC64) 2547fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 254879770002SRichard Henderson #else 254979770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 255079770002SRichard Henderson #endif 2551fcf5ef2aSThomas Huth } 2552fcf5ef2aSThomas Huth 2553fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2554fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2555fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2556fcf5ef2aSThomas Huth { 255779770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2558fcf5ef2aSThomas Huth } 2559fcf5ef2aSThomas Huth #endif 2560fcf5ef2aSThomas Huth 2561fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2562fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2563fcf5ef2aSThomas Huth { 2564fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2565fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2566fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2567fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2568fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2569fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2570fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2571fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2572fcf5ef2aSThomas Huth tcg_temp_free(t0); 2573fcf5ef2aSThomas Huth } 2574fcf5ef2aSThomas Huth 2575fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2576fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2577fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2578fcf5ef2aSThomas Huth { 2579fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2580fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2581fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2582fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2583fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2584fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2585fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2586fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2587fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2588fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2589fcf5ef2aSThomas Huth tcg_temp_free(t0); 2590fcf5ef2aSThomas Huth } 2591fcf5ef2aSThomas Huth #endif 2592fcf5ef2aSThomas Huth 2593fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2594fcf5ef2aSThomas Huth /* bpermd */ 2595fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2596fcf5ef2aSThomas Huth { 2597fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2598fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2599fcf5ef2aSThomas Huth } 2600fcf5ef2aSThomas Huth #endif 2601fcf5ef2aSThomas Huth 2602fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2603fcf5ef2aSThomas Huth /* extsw & extsw. */ 2604fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2605fcf5ef2aSThomas Huth 2606fcf5ef2aSThomas Huth /* cntlzd */ 2607fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2608fcf5ef2aSThomas Huth { 26099b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2610efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2611fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2612fcf5ef2aSThomas Huth } 2613efe843d8SDavid Gibson } 2614fcf5ef2aSThomas Huth 2615fcf5ef2aSThomas Huth /* cnttzd */ 2616fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2617fcf5ef2aSThomas Huth { 26189b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2619fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2620fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2621fcf5ef2aSThomas Huth } 2622fcf5ef2aSThomas Huth } 2623fcf5ef2aSThomas Huth 2624fcf5ef2aSThomas Huth /* darn */ 2625fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2626fcf5ef2aSThomas Huth { 2627fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2628fcf5ef2aSThomas Huth 26297e4357f6SRichard Henderson if (l > 2) { 26307e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 26317e4357f6SRichard Henderson } else { 2632f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2633fcf5ef2aSThomas Huth if (l == 0) { 2634fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 26357e4357f6SRichard Henderson } else { 2636fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2637fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 26387e4357f6SRichard Henderson } 2639fcf5ef2aSThomas Huth } 2640fcf5ef2aSThomas Huth } 2641fcf5ef2aSThomas Huth #endif 2642fcf5ef2aSThomas Huth 2643fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2644fcf5ef2aSThomas Huth 2645fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2646fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2647fcf5ef2aSThomas Huth { 2648fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2649fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2650fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2651fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2652fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2653fcf5ef2aSThomas Huth 2654fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2655fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2656fcf5ef2aSThomas Huth } else { 2657fcf5ef2aSThomas Huth target_ulong mask; 2658c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2659fcf5ef2aSThomas Huth TCGv t1; 2660fcf5ef2aSThomas Huth 2661fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2662fcf5ef2aSThomas Huth mb += 32; 2663fcf5ef2aSThomas Huth me += 32; 2664fcf5ef2aSThomas Huth #endif 2665fcf5ef2aSThomas Huth mask = MASK(mb, me); 2666fcf5ef2aSThomas Huth 2667c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2668c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2669c4f6a4a3SDaniele Buono mask_in_32b = false; 2670c4f6a4a3SDaniele Buono } 2671c4f6a4a3SDaniele Buono #endif 2672fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2673c4f6a4a3SDaniele Buono if (mask_in_32b) { 2674fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2675fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2676fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2677fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2678fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2679fcf5ef2aSThomas Huth } else { 2680fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2681fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2682fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2683fcf5ef2aSThomas Huth #else 2684fcf5ef2aSThomas Huth g_assert_not_reached(); 2685fcf5ef2aSThomas Huth #endif 2686fcf5ef2aSThomas Huth } 2687fcf5ef2aSThomas Huth 2688fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2689fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2690fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2691fcf5ef2aSThomas Huth tcg_temp_free(t1); 2692fcf5ef2aSThomas Huth } 2693fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2694fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2695fcf5ef2aSThomas Huth } 2696fcf5ef2aSThomas Huth } 2697fcf5ef2aSThomas Huth 2698fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2699fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2700fcf5ef2aSThomas Huth { 2701fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2702fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27037b4d326fSRichard Henderson int sh = SH(ctx->opcode); 27047b4d326fSRichard Henderson int mb = MB(ctx->opcode); 27057b4d326fSRichard Henderson int me = ME(ctx->opcode); 27067b4d326fSRichard Henderson int len = me - mb + 1; 27077b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2708fcf5ef2aSThomas Huth 27097b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 27107b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27117b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 27127b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2713fcf5ef2aSThomas Huth } else { 2714fcf5ef2aSThomas Huth target_ulong mask; 2715c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2716fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2717fcf5ef2aSThomas Huth mb += 32; 2718fcf5ef2aSThomas Huth me += 32; 2719fcf5ef2aSThomas Huth #endif 2720fcf5ef2aSThomas Huth mask = MASK(mb, me); 2721c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2722c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2723c4f6a4a3SDaniele Buono mask_in_32b = false; 2724c4f6a4a3SDaniele Buono } 2725c4f6a4a3SDaniele Buono #endif 2726c4f6a4a3SDaniele Buono if (mask_in_32b) { 27277b4d326fSRichard Henderson if (sh == 0) { 27287b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 272994f040aaSVitaly Chikunov } else { 2730fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2731fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2732fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2733fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2734fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2735fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 273694f040aaSVitaly Chikunov } 2737fcf5ef2aSThomas Huth } else { 2738fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2739fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2740fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2741fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2742fcf5ef2aSThomas Huth #else 2743fcf5ef2aSThomas Huth g_assert_not_reached(); 2744fcf5ef2aSThomas Huth #endif 2745fcf5ef2aSThomas Huth } 2746fcf5ef2aSThomas Huth } 2747fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2748fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2749fcf5ef2aSThomas Huth } 2750fcf5ef2aSThomas Huth } 2751fcf5ef2aSThomas Huth 2752fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2753fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2754fcf5ef2aSThomas Huth { 2755fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2756fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2757fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2758fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2759fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2760fcf5ef2aSThomas Huth target_ulong mask; 2761c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2762fcf5ef2aSThomas Huth 2763fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2764fcf5ef2aSThomas Huth mb += 32; 2765fcf5ef2aSThomas Huth me += 32; 2766fcf5ef2aSThomas Huth #endif 2767fcf5ef2aSThomas Huth mask = MASK(mb, me); 2768fcf5ef2aSThomas Huth 2769c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2770c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2771c4f6a4a3SDaniele Buono mask_in_32b = false; 2772c4f6a4a3SDaniele Buono } 2773c4f6a4a3SDaniele Buono #endif 2774c4f6a4a3SDaniele Buono if (mask_in_32b) { 2775fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2776fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2777fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2778fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2779fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2780fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2781fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2782fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2783fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2784fcf5ef2aSThomas Huth } else { 2785fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2786fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2787fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2788fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2789fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2790fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2791fcf5ef2aSThomas Huth #else 2792fcf5ef2aSThomas Huth g_assert_not_reached(); 2793fcf5ef2aSThomas Huth #endif 2794fcf5ef2aSThomas Huth } 2795fcf5ef2aSThomas Huth 2796fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2797fcf5ef2aSThomas Huth 2798fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2799fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2800fcf5ef2aSThomas Huth } 2801fcf5ef2aSThomas Huth } 2802fcf5ef2aSThomas Huth 2803fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2804fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2805fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2806fcf5ef2aSThomas Huth { \ 2807fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2808fcf5ef2aSThomas Huth } \ 2809fcf5ef2aSThomas Huth \ 2810fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2811fcf5ef2aSThomas Huth { \ 2812fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2813fcf5ef2aSThomas Huth } 2814fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2815fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2816fcf5ef2aSThomas Huth { \ 2817fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2818fcf5ef2aSThomas Huth } \ 2819fcf5ef2aSThomas Huth \ 2820fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2821fcf5ef2aSThomas Huth { \ 2822fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2823fcf5ef2aSThomas Huth } \ 2824fcf5ef2aSThomas Huth \ 2825fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2826fcf5ef2aSThomas Huth { \ 2827fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2828fcf5ef2aSThomas Huth } \ 2829fcf5ef2aSThomas Huth \ 2830fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2831fcf5ef2aSThomas Huth { \ 2832fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2833fcf5ef2aSThomas Huth } 2834fcf5ef2aSThomas Huth 2835fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2836fcf5ef2aSThomas Huth { 2837fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2838fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 28397b4d326fSRichard Henderson int len = me - mb + 1; 28407b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2841fcf5ef2aSThomas Huth 28427b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 28437b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 28447b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 28457b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2846fcf5ef2aSThomas Huth } else { 2847fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2848fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2849fcf5ef2aSThomas Huth } 2850fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2851fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2852fcf5ef2aSThomas Huth } 2853fcf5ef2aSThomas Huth } 2854fcf5ef2aSThomas Huth 2855fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2856fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2857fcf5ef2aSThomas Huth { 2858fcf5ef2aSThomas Huth uint32_t sh, mb; 2859fcf5ef2aSThomas Huth 2860fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2861fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2862fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2863fcf5ef2aSThomas Huth } 2864fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2865fcf5ef2aSThomas Huth 2866fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2867fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2868fcf5ef2aSThomas Huth { 2869fcf5ef2aSThomas Huth uint32_t sh, me; 2870fcf5ef2aSThomas Huth 2871fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2872fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2873fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2874fcf5ef2aSThomas Huth } 2875fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2876fcf5ef2aSThomas Huth 2877fcf5ef2aSThomas Huth /* rldic - rldic. */ 2878fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2879fcf5ef2aSThomas Huth { 2880fcf5ef2aSThomas Huth uint32_t sh, mb; 2881fcf5ef2aSThomas Huth 2882fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2883fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2884fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2885fcf5ef2aSThomas Huth } 2886fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2887fcf5ef2aSThomas Huth 2888fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2889fcf5ef2aSThomas Huth { 2890fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2891fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2892fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2893fcf5ef2aSThomas Huth TCGv t0; 2894fcf5ef2aSThomas Huth 2895fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2896fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2897fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2898fcf5ef2aSThomas Huth tcg_temp_free(t0); 2899fcf5ef2aSThomas Huth 2900fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2901fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2902fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2903fcf5ef2aSThomas Huth } 2904fcf5ef2aSThomas Huth } 2905fcf5ef2aSThomas Huth 2906fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2907fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2908fcf5ef2aSThomas Huth { 2909fcf5ef2aSThomas Huth uint32_t mb; 2910fcf5ef2aSThomas Huth 2911fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2912fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2913fcf5ef2aSThomas Huth } 2914fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2915fcf5ef2aSThomas Huth 2916fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2917fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2918fcf5ef2aSThomas Huth { 2919fcf5ef2aSThomas Huth uint32_t me; 2920fcf5ef2aSThomas Huth 2921fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2922fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2923fcf5ef2aSThomas Huth } 2924fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2925fcf5ef2aSThomas Huth 2926fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2927fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2928fcf5ef2aSThomas Huth { 2929fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2930fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2931fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2932fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2933fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2934fcf5ef2aSThomas Huth 2935fcf5ef2aSThomas Huth if (mb <= me) { 2936fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2937fcf5ef2aSThomas Huth } else { 2938fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2939fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2940fcf5ef2aSThomas Huth 2941fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2942fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2943fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2944fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2945fcf5ef2aSThomas Huth tcg_temp_free(t1); 2946fcf5ef2aSThomas Huth } 2947fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2948fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2949fcf5ef2aSThomas Huth } 2950fcf5ef2aSThomas Huth } 2951fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2952fcf5ef2aSThomas Huth #endif 2953fcf5ef2aSThomas Huth 2954fcf5ef2aSThomas Huth /*** Integer shift ***/ 2955fcf5ef2aSThomas Huth 2956fcf5ef2aSThomas Huth /* slw & slw. */ 2957fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2958fcf5ef2aSThomas Huth { 2959fcf5ef2aSThomas Huth TCGv t0, t1; 2960fcf5ef2aSThomas Huth 2961fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2962fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2963fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2964fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2965fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2966fcf5ef2aSThomas Huth #else 2967fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2968fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2969fcf5ef2aSThomas Huth #endif 2970fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2971fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2972fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2973fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2974fcf5ef2aSThomas Huth tcg_temp_free(t1); 2975fcf5ef2aSThomas Huth tcg_temp_free(t0); 2976fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2977efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2978fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2979fcf5ef2aSThomas Huth } 2980efe843d8SDavid Gibson } 2981fcf5ef2aSThomas Huth 2982fcf5ef2aSThomas Huth /* sraw & sraw. */ 2983fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2984fcf5ef2aSThomas Huth { 2985fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2986fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2987efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2988fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2989fcf5ef2aSThomas Huth } 2990efe843d8SDavid Gibson } 2991fcf5ef2aSThomas Huth 2992fcf5ef2aSThomas Huth /* srawi & srawi. */ 2993fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2994fcf5ef2aSThomas Huth { 2995fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2996fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2997fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2998fcf5ef2aSThomas Huth if (sh == 0) { 2999fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3000fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3001af1c259fSSandipan Das if (is_isa300(ctx)) { 3002af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3003af1c259fSSandipan Das } 3004fcf5ef2aSThomas Huth } else { 3005fcf5ef2aSThomas Huth TCGv t0; 3006fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3007fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 3008fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3009fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 3010fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3011fcf5ef2aSThomas Huth tcg_temp_free(t0); 3012fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3013af1c259fSSandipan Das if (is_isa300(ctx)) { 3014af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3015af1c259fSSandipan Das } 3016fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 3017fcf5ef2aSThomas Huth } 3018fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3019fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3020fcf5ef2aSThomas Huth } 3021fcf5ef2aSThomas Huth } 3022fcf5ef2aSThomas Huth 3023fcf5ef2aSThomas Huth /* srw & srw. */ 3024fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 3025fcf5ef2aSThomas Huth { 3026fcf5ef2aSThomas Huth TCGv t0, t1; 3027fcf5ef2aSThomas Huth 3028fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3029fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3030fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3031fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3032fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3033fcf5ef2aSThomas Huth #else 3034fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3035fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3036fcf5ef2aSThomas Huth #endif 3037fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3038fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3039fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3040fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3041fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3042fcf5ef2aSThomas Huth tcg_temp_free(t1); 3043fcf5ef2aSThomas Huth tcg_temp_free(t0); 3044efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3045fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3046fcf5ef2aSThomas Huth } 3047efe843d8SDavid Gibson } 3048fcf5ef2aSThomas Huth 3049fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3050fcf5ef2aSThomas Huth /* sld & sld. */ 3051fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3052fcf5ef2aSThomas Huth { 3053fcf5ef2aSThomas Huth TCGv t0, t1; 3054fcf5ef2aSThomas Huth 3055fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3056fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3057fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3058fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3059fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3060fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3061fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3062fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3063fcf5ef2aSThomas Huth tcg_temp_free(t1); 3064fcf5ef2aSThomas Huth tcg_temp_free(t0); 3065efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3066fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3067fcf5ef2aSThomas Huth } 3068efe843d8SDavid Gibson } 3069fcf5ef2aSThomas Huth 3070fcf5ef2aSThomas Huth /* srad & srad. */ 3071fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3072fcf5ef2aSThomas Huth { 3073fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3074fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3075efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3076fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3077fcf5ef2aSThomas Huth } 3078efe843d8SDavid Gibson } 3079fcf5ef2aSThomas Huth /* sradi & sradi. */ 3080fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3081fcf5ef2aSThomas Huth { 3082fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3083fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3084fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3085fcf5ef2aSThomas Huth if (sh == 0) { 3086fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3087fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3088af1c259fSSandipan Das if (is_isa300(ctx)) { 3089af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3090af1c259fSSandipan Das } 3091fcf5ef2aSThomas Huth } else { 3092fcf5ef2aSThomas Huth TCGv t0; 3093fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3094fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3095fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3096fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3097fcf5ef2aSThomas Huth tcg_temp_free(t0); 3098fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3099af1c259fSSandipan Das if (is_isa300(ctx)) { 3100af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3101af1c259fSSandipan Das } 3102fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3103fcf5ef2aSThomas Huth } 3104fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3105fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3106fcf5ef2aSThomas Huth } 3107fcf5ef2aSThomas Huth } 3108fcf5ef2aSThomas Huth 3109fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3110fcf5ef2aSThomas Huth { 3111fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3112fcf5ef2aSThomas Huth } 3113fcf5ef2aSThomas Huth 3114fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3115fcf5ef2aSThomas Huth { 3116fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3117fcf5ef2aSThomas Huth } 3118fcf5ef2aSThomas Huth 3119fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3120fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3121fcf5ef2aSThomas Huth { 3122fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3123fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3124fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3125fcf5ef2aSThomas Huth 3126fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3127fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3128fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3129fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3130fcf5ef2aSThomas Huth } 3131fcf5ef2aSThomas Huth } 3132fcf5ef2aSThomas Huth 3133fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3134fcf5ef2aSThomas Huth { 3135fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3136fcf5ef2aSThomas Huth } 3137fcf5ef2aSThomas Huth 3138fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3139fcf5ef2aSThomas Huth { 3140fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3141fcf5ef2aSThomas Huth } 3142fcf5ef2aSThomas Huth 3143fcf5ef2aSThomas Huth /* srd & srd. */ 3144fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3145fcf5ef2aSThomas Huth { 3146fcf5ef2aSThomas Huth TCGv t0, t1; 3147fcf5ef2aSThomas Huth 3148fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3149fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3150fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3151fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3152fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3153fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3154fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3155fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3156fcf5ef2aSThomas Huth tcg_temp_free(t1); 3157fcf5ef2aSThomas Huth tcg_temp_free(t0); 3158efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3159fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3160fcf5ef2aSThomas Huth } 3161efe843d8SDavid Gibson } 3162fcf5ef2aSThomas Huth #endif 3163fcf5ef2aSThomas Huth 3164fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3165fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3166fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3167fcf5ef2aSThomas Huth target_long maskl) 3168fcf5ef2aSThomas Huth { 3169fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3170fcf5ef2aSThomas Huth 3171fcf5ef2aSThomas Huth simm &= ~maskl; 3172fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3173fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3174fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3175fcf5ef2aSThomas Huth } 3176fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3177fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3178fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3179fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3180fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3181fcf5ef2aSThomas Huth } 3182fcf5ef2aSThomas Huth } else { 3183fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3184fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3185fcf5ef2aSThomas Huth } else { 3186fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3187fcf5ef2aSThomas Huth } 3188fcf5ef2aSThomas Huth } 3189fcf5ef2aSThomas Huth } 3190fcf5ef2aSThomas Huth 3191fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3192fcf5ef2aSThomas Huth { 3193fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3194fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3195fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3196fcf5ef2aSThomas Huth } else { 3197fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3198fcf5ef2aSThomas Huth } 3199fcf5ef2aSThomas Huth } else { 3200fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3201fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3202fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3203fcf5ef2aSThomas Huth } 3204fcf5ef2aSThomas Huth } 3205fcf5ef2aSThomas Huth } 3206fcf5ef2aSThomas Huth 3207fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3208fcf5ef2aSThomas Huth { 3209fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3210fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3211fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3212fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3213fcf5ef2aSThomas Huth } else { 3214fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3215fcf5ef2aSThomas Huth } 3216fcf5ef2aSThomas Huth } 3217fcf5ef2aSThomas Huth 3218fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3219fcf5ef2aSThomas Huth target_long val) 3220fcf5ef2aSThomas Huth { 3221fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3222fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3223fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3224fcf5ef2aSThomas Huth } 3225fcf5ef2aSThomas Huth } 3226fcf5ef2aSThomas Huth 3227fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3228fcf5ef2aSThomas Huth { 3229fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3230fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3231fcf5ef2aSThomas Huth } 3232fcf5ef2aSThomas Huth 3233eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3234eb63efd9SFernando Eckhardt Valle { 3235eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3236eb63efd9SFernando Eckhardt Valle if (ra) { 3237eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3238eb63efd9SFernando Eckhardt Valle } else { 3239eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3240eb63efd9SFernando Eckhardt Valle } 3241eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3242eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3243eb63efd9SFernando Eckhardt Valle } 3244eb63efd9SFernando Eckhardt Valle return ea; 3245eb63efd9SFernando Eckhardt Valle } 3246eb63efd9SFernando Eckhardt Valle 3247fcf5ef2aSThomas Huth /*** Integer load ***/ 3248fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3249fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3250fcf5ef2aSThomas Huth 3251fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3252fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3253fcf5ef2aSThomas Huth TCGv val, \ 3254fcf5ef2aSThomas Huth TCGv addr) \ 3255fcf5ef2aSThomas Huth { \ 3256fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3257fcf5ef2aSThomas Huth } 3258fcf5ef2aSThomas Huth 3259fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3260fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3261fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3262fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3263fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3264fcf5ef2aSThomas Huth 3265fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3266fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3267fcf5ef2aSThomas Huth 3268fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3269fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3270fcf5ef2aSThomas Huth TCGv_i64 val, \ 3271fcf5ef2aSThomas Huth TCGv addr) \ 3272fcf5ef2aSThomas Huth { \ 3273fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3274fcf5ef2aSThomas Huth } 3275fcf5ef2aSThomas Huth 3276fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3277fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3278fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3279fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3280*fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3281fcf5ef2aSThomas Huth 3282fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3283*fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3284fcf5ef2aSThomas Huth #endif 3285fcf5ef2aSThomas Huth 3286fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3287fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3288fcf5ef2aSThomas Huth TCGv val, \ 3289fcf5ef2aSThomas Huth TCGv addr) \ 3290fcf5ef2aSThomas Huth { \ 3291fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3292fcf5ef2aSThomas Huth } 3293fcf5ef2aSThomas Huth 3294e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3295fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3296e8f4c8d6SRichard Henderson #endif 3297fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3298fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3299fcf5ef2aSThomas Huth 3300fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3301fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3302fcf5ef2aSThomas Huth 3303fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3304fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3305fcf5ef2aSThomas Huth TCGv_i64 val, \ 3306fcf5ef2aSThomas Huth TCGv addr) \ 3307fcf5ef2aSThomas Huth { \ 3308fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3309fcf5ef2aSThomas Huth } 3310fcf5ef2aSThomas Huth 3311fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3312fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3313fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3314*fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3315fcf5ef2aSThomas Huth 3316fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3317*fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3318fcf5ef2aSThomas Huth #endif 3319fcf5ef2aSThomas Huth 3320fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3321fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3322fcf5ef2aSThomas Huth { \ 3323fcf5ef2aSThomas Huth TCGv EA; \ 3324fcf5ef2aSThomas Huth chk; \ 3325fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3326fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3327fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3328fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3329fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3330fcf5ef2aSThomas Huth } 3331fcf5ef2aSThomas Huth 3332fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3333fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3334fcf5ef2aSThomas Huth 3335fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3336fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3337fcf5ef2aSThomas Huth 333850728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 333950728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 334050728199SRoman Kapl { \ 334150728199SRoman Kapl TCGv EA; \ 334250728199SRoman Kapl CHK_SV; \ 334350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 334450728199SRoman Kapl EA = tcg_temp_new(); \ 334550728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 334650728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 334750728199SRoman Kapl tcg_temp_free(EA); \ 334850728199SRoman Kapl } 334950728199SRoman Kapl 335050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 335150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 335250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 335350728199SRoman Kapl #if defined(TARGET_PPC64) 3354*fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 335550728199SRoman Kapl #endif 335650728199SRoman Kapl 3357fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3358fcf5ef2aSThomas Huth /* CI load/store variants */ 3359fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3360fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3361fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3362fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3363fcf5ef2aSThomas Huth #endif 3364fcf5ef2aSThomas Huth 3365fcf5ef2aSThomas Huth /*** Integer store ***/ 3366fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3367fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3368fcf5ef2aSThomas Huth { \ 3369fcf5ef2aSThomas Huth TCGv EA; \ 3370fcf5ef2aSThomas Huth chk; \ 3371fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3372fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3373fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3374fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3375fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3376fcf5ef2aSThomas Huth } 3377fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3378fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3379fcf5ef2aSThomas Huth 3380fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3381fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3382fcf5ef2aSThomas Huth 338350728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 338450728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 338550728199SRoman Kapl { \ 338650728199SRoman Kapl TCGv EA; \ 338750728199SRoman Kapl CHK_SV; \ 338850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 338950728199SRoman Kapl EA = tcg_temp_new(); \ 339050728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 339150728199SRoman Kapl tcg_gen_qemu_st_tl( \ 339250728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 339350728199SRoman Kapl tcg_temp_free(EA); \ 339450728199SRoman Kapl } 339550728199SRoman Kapl 339650728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 339750728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 339850728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 339950728199SRoman Kapl #if defined(TARGET_PPC64) 3400*fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 340150728199SRoman Kapl #endif 340250728199SRoman Kapl 3403fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3404fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3405fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3406fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3407fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3408fcf5ef2aSThomas Huth #endif 3409fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3410fcf5ef2aSThomas Huth 3411fcf5ef2aSThomas Huth /* lhbrx */ 3412fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3413fcf5ef2aSThomas Huth 3414fcf5ef2aSThomas Huth /* lwbrx */ 3415fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3416fcf5ef2aSThomas Huth 3417fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3418fcf5ef2aSThomas Huth /* ldbrx */ 3419fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3420fcf5ef2aSThomas Huth /* stdbrx */ 3421fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3422fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3423fcf5ef2aSThomas Huth 3424fcf5ef2aSThomas Huth /* sthbrx */ 3425fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3426fcf5ef2aSThomas Huth /* stwbrx */ 3427fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3428fcf5ef2aSThomas Huth 3429fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3430fcf5ef2aSThomas Huth 3431fcf5ef2aSThomas Huth /* lmw */ 3432fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3433fcf5ef2aSThomas Huth { 3434fcf5ef2aSThomas Huth TCGv t0; 3435fcf5ef2aSThomas Huth TCGv_i32 t1; 3436fcf5ef2aSThomas Huth 3437fcf5ef2aSThomas Huth if (ctx->le_mode) { 3438fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3439fcf5ef2aSThomas Huth return; 3440fcf5ef2aSThomas Huth } 3441fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3442fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3443fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3444fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3445fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3446fcf5ef2aSThomas Huth tcg_temp_free(t0); 3447fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3448fcf5ef2aSThomas Huth } 3449fcf5ef2aSThomas Huth 3450fcf5ef2aSThomas Huth /* stmw */ 3451fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3452fcf5ef2aSThomas Huth { 3453fcf5ef2aSThomas Huth TCGv t0; 3454fcf5ef2aSThomas Huth TCGv_i32 t1; 3455fcf5ef2aSThomas Huth 3456fcf5ef2aSThomas Huth if (ctx->le_mode) { 3457fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3458fcf5ef2aSThomas Huth return; 3459fcf5ef2aSThomas Huth } 3460fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3461fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3462fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3463fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3464fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3465fcf5ef2aSThomas Huth tcg_temp_free(t0); 3466fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3467fcf5ef2aSThomas Huth } 3468fcf5ef2aSThomas Huth 3469fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3470fcf5ef2aSThomas Huth 3471fcf5ef2aSThomas Huth /* lswi */ 3472efe843d8SDavid Gibson /* 3473efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3474efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3475efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3476efe843d8SDavid Gibson * spec... 3477fcf5ef2aSThomas Huth */ 3478fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3479fcf5ef2aSThomas Huth { 3480fcf5ef2aSThomas Huth TCGv t0; 3481fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3482fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3483fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3484fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3485fcf5ef2aSThomas Huth int nr; 3486fcf5ef2aSThomas Huth 3487fcf5ef2aSThomas Huth if (ctx->le_mode) { 3488fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3489fcf5ef2aSThomas Huth return; 3490fcf5ef2aSThomas Huth } 3491efe843d8SDavid Gibson if (nb == 0) { 3492fcf5ef2aSThomas Huth nb = 32; 3493efe843d8SDavid Gibson } 3494f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3495fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3496fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3497fcf5ef2aSThomas Huth return; 3498fcf5ef2aSThomas Huth } 3499fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3500fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3501fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3502fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3503fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3504fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3505fcf5ef2aSThomas Huth tcg_temp_free(t0); 3506fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3507fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3508fcf5ef2aSThomas Huth } 3509fcf5ef2aSThomas Huth 3510fcf5ef2aSThomas Huth /* lswx */ 3511fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3512fcf5ef2aSThomas Huth { 3513fcf5ef2aSThomas Huth TCGv t0; 3514fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3515fcf5ef2aSThomas Huth 3516fcf5ef2aSThomas Huth if (ctx->le_mode) { 3517fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3518fcf5ef2aSThomas Huth return; 3519fcf5ef2aSThomas Huth } 3520fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3521fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3522fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3523fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3524fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3525fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3526fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3527fcf5ef2aSThomas Huth tcg_temp_free(t0); 3528fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3529fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3530fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3531fcf5ef2aSThomas Huth } 3532fcf5ef2aSThomas Huth 3533fcf5ef2aSThomas Huth /* stswi */ 3534fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3535fcf5ef2aSThomas Huth { 3536fcf5ef2aSThomas Huth TCGv t0; 3537fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3538fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3539fcf5ef2aSThomas Huth 3540fcf5ef2aSThomas Huth if (ctx->le_mode) { 3541fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3542fcf5ef2aSThomas Huth return; 3543fcf5ef2aSThomas Huth } 3544fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3545fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3546fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3547efe843d8SDavid Gibson if (nb == 0) { 3548fcf5ef2aSThomas Huth nb = 32; 3549efe843d8SDavid Gibson } 3550fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3551fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3552fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3553fcf5ef2aSThomas Huth tcg_temp_free(t0); 3554fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3555fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3556fcf5ef2aSThomas Huth } 3557fcf5ef2aSThomas Huth 3558fcf5ef2aSThomas Huth /* stswx */ 3559fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3560fcf5ef2aSThomas Huth { 3561fcf5ef2aSThomas Huth TCGv t0; 3562fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3563fcf5ef2aSThomas Huth 3564fcf5ef2aSThomas Huth if (ctx->le_mode) { 3565fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3566fcf5ef2aSThomas Huth return; 3567fcf5ef2aSThomas Huth } 3568fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3569fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3570fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3571fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3572fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3573fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3574fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3575fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3576fcf5ef2aSThomas Huth tcg_temp_free(t0); 3577fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3578fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3579fcf5ef2aSThomas Huth } 3580fcf5ef2aSThomas Huth 3581fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3582fcf5ef2aSThomas Huth /* eieio */ 3583fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3584fcf5ef2aSThomas Huth { 3585c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3586c8fd8373SCédric Le Goater 3587c8fd8373SCédric Le Goater /* 3588c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3589c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3590c8fd8373SCédric Le Goater */ 3591c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3592c8fd8373SCédric Le Goater /* 3593c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3594c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3595c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3596c8fd8373SCédric Le Goater * complain to the user. 3597c8fd8373SCédric Le Goater */ 3598c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3599c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 36002c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3601c8fd8373SCédric Le Goater } else { 3602c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3603c8fd8373SCédric Le Goater } 3604c8fd8373SCédric Le Goater } 3605c8fd8373SCédric Le Goater 3606c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3607fcf5ef2aSThomas Huth } 3608fcf5ef2aSThomas Huth 3609fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3610fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3611fcf5ef2aSThomas Huth { 3612fcf5ef2aSThomas Huth TCGv_i32 t; 3613fcf5ef2aSThomas Huth TCGLabel *l; 3614fcf5ef2aSThomas Huth 3615fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3616fcf5ef2aSThomas Huth return; 3617fcf5ef2aSThomas Huth } 3618fcf5ef2aSThomas Huth l = gen_new_label(); 3619fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3620fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3621fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3622fcf5ef2aSThomas Huth if (global) { 3623fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3624fcf5ef2aSThomas Huth } else { 3625fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3626fcf5ef2aSThomas Huth } 3627fcf5ef2aSThomas Huth gen_set_label(l); 3628fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3629fcf5ef2aSThomas Huth } 3630fcf5ef2aSThomas Huth #else 3631fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3632fcf5ef2aSThomas Huth #endif 3633fcf5ef2aSThomas Huth 3634fcf5ef2aSThomas Huth /* isync */ 3635fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3636fcf5ef2aSThomas Huth { 3637fcf5ef2aSThomas Huth /* 3638fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3639fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3640fcf5ef2aSThomas Huth */ 3641fcf5ef2aSThomas Huth if (!ctx->pr) { 3642fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3643fcf5ef2aSThomas Huth } 36444771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3645d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3646fcf5ef2aSThomas Huth } 3647fcf5ef2aSThomas Huth 3648fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3649fcf5ef2aSThomas Huth 365014776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 36512a4e6c1bSRichard Henderson { 36522a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 36532a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 36542a4e6c1bSRichard Henderson 36552a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 36562a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 36572a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 36582a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 36592a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 36602a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 36612a4e6c1bSRichard Henderson tcg_temp_free(t0); 36622a4e6c1bSRichard Henderson } 36632a4e6c1bSRichard Henderson 3664fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3665fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3666fcf5ef2aSThomas Huth { \ 36672a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3668fcf5ef2aSThomas Huth } 3669fcf5ef2aSThomas Huth 3670fcf5ef2aSThomas Huth /* lwarx */ 3671fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3672fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3673fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3674fcf5ef2aSThomas Huth 367514776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 367620923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 367720923c1dSRichard Henderson { 367820923c1dSRichard Henderson TCGv t = tcg_temp_new(); 367920923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 368020923c1dSRichard Henderson TCGv u = tcg_temp_new(); 368120923c1dSRichard Henderson 368220923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 368320923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 368420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 368520923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 368620923c1dSRichard Henderson 368720923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 368820923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 368920923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 369020923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 369120923c1dSRichard Henderson 369220923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 369320923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 369420923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 369520923c1dSRichard Henderson 369620923c1dSRichard Henderson tcg_temp_free(t); 369720923c1dSRichard Henderson tcg_temp_free(t2); 369820923c1dSRichard Henderson tcg_temp_free(u); 369920923c1dSRichard Henderson } 370020923c1dSRichard Henderson 370114776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 370220ba8504SRichard Henderson { 370320ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 370420ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 370520923c1dSRichard Henderson int rt = rD(ctx->opcode); 370620923c1dSRichard Henderson bool need_serial; 370720ba8504SRichard Henderson TCGv src, dst; 370820ba8504SRichard Henderson 370920ba8504SRichard Henderson gen_addr_register(ctx, EA); 371020923c1dSRichard Henderson dst = cpu_gpr[rt]; 371120923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 371220ba8504SRichard Henderson 371320923c1dSRichard Henderson need_serial = false; 371420ba8504SRichard Henderson memop |= MO_ALIGN; 371520ba8504SRichard Henderson switch (gpr_FC) { 371620ba8504SRichard Henderson case 0: /* Fetch and add */ 371720ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 371820ba8504SRichard Henderson break; 371920ba8504SRichard Henderson case 1: /* Fetch and xor */ 372020ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 372120ba8504SRichard Henderson break; 372220ba8504SRichard Henderson case 2: /* Fetch and or */ 372320ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 372420ba8504SRichard Henderson break; 372520ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 372620ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 372720ba8504SRichard Henderson break; 3728b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3729b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3730b8ce0f86SRichard Henderson break; 3731b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3732b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3733b8ce0f86SRichard Henderson break; 3734b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3735b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3736b8ce0f86SRichard Henderson break; 3737b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3738b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3739b8ce0f86SRichard Henderson break; 374020ba8504SRichard Henderson case 8: /* Swap */ 374120ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 374220ba8504SRichard Henderson break; 374320923c1dSRichard Henderson 374420923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 374520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 374620923c1dSRichard Henderson need_serial = true; 374720923c1dSRichard Henderson } else { 374820923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 374920923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 375020923c1dSRichard Henderson 375120923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 375220923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 375320923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 375420923c1dSRichard Henderson } else { 375520923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 375620923c1dSRichard Henderson } 375720923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 375820923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 375920923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 376020923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 376120923c1dSRichard Henderson 376220923c1dSRichard Henderson tcg_temp_free(t0); 376320923c1dSRichard Henderson tcg_temp_free(t1); 376420923c1dSRichard Henderson } 376520ba8504SRichard Henderson break; 376620923c1dSRichard Henderson 376720923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 376820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 376920923c1dSRichard Henderson need_serial = true; 377020923c1dSRichard Henderson } else { 377120923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 377220923c1dSRichard Henderson } 377320923c1dSRichard Henderson break; 377420923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 377520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 377620923c1dSRichard Henderson need_serial = true; 377720923c1dSRichard Henderson } else { 377820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 377920923c1dSRichard Henderson } 378020923c1dSRichard Henderson break; 378120923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 378220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 378320923c1dSRichard Henderson need_serial = true; 378420923c1dSRichard Henderson } else { 378520923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 378620923c1dSRichard Henderson } 378720923c1dSRichard Henderson break; 378820923c1dSRichard Henderson 378920ba8504SRichard Henderson default: 379020ba8504SRichard Henderson /* invoke data storage error handler */ 379120ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 379220ba8504SRichard Henderson } 379320ba8504SRichard Henderson tcg_temp_free(EA); 379420923c1dSRichard Henderson 379520923c1dSRichard Henderson if (need_serial) { 379620923c1dSRichard Henderson /* Restart with exclusive lock. */ 379720923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 379820923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 379920923c1dSRichard Henderson } 3800a68a6146SBalamuruhan S } 3801a68a6146SBalamuruhan S 380220ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 380320ba8504SRichard Henderson { 380420ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 380520ba8504SRichard Henderson } 380620ba8504SRichard Henderson 380720ba8504SRichard Henderson #ifdef TARGET_PPC64 380820ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 380920ba8504SRichard Henderson { 3810*fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 381120ba8504SRichard Henderson } 3812a68a6146SBalamuruhan S #endif 3813a68a6146SBalamuruhan S 381414776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 38159deb041cSRichard Henderson { 38169deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 38179deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 38189deb041cSRichard Henderson TCGv src, discard; 38199deb041cSRichard Henderson 38209deb041cSRichard Henderson gen_addr_register(ctx, EA); 38219deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 38229deb041cSRichard Henderson discard = tcg_temp_new(); 38239deb041cSRichard Henderson 38249deb041cSRichard Henderson memop |= MO_ALIGN; 38259deb041cSRichard Henderson switch (gpr_FC) { 38269deb041cSRichard Henderson case 0: /* add and Store */ 38279deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38289deb041cSRichard Henderson break; 38299deb041cSRichard Henderson case 1: /* xor and Store */ 38309deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38319deb041cSRichard Henderson break; 38329deb041cSRichard Henderson case 2: /* Or and Store */ 38339deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38349deb041cSRichard Henderson break; 38359deb041cSRichard Henderson case 3: /* 'and' and Store */ 38369deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38379deb041cSRichard Henderson break; 38389deb041cSRichard Henderson case 4: /* Store max unsigned */ 3839b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3840b8ce0f86SRichard Henderson break; 38419deb041cSRichard Henderson case 5: /* Store max signed */ 3842b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3843b8ce0f86SRichard Henderson break; 38449deb041cSRichard Henderson case 6: /* Store min unsigned */ 3845b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3846b8ce0f86SRichard Henderson break; 38479deb041cSRichard Henderson case 7: /* Store min signed */ 3848b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3849b8ce0f86SRichard Henderson break; 38509deb041cSRichard Henderson case 24: /* Store twin */ 38517fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 38527fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 38537fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 38547fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 38557fbc2b20SRichard Henderson } else { 38567fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 38577fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 38587fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 38597fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 38607fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 38617fbc2b20SRichard Henderson 38627fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 38637fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 38647fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 38657fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 38667fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 38677fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 38687fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 38697fbc2b20SRichard Henderson 38707fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 38717fbc2b20SRichard Henderson tcg_temp_free(s2); 38727fbc2b20SRichard Henderson tcg_temp_free(s); 38737fbc2b20SRichard Henderson tcg_temp_free(t2); 38747fbc2b20SRichard Henderson tcg_temp_free(t); 38757fbc2b20SRichard Henderson } 38769deb041cSRichard Henderson break; 38779deb041cSRichard Henderson default: 38789deb041cSRichard Henderson /* invoke data storage error handler */ 38799deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 38809deb041cSRichard Henderson } 38819deb041cSRichard Henderson tcg_temp_free(discard); 38829deb041cSRichard Henderson tcg_temp_free(EA); 3883a3401188SBalamuruhan S } 3884a3401188SBalamuruhan S 38859deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 38869deb041cSRichard Henderson { 38879deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 38889deb041cSRichard Henderson } 38899deb041cSRichard Henderson 38909deb041cSRichard Henderson #ifdef TARGET_PPC64 38919deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 38929deb041cSRichard Henderson { 3893*fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 38949deb041cSRichard Henderson } 3895a3401188SBalamuruhan S #endif 3896a3401188SBalamuruhan S 389714776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3898fcf5ef2aSThomas Huth { 3899253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3900253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3901d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3902d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3903fcf5ef2aSThomas Huth 3904d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3905d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3906d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3907d8b86898SRichard Henderson tcg_temp_free(t0); 3908253ce7b2SNikunj A Dadhania 3909253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3910253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3911253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3912253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3913253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3914253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3915253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3916253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3917253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3918253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3919253ce7b2SNikunj A Dadhania 3920fcf5ef2aSThomas Huth gen_set_label(l1); 39214771df23SNikunj A Dadhania 3922efe843d8SDavid Gibson /* 3923efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 3924efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 3925efe843d8SDavid Gibson */ 39264771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3927253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3928253ce7b2SNikunj A Dadhania 3929253ce7b2SNikunj A Dadhania gen_set_label(l2); 3930fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3931fcf5ef2aSThomas Huth } 3932fcf5ef2aSThomas Huth 3933fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3934fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3935fcf5ef2aSThomas Huth { \ 3936d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3937fcf5ef2aSThomas Huth } 3938fcf5ef2aSThomas Huth 3939fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3940fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3941fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3942fcf5ef2aSThomas Huth 3943fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3944fcf5ef2aSThomas Huth /* ldarx */ 3945*fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3946fcf5ef2aSThomas Huth /* stdcx. */ 3947*fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3948fcf5ef2aSThomas Huth 3949fcf5ef2aSThomas Huth /* lqarx */ 3950fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3951fcf5ef2aSThomas Huth { 3952fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 395394bf2658SRichard Henderson TCGv EA, hi, lo; 3954fcf5ef2aSThomas Huth 3955fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3956fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3957fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3958fcf5ef2aSThomas Huth return; 3959fcf5ef2aSThomas Huth } 3960fcf5ef2aSThomas Huth 3961fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 396294bf2658SRichard Henderson EA = tcg_temp_new(); 3963fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 396494bf2658SRichard Henderson 396594bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 396694bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 396794bf2658SRichard Henderson hi = cpu_gpr[rd]; 396894bf2658SRichard Henderson 396994bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3970f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 397194bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 397294bf2658SRichard Henderson if (ctx->le_mode) { 397368e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN, 397494bf2658SRichard Henderson ctx->mem_idx)); 397594bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3976fcf5ef2aSThomas Huth } else { 397768e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN, 397894bf2658SRichard Henderson ctx->mem_idx)); 397994bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3980fcf5ef2aSThomas Huth } 398194bf2658SRichard Henderson tcg_temp_free_i32(oi); 398294bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3983f34ec0f6SRichard Henderson } else { 398494bf2658SRichard Henderson /* Restart with exclusive lock. */ 398594bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 398694bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 398794bf2658SRichard Henderson tcg_temp_free(EA); 398894bf2658SRichard Henderson return; 3989f34ec0f6SRichard Henderson } 399094bf2658SRichard Henderson } else if (ctx->le_mode) { 3991*fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEUQ | MO_ALIGN_16); 3992fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3993fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3994*fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEUQ); 399594bf2658SRichard Henderson } else { 3996*fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEUQ | MO_ALIGN_16); 399794bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 399894bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3999*fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEUQ); 400094bf2658SRichard Henderson } 4001fcf5ef2aSThomas Huth tcg_temp_free(EA); 400294bf2658SRichard Henderson 400394bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 400494bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4005fcf5ef2aSThomas Huth } 4006fcf5ef2aSThomas Huth 4007fcf5ef2aSThomas Huth /* stqcx. */ 4008fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4009fcf5ef2aSThomas Huth { 40104a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 40114a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4012fcf5ef2aSThomas Huth 40134a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4014fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4015fcf5ef2aSThomas Huth return; 4016fcf5ef2aSThomas Huth } 40174a9b3c5dSRichard Henderson 4018fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 40194a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4020fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4021fcf5ef2aSThomas Huth 40224a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 40234a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 40244a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4025fcf5ef2aSThomas Huth 40264a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4027f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 402868e33d86SRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); 40294a9b3c5dSRichard Henderson if (ctx->le_mode) { 4030f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4031f34ec0f6SRichard Henderson EA, lo, hi, oi); 4032fcf5ef2aSThomas Huth } else { 4033f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4034f34ec0f6SRichard Henderson EA, lo, hi, oi); 4035fcf5ef2aSThomas Huth } 4036f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4037f34ec0f6SRichard Henderson } else { 40384a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 40394a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 40404a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4041f34ec0f6SRichard Henderson } 4042fcf5ef2aSThomas Huth tcg_temp_free(EA); 40434a9b3c5dSRichard Henderson } else { 40444a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 40454a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 40464a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 40474a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4048fcf5ef2aSThomas Huth 40494a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 40504a9b3c5dSRichard Henderson tcg_temp_free(EA); 40514a9b3c5dSRichard Henderson 40524a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 40534a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40544a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 40554a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 40564a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40574a9b3c5dSRichard Henderson 40584a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40594a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 40604a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40614a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 40624a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 40634a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40644a9b3c5dSRichard Henderson 40654a9b3c5dSRichard Henderson /* Success */ 40664a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 40674a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40684a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 40694a9b3c5dSRichard Henderson 40704a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40714a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 40724a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 40734a9b3c5dSRichard Henderson 40744a9b3c5dSRichard Henderson gen_set_label(lab_fail); 40754a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40764a9b3c5dSRichard Henderson 40774a9b3c5dSRichard Henderson gen_set_label(lab_over); 40784a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 40794a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 40804a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 40814a9b3c5dSRichard Henderson } 40824a9b3c5dSRichard Henderson } 4083fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4084fcf5ef2aSThomas Huth 4085fcf5ef2aSThomas Huth /* sync */ 4086fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4087fcf5ef2aSThomas Huth { 4088fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4089fcf5ef2aSThomas Huth 4090fcf5ef2aSThomas Huth /* 4091fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4092fcf5ef2aSThomas Huth * 4093fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4094fcf5ef2aSThomas Huth * 4095fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4096fcf5ef2aSThomas Huth * check MSR_PR as well. 4097fcf5ef2aSThomas Huth */ 4098fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4099fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4100fcf5ef2aSThomas Huth } 41014771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4102fcf5ef2aSThomas Huth } 4103fcf5ef2aSThomas Huth 4104fcf5ef2aSThomas Huth /* wait */ 4105fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4106fcf5ef2aSThomas Huth { 4107fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4108fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4109fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4110fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4111fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4112b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4113fcf5ef2aSThomas Huth } 4114fcf5ef2aSThomas Huth 4115fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4116fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4117fcf5ef2aSThomas Huth { 4118fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4119fcf5ef2aSThomas Huth GEN_PRIV; 4120fcf5ef2aSThomas Huth #else 4121fcf5ef2aSThomas Huth TCGv_i32 t; 4122fcf5ef2aSThomas Huth 4123fcf5ef2aSThomas Huth CHK_HV; 4124fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4125fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4126fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4127154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4128154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4129fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4130fcf5ef2aSThomas Huth } 4131fcf5ef2aSThomas Huth 4132fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4133fcf5ef2aSThomas Huth { 4134fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4135fcf5ef2aSThomas Huth GEN_PRIV; 4136fcf5ef2aSThomas Huth #else 4137fcf5ef2aSThomas Huth TCGv_i32 t; 4138fcf5ef2aSThomas Huth 4139fcf5ef2aSThomas Huth CHK_HV; 4140fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4141fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4142fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4143154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4144154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4145fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4146fcf5ef2aSThomas Huth } 4147fcf5ef2aSThomas Huth 4148cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4149cdee0e72SNikunj A Dadhania { 415021c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 415121c0d66aSBenjamin Herrenschmidt GEN_PRIV; 415221c0d66aSBenjamin Herrenschmidt #else 415321c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 415421c0d66aSBenjamin Herrenschmidt 415521c0d66aSBenjamin Herrenschmidt CHK_HV; 415621c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 415721c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 415821c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 415921c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 416021c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 416121c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4162cdee0e72SNikunj A Dadhania } 4163cdee0e72SNikunj A Dadhania 4164fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4165fcf5ef2aSThomas Huth { 4166fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4167fcf5ef2aSThomas Huth GEN_PRIV; 4168fcf5ef2aSThomas Huth #else 4169fcf5ef2aSThomas Huth TCGv_i32 t; 4170fcf5ef2aSThomas Huth 4171fcf5ef2aSThomas Huth CHK_HV; 4172fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4173fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4174fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4175154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4176154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4177fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4178fcf5ef2aSThomas Huth } 4179fcf5ef2aSThomas Huth 4180fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4181fcf5ef2aSThomas Huth { 4182fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4183fcf5ef2aSThomas Huth GEN_PRIV; 4184fcf5ef2aSThomas Huth #else 4185fcf5ef2aSThomas Huth TCGv_i32 t; 4186fcf5ef2aSThomas Huth 4187fcf5ef2aSThomas Huth CHK_HV; 4188fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4189fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4190fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4191154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4192154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4193fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4194fcf5ef2aSThomas Huth } 4195fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4196fcf5ef2aSThomas Huth 4197fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4198fcf5ef2aSThomas Huth { 4199fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4200efe843d8SDavid Gibson if (ctx->has_cfar) { 4201fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4202efe843d8SDavid Gibson } 4203fcf5ef2aSThomas Huth #endif 4204fcf5ef2aSThomas Huth } 4205fcf5ef2aSThomas Huth 420646d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 420746d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 420846d396bdSDaniel Henrique Barboza { 420946d396bdSDaniel Henrique Barboza /* 421046d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 421146d396bdSDaniel Henrique Barboza * instructions. 421246d396bdSDaniel Henrique Barboza */ 421346d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 421446d396bdSDaniel Henrique Barboza return; 421546d396bdSDaniel Henrique Barboza } 421646d396bdSDaniel Henrique Barboza 421746d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 421846d396bdSDaniel Henrique Barboza /* 421946d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 422046d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 422146d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 422246d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 422346d396bdSDaniel Henrique Barboza */ 422446d396bdSDaniel Henrique Barboza gen_icount_io_start(ctx); 422546d396bdSDaniel Henrique Barboza 422646d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 422746d396bdSDaniel Henrique Barboza #else 422846d396bdSDaniel Henrique Barboza /* 422946d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 423046d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 423146d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 423246d396bdSDaniel Henrique Barboza */ 423346d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 423446d396bdSDaniel Henrique Barboza 423546d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 423646d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 423746d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 423846d396bdSDaniel Henrique Barboza 423946d396bdSDaniel Henrique Barboza tcg_temp_free(t0); 424046d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 424146d396bdSDaniel Henrique Barboza } 424246d396bdSDaniel Henrique Barboza #else 424346d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 424446d396bdSDaniel Henrique Barboza { 424546d396bdSDaniel Henrique Barboza return; 424646d396bdSDaniel Henrique Barboza } 424746d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 424846d396bdSDaniel Henrique Barboza 4249fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4250fcf5ef2aSThomas Huth { 42516e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4252fcf5ef2aSThomas Huth } 4253fcf5ef2aSThomas Huth 42540e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 42550e3bf489SRoman Kapl { 42569498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 42570e3bf489SRoman Kapl gen_debug_exception(ctx); 42580e3bf489SRoman Kapl } else { 425946d396bdSDaniel Henrique Barboza /* 426046d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 426146d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 426246d396bdSDaniel Henrique Barboza */ 426346d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 426446d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 426546d396bdSDaniel Henrique Barboza } 426646d396bdSDaniel Henrique Barboza 42670e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 42680e3bf489SRoman Kapl } 42690e3bf489SRoman Kapl } 42700e3bf489SRoman Kapl 4271fcf5ef2aSThomas Huth /*** Branch ***/ 4272c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4273fcf5ef2aSThomas Huth { 4274fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4275fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4276fcf5ef2aSThomas Huth } 4277fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 427846d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4279fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4280fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 428107ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4282fcf5ef2aSThomas Huth } else { 4283fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 42840e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4285fcf5ef2aSThomas Huth } 4286fcf5ef2aSThomas Huth } 4287fcf5ef2aSThomas Huth 4288fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4289fcf5ef2aSThomas Huth { 4290fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4291fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4292fcf5ef2aSThomas Huth } 4293fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4294fcf5ef2aSThomas Huth } 4295fcf5ef2aSThomas Huth 4296fcf5ef2aSThomas Huth /* b ba bl bla */ 4297fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4298fcf5ef2aSThomas Huth { 4299fcf5ef2aSThomas Huth target_ulong li, target; 4300fcf5ef2aSThomas Huth 4301fcf5ef2aSThomas Huth /* sign extend LI */ 4302fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4303fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4304fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43052c2bcb1bSRichard Henderson target = ctx->cia + li; 4306fcf5ef2aSThomas Huth } else { 4307fcf5ef2aSThomas Huth target = li; 4308fcf5ef2aSThomas Huth } 4309fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4310b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4311fcf5ef2aSThomas Huth } 43122c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4313fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 43146086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4315fcf5ef2aSThomas Huth } 4316fcf5ef2aSThomas Huth 4317fcf5ef2aSThomas Huth #define BCOND_IM 0 4318fcf5ef2aSThomas Huth #define BCOND_LR 1 4319fcf5ef2aSThomas Huth #define BCOND_CTR 2 4320fcf5ef2aSThomas Huth #define BCOND_TAR 3 4321fcf5ef2aSThomas Huth 4322c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4323fcf5ef2aSThomas Huth { 4324fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4325fcf5ef2aSThomas Huth TCGLabel *l1; 4326fcf5ef2aSThomas Huth TCGv target; 43270e3bf489SRoman Kapl 4328fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4329fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4330efe843d8SDavid Gibson if (type == BCOND_CTR) { 4331fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4332efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4333fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4334efe843d8SDavid Gibson } else { 4335fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4336efe843d8SDavid Gibson } 4337fcf5ef2aSThomas Huth } else { 4338f764718dSRichard Henderson target = NULL; 4339fcf5ef2aSThomas Huth } 4340efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4341b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4342efe843d8SDavid Gibson } 4343fcf5ef2aSThomas Huth l1 = gen_new_label(); 4344fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4345fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4346fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4347fa200c95SGreg Kurz 4348fa200c95SGreg Kurz if (type == BCOND_CTR) { 4349fa200c95SGreg Kurz /* 4350fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4351fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4352fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 435315d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 435415d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 435515d68c5eSGreg Kurz * it basically useless and thus never used in real code. 435615d68c5eSGreg Kurz * 435715d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 435815d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 435915d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 436015d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 436115d68c5eSGreg Kurz * doing anything else harmful. 4362fa200c95SGreg Kurz */ 4363d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4364fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 43659acc95cdSGreg Kurz tcg_temp_free(temp); 43669acc95cdSGreg Kurz tcg_temp_free(target); 4367fcf5ef2aSThomas Huth return; 4368fcf5ef2aSThomas Huth } 4369fa200c95SGreg Kurz 4370fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4371fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4372fa200c95SGreg Kurz } else { 4373fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4374fa200c95SGreg Kurz } 4375fa200c95SGreg Kurz if (bo & 0x2) { 4376fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4377fa200c95SGreg Kurz } else { 4378fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4379fa200c95SGreg Kurz } 4380fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4381fa200c95SGreg Kurz } else { 4382fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4383fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4384fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4385fcf5ef2aSThomas Huth } else { 4386fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4387fcf5ef2aSThomas Huth } 4388fcf5ef2aSThomas Huth if (bo & 0x2) { 4389fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4390fcf5ef2aSThomas Huth } else { 4391fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4392fcf5ef2aSThomas Huth } 4393fa200c95SGreg Kurz } 4394fcf5ef2aSThomas Huth tcg_temp_free(temp); 4395fcf5ef2aSThomas Huth } 4396fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4397fcf5ef2aSThomas Huth /* Test CR */ 4398fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4399fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4400fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4401fcf5ef2aSThomas Huth 4402fcf5ef2aSThomas Huth if (bo & 0x8) { 4403fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4404fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4405fcf5ef2aSThomas Huth } else { 4406fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4407fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4408fcf5ef2aSThomas Huth } 4409fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4410fcf5ef2aSThomas Huth } 44112c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4412fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4413fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4414fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 44152c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4416fcf5ef2aSThomas Huth } else { 4417fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4418fcf5ef2aSThomas Huth } 4419fcf5ef2aSThomas Huth } else { 4420fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4421fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4422fcf5ef2aSThomas Huth } else { 4423fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4424fcf5ef2aSThomas Huth } 44250e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4426c4a2e3a9SRichard Henderson tcg_temp_free(target); 4427c4a2e3a9SRichard Henderson } 4428fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 44290e3bf489SRoman Kapl /* fallthrough case */ 4430fcf5ef2aSThomas Huth gen_set_label(l1); 4431b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4432fcf5ef2aSThomas Huth } 44336086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4434fcf5ef2aSThomas Huth } 4435fcf5ef2aSThomas Huth 4436fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4437fcf5ef2aSThomas Huth { 4438fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4439fcf5ef2aSThomas Huth } 4440fcf5ef2aSThomas Huth 4441fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4442fcf5ef2aSThomas Huth { 4443fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4444fcf5ef2aSThomas Huth } 4445fcf5ef2aSThomas Huth 4446fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4447fcf5ef2aSThomas Huth { 4448fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4449fcf5ef2aSThomas Huth } 4450fcf5ef2aSThomas Huth 4451fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4452fcf5ef2aSThomas Huth { 4453fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4454fcf5ef2aSThomas Huth } 4455fcf5ef2aSThomas Huth 4456fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4457fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4458fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4459fcf5ef2aSThomas Huth { \ 4460fcf5ef2aSThomas Huth uint8_t bitmask; \ 4461fcf5ef2aSThomas Huth int sh; \ 4462fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4463fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4464fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4465fcf5ef2aSThomas Huth if (sh > 0) \ 4466fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4467fcf5ef2aSThomas Huth else if (sh < 0) \ 4468fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4469fcf5ef2aSThomas Huth else \ 4470fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4471fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4472fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4473fcf5ef2aSThomas Huth if (sh > 0) \ 4474fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4475fcf5ef2aSThomas Huth else if (sh < 0) \ 4476fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4477fcf5ef2aSThomas Huth else \ 4478fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4479fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4480fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4481fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4482fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4483fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4484fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4485fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4486fcf5ef2aSThomas Huth } 4487fcf5ef2aSThomas Huth 4488fcf5ef2aSThomas Huth /* crand */ 4489fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4490fcf5ef2aSThomas Huth /* crandc */ 4491fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4492fcf5ef2aSThomas Huth /* creqv */ 4493fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4494fcf5ef2aSThomas Huth /* crnand */ 4495fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4496fcf5ef2aSThomas Huth /* crnor */ 4497fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4498fcf5ef2aSThomas Huth /* cror */ 4499fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4500fcf5ef2aSThomas Huth /* crorc */ 4501fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4502fcf5ef2aSThomas Huth /* crxor */ 4503fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4504fcf5ef2aSThomas Huth 4505fcf5ef2aSThomas Huth /* mcrf */ 4506fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4507fcf5ef2aSThomas Huth { 4508fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4509fcf5ef2aSThomas Huth } 4510fcf5ef2aSThomas Huth 4511fcf5ef2aSThomas Huth /*** System linkage ***/ 4512fcf5ef2aSThomas Huth 4513fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4514fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4515fcf5ef2aSThomas Huth { 4516fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4517fcf5ef2aSThomas Huth GEN_PRIV; 4518fcf5ef2aSThomas Huth #else 4519efe843d8SDavid Gibson /* 4520efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4521fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4522fcf5ef2aSThomas Huth */ 4523d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4524fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4525fcf5ef2aSThomas Huth return; 4526fcf5ef2aSThomas Huth } 4527fcf5ef2aSThomas Huth /* Restore CPU state */ 4528fcf5ef2aSThomas Huth CHK_SV; 4529f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45302c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4531fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 453259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4533fcf5ef2aSThomas Huth #endif 4534fcf5ef2aSThomas Huth } 4535fcf5ef2aSThomas Huth 4536fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4537fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4538fcf5ef2aSThomas Huth { 4539fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4540fcf5ef2aSThomas Huth GEN_PRIV; 4541fcf5ef2aSThomas Huth #else 4542fcf5ef2aSThomas Huth /* Restore CPU state */ 4543fcf5ef2aSThomas Huth CHK_SV; 4544f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45452c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4546fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 454759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4548fcf5ef2aSThomas Huth #endif 4549fcf5ef2aSThomas Huth } 4550fcf5ef2aSThomas Huth 45513c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45523c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 45533c89b8d6SNicholas Piggin { 45543c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 45553c89b8d6SNicholas Piggin GEN_PRIV; 45563c89b8d6SNicholas Piggin #else 45573c89b8d6SNicholas Piggin /* Restore CPU state */ 45583c89b8d6SNicholas Piggin CHK_SV; 4559f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45602c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 45613c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 456259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 45633c89b8d6SNicholas Piggin #endif 45643c89b8d6SNicholas Piggin } 45653c89b8d6SNicholas Piggin #endif 45663c89b8d6SNicholas Piggin 4567fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4568fcf5ef2aSThomas Huth { 4569fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4570fcf5ef2aSThomas Huth GEN_PRIV; 4571fcf5ef2aSThomas Huth #else 4572fcf5ef2aSThomas Huth /* Restore CPU state */ 4573fcf5ef2aSThomas Huth CHK_HV; 4574fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 457559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4576fcf5ef2aSThomas Huth #endif 4577fcf5ef2aSThomas Huth } 4578fcf5ef2aSThomas Huth #endif 4579fcf5ef2aSThomas Huth 4580fcf5ef2aSThomas Huth /* sc */ 4581fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4582fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4583fcf5ef2aSThomas Huth #else 4584fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 45853c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4586fcf5ef2aSThomas Huth #endif 4587fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4588fcf5ef2aSThomas Huth { 4589fcf5ef2aSThomas Huth uint32_t lev; 4590fcf5ef2aSThomas Huth 4591fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4592fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4593fcf5ef2aSThomas Huth } 4594fcf5ef2aSThomas Huth 45953c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 45963c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45973c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 45983c89b8d6SNicholas Piggin { 4599f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 46003c89b8d6SNicholas Piggin 4601f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 46022c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4603f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 46043c89b8d6SNicholas Piggin 46057a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 46063c89b8d6SNicholas Piggin } 46073c89b8d6SNicholas Piggin #endif 46083c89b8d6SNicholas Piggin #endif 46093c89b8d6SNicholas Piggin 4610fcf5ef2aSThomas Huth /*** Trap ***/ 4611fcf5ef2aSThomas Huth 4612fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4613fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4614fcf5ef2aSThomas Huth { 4615fcf5ef2aSThomas Huth /* Trap never */ 4616fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4617fcf5ef2aSThomas Huth return true; 4618fcf5ef2aSThomas Huth } 4619fcf5ef2aSThomas Huth /* Trap always */ 4620fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4621fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4622fcf5ef2aSThomas Huth return true; 4623fcf5ef2aSThomas Huth } 4624fcf5ef2aSThomas Huth return false; 4625fcf5ef2aSThomas Huth } 4626fcf5ef2aSThomas Huth 4627fcf5ef2aSThomas Huth /* tw */ 4628fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4629fcf5ef2aSThomas Huth { 4630fcf5ef2aSThomas Huth TCGv_i32 t0; 4631fcf5ef2aSThomas Huth 4632fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4633fcf5ef2aSThomas Huth return; 4634fcf5ef2aSThomas Huth } 4635fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4636fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4637fcf5ef2aSThomas Huth t0); 4638fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4639fcf5ef2aSThomas Huth } 4640fcf5ef2aSThomas Huth 4641fcf5ef2aSThomas Huth /* twi */ 4642fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4643fcf5ef2aSThomas Huth { 4644fcf5ef2aSThomas Huth TCGv t0; 4645fcf5ef2aSThomas Huth TCGv_i32 t1; 4646fcf5ef2aSThomas Huth 4647fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4648fcf5ef2aSThomas Huth return; 4649fcf5ef2aSThomas Huth } 4650fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4651fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4652fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4653fcf5ef2aSThomas Huth tcg_temp_free(t0); 4654fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4655fcf5ef2aSThomas Huth } 4656fcf5ef2aSThomas Huth 4657fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4658fcf5ef2aSThomas Huth /* td */ 4659fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4660fcf5ef2aSThomas Huth { 4661fcf5ef2aSThomas Huth TCGv_i32 t0; 4662fcf5ef2aSThomas Huth 4663fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4664fcf5ef2aSThomas Huth return; 4665fcf5ef2aSThomas Huth } 4666fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4667fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4668fcf5ef2aSThomas Huth t0); 4669fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4670fcf5ef2aSThomas Huth } 4671fcf5ef2aSThomas Huth 4672fcf5ef2aSThomas Huth /* tdi */ 4673fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4674fcf5ef2aSThomas Huth { 4675fcf5ef2aSThomas Huth TCGv t0; 4676fcf5ef2aSThomas Huth TCGv_i32 t1; 4677fcf5ef2aSThomas Huth 4678fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4679fcf5ef2aSThomas Huth return; 4680fcf5ef2aSThomas Huth } 4681fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4682fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4683fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4684fcf5ef2aSThomas Huth tcg_temp_free(t0); 4685fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4686fcf5ef2aSThomas Huth } 4687fcf5ef2aSThomas Huth #endif 4688fcf5ef2aSThomas Huth 4689fcf5ef2aSThomas Huth /*** Processor control ***/ 4690fcf5ef2aSThomas Huth 4691fcf5ef2aSThomas Huth /* mcrxr */ 4692fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4693fcf5ef2aSThomas Huth { 4694fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4695fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4696fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4697fcf5ef2aSThomas Huth 4698fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4699fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4700fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4701fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4702fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4703fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4704fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4705fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4706fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4707fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4708fcf5ef2aSThomas Huth 4709fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4710fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4711fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4712fcf5ef2aSThomas Huth } 4713fcf5ef2aSThomas Huth 4714b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4715b63d0434SNikunj A Dadhania /* mcrxrx */ 4716b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4717b63d0434SNikunj A Dadhania { 4718b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4719b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4720b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4721b63d0434SNikunj A Dadhania 4722b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4723b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4724b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4725b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4726b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4727b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4728b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4729b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4730b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4731b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4732b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4733b63d0434SNikunj A Dadhania } 4734b63d0434SNikunj A Dadhania #endif 4735b63d0434SNikunj A Dadhania 4736fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4737fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4738fcf5ef2aSThomas Huth { 4739fcf5ef2aSThomas Huth uint32_t crm, crn; 4740fcf5ef2aSThomas Huth 4741fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4742fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4743fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4744fcf5ef2aSThomas Huth crn = ctz32(crm); 4745fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4746fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4747fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4748fcf5ef2aSThomas Huth } 4749fcf5ef2aSThomas Huth } else { 4750fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4751fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4752fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4753fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4754fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4755fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4756fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4757fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4758fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4759fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4760fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4761fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4762fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4763fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4764fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4765fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4766fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4767fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4768fcf5ef2aSThomas Huth } 4769fcf5ef2aSThomas Huth } 4770fcf5ef2aSThomas Huth 4771fcf5ef2aSThomas Huth /* mfmsr */ 4772fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4773fcf5ef2aSThomas Huth { 4774fcf5ef2aSThomas Huth CHK_SV; 4775fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4776fcf5ef2aSThomas Huth } 4777fcf5ef2aSThomas Huth 4778fcf5ef2aSThomas Huth /* mfspr */ 4779fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4780fcf5ef2aSThomas Huth { 4781fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4782fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4783fcf5ef2aSThomas Huth 4784fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4785fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4786fcf5ef2aSThomas Huth #else 4787fcf5ef2aSThomas Huth if (ctx->pr) { 4788fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4789fcf5ef2aSThomas Huth } else if (ctx->hv) { 4790fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4791fcf5ef2aSThomas Huth } else { 4792fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4793fcf5ef2aSThomas Huth } 4794fcf5ef2aSThomas Huth #endif 4795fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4796fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4797fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4798fcf5ef2aSThomas Huth } else { 4799fcf5ef2aSThomas Huth /* Privilege exception */ 4800efe843d8SDavid Gibson /* 4801efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4802fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4803fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4804fcf5ef2aSThomas Huth */ 4805fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 480631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 480731085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48082c2bcb1bSRichard Henderson ctx->cia); 4809fcf5ef2aSThomas Huth } 4810fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4811fcf5ef2aSThomas Huth } 4812fcf5ef2aSThomas Huth } else { 4813fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4814fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4815fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4816fcf5ef2aSThomas Huth /* This is a nop */ 4817fcf5ef2aSThomas Huth return; 4818fcf5ef2aSThomas Huth } 4819fcf5ef2aSThomas Huth /* Not defined */ 482031085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 482131085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 48222c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4823fcf5ef2aSThomas Huth 4824efe843d8SDavid Gibson /* 4825efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4826efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4827fcf5ef2aSThomas Huth */ 4828fcf5ef2aSThomas Huth if (sprn & 0x10) { 4829fcf5ef2aSThomas Huth if (ctx->pr) { 4830fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4831fcf5ef2aSThomas Huth } 4832fcf5ef2aSThomas Huth } else { 4833fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4834fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4835fcf5ef2aSThomas Huth } 4836fcf5ef2aSThomas Huth } 4837fcf5ef2aSThomas Huth } 4838fcf5ef2aSThomas Huth } 4839fcf5ef2aSThomas Huth 4840fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4841fcf5ef2aSThomas Huth { 4842fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4843fcf5ef2aSThomas Huth } 4844fcf5ef2aSThomas Huth 4845fcf5ef2aSThomas Huth /* mftb */ 4846fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4847fcf5ef2aSThomas Huth { 4848fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4849fcf5ef2aSThomas Huth } 4850fcf5ef2aSThomas Huth 4851fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4852fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4853fcf5ef2aSThomas Huth { 4854fcf5ef2aSThomas Huth uint32_t crm, crn; 4855fcf5ef2aSThomas Huth 4856fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4857fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4858fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4859fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4860fcf5ef2aSThomas Huth crn = ctz32(crm); 4861fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4862fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4863fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4864fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4865fcf5ef2aSThomas Huth } 4866fcf5ef2aSThomas Huth } else { 4867fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4868fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4869fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4870fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4871fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4872fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4873fcf5ef2aSThomas Huth } 4874fcf5ef2aSThomas Huth } 4875fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4876fcf5ef2aSThomas Huth } 4877fcf5ef2aSThomas Huth } 4878fcf5ef2aSThomas Huth 4879fcf5ef2aSThomas Huth /* mtmsr */ 4880fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4881fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4882fcf5ef2aSThomas Huth { 4883caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4884caf590ddSNicholas Piggin gen_invalid(ctx); 4885caf590ddSNicholas Piggin return; 4886caf590ddSNicholas Piggin } 4887caf590ddSNicholas Piggin 4888fcf5ef2aSThomas Huth CHK_SV; 4889fcf5ef2aSThomas Huth 4890fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48916fa5726bSMatheus Ferst TCGv t0, t1; 48926fa5726bSMatheus Ferst target_ulong mask; 48936fa5726bSMatheus Ferst 48946fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48956fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48966fa5726bSMatheus Ferst 4897f5b6daacSRichard Henderson gen_icount_io_start(ctx); 48986fa5726bSMatheus Ferst 4899fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49005ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 49016fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4902fcf5ef2aSThomas Huth } else { 49036fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 49046fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 49056fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4906efe843d8SDavid Gibson /* 4907efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4908efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4909efe843d8SDavid Gibson * ppc_store_msr 4910fcf5ef2aSThomas Huth */ 4911b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4912fcf5ef2aSThomas Huth } 49136fa5726bSMatheus Ferst 49146fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 49156fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 49166fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 49176fa5726bSMatheus Ferst 49186fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 49196fa5726bSMatheus Ferst 49205ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4921d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 49226fa5726bSMatheus Ferst 49236fa5726bSMatheus Ferst tcg_temp_free(t0); 49246fa5726bSMatheus Ferst tcg_temp_free(t1); 4925fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4926fcf5ef2aSThomas Huth } 4927fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4928fcf5ef2aSThomas Huth 4929fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4930fcf5ef2aSThomas Huth { 4931fcf5ef2aSThomas Huth CHK_SV; 4932fcf5ef2aSThomas Huth 4933fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 49346fa5726bSMatheus Ferst TCGv t0, t1; 49356fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 49366fa5726bSMatheus Ferst 49376fa5726bSMatheus Ferst t0 = tcg_temp_new(); 49386fa5726bSMatheus Ferst t1 = tcg_temp_new(); 49396fa5726bSMatheus Ferst 4940f5b6daacSRichard Henderson gen_icount_io_start(ctx); 4941fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49425ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 49436fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4944fcf5ef2aSThomas Huth } else { 49456fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 49466fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4947fcf5ef2aSThomas Huth 4948efe843d8SDavid Gibson /* 4949efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4950efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4951efe843d8SDavid Gibson * ppc_store_msr 4952fcf5ef2aSThomas Huth */ 4953b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4954fcf5ef2aSThomas Huth } 49556fa5726bSMatheus Ferst 49566fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 49576fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 49586fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 49596fa5726bSMatheus Ferst 49606fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 49616fa5726bSMatheus Ferst 49625ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4963d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 49646fa5726bSMatheus Ferst 49656fa5726bSMatheus Ferst tcg_temp_free(t0); 49666fa5726bSMatheus Ferst tcg_temp_free(t1); 4967fcf5ef2aSThomas Huth #endif 4968fcf5ef2aSThomas Huth } 4969fcf5ef2aSThomas Huth 4970fcf5ef2aSThomas Huth /* mtspr */ 4971fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4972fcf5ef2aSThomas Huth { 4973fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4974fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4975fcf5ef2aSThomas Huth 4976fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4977fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4978fcf5ef2aSThomas Huth #else 4979fcf5ef2aSThomas Huth if (ctx->pr) { 4980fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4981fcf5ef2aSThomas Huth } else if (ctx->hv) { 4982fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4983fcf5ef2aSThomas Huth } else { 4984fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4985fcf5ef2aSThomas Huth } 4986fcf5ef2aSThomas Huth #endif 4987fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4988fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4989fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4990fcf5ef2aSThomas Huth } else { 4991fcf5ef2aSThomas Huth /* Privilege exception */ 499231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 499331085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 49942c2bcb1bSRichard Henderson ctx->cia); 4995fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4996fcf5ef2aSThomas Huth } 4997fcf5ef2aSThomas Huth } else { 4998fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4999fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5000fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5001fcf5ef2aSThomas Huth /* This is a nop */ 5002fcf5ef2aSThomas Huth return; 5003fcf5ef2aSThomas Huth } 5004fcf5ef2aSThomas Huth 5005fcf5ef2aSThomas Huth /* Not defined */ 500631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 500731085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 50082c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5009fcf5ef2aSThomas Huth 5010fcf5ef2aSThomas Huth 5011efe843d8SDavid Gibson /* 5012efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5013efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5014fcf5ef2aSThomas Huth */ 5015fcf5ef2aSThomas Huth if (sprn & 0x10) { 5016fcf5ef2aSThomas Huth if (ctx->pr) { 5017fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5018fcf5ef2aSThomas Huth } 5019fcf5ef2aSThomas Huth } else { 5020fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5021fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5022fcf5ef2aSThomas Huth } 5023fcf5ef2aSThomas Huth } 5024fcf5ef2aSThomas Huth } 5025fcf5ef2aSThomas Huth } 5026fcf5ef2aSThomas Huth 5027fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5028fcf5ef2aSThomas Huth /* setb */ 5029fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5030fcf5ef2aSThomas Huth { 5031fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 50326f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 50336f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 5034fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5035fcf5ef2aSThomas Huth 5036fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5037fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5038fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5039fcf5ef2aSThomas Huth 5040fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5041fcf5ef2aSThomas Huth } 5042fcf5ef2aSThomas Huth #endif 5043fcf5ef2aSThomas Huth 5044fcf5ef2aSThomas Huth /*** Cache management ***/ 5045fcf5ef2aSThomas Huth 5046fcf5ef2aSThomas Huth /* dcbf */ 5047fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5048fcf5ef2aSThomas Huth { 5049fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5050fcf5ef2aSThomas Huth TCGv t0; 5051fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5052fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5053fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5054fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5055fcf5ef2aSThomas Huth tcg_temp_free(t0); 5056fcf5ef2aSThomas Huth } 5057fcf5ef2aSThomas Huth 505850728199SRoman Kapl /* dcbfep (external PID dcbf) */ 505950728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 506050728199SRoman Kapl { 506150728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 506250728199SRoman Kapl TCGv t0; 506350728199SRoman Kapl CHK_SV; 506450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 506550728199SRoman Kapl t0 = tcg_temp_new(); 506650728199SRoman Kapl gen_addr_reg_index(ctx, t0); 506750728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 506850728199SRoman Kapl tcg_temp_free(t0); 506950728199SRoman Kapl } 507050728199SRoman Kapl 5071fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5072fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5073fcf5ef2aSThomas Huth { 5074fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5075fcf5ef2aSThomas Huth GEN_PRIV; 5076fcf5ef2aSThomas Huth #else 5077fcf5ef2aSThomas Huth TCGv EA, val; 5078fcf5ef2aSThomas Huth 5079fcf5ef2aSThomas Huth CHK_SV; 5080fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5081fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5082fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5083fcf5ef2aSThomas Huth val = tcg_temp_new(); 5084fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5085fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5086fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5087fcf5ef2aSThomas Huth tcg_temp_free(val); 5088fcf5ef2aSThomas Huth tcg_temp_free(EA); 5089fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5090fcf5ef2aSThomas Huth } 5091fcf5ef2aSThomas Huth 5092fcf5ef2aSThomas Huth /* dcdst */ 5093fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5094fcf5ef2aSThomas Huth { 5095fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5096fcf5ef2aSThomas Huth TCGv t0; 5097fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5098fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5099fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5100fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5101fcf5ef2aSThomas Huth tcg_temp_free(t0); 5102fcf5ef2aSThomas Huth } 5103fcf5ef2aSThomas Huth 510450728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 510550728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 510650728199SRoman Kapl { 510750728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 510850728199SRoman Kapl TCGv t0; 510950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 511050728199SRoman Kapl t0 = tcg_temp_new(); 511150728199SRoman Kapl gen_addr_reg_index(ctx, t0); 511250728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 511350728199SRoman Kapl tcg_temp_free(t0); 511450728199SRoman Kapl } 511550728199SRoman Kapl 5116fcf5ef2aSThomas Huth /* dcbt */ 5117fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5118fcf5ef2aSThomas Huth { 5119efe843d8SDavid Gibson /* 5120efe843d8SDavid Gibson * interpreted as no-op 5121efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5122efe843d8SDavid Gibson * does not generate any exception 5123fcf5ef2aSThomas Huth */ 5124fcf5ef2aSThomas Huth } 5125fcf5ef2aSThomas Huth 512650728199SRoman Kapl /* dcbtep */ 512750728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 512850728199SRoman Kapl { 5129efe843d8SDavid Gibson /* 5130efe843d8SDavid Gibson * interpreted as no-op 5131efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5132efe843d8SDavid Gibson * does not generate any exception 513350728199SRoman Kapl */ 513450728199SRoman Kapl } 513550728199SRoman Kapl 5136fcf5ef2aSThomas Huth /* dcbtst */ 5137fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5138fcf5ef2aSThomas Huth { 5139efe843d8SDavid Gibson /* 5140efe843d8SDavid Gibson * interpreted as no-op 5141efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5142efe843d8SDavid Gibson * does not generate any exception 5143fcf5ef2aSThomas Huth */ 5144fcf5ef2aSThomas Huth } 5145fcf5ef2aSThomas Huth 514650728199SRoman Kapl /* dcbtstep */ 514750728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 514850728199SRoman Kapl { 5149efe843d8SDavid Gibson /* 5150efe843d8SDavid Gibson * interpreted as no-op 5151efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5152efe843d8SDavid Gibson * does not generate any exception 515350728199SRoman Kapl */ 515450728199SRoman Kapl } 515550728199SRoman Kapl 5156fcf5ef2aSThomas Huth /* dcbtls */ 5157fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5158fcf5ef2aSThomas Huth { 5159fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5160fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5161fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5162fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5163fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5164fcf5ef2aSThomas Huth tcg_temp_free(t0); 5165fcf5ef2aSThomas Huth } 5166fcf5ef2aSThomas Huth 5167fcf5ef2aSThomas Huth /* dcbz */ 5168fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5169fcf5ef2aSThomas Huth { 5170fcf5ef2aSThomas Huth TCGv tcgv_addr; 5171fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5172fcf5ef2aSThomas Huth 5173fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5174fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5175fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5176fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5177fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5178fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5179fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5180fcf5ef2aSThomas Huth } 5181fcf5ef2aSThomas Huth 518250728199SRoman Kapl /* dcbzep */ 518350728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 518450728199SRoman Kapl { 518550728199SRoman Kapl TCGv tcgv_addr; 518650728199SRoman Kapl TCGv_i32 tcgv_op; 518750728199SRoman Kapl 518850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 518950728199SRoman Kapl tcgv_addr = tcg_temp_new(); 519050728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 519150728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 519250728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 519350728199SRoman Kapl tcg_temp_free(tcgv_addr); 519450728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 519550728199SRoman Kapl } 519650728199SRoman Kapl 5197fcf5ef2aSThomas Huth /* dst / dstt */ 5198fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5199fcf5ef2aSThomas Huth { 5200fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5201fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5202fcf5ef2aSThomas Huth } else { 5203fcf5ef2aSThomas Huth /* interpreted as no-op */ 5204fcf5ef2aSThomas Huth } 5205fcf5ef2aSThomas Huth } 5206fcf5ef2aSThomas Huth 5207fcf5ef2aSThomas Huth /* dstst /dststt */ 5208fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5209fcf5ef2aSThomas Huth { 5210fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5211fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5212fcf5ef2aSThomas Huth } else { 5213fcf5ef2aSThomas Huth /* interpreted as no-op */ 5214fcf5ef2aSThomas Huth } 5215fcf5ef2aSThomas Huth 5216fcf5ef2aSThomas Huth } 5217fcf5ef2aSThomas Huth 5218fcf5ef2aSThomas Huth /* dss / dssall */ 5219fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5220fcf5ef2aSThomas Huth { 5221fcf5ef2aSThomas Huth /* interpreted as no-op */ 5222fcf5ef2aSThomas Huth } 5223fcf5ef2aSThomas Huth 5224fcf5ef2aSThomas Huth /* icbi */ 5225fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5226fcf5ef2aSThomas Huth { 5227fcf5ef2aSThomas Huth TCGv t0; 5228fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5229fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5230fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5231fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5232fcf5ef2aSThomas Huth tcg_temp_free(t0); 5233fcf5ef2aSThomas Huth } 5234fcf5ef2aSThomas Huth 523550728199SRoman Kapl /* icbiep */ 523650728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 523750728199SRoman Kapl { 523850728199SRoman Kapl TCGv t0; 523950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 524050728199SRoman Kapl t0 = tcg_temp_new(); 524150728199SRoman Kapl gen_addr_reg_index(ctx, t0); 524250728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 524350728199SRoman Kapl tcg_temp_free(t0); 524450728199SRoman Kapl } 524550728199SRoman Kapl 5246fcf5ef2aSThomas Huth /* Optional: */ 5247fcf5ef2aSThomas Huth /* dcba */ 5248fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5249fcf5ef2aSThomas Huth { 5250efe843d8SDavid Gibson /* 5251efe843d8SDavid Gibson * interpreted as no-op 5252efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5253fcf5ef2aSThomas Huth * but does not generate any exception 5254fcf5ef2aSThomas Huth */ 5255fcf5ef2aSThomas Huth } 5256fcf5ef2aSThomas Huth 5257fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5258fcf5ef2aSThomas Huth /* Supervisor only: */ 5259fcf5ef2aSThomas Huth 5260fcf5ef2aSThomas Huth /* mfsr */ 5261fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5262fcf5ef2aSThomas Huth { 5263fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5264fcf5ef2aSThomas Huth GEN_PRIV; 5265fcf5ef2aSThomas Huth #else 5266fcf5ef2aSThomas Huth TCGv t0; 5267fcf5ef2aSThomas Huth 5268fcf5ef2aSThomas Huth CHK_SV; 5269fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5270fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5271fcf5ef2aSThomas Huth tcg_temp_free(t0); 5272fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5273fcf5ef2aSThomas Huth } 5274fcf5ef2aSThomas Huth 5275fcf5ef2aSThomas Huth /* mfsrin */ 5276fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5277fcf5ef2aSThomas Huth { 5278fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5279fcf5ef2aSThomas Huth GEN_PRIV; 5280fcf5ef2aSThomas Huth #else 5281fcf5ef2aSThomas Huth TCGv t0; 5282fcf5ef2aSThomas Huth 5283fcf5ef2aSThomas Huth CHK_SV; 5284fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5285e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5286fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5287fcf5ef2aSThomas Huth tcg_temp_free(t0); 5288fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5289fcf5ef2aSThomas Huth } 5290fcf5ef2aSThomas Huth 5291fcf5ef2aSThomas Huth /* mtsr */ 5292fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5293fcf5ef2aSThomas Huth { 5294fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5295fcf5ef2aSThomas Huth GEN_PRIV; 5296fcf5ef2aSThomas Huth #else 5297fcf5ef2aSThomas Huth TCGv t0; 5298fcf5ef2aSThomas Huth 5299fcf5ef2aSThomas Huth CHK_SV; 5300fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5301fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5302fcf5ef2aSThomas Huth tcg_temp_free(t0); 5303fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5304fcf5ef2aSThomas Huth } 5305fcf5ef2aSThomas Huth 5306fcf5ef2aSThomas Huth /* mtsrin */ 5307fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5308fcf5ef2aSThomas Huth { 5309fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5310fcf5ef2aSThomas Huth GEN_PRIV; 5311fcf5ef2aSThomas Huth #else 5312fcf5ef2aSThomas Huth TCGv t0; 5313fcf5ef2aSThomas Huth CHK_SV; 5314fcf5ef2aSThomas Huth 5315fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5316e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5317fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5318fcf5ef2aSThomas Huth tcg_temp_free(t0); 5319fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5320fcf5ef2aSThomas Huth } 5321fcf5ef2aSThomas Huth 5322fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5323fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5324fcf5ef2aSThomas Huth 5325fcf5ef2aSThomas Huth /* mfsr */ 5326fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5327fcf5ef2aSThomas Huth { 5328fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5329fcf5ef2aSThomas Huth GEN_PRIV; 5330fcf5ef2aSThomas Huth #else 5331fcf5ef2aSThomas Huth TCGv t0; 5332fcf5ef2aSThomas Huth 5333fcf5ef2aSThomas Huth CHK_SV; 5334fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5335fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5336fcf5ef2aSThomas Huth tcg_temp_free(t0); 5337fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5338fcf5ef2aSThomas Huth } 5339fcf5ef2aSThomas Huth 5340fcf5ef2aSThomas Huth /* mfsrin */ 5341fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5342fcf5ef2aSThomas Huth { 5343fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5344fcf5ef2aSThomas Huth GEN_PRIV; 5345fcf5ef2aSThomas Huth #else 5346fcf5ef2aSThomas Huth TCGv t0; 5347fcf5ef2aSThomas Huth 5348fcf5ef2aSThomas Huth CHK_SV; 5349fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5350e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5351fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5352fcf5ef2aSThomas Huth tcg_temp_free(t0); 5353fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5354fcf5ef2aSThomas Huth } 5355fcf5ef2aSThomas Huth 5356fcf5ef2aSThomas Huth /* mtsr */ 5357fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5358fcf5ef2aSThomas Huth { 5359fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5360fcf5ef2aSThomas Huth GEN_PRIV; 5361fcf5ef2aSThomas Huth #else 5362fcf5ef2aSThomas Huth TCGv t0; 5363fcf5ef2aSThomas Huth 5364fcf5ef2aSThomas Huth CHK_SV; 5365fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5366fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5367fcf5ef2aSThomas Huth tcg_temp_free(t0); 5368fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5369fcf5ef2aSThomas Huth } 5370fcf5ef2aSThomas Huth 5371fcf5ef2aSThomas Huth /* mtsrin */ 5372fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5373fcf5ef2aSThomas Huth { 5374fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5375fcf5ef2aSThomas Huth GEN_PRIV; 5376fcf5ef2aSThomas Huth #else 5377fcf5ef2aSThomas Huth TCGv t0; 5378fcf5ef2aSThomas Huth 5379fcf5ef2aSThomas Huth CHK_SV; 5380fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5381e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5382fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5383fcf5ef2aSThomas Huth tcg_temp_free(t0); 5384fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5385fcf5ef2aSThomas Huth } 5386fcf5ef2aSThomas Huth 5387fcf5ef2aSThomas Huth /* slbmte */ 5388fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5389fcf5ef2aSThomas Huth { 5390fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5391fcf5ef2aSThomas Huth GEN_PRIV; 5392fcf5ef2aSThomas Huth #else 5393fcf5ef2aSThomas Huth CHK_SV; 5394fcf5ef2aSThomas Huth 5395fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5396fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5397fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5398fcf5ef2aSThomas Huth } 5399fcf5ef2aSThomas Huth 5400fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5401fcf5ef2aSThomas Huth { 5402fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5403fcf5ef2aSThomas Huth GEN_PRIV; 5404fcf5ef2aSThomas Huth #else 5405fcf5ef2aSThomas Huth CHK_SV; 5406fcf5ef2aSThomas Huth 5407fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5408fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5409fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5410fcf5ef2aSThomas Huth } 5411fcf5ef2aSThomas Huth 5412fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5413fcf5ef2aSThomas Huth { 5414fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5415fcf5ef2aSThomas Huth GEN_PRIV; 5416fcf5ef2aSThomas Huth #else 5417fcf5ef2aSThomas Huth CHK_SV; 5418fcf5ef2aSThomas Huth 5419fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5420fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5421fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5422fcf5ef2aSThomas Huth } 5423fcf5ef2aSThomas Huth 5424fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5425fcf5ef2aSThomas Huth { 5426fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5427fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5428fcf5ef2aSThomas Huth #else 5429fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5430fcf5ef2aSThomas Huth 5431fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5432fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5433fcf5ef2aSThomas Huth return; 5434fcf5ef2aSThomas Huth } 5435fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5436fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5437fcf5ef2aSThomas Huth l1 = gen_new_label(); 5438fcf5ef2aSThomas Huth l2 = gen_new_label(); 5439fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5440fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5441efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5442fcf5ef2aSThomas Huth tcg_gen_br(l2); 5443fcf5ef2aSThomas Huth gen_set_label(l1); 5444fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5445fcf5ef2aSThomas Huth gen_set_label(l2); 5446fcf5ef2aSThomas Huth #endif 5447fcf5ef2aSThomas Huth } 5448fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5449fcf5ef2aSThomas Huth 5450fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5451fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5452fcf5ef2aSThomas Huth 5453fcf5ef2aSThomas Huth /* tlbia */ 5454fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5455fcf5ef2aSThomas Huth { 5456fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5457fcf5ef2aSThomas Huth GEN_PRIV; 5458fcf5ef2aSThomas Huth #else 5459fcf5ef2aSThomas Huth CHK_HV; 5460fcf5ef2aSThomas Huth 5461fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5462fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5463fcf5ef2aSThomas Huth } 5464fcf5ef2aSThomas Huth 5465fcf5ef2aSThomas Huth /* tlbiel */ 5466fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5467fcf5ef2aSThomas Huth { 5468fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5469fcf5ef2aSThomas Huth GEN_PRIV; 5470fcf5ef2aSThomas Huth #else 547192fb92d3SMatheus Ferst bool psr = (ctx->opcode >> 17) & 0x1; 547292fb92d3SMatheus Ferst 547392fb92d3SMatheus Ferst if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) { 547492fb92d3SMatheus Ferst /* 547592fb92d3SMatheus Ferst * tlbiel is privileged except when PSR=0 and HR=1, making it 547692fb92d3SMatheus Ferst * hypervisor privileged. 547792fb92d3SMatheus Ferst */ 547892fb92d3SMatheus Ferst GEN_PRIV; 547992fb92d3SMatheus Ferst } 5480fcf5ef2aSThomas Huth 5481fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5482fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5483fcf5ef2aSThomas Huth } 5484fcf5ef2aSThomas Huth 5485fcf5ef2aSThomas Huth /* tlbie */ 5486fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5487fcf5ef2aSThomas Huth { 5488fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5489fcf5ef2aSThomas Huth GEN_PRIV; 5490fcf5ef2aSThomas Huth #else 549192fb92d3SMatheus Ferst bool psr = (ctx->opcode >> 17) & 0x1; 5492fcf5ef2aSThomas Huth TCGv_i32 t1; 5493c6fd28fdSSuraj Jitindar Singh 549492fb92d3SMatheus Ferst if (ctx->pr) { 549592fb92d3SMatheus Ferst /* tlbie is privileged... */ 549692fb92d3SMatheus Ferst GEN_PRIV; 549792fb92d3SMatheus Ferst } else if (!ctx->hv) { 549892fb92d3SMatheus Ferst if (!ctx->gtse || (!psr && ctx->hr)) { 549992fb92d3SMatheus Ferst /* 550092fb92d3SMatheus Ferst * ... except when GTSE=0 or when PSR=0 and HR=1, making it 550192fb92d3SMatheus Ferst * hypervisor privileged. 550292fb92d3SMatheus Ferst */ 550392fb92d3SMatheus Ferst GEN_PRIV; 550492fb92d3SMatheus Ferst } 5505c6fd28fdSSuraj Jitindar Singh } 5506fcf5ef2aSThomas Huth 5507fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5508fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5509fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5510fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5511fcf5ef2aSThomas Huth tcg_temp_free(t0); 5512fcf5ef2aSThomas Huth } else { 5513fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5514fcf5ef2aSThomas Huth } 5515fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 5516fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5517fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5518fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5519fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5520fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5521fcf5ef2aSThomas Huth } 5522fcf5ef2aSThomas Huth 5523fcf5ef2aSThomas Huth /* tlbsync */ 5524fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5525fcf5ef2aSThomas Huth { 5526fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5527fcf5ef2aSThomas Huth GEN_PRIV; 5528fcf5ef2aSThomas Huth #else 552991c60f12SCédric Le Goater 553091c60f12SCédric Le Goater if (ctx->gtse) { 553191c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 553291c60f12SCédric Le Goater } else { 553391c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 553491c60f12SCédric Le Goater } 5535fcf5ef2aSThomas Huth 5536fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5537fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5538fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5539fcf5ef2aSThomas Huth } 5540fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5541fcf5ef2aSThomas Huth } 5542fcf5ef2aSThomas Huth 5543fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5544fcf5ef2aSThomas Huth /* slbia */ 5545fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5546fcf5ef2aSThomas Huth { 5547fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5548fcf5ef2aSThomas Huth GEN_PRIV; 5549fcf5ef2aSThomas Huth #else 55500418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 55510418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 55520418bf78SNicholas Piggin 5553fcf5ef2aSThomas Huth CHK_SV; 5554fcf5ef2aSThomas Huth 55550418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 55563119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 5557fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5558fcf5ef2aSThomas Huth } 5559fcf5ef2aSThomas Huth 5560fcf5ef2aSThomas Huth /* slbie */ 5561fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5562fcf5ef2aSThomas Huth { 5563fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5564fcf5ef2aSThomas Huth GEN_PRIV; 5565fcf5ef2aSThomas Huth #else 5566fcf5ef2aSThomas Huth CHK_SV; 5567fcf5ef2aSThomas Huth 5568fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5569fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5570fcf5ef2aSThomas Huth } 5571a63f1dfcSNikunj A Dadhania 5572a63f1dfcSNikunj A Dadhania /* slbieg */ 5573a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5574a63f1dfcSNikunj A Dadhania { 5575a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5576a63f1dfcSNikunj A Dadhania GEN_PRIV; 5577a63f1dfcSNikunj A Dadhania #else 5578a63f1dfcSNikunj A Dadhania CHK_SV; 5579a63f1dfcSNikunj A Dadhania 5580a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5581a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5582a63f1dfcSNikunj A Dadhania } 5583a63f1dfcSNikunj A Dadhania 558462d897caSNikunj A Dadhania /* slbsync */ 558562d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 558662d897caSNikunj A Dadhania { 558762d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 558862d897caSNikunj A Dadhania GEN_PRIV; 558962d897caSNikunj A Dadhania #else 559062d897caSNikunj A Dadhania CHK_SV; 559162d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 559262d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 559362d897caSNikunj A Dadhania } 559462d897caSNikunj A Dadhania 5595fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5596fcf5ef2aSThomas Huth 5597fcf5ef2aSThomas Huth /*** External control ***/ 5598fcf5ef2aSThomas Huth /* Optional: */ 5599fcf5ef2aSThomas Huth 5600fcf5ef2aSThomas Huth /* eciwx */ 5601fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5602fcf5ef2aSThomas Huth { 5603fcf5ef2aSThomas Huth TCGv t0; 5604fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5605fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5606fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5607fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5608c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5609c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5610fcf5ef2aSThomas Huth tcg_temp_free(t0); 5611fcf5ef2aSThomas Huth } 5612fcf5ef2aSThomas Huth 5613fcf5ef2aSThomas Huth /* ecowx */ 5614fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5615fcf5ef2aSThomas Huth { 5616fcf5ef2aSThomas Huth TCGv t0; 5617fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5618fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5619fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5620fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5621c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5622c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5623fcf5ef2aSThomas Huth tcg_temp_free(t0); 5624fcf5ef2aSThomas Huth } 5625fcf5ef2aSThomas Huth 5626fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5627fcf5ef2aSThomas Huth 5628fcf5ef2aSThomas Huth /* abs - abs. */ 5629fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5630fcf5ef2aSThomas Huth { 5631fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5632fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5633fe21b785SRichard Henderson 5634fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5635efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5636fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5637fcf5ef2aSThomas Huth } 5638efe843d8SDavid Gibson } 5639fcf5ef2aSThomas Huth 5640fcf5ef2aSThomas Huth /* abso - abso. */ 5641fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5642fcf5ef2aSThomas Huth { 5643fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5644fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5645fe21b785SRichard Henderson 5646fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5647fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5648fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5649efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5650fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5651fcf5ef2aSThomas Huth } 5652efe843d8SDavid Gibson } 5653fcf5ef2aSThomas Huth 5654fcf5ef2aSThomas Huth /* clcs */ 5655fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5656fcf5ef2aSThomas Huth { 5657fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5658fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5659fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5660fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5661fcf5ef2aSThomas Huth } 5662fcf5ef2aSThomas Huth 5663fcf5ef2aSThomas Huth /* div - div. */ 5664fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5665fcf5ef2aSThomas Huth { 5666fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5667fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5668efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5669fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5670fcf5ef2aSThomas Huth } 5671efe843d8SDavid Gibson } 5672fcf5ef2aSThomas Huth 5673fcf5ef2aSThomas Huth /* divo - divo. */ 5674fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5675fcf5ef2aSThomas Huth { 5676fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5677fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5678efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5679fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5680fcf5ef2aSThomas Huth } 5681efe843d8SDavid Gibson } 5682fcf5ef2aSThomas Huth 5683fcf5ef2aSThomas Huth /* divs - divs. */ 5684fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5685fcf5ef2aSThomas Huth { 5686fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5687fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5688efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5689fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5690fcf5ef2aSThomas Huth } 5691efe843d8SDavid Gibson } 5692fcf5ef2aSThomas Huth 5693fcf5ef2aSThomas Huth /* divso - divso. */ 5694fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5695fcf5ef2aSThomas Huth { 5696fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5697fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5698efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5699fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5700fcf5ef2aSThomas Huth } 5701efe843d8SDavid Gibson } 5702fcf5ef2aSThomas Huth 5703fcf5ef2aSThomas Huth /* doz - doz. */ 5704fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5705fcf5ef2aSThomas Huth { 5706fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5707fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5708efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5709efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5710efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5711efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 5712fcf5ef2aSThomas Huth tcg_gen_br(l2); 5713fcf5ef2aSThomas Huth gen_set_label(l1); 5714fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5715fcf5ef2aSThomas Huth gen_set_label(l2); 5716efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5717fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5718fcf5ef2aSThomas Huth } 5719efe843d8SDavid Gibson } 5720fcf5ef2aSThomas Huth 5721fcf5ef2aSThomas Huth /* dozo - dozo. */ 5722fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5723fcf5ef2aSThomas Huth { 5724fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5725fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5726fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5727fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5728fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5729fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5730fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5731efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5732efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5733fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5734fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5735fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5736fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5737fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5738fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5739fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5740fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5741fcf5ef2aSThomas Huth tcg_gen_br(l2); 5742fcf5ef2aSThomas Huth gen_set_label(l1); 5743fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5744fcf5ef2aSThomas Huth gen_set_label(l2); 5745fcf5ef2aSThomas Huth tcg_temp_free(t0); 5746fcf5ef2aSThomas Huth tcg_temp_free(t1); 5747fcf5ef2aSThomas Huth tcg_temp_free(t2); 5748efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5749fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5750fcf5ef2aSThomas Huth } 5751efe843d8SDavid Gibson } 5752fcf5ef2aSThomas Huth 5753fcf5ef2aSThomas Huth /* dozi */ 5754fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5755fcf5ef2aSThomas Huth { 5756fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5757fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5758fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5759fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5760fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5761fcf5ef2aSThomas Huth tcg_gen_br(l2); 5762fcf5ef2aSThomas Huth gen_set_label(l1); 5763fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5764fcf5ef2aSThomas Huth gen_set_label(l2); 5765efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5766fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5767fcf5ef2aSThomas Huth } 5768efe843d8SDavid Gibson } 5769fcf5ef2aSThomas Huth 5770fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5771fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5772fcf5ef2aSThomas Huth { 5773fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5774fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5775fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5776fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5777fcf5ef2aSThomas Huth 5778fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5779fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5780fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5781fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5782fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5783fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5784fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5785efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5786fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5787efe843d8SDavid Gibson } 5788fcf5ef2aSThomas Huth tcg_temp_free(t0); 5789fcf5ef2aSThomas Huth } 5790fcf5ef2aSThomas Huth 5791fcf5ef2aSThomas Huth /* maskg - maskg. */ 5792fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5793fcf5ef2aSThomas Huth { 5794fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5795fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5796fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5797fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5798fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5799fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5800fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5801fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5802fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5803fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5804fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5805fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5806fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5807fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5808fcf5ef2aSThomas Huth gen_set_label(l1); 5809fcf5ef2aSThomas Huth tcg_temp_free(t0); 5810fcf5ef2aSThomas Huth tcg_temp_free(t1); 5811fcf5ef2aSThomas Huth tcg_temp_free(t2); 5812fcf5ef2aSThomas Huth tcg_temp_free(t3); 5813efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5814fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5815fcf5ef2aSThomas Huth } 5816efe843d8SDavid Gibson } 5817fcf5ef2aSThomas Huth 5818fcf5ef2aSThomas Huth /* maskir - maskir. */ 5819fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5820fcf5ef2aSThomas Huth { 5821fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5822fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5823fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5824fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5825fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5826fcf5ef2aSThomas Huth tcg_temp_free(t0); 5827fcf5ef2aSThomas Huth tcg_temp_free(t1); 5828efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5829fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5830fcf5ef2aSThomas Huth } 5831efe843d8SDavid Gibson } 5832fcf5ef2aSThomas Huth 5833fcf5ef2aSThomas Huth /* mul - mul. */ 5834fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5835fcf5ef2aSThomas Huth { 5836fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5837fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5838fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5839fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5840fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5841fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5842fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5843fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5844fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5845fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5846fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5847fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5848fcf5ef2aSThomas Huth tcg_temp_free(t2); 5849efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5850fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5851fcf5ef2aSThomas Huth } 5852efe843d8SDavid Gibson } 5853fcf5ef2aSThomas Huth 5854fcf5ef2aSThomas Huth /* mulo - mulo. */ 5855fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5856fcf5ef2aSThomas Huth { 5857fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5858fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5859fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5860fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5861fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5862fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5863fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5864fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5865fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5866fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5867fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5868fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5869fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5870fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5871fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5872fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5873fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5874fcf5ef2aSThomas Huth gen_set_label(l1); 5875fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5876fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5877fcf5ef2aSThomas Huth tcg_temp_free(t2); 5878efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5879fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5880fcf5ef2aSThomas Huth } 5881efe843d8SDavid Gibson } 5882fcf5ef2aSThomas Huth 5883fcf5ef2aSThomas Huth /* nabs - nabs. */ 5884fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5885fcf5ef2aSThomas Huth { 5886fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5887fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5888fe21b785SRichard Henderson 5889fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5890fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5891efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5892fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5893fcf5ef2aSThomas Huth } 5894efe843d8SDavid Gibson } 5895fcf5ef2aSThomas Huth 5896fcf5ef2aSThomas Huth /* nabso - nabso. */ 5897fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5898fcf5ef2aSThomas Huth { 5899fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5900fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5901fe21b785SRichard Henderson 5902fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5903fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5904fcf5ef2aSThomas Huth /* nabs never overflows */ 5905fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5906efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5907fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5908fcf5ef2aSThomas Huth } 5909efe843d8SDavid Gibson } 5910fcf5ef2aSThomas Huth 5911fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5912fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5913fcf5ef2aSThomas Huth { 5914fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5915fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5916fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5917fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5918fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5919fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5920efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5921efe843d8SDavid Gibson ~MASK(mb, me)); 5922fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5923fcf5ef2aSThomas Huth tcg_temp_free(t0); 5924efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5925fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5926fcf5ef2aSThomas Huth } 5927efe843d8SDavid Gibson } 5928fcf5ef2aSThomas Huth 5929fcf5ef2aSThomas Huth /* rrib - rrib. */ 5930fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5931fcf5ef2aSThomas Huth { 5932fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5933fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5934fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5935fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5936fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5937fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5938fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5939fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5940fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5941fcf5ef2aSThomas Huth tcg_temp_free(t0); 5942fcf5ef2aSThomas Huth tcg_temp_free(t1); 5943efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5944fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5945fcf5ef2aSThomas Huth } 5946efe843d8SDavid Gibson } 5947fcf5ef2aSThomas Huth 5948fcf5ef2aSThomas Huth /* sle - sle. */ 5949fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 5950fcf5ef2aSThomas Huth { 5951fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5952fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5953fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5954fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5955fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5956fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5957fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5958fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5959fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5960fcf5ef2aSThomas Huth tcg_temp_free(t0); 5961fcf5ef2aSThomas Huth tcg_temp_free(t1); 5962efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5963fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5964fcf5ef2aSThomas Huth } 5965efe843d8SDavid Gibson } 5966fcf5ef2aSThomas Huth 5967fcf5ef2aSThomas Huth /* sleq - sleq. */ 5968fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 5969fcf5ef2aSThomas Huth { 5970fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5971fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5972fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5973fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5974fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5975fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 5976fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5977fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5978fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5979fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5980fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5981fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5982fcf5ef2aSThomas Huth tcg_temp_free(t0); 5983fcf5ef2aSThomas Huth tcg_temp_free(t1); 5984fcf5ef2aSThomas Huth tcg_temp_free(t2); 5985efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5986fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5987fcf5ef2aSThomas Huth } 5988efe843d8SDavid Gibson } 5989fcf5ef2aSThomas Huth 5990fcf5ef2aSThomas Huth /* sliq - sliq. */ 5991fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 5992fcf5ef2aSThomas Huth { 5993fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5994fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5995fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5996fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5997fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5998fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5999fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6000fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6001fcf5ef2aSThomas Huth tcg_temp_free(t0); 6002fcf5ef2aSThomas Huth tcg_temp_free(t1); 6003efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6004fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6005fcf5ef2aSThomas Huth } 6006efe843d8SDavid Gibson } 6007fcf5ef2aSThomas Huth 6008fcf5ef2aSThomas Huth /* slliq - slliq. */ 6009fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6010fcf5ef2aSThomas Huth { 6011fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6012fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6013fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6014fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6015fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6016fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6017fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6018fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6019fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6020fcf5ef2aSThomas Huth tcg_temp_free(t0); 6021fcf5ef2aSThomas Huth tcg_temp_free(t1); 6022efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6023fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6024fcf5ef2aSThomas Huth } 6025efe843d8SDavid Gibson } 6026fcf5ef2aSThomas Huth 6027fcf5ef2aSThomas Huth /* sllq - sllq. */ 6028fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6029fcf5ef2aSThomas Huth { 6030fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6031fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6032fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6033fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6034fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6035fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6036fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6037fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6038fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6039fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6040fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6041fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6042fcf5ef2aSThomas Huth tcg_gen_br(l2); 6043fcf5ef2aSThomas Huth gen_set_label(l1); 6044fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6045fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6046fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6047fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6048fcf5ef2aSThomas Huth gen_set_label(l2); 6049fcf5ef2aSThomas Huth tcg_temp_free(t0); 6050fcf5ef2aSThomas Huth tcg_temp_free(t1); 6051fcf5ef2aSThomas Huth tcg_temp_free(t2); 6052efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6053fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6054fcf5ef2aSThomas Huth } 6055efe843d8SDavid Gibson } 6056fcf5ef2aSThomas Huth 6057fcf5ef2aSThomas Huth /* slq - slq. */ 6058fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6059fcf5ef2aSThomas Huth { 6060fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6061fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6062fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6063fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6064fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6065fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6066fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6067fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6068fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6069fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6070fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6071fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6072fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6073fcf5ef2aSThomas Huth gen_set_label(l1); 6074fcf5ef2aSThomas Huth tcg_temp_free(t0); 6075fcf5ef2aSThomas Huth tcg_temp_free(t1); 6076efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6077fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6078fcf5ef2aSThomas Huth } 6079efe843d8SDavid Gibson } 6080fcf5ef2aSThomas Huth 6081fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6082fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6083fcf5ef2aSThomas Huth { 6084fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6085fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6086fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6087fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6088fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6089fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6090fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6091fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6092fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6093fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6094fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6095fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6096fcf5ef2aSThomas Huth gen_set_label(l1); 6097fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6098fcf5ef2aSThomas Huth tcg_temp_free(t0); 6099fcf5ef2aSThomas Huth tcg_temp_free(t1); 6100efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6101fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6102fcf5ef2aSThomas Huth } 6103efe843d8SDavid Gibson } 6104fcf5ef2aSThomas Huth 6105fcf5ef2aSThomas Huth /* sraq - sraq. */ 6106fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6107fcf5ef2aSThomas Huth { 6108fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6109fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6110fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6111fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6112fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6113fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6114fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6115fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6116fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6117fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6118fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6119fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6120fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6121fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6122fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6123fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6124fcf5ef2aSThomas Huth gen_set_label(l1); 6125fcf5ef2aSThomas Huth tcg_temp_free(t0); 6126fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6127fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6128fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6129fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6130fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6131fcf5ef2aSThomas Huth gen_set_label(l2); 6132fcf5ef2aSThomas Huth tcg_temp_free(t1); 6133fcf5ef2aSThomas Huth tcg_temp_free(t2); 6134efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6135fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6136fcf5ef2aSThomas Huth } 6137efe843d8SDavid Gibson } 6138fcf5ef2aSThomas Huth 6139fcf5ef2aSThomas Huth /* sre - sre. */ 6140fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6141fcf5ef2aSThomas Huth { 6142fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6143fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6144fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6145fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6146fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6147fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6148fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6149fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6150fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6151fcf5ef2aSThomas Huth tcg_temp_free(t0); 6152fcf5ef2aSThomas Huth tcg_temp_free(t1); 6153efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6154fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6155fcf5ef2aSThomas Huth } 6156efe843d8SDavid Gibson } 6157fcf5ef2aSThomas Huth 6158fcf5ef2aSThomas Huth /* srea - srea. */ 6159fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6160fcf5ef2aSThomas Huth { 6161fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6162fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6163fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6164fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6165fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6166fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6167fcf5ef2aSThomas Huth tcg_temp_free(t0); 6168fcf5ef2aSThomas Huth tcg_temp_free(t1); 6169efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6170fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6171fcf5ef2aSThomas Huth } 6172efe843d8SDavid Gibson } 6173fcf5ef2aSThomas Huth 6174fcf5ef2aSThomas Huth /* sreq */ 6175fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6176fcf5ef2aSThomas Huth { 6177fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6178fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6179fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6180fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6181fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6182fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6183fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6184fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6185fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6186fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6187fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6188fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6189fcf5ef2aSThomas Huth tcg_temp_free(t0); 6190fcf5ef2aSThomas Huth tcg_temp_free(t1); 6191fcf5ef2aSThomas Huth tcg_temp_free(t2); 6192efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6193fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6194fcf5ef2aSThomas Huth } 6195efe843d8SDavid Gibson } 6196fcf5ef2aSThomas Huth 6197fcf5ef2aSThomas Huth /* sriq */ 6198fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6199fcf5ef2aSThomas Huth { 6200fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6201fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6202fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6203fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6204fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6205fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6206fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6207fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6208fcf5ef2aSThomas Huth tcg_temp_free(t0); 6209fcf5ef2aSThomas Huth tcg_temp_free(t1); 6210efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6211fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6212fcf5ef2aSThomas Huth } 6213efe843d8SDavid Gibson } 6214fcf5ef2aSThomas Huth 6215fcf5ef2aSThomas Huth /* srliq */ 6216fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6217fcf5ef2aSThomas Huth { 6218fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6219fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6220fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6221fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6222fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6223fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6224fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6225fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6226fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6227fcf5ef2aSThomas Huth tcg_temp_free(t0); 6228fcf5ef2aSThomas Huth tcg_temp_free(t1); 6229efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6230fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6231fcf5ef2aSThomas Huth } 6232efe843d8SDavid Gibson } 6233fcf5ef2aSThomas Huth 6234fcf5ef2aSThomas Huth /* srlq */ 6235fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6236fcf5ef2aSThomas Huth { 6237fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6238fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6239fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6240fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6241fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6242fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6243fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6244fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6245fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6246fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6247fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6248fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6249fcf5ef2aSThomas Huth tcg_gen_br(l2); 6250fcf5ef2aSThomas Huth gen_set_label(l1); 6251fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6252fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6253fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6254fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6255fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6256fcf5ef2aSThomas Huth gen_set_label(l2); 6257fcf5ef2aSThomas Huth tcg_temp_free(t0); 6258fcf5ef2aSThomas Huth tcg_temp_free(t1); 6259fcf5ef2aSThomas Huth tcg_temp_free(t2); 6260efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6261fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6262fcf5ef2aSThomas Huth } 6263efe843d8SDavid Gibson } 6264fcf5ef2aSThomas Huth 6265fcf5ef2aSThomas Huth /* srq */ 6266fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6267fcf5ef2aSThomas Huth { 6268fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6269fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6270fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6271fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6272fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6273fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6274fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6275fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6276fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6277fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6278fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6279fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6280fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6281fcf5ef2aSThomas Huth gen_set_label(l1); 6282fcf5ef2aSThomas Huth tcg_temp_free(t0); 6283fcf5ef2aSThomas Huth tcg_temp_free(t1); 6284efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6285fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6286fcf5ef2aSThomas Huth } 6287efe843d8SDavid Gibson } 6288fcf5ef2aSThomas Huth 6289fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6290fcf5ef2aSThomas Huth 6291fcf5ef2aSThomas Huth /* dsa */ 6292fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6293fcf5ef2aSThomas Huth { 6294fcf5ef2aSThomas Huth /* XXX: TODO */ 6295fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6296fcf5ef2aSThomas Huth } 6297fcf5ef2aSThomas Huth 6298fcf5ef2aSThomas Huth /* esa */ 6299fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6300fcf5ef2aSThomas Huth { 6301fcf5ef2aSThomas Huth /* XXX: TODO */ 6302fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6303fcf5ef2aSThomas Huth } 6304fcf5ef2aSThomas Huth 6305fcf5ef2aSThomas Huth /* mfrom */ 6306fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6307fcf5ef2aSThomas Huth { 6308fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6309fcf5ef2aSThomas Huth GEN_PRIV; 6310fcf5ef2aSThomas Huth #else 6311fcf5ef2aSThomas Huth CHK_SV; 6312fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6313fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6314fcf5ef2aSThomas Huth } 6315fcf5ef2aSThomas Huth 6316fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6317fcf5ef2aSThomas Huth 6318fcf5ef2aSThomas Huth /* tlbld */ 6319fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6320fcf5ef2aSThomas Huth { 6321fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6322fcf5ef2aSThomas Huth GEN_PRIV; 6323fcf5ef2aSThomas Huth #else 6324fcf5ef2aSThomas Huth CHK_SV; 6325fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6326fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6327fcf5ef2aSThomas Huth } 6328fcf5ef2aSThomas Huth 6329fcf5ef2aSThomas Huth /* tlbli */ 6330fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6331fcf5ef2aSThomas Huth { 6332fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6333fcf5ef2aSThomas Huth GEN_PRIV; 6334fcf5ef2aSThomas Huth #else 6335fcf5ef2aSThomas Huth CHK_SV; 6336fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6337fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6338fcf5ef2aSThomas Huth } 6339fcf5ef2aSThomas Huth 6340fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6341fcf5ef2aSThomas Huth 6342fcf5ef2aSThomas Huth /* clf */ 6343fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6344fcf5ef2aSThomas Huth { 6345fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6346fcf5ef2aSThomas Huth } 6347fcf5ef2aSThomas Huth 6348fcf5ef2aSThomas Huth /* cli */ 6349fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6350fcf5ef2aSThomas Huth { 6351fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6352fcf5ef2aSThomas Huth GEN_PRIV; 6353fcf5ef2aSThomas Huth #else 6354fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6355fcf5ef2aSThomas Huth CHK_SV; 6356fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6357fcf5ef2aSThomas Huth } 6358fcf5ef2aSThomas Huth 6359fcf5ef2aSThomas Huth /* dclst */ 6360fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6361fcf5ef2aSThomas Huth { 6362fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6363fcf5ef2aSThomas Huth } 6364fcf5ef2aSThomas Huth 6365fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6366fcf5ef2aSThomas Huth { 6367fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6368fcf5ef2aSThomas Huth GEN_PRIV; 6369fcf5ef2aSThomas Huth #else 6370fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6371fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6372fcf5ef2aSThomas Huth TCGv t0; 6373fcf5ef2aSThomas Huth 6374fcf5ef2aSThomas Huth CHK_SV; 6375fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6376fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6377e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6378fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6379fcf5ef2aSThomas Huth tcg_temp_free(t0); 6380efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6381fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6382efe843d8SDavid Gibson } 6383fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6384fcf5ef2aSThomas Huth } 6385fcf5ef2aSThomas Huth 6386fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6387fcf5ef2aSThomas Huth { 6388fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6389fcf5ef2aSThomas Huth GEN_PRIV; 6390fcf5ef2aSThomas Huth #else 6391fcf5ef2aSThomas Huth TCGv t0; 6392fcf5ef2aSThomas Huth 6393fcf5ef2aSThomas Huth CHK_SV; 6394fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6395fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6396fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6397fcf5ef2aSThomas Huth tcg_temp_free(t0); 6398fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6399fcf5ef2aSThomas Huth } 6400fcf5ef2aSThomas Huth 6401fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6402fcf5ef2aSThomas Huth { 6403fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6404fcf5ef2aSThomas Huth GEN_PRIV; 6405fcf5ef2aSThomas Huth #else 6406fcf5ef2aSThomas Huth CHK_SV; 6407fcf5ef2aSThomas Huth 6408fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 640959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6410fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6411fcf5ef2aSThomas Huth } 6412fcf5ef2aSThomas Huth 6413fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6414fcf5ef2aSThomas Huth 6415fcf5ef2aSThomas Huth /* BookE specific instructions */ 6416fcf5ef2aSThomas Huth 6417fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6418fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6419fcf5ef2aSThomas Huth { 6420fcf5ef2aSThomas Huth /* XXX: TODO */ 6421fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6422fcf5ef2aSThomas Huth } 6423fcf5ef2aSThomas Huth 6424fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6425fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6426fcf5ef2aSThomas Huth { 6427fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6428fcf5ef2aSThomas Huth GEN_PRIV; 6429fcf5ef2aSThomas Huth #else 6430fcf5ef2aSThomas Huth TCGv t0; 6431fcf5ef2aSThomas Huth 6432fcf5ef2aSThomas Huth CHK_SV; 6433fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6434fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6435fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6436fcf5ef2aSThomas Huth tcg_temp_free(t0); 6437fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6438fcf5ef2aSThomas Huth } 6439fcf5ef2aSThomas Huth 6440fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6441fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6442fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6443fcf5ef2aSThomas Huth { 6444fcf5ef2aSThomas Huth TCGv t0, t1; 6445fcf5ef2aSThomas Huth 6446fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6447fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6448fcf5ef2aSThomas Huth 6449fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6450fcf5ef2aSThomas Huth case 0x05: 6451fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6452fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6453fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6454fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6455fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6456fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6457fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6458fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6459fcf5ef2aSThomas Huth break; 6460fcf5ef2aSThomas Huth case 0x04: 6461fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6462fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6463fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6464fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6465fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6466fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6467fcf5ef2aSThomas Huth break; 6468fcf5ef2aSThomas Huth case 0x01: 6469fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6470fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6471fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6472fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6473fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6474fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6475fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6476fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6477fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6478fcf5ef2aSThomas Huth break; 6479fcf5ef2aSThomas Huth case 0x00: 6480fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6481fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6482fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6483fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6484fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6485fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6486fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6487fcf5ef2aSThomas Huth break; 6488fcf5ef2aSThomas Huth case 0x0D: 6489fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6490fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 6491fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6492fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6493fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6494fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6495fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6496fcf5ef2aSThomas Huth break; 6497fcf5ef2aSThomas Huth case 0x0C: 6498fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6499fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6500fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6501fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6502fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6503fcf5ef2aSThomas Huth break; 6504fcf5ef2aSThomas Huth } 6505fcf5ef2aSThomas Huth if (opc2 & 0x04) { 6506fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6507fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 6508fcf5ef2aSThomas Huth if (opc2 & 0x02) { 6509fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 6510fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6511fcf5ef2aSThomas Huth } else { 6512fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 6513fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6514fcf5ef2aSThomas Huth } 6515fcf5ef2aSThomas Huth 6516fcf5ef2aSThomas Huth if (opc3 & 0x12) { 6517fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 6518fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6519fcf5ef2aSThomas Huth 6520fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6521fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6522fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6523fcf5ef2aSThomas Huth } 6524fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6525fcf5ef2aSThomas Huth /* Signed */ 6526fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6527fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6528fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6529fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6530fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6531fcf5ef2aSThomas Huth /* Saturate */ 6532fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6533fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6534fcf5ef2aSThomas Huth } 6535fcf5ef2aSThomas Huth } else { 6536fcf5ef2aSThomas Huth /* Unsigned */ 6537fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6538fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6539fcf5ef2aSThomas Huth /* Saturate */ 6540fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6541fcf5ef2aSThomas Huth } 6542fcf5ef2aSThomas Huth } 6543fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6544fcf5ef2aSThomas Huth /* Check overflow */ 6545fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6546fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6547fcf5ef2aSThomas Huth } 6548fcf5ef2aSThomas Huth gen_set_label(l1); 6549fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6550fcf5ef2aSThomas Huth } 6551fcf5ef2aSThomas Huth } else { 6552fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6553fcf5ef2aSThomas Huth } 6554fcf5ef2aSThomas Huth tcg_temp_free(t0); 6555fcf5ef2aSThomas Huth tcg_temp_free(t1); 6556fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6557fcf5ef2aSThomas Huth /* Update Rc0 */ 6558fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6559fcf5ef2aSThomas Huth } 6560fcf5ef2aSThomas Huth } 6561fcf5ef2aSThomas Huth 6562fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6563fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6564fcf5ef2aSThomas Huth { \ 6565fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6566fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6567fcf5ef2aSThomas Huth } 6568fcf5ef2aSThomas Huth 6569fcf5ef2aSThomas Huth /* macchw - macchw. */ 6570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6571fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6573fcf5ef2aSThomas Huth /* macchws - macchws. */ 6574fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6575fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6576fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6577fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6578fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6579fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6580fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6581fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6582fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6583fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6584fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6585fcf5ef2aSThomas Huth /* machhw - machhw. */ 6586fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6587fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6588fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6589fcf5ef2aSThomas Huth /* machhws - machhws. */ 6590fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6591fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6592fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6593fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6594fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6595fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6596fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6597fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6598fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6599fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6600fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6601fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6602fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6603fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6604fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6605fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6606fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6607fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6608fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6609fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6610fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6611fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6612fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6613fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6614fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6615fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6616fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6617fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6618fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6619fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6620fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6621fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6622fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6623fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6624fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6625fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6626fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6627fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6628fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6629fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6630fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6631fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6632fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6633fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6634fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6635fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6636fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6637fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6638fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6639fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6640fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6641fcf5ef2aSThomas Huth 6642fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6643fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6644fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6645fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6646fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6647fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6648fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6649fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6650fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6651fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6652fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6653fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6654fcf5ef2aSThomas Huth 6655fcf5ef2aSThomas Huth /* mfdcr */ 6656fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6657fcf5ef2aSThomas Huth { 6658fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6659fcf5ef2aSThomas Huth GEN_PRIV; 6660fcf5ef2aSThomas Huth #else 6661fcf5ef2aSThomas Huth TCGv dcrn; 6662fcf5ef2aSThomas Huth 6663fcf5ef2aSThomas Huth CHK_SV; 6664fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6665fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6666fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6667fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6668fcf5ef2aSThomas Huth } 6669fcf5ef2aSThomas Huth 6670fcf5ef2aSThomas Huth /* mtdcr */ 6671fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6672fcf5ef2aSThomas Huth { 6673fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6674fcf5ef2aSThomas Huth GEN_PRIV; 6675fcf5ef2aSThomas Huth #else 6676fcf5ef2aSThomas Huth TCGv dcrn; 6677fcf5ef2aSThomas Huth 6678fcf5ef2aSThomas Huth CHK_SV; 6679fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6680fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6681fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6682fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6683fcf5ef2aSThomas Huth } 6684fcf5ef2aSThomas Huth 6685fcf5ef2aSThomas Huth /* mfdcrx */ 6686fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6687fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6688fcf5ef2aSThomas Huth { 6689fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6690fcf5ef2aSThomas Huth GEN_PRIV; 6691fcf5ef2aSThomas Huth #else 6692fcf5ef2aSThomas Huth CHK_SV; 6693fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6694fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6695fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6696fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6697fcf5ef2aSThomas Huth } 6698fcf5ef2aSThomas Huth 6699fcf5ef2aSThomas Huth /* mtdcrx */ 6700fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6701fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6702fcf5ef2aSThomas Huth { 6703fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6704fcf5ef2aSThomas Huth GEN_PRIV; 6705fcf5ef2aSThomas Huth #else 6706fcf5ef2aSThomas Huth CHK_SV; 6707fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6708fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6709fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6710fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6711fcf5ef2aSThomas Huth } 6712fcf5ef2aSThomas Huth 6713fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6714fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6715fcf5ef2aSThomas Huth { 6716fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6717fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6718fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6719fcf5ef2aSThomas Huth } 6720fcf5ef2aSThomas Huth 6721fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6722fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6723fcf5ef2aSThomas Huth { 6724fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6725fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6726fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6727fcf5ef2aSThomas Huth } 6728fcf5ef2aSThomas Huth 6729fcf5ef2aSThomas Huth /* dccci */ 6730fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6731fcf5ef2aSThomas Huth { 6732fcf5ef2aSThomas Huth CHK_SV; 6733fcf5ef2aSThomas Huth /* interpreted as no-op */ 6734fcf5ef2aSThomas Huth } 6735fcf5ef2aSThomas Huth 6736fcf5ef2aSThomas Huth /* dcread */ 6737fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6738fcf5ef2aSThomas Huth { 6739fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6740fcf5ef2aSThomas Huth GEN_PRIV; 6741fcf5ef2aSThomas Huth #else 6742fcf5ef2aSThomas Huth TCGv EA, val; 6743fcf5ef2aSThomas Huth 6744fcf5ef2aSThomas Huth CHK_SV; 6745fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6746fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6747fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6748fcf5ef2aSThomas Huth val = tcg_temp_new(); 6749fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6750fcf5ef2aSThomas Huth tcg_temp_free(val); 6751fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6752fcf5ef2aSThomas Huth tcg_temp_free(EA); 6753fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6754fcf5ef2aSThomas Huth } 6755fcf5ef2aSThomas Huth 6756fcf5ef2aSThomas Huth /* icbt */ 6757fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6758fcf5ef2aSThomas Huth { 6759efe843d8SDavid Gibson /* 6760efe843d8SDavid Gibson * interpreted as no-op 6761efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6762efe843d8SDavid Gibson * does not generate any exception 6763fcf5ef2aSThomas Huth */ 6764fcf5ef2aSThomas Huth } 6765fcf5ef2aSThomas Huth 6766fcf5ef2aSThomas Huth /* iccci */ 6767fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6768fcf5ef2aSThomas Huth { 6769fcf5ef2aSThomas Huth CHK_SV; 6770fcf5ef2aSThomas Huth /* interpreted as no-op */ 6771fcf5ef2aSThomas Huth } 6772fcf5ef2aSThomas Huth 6773fcf5ef2aSThomas Huth /* icread */ 6774fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6775fcf5ef2aSThomas Huth { 6776fcf5ef2aSThomas Huth CHK_SV; 6777fcf5ef2aSThomas Huth /* interpreted as no-op */ 6778fcf5ef2aSThomas Huth } 6779fcf5ef2aSThomas Huth 6780fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6781fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6782fcf5ef2aSThomas Huth { 6783fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6784fcf5ef2aSThomas Huth GEN_PRIV; 6785fcf5ef2aSThomas Huth #else 6786fcf5ef2aSThomas Huth CHK_SV; 6787fcf5ef2aSThomas Huth /* Restore CPU state */ 6788fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 678959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6790fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6791fcf5ef2aSThomas Huth } 6792fcf5ef2aSThomas Huth 6793fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6794fcf5ef2aSThomas Huth { 6795fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6796fcf5ef2aSThomas Huth GEN_PRIV; 6797fcf5ef2aSThomas Huth #else 6798fcf5ef2aSThomas Huth CHK_SV; 6799fcf5ef2aSThomas Huth /* Restore CPU state */ 6800fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 680159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6802fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6803fcf5ef2aSThomas Huth } 6804fcf5ef2aSThomas Huth 6805fcf5ef2aSThomas Huth /* BookE specific */ 6806fcf5ef2aSThomas Huth 6807fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6808fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6809fcf5ef2aSThomas Huth { 6810fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6811fcf5ef2aSThomas Huth GEN_PRIV; 6812fcf5ef2aSThomas Huth #else 6813fcf5ef2aSThomas Huth CHK_SV; 6814fcf5ef2aSThomas Huth /* Restore CPU state */ 6815fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 681659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6817fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6818fcf5ef2aSThomas Huth } 6819fcf5ef2aSThomas Huth 6820fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6821fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6822fcf5ef2aSThomas Huth { 6823fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6824fcf5ef2aSThomas Huth GEN_PRIV; 6825fcf5ef2aSThomas Huth #else 6826fcf5ef2aSThomas Huth CHK_SV; 6827fcf5ef2aSThomas Huth /* Restore CPU state */ 6828fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 682959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6830fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6831fcf5ef2aSThomas Huth } 6832fcf5ef2aSThomas Huth 6833fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6834fcf5ef2aSThomas Huth 6835fcf5ef2aSThomas Huth /* tlbre */ 6836fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6837fcf5ef2aSThomas Huth { 6838fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6839fcf5ef2aSThomas Huth GEN_PRIV; 6840fcf5ef2aSThomas Huth #else 6841fcf5ef2aSThomas Huth CHK_SV; 6842fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6843fcf5ef2aSThomas Huth case 0: 6844fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6845fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6846fcf5ef2aSThomas Huth break; 6847fcf5ef2aSThomas Huth case 1: 6848fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6849fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6850fcf5ef2aSThomas Huth break; 6851fcf5ef2aSThomas Huth default: 6852fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6853fcf5ef2aSThomas Huth break; 6854fcf5ef2aSThomas Huth } 6855fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6856fcf5ef2aSThomas Huth } 6857fcf5ef2aSThomas Huth 6858fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6859fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6860fcf5ef2aSThomas Huth { 6861fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6862fcf5ef2aSThomas Huth GEN_PRIV; 6863fcf5ef2aSThomas Huth #else 6864fcf5ef2aSThomas Huth TCGv t0; 6865fcf5ef2aSThomas Huth 6866fcf5ef2aSThomas Huth CHK_SV; 6867fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6868fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6869fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6870fcf5ef2aSThomas Huth tcg_temp_free(t0); 6871fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6872fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6873fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6874fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6875fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6876fcf5ef2aSThomas Huth gen_set_label(l1); 6877fcf5ef2aSThomas Huth } 6878fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6879fcf5ef2aSThomas Huth } 6880fcf5ef2aSThomas Huth 6881fcf5ef2aSThomas Huth /* tlbwe */ 6882fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6883fcf5ef2aSThomas Huth { 6884fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6885fcf5ef2aSThomas Huth GEN_PRIV; 6886fcf5ef2aSThomas Huth #else 6887fcf5ef2aSThomas Huth CHK_SV; 6888fcf5ef2aSThomas Huth 6889fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6890fcf5ef2aSThomas Huth case 0: 6891fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6892fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6893fcf5ef2aSThomas Huth break; 6894fcf5ef2aSThomas Huth case 1: 6895fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6896fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6897fcf5ef2aSThomas Huth break; 6898fcf5ef2aSThomas Huth default: 6899fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6900fcf5ef2aSThomas Huth break; 6901fcf5ef2aSThomas Huth } 6902fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6903fcf5ef2aSThomas Huth } 6904fcf5ef2aSThomas Huth 6905fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6906fcf5ef2aSThomas Huth 6907fcf5ef2aSThomas Huth /* tlbre */ 6908fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6909fcf5ef2aSThomas Huth { 6910fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6911fcf5ef2aSThomas Huth GEN_PRIV; 6912fcf5ef2aSThomas Huth #else 6913fcf5ef2aSThomas Huth CHK_SV; 6914fcf5ef2aSThomas Huth 6915fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6916fcf5ef2aSThomas Huth case 0: 6917fcf5ef2aSThomas Huth case 1: 6918fcf5ef2aSThomas Huth case 2: 6919fcf5ef2aSThomas Huth { 6920fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6921fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6922fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6923fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6924fcf5ef2aSThomas Huth } 6925fcf5ef2aSThomas Huth break; 6926fcf5ef2aSThomas Huth default: 6927fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6928fcf5ef2aSThomas Huth break; 6929fcf5ef2aSThomas Huth } 6930fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6931fcf5ef2aSThomas Huth } 6932fcf5ef2aSThomas Huth 6933fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6934fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6935fcf5ef2aSThomas Huth { 6936fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6937fcf5ef2aSThomas Huth GEN_PRIV; 6938fcf5ef2aSThomas Huth #else 6939fcf5ef2aSThomas Huth TCGv t0; 6940fcf5ef2aSThomas Huth 6941fcf5ef2aSThomas Huth CHK_SV; 6942fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6943fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6944fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6945fcf5ef2aSThomas Huth tcg_temp_free(t0); 6946fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6947fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6948fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6949fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6950fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6951fcf5ef2aSThomas Huth gen_set_label(l1); 6952fcf5ef2aSThomas Huth } 6953fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6954fcf5ef2aSThomas Huth } 6955fcf5ef2aSThomas Huth 6956fcf5ef2aSThomas Huth /* tlbwe */ 6957fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6958fcf5ef2aSThomas Huth { 6959fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6960fcf5ef2aSThomas Huth GEN_PRIV; 6961fcf5ef2aSThomas Huth #else 6962fcf5ef2aSThomas Huth CHK_SV; 6963fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6964fcf5ef2aSThomas Huth case 0: 6965fcf5ef2aSThomas Huth case 1: 6966fcf5ef2aSThomas Huth case 2: 6967fcf5ef2aSThomas Huth { 6968fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6969fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6970fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6971fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6972fcf5ef2aSThomas Huth } 6973fcf5ef2aSThomas Huth break; 6974fcf5ef2aSThomas Huth default: 6975fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6976fcf5ef2aSThomas Huth break; 6977fcf5ef2aSThomas Huth } 6978fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6979fcf5ef2aSThomas Huth } 6980fcf5ef2aSThomas Huth 6981fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6982fcf5ef2aSThomas Huth 6983fcf5ef2aSThomas Huth /* tlbre */ 6984fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6985fcf5ef2aSThomas Huth { 6986fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6987fcf5ef2aSThomas Huth GEN_PRIV; 6988fcf5ef2aSThomas Huth #else 6989fcf5ef2aSThomas Huth CHK_SV; 6990fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6991fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6992fcf5ef2aSThomas Huth } 6993fcf5ef2aSThomas Huth 6994fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6995fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6996fcf5ef2aSThomas Huth { 6997fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6998fcf5ef2aSThomas Huth GEN_PRIV; 6999fcf5ef2aSThomas Huth #else 7000fcf5ef2aSThomas Huth TCGv t0; 7001fcf5ef2aSThomas Huth 7002fcf5ef2aSThomas Huth CHK_SV; 7003fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7004fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7005fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7006fcf5ef2aSThomas Huth } else { 7007fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7008fcf5ef2aSThomas Huth } 7009fcf5ef2aSThomas Huth 7010fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7011fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7012fcf5ef2aSThomas Huth tcg_temp_free(t0); 7013fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7014fcf5ef2aSThomas Huth } 7015fcf5ef2aSThomas Huth 7016fcf5ef2aSThomas Huth /* tlbwe */ 7017fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7018fcf5ef2aSThomas Huth { 7019fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7020fcf5ef2aSThomas Huth GEN_PRIV; 7021fcf5ef2aSThomas Huth #else 7022fcf5ef2aSThomas Huth CHK_SV; 7023fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7024fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7025fcf5ef2aSThomas Huth } 7026fcf5ef2aSThomas Huth 7027fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7028fcf5ef2aSThomas Huth { 7029fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7030fcf5ef2aSThomas Huth GEN_PRIV; 7031fcf5ef2aSThomas Huth #else 7032fcf5ef2aSThomas Huth TCGv t0; 7033fcf5ef2aSThomas Huth 7034fcf5ef2aSThomas Huth CHK_SV; 7035fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7036fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7037fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7038fcf5ef2aSThomas Huth tcg_temp_free(t0); 7039fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7040fcf5ef2aSThomas Huth } 7041fcf5ef2aSThomas Huth 7042fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7043fcf5ef2aSThomas Huth { 7044fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7045fcf5ef2aSThomas Huth GEN_PRIV; 7046fcf5ef2aSThomas Huth #else 7047fcf5ef2aSThomas Huth TCGv t0; 7048fcf5ef2aSThomas Huth 7049fcf5ef2aSThomas Huth CHK_SV; 7050fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7051fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7052fcf5ef2aSThomas Huth 7053fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7054fcf5ef2aSThomas Huth case 0: 7055fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7056fcf5ef2aSThomas Huth break; 7057fcf5ef2aSThomas Huth case 1: 7058fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7059fcf5ef2aSThomas Huth break; 7060fcf5ef2aSThomas Huth case 3: 7061fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7062fcf5ef2aSThomas Huth break; 7063fcf5ef2aSThomas Huth default: 7064fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7065fcf5ef2aSThomas Huth break; 7066fcf5ef2aSThomas Huth } 7067fcf5ef2aSThomas Huth 7068fcf5ef2aSThomas Huth tcg_temp_free(t0); 7069fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7070fcf5ef2aSThomas Huth } 7071fcf5ef2aSThomas Huth 7072fcf5ef2aSThomas Huth 7073fcf5ef2aSThomas Huth /* wrtee */ 7074fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7075fcf5ef2aSThomas Huth { 7076fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7077fcf5ef2aSThomas Huth GEN_PRIV; 7078fcf5ef2aSThomas Huth #else 7079fcf5ef2aSThomas Huth TCGv t0; 7080fcf5ef2aSThomas Huth 7081fcf5ef2aSThomas Huth CHK_SV; 7082fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7083fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7084fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7085fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7086fcf5ef2aSThomas Huth tcg_temp_free(t0); 7087efe843d8SDavid Gibson /* 7088efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7089efe843d8SDavid Gibson * just set msr_ee to 1 7090fcf5ef2aSThomas Huth */ 7091d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7092fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7093fcf5ef2aSThomas Huth } 7094fcf5ef2aSThomas Huth 7095fcf5ef2aSThomas Huth /* wrteei */ 7096fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7097fcf5ef2aSThomas Huth { 7098fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7099fcf5ef2aSThomas Huth GEN_PRIV; 7100fcf5ef2aSThomas Huth #else 7101fcf5ef2aSThomas Huth CHK_SV; 7102fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7103fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7104fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7105d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7106fcf5ef2aSThomas Huth } else { 7107fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7108fcf5ef2aSThomas Huth } 7109fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7110fcf5ef2aSThomas Huth } 7111fcf5ef2aSThomas Huth 7112fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7113fcf5ef2aSThomas Huth 7114fcf5ef2aSThomas Huth /* dlmzb */ 7115fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7116fcf5ef2aSThomas Huth { 7117fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7118fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7119fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7120fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7121fcf5ef2aSThomas Huth } 7122fcf5ef2aSThomas Huth 7123fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7124fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7125fcf5ef2aSThomas Huth { 7126fcf5ef2aSThomas Huth /* interpreted as no-op */ 7127fcf5ef2aSThomas Huth } 7128fcf5ef2aSThomas Huth 7129fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7130fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7131fcf5ef2aSThomas Huth { 713227a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 713327a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 713427a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 713527a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 713627a3ea7eSBALATON Zoltan } 713727a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7138fcf5ef2aSThomas Huth } 7139fcf5ef2aSThomas Huth 7140fcf5ef2aSThomas Huth /* icbt */ 7141fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7142fcf5ef2aSThomas Huth { 7143efe843d8SDavid Gibson /* 7144efe843d8SDavid Gibson * interpreted as no-op 7145efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7146efe843d8SDavid Gibson * does not generate any exception 7147fcf5ef2aSThomas Huth */ 7148fcf5ef2aSThomas Huth } 7149fcf5ef2aSThomas Huth 7150fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7151fcf5ef2aSThomas Huth 7152fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7153fcf5ef2aSThomas Huth { 7154fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7155fcf5ef2aSThomas Huth GEN_PRIV; 7156fcf5ef2aSThomas Huth #else 7157ebca5e6dSCédric Le Goater CHK_HV; 7158d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 71597af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71607af1e7b0SCédric Le Goater } else { 7161fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71627af1e7b0SCédric Le Goater } 7163fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7164fcf5ef2aSThomas Huth } 7165fcf5ef2aSThomas Huth 7166fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7167fcf5ef2aSThomas Huth { 7168fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7169fcf5ef2aSThomas Huth GEN_PRIV; 7170fcf5ef2aSThomas Huth #else 7171ebca5e6dSCédric Le Goater CHK_HV; 7172d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 71737af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 71747af1e7b0SCédric Le Goater } else { 7175fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 71767af1e7b0SCédric Le Goater } 7177fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7178fcf5ef2aSThomas Huth } 7179fcf5ef2aSThomas Huth 71805ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 71815ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 71825ba7ba1dSCédric Le Goater { 71835ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 71845ba7ba1dSCédric Le Goater GEN_PRIV; 71855ba7ba1dSCédric Le Goater #else 71865ba7ba1dSCédric Le Goater CHK_SV; 71875ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71885ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 71895ba7ba1dSCédric Le Goater } 71905ba7ba1dSCédric Le Goater 71915ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 71925ba7ba1dSCédric Le Goater { 71935ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 71945ba7ba1dSCédric Le Goater GEN_PRIV; 71955ba7ba1dSCédric Le Goater #else 71965ba7ba1dSCédric Le Goater CHK_SV; 71975ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71985ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 71995ba7ba1dSCédric Le Goater } 72005ba7ba1dSCédric Le Goater #endif 72015ba7ba1dSCédric Le Goater 72027af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 72037af1e7b0SCédric Le Goater { 72047af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 72057af1e7b0SCédric Le Goater GEN_PRIV; 72067af1e7b0SCédric Le Goater #else 72077af1e7b0SCédric Le Goater CHK_HV; 72087af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 72097af1e7b0SCédric Le Goater /* interpreted as no-op */ 72107af1e7b0SCédric Le Goater } 7211fcf5ef2aSThomas Huth 7212fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7213fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7214fcf5ef2aSThomas Huth { 7215fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7216fcf5ef2aSThomas Huth 7217fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7218fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7219fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7220fcf5ef2aSThomas Huth } 7221fcf5ef2aSThomas Huth 7222fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7223fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7224fcf5ef2aSThomas Huth { 7225fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7226fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7227fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7228fcf5ef2aSThomas Huth 7229fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7230fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7231fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7232fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7233fcf5ef2aSThomas Huth } else { 7234fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7235fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7236fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7237fcf5ef2aSThomas Huth } 7238fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7239fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7240fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7241fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7242fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7243fcf5ef2aSThomas Huth } 7244fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7245fcf5ef2aSThomas Huth 7246fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7247fcf5ef2aSThomas Huth { 7248fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7249fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7250fcf5ef2aSThomas Huth return; 7251fcf5ef2aSThomas Huth } 7252fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7253fcf5ef2aSThomas Huth } 7254fcf5ef2aSThomas Huth 7255fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7256fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7257fcf5ef2aSThomas Huth { \ 7258fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7259fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7260fcf5ef2aSThomas Huth return; \ 7261fcf5ef2aSThomas Huth } \ 7262efe843d8SDavid Gibson /* \ 7263efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7264fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7265fcf5ef2aSThomas Huth * \ 7266fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7267fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7268fcf5ef2aSThomas Huth */ \ 7269fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7270fcf5ef2aSThomas Huth } 7271fcf5ef2aSThomas Huth 7272fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7273fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7274fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7275fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7276fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7277fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7278fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7279efe843d8SDavid Gibson 7280b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7281b8b4576eSSuraj Jitindar Singh { 7282efe843d8SDavid Gibson /* Do Nothing */ 7283b8b4576eSSuraj Jitindar Singh } 7284fcf5ef2aSThomas Huth 728580b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 728680b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 728780b8c1eeSNikunj A Dadhania { \ 7288efe843d8SDavid Gibson /* \ 7289efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7290efe843d8SDavid Gibson * implementation of the copy paste facility \ 729180b8c1eeSNikunj A Dadhania */ \ 729280b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 729380b8c1eeSNikunj A Dadhania } 729480b8c1eeSNikunj A Dadhania 729580b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 729680b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 729780b8c1eeSNikunj A Dadhania 7298fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7299fcf5ef2aSThomas Huth { 7300fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7301fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7302fcf5ef2aSThomas Huth return; 7303fcf5ef2aSThomas Huth } 7304efe843d8SDavid Gibson /* 7305efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7306efe843d8SDavid Gibson * simple: 7307fcf5ef2aSThomas Huth * 7308fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7309fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7310fcf5ef2aSThomas Huth */ 7311fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7312fcf5ef2aSThomas Huth } 7313fcf5ef2aSThomas Huth 7314fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7315fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7316fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7317fcf5ef2aSThomas Huth { \ 7318fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7319fcf5ef2aSThomas Huth } 7320fcf5ef2aSThomas Huth 7321fcf5ef2aSThomas Huth #else 7322fcf5ef2aSThomas Huth 7323fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7324fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7325fcf5ef2aSThomas Huth { \ 7326fcf5ef2aSThomas Huth CHK_SV; \ 7327fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7328fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7329fcf5ef2aSThomas Huth return; \ 7330fcf5ef2aSThomas Huth } \ 7331efe843d8SDavid Gibson /* \ 7332efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7333fcf5ef2aSThomas Huth * simple: \ 7334fcf5ef2aSThomas Huth * \ 7335fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7336fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7337fcf5ef2aSThomas Huth */ \ 7338fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7339fcf5ef2aSThomas Huth } 7340fcf5ef2aSThomas Huth 7341fcf5ef2aSThomas Huth #endif 7342fcf5ef2aSThomas Huth 7343fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7344fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7345fcf5ef2aSThomas Huth 73461a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 73471a404c91SMark Cave-Ayland { 7348e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 73491a404c91SMark Cave-Ayland } 73501a404c91SMark Cave-Ayland 73511a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 73521a404c91SMark Cave-Ayland { 7353e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 73541a404c91SMark Cave-Ayland } 73551a404c91SMark Cave-Ayland 7356c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7357c4a18dbfSMark Cave-Ayland { 735837da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7359c4a18dbfSMark Cave-Ayland } 7360c4a18dbfSMark Cave-Ayland 7361c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7362c4a18dbfSMark Cave-Ayland { 736337da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7364c4a18dbfSMark Cave-Ayland } 7365c4a18dbfSMark Cave-Ayland 7366c9826ae9SRichard Henderson /* 7367f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 7368f2aabda8SRichard Henderson */ 7369d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 7370d39b2cc7SLuis Pires { 7371d39b2cc7SLuis Pires return x * 2; 7372d39b2cc7SLuis Pires } 7373d39b2cc7SLuis Pires 7374f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 7375f2aabda8SRichard Henderson { 7376f2aabda8SRichard Henderson return x * 4; 7377f2aabda8SRichard Henderson } 7378f2aabda8SRichard Henderson 7379e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 7380e10271e1SMatheus Ferst { 7381e10271e1SMatheus Ferst return x * 16; 7382e10271e1SMatheus Ferst } 7383e10271e1SMatheus Ferst 7384f2aabda8SRichard Henderson /* 7385c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 7386c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 7387c9826ae9SRichard Henderson * proper variable. 7388c9826ae9SRichard Henderson */ 7389c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 7390c9826ae9SRichard Henderson do { \ 7391c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 7392c9826ae9SRichard Henderson return false; \ 7393c9826ae9SRichard Henderson } \ 7394c9826ae9SRichard Henderson } while (0) 7395c9826ae9SRichard Henderson 7396c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 7397c9826ae9SRichard Henderson do { \ 7398c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 7399c9826ae9SRichard Henderson return false; \ 7400c9826ae9SRichard Henderson } \ 7401c9826ae9SRichard Henderson } while (0) 7402c9826ae9SRichard Henderson 7403c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 7404c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 7405c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 7406c9826ae9SRichard Henderson #else 7407c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 7408c9826ae9SRichard Henderson #endif 7409c9826ae9SRichard Henderson 7410e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 7411e2205a46SBruno Larsen do { \ 7412e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 7413e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 7414e2205a46SBruno Larsen return true; \ 7415e2205a46SBruno Larsen } \ 7416e2205a46SBruno Larsen } while (0) 7417e2205a46SBruno Larsen 74188226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 74198226cb2dSBruno Larsen (billionai) do { \ 74208226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 74218226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 74228226cb2dSBruno Larsen (billionai) return true; \ 74238226cb2dSBruno Larsen (billionai) } \ 74248226cb2dSBruno Larsen (billionai) } while (0) 74258226cb2dSBruno Larsen (billionai) 742686057426SFernando Valle #define REQUIRE_FPU(ctx) \ 742786057426SFernando Valle do { \ 742886057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 742986057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 743086057426SFernando Valle return true; \ 743186057426SFernando Valle } \ 743286057426SFernando Valle } while (0) 743386057426SFernando Valle 7434f2aabda8SRichard Henderson /* 7435f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 7436f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 7437f2aabda8SRichard Henderson */ 7438f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 7439f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7440f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 7441f2aabda8SRichard Henderson 7442f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 7443f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7444f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 7445f2aabda8SRichard Henderson 7446f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 7447f2aabda8SRichard Henderson 7448f2aabda8SRichard Henderson 744999082815SRichard Henderson #include "decode-insn32.c.inc" 745099082815SRichard Henderson #include "decode-insn64.c.inc" 7451565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 7452565cb109SGustavo Romero 7453725b2d4dSFernando Eckhardt Valle /* 7454725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 7455725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 7456725b2d4dSFernando Eckhardt Valle */ 7457725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 7458725b2d4dSFernando Eckhardt Valle { 7459725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 7460725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 7461725b2d4dSFernando Eckhardt Valle d->si = a->si; 7462725b2d4dSFernando Eckhardt Valle if (a->r) { 7463725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 7464725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 7465725b2d4dSFernando Eckhardt Valle return false; 7466725b2d4dSFernando Eckhardt Valle } 7467725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 7468725b2d4dSFernando Eckhardt Valle } 7469725b2d4dSFernando Eckhardt Valle return true; 7470725b2d4dSFernando Eckhardt Valle } 7471725b2d4dSFernando Eckhardt Valle 747299082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 747399082815SRichard Henderson 7474139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7475fcf5ef2aSThomas Huth 7476139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7477fcf5ef2aSThomas Huth 7478139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7479fcf5ef2aSThomas Huth 7480139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7481fcf5ef2aSThomas Huth 7482139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7483fcf5ef2aSThomas Huth 74841f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 74851f26c751SDaniel Henrique Barboza 74865cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 74875cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 74885cb091a4SNikunj A Dadhania { 74895cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 74905cb091a4SNikunj A Dadhania case 0: /* lfdp */ 74915cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 74925cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 74935cb091a4SNikunj A Dadhania } 74945cb091a4SNikunj A Dadhania break; 74955cb091a4SNikunj A Dadhania case 2: /* lxsd */ 74965cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 74975cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 74985cb091a4SNikunj A Dadhania } 74995cb091a4SNikunj A Dadhania break; 75005cb091a4SNikunj A Dadhania case 3: /* lxssp */ 75015cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 75025cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 75035cb091a4SNikunj A Dadhania } 75045cb091a4SNikunj A Dadhania break; 75055cb091a4SNikunj A Dadhania } 75065cb091a4SNikunj A Dadhania return gen_invalid(ctx); 75075cb091a4SNikunj A Dadhania } 75085cb091a4SNikunj A Dadhania 7509d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7510e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7511e3001664SNikunj A Dadhania { 751272b70d5cSLucas Mateus Castro (alqotel) if ((ctx->opcode & 3) != 1) { /* DS-FORM */ 7513e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7514e3001664SNikunj A Dadhania case 0: /* stfdp */ 7515e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7516e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7517e3001664SNikunj A Dadhania } 7518e3001664SNikunj A Dadhania break; 7519e3001664SNikunj A Dadhania case 2: /* stxsd */ 7520e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7521e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7522e3001664SNikunj A Dadhania } 7523e3001664SNikunj A Dadhania break; 7524e3001664SNikunj A Dadhania case 3: /* stxssp */ 7525e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7526e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7527e3001664SNikunj A Dadhania } 7528e3001664SNikunj A Dadhania break; 7529e3001664SNikunj A Dadhania } 7530e3001664SNikunj A Dadhania } 7531e3001664SNikunj A Dadhania return gen_invalid(ctx); 7532e3001664SNikunj A Dadhania } 7533e3001664SNikunj A Dadhania 75349d69cfa2SLijun Pan #if defined(TARGET_PPC64) 75359d69cfa2SLijun Pan /* brd */ 75369d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 75379d69cfa2SLijun Pan { 75389d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 75399d69cfa2SLijun Pan } 75409d69cfa2SLijun Pan 75419d69cfa2SLijun Pan /* brw */ 75429d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 75439d69cfa2SLijun Pan { 75449d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 75459d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 75469d69cfa2SLijun Pan 75479d69cfa2SLijun Pan } 75489d69cfa2SLijun Pan 75499d69cfa2SLijun Pan /* brh */ 75509d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 75519d69cfa2SLijun Pan { 7552491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 75539d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 75549d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 75559d69cfa2SLijun Pan 75569d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 7557491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 7558491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 75599d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 75609d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 75619d69cfa2SLijun Pan 75629d69cfa2SLijun Pan tcg_temp_free_i64(t1); 75639d69cfa2SLijun Pan tcg_temp_free_i64(t2); 75649d69cfa2SLijun Pan } 75659d69cfa2SLijun Pan #endif 75669d69cfa2SLijun Pan 7567fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 75689d69cfa2SLijun Pan #if defined(TARGET_PPC64) 75699d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 75709d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 75719d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 75729d69cfa2SLijun Pan #endif 7573fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7574fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7575fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7576fcf5ef2aSThomas Huth #endif 7577fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7578fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7579fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7580fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7581fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7582fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7583fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7584fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7585fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7586fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7587fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7588fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7589fcf5ef2aSThomas Huth #endif 7590fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7591fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7592fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7593fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7594fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7595fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7596fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 759780b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7598b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 759980b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7600fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7601fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7602fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7603fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7604fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7605fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7606fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7607fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7608fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7609fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7610fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7611fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7612fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7613fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7614fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7615fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7616fcf5ef2aSThomas Huth #endif 7617fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7618fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7619fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7620fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7621fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7622fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7623fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7624fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7625fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7626fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7627fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7628fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7629fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7630fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7631fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7632fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7633fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7634fcf5ef2aSThomas Huth #endif 76355cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 76365cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 763772b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 7638e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7639fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7640fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7641fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7642fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7643fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7644fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7645c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7646fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7647fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7648fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7649fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7650a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7651a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7652fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7653fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7654fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7655fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7656a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7657a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7658fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7659fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7660fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7661fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7662fcf5ef2aSThomas Huth #endif 7663fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7664fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7665c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7666fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7667fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7668fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7669fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7670fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7671fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7672fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7673fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7674fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 76753c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 76763c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 76773c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 76783c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 76793c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 76803c89b8d6SNicholas Piggin #endif 7681cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7682fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7683fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7684fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7685fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7686fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7687fcf5ef2aSThomas Huth #endif 76883c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 76893c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 76903c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7691fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7692fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7693fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7694fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7695fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7696fcf5ef2aSThomas Huth #endif 7697fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7698fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7699fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7700fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7701fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7702fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7703fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7704fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7705fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7706b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7707fcf5ef2aSThomas Huth #endif 7708fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7709fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7710fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 771150728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7712fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7713fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 771450728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7715fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 771650728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7717fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 771850728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7719fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7720fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 772150728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7722fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 772399d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7724fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7725fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 772650728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7727fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7728fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7729fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7730fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7731fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7732fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7733fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7734fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7735fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7736fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7737fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7738fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7739fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7740fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7741fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7742fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7743fcf5ef2aSThomas Huth #endif 7744fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7745efe843d8SDavid Gibson /* 7746efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 7747efe843d8SDavid Gibson * different ISA versions 7748efe843d8SDavid Gibson */ 7749fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7750fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7751c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7752c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7753fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7754fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7755fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7756fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7757a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 775862d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7759fcf5ef2aSThomas Huth #endif 7760fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7761fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7762fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7763fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7764fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7765fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7766fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7767fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7768fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7769fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7770fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7771fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7772fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7773fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7774fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7775fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7776fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7777fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7778fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7779fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7780fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7781fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7782fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7783fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7784fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7785fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7786fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7787fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7788fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7789fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7790fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7791fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7792fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7793fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7794fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7795fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7796fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7797fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7798fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7799fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7800fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7801fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7802fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7803fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7804fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7805fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7806fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7807fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7808fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7809fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7810fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7811fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7812fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7813fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7814fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7815fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7816fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7817fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7818fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7819fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7820fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7821fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7822fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7823fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7824fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7825fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7826fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7827fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7828fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7829fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7830fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7831fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7832fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7833fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7834fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7835fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7836fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7837fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7838fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7839fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7840fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7841fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7842fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7843fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7844fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7845fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7846fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7847fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7848fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7849fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7850fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7851fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 78527af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 78537af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7854fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7855fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7856fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7857fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7858fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 785927a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7860fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7861fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 78620c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 78630c8d8c8bSBALATON Zoltan PPC_440_SPEC), 7864fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7865fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7866fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7867fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7868fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7869fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7870fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7871fcf5ef2aSThomas Huth PPC2_ISA300), 7872fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 78735ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 78745ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 78755ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 78765ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 7877fcf5ef2aSThomas Huth #endif 7878fcf5ef2aSThomas Huth 7879fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 7880fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 7881fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7882fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7883fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7884fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7885fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7886fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7887fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7888fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7889fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7890fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7891fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7892fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7893fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 78944c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7895fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7896fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7897fcf5ef2aSThomas Huth 7898fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 7899fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7900fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7901fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7902fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7903fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7904fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7905fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7906fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7907fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7908fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7909fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7910fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7911fcf5ef2aSThomas Huth 7912fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7913fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 7914fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7915fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7916fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7917fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7918fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7919fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7920fcf5ef2aSThomas Huth 7921fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7922fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7923fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7924fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7925fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7926fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7927fcf5ef2aSThomas Huth 7928fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 7929fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7930fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7931fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7932fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7933fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7934fcf5ef2aSThomas Huth #endif 7935fcf5ef2aSThomas Huth 7936fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 7937fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 7938fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7939fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7940fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7941fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7942fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7943fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7944fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7945fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7946fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7947fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7948fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7949fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7950fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7951fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7952fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7953fcf5ef2aSThomas Huth 7954fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 7955fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 7956fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7957fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7958fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7959fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7960fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7961fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7962fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7963fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7964fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7965fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7966fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7967fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7968fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7969fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7970fcf5ef2aSThomas Huth #endif 7971fcf5ef2aSThomas Huth 7972fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7973fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 7974fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 7975fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 7976fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7977fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7978fcf5ef2aSThomas Huth PPC_64B) 7979fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 7980fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7981fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7982fcf5ef2aSThomas Huth PPC_64B), \ 7983fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7984fcf5ef2aSThomas Huth PPC_64B), \ 7985fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7986fcf5ef2aSThomas Huth PPC_64B) 7987fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7988fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7989fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7990fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7991fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7992fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7993fcf5ef2aSThomas Huth #endif 7994fcf5ef2aSThomas Huth 7995fcf5ef2aSThomas Huth #undef GEN_LDX_E 7996fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7997fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7998fcf5ef2aSThomas Huth 7999fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8000fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8001fcf5ef2aSThomas Huth 8002fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8003fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8004fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8005fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8006fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8007fcf5ef2aSThomas Huth #endif 8008fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8009fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8010fcf5ef2aSThomas Huth 801150728199SRoman Kapl /* External PID based load */ 801250728199SRoman Kapl #undef GEN_LDEPX 801350728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 801450728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 801550728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 801650728199SRoman Kapl 801750728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 801850728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 801950728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 802050728199SRoman Kapl #if defined(TARGET_PPC64) 8021*fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 802250728199SRoman Kapl #endif 802350728199SRoman Kapl 8024fcf5ef2aSThomas Huth #undef GEN_STX_E 8025fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 80260123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8027fcf5ef2aSThomas Huth 8028fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8029fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8030fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8031fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8032fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8033fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8034fcf5ef2aSThomas Huth #endif 8035fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8036fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8037fcf5ef2aSThomas Huth 803850728199SRoman Kapl #undef GEN_STEPX 803950728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 804050728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 804150728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 804250728199SRoman Kapl 804350728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 804450728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 804550728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 804650728199SRoman Kapl #if defined(TARGET_PPC64) 8047*fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 804850728199SRoman Kapl #endif 804950728199SRoman Kapl 8050fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8051fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8052fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8053fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8054fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8055fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8056fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8057fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8058fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8059fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8060fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8061fcf5ef2aSThomas Huth 8062fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8063fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8064fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8065fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8066fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8067fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8068fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8069fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8070fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8071fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8072fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8073fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8074fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8075fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8076fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8077fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8078fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8079fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8080fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8081fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8082fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8083fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8084fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8085fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8086fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8087fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8088fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8089fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8090fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8091fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8092fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8093fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8094fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8095fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8096fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8097fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8098fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8099fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8100fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8101fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8102fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8103fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8104fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8105fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8106fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8107fcf5ef2aSThomas Huth 8108fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8109fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8110fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8111fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8112fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8113fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8114fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8115fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8116fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8117fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8118fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8119fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8120fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8121fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8122fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8123fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8124fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8125fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8126fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8127fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8128fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8129fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8130fcf5ef2aSThomas Huth 8131139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8132fcf5ef2aSThomas Huth 8133139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8134fcf5ef2aSThomas Huth 8135139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8136fcf5ef2aSThomas Huth 8137139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8138fcf5ef2aSThomas Huth }; 8139fcf5ef2aSThomas Huth 81407468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 81417468e2c8SBruno Larsen (billionai) /* Opcode types */ 81427468e2c8SBruno Larsen (billionai) enum { 81437468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 81447468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 81457468e2c8SBruno Larsen (billionai) }; 81467468e2c8SBruno Larsen (billionai) 81477468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 81487468e2c8SBruno Larsen (billionai) 81497468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 81507468e2c8SBruno Larsen (billionai) { 81517468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 81527468e2c8SBruno Larsen (billionai) } 81537468e2c8SBruno Larsen (billionai) 81547468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 81557468e2c8SBruno Larsen (billionai) { 81567468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 81577468e2c8SBruno Larsen (billionai) } 81587468e2c8SBruno Larsen (billionai) 81597468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 81607468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 81617468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 81627468e2c8SBruno Larsen (billionai) { 81637468e2c8SBruno Larsen (billionai) int i; 81647468e2c8SBruno Larsen (billionai) 81657468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 81667468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 81677468e2c8SBruno Larsen (billionai) } 81687468e2c8SBruno Larsen (billionai) } 81697468e2c8SBruno Larsen (billionai) 81707468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 81717468e2c8SBruno Larsen (billionai) { 81727468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 81737468e2c8SBruno Larsen (billionai) 81747468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 81757468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 81767468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 81777468e2c8SBruno Larsen (billionai) 81787468e2c8SBruno Larsen (billionai) return 0; 81797468e2c8SBruno Larsen (billionai) } 81807468e2c8SBruno Larsen (billionai) 81817468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 81827468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 81837468e2c8SBruno Larsen (billionai) { 81847468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 81857468e2c8SBruno Larsen (billionai) return -1; 81867468e2c8SBruno Larsen (billionai) } 81877468e2c8SBruno Larsen (billionai) table[idx] = handler; 81887468e2c8SBruno Larsen (billionai) 81897468e2c8SBruno Larsen (billionai) return 0; 81907468e2c8SBruno Larsen (billionai) } 81917468e2c8SBruno Larsen (billionai) 81927468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 81937468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 81947468e2c8SBruno Larsen (billionai) { 81957468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 81967468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 81977468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 81987468e2c8SBruno Larsen (billionai) return -1; 81997468e2c8SBruno Larsen (billionai) } 82007468e2c8SBruno Larsen (billionai) 82017468e2c8SBruno Larsen (billionai) return 0; 82027468e2c8SBruno Larsen (billionai) } 82037468e2c8SBruno Larsen (billionai) 82047468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 82057468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82067468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82077468e2c8SBruno Larsen (billionai) { 82087468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 82097468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 82107468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 82117468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 82127468e2c8SBruno Larsen (billionai) return -1; 82137468e2c8SBruno Larsen (billionai) } 82147468e2c8SBruno Larsen (billionai) } else { 82157468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 82167468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 82177468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 82187468e2c8SBruno Larsen (billionai) return -1; 82197468e2c8SBruno Larsen (billionai) } 82207468e2c8SBruno Larsen (billionai) } 82217468e2c8SBruno Larsen (billionai) if (handler != NULL && 82227468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 82237468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 82247468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 82257468e2c8SBruno Larsen (billionai) return -1; 82267468e2c8SBruno Larsen (billionai) } 82277468e2c8SBruno Larsen (billionai) 82287468e2c8SBruno Larsen (billionai) return 0; 82297468e2c8SBruno Larsen (billionai) } 82307468e2c8SBruno Larsen (billionai) 82317468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 82327468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82337468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82347468e2c8SBruno Larsen (billionai) { 82357468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 82367468e2c8SBruno Larsen (billionai) } 82377468e2c8SBruno Larsen (billionai) 82387468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 82397468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82407468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 82417468e2c8SBruno Larsen (billionai) { 82427468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 82437468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 82447468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 82457468e2c8SBruno Larsen (billionai) return -1; 82467468e2c8SBruno Larsen (billionai) } 82477468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 82487468e2c8SBruno Larsen (billionai) handler) < 0) { 82497468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 82507468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 82517468e2c8SBruno Larsen (billionai) return -1; 82527468e2c8SBruno Larsen (billionai) } 82537468e2c8SBruno Larsen (billionai) 82547468e2c8SBruno Larsen (billionai) return 0; 82557468e2c8SBruno Larsen (billionai) } 82567468e2c8SBruno Larsen (billionai) 82577468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 82587468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82597468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 82607468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82617468e2c8SBruno Larsen (billionai) { 82627468e2c8SBruno Larsen (billionai) opc_handler_t **table; 82637468e2c8SBruno Larsen (billionai) 82647468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 82657468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 82667468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 82677468e2c8SBruno Larsen (billionai) return -1; 82687468e2c8SBruno Larsen (billionai) } 82697468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 82707468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 82717468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 82727468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 82737468e2c8SBruno Larsen (billionai) return -1; 82747468e2c8SBruno Larsen (billionai) } 82757468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 82767468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 82777468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 82787468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 82797468e2c8SBruno Larsen (billionai) return -1; 82807468e2c8SBruno Larsen (billionai) } 82817468e2c8SBruno Larsen (billionai) return 0; 82827468e2c8SBruno Larsen (billionai) } 82837468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 82847468e2c8SBruno Larsen (billionai) { 82857468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 82867468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 82877468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 82887468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 82897468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 82907468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 82917468e2c8SBruno Larsen (billionai) return -1; 82927468e2c8SBruno Larsen (billionai) } 82937468e2c8SBruno Larsen (billionai) } else { 82947468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 82957468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 82967468e2c8SBruno Larsen (billionai) return -1; 82977468e2c8SBruno Larsen (billionai) } 82987468e2c8SBruno Larsen (billionai) } 82997468e2c8SBruno Larsen (billionai) } else { 83007468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 83017468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 83027468e2c8SBruno Larsen (billionai) return -1; 83037468e2c8SBruno Larsen (billionai) } 83047468e2c8SBruno Larsen (billionai) } 83057468e2c8SBruno Larsen (billionai) } else { 83067468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 83077468e2c8SBruno Larsen (billionai) return -1; 83087468e2c8SBruno Larsen (billionai) } 83097468e2c8SBruno Larsen (billionai) } 83107468e2c8SBruno Larsen (billionai) 83117468e2c8SBruno Larsen (billionai) return 0; 83127468e2c8SBruno Larsen (billionai) } 83137468e2c8SBruno Larsen (billionai) 83147468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 83157468e2c8SBruno Larsen (billionai) { 83167468e2c8SBruno Larsen (billionai) int i, count, tmp; 83177468e2c8SBruno Larsen (billionai) 83187468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 83197468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 83207468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 83217468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 83227468e2c8SBruno Larsen (billionai) } 83237468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 83247468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 83257468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 83267468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 83277468e2c8SBruno Larsen (billionai) if (tmp == 0) { 83287468e2c8SBruno Larsen (billionai) free(table[i]); 83297468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 83307468e2c8SBruno Larsen (billionai) } else { 83317468e2c8SBruno Larsen (billionai) count++; 83327468e2c8SBruno Larsen (billionai) } 83337468e2c8SBruno Larsen (billionai) } else { 83347468e2c8SBruno Larsen (billionai) count++; 83357468e2c8SBruno Larsen (billionai) } 83367468e2c8SBruno Larsen (billionai) } 83377468e2c8SBruno Larsen (billionai) } 83387468e2c8SBruno Larsen (billionai) 83397468e2c8SBruno Larsen (billionai) return count; 83407468e2c8SBruno Larsen (billionai) } 83417468e2c8SBruno Larsen (billionai) 83427468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 83437468e2c8SBruno Larsen (billionai) { 83447468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 83457468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 83467468e2c8SBruno Larsen (billionai) } 83477468e2c8SBruno Larsen (billionai) } 83487468e2c8SBruno Larsen (billionai) 83497468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 83507468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 83517468e2c8SBruno Larsen (billionai) { 83527468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 83537468e2c8SBruno Larsen (billionai) opcode_t *opc; 83547468e2c8SBruno Larsen (billionai) 83557468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 83567468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 83577468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 83587468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 83597468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 83607468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 83617468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 83627468e2c8SBruno Larsen (billionai) opc->opc3); 83637468e2c8SBruno Larsen (billionai) return; 83647468e2c8SBruno Larsen (billionai) } 83657468e2c8SBruno Larsen (billionai) } 83667468e2c8SBruno Larsen (billionai) } 83677468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 83687468e2c8SBruno Larsen (billionai) fflush(stdout); 83697468e2c8SBruno Larsen (billionai) fflush(stderr); 83707468e2c8SBruno Larsen (billionai) } 83717468e2c8SBruno Larsen (billionai) 83727468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 83737468e2c8SBruno Larsen (billionai) { 83747468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 83757468e2c8SBruno Larsen (billionai) int i, j, k; 83767468e2c8SBruno Larsen (billionai) 83777468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 83787468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 83797468e2c8SBruno Larsen (billionai) continue; 83807468e2c8SBruno Larsen (billionai) } 83817468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 83827468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 83837468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 83847468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 83857468e2c8SBruno Larsen (billionai) continue; 83867468e2c8SBruno Larsen (billionai) } 83877468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 83887468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 83897468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 83907468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 83917468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 83927468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 83937468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 83947468e2c8SBruno Larsen (billionai) } 83957468e2c8SBruno Larsen (billionai) } 83967468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 83977468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 83987468e2c8SBruno Larsen (billionai) } 83997468e2c8SBruno Larsen (billionai) } 84007468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 84017468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 84027468e2c8SBruno Larsen (billionai) } 84037468e2c8SBruno Larsen (billionai) } 84047468e2c8SBruno Larsen (billionai) } 84057468e2c8SBruno Larsen (billionai) 84067468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 84077468e2c8SBruno Larsen (billionai) { 84087468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 84097468e2c8SBruno Larsen (billionai) 84107468e2c8SBruno Larsen (billionai) /* 84117468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 84127468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 84137468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 84147468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 84157468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 84167468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 84177468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 84187468e2c8SBruno Larsen (billionai) */ 84197468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 84207468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 84217468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 84227468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 84237468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 84247468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 84257468e2c8SBruno Larsen (billionai) } 84267468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 84277468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 84287468e2c8SBruno Larsen (billionai) return 0; 84297468e2c8SBruno Larsen (billionai) } 84307468e2c8SBruno Larsen (billionai) 8431624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 8432624cb07fSRichard Henderson { 8433624cb07fSRichard Henderson opc_handler_t **table, *handler; 8434624cb07fSRichard Henderson uint32_t inval; 8435624cb07fSRichard Henderson 8436624cb07fSRichard Henderson ctx->opcode = insn; 8437624cb07fSRichard Henderson 8438624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8439624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8440624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 8441624cb07fSRichard Henderson 8442624cb07fSRichard Henderson table = cpu->opcodes; 8443624cb07fSRichard Henderson handler = table[opc1(insn)]; 8444624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8445624cb07fSRichard Henderson table = ind_table(handler); 8446624cb07fSRichard Henderson handler = table[opc2(insn)]; 8447624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8448624cb07fSRichard Henderson table = ind_table(handler); 8449624cb07fSRichard Henderson handler = table[opc3(insn)]; 8450624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8451624cb07fSRichard Henderson table = ind_table(handler); 8452624cb07fSRichard Henderson handler = table[opc4(insn)]; 8453624cb07fSRichard Henderson } 8454624cb07fSRichard Henderson } 8455624cb07fSRichard Henderson } 8456624cb07fSRichard Henderson 8457624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 8458624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 8459624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8460624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8461624cb07fSRichard Henderson TARGET_FMT_lx "\n", 8462624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8463624cb07fSRichard Henderson insn, ctx->cia); 8464624cb07fSRichard Henderson return false; 8465624cb07fSRichard Henderson } 8466624cb07fSRichard Henderson 8467624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8468624cb07fSRichard Henderson && Rc(insn))) { 8469624cb07fSRichard Henderson inval = handler->inval2; 8470624cb07fSRichard Henderson } else { 8471624cb07fSRichard Henderson inval = handler->inval1; 8472624cb07fSRichard Henderson } 8473624cb07fSRichard Henderson 8474624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 8475624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8476624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8477624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 8478624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8479624cb07fSRichard Henderson insn, ctx->cia); 8480624cb07fSRichard Henderson return false; 8481624cb07fSRichard Henderson } 8482624cb07fSRichard Henderson 8483624cb07fSRichard Henderson handler->handler(ctx); 8484624cb07fSRichard Henderson return true; 8485624cb07fSRichard Henderson } 8486624cb07fSRichard Henderson 8487b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 8488fcf5ef2aSThomas Huth { 8489b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 84909c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 84912df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 8492fcf5ef2aSThomas Huth 8493b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 84942df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 8495d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 84962df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 84972df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 8498b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 8499b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 8500b0c2d521SEmilio G. Cota ctx->access_type = -1; 8501d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 85022df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 8503b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 85040e3bf489SRoman Kapl ctx->flags = env->flags; 8505fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 85062df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 8507b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 8508fcf5ef2aSThomas Huth #endif 8509e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 8510e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 8511d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 8512fcf5ef2aSThomas Huth 85132df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 85142df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 85152df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 85162df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 85172df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 8518f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 85191db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 8520f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 8521f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 852246d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 85232df4fe7aSRichard Henderson 8524b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 85252df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 85262df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 85279498d103SRichard Henderson ctx->base.max_insns = 1; 8528efe843d8SDavid Gibson } 85292df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 8530b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 8531efe843d8SDavid Gibson } 853213b45575SRichard Henderson } 8533fcf5ef2aSThomas Huth 8534b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 8535b0c2d521SEmilio G. Cota { 8536b0c2d521SEmilio G. Cota } 8537fcf5ef2aSThomas Huth 8538b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 8539b0c2d521SEmilio G. Cota { 8540b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 8541b0c2d521SEmilio G. Cota } 8542b0c2d521SEmilio G. Cota 854399082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 854499082815SRichard Henderson { 854599082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 854699082815SRichard Henderson return opc1(insn) == 1; 854799082815SRichard Henderson } 854899082815SRichard Henderson 8549b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 8550b0c2d521SEmilio G. Cota { 8551b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 855228876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 8553b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 855499082815SRichard Henderson target_ulong pc; 8555624cb07fSRichard Henderson uint32_t insn; 8556624cb07fSRichard Henderson bool ok; 8557b0c2d521SEmilio G. Cota 8558fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 8559fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 8560b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 8561b0c2d521SEmilio G. Cota 856299082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 85634e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 856499082815SRichard Henderson ctx->base.pc_next = pc += 4; 8565fcf5ef2aSThomas Huth 856699082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 856799082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 856899082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 856999082815SRichard Henderson } else if ((pc & 63) == 0) { 857099082815SRichard Henderson /* 857199082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 857299082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 857399082815SRichard Henderson * 64-byte address boundary (system alignment error). 857499082815SRichard Henderson */ 857599082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 857699082815SRichard Henderson ok = true; 857799082815SRichard Henderson } else { 85784e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 85794e116893SIlya Leoshkevich need_byteswap(ctx)); 858099082815SRichard Henderson ctx->base.pc_next = pc += 4; 858199082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 858299082815SRichard Henderson } 8583624cb07fSRichard Henderson if (!ok) { 8584624cb07fSRichard Henderson gen_invalid(ctx); 8585fcf5ef2aSThomas Huth } 8586624cb07fSRichard Henderson 858764a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 858899082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 858964a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 859064a0f644SRichard Henderson } 859164a0f644SRichard Henderson 859251eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 8593fcf5ef2aSThomas Huth } 8594b0c2d521SEmilio G. Cota 8595b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 8596b0c2d521SEmilio G. Cota { 8597b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8598a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 8599a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 8600b0c2d521SEmilio G. Cota 8601a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 8602a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 86033d8a5b69SRichard Henderson return; 86043d8a5b69SRichard Henderson } 86053d8a5b69SRichard Henderson 8606a9b5b3d0SRichard Henderson /* Honor single stepping. */ 86079498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 86089498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 8609a9b5b3d0SRichard Henderson switch (is_jmp) { 8610a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8611a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8612a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8613a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8614a9b5b3d0SRichard Henderson break; 8615a9b5b3d0SRichard Henderson case DISAS_EXIT: 8616a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8617a9b5b3d0SRichard Henderson break; 8618a9b5b3d0SRichard Henderson default: 8619a9b5b3d0SRichard Henderson g_assert_not_reached(); 8620fcf5ef2aSThomas Huth } 862113b45575SRichard Henderson 8622a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 8623a9b5b3d0SRichard Henderson return; 8624a9b5b3d0SRichard Henderson } 8625a9b5b3d0SRichard Henderson 8626a9b5b3d0SRichard Henderson switch (is_jmp) { 8627a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8628a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 862946d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 8630a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 8631a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8632a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 8633a9b5b3d0SRichard Henderson break; 8634a9b5b3d0SRichard Henderson } 8635a9b5b3d0SRichard Henderson /* fall through */ 8636a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8637a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8638a9b5b3d0SRichard Henderson /* fall through */ 8639a9b5b3d0SRichard Henderson case DISAS_CHAIN: 864046d396bdSDaniel Henrique Barboza /* 864146d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 864246d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 864346d396bdSDaniel Henrique Barboza */ 864446d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 864546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 864646d396bdSDaniel Henrique Barboza } 864746d396bdSDaniel Henrique Barboza 8648a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 8649a9b5b3d0SRichard Henderson break; 8650a9b5b3d0SRichard Henderson 8651a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8652a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8653a9b5b3d0SRichard Henderson /* fall through */ 8654a9b5b3d0SRichard Henderson case DISAS_EXIT: 865546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 865607ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 8657a9b5b3d0SRichard Henderson break; 8658a9b5b3d0SRichard Henderson 8659a9b5b3d0SRichard Henderson default: 8660a9b5b3d0SRichard Henderson g_assert_not_reached(); 8661fcf5ef2aSThomas Huth } 8662fcf5ef2aSThomas Huth } 8663b0c2d521SEmilio G. Cota 8664b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8665b0c2d521SEmilio G. Cota { 8666b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8667b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8668b0c2d521SEmilio G. Cota } 8669b0c2d521SEmilio G. Cota 8670b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 8671b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 8672b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 8673b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 8674b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 8675b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 8676b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 8677b0c2d521SEmilio G. Cota }; 8678b0c2d521SEmilio G. Cota 86798b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8680b0c2d521SEmilio G. Cota { 8681b0c2d521SEmilio G. Cota DisasContext ctx; 8682b0c2d521SEmilio G. Cota 86838b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8684fcf5ef2aSThomas Huth } 8685fcf5ef2aSThomas Huth 8686fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8687fcf5ef2aSThomas Huth target_ulong *data) 8688fcf5ef2aSThomas Huth { 8689fcf5ef2aSThomas Huth env->nip = data[0]; 8690fcf5ef2aSThomas Huth } 8691