1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3899e964efSFabiano Rosas #include "spr_common.h" 39eeaaefe9SLeandro Lupori #include "power8-pmu.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth 47fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 48efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 49fcf5ef2aSThomas Huth 50fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 51fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 52fcf5ef2aSThomas Huth #else 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 54fcf5ef2aSThomas Huth #endif 55fcf5ef2aSThomas Huth /*****************************************************************************/ 56fcf5ef2aSThomas Huth /* Code translation helpers */ 57fcf5ef2aSThomas Huth 58fcf5ef2aSThomas Huth /* global register indexes */ 59fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 60fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 61fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 62fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 63fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 64fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 65fcf5ef2aSThomas Huth static TCGv cpu_nip; 66fcf5ef2aSThomas Huth static TCGv cpu_msr; 67fcf5ef2aSThomas Huth static TCGv cpu_ctr; 68fcf5ef2aSThomas Huth static TCGv cpu_lr; 69fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 70fcf5ef2aSThomas Huth static TCGv cpu_cfar; 71fcf5ef2aSThomas Huth #endif 72dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 73fcf5ef2aSThomas Huth static TCGv cpu_reserve; 74253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 75894448aeSRichard Henderson static TCGv cpu_reserve_val2; 76fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 77fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth void ppc_translate_init(void) 82fcf5ef2aSThomas Huth { 83fcf5ef2aSThomas Huth int i; 84fcf5ef2aSThomas Huth char *p; 85fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 86fcf5ef2aSThomas Huth 87fcf5ef2aSThomas Huth p = cpu_reg_names; 88fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 91fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 92fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 93fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 94fcf5ef2aSThomas Huth p += 5; 95fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 96fcf5ef2aSThomas Huth } 97fcf5ef2aSThomas Huth 98fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 99fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 100fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 101fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 102fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 103fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 105fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 106fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 107fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 108fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth } 110fcf5ef2aSThomas Huth 111fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 112fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 115fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 118fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 124fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 125fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 126fcf5ef2aSThomas Huth #endif 127fcf5ef2aSThomas Huth 128fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 130fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 132fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 134fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 135fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 136dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 138dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 139dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 140fcf5ef2aSThomas Huth 141fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 142fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 143fcf5ef2aSThomas Huth "reserve_addr"); 144253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 145253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 146253ce7b2SNikunj A Dadhania "reserve_val"); 147894448aeSRichard Henderson cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 148894448aeSRichard Henderson offsetof(CPUPPCState, reserve_val2), 149894448aeSRichard Henderson "reserve_val2"); 150fcf5ef2aSThomas Huth 151fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 152fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 155efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 156efe843d8SDavid Gibson "access_type"); 157fcf5ef2aSThomas Huth } 158fcf5ef2aSThomas Huth 159fcf5ef2aSThomas Huth /* internal defines */ 160fcf5ef2aSThomas Huth struct DisasContext { 161b6bac4bcSEmilio G. Cota DisasContextBase base; 1622c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 163fcf5ef2aSThomas Huth uint32_t opcode; 164fcf5ef2aSThomas Huth /* Routine used to access memory */ 165fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 166fcf5ef2aSThomas Huth bool lazy_tlb_flush; 167fcf5ef2aSThomas Huth bool need_access_type; 168fcf5ef2aSThomas Huth int mem_idx; 169fcf5ef2aSThomas Huth int access_type; 170fcf5ef2aSThomas Huth /* Translation flags */ 17114776ab5STony Nguyen MemOp default_tcg_memop_mask; 172fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 173fcf5ef2aSThomas Huth bool sf_mode; 174fcf5ef2aSThomas Huth bool has_cfar; 175fcf5ef2aSThomas Huth #endif 176fcf5ef2aSThomas Huth bool fpu_enabled; 177fcf5ef2aSThomas Huth bool altivec_enabled; 178fcf5ef2aSThomas Huth bool vsx_enabled; 179fcf5ef2aSThomas Huth bool spe_enabled; 180fcf5ef2aSThomas Huth bool tm_enabled; 181c6fd28fdSSuraj Jitindar Singh bool gtse; 1821db3632aSMatheus Ferst bool hr; 183f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 184f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 1858b3d1c49SLeandro Lupori bool mmcr0_pmcjce; 1868b3d1c49SLeandro Lupori bool pmc_other; 18746d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 188fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 189fcf5ef2aSThomas Huth int singlestep_enabled; 1900e3bf489SRoman Kapl uint32_t flags; 191fcf5ef2aSThomas Huth uint64_t insns_flags; 192fcf5ef2aSThomas Huth uint64_t insns_flags2; 193fcf5ef2aSThomas Huth }; 194fcf5ef2aSThomas Huth 195a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 196a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 197a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 198a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 199a9b5b3d0SRichard Henderson 200fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 201fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 202fcf5ef2aSThomas Huth { 203ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 204fcf5ef2aSThomas Huth return ctx->le_mode; 205fcf5ef2aSThomas Huth #else 206fcf5ef2aSThomas Huth return !ctx->le_mode; 207fcf5ef2aSThomas Huth #endif 208fcf5ef2aSThomas Huth } 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 211fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 212fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 213fcf5ef2aSThomas Huth #else 214fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 215fcf5ef2aSThomas Huth #endif 216fcf5ef2aSThomas Huth 217fcf5ef2aSThomas Huth struct opc_handler_t { 218fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 219fcf5ef2aSThomas Huth uint32_t inval1; 220fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 221fcf5ef2aSThomas Huth uint32_t inval2; 222fcf5ef2aSThomas Huth /* instruction type */ 223fcf5ef2aSThomas Huth uint64_t type; 224fcf5ef2aSThomas Huth /* extended instruction type */ 225fcf5ef2aSThomas Huth uint64_t type2; 226fcf5ef2aSThomas Huth /* handler */ 227fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 228fcf5ef2aSThomas Huth }; 229fcf5ef2aSThomas Huth 2300e3bf489SRoman Kapl /* SPR load/store helpers */ 2310e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2320e3bf489SRoman Kapl { 2330e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2340e3bf489SRoman Kapl } 2350e3bf489SRoman Kapl 2360e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2370e3bf489SRoman Kapl { 2380e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2390e3bf489SRoman Kapl } 2400e3bf489SRoman Kapl 241fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 242fcf5ef2aSThomas Huth { 243fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 244fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 245fcf5ef2aSThomas Huth ctx->access_type = access_type; 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth } 248fcf5ef2aSThomas Huth 249fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 250fcf5ef2aSThomas Huth { 251fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 252fcf5ef2aSThomas Huth nip = (uint32_t)nip; 253fcf5ef2aSThomas Huth } 254fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 255fcf5ef2aSThomas Huth } 256fcf5ef2aSThomas Huth 257fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 258fcf5ef2aSThomas Huth { 259fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 260fcf5ef2aSThomas Huth 261efe843d8SDavid Gibson /* 262efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 263efe843d8SDavid Gibson * faulting instruction 264fcf5ef2aSThomas Huth */ 2652c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 2667058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 2677058ff52SRichard Henderson t1 = tcg_constant_i32(error); 268fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 2693d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 270fcf5ef2aSThomas Huth } 271fcf5ef2aSThomas Huth 272fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 273fcf5ef2aSThomas Huth { 274fcf5ef2aSThomas Huth TCGv_i32 t0; 275fcf5ef2aSThomas Huth 276efe843d8SDavid Gibson /* 277efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 278efe843d8SDavid Gibson * faulting instruction 279fcf5ef2aSThomas Huth */ 2802c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 2817058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 282fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 2833d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 284fcf5ef2aSThomas Huth } 285fcf5ef2aSThomas Huth 286fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 287fcf5ef2aSThomas Huth target_ulong nip) 288fcf5ef2aSThomas Huth { 289fcf5ef2aSThomas Huth TCGv_i32 t0; 290fcf5ef2aSThomas Huth 291fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 2927058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 293fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 2943d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 295fcf5ef2aSThomas Huth } 296fcf5ef2aSThomas Huth 297f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 298f5b6daacSRichard Henderson { 299f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 300f5b6daacSRichard Henderson gen_io_start(); 301f5b6daacSRichard Henderson /* 302f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 303f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 304f5b6daacSRichard Henderson * decide if we need to return to the main loop. 305f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 306f5b6daacSRichard Henderson */ 307f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 308f5b6daacSRichard Henderson } 309f5b6daacSRichard Henderson } 310f5b6daacSRichard Henderson 3112fdedcbcSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 3122fdedcbcSMatheus Ferst static void gen_ppc_maybe_interrupt(DisasContext *ctx) 3132fdedcbcSMatheus Ferst { 3142fdedcbcSMatheus Ferst gen_icount_io_start(ctx); 3152fdedcbcSMatheus Ferst gen_helper_ppc_maybe_interrupt(cpu_env); 3162fdedcbcSMatheus Ferst } 3172fdedcbcSMatheus Ferst #endif 3182fdedcbcSMatheus Ferst 319e150ac89SRoman Kapl /* 320e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 321e150ac89SRoman Kapl * SPR registers for this exception. 322e150ac89SRoman Kapl * 323e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 324e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3250e3bf489SRoman Kapl */ 326e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3270e3bf489SRoman Kapl { 3280e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3290e3bf489SRoman Kapl target_ulong dbsr = 0; 330e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3310e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 332e150ac89SRoman Kapl } else { 333e150ac89SRoman Kapl /* Must have been branch */ 3340e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3350e3bf489SRoman Kapl } 3360e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3370e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3380e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3390e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3400e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3410e3bf489SRoman Kapl } else { 342e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3430e3bf489SRoman Kapl } 3440e3bf489SRoman Kapl } 3450e3bf489SRoman Kapl 346fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 347fcf5ef2aSThomas Huth { 3489498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3493d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 350fcf5ef2aSThomas Huth } 351fcf5ef2aSThomas Huth 352fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 353fcf5ef2aSThomas Huth { 354fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 355fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 356fcf5ef2aSThomas Huth } 357fcf5ef2aSThomas Huth 358fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 359fcf5ef2aSThomas Huth { 360fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 361fcf5ef2aSThomas Huth } 362fcf5ef2aSThomas Huth 363fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 364fcf5ef2aSThomas Huth { 365fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 366fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 367fcf5ef2aSThomas Huth } 368fcf5ef2aSThomas Huth 36937f219c8SBruno Larsen (billionai) /*****************************************************************************/ 37037f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 37137f219c8SBruno Larsen (billionai) 372a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 37337f219c8SBruno Larsen (billionai) { 37437f219c8SBruno Larsen (billionai) #if 0 37537f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 37637f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 37737f219c8SBruno Larsen (billionai) #endif 37837f219c8SBruno Larsen (billionai) } 37937f219c8SBruno Larsen (billionai) 38037f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 38137f219c8SBruno Larsen (billionai) 38237f219c8SBruno Larsen (billionai) /* 38337f219c8SBruno Larsen (billionai) * Generic callbacks: 38437f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 38537f219c8SBruno Larsen (billionai) */ 38637f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 38737f219c8SBruno Larsen (billionai) { 38837f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 3897058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 39037f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 39137f219c8SBruno Larsen (billionai) #endif 39237f219c8SBruno Larsen (billionai) } 39337f219c8SBruno Larsen (billionai) 394a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 39537f219c8SBruno Larsen (billionai) { 39637f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 39737f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 39837f219c8SBruno Larsen (billionai) } 39937f219c8SBruno Larsen (billionai) 40037f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 40137f219c8SBruno Larsen (billionai) { 40237f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4037058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 40437f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 40537f219c8SBruno Larsen (billionai) #endif 40637f219c8SBruno Larsen (billionai) } 40737f219c8SBruno Larsen (billionai) 408a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 40937f219c8SBruno Larsen (billionai) { 41037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 41137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41237f219c8SBruno Larsen (billionai) } 41337f219c8SBruno Larsen (billionai) 414a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 41537f219c8SBruno Larsen (billionai) { 41637f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 41737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 41837f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 41937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42037f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42137f219c8SBruno Larsen (billionai) #else 42237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 42337f219c8SBruno Larsen (billionai) #endif 42437f219c8SBruno Larsen (billionai) } 42537f219c8SBruno Larsen (billionai) 426*fbda88f7SNicholas Piggin void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 427*fbda88f7SNicholas Piggin { 428*fbda88f7SNicholas Piggin spr_write_generic32(ctx, sprn, gprn); 429*fbda88f7SNicholas Piggin 430*fbda88f7SNicholas Piggin /* 431*fbda88f7SNicholas Piggin * SPR_CTRL writes must force a new translation block, 432*fbda88f7SNicholas Piggin * allowing the PMU to calculate the run latch events with 433*fbda88f7SNicholas Piggin * more accuracy. 434*fbda88f7SNicholas Piggin */ 435*fbda88f7SNicholas Piggin ctx->base.is_jmp = DISAS_EXIT_UPDATE; 436*fbda88f7SNicholas Piggin } 437*fbda88f7SNicholas Piggin 438*fbda88f7SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 439a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 44037f219c8SBruno Larsen (billionai) { 44137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 44337f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 44437f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 44537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 44637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 44737f219c8SBruno Larsen (billionai) } 44837f219c8SBruno Larsen (billionai) 449a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 45037f219c8SBruno Larsen (billionai) { 45137f219c8SBruno Larsen (billionai) } 45237f219c8SBruno Larsen (billionai) 45337f219c8SBruno Larsen (billionai) #endif 45437f219c8SBruno Larsen (billionai) 45537f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 45637f219c8SBruno Larsen (billionai) /* XER */ 457a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 45837f219c8SBruno Larsen (billionai) { 45937f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 46037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 46137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 46237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 46337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 46437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 46537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 46637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 46737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 46837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 46937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47037f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 47137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 47237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 47437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47537f219c8SBruno Larsen (billionai) } 47637f219c8SBruno Larsen (billionai) } 47737f219c8SBruno Larsen (billionai) 478a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 47937f219c8SBruno Larsen (billionai) { 48037f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 48137f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 48237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 48337f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 48437f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 48537f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 48637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 48737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 48837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 48937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 49037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 49137f219c8SBruno Larsen (billionai) } 49237f219c8SBruno Larsen (billionai) 49337f219c8SBruno Larsen (billionai) /* LR */ 494a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 49537f219c8SBruno Larsen (billionai) { 49637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 49737f219c8SBruno Larsen (billionai) } 49837f219c8SBruno Larsen (billionai) 499a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 50037f219c8SBruno Larsen (billionai) { 50137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 50237f219c8SBruno Larsen (billionai) } 50337f219c8SBruno Larsen (billionai) 50437f219c8SBruno Larsen (billionai) /* CFAR */ 50537f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 506a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 50737f219c8SBruno Larsen (billionai) { 50837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 50937f219c8SBruno Larsen (billionai) } 51037f219c8SBruno Larsen (billionai) 511a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 51237f219c8SBruno Larsen (billionai) { 51337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 51437f219c8SBruno Larsen (billionai) } 51537f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 51637f219c8SBruno Larsen (billionai) 51737f219c8SBruno Larsen (billionai) /* CTR */ 518a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 51937f219c8SBruno Larsen (billionai) { 52037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 52137f219c8SBruno Larsen (billionai) } 52237f219c8SBruno Larsen (billionai) 523a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 52437f219c8SBruno Larsen (billionai) { 52537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 52637f219c8SBruno Larsen (billionai) } 52737f219c8SBruno Larsen (billionai) 52837f219c8SBruno Larsen (billionai) /* User read access to SPR */ 52937f219c8SBruno Larsen (billionai) /* USPRx */ 53037f219c8SBruno Larsen (billionai) /* UMMCRx */ 53137f219c8SBruno Larsen (billionai) /* UPMCx */ 53237f219c8SBruno Larsen (billionai) /* USIA */ 53337f219c8SBruno Larsen (billionai) /* UDECR */ 534a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 53537f219c8SBruno Larsen (billionai) { 53637f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 53737f219c8SBruno Larsen (billionai) } 53837f219c8SBruno Larsen (billionai) 53937f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 540a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 54137f219c8SBruno Larsen (billionai) { 54237f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 54337f219c8SBruno Larsen (billionai) } 54437f219c8SBruno Larsen (billionai) #endif 54537f219c8SBruno Larsen (billionai) 54637f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 54737f219c8SBruno Larsen (billionai) /* DECR */ 54837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 549a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 55037f219c8SBruno Larsen (billionai) { 551f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55237f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 55337f219c8SBruno Larsen (billionai) } 55437f219c8SBruno Larsen (billionai) 555a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 55637f219c8SBruno Larsen (billionai) { 557f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55837f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 55937f219c8SBruno Larsen (billionai) } 56037f219c8SBruno Larsen (billionai) #endif 56137f219c8SBruno Larsen (billionai) 56237f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 56337f219c8SBruno Larsen (billionai) /* Time base */ 564a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 56537f219c8SBruno Larsen (billionai) { 566f5b6daacSRichard Henderson gen_icount_io_start(ctx); 56737f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 56837f219c8SBruno Larsen (billionai) } 56937f219c8SBruno Larsen (billionai) 570a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 57137f219c8SBruno Larsen (billionai) { 572f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57337f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 57437f219c8SBruno Larsen (billionai) } 57537f219c8SBruno Larsen (billionai) 576a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 57737f219c8SBruno Larsen (billionai) { 57837f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 57937f219c8SBruno Larsen (billionai) } 58037f219c8SBruno Larsen (billionai) 581a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 58237f219c8SBruno Larsen (billionai) { 58337f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 58437f219c8SBruno Larsen (billionai) } 58537f219c8SBruno Larsen (billionai) 58637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 587a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 58837f219c8SBruno Larsen (billionai) { 589f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59037f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 59137f219c8SBruno Larsen (billionai) } 59237f219c8SBruno Larsen (billionai) 593a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 59437f219c8SBruno Larsen (billionai) { 595f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59637f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 59737f219c8SBruno Larsen (billionai) } 59837f219c8SBruno Larsen (billionai) 599a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 60037f219c8SBruno Larsen (billionai) { 60137f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 60237f219c8SBruno Larsen (billionai) } 60337f219c8SBruno Larsen (billionai) 604a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 60537f219c8SBruno Larsen (billionai) { 60637f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 60737f219c8SBruno Larsen (billionai) } 60837f219c8SBruno Larsen (billionai) 60937f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 610a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 61137f219c8SBruno Larsen (billionai) { 612f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61337f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 61437f219c8SBruno Larsen (billionai) } 61537f219c8SBruno Larsen (billionai) 616a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 61737f219c8SBruno Larsen (billionai) { 618f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61937f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 62037f219c8SBruno Larsen (billionai) } 62137f219c8SBruno Larsen (billionai) 62237f219c8SBruno Larsen (billionai) /* HDECR */ 623a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 62437f219c8SBruno Larsen (billionai) { 625f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62637f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 62737f219c8SBruno Larsen (billionai) } 62837f219c8SBruno Larsen (billionai) 629a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 63037f219c8SBruno Larsen (billionai) { 631f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63237f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 63337f219c8SBruno Larsen (billionai) } 63437f219c8SBruno Larsen (billionai) 635a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 63637f219c8SBruno Larsen (billionai) { 637f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63837f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 63937f219c8SBruno Larsen (billionai) } 64037f219c8SBruno Larsen (billionai) 641a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 64237f219c8SBruno Larsen (billionai) { 643f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64437f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 64537f219c8SBruno Larsen (billionai) } 64637f219c8SBruno Larsen (billionai) 647a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 64837f219c8SBruno Larsen (billionai) { 649f5b6daacSRichard Henderson gen_icount_io_start(ctx); 65037f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 65137f219c8SBruno Larsen (billionai) } 65237f219c8SBruno Larsen (billionai) 65337f219c8SBruno Larsen (billionai) #endif 65437f219c8SBruno Larsen (billionai) #endif 65537f219c8SBruno Larsen (billionai) 65637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 65737f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 65837f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 659a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 66037f219c8SBruno Larsen (billionai) { 66137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 66237f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 66337f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 66437f219c8SBruno Larsen (billionai) } 66537f219c8SBruno Larsen (billionai) 666a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 66737f219c8SBruno Larsen (billionai) { 66837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 66937f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 67037f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 67137f219c8SBruno Larsen (billionai) } 67237f219c8SBruno Larsen (billionai) 673a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 67437f219c8SBruno Larsen (billionai) { 6757058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 67637f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 67737f219c8SBruno Larsen (billionai) } 67837f219c8SBruno Larsen (billionai) 679a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 68037f219c8SBruno Larsen (billionai) { 6817058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 68237f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) 685a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 68637f219c8SBruno Larsen (billionai) { 6877058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 68837f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68937f219c8SBruno Larsen (billionai) } 69037f219c8SBruno Larsen (billionai) 691a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 69237f219c8SBruno Larsen (billionai) { 6937058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 69437f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 69537f219c8SBruno Larsen (billionai) } 69637f219c8SBruno Larsen (billionai) 69737f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 69837f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 699a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 70037f219c8SBruno Larsen (billionai) { 70137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70237f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70337f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 70437f219c8SBruno Larsen (billionai) } 70537f219c8SBruno Larsen (billionai) 706a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 70737f219c8SBruno Larsen (billionai) { 70837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70937f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 71037f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 71137f219c8SBruno Larsen (billionai) } 71237f219c8SBruno Larsen (billionai) 713a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 71437f219c8SBruno Larsen (billionai) { 7157058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 71637f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71737f219c8SBruno Larsen (billionai) } 71837f219c8SBruno Larsen (billionai) 719a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 72037f219c8SBruno Larsen (billionai) { 7217058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 72237f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 72337f219c8SBruno Larsen (billionai) } 72437f219c8SBruno Larsen (billionai) 725a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 72637f219c8SBruno Larsen (billionai) { 7277058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 72837f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 72937f219c8SBruno Larsen (billionai) } 73037f219c8SBruno Larsen (billionai) 731a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 73237f219c8SBruno Larsen (billionai) { 7337058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 73437f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 73537f219c8SBruno Larsen (billionai) } 73637f219c8SBruno Larsen (billionai) 73737f219c8SBruno Larsen (billionai) /* SDR1 */ 738a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 73937f219c8SBruno Larsen (billionai) { 74037f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 74137f219c8SBruno Larsen (billionai) } 74237f219c8SBruno Larsen (billionai) 74337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 74437f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 74537f219c8SBruno Larsen (billionai) /* PIDR */ 746a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 74737f219c8SBruno Larsen (billionai) { 74837f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 74937f219c8SBruno Larsen (billionai) } 75037f219c8SBruno Larsen (billionai) 751a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 75237f219c8SBruno Larsen (billionai) { 75337f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 75437f219c8SBruno Larsen (billionai) } 75537f219c8SBruno Larsen (billionai) 756a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 75737f219c8SBruno Larsen (billionai) { 75837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 75937f219c8SBruno Larsen (billionai) } 76037f219c8SBruno Larsen (billionai) 761a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 76237f219c8SBruno Larsen (billionai) { 76337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 76437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 76537f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 76637f219c8SBruno Larsen (billionai) } 767a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 76837f219c8SBruno Larsen (billionai) { 76937f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 77037f219c8SBruno Larsen (billionai) } 77137f219c8SBruno Larsen (billionai) 772a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 77337f219c8SBruno Larsen (billionai) { 77437f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 77537f219c8SBruno Larsen (billionai) } 77637f219c8SBruno Larsen (billionai) 77737f219c8SBruno Larsen (billionai) /* DPDES */ 778a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 77937f219c8SBruno Larsen (billionai) { 78037f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 78137f219c8SBruno Larsen (billionai) } 78237f219c8SBruno Larsen (billionai) 783a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 78437f219c8SBruno Larsen (billionai) { 78537f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 78637f219c8SBruno Larsen (billionai) } 78737f219c8SBruno Larsen (billionai) #endif 78837f219c8SBruno Larsen (billionai) #endif 78937f219c8SBruno Larsen (billionai) 79037f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 79137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 792a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 79337f219c8SBruno Larsen (billionai) { 794f5b6daacSRichard Henderson gen_icount_io_start(ctx); 79537f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 79637f219c8SBruno Larsen (billionai) } 79737f219c8SBruno Larsen (billionai) 798a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 79937f219c8SBruno Larsen (billionai) { 800f5b6daacSRichard Henderson gen_icount_io_start(ctx); 80137f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 80237f219c8SBruno Larsen (billionai) } 80337f219c8SBruno Larsen (billionai) 804a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 80537f219c8SBruno Larsen (billionai) { 806f5b6daacSRichard Henderson gen_icount_io_start(ctx); 80737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 80837f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 80937f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 810d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 81137f219c8SBruno Larsen (billionai) } 81237f219c8SBruno Larsen (billionai) 813a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 81437f219c8SBruno Larsen (billionai) { 815f5b6daacSRichard Henderson gen_icount_io_start(ctx); 81637f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 81737f219c8SBruno Larsen (billionai) } 81837f219c8SBruno Larsen (billionai) 819cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 820cbd8f17dSCédric Le Goater { 821cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 822cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 823cbd8f17dSCédric Le Goater } 824cbd8f17dSCédric Le Goater 825cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 826cbd8f17dSCédric Le Goater { 827cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 828cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 829cbd8f17dSCédric Le Goater } 830cbd8f17dSCédric Le Goater 831dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 832dd69d140SCédric Le Goater { 833dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 834dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 83547822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 836dd69d140SCédric Le Goater } 837dd69d140SCédric Le Goater 838a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 83937f219c8SBruno Larsen (billionai) { 840f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84137f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 84237f219c8SBruno Larsen (billionai) } 84337f219c8SBruno Larsen (billionai) 844a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 84537f219c8SBruno Larsen (billionai) { 846f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84737f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 84837f219c8SBruno Larsen (billionai) } 84937f219c8SBruno Larsen (billionai) #endif 85037f219c8SBruno Larsen (billionai) 851328c95fcSCédric Le Goater /* PIR */ 85237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 853a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 85437f219c8SBruno Larsen (billionai) { 85537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 85637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 85737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 85837f219c8SBruno Larsen (billionai) } 85937f219c8SBruno Larsen (billionai) #endif 86037f219c8SBruno Larsen (billionai) 86137f219c8SBruno Larsen (billionai) /* SPE specific registers */ 862a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 86337f219c8SBruno Larsen (billionai) { 86437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 86537f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 86637f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 86737f219c8SBruno Larsen (billionai) } 86837f219c8SBruno Larsen (billionai) 869a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 87037f219c8SBruno Larsen (billionai) { 87137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 87237f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 87337f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 87437f219c8SBruno Larsen (billionai) } 87537f219c8SBruno Larsen (billionai) 87637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 87737f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 878a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 87937f219c8SBruno Larsen (billionai) { 88037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 88137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 88237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 88337f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 88437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 88537f219c8SBruno Larsen (billionai) } 88637f219c8SBruno Larsen (billionai) 887a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 88837f219c8SBruno Larsen (billionai) { 88937f219c8SBruno Larsen (billionai) int sprn_offs; 89037f219c8SBruno Larsen (billionai) 89137f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 89237f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 89337f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 89437f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 89537f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 89637f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 89737f219c8SBruno Larsen (billionai) } else { 8988e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 8998e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9008e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 90137f219c8SBruno Larsen (billionai) return; 90237f219c8SBruno Larsen (billionai) } 90337f219c8SBruno Larsen (billionai) 90437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 90537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 90637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 90737f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 90837f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 90937f219c8SBruno Larsen (billionai) } 91037f219c8SBruno Larsen (billionai) #endif 91137f219c8SBruno Larsen (billionai) 91237f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 91337f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 914a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 91537f219c8SBruno Larsen (billionai) { 91637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 91737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 91837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 91937f219c8SBruno Larsen (billionai) 92037f219c8SBruno Larsen (billionai) /* 92137f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 92237f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 92337f219c8SBruno Larsen (billionai) */ 92437f219c8SBruno Larsen (billionai) 92537f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 92637f219c8SBruno Larsen (billionai) if (ctx->pr) { 92737f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 92837f219c8SBruno Larsen (billionai) } else { 92937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 93037f219c8SBruno Larsen (billionai) } 93137f219c8SBruno Larsen (billionai) 93237f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 93337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 93437f219c8SBruno Larsen (billionai) 93537f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 93637f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 93737f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 93837f219c8SBruno Larsen (billionai) 93937f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 94037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 94137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 94237f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 94337f219c8SBruno Larsen (billionai) } 94437f219c8SBruno Larsen (billionai) 945a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 94637f219c8SBruno Larsen (billionai) { 94737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 94837f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 94937f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 95037f219c8SBruno Larsen (billionai) 95137f219c8SBruno Larsen (billionai) /* 95237f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 95337f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 95437f219c8SBruno Larsen (billionai) */ 95537f219c8SBruno Larsen (billionai) 95637f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 95737f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 95837f219c8SBruno Larsen (billionai) 95937f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 96037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 96137f219c8SBruno Larsen (billionai) 96237f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 96337f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 96437f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 96537f219c8SBruno Larsen (billionai) 96637f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 96737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 96837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 96937f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 97037f219c8SBruno Larsen (billionai) } 97137f219c8SBruno Larsen (billionai) 972a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 97337f219c8SBruno Larsen (billionai) { 97437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 97537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 97637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 97737f219c8SBruno Larsen (billionai) 97837f219c8SBruno Larsen (billionai) /* 97937f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 98037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 98137f219c8SBruno Larsen (billionai) */ 98237f219c8SBruno Larsen (billionai) 98337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 98437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 98537f219c8SBruno Larsen (billionai) 98637f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98837f219c8SBruno Larsen (billionai) 98937f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 99037f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 99137f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 99237f219c8SBruno Larsen (billionai) 99337f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 99437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 99537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 99637f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 99737f219c8SBruno Larsen (billionai) } 99837f219c8SBruno Larsen (billionai) #endif 99937f219c8SBruno Larsen (billionai) #endif 100037f219c8SBruno Larsen (billionai) 100137f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1002a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 100337f219c8SBruno Larsen (billionai) { 100437f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 100537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 100637f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 100737f219c8SBruno Larsen (billionai) } 100837f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 100937f219c8SBruno Larsen (billionai) 101037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1011a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 101237f219c8SBruno Larsen (billionai) { 101337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 101437f219c8SBruno Larsen (billionai) 101537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 101637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 101737f219c8SBruno Larsen (billionai) } 101837f219c8SBruno Larsen (billionai) 1019a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 102037f219c8SBruno Larsen (billionai) { 102137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 102237f219c8SBruno Larsen (billionai) 102337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 102437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 102537f219c8SBruno Larsen (billionai) } 102637f219c8SBruno Larsen (billionai) 1027a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 102837f219c8SBruno Larsen (billionai) { 102937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103037f219c8SBruno Larsen (billionai) 103137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 103237f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 103337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 103437f219c8SBruno Larsen (billionai) } 103537f219c8SBruno Larsen (billionai) 1036a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 103737f219c8SBruno Larsen (billionai) { 103837f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 103937f219c8SBruno Larsen (billionai) } 104037f219c8SBruno Larsen (billionai) 1041a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 104237f219c8SBruno Larsen (billionai) { 10437058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 104437f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 104537f219c8SBruno Larsen (billionai) } 10467058ff52SRichard Henderson 1047a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 104837f219c8SBruno Larsen (billionai) { 104937f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 105037f219c8SBruno Larsen (billionai) } 10517058ff52SRichard Henderson 1052a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 105337f219c8SBruno Larsen (billionai) { 105437f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 105537f219c8SBruno Larsen (billionai) } 105637f219c8SBruno Larsen (billionai) 105737f219c8SBruno Larsen (billionai) #endif 105837f219c8SBruno Larsen (billionai) 105937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1060a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 106137f219c8SBruno Larsen (billionai) { 106237f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 106337f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 106437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 106537f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 106637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 106737f219c8SBruno Larsen (billionai) } 106837f219c8SBruno Larsen (billionai) 1069a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 107037f219c8SBruno Larsen (billionai) { 107137f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 107237f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 107337f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 107437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 107537f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 107637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 107737f219c8SBruno Larsen (billionai) } 107837f219c8SBruno Larsen (billionai) 107937f219c8SBruno Larsen (billionai) #endif 108037f219c8SBruno Larsen (billionai) 108137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 108237f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 108337f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 108437f219c8SBruno Larsen (billionai) { 10857058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 10867058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 10877058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 108837f219c8SBruno Larsen (billionai) 108937f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 109037f219c8SBruno Larsen (billionai) } 109137f219c8SBruno Larsen (billionai) 109237f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 109337f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 109437f219c8SBruno Larsen (billionai) { 10957058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 10967058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 10977058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 109837f219c8SBruno Larsen (billionai) 109937f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 110037f219c8SBruno Larsen (billionai) } 110137f219c8SBruno Larsen (billionai) 1102a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 110337f219c8SBruno Larsen (billionai) { 110437f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 110537f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 110637f219c8SBruno Larsen (billionai) 110737f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 110837f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 110937f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 111037f219c8SBruno Larsen (billionai) } 111137f219c8SBruno Larsen (billionai) 1112a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 111337f219c8SBruno Larsen (billionai) { 111437f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 111537f219c8SBruno Larsen (billionai) 111637f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 111737f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 111837f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 111937f219c8SBruno Larsen (billionai) } 112037f219c8SBruno Larsen (billionai) 112137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1122a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 112337f219c8SBruno Larsen (billionai) { 112437f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 112537f219c8SBruno Larsen (billionai) 112637f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 112737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 112837f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 112937f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 113037f219c8SBruno Larsen (billionai) } 113137f219c8SBruno Larsen (billionai) 1132a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 113337f219c8SBruno Larsen (billionai) { 113437f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 113537f219c8SBruno Larsen (billionai) } 113637f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 113737f219c8SBruno Larsen (billionai) 1138a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 113937f219c8SBruno Larsen (billionai) { 114037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 114137f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 114237f219c8SBruno Larsen (billionai) } 114337f219c8SBruno Larsen (billionai) 1144a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 114537f219c8SBruno Larsen (billionai) { 114637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 114737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 114837f219c8SBruno Larsen (billionai) } 114937f219c8SBruno Larsen (billionai) 1150a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 115137f219c8SBruno Larsen (billionai) { 115237f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 115337f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 115437f219c8SBruno Larsen (billionai) } 115537f219c8SBruno Larsen (billionai) 1156a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 115737f219c8SBruno Larsen (billionai) { 115837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 115937f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 116037f219c8SBruno Larsen (billionai) } 116137f219c8SBruno Larsen (billionai) 1162a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 116337f219c8SBruno Larsen (billionai) { 116437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 116537f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 116637f219c8SBruno Larsen (billionai) } 116737f219c8SBruno Larsen (billionai) 1168a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 116937f219c8SBruno Larsen (billionai) { 117037f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 117137f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 117237f219c8SBruno Larsen (billionai) } 117337f219c8SBruno Larsen (billionai) 1174a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 117537f219c8SBruno Larsen (billionai) { 117637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 117737f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 117837f219c8SBruno Larsen (billionai) } 117937f219c8SBruno Larsen (billionai) 1180a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 118137f219c8SBruno Larsen (billionai) { 118237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 118337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 118437f219c8SBruno Larsen (billionai) } 118537f219c8SBruno Larsen (billionai) 1186a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 118737f219c8SBruno Larsen (billionai) { 118837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 118937f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 119037f219c8SBruno Larsen (billionai) } 119137f219c8SBruno Larsen (billionai) 1192a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 119337f219c8SBruno Larsen (billionai) { 119437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 119537f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 119637f219c8SBruno Larsen (billionai) } 1197395b5d5bSNicholas Miehlbradt 1198395b5d5bSNicholas Miehlbradt void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1199395b5d5bSNicholas Miehlbradt { 1200395b5d5bSNicholas Miehlbradt TCGv t0 = tcg_temp_new(); 1201395b5d5bSNicholas Miehlbradt 1202395b5d5bSNicholas Miehlbradt /* 1203395b5d5bSNicholas Miehlbradt * Access to the (H)DEXCR in problem state is done using separated 1204395b5d5bSNicholas Miehlbradt * SPR indexes which are 16 below the SPR indexes which have full 1205395b5d5bSNicholas Miehlbradt * access to the (H)DEXCR in privileged state. Problem state can 1206395b5d5bSNicholas Miehlbradt * only read bits 32:63, bits 0:31 return 0. 1207395b5d5bSNicholas Miehlbradt * 1208395b5d5bSNicholas Miehlbradt * See section 9.3.1-9.3.2 of PowerISA v3.1B 1209395b5d5bSNicholas Miehlbradt */ 1210395b5d5bSNicholas Miehlbradt 1211395b5d5bSNicholas Miehlbradt gen_load_spr(t0, sprn + 16); 1212395b5d5bSNicholas Miehlbradt tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1213395b5d5bSNicholas Miehlbradt } 121437f219c8SBruno Larsen (billionai) #endif 121537f219c8SBruno Larsen (billionai) 1216fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1217fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1218fcf5ef2aSThomas Huth 1219fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1220fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1221fcf5ef2aSThomas Huth 1222fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1223fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1224fcf5ef2aSThomas Huth 1225fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1226fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1227fcf5ef2aSThomas Huth 1228fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1229fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1230fcf5ef2aSThomas Huth 1231fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1232fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1233fcf5ef2aSThomas Huth 1234fcf5ef2aSThomas Huth typedef struct opcode_t { 1235fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1236fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1237fcf5ef2aSThomas Huth unsigned char pad[4]; 1238fcf5ef2aSThomas Huth #endif 1239fcf5ef2aSThomas Huth opc_handler_t handler; 1240fcf5ef2aSThomas Huth const char *oname; 1241fcf5ef2aSThomas Huth } opcode_t; 1242fcf5ef2aSThomas Huth 12439f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 12449f0cf041SMatheus Ferst { 12459f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 12469f0cf041SMatheus Ferst } 12479f0cf041SMatheus Ferst 1248fcf5ef2aSThomas Huth /* Helpers for priv. check */ 12499f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1250fcf5ef2aSThomas Huth do { \ 12519f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1252fcf5ef2aSThomas Huth } while (0) 1253fcf5ef2aSThomas Huth 1254fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 12559f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 12569f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 12579f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1258fcf5ef2aSThomas Huth #else 12599f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1260fcf5ef2aSThomas Huth do { \ 1261fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 12629f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1263fcf5ef2aSThomas Huth } \ 1264fcf5ef2aSThomas Huth } while (0) 12659f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1266fcf5ef2aSThomas Huth do { \ 1267fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 12689f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1269fcf5ef2aSThomas Huth } \ 1270fcf5ef2aSThomas Huth } while (0) 12719f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1272fcf5ef2aSThomas Huth do { \ 1273fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 12749f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1275fcf5ef2aSThomas Huth } \ 1276fcf5ef2aSThomas Huth } while (0) 1277fcf5ef2aSThomas Huth #endif 1278fcf5ef2aSThomas Huth 12799f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1280fcf5ef2aSThomas Huth 1281fcf5ef2aSThomas Huth /*****************************************************************************/ 1282fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1283fcf5ef2aSThomas Huth 1284fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1285fcf5ef2aSThomas Huth { \ 1286fcf5ef2aSThomas Huth .opc1 = op1, \ 1287fcf5ef2aSThomas Huth .opc2 = op2, \ 1288fcf5ef2aSThomas Huth .opc3 = op3, \ 1289fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1290fcf5ef2aSThomas Huth .handler = { \ 1291fcf5ef2aSThomas Huth .inval1 = invl, \ 1292fcf5ef2aSThomas Huth .type = _typ, \ 1293fcf5ef2aSThomas Huth .type2 = _typ2, \ 1294fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1295fcf5ef2aSThomas Huth }, \ 1296fcf5ef2aSThomas Huth .oname = stringify(name), \ 1297fcf5ef2aSThomas Huth } 1298fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1299fcf5ef2aSThomas Huth { \ 1300fcf5ef2aSThomas Huth .opc1 = op1, \ 1301fcf5ef2aSThomas Huth .opc2 = op2, \ 1302fcf5ef2aSThomas Huth .opc3 = op3, \ 1303fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1304fcf5ef2aSThomas Huth .handler = { \ 1305fcf5ef2aSThomas Huth .inval1 = invl1, \ 1306fcf5ef2aSThomas Huth .inval2 = invl2, \ 1307fcf5ef2aSThomas Huth .type = _typ, \ 1308fcf5ef2aSThomas Huth .type2 = _typ2, \ 1309fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1310fcf5ef2aSThomas Huth }, \ 1311fcf5ef2aSThomas Huth .oname = stringify(name), \ 1312fcf5ef2aSThomas Huth } 1313fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1314fcf5ef2aSThomas Huth { \ 1315fcf5ef2aSThomas Huth .opc1 = op1, \ 1316fcf5ef2aSThomas Huth .opc2 = op2, \ 1317fcf5ef2aSThomas Huth .opc3 = op3, \ 1318fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1319fcf5ef2aSThomas Huth .handler = { \ 1320fcf5ef2aSThomas Huth .inval1 = invl, \ 1321fcf5ef2aSThomas Huth .type = _typ, \ 1322fcf5ef2aSThomas Huth .type2 = _typ2, \ 1323fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1324fcf5ef2aSThomas Huth }, \ 1325fcf5ef2aSThomas Huth .oname = onam, \ 1326fcf5ef2aSThomas Huth } 1327fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1328fcf5ef2aSThomas Huth { \ 1329fcf5ef2aSThomas Huth .opc1 = op1, \ 1330fcf5ef2aSThomas Huth .opc2 = op2, \ 1331fcf5ef2aSThomas Huth .opc3 = op3, \ 1332fcf5ef2aSThomas Huth .opc4 = op4, \ 1333fcf5ef2aSThomas Huth .handler = { \ 1334fcf5ef2aSThomas Huth .inval1 = invl, \ 1335fcf5ef2aSThomas Huth .type = _typ, \ 1336fcf5ef2aSThomas Huth .type2 = _typ2, \ 1337fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1338fcf5ef2aSThomas Huth }, \ 1339fcf5ef2aSThomas Huth .oname = stringify(name), \ 1340fcf5ef2aSThomas Huth } 1341fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1342fcf5ef2aSThomas Huth { \ 1343fcf5ef2aSThomas Huth .opc1 = op1, \ 1344fcf5ef2aSThomas Huth .opc2 = op2, \ 1345fcf5ef2aSThomas Huth .opc3 = op3, \ 1346fcf5ef2aSThomas Huth .opc4 = op4, \ 1347fcf5ef2aSThomas Huth .handler = { \ 1348fcf5ef2aSThomas Huth .inval1 = invl, \ 1349fcf5ef2aSThomas Huth .type = _typ, \ 1350fcf5ef2aSThomas Huth .type2 = _typ2, \ 1351fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1352fcf5ef2aSThomas Huth }, \ 1353fcf5ef2aSThomas Huth .oname = onam, \ 1354fcf5ef2aSThomas Huth } 1355fcf5ef2aSThomas Huth 1356fcf5ef2aSThomas Huth /* Invalid instruction */ 1357fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1358fcf5ef2aSThomas Huth { 1359fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1360fcf5ef2aSThomas Huth } 1361fcf5ef2aSThomas Huth 1362fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1363fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1364fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1365fcf5ef2aSThomas Huth .type = PPC_NONE, 1366fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1367fcf5ef2aSThomas Huth .handler = gen_invalid, 1368fcf5ef2aSThomas Huth }; 1369fcf5ef2aSThomas Huth 1370fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1371fcf5ef2aSThomas Huth 1372fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1373fcf5ef2aSThomas Huth { 1374fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1375b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1376b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1377fcf5ef2aSThomas Huth 1378b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1379b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1380efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1381efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1382b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1383efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1384efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1385b62b3686Spbonzini@redhat.com 1386b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1387fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1388b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1389fcf5ef2aSThomas Huth } 1390fcf5ef2aSThomas Huth 1391fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1392fcf5ef2aSThomas Huth { 13937058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1394fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1395fcf5ef2aSThomas Huth } 1396fcf5ef2aSThomas Huth 1397fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1398fcf5ef2aSThomas Huth { 1399fcf5ef2aSThomas Huth TCGv t0, t1; 1400fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1401fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1402fcf5ef2aSThomas Huth if (s) { 1403fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1404fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1405fcf5ef2aSThomas Huth } else { 1406fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1407fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1408fcf5ef2aSThomas Huth } 1409fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1410fcf5ef2aSThomas Huth } 1411fcf5ef2aSThomas Huth 1412fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1413fcf5ef2aSThomas Huth { 14147058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1415fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1416fcf5ef2aSThomas Huth } 1417fcf5ef2aSThomas Huth 1418fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1419fcf5ef2aSThomas Huth { 1420fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1421fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1422fcf5ef2aSThomas Huth } else { 1423fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1424fcf5ef2aSThomas Huth } 1425fcf5ef2aSThomas Huth } 1426fcf5ef2aSThomas Huth 1427fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1428fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1429fcf5ef2aSThomas Huth { 1430fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1431fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1432fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1433fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1434fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1435fcf5ef2aSThomas Huth 1436fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1437fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1438fcf5ef2aSThomas Huth 1439fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1440fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1441fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1442fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1443fcf5ef2aSThomas Huth 1444fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1445fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1446fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1447fcf5ef2aSThomas Huth 1448fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1449fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1450fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1451fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1452fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1453fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1454fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1455fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1456fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1457fcf5ef2aSThomas Huth } 1458efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1459fcf5ef2aSThomas Huth } 1460fcf5ef2aSThomas Huth 1461fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1462fcf5ef2aSThomas Huth /* cmpeqb */ 1463fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1464fcf5ef2aSThomas Huth { 1465fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1466fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1467fcf5ef2aSThomas Huth } 1468fcf5ef2aSThomas Huth #endif 1469fcf5ef2aSThomas Huth 1470fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1471fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1472fcf5ef2aSThomas Huth { 1473fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1474fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1475fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1476fcf5ef2aSThomas Huth TCGv zr; 1477fcf5ef2aSThomas Huth 1478fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1479fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1480fcf5ef2aSThomas Huth 14817058ff52SRichard Henderson zr = tcg_constant_tl(0); 1482fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1483fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1484fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1485fcf5ef2aSThomas Huth } 1486fcf5ef2aSThomas Huth 1487fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1488fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1489fcf5ef2aSThomas Huth { 1490fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1491fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1492fcf5ef2aSThomas Huth } 1493fcf5ef2aSThomas Huth 1494fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1495fcf5ef2aSThomas Huth 1496fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1497fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1498fcf5ef2aSThomas Huth { 1499fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1500fcf5ef2aSThomas Huth 1501fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1502fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1503fcf5ef2aSThomas Huth if (sub) { 1504fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1505fcf5ef2aSThomas Huth } else { 1506fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1507fcf5ef2aSThomas Huth } 1508fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1509dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1510dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1511dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1512fcf5ef2aSThomas Huth } 1513dc0ad844SNikunj A Dadhania } else { 1514dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1515dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1516dc0ad844SNikunj A Dadhania } 151738a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1518dc0ad844SNikunj A Dadhania } 1519fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1520fcf5ef2aSThomas Huth } 1521fcf5ef2aSThomas Huth 15226b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15236b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15244c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15256b10d008SNikunj A Dadhania { 15266b10d008SNikunj A Dadhania TCGv t0; 15276b10d008SNikunj A Dadhania 15286b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 15296b10d008SNikunj A Dadhania return; 15306b10d008SNikunj A Dadhania } 15316b10d008SNikunj A Dadhania 15326b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 153333903d0aSNikunj A Dadhania if (sub) { 153433903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 153533903d0aSNikunj A Dadhania } else { 15366b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 153733903d0aSNikunj A Dadhania } 15386b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 15394c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 15406b10d008SNikunj A Dadhania } 15416b10d008SNikunj A Dadhania 1542fcf5ef2aSThomas Huth /* Common add function */ 1543fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 15444c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 15454c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1546fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1547fcf5ef2aSThomas Huth { 1548fcf5ef2aSThomas Huth TCGv t0 = ret; 1549fcf5ef2aSThomas Huth 1550fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1551fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1552fcf5ef2aSThomas Huth } 1553fcf5ef2aSThomas Huth 1554fcf5ef2aSThomas Huth if (compute_ca) { 1555fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1556efe843d8SDavid Gibson /* 1557efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1558efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1559efe843d8SDavid Gibson * produce the carry into bit 32. 1560efe843d8SDavid Gibson */ 1561fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1562fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1563fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1564fcf5ef2aSThomas Huth if (add_ca) { 15654c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1566fcf5ef2aSThomas Huth } 15674c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 15684c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 15696b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 15704c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 15716b10d008SNikunj A Dadhania } 1572fcf5ef2aSThomas Huth } else { 15737058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 1574fcf5ef2aSThomas Huth if (add_ca) { 15754c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 15764c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1577fcf5ef2aSThomas Huth } else { 15784c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1579fcf5ef2aSThomas Huth } 15804c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1581fcf5ef2aSThomas Huth } 1582fcf5ef2aSThomas Huth } else { 1583fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1584fcf5ef2aSThomas Huth if (add_ca) { 15854c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1586fcf5ef2aSThomas Huth } 1587fcf5ef2aSThomas Huth } 1588fcf5ef2aSThomas Huth 1589fcf5ef2aSThomas Huth if (compute_ov) { 1590fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1591fcf5ef2aSThomas Huth } 1592fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1593fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1594fcf5ef2aSThomas Huth } 1595fcf5ef2aSThomas Huth 159611f4e8f8SRichard Henderson if (t0 != ret) { 1597fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1598fcf5ef2aSThomas Huth } 1599fcf5ef2aSThomas Huth } 1600fcf5ef2aSThomas Huth /* Add functions with two operands */ 16014c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1602fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1603fcf5ef2aSThomas Huth { \ 1604fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1605fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16064c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1607fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1608fcf5ef2aSThomas Huth } 1609fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16104c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1611fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1612fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1613fcf5ef2aSThomas Huth { \ 16147058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 1615fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1616fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16174c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1618fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1619fcf5ef2aSThomas Huth } 1620fcf5ef2aSThomas Huth 1621fcf5ef2aSThomas Huth /* add add. addo addo. */ 16224c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 16234c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1624fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 16254c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 16264c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1627fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 16284c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 16294c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1630fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 16314c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 16324c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 16334c5920afSSuraj Jitindar Singh /* addex */ 16344c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1635fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 16364c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 16374c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1638fcf5ef2aSThomas Huth /* addic addic.*/ 1639fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1640fcf5ef2aSThomas Huth { 16417058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1642fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 16434c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1644fcf5ef2aSThomas Huth } 1645fcf5ef2aSThomas Huth 1646fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1647fcf5ef2aSThomas Huth { 1648fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1649fcf5ef2aSThomas Huth } 1650fcf5ef2aSThomas Huth 1651fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1652fcf5ef2aSThomas Huth { 1653fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1654fcf5ef2aSThomas Huth } 1655fcf5ef2aSThomas Huth 1656fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1657fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1658fcf5ef2aSThomas Huth { 1659fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1660fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1661fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1662fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1663fcf5ef2aSThomas Huth 1664fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1665fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1666fcf5ef2aSThomas Huth if (sign) { 1667fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1668fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1669fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1670fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1671fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1672fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1673fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1674fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1675fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1676fcf5ef2aSThomas Huth } else { 1677fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1678fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1679fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1680fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1681fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1682fcf5ef2aSThomas Huth } 1683fcf5ef2aSThomas Huth if (compute_ov) { 1684fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1685c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1686c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1687c44027ffSNikunj A Dadhania } 1688fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1689fcf5ef2aSThomas Huth } 1690fcf5ef2aSThomas Huth 1691efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1692fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1693fcf5ef2aSThomas Huth } 1694efe843d8SDavid Gibson } 1695fcf5ef2aSThomas Huth /* Div functions */ 1696fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1697fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1698fcf5ef2aSThomas Huth { \ 1699fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1700fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1701fcf5ef2aSThomas Huth sign, compute_ov); \ 1702fcf5ef2aSThomas Huth } 1703fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1704fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1705fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1706fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1707fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1708fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1709fcf5ef2aSThomas Huth 1710fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1711fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1712fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1713fcf5ef2aSThomas Huth { \ 17147058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1715fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1716fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1717fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1718fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1719fcf5ef2aSThomas Huth } \ 1720fcf5ef2aSThomas Huth } 1721fcf5ef2aSThomas Huth 1722fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1723fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1724fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1725fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1726fcf5ef2aSThomas Huth 1727fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1728fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1729fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1730fcf5ef2aSThomas Huth { 1731fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1732fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1733fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1734fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1735fcf5ef2aSThomas Huth 1736fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1737fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1738fcf5ef2aSThomas Huth if (sign) { 1739fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1740fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1741fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1742fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1743fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1744fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1745fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1746fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1747fcf5ef2aSThomas Huth } else { 1748fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1749fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1750fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1751fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1752fcf5ef2aSThomas Huth } 1753fcf5ef2aSThomas Huth if (compute_ov) { 1754fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1755c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1756c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1757c44027ffSNikunj A Dadhania } 1758fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1759fcf5ef2aSThomas Huth } 1760fcf5ef2aSThomas Huth 1761efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1762fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1763fcf5ef2aSThomas Huth } 1764efe843d8SDavid Gibson } 1765fcf5ef2aSThomas Huth 1766fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1767fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1768fcf5ef2aSThomas Huth { \ 1769fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1770fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1771fcf5ef2aSThomas Huth sign, compute_ov); \ 1772fcf5ef2aSThomas Huth } 1773c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1774fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1775fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1776c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1777fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1778fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1779fcf5ef2aSThomas Huth 1780fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1781fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1782fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1783fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1784fcf5ef2aSThomas Huth #endif 1785fcf5ef2aSThomas Huth 1786fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1787fcf5ef2aSThomas Huth TCGv arg2, int sign) 1788fcf5ef2aSThomas Huth { 1789fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1790fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1791fcf5ef2aSThomas Huth 1792fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1793fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1794fcf5ef2aSThomas Huth if (sign) { 1795fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1796fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1797fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1798fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1799fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1800fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1801fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1802fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1803fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1804fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1805fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1806fcf5ef2aSThomas Huth } else { 18077058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(1); 18087058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(0); 1809fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1810a253231fSRichard Henderson tcg_gen_remu_i32(t0, t0, t1); 1811a253231fSRichard Henderson tcg_gen_extu_i32_tl(ret, t0); 1812fcf5ef2aSThomas Huth } 1813fcf5ef2aSThomas Huth } 1814fcf5ef2aSThomas Huth 1815fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1816fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1817fcf5ef2aSThomas Huth { \ 1818fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1819fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1820fcf5ef2aSThomas Huth sign); \ 1821fcf5ef2aSThomas Huth } 1822fcf5ef2aSThomas Huth 1823fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1824fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1825fcf5ef2aSThomas Huth 1826fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1827fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1828fcf5ef2aSThomas Huth TCGv arg2, int sign) 1829fcf5ef2aSThomas Huth { 1830fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1831fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1832fcf5ef2aSThomas Huth 1833fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1834fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1835fcf5ef2aSThomas Huth if (sign) { 1836fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1837fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1838fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1839fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1840fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1841fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1842fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1843fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1844fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1845fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1846fcf5ef2aSThomas Huth } else { 18477058ff52SRichard Henderson TCGv_i64 t2 = tcg_constant_i64(1); 18487058ff52SRichard Henderson TCGv_i64 t3 = tcg_constant_i64(0); 1849fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1850fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1851fcf5ef2aSThomas Huth } 1852fcf5ef2aSThomas Huth } 1853fcf5ef2aSThomas Huth 1854fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1855fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1856fcf5ef2aSThomas Huth { \ 1857fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1858fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1859fcf5ef2aSThomas Huth sign); \ 1860fcf5ef2aSThomas Huth } 1861fcf5ef2aSThomas Huth 1862fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1863fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1864fcf5ef2aSThomas Huth #endif 1865fcf5ef2aSThomas Huth 1866fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1867fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1868fcf5ef2aSThomas Huth { 1869fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1870fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1871fcf5ef2aSThomas Huth 1872fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1873fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1874fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1875fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1876efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1877fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1878fcf5ef2aSThomas Huth } 1879efe843d8SDavid Gibson } 1880fcf5ef2aSThomas Huth 1881fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1882fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1883fcf5ef2aSThomas Huth { 1884fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1885fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1886fcf5ef2aSThomas Huth 1887fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1888fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1889fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1890fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1891efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1892fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1893fcf5ef2aSThomas Huth } 1894efe843d8SDavid Gibson } 1895fcf5ef2aSThomas Huth 1896fcf5ef2aSThomas Huth /* mullw mullw. */ 1897fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1898fcf5ef2aSThomas Huth { 1899fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1900fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1901fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1902fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1903fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1904fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1905fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1906fcf5ef2aSThomas Huth #else 1907fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1908fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1909fcf5ef2aSThomas Huth #endif 1910efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1911fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1912fcf5ef2aSThomas Huth } 1913efe843d8SDavid Gibson } 1914fcf5ef2aSThomas Huth 1915fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1916fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1917fcf5ef2aSThomas Huth { 1918fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1919fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1920fcf5ef2aSThomas Huth 1921fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1922fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1923fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1924fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1925fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1926fcf5ef2aSThomas Huth #else 1927fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1928fcf5ef2aSThomas Huth #endif 1929fcf5ef2aSThomas Huth 1930fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1931fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1932fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 193361aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 193461aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 193561aa9a69SNikunj A Dadhania } 1936fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1937fcf5ef2aSThomas Huth 1938efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1939fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1940fcf5ef2aSThomas Huth } 1941efe843d8SDavid Gibson } 1942fcf5ef2aSThomas Huth 1943fcf5ef2aSThomas Huth /* mulli */ 1944fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1945fcf5ef2aSThomas Huth { 1946fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1947fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1948fcf5ef2aSThomas Huth } 1949fcf5ef2aSThomas Huth 1950fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1951fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1952fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1953fcf5ef2aSThomas Huth { 1954fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1955fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1956fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1957fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1958fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1959fcf5ef2aSThomas Huth } 1960fcf5ef2aSThomas Huth } 1961fcf5ef2aSThomas Huth 1962fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1963fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1964fcf5ef2aSThomas Huth { 1965fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1966fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1967fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1968fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1969fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1970fcf5ef2aSThomas Huth } 1971fcf5ef2aSThomas Huth } 1972fcf5ef2aSThomas Huth 1973fcf5ef2aSThomas Huth /* mulld mulld. */ 1974fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1975fcf5ef2aSThomas Huth { 1976fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1977fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1978efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1979fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1980fcf5ef2aSThomas Huth } 1981efe843d8SDavid Gibson } 1982fcf5ef2aSThomas Huth 1983fcf5ef2aSThomas Huth /* mulldo mulldo. */ 1984fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 1985fcf5ef2aSThomas Huth { 1986fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1987fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1988fcf5ef2aSThomas Huth 1989fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1990fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1991fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1992fcf5ef2aSThomas Huth 1993fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 1994fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 199561aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 199661aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 199761aa9a69SNikunj A Dadhania } 1998fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1999fcf5ef2aSThomas Huth 2000fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2001fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2002fcf5ef2aSThomas Huth } 2003fcf5ef2aSThomas Huth } 2004fcf5ef2aSThomas Huth #endif 2005fcf5ef2aSThomas Huth 2006fcf5ef2aSThomas Huth /* Common subf function */ 2007fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2008fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2009fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2010fcf5ef2aSThomas Huth { 2011fcf5ef2aSThomas Huth TCGv t0 = ret; 2012fcf5ef2aSThomas Huth 2013fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2014fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2015fcf5ef2aSThomas Huth } 2016fcf5ef2aSThomas Huth 2017fcf5ef2aSThomas Huth if (compute_ca) { 2018fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2019fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2020efe843d8SDavid Gibson /* 2021efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2022efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2023efe843d8SDavid Gibson * produce the carry into bit 32. 2024efe843d8SDavid Gibson */ 2025fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2026fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2027fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2028fcf5ef2aSThomas Huth if (add_ca) { 2029fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2030fcf5ef2aSThomas Huth } else { 2031fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2032fcf5ef2aSThomas Huth } 2033fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2034fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2035fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2036e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 203733903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 203833903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 203933903d0aSNikunj A Dadhania } 2040fcf5ef2aSThomas Huth } else if (add_ca) { 2041fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2042fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 20437058ff52SRichard Henderson zero = tcg_constant_tl(0); 2044fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2045fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 20464c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2047fcf5ef2aSThomas Huth } else { 2048fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2049fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 20504c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2051fcf5ef2aSThomas Huth } 2052fcf5ef2aSThomas Huth } else if (add_ca) { 2053efe843d8SDavid Gibson /* 2054efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2055efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2056efe843d8SDavid Gibson */ 2057fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2058fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2059fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2060fcf5ef2aSThomas Huth } else { 2061fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2062fcf5ef2aSThomas Huth } 2063fcf5ef2aSThomas Huth 2064fcf5ef2aSThomas Huth if (compute_ov) { 2065fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2066fcf5ef2aSThomas Huth } 2067fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2068fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2069fcf5ef2aSThomas Huth } 2070fcf5ef2aSThomas Huth 207111f4e8f8SRichard Henderson if (t0 != ret) { 2072fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2073fcf5ef2aSThomas Huth } 2074fcf5ef2aSThomas Huth } 2075fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2076fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2077fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2078fcf5ef2aSThomas Huth { \ 2079fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2080fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2081fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2082fcf5ef2aSThomas Huth } 2083fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2084fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2085fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2086fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2087fcf5ef2aSThomas Huth { \ 20887058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 2089fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2090fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2091fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2092fcf5ef2aSThomas Huth } 2093fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2094fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2095fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2096fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2097fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2098fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2099fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2100fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2101fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2102fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2103fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2104fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2105fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2106fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2107fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2108fcf5ef2aSThomas Huth 2109fcf5ef2aSThomas Huth /* subfic */ 2110fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2111fcf5ef2aSThomas Huth { 21127058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2113fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2114fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2115fcf5ef2aSThomas Huth } 2116fcf5ef2aSThomas Huth 2117fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2118fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2119fcf5ef2aSThomas Huth { 21207058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 2121fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2122fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2123fcf5ef2aSThomas Huth } 2124fcf5ef2aSThomas Huth 2125fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2126fcf5ef2aSThomas Huth { 21271480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 21281480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 21291480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 21301480d71cSNikunj A Dadhania } 2131fcf5ef2aSThomas Huth } 2132fcf5ef2aSThomas Huth 2133fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2134fcf5ef2aSThomas Huth { 2135fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2136fcf5ef2aSThomas Huth } 2137fcf5ef2aSThomas Huth 2138fcf5ef2aSThomas Huth /*** Integer logical ***/ 2139fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2140fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2141fcf5ef2aSThomas Huth { \ 2142fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2143fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2144fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2145fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2146fcf5ef2aSThomas Huth } 2147fcf5ef2aSThomas Huth 2148fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2149fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2150fcf5ef2aSThomas Huth { \ 2151fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2152fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2153fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2154fcf5ef2aSThomas Huth } 2155fcf5ef2aSThomas Huth 2156fcf5ef2aSThomas Huth /* and & and. */ 2157fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2158fcf5ef2aSThomas Huth /* andc & andc. */ 2159fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2160fcf5ef2aSThomas Huth 2161fcf5ef2aSThomas Huth /* andi. */ 2162fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2163fcf5ef2aSThomas Huth { 2164efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2165efe843d8SDavid Gibson UIMM(ctx->opcode)); 2166fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2167fcf5ef2aSThomas Huth } 2168fcf5ef2aSThomas Huth 2169fcf5ef2aSThomas Huth /* andis. */ 2170fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2171fcf5ef2aSThomas Huth { 2172efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2173efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2174fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2175fcf5ef2aSThomas Huth } 2176fcf5ef2aSThomas Huth 2177fcf5ef2aSThomas Huth /* cntlzw */ 2178fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2179fcf5ef2aSThomas Huth { 21809b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 21819b8514e5SRichard Henderson 21829b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 21839b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 21849b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 21859b8514e5SRichard Henderson 2186efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2187fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2188fcf5ef2aSThomas Huth } 2189efe843d8SDavid Gibson } 2190fcf5ef2aSThomas Huth 2191fcf5ef2aSThomas Huth /* cnttzw */ 2192fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2193fcf5ef2aSThomas Huth { 21949b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 21959b8514e5SRichard Henderson 21969b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 21979b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 21989b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 21999b8514e5SRichard Henderson 2200fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2201fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2202fcf5ef2aSThomas Huth } 2203fcf5ef2aSThomas Huth } 2204fcf5ef2aSThomas Huth 2205fcf5ef2aSThomas Huth /* eqv & eqv. */ 2206fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2207fcf5ef2aSThomas Huth /* extsb & extsb. */ 2208fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2209fcf5ef2aSThomas Huth /* extsh & extsh. */ 2210fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2211fcf5ef2aSThomas Huth /* nand & nand. */ 2212fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2213fcf5ef2aSThomas Huth /* nor & nor. */ 2214fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2215fcf5ef2aSThomas Huth 2216fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2217fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2218fcf5ef2aSThomas Huth { 22197058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(0); 2220fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2221fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2222fcf5ef2aSThomas Huth 2223fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2224b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2225fcf5ef2aSThomas Huth } 2226fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2227fcf5ef2aSThomas Huth 2228fcf5ef2aSThomas Huth /* or & or. */ 2229fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2230fcf5ef2aSThomas Huth { 2231fcf5ef2aSThomas Huth int rs, ra, rb; 2232fcf5ef2aSThomas Huth 2233fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2234fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2235fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2236fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2237fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2238efe843d8SDavid Gibson if (rs != rb) { 2239fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2240efe843d8SDavid Gibson } else { 2241fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2242efe843d8SDavid Gibson } 2243efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2244fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2245efe843d8SDavid Gibson } 2246fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2247fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2248fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2249fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2250fcf5ef2aSThomas Huth int prio = 0; 2251fcf5ef2aSThomas Huth 2252fcf5ef2aSThomas Huth switch (rs) { 2253fcf5ef2aSThomas Huth case 1: 2254fcf5ef2aSThomas Huth /* Set process priority to low */ 2255fcf5ef2aSThomas Huth prio = 2; 2256fcf5ef2aSThomas Huth break; 2257fcf5ef2aSThomas Huth case 6: 2258fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2259fcf5ef2aSThomas Huth prio = 3; 2260fcf5ef2aSThomas Huth break; 2261fcf5ef2aSThomas Huth case 2: 2262fcf5ef2aSThomas Huth /* Set process priority to normal */ 2263fcf5ef2aSThomas Huth prio = 4; 2264fcf5ef2aSThomas Huth break; 2265fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2266fcf5ef2aSThomas Huth case 31: 2267fcf5ef2aSThomas Huth if (!ctx->pr) { 2268fcf5ef2aSThomas Huth /* Set process priority to very low */ 2269fcf5ef2aSThomas Huth prio = 1; 2270fcf5ef2aSThomas Huth } 2271fcf5ef2aSThomas Huth break; 2272fcf5ef2aSThomas Huth case 5: 2273fcf5ef2aSThomas Huth if (!ctx->pr) { 2274fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2275fcf5ef2aSThomas Huth prio = 5; 2276fcf5ef2aSThomas Huth } 2277fcf5ef2aSThomas Huth break; 2278fcf5ef2aSThomas Huth case 3: 2279fcf5ef2aSThomas Huth if (!ctx->pr) { 2280fcf5ef2aSThomas Huth /* Set process priority to high */ 2281fcf5ef2aSThomas Huth prio = 6; 2282fcf5ef2aSThomas Huth } 2283fcf5ef2aSThomas Huth break; 2284fcf5ef2aSThomas Huth case 7: 2285fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2286fcf5ef2aSThomas Huth /* Set process priority to very high */ 2287fcf5ef2aSThomas Huth prio = 7; 2288fcf5ef2aSThomas Huth } 2289fcf5ef2aSThomas Huth break; 2290fcf5ef2aSThomas Huth #endif 2291fcf5ef2aSThomas Huth default: 2292fcf5ef2aSThomas Huth break; 2293fcf5ef2aSThomas Huth } 2294fcf5ef2aSThomas Huth if (prio) { 2295fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2296fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2297fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2298fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2299fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2300fcf5ef2aSThomas Huth } 2301fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2302efe843d8SDavid Gibson /* 2303efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2304efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2305efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2306efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2307fcf5ef2aSThomas Huth */ 2308fcf5ef2aSThomas Huth gen_pause(ctx); 2309fcf5ef2aSThomas Huth #endif 2310fcf5ef2aSThomas Huth #endif 2311fcf5ef2aSThomas Huth } 2312fcf5ef2aSThomas Huth } 2313fcf5ef2aSThomas Huth /* orc & orc. */ 2314fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2315fcf5ef2aSThomas Huth 2316fcf5ef2aSThomas Huth /* xor & xor. */ 2317fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2318fcf5ef2aSThomas Huth { 2319fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2320efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2321efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2322efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2323efe843d8SDavid Gibson } else { 2324fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2325efe843d8SDavid Gibson } 2326efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2327fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2328fcf5ef2aSThomas Huth } 2329efe843d8SDavid Gibson } 2330fcf5ef2aSThomas Huth 2331fcf5ef2aSThomas Huth /* ori */ 2332fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2333fcf5ef2aSThomas Huth { 2334fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2335fcf5ef2aSThomas Huth 2336fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2337fcf5ef2aSThomas Huth return; 2338fcf5ef2aSThomas Huth } 2339fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2340fcf5ef2aSThomas Huth } 2341fcf5ef2aSThomas Huth 2342fcf5ef2aSThomas Huth /* oris */ 2343fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2344fcf5ef2aSThomas Huth { 2345fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2346fcf5ef2aSThomas Huth 2347fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2348fcf5ef2aSThomas Huth /* NOP */ 2349fcf5ef2aSThomas Huth return; 2350fcf5ef2aSThomas Huth } 2351efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2352efe843d8SDavid Gibson uimm << 16); 2353fcf5ef2aSThomas Huth } 2354fcf5ef2aSThomas Huth 2355fcf5ef2aSThomas Huth /* xori */ 2356fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2357fcf5ef2aSThomas Huth { 2358fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2359fcf5ef2aSThomas Huth 2360fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2361fcf5ef2aSThomas Huth /* NOP */ 2362fcf5ef2aSThomas Huth return; 2363fcf5ef2aSThomas Huth } 2364fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2365fcf5ef2aSThomas Huth } 2366fcf5ef2aSThomas Huth 2367fcf5ef2aSThomas Huth /* xoris */ 2368fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2369fcf5ef2aSThomas Huth { 2370fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2371fcf5ef2aSThomas Huth 2372fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2373fcf5ef2aSThomas Huth /* NOP */ 2374fcf5ef2aSThomas Huth return; 2375fcf5ef2aSThomas Huth } 2376efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2377efe843d8SDavid Gibson uimm << 16); 2378fcf5ef2aSThomas Huth } 2379fcf5ef2aSThomas Huth 2380fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2381fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2382fcf5ef2aSThomas Huth { 2383fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2384fcf5ef2aSThomas Huth } 2385fcf5ef2aSThomas Huth 2386fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2387fcf5ef2aSThomas Huth { 238879770002SRichard Henderson #if defined(TARGET_PPC64) 2389fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 239079770002SRichard Henderson #else 239179770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 239279770002SRichard Henderson #endif 2393fcf5ef2aSThomas Huth } 2394fcf5ef2aSThomas Huth 2395fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2396fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2397fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2398fcf5ef2aSThomas Huth { 239979770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2400fcf5ef2aSThomas Huth } 2401fcf5ef2aSThomas Huth #endif 2402fcf5ef2aSThomas Huth 2403fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2404fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2405fcf5ef2aSThomas Huth { 2406fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2407fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2408fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2409fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2410fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2411fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2412fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2413fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2414fcf5ef2aSThomas Huth } 2415fcf5ef2aSThomas Huth 2416fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2417fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2418fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2419fcf5ef2aSThomas Huth { 2420fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2421fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2422fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2423fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2424fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2425fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2426fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2427fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2428fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2429fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2430fcf5ef2aSThomas Huth } 2431fcf5ef2aSThomas Huth #endif 2432fcf5ef2aSThomas Huth 2433fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2434fcf5ef2aSThomas Huth /* bpermd */ 2435fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2436fcf5ef2aSThomas Huth { 2437fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2438fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2439fcf5ef2aSThomas Huth } 2440fcf5ef2aSThomas Huth #endif 2441fcf5ef2aSThomas Huth 2442fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2443fcf5ef2aSThomas Huth /* extsw & extsw. */ 2444fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2445fcf5ef2aSThomas Huth 2446fcf5ef2aSThomas Huth /* cntlzd */ 2447fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2448fcf5ef2aSThomas Huth { 24499b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2450efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2451fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2452fcf5ef2aSThomas Huth } 2453efe843d8SDavid Gibson } 2454fcf5ef2aSThomas Huth 2455fcf5ef2aSThomas Huth /* cnttzd */ 2456fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2457fcf5ef2aSThomas Huth { 24589b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2459fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2460fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2461fcf5ef2aSThomas Huth } 2462fcf5ef2aSThomas Huth } 2463fcf5ef2aSThomas Huth 2464fcf5ef2aSThomas Huth /* darn */ 2465fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2466fcf5ef2aSThomas Huth { 2467fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2468fcf5ef2aSThomas Huth 24697e4357f6SRichard Henderson if (l > 2) { 24707e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 24717e4357f6SRichard Henderson } else { 2472f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2473fcf5ef2aSThomas Huth if (l == 0) { 2474fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 24757e4357f6SRichard Henderson } else { 2476fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2477fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 24787e4357f6SRichard Henderson } 2479fcf5ef2aSThomas Huth } 2480fcf5ef2aSThomas Huth } 2481fcf5ef2aSThomas Huth #endif 2482fcf5ef2aSThomas Huth 2483fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2484fcf5ef2aSThomas Huth 2485fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2486fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2487fcf5ef2aSThomas Huth { 2488fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2489fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2490fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2491fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2492fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2493fcf5ef2aSThomas Huth 2494fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2495fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2496fcf5ef2aSThomas Huth } else { 2497fcf5ef2aSThomas Huth target_ulong mask; 2498c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2499fcf5ef2aSThomas Huth TCGv t1; 2500fcf5ef2aSThomas Huth 2501fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2502fcf5ef2aSThomas Huth mb += 32; 2503fcf5ef2aSThomas Huth me += 32; 2504fcf5ef2aSThomas Huth #endif 2505fcf5ef2aSThomas Huth mask = MASK(mb, me); 2506fcf5ef2aSThomas Huth 2507c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2508c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2509c4f6a4a3SDaniele Buono mask_in_32b = false; 2510c4f6a4a3SDaniele Buono } 2511c4f6a4a3SDaniele Buono #endif 2512fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2513c4f6a4a3SDaniele Buono if (mask_in_32b) { 2514fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2515fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2516fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2517fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2518fcf5ef2aSThomas Huth } else { 2519fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2520fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2521fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2522fcf5ef2aSThomas Huth #else 2523fcf5ef2aSThomas Huth g_assert_not_reached(); 2524fcf5ef2aSThomas Huth #endif 2525fcf5ef2aSThomas Huth } 2526fcf5ef2aSThomas Huth 2527fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2528fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2529fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2530fcf5ef2aSThomas Huth } 2531fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2532fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2533fcf5ef2aSThomas Huth } 2534fcf5ef2aSThomas Huth } 2535fcf5ef2aSThomas Huth 2536fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2537fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2538fcf5ef2aSThomas Huth { 2539fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2540fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 25417b4d326fSRichard Henderson int sh = SH(ctx->opcode); 25427b4d326fSRichard Henderson int mb = MB(ctx->opcode); 25437b4d326fSRichard Henderson int me = ME(ctx->opcode); 25447b4d326fSRichard Henderson int len = me - mb + 1; 25457b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2546fcf5ef2aSThomas Huth 25477b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 25487b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 25497b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 25507b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2551fcf5ef2aSThomas Huth } else { 2552fcf5ef2aSThomas Huth target_ulong mask; 2553c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2554fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2555fcf5ef2aSThomas Huth mb += 32; 2556fcf5ef2aSThomas Huth me += 32; 2557fcf5ef2aSThomas Huth #endif 2558fcf5ef2aSThomas Huth mask = MASK(mb, me); 2559c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2560c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2561c4f6a4a3SDaniele Buono mask_in_32b = false; 2562c4f6a4a3SDaniele Buono } 2563c4f6a4a3SDaniele Buono #endif 2564c4f6a4a3SDaniele Buono if (mask_in_32b) { 25657b4d326fSRichard Henderson if (sh == 0) { 25667b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 256794f040aaSVitaly Chikunov } else { 2568fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2569fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2570fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2571fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2572fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 257394f040aaSVitaly Chikunov } 2574fcf5ef2aSThomas Huth } else { 2575fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2576fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2577fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2578fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2579fcf5ef2aSThomas Huth #else 2580fcf5ef2aSThomas Huth g_assert_not_reached(); 2581fcf5ef2aSThomas Huth #endif 2582fcf5ef2aSThomas Huth } 2583fcf5ef2aSThomas Huth } 2584fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2585fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2586fcf5ef2aSThomas Huth } 2587fcf5ef2aSThomas Huth } 2588fcf5ef2aSThomas Huth 2589fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2590fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2591fcf5ef2aSThomas Huth { 2592fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2593fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2594fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2595fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2596fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2597fcf5ef2aSThomas Huth target_ulong mask; 2598c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2599fcf5ef2aSThomas Huth 2600fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2601fcf5ef2aSThomas Huth mb += 32; 2602fcf5ef2aSThomas Huth me += 32; 2603fcf5ef2aSThomas Huth #endif 2604fcf5ef2aSThomas Huth mask = MASK(mb, me); 2605fcf5ef2aSThomas Huth 2606c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2607c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2608c4f6a4a3SDaniele Buono mask_in_32b = false; 2609c4f6a4a3SDaniele Buono } 2610c4f6a4a3SDaniele Buono #endif 2611c4f6a4a3SDaniele Buono if (mask_in_32b) { 2612fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2613fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2614fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2615fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2616fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2617fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2618fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2619fcf5ef2aSThomas Huth } else { 2620fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2621fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2622fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2623fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2624fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2625fcf5ef2aSThomas Huth #else 2626fcf5ef2aSThomas Huth g_assert_not_reached(); 2627fcf5ef2aSThomas Huth #endif 2628fcf5ef2aSThomas Huth } 2629fcf5ef2aSThomas Huth 2630fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2631fcf5ef2aSThomas Huth 2632fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2633fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2634fcf5ef2aSThomas Huth } 2635fcf5ef2aSThomas Huth } 2636fcf5ef2aSThomas Huth 2637fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2638fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2639fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2640fcf5ef2aSThomas Huth { \ 2641fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2642fcf5ef2aSThomas Huth } \ 2643fcf5ef2aSThomas Huth \ 2644fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2645fcf5ef2aSThomas Huth { \ 2646fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2647fcf5ef2aSThomas Huth } 2648fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2649fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2650fcf5ef2aSThomas Huth { \ 2651fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2652fcf5ef2aSThomas Huth } \ 2653fcf5ef2aSThomas Huth \ 2654fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2655fcf5ef2aSThomas Huth { \ 2656fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2657fcf5ef2aSThomas Huth } \ 2658fcf5ef2aSThomas Huth \ 2659fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2660fcf5ef2aSThomas Huth { \ 2661fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2662fcf5ef2aSThomas Huth } \ 2663fcf5ef2aSThomas Huth \ 2664fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2665fcf5ef2aSThomas Huth { \ 2666fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2667fcf5ef2aSThomas Huth } 2668fcf5ef2aSThomas Huth 2669fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2670fcf5ef2aSThomas Huth { 2671fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2672fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26737b4d326fSRichard Henderson int len = me - mb + 1; 26747b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2675fcf5ef2aSThomas Huth 26767b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 26777b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26787b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 26797b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2680fcf5ef2aSThomas Huth } else { 2681fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2682fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2683fcf5ef2aSThomas Huth } 2684fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2685fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2686fcf5ef2aSThomas Huth } 2687fcf5ef2aSThomas Huth } 2688fcf5ef2aSThomas Huth 2689fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2690fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2691fcf5ef2aSThomas Huth { 2692fcf5ef2aSThomas Huth uint32_t sh, mb; 2693fcf5ef2aSThomas Huth 2694fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2695fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2696fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2697fcf5ef2aSThomas Huth } 2698fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2699fcf5ef2aSThomas Huth 2700fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2701fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2702fcf5ef2aSThomas Huth { 2703fcf5ef2aSThomas Huth uint32_t sh, me; 2704fcf5ef2aSThomas Huth 2705fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2706fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2707fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2708fcf5ef2aSThomas Huth } 2709fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2710fcf5ef2aSThomas Huth 2711fcf5ef2aSThomas Huth /* rldic - rldic. */ 2712fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2713fcf5ef2aSThomas Huth { 2714fcf5ef2aSThomas Huth uint32_t sh, mb; 2715fcf5ef2aSThomas Huth 2716fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2717fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2718fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2719fcf5ef2aSThomas Huth } 2720fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2721fcf5ef2aSThomas Huth 2722fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2723fcf5ef2aSThomas Huth { 2724fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2725fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2726fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2727fcf5ef2aSThomas Huth TCGv t0; 2728fcf5ef2aSThomas Huth 2729fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2730fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2731fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2732fcf5ef2aSThomas Huth 2733fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2734fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2735fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2736fcf5ef2aSThomas Huth } 2737fcf5ef2aSThomas Huth } 2738fcf5ef2aSThomas Huth 2739fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2740fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2741fcf5ef2aSThomas Huth { 2742fcf5ef2aSThomas Huth uint32_t mb; 2743fcf5ef2aSThomas Huth 2744fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2745fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2746fcf5ef2aSThomas Huth } 2747fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2748fcf5ef2aSThomas Huth 2749fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2750fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2751fcf5ef2aSThomas Huth { 2752fcf5ef2aSThomas Huth uint32_t me; 2753fcf5ef2aSThomas Huth 2754fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2755fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2756fcf5ef2aSThomas Huth } 2757fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2758fcf5ef2aSThomas Huth 2759fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2760fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2761fcf5ef2aSThomas Huth { 2762fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2763fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2764fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2765fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2766fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2767fcf5ef2aSThomas Huth 2768fcf5ef2aSThomas Huth if (mb <= me) { 2769fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2770fcf5ef2aSThomas Huth } else { 2771fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2772fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2773fcf5ef2aSThomas Huth 2774fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2775fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2776fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2777fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2778fcf5ef2aSThomas Huth } 2779fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2780fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2781fcf5ef2aSThomas Huth } 2782fcf5ef2aSThomas Huth } 2783fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2784fcf5ef2aSThomas Huth #endif 2785fcf5ef2aSThomas Huth 2786fcf5ef2aSThomas Huth /*** Integer shift ***/ 2787fcf5ef2aSThomas Huth 2788fcf5ef2aSThomas Huth /* slw & slw. */ 2789fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2790fcf5ef2aSThomas Huth { 2791fcf5ef2aSThomas Huth TCGv t0, t1; 2792fcf5ef2aSThomas Huth 2793fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2794fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2795fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2796fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2797fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2798fcf5ef2aSThomas Huth #else 2799fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2800fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2801fcf5ef2aSThomas Huth #endif 2802fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2803fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2804fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2805fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2806fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2807efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2808fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2809fcf5ef2aSThomas Huth } 2810efe843d8SDavid Gibson } 2811fcf5ef2aSThomas Huth 2812fcf5ef2aSThomas Huth /* sraw & sraw. */ 2813fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2814fcf5ef2aSThomas Huth { 2815fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2816fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2817efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2818fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2819fcf5ef2aSThomas Huth } 2820efe843d8SDavid Gibson } 2821fcf5ef2aSThomas Huth 2822fcf5ef2aSThomas Huth /* srawi & srawi. */ 2823fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2824fcf5ef2aSThomas Huth { 2825fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2826fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2827fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2828fcf5ef2aSThomas Huth if (sh == 0) { 2829fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2830fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2831af1c259fSSandipan Das if (is_isa300(ctx)) { 2832af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2833af1c259fSSandipan Das } 2834fcf5ef2aSThomas Huth } else { 2835fcf5ef2aSThomas Huth TCGv t0; 2836fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2837fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2838fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2839fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2840fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2841fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2842af1c259fSSandipan Das if (is_isa300(ctx)) { 2843af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2844af1c259fSSandipan Das } 2845fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2846fcf5ef2aSThomas Huth } 2847fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2848fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2849fcf5ef2aSThomas Huth } 2850fcf5ef2aSThomas Huth } 2851fcf5ef2aSThomas Huth 2852fcf5ef2aSThomas Huth /* srw & srw. */ 2853fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2854fcf5ef2aSThomas Huth { 2855fcf5ef2aSThomas Huth TCGv t0, t1; 2856fcf5ef2aSThomas Huth 2857fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2858fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2859fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2860fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2861fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2862fcf5ef2aSThomas Huth #else 2863fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2864fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2865fcf5ef2aSThomas Huth #endif 2866fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2867fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2868fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2869fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2870fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2871efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2872fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2873fcf5ef2aSThomas Huth } 2874efe843d8SDavid Gibson } 2875fcf5ef2aSThomas Huth 2876fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2877fcf5ef2aSThomas Huth /* sld & sld. */ 2878fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2879fcf5ef2aSThomas Huth { 2880fcf5ef2aSThomas Huth TCGv t0, t1; 2881fcf5ef2aSThomas Huth 2882fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2883fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2884fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2885fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2886fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2887fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2888fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2889fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2890efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2891fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2892fcf5ef2aSThomas Huth } 2893efe843d8SDavid Gibson } 2894fcf5ef2aSThomas Huth 2895fcf5ef2aSThomas Huth /* srad & srad. */ 2896fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2897fcf5ef2aSThomas Huth { 2898fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2899fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2900efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2901fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2902fcf5ef2aSThomas Huth } 2903efe843d8SDavid Gibson } 2904fcf5ef2aSThomas Huth /* sradi & sradi. */ 2905fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2906fcf5ef2aSThomas Huth { 2907fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2908fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2909fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2910fcf5ef2aSThomas Huth if (sh == 0) { 2911fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2912fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2913af1c259fSSandipan Das if (is_isa300(ctx)) { 2914af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2915af1c259fSSandipan Das } 2916fcf5ef2aSThomas Huth } else { 2917fcf5ef2aSThomas Huth TCGv t0; 2918fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2919fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2920fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2921fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2922fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2923af1c259fSSandipan Das if (is_isa300(ctx)) { 2924af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2925af1c259fSSandipan Das } 2926fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2927fcf5ef2aSThomas Huth } 2928fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2929fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2930fcf5ef2aSThomas Huth } 2931fcf5ef2aSThomas Huth } 2932fcf5ef2aSThomas Huth 2933fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2934fcf5ef2aSThomas Huth { 2935fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2936fcf5ef2aSThomas Huth } 2937fcf5ef2aSThomas Huth 2938fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2939fcf5ef2aSThomas Huth { 2940fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2941fcf5ef2aSThomas Huth } 2942fcf5ef2aSThomas Huth 2943fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2944fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2945fcf5ef2aSThomas Huth { 2946fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2947fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2948fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2949fcf5ef2aSThomas Huth 2950fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2951fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2952fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2953fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2954fcf5ef2aSThomas Huth } 2955fcf5ef2aSThomas Huth } 2956fcf5ef2aSThomas Huth 2957fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2958fcf5ef2aSThomas Huth { 2959fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2960fcf5ef2aSThomas Huth } 2961fcf5ef2aSThomas Huth 2962fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2963fcf5ef2aSThomas Huth { 2964fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2965fcf5ef2aSThomas Huth } 2966fcf5ef2aSThomas Huth 2967fcf5ef2aSThomas Huth /* srd & srd. */ 2968fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2969fcf5ef2aSThomas Huth { 2970fcf5ef2aSThomas Huth TCGv t0, t1; 2971fcf5ef2aSThomas Huth 2972fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2973fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2974fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2975fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2976fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2977fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2978fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2979fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2980efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2981fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2982fcf5ef2aSThomas Huth } 2983efe843d8SDavid Gibson } 2984fcf5ef2aSThomas Huth #endif 2985fcf5ef2aSThomas Huth 2986fcf5ef2aSThomas Huth /*** Addressing modes ***/ 2987fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2988fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2989fcf5ef2aSThomas Huth target_long maskl) 2990fcf5ef2aSThomas Huth { 2991fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2992fcf5ef2aSThomas Huth 2993fcf5ef2aSThomas Huth simm &= ~maskl; 2994fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2995fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2996fcf5ef2aSThomas Huth simm = (uint32_t)simm; 2997fcf5ef2aSThomas Huth } 2998fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 2999fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3000fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3001fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3002fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3003fcf5ef2aSThomas Huth } 3004fcf5ef2aSThomas Huth } else { 3005fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3006fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3007fcf5ef2aSThomas Huth } else { 3008fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3009fcf5ef2aSThomas Huth } 3010fcf5ef2aSThomas Huth } 3011fcf5ef2aSThomas Huth } 3012fcf5ef2aSThomas Huth 3013fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3014fcf5ef2aSThomas Huth { 3015fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3016fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3017fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3018fcf5ef2aSThomas Huth } else { 3019fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3020fcf5ef2aSThomas Huth } 3021fcf5ef2aSThomas Huth } else { 3022fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3023fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3024fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3025fcf5ef2aSThomas Huth } 3026fcf5ef2aSThomas Huth } 3027fcf5ef2aSThomas Huth } 3028fcf5ef2aSThomas Huth 3029fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3030fcf5ef2aSThomas Huth { 3031fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3032fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3033fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3034fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3035fcf5ef2aSThomas Huth } else { 3036fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3037fcf5ef2aSThomas Huth } 3038fcf5ef2aSThomas Huth } 3039fcf5ef2aSThomas Huth 3040fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3041fcf5ef2aSThomas Huth target_long val) 3042fcf5ef2aSThomas Huth { 3043fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3044fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3045fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3046fcf5ef2aSThomas Huth } 3047fcf5ef2aSThomas Huth } 3048fcf5ef2aSThomas Huth 3049fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3050fcf5ef2aSThomas Huth { 3051fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3052fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3053fcf5ef2aSThomas Huth } 3054fcf5ef2aSThomas Huth 3055eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3056eb63efd9SFernando Eckhardt Valle { 3057eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3058eb63efd9SFernando Eckhardt Valle if (ra) { 3059eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3060eb63efd9SFernando Eckhardt Valle } else { 3061eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3062eb63efd9SFernando Eckhardt Valle } 3063eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3064eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3065eb63efd9SFernando Eckhardt Valle } 3066eb63efd9SFernando Eckhardt Valle return ea; 3067eb63efd9SFernando Eckhardt Valle } 3068eb63efd9SFernando Eckhardt Valle 3069fcf5ef2aSThomas Huth /*** Integer load ***/ 3070fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3071fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3072fcf5ef2aSThomas Huth 3073fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3074fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3075fcf5ef2aSThomas Huth TCGv val, \ 3076fcf5ef2aSThomas Huth TCGv addr) \ 3077fcf5ef2aSThomas Huth { \ 3078fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3079fcf5ef2aSThomas Huth } 3080fcf5ef2aSThomas Huth 3081fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3082fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3083fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3084fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3085fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3086fcf5ef2aSThomas Huth 3087fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3088fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3089fcf5ef2aSThomas Huth 3090fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3091fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3092fcf5ef2aSThomas Huth TCGv_i64 val, \ 3093fcf5ef2aSThomas Huth TCGv addr) \ 3094fcf5ef2aSThomas Huth { \ 3095fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3096fcf5ef2aSThomas Huth } 3097fcf5ef2aSThomas Huth 3098fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3099fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3100fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3101fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3102fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3103fcf5ef2aSThomas Huth 3104fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3105fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3106fcf5ef2aSThomas Huth #endif 3107fcf5ef2aSThomas Huth 3108fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3109fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3110fcf5ef2aSThomas Huth TCGv val, \ 3111fcf5ef2aSThomas Huth TCGv addr) \ 3112fcf5ef2aSThomas Huth { \ 3113fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3114fcf5ef2aSThomas Huth } 3115fcf5ef2aSThomas Huth 3116e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3117fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3118e8f4c8d6SRichard Henderson #endif 3119fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3120fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3121fcf5ef2aSThomas Huth 3122fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3123fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3124fcf5ef2aSThomas Huth 3125fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3126fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3127fcf5ef2aSThomas Huth TCGv_i64 val, \ 3128fcf5ef2aSThomas Huth TCGv addr) \ 3129fcf5ef2aSThomas Huth { \ 3130fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3131fcf5ef2aSThomas Huth } 3132fcf5ef2aSThomas Huth 3133fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3134fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3135fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3136fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3137fcf5ef2aSThomas Huth 3138fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3139fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3140fcf5ef2aSThomas Huth #endif 3141fcf5ef2aSThomas Huth 3142fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3143fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3144fcf5ef2aSThomas Huth { \ 3145fcf5ef2aSThomas Huth TCGv EA; \ 31469f0cf041SMatheus Ferst chk(ctx); \ 3147fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3148fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3149fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3150fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3151fcf5ef2aSThomas Huth } 3152fcf5ef2aSThomas Huth 3153fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3154fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3155fcf5ef2aSThomas Huth 3156fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3157fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3158fcf5ef2aSThomas Huth 315950728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 316050728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 316150728199SRoman Kapl { \ 316250728199SRoman Kapl TCGv EA; \ 31639f0cf041SMatheus Ferst CHK_SV(ctx); \ 316450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 316550728199SRoman Kapl EA = tcg_temp_new(); \ 316650728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 316750728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 316850728199SRoman Kapl } 316950728199SRoman Kapl 317050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 317150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 317250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 317350728199SRoman Kapl #if defined(TARGET_PPC64) 3174fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 317550728199SRoman Kapl #endif 317650728199SRoman Kapl 3177fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3178fcf5ef2aSThomas Huth /* CI load/store variants */ 3179fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3180fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3181fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3182fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3183fcf5ef2aSThomas Huth #endif 3184fcf5ef2aSThomas Huth 3185fcf5ef2aSThomas Huth /*** Integer store ***/ 3186fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3187fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3188fcf5ef2aSThomas Huth { \ 3189fcf5ef2aSThomas Huth TCGv EA; \ 31909f0cf041SMatheus Ferst chk(ctx); \ 3191fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3192fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3193fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3194fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3195fcf5ef2aSThomas Huth } 3196fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3197fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3198fcf5ef2aSThomas Huth 3199fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3200fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3201fcf5ef2aSThomas Huth 320250728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 320350728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 320450728199SRoman Kapl { \ 320550728199SRoman Kapl TCGv EA; \ 32069f0cf041SMatheus Ferst CHK_SV(ctx); \ 320750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 320850728199SRoman Kapl EA = tcg_temp_new(); \ 320950728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 321050728199SRoman Kapl tcg_gen_qemu_st_tl( \ 321150728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 321250728199SRoman Kapl } 321350728199SRoman Kapl 321450728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 321550728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 321650728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 321750728199SRoman Kapl #if defined(TARGET_PPC64) 3218fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 321950728199SRoman Kapl #endif 322050728199SRoman Kapl 3221fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3222fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3223fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3224fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3225fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3226fcf5ef2aSThomas Huth #endif 3227fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3228fcf5ef2aSThomas Huth 3229fcf5ef2aSThomas Huth /* lhbrx */ 3230fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3231fcf5ef2aSThomas Huth 3232fcf5ef2aSThomas Huth /* lwbrx */ 3233fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3234fcf5ef2aSThomas Huth 3235fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3236fcf5ef2aSThomas Huth /* ldbrx */ 3237fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3238fcf5ef2aSThomas Huth /* stdbrx */ 3239fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3240fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3241fcf5ef2aSThomas Huth 3242fcf5ef2aSThomas Huth /* sthbrx */ 3243fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3244fcf5ef2aSThomas Huth /* stwbrx */ 3245fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3246fcf5ef2aSThomas Huth 3247fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3248fcf5ef2aSThomas Huth 3249fcf5ef2aSThomas Huth /* lmw */ 3250fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3251fcf5ef2aSThomas Huth { 3252fcf5ef2aSThomas Huth TCGv t0; 3253fcf5ef2aSThomas Huth TCGv_i32 t1; 3254fcf5ef2aSThomas Huth 3255fcf5ef2aSThomas Huth if (ctx->le_mode) { 3256fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3257fcf5ef2aSThomas Huth return; 3258fcf5ef2aSThomas Huth } 3259fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3260fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 32617058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 3262fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3263fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3264fcf5ef2aSThomas Huth } 3265fcf5ef2aSThomas Huth 3266fcf5ef2aSThomas Huth /* stmw */ 3267fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3268fcf5ef2aSThomas Huth { 3269fcf5ef2aSThomas Huth TCGv t0; 3270fcf5ef2aSThomas Huth TCGv_i32 t1; 3271fcf5ef2aSThomas Huth 3272fcf5ef2aSThomas Huth if (ctx->le_mode) { 3273fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3274fcf5ef2aSThomas Huth return; 3275fcf5ef2aSThomas Huth } 3276fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3277fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 32787058ff52SRichard Henderson t1 = tcg_constant_i32(rS(ctx->opcode)); 3279fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3280fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3281fcf5ef2aSThomas Huth } 3282fcf5ef2aSThomas Huth 3283fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3284fcf5ef2aSThomas Huth 3285fcf5ef2aSThomas Huth /* lswi */ 3286efe843d8SDavid Gibson /* 3287efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3288efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3289efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3290efe843d8SDavid Gibson * spec... 3291fcf5ef2aSThomas Huth */ 3292fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3293fcf5ef2aSThomas Huth { 3294fcf5ef2aSThomas Huth TCGv t0; 3295fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3296fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3297fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3298fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3299fcf5ef2aSThomas Huth int nr; 3300fcf5ef2aSThomas Huth 3301fcf5ef2aSThomas Huth if (ctx->le_mode) { 3302fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3303fcf5ef2aSThomas Huth return; 3304fcf5ef2aSThomas Huth } 3305efe843d8SDavid Gibson if (nb == 0) { 3306fcf5ef2aSThomas Huth nb = 32; 3307efe843d8SDavid Gibson } 3308f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3309fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3310fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3311fcf5ef2aSThomas Huth return; 3312fcf5ef2aSThomas Huth } 3313fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3314fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3315fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 33167058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 33177058ff52SRichard Henderson t2 = tcg_constant_i32(start); 3318fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3319fcf5ef2aSThomas Huth } 3320fcf5ef2aSThomas Huth 3321fcf5ef2aSThomas Huth /* lswx */ 3322fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3323fcf5ef2aSThomas Huth { 3324fcf5ef2aSThomas Huth TCGv t0; 3325fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3326fcf5ef2aSThomas Huth 3327fcf5ef2aSThomas Huth if (ctx->le_mode) { 3328fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3329fcf5ef2aSThomas Huth return; 3330fcf5ef2aSThomas Huth } 3331fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3332fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3333fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 33347058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 33357058ff52SRichard Henderson t2 = tcg_constant_i32(rA(ctx->opcode)); 33367058ff52SRichard Henderson t3 = tcg_constant_i32(rB(ctx->opcode)); 3337fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3338fcf5ef2aSThomas Huth } 3339fcf5ef2aSThomas Huth 3340fcf5ef2aSThomas Huth /* stswi */ 3341fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3342fcf5ef2aSThomas Huth { 3343fcf5ef2aSThomas Huth TCGv t0; 3344fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3345fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3346fcf5ef2aSThomas Huth 3347fcf5ef2aSThomas Huth if (ctx->le_mode) { 3348fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3349fcf5ef2aSThomas Huth return; 3350fcf5ef2aSThomas Huth } 3351fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3352fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3353fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3354efe843d8SDavid Gibson if (nb == 0) { 3355fcf5ef2aSThomas Huth nb = 32; 3356efe843d8SDavid Gibson } 33577058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 33587058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3359fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3360fcf5ef2aSThomas Huth } 3361fcf5ef2aSThomas Huth 3362fcf5ef2aSThomas Huth /* stswx */ 3363fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3364fcf5ef2aSThomas Huth { 3365fcf5ef2aSThomas Huth TCGv t0; 3366fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3367fcf5ef2aSThomas Huth 3368fcf5ef2aSThomas Huth if (ctx->le_mode) { 3369fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3370fcf5ef2aSThomas Huth return; 3371fcf5ef2aSThomas Huth } 3372fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3373fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3374fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3375fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3376fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3377fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 33787058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3379fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3380fcf5ef2aSThomas Huth } 3381fcf5ef2aSThomas Huth 3382fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3383fcf5ef2aSThomas Huth /* eieio */ 3384fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3385fcf5ef2aSThomas Huth { 3386fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3387fcb830afSNicholas Piggin 3388fcb830afSNicholas Piggin /* 3389fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3390fcb830afSNicholas Piggin * operations in the set: 3391fcb830afSNicholas Piggin * - loads from CI memory. 3392fcb830afSNicholas Piggin * - stores to CI memory. 3393fcb830afSNicholas Piggin * - stores to WT memory. 3394fcb830afSNicholas Piggin * 3395fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3396fcb830afSNicholas Piggin * - stores to cacheble memory. 3397fcb830afSNicholas Piggin * 3398fcb830afSNicholas Piggin * It also serializes instructions: 3399fcb830afSNicholas Piggin * - dcbt and dcbst. 3400fcb830afSNicholas Piggin * 3401fcb830afSNicholas Piggin * It separately serializes: 3402fcb830afSNicholas Piggin * - tlbie and tlbsync. 3403fcb830afSNicholas Piggin * 3404fcb830afSNicholas Piggin * And separately serializes: 3405fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3406fcb830afSNicholas Piggin * 3407fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3408fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3409fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3410fcb830afSNicholas Piggin * serialization. 3411fcb830afSNicholas Piggin */ 3412c8fd8373SCédric Le Goater 3413c8fd8373SCédric Le Goater /* 3414c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3415c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3416c8fd8373SCédric Le Goater */ 3417c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3418c8fd8373SCédric Le Goater /* 3419c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3420c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3421c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3422c8fd8373SCédric Le Goater * complain to the user. 3423c8fd8373SCédric Le Goater */ 3424c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3425c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 34262c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3427c8fd8373SCédric Le Goater } else { 3428c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3429c8fd8373SCédric Le Goater } 3430c8fd8373SCédric Le Goater } 3431c8fd8373SCédric Le Goater 3432c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3433fcf5ef2aSThomas Huth } 3434fcf5ef2aSThomas Huth 3435fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3436fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3437fcf5ef2aSThomas Huth { 3438fcf5ef2aSThomas Huth TCGv_i32 t; 3439fcf5ef2aSThomas Huth TCGLabel *l; 3440fcf5ef2aSThomas Huth 3441fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3442fcf5ef2aSThomas Huth return; 3443fcf5ef2aSThomas Huth } 3444fcf5ef2aSThomas Huth l = gen_new_label(); 3445fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3446fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3447fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3448fcf5ef2aSThomas Huth if (global) { 3449fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3450fcf5ef2aSThomas Huth } else { 3451fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3452fcf5ef2aSThomas Huth } 3453fcf5ef2aSThomas Huth gen_set_label(l); 3454fcf5ef2aSThomas Huth } 3455fcf5ef2aSThomas Huth #else 3456fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3457fcf5ef2aSThomas Huth #endif 3458fcf5ef2aSThomas Huth 3459fcf5ef2aSThomas Huth /* isync */ 3460fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3461fcf5ef2aSThomas Huth { 3462fcf5ef2aSThomas Huth /* 3463fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3464fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3465fcf5ef2aSThomas Huth */ 3466fcf5ef2aSThomas Huth if (!ctx->pr) { 3467fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3468fcf5ef2aSThomas Huth } 34694771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3470d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3471fcf5ef2aSThomas Huth } 3472fcf5ef2aSThomas Huth 3473fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3474fcf5ef2aSThomas Huth 347514776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 34762a4e6c1bSRichard Henderson { 34772a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 34782a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 34792a4e6c1bSRichard Henderson 34802a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 34812a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 34822a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 34832a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 34842a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 34852a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 34862a4e6c1bSRichard Henderson } 34872a4e6c1bSRichard Henderson 3488fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3489fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3490fcf5ef2aSThomas Huth { \ 34912a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3492fcf5ef2aSThomas Huth } 3493fcf5ef2aSThomas Huth 3494fcf5ef2aSThomas Huth /* lwarx */ 3495fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3496fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3497fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3498fcf5ef2aSThomas Huth 349914776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 350020923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 350120923c1dSRichard Henderson { 350220923c1dSRichard Henderson TCGv t = tcg_temp_new(); 350320923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 350420923c1dSRichard Henderson TCGv u = tcg_temp_new(); 350520923c1dSRichard Henderson 350620923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 350720923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 350820923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 350920923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 351020923c1dSRichard Henderson 351120923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 351220923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 351320923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 351420923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 351520923c1dSRichard Henderson 351620923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 351720923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 351820923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 351920923c1dSRichard Henderson } 352020923c1dSRichard Henderson 352114776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 352220ba8504SRichard Henderson { 352320ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 352420ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 352520923c1dSRichard Henderson int rt = rD(ctx->opcode); 352620923c1dSRichard Henderson bool need_serial; 352720ba8504SRichard Henderson TCGv src, dst; 352820ba8504SRichard Henderson 352920ba8504SRichard Henderson gen_addr_register(ctx, EA); 353020923c1dSRichard Henderson dst = cpu_gpr[rt]; 353120923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 353220ba8504SRichard Henderson 353320923c1dSRichard Henderson need_serial = false; 353420ba8504SRichard Henderson memop |= MO_ALIGN; 353520ba8504SRichard Henderson switch (gpr_FC) { 353620ba8504SRichard Henderson case 0: /* Fetch and add */ 353720ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 353820ba8504SRichard Henderson break; 353920ba8504SRichard Henderson case 1: /* Fetch and xor */ 354020ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 354120ba8504SRichard Henderson break; 354220ba8504SRichard Henderson case 2: /* Fetch and or */ 354320ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 354420ba8504SRichard Henderson break; 354520ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 354620ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 354720ba8504SRichard Henderson break; 3548b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3549b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3550b8ce0f86SRichard Henderson break; 3551b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3552b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3553b8ce0f86SRichard Henderson break; 3554b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3555b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3556b8ce0f86SRichard Henderson break; 3557b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3558b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3559b8ce0f86SRichard Henderson break; 356020ba8504SRichard Henderson case 8: /* Swap */ 356120ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 356220ba8504SRichard Henderson break; 356320923c1dSRichard Henderson 356420923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 356520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 356620923c1dSRichard Henderson need_serial = true; 356720923c1dSRichard Henderson } else { 356820923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 356920923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 357020923c1dSRichard Henderson 357120923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 357220923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 357320923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 357420923c1dSRichard Henderson } else { 357520923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 357620923c1dSRichard Henderson } 357720923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 357820923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 357920923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 358020923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 358120923c1dSRichard Henderson } 358220ba8504SRichard Henderson break; 358320923c1dSRichard Henderson 358420923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 358520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 358620923c1dSRichard Henderson need_serial = true; 358720923c1dSRichard Henderson } else { 358820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 358920923c1dSRichard Henderson } 359020923c1dSRichard Henderson break; 359120923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 359220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 359320923c1dSRichard Henderson need_serial = true; 359420923c1dSRichard Henderson } else { 359520923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 359620923c1dSRichard Henderson } 359720923c1dSRichard Henderson break; 359820923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 359920923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 360020923c1dSRichard Henderson need_serial = true; 360120923c1dSRichard Henderson } else { 360220923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 360320923c1dSRichard Henderson } 360420923c1dSRichard Henderson break; 360520923c1dSRichard Henderson 360620ba8504SRichard Henderson default: 360720ba8504SRichard Henderson /* invoke data storage error handler */ 360820ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 360920ba8504SRichard Henderson } 361020923c1dSRichard Henderson 361120923c1dSRichard Henderson if (need_serial) { 361220923c1dSRichard Henderson /* Restart with exclusive lock. */ 361320923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 361420923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 361520923c1dSRichard Henderson } 3616a68a6146SBalamuruhan S } 3617a68a6146SBalamuruhan S 361820ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 361920ba8504SRichard Henderson { 362020ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 362120ba8504SRichard Henderson } 362220ba8504SRichard Henderson 362320ba8504SRichard Henderson #ifdef TARGET_PPC64 362420ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 362520ba8504SRichard Henderson { 3626fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 362720ba8504SRichard Henderson } 3628a68a6146SBalamuruhan S #endif 3629a68a6146SBalamuruhan S 363014776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 36319deb041cSRichard Henderson { 36329deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 36339deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 36349deb041cSRichard Henderson TCGv src, discard; 36359deb041cSRichard Henderson 36369deb041cSRichard Henderson gen_addr_register(ctx, EA); 36379deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 36389deb041cSRichard Henderson discard = tcg_temp_new(); 36399deb041cSRichard Henderson 36409deb041cSRichard Henderson memop |= MO_ALIGN; 36419deb041cSRichard Henderson switch (gpr_FC) { 36429deb041cSRichard Henderson case 0: /* add and Store */ 36439deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36449deb041cSRichard Henderson break; 36459deb041cSRichard Henderson case 1: /* xor and Store */ 36469deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36479deb041cSRichard Henderson break; 36489deb041cSRichard Henderson case 2: /* Or and Store */ 36499deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36509deb041cSRichard Henderson break; 36519deb041cSRichard Henderson case 3: /* 'and' and Store */ 36529deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 36539deb041cSRichard Henderson break; 36549deb041cSRichard Henderson case 4: /* Store max unsigned */ 3655b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3656b8ce0f86SRichard Henderson break; 36579deb041cSRichard Henderson case 5: /* Store max signed */ 3658b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3659b8ce0f86SRichard Henderson break; 36609deb041cSRichard Henderson case 6: /* Store min unsigned */ 3661b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3662b8ce0f86SRichard Henderson break; 36639deb041cSRichard Henderson case 7: /* Store min signed */ 3664b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3665b8ce0f86SRichard Henderson break; 36669deb041cSRichard Henderson case 24: /* Store twin */ 36677fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 36687fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 36697fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 36707fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 36717fbc2b20SRichard Henderson } else { 36727fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 36737fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 36747fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 36757fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 36767fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 36777fbc2b20SRichard Henderson 36787fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 36797fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 36807fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 36817fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 36827fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 36837fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 36847fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 36857fbc2b20SRichard Henderson } 36869deb041cSRichard Henderson break; 36879deb041cSRichard Henderson default: 36889deb041cSRichard Henderson /* invoke data storage error handler */ 36899deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 36909deb041cSRichard Henderson } 3691a3401188SBalamuruhan S } 3692a3401188SBalamuruhan S 36939deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 36949deb041cSRichard Henderson { 36959deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 36969deb041cSRichard Henderson } 36979deb041cSRichard Henderson 36989deb041cSRichard Henderson #ifdef TARGET_PPC64 36999deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 37009deb041cSRichard Henderson { 3701fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 37029deb041cSRichard Henderson } 3703a3401188SBalamuruhan S #endif 3704a3401188SBalamuruhan S 370514776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3706fcf5ef2aSThomas Huth { 3707253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3708253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3709d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3710d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3711fcf5ef2aSThomas Huth 3712d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3713d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3714d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3715253ce7b2SNikunj A Dadhania 3716253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3717253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3718253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3719253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3720253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3721253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3722253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3723253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3724253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3725253ce7b2SNikunj A Dadhania 3726fcf5ef2aSThomas Huth gen_set_label(l1); 37274771df23SNikunj A Dadhania 3728efe843d8SDavid Gibson /* 3729efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 3730efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 3731efe843d8SDavid Gibson */ 37324771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3733253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3734253ce7b2SNikunj A Dadhania 3735253ce7b2SNikunj A Dadhania gen_set_label(l2); 3736fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3737fcf5ef2aSThomas Huth } 3738fcf5ef2aSThomas Huth 3739fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3740fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3741fcf5ef2aSThomas Huth { \ 3742d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3743fcf5ef2aSThomas Huth } 3744fcf5ef2aSThomas Huth 3745fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3746fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3747fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3748fcf5ef2aSThomas Huth 3749fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3750fcf5ef2aSThomas Huth /* ldarx */ 3751fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3752fcf5ef2aSThomas Huth /* stdcx. */ 3753fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3754fcf5ef2aSThomas Huth 3755fcf5ef2aSThomas Huth /* lqarx */ 3756fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3757fcf5ef2aSThomas Huth { 3758fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 375994bf2658SRichard Henderson TCGv EA, hi, lo; 376057b38ffdSRichard Henderson TCGv_i128 t16; 3761fcf5ef2aSThomas Huth 3762fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3763fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3764fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3765fcf5ef2aSThomas Huth return; 3766fcf5ef2aSThomas Huth } 3767fcf5ef2aSThomas Huth 3768fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 376994bf2658SRichard Henderson EA = tcg_temp_new(); 3770fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 377194bf2658SRichard Henderson 377294bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 377394bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 377494bf2658SRichard Henderson hi = cpu_gpr[rd]; 377594bf2658SRichard Henderson 377657b38ffdSRichard Henderson t16 = tcg_temp_new_i128(); 377757b38ffdSRichard Henderson tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 377857b38ffdSRichard Henderson tcg_gen_extr_i128_i64(lo, hi, t16); 377994bf2658SRichard Henderson 378094bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 378194bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3782fcf5ef2aSThomas Huth } 3783fcf5ef2aSThomas Huth 3784fcf5ef2aSThomas Huth /* stqcx. */ 3785fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3786fcf5ef2aSThomas Huth { 3787894448aeSRichard Henderson TCGLabel *lab_fail, *lab_over; 37884a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 3789894448aeSRichard Henderson TCGv EA, t0, t1; 3790894448aeSRichard Henderson TCGv_i128 cmp, val; 3791fcf5ef2aSThomas Huth 37924a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3793fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3794fcf5ef2aSThomas Huth return; 3795fcf5ef2aSThomas Huth } 37964a9b3c5dSRichard Henderson 3797894448aeSRichard Henderson lab_fail = gen_new_label(); 3798894448aeSRichard Henderson lab_over = gen_new_label(); 3799894448aeSRichard Henderson 3800fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 38014a9b3c5dSRichard Henderson EA = tcg_temp_new(); 3802fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3803fcf5ef2aSThomas Huth 38044a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 38054a9b3c5dSRichard Henderson 3806894448aeSRichard Henderson cmp = tcg_temp_new_i128(); 3807894448aeSRichard Henderson val = tcg_temp_new_i128(); 38084a9b3c5dSRichard Henderson 3809894448aeSRichard Henderson tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 38104a9b3c5dSRichard Henderson 3811894448aeSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3812894448aeSRichard Henderson tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 38134a9b3c5dSRichard Henderson 3814894448aeSRichard Henderson tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3815894448aeSRichard Henderson DEF_MEMOP(MO_128 | MO_ALIGN)); 3816894448aeSRichard Henderson 3817894448aeSRichard Henderson t0 = tcg_temp_new(); 3818894448aeSRichard Henderson t1 = tcg_temp_new(); 3819894448aeSRichard Henderson tcg_gen_extr_i128_i64(t1, t0, val); 3820894448aeSRichard Henderson 3821894448aeSRichard Henderson tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3822894448aeSRichard Henderson tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3823894448aeSRichard Henderson tcg_gen_or_tl(t0, t0, t1); 3824894448aeSRichard Henderson 3825894448aeSRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3826894448aeSRichard Henderson tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3827894448aeSRichard Henderson tcg_gen_or_tl(t0, t0, cpu_so); 3828894448aeSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3829894448aeSRichard Henderson 38304a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 38314a9b3c5dSRichard Henderson gen_set_label(lab_fail); 3832894448aeSRichard Henderson 3833894448aeSRichard Henderson /* 3834894448aeSRichard Henderson * Address mismatch implies failure. But we still need to provide 3835894448aeSRichard Henderson * the memory barrier semantics of the instruction. 3836894448aeSRichard Henderson */ 3837894448aeSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 38384a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 38394a9b3c5dSRichard Henderson 38404a9b3c5dSRichard Henderson gen_set_label(lab_over); 38414a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 38424a9b3c5dSRichard Henderson } 3843fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3844fcf5ef2aSThomas Huth 3845fcf5ef2aSThomas Huth /* sync */ 3846fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3847fcf5ef2aSThomas Huth { 384803abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 3849fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3850fcf5ef2aSThomas Huth 385103abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 385203abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 385303abfd90SNicholas Piggin } 385403abfd90SNicholas Piggin 3855fcf5ef2aSThomas Huth /* 3856fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3857fcf5ef2aSThomas Huth * 3858fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3859fcf5ef2aSThomas Huth * 3860fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3861fcf5ef2aSThomas Huth * check MSR_PR as well. 3862fcf5ef2aSThomas Huth */ 3863fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3864fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3865fcf5ef2aSThomas Huth } 386603abfd90SNicholas Piggin 386703abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 3868fcf5ef2aSThomas Huth } 3869fcf5ef2aSThomas Huth 3870fcf5ef2aSThomas Huth /* wait */ 3871fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3872fcf5ef2aSThomas Huth { 38730c9717ffSNicholas Piggin uint32_t wc; 38740c9717ffSNicholas Piggin 38750c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 38760c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 38770c9717ffSNicholas Piggin 38780c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 38790c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 38800c9717ffSNicholas Piggin wc = WC(ctx->opcode); 38810c9717ffSNicholas Piggin } else { 38820c9717ffSNicholas Piggin wc = 0; 38830c9717ffSNicholas Piggin } 38840c9717ffSNicholas Piggin 38850c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 38860c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 38870c9717ffSNicholas Piggin wc = WC(ctx->opcode); 38880c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 38890c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 38900c9717ffSNicholas Piggin 38910c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 38920c9717ffSNicholas Piggin if (wc == 3) { 38930c9717ffSNicholas Piggin gen_invalid(ctx); 38940c9717ffSNicholas Piggin return; 38950c9717ffSNicholas Piggin } 38960c9717ffSNicholas Piggin 38970c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 38980c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 38990c9717ffSNicholas Piggin gen_invalid(ctx); 39000c9717ffSNicholas Piggin return; 39010c9717ffSNicholas Piggin } 39020c9717ffSNicholas Piggin 39030c9717ffSNicholas Piggin } else { /* ISA300 */ 39040c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 39050c9717ffSNicholas Piggin if (wc > 0) { 39060c9717ffSNicholas Piggin gen_invalid(ctx); 39070c9717ffSNicholas Piggin return; 39080c9717ffSNicholas Piggin } 39090c9717ffSNicholas Piggin } 39100c9717ffSNicholas Piggin 39110c9717ffSNicholas Piggin } else { 39120c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 39130c9717ffSNicholas Piggin gen_invalid(ctx); 39140c9717ffSNicholas Piggin return; 39150c9717ffSNicholas Piggin } 39160c9717ffSNicholas Piggin 39170c9717ffSNicholas Piggin /* 39180c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 39190c9717ffSNicholas Piggin * to occur. 39200c9717ffSNicholas Piggin */ 39210c9717ffSNicholas Piggin if (wc == 0) { 39227058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(1); 3923fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3924fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3925fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3926b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3927fcf5ef2aSThomas Huth } 3928fcf5ef2aSThomas Huth 39290c9717ffSNicholas Piggin /* 39300c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 39310c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 39320c9717ffSNicholas Piggin * 39330c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 39340c9717ffSNicholas Piggin * no-ops. 39350c9717ffSNicholas Piggin * 39360c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 39370c9717ffSNicholas Piggin * 39380c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 39390c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 39400c9717ffSNicholas Piggin * 39410c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 39420c9717ffSNicholas Piggin * 39430c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 39440c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 39450c9717ffSNicholas Piggin * can be implemented as a no-op. 39460c9717ffSNicholas Piggin * 39470c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 39480c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 39490c9717ffSNicholas Piggin * no-op. 39500c9717ffSNicholas Piggin * 39510c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 39520c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 39530c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 39540c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 39550c9717ffSNicholas Piggin * (if suboptimal). 39560c9717ffSNicholas Piggin */ 39570c9717ffSNicholas Piggin } 39580c9717ffSNicholas Piggin 3959fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3960fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3961fcf5ef2aSThomas Huth { 3962fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 39639f0cf041SMatheus Ferst GEN_PRIV(ctx); 3964fcf5ef2aSThomas Huth #else 3965fcf5ef2aSThomas Huth TCGv_i32 t; 3966fcf5ef2aSThomas Huth 39679f0cf041SMatheus Ferst CHK_HV(ctx); 39687058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_DOZE); 3969fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3970154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3971154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3972fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3973fcf5ef2aSThomas Huth } 3974fcf5ef2aSThomas Huth 3975fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3976fcf5ef2aSThomas Huth { 3977fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 39789f0cf041SMatheus Ferst GEN_PRIV(ctx); 3979fcf5ef2aSThomas Huth #else 3980fcf5ef2aSThomas Huth TCGv_i32 t; 3981fcf5ef2aSThomas Huth 39829f0cf041SMatheus Ferst CHK_HV(ctx); 39837058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_NAP); 3984fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3985154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3986154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3987fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3988fcf5ef2aSThomas Huth } 3989fcf5ef2aSThomas Huth 3990cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 3991cdee0e72SNikunj A Dadhania { 399221c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 39939f0cf041SMatheus Ferst GEN_PRIV(ctx); 399421c0d66aSBenjamin Herrenschmidt #else 399521c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 399621c0d66aSBenjamin Herrenschmidt 39979f0cf041SMatheus Ferst CHK_HV(ctx); 39987058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_STOP); 399921c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 400021c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 400121c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 400221c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4003cdee0e72SNikunj A Dadhania } 4004cdee0e72SNikunj A Dadhania 4005fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4006fcf5ef2aSThomas Huth { 4007fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40089f0cf041SMatheus Ferst GEN_PRIV(ctx); 4009fcf5ef2aSThomas Huth #else 4010fcf5ef2aSThomas Huth TCGv_i32 t; 4011fcf5ef2aSThomas Huth 40129f0cf041SMatheus Ferst CHK_HV(ctx); 40137058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_SLEEP); 4014fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4015154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4016154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4017fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4018fcf5ef2aSThomas Huth } 4019fcf5ef2aSThomas Huth 4020fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4021fcf5ef2aSThomas Huth { 4022fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40239f0cf041SMatheus Ferst GEN_PRIV(ctx); 4024fcf5ef2aSThomas Huth #else 4025fcf5ef2aSThomas Huth TCGv_i32 t; 4026fcf5ef2aSThomas Huth 40279f0cf041SMatheus Ferst CHK_HV(ctx); 40287058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_RVWINKLE); 4029fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4030154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4031154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4032fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4033fcf5ef2aSThomas Huth } 4034fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4035fcf5ef2aSThomas Huth 4036fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4037fcf5ef2aSThomas Huth { 4038fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4039efe843d8SDavid Gibson if (ctx->has_cfar) { 4040fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4041efe843d8SDavid Gibson } 4042fcf5ef2aSThomas Huth #endif 4043fcf5ef2aSThomas Huth } 4044fcf5ef2aSThomas Huth 404546d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 404646d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 404746d396bdSDaniel Henrique Barboza { 404846d396bdSDaniel Henrique Barboza /* 404946d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 405046d396bdSDaniel Henrique Barboza * instructions. 405146d396bdSDaniel Henrique Barboza */ 405246d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 405346d396bdSDaniel Henrique Barboza return; 405446d396bdSDaniel Henrique Barboza } 405546d396bdSDaniel Henrique Barboza 405646d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 4057eeaaefe9SLeandro Lupori TCGLabel *l; 4058eeaaefe9SLeandro Lupori TCGv t0; 4059eeaaefe9SLeandro Lupori 406046d396bdSDaniel Henrique Barboza /* 406146d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 406246d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 406346d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 406446d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 406546d396bdSDaniel Henrique Barboza */ 406646d396bdSDaniel Henrique Barboza gen_icount_io_start(ctx); 406746d396bdSDaniel Henrique Barboza 4068eeaaefe9SLeandro Lupori /* Avoid helper calls when only PMC5-6 are enabled. */ 4069eeaaefe9SLeandro Lupori if (!ctx->pmc_other) { 4070eeaaefe9SLeandro Lupori l = gen_new_label(); 4071eeaaefe9SLeandro Lupori t0 = tcg_temp_new(); 4072eeaaefe9SLeandro Lupori 4073eeaaefe9SLeandro Lupori gen_load_spr(t0, SPR_POWER_PMC5); 4074eeaaefe9SLeandro Lupori tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4075eeaaefe9SLeandro Lupori gen_store_spr(SPR_POWER_PMC5, t0); 4076eeaaefe9SLeandro Lupori /* Check for overflow, if it's enabled */ 4077eeaaefe9SLeandro Lupori if (ctx->mmcr0_pmcjce) { 4078eeaaefe9SLeandro Lupori tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4079eeaaefe9SLeandro Lupori gen_helper_handle_pmc5_overflow(cpu_env); 4080eeaaefe9SLeandro Lupori } 4081eeaaefe9SLeandro Lupori 4082eeaaefe9SLeandro Lupori gen_set_label(l); 4083eeaaefe9SLeandro Lupori } else { 408446d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4085eeaaefe9SLeandro Lupori } 408646d396bdSDaniel Henrique Barboza #else 408746d396bdSDaniel Henrique Barboza /* 408846d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 408946d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 409046d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 409146d396bdSDaniel Henrique Barboza */ 409246d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 409346d396bdSDaniel Henrique Barboza 409446d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 409546d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 409646d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 409746d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 409846d396bdSDaniel Henrique Barboza } 409946d396bdSDaniel Henrique Barboza #else 410046d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 410146d396bdSDaniel Henrique Barboza { 410246d396bdSDaniel Henrique Barboza return; 410346d396bdSDaniel Henrique Barboza } 410446d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 410546d396bdSDaniel Henrique Barboza 4106fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4107fcf5ef2aSThomas Huth { 41086e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4109fcf5ef2aSThomas Huth } 4110fcf5ef2aSThomas Huth 41110e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 41120e3bf489SRoman Kapl { 41139498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 41140e3bf489SRoman Kapl gen_debug_exception(ctx); 41150e3bf489SRoman Kapl } else { 411646d396bdSDaniel Henrique Barboza /* 411746d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 411846d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 411946d396bdSDaniel Henrique Barboza */ 412046d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 412146d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 412246d396bdSDaniel Henrique Barboza } 412346d396bdSDaniel Henrique Barboza 41240e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 41250e3bf489SRoman Kapl } 41260e3bf489SRoman Kapl } 41270e3bf489SRoman Kapl 4128fcf5ef2aSThomas Huth /*** Branch ***/ 4129c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4130fcf5ef2aSThomas Huth { 4131fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4132fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4133fcf5ef2aSThomas Huth } 4134fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 413546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4136fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4137fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 413807ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4139fcf5ef2aSThomas Huth } else { 4140fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 41410e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4142fcf5ef2aSThomas Huth } 4143fcf5ef2aSThomas Huth } 4144fcf5ef2aSThomas Huth 4145fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4146fcf5ef2aSThomas Huth { 4147fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4148fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4149fcf5ef2aSThomas Huth } 4150fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4151fcf5ef2aSThomas Huth } 4152fcf5ef2aSThomas Huth 4153fcf5ef2aSThomas Huth /* b ba bl bla */ 4154fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4155fcf5ef2aSThomas Huth { 4156fcf5ef2aSThomas Huth target_ulong li, target; 4157fcf5ef2aSThomas Huth 4158fcf5ef2aSThomas Huth /* sign extend LI */ 4159fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4160fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4161fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 41622c2bcb1bSRichard Henderson target = ctx->cia + li; 4163fcf5ef2aSThomas Huth } else { 4164fcf5ef2aSThomas Huth target = li; 4165fcf5ef2aSThomas Huth } 4166fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4167b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4168fcf5ef2aSThomas Huth } 41692c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4170fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 41716086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4172fcf5ef2aSThomas Huth } 4173fcf5ef2aSThomas Huth 4174fcf5ef2aSThomas Huth #define BCOND_IM 0 4175fcf5ef2aSThomas Huth #define BCOND_LR 1 4176fcf5ef2aSThomas Huth #define BCOND_CTR 2 4177fcf5ef2aSThomas Huth #define BCOND_TAR 3 4178fcf5ef2aSThomas Huth 4179c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4180fcf5ef2aSThomas Huth { 4181fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4182fcf5ef2aSThomas Huth TCGLabel *l1; 4183fcf5ef2aSThomas Huth TCGv target; 41840e3bf489SRoman Kapl 4185fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 41869723281fSRichard Henderson target = tcg_temp_new(); 4187efe843d8SDavid Gibson if (type == BCOND_CTR) { 4188fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4189efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4190fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4191efe843d8SDavid Gibson } else { 4192fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4193efe843d8SDavid Gibson } 4194fcf5ef2aSThomas Huth } else { 4195f764718dSRichard Henderson target = NULL; 4196fcf5ef2aSThomas Huth } 4197efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4198b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4199efe843d8SDavid Gibson } 4200fcf5ef2aSThomas Huth l1 = gen_new_label(); 4201fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4202fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4203fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4204fa200c95SGreg Kurz 4205fa200c95SGreg Kurz if (type == BCOND_CTR) { 4206fa200c95SGreg Kurz /* 4207fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4208fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4209fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 421015d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 421115d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 421215d68c5eSGreg Kurz * it basically useless and thus never used in real code. 421315d68c5eSGreg Kurz * 421415d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 421515d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 421615d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 421715d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 421815d68c5eSGreg Kurz * doing anything else harmful. 4219fa200c95SGreg Kurz */ 4220d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4221fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4222fcf5ef2aSThomas Huth return; 4223fcf5ef2aSThomas Huth } 4224fa200c95SGreg Kurz 4225fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4226fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4227fa200c95SGreg Kurz } else { 4228fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4229fa200c95SGreg Kurz } 4230fa200c95SGreg Kurz if (bo & 0x2) { 4231fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4232fa200c95SGreg Kurz } else { 4233fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4234fa200c95SGreg Kurz } 4235fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4236fa200c95SGreg Kurz } else { 4237fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4238fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4239fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4240fcf5ef2aSThomas Huth } else { 4241fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4242fcf5ef2aSThomas Huth } 4243fcf5ef2aSThomas Huth if (bo & 0x2) { 4244fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4245fcf5ef2aSThomas Huth } else { 4246fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4247fcf5ef2aSThomas Huth } 4248fa200c95SGreg Kurz } 4249fcf5ef2aSThomas Huth } 4250fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4251fcf5ef2aSThomas Huth /* Test CR */ 4252fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4253fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4254fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4255fcf5ef2aSThomas Huth 4256fcf5ef2aSThomas Huth if (bo & 0x8) { 4257fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4258fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4259fcf5ef2aSThomas Huth } else { 4260fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4261fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4262fcf5ef2aSThomas Huth } 4263fcf5ef2aSThomas Huth } 42642c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4265fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4266fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4267fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 42682c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4269fcf5ef2aSThomas Huth } else { 4270fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4271fcf5ef2aSThomas Huth } 4272fcf5ef2aSThomas Huth } else { 4273fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4274fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4275fcf5ef2aSThomas Huth } else { 4276fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4277fcf5ef2aSThomas Huth } 42780e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4279c4a2e3a9SRichard Henderson } 4280fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 42810e3bf489SRoman Kapl /* fallthrough case */ 4282fcf5ef2aSThomas Huth gen_set_label(l1); 4283b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4284fcf5ef2aSThomas Huth } 42856086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4286fcf5ef2aSThomas Huth } 4287fcf5ef2aSThomas Huth 4288fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4289fcf5ef2aSThomas Huth { 4290fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4291fcf5ef2aSThomas Huth } 4292fcf5ef2aSThomas Huth 4293fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4294fcf5ef2aSThomas Huth { 4295fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4296fcf5ef2aSThomas Huth } 4297fcf5ef2aSThomas Huth 4298fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4299fcf5ef2aSThomas Huth { 4300fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4301fcf5ef2aSThomas Huth } 4302fcf5ef2aSThomas Huth 4303fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4304fcf5ef2aSThomas Huth { 4305fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4306fcf5ef2aSThomas Huth } 4307fcf5ef2aSThomas Huth 4308fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4309fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4310fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4311fcf5ef2aSThomas Huth { \ 4312fcf5ef2aSThomas Huth uint8_t bitmask; \ 4313fcf5ef2aSThomas Huth int sh; \ 4314fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4315fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4316fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4317fcf5ef2aSThomas Huth if (sh > 0) \ 4318fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4319fcf5ef2aSThomas Huth else if (sh < 0) \ 4320fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4321fcf5ef2aSThomas Huth else \ 4322fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4323fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4324fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4325fcf5ef2aSThomas Huth if (sh > 0) \ 4326fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4327fcf5ef2aSThomas Huth else if (sh < 0) \ 4328fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4329fcf5ef2aSThomas Huth else \ 4330fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4331fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4332fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4333fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4334fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4335fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4336fcf5ef2aSThomas Huth } 4337fcf5ef2aSThomas Huth 4338fcf5ef2aSThomas Huth /* crand */ 4339fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4340fcf5ef2aSThomas Huth /* crandc */ 4341fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4342fcf5ef2aSThomas Huth /* creqv */ 4343fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4344fcf5ef2aSThomas Huth /* crnand */ 4345fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4346fcf5ef2aSThomas Huth /* crnor */ 4347fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4348fcf5ef2aSThomas Huth /* cror */ 4349fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4350fcf5ef2aSThomas Huth /* crorc */ 4351fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4352fcf5ef2aSThomas Huth /* crxor */ 4353fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4354fcf5ef2aSThomas Huth 4355fcf5ef2aSThomas Huth /* mcrf */ 4356fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4357fcf5ef2aSThomas Huth { 4358fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4359fcf5ef2aSThomas Huth } 4360fcf5ef2aSThomas Huth 4361fcf5ef2aSThomas Huth /*** System linkage ***/ 4362fcf5ef2aSThomas Huth 4363fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4364fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4365fcf5ef2aSThomas Huth { 4366fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 43679f0cf041SMatheus Ferst GEN_PRIV(ctx); 4368fcf5ef2aSThomas Huth #else 4369efe843d8SDavid Gibson /* 4370efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4371fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4372fcf5ef2aSThomas Huth */ 4373d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4374fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4375fcf5ef2aSThomas Huth return; 4376fcf5ef2aSThomas Huth } 4377fcf5ef2aSThomas Huth /* Restore CPU state */ 43789f0cf041SMatheus Ferst CHK_SV(ctx); 4379f5b6daacSRichard Henderson gen_icount_io_start(ctx); 43802c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4381fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 438259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4383fcf5ef2aSThomas Huth #endif 4384fcf5ef2aSThomas Huth } 4385fcf5ef2aSThomas Huth 4386fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4387fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4388fcf5ef2aSThomas Huth { 4389fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 43909f0cf041SMatheus Ferst GEN_PRIV(ctx); 4391fcf5ef2aSThomas Huth #else 4392fcf5ef2aSThomas Huth /* Restore CPU state */ 43939f0cf041SMatheus Ferst CHK_SV(ctx); 4394f5b6daacSRichard Henderson gen_icount_io_start(ctx); 43952c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4396fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 439759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4398fcf5ef2aSThomas Huth #endif 4399fcf5ef2aSThomas Huth } 4400fcf5ef2aSThomas Huth 44013c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 44023c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 44033c89b8d6SNicholas Piggin { 44043c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 44059f0cf041SMatheus Ferst GEN_PRIV(ctx); 44063c89b8d6SNicholas Piggin #else 44073c89b8d6SNicholas Piggin /* Restore CPU state */ 44089f0cf041SMatheus Ferst CHK_SV(ctx); 4409f5b6daacSRichard Henderson gen_icount_io_start(ctx); 44102c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 44113c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 441259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 44133c89b8d6SNicholas Piggin #endif 44143c89b8d6SNicholas Piggin } 44153c89b8d6SNicholas Piggin #endif 44163c89b8d6SNicholas Piggin 4417fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4418fcf5ef2aSThomas Huth { 4419fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44209f0cf041SMatheus Ferst GEN_PRIV(ctx); 4421fcf5ef2aSThomas Huth #else 4422fcf5ef2aSThomas Huth /* Restore CPU state */ 44239f0cf041SMatheus Ferst CHK_HV(ctx); 4424fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 442559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4426fcf5ef2aSThomas Huth #endif 4427fcf5ef2aSThomas Huth } 4428fcf5ef2aSThomas Huth #endif 4429fcf5ef2aSThomas Huth 4430fcf5ef2aSThomas Huth /* sc */ 4431fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4432fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4433fcf5ef2aSThomas Huth #else 4434fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 44353c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4436fcf5ef2aSThomas Huth #endif 4437fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4438fcf5ef2aSThomas Huth { 4439fcf5ef2aSThomas Huth uint32_t lev; 4440fcf5ef2aSThomas Huth 4441fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4442fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4443fcf5ef2aSThomas Huth } 4444fcf5ef2aSThomas Huth 44453c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 44463c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 44473c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 44483c89b8d6SNicholas Piggin { 4449f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 44503c89b8d6SNicholas Piggin 4451f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 44522c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4453f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 44543c89b8d6SNicholas Piggin 44557a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 44563c89b8d6SNicholas Piggin } 44573c89b8d6SNicholas Piggin #endif 44583c89b8d6SNicholas Piggin #endif 44593c89b8d6SNicholas Piggin 4460fcf5ef2aSThomas Huth /*** Trap ***/ 4461fcf5ef2aSThomas Huth 4462fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4463fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4464fcf5ef2aSThomas Huth { 4465fcf5ef2aSThomas Huth /* Trap never */ 4466fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4467fcf5ef2aSThomas Huth return true; 4468fcf5ef2aSThomas Huth } 4469fcf5ef2aSThomas Huth /* Trap always */ 4470fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4471fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4472fcf5ef2aSThomas Huth return true; 4473fcf5ef2aSThomas Huth } 4474fcf5ef2aSThomas Huth return false; 4475fcf5ef2aSThomas Huth } 4476fcf5ef2aSThomas Huth 4477fcf5ef2aSThomas Huth /* tw */ 4478fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4479fcf5ef2aSThomas Huth { 4480fcf5ef2aSThomas Huth TCGv_i32 t0; 4481fcf5ef2aSThomas Huth 4482fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4483fcf5ef2aSThomas Huth return; 4484fcf5ef2aSThomas Huth } 44857058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4486fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4487fcf5ef2aSThomas Huth t0); 4488fcf5ef2aSThomas Huth } 4489fcf5ef2aSThomas Huth 4490fcf5ef2aSThomas Huth /* twi */ 4491fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4492fcf5ef2aSThomas Huth { 4493fcf5ef2aSThomas Huth TCGv t0; 4494fcf5ef2aSThomas Huth TCGv_i32 t1; 4495fcf5ef2aSThomas Huth 4496fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4497fcf5ef2aSThomas Huth return; 4498fcf5ef2aSThomas Huth } 44997058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45007058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4501fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4502fcf5ef2aSThomas Huth } 4503fcf5ef2aSThomas Huth 4504fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4505fcf5ef2aSThomas Huth /* td */ 4506fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4507fcf5ef2aSThomas Huth { 4508fcf5ef2aSThomas Huth TCGv_i32 t0; 4509fcf5ef2aSThomas Huth 4510fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4511fcf5ef2aSThomas Huth return; 4512fcf5ef2aSThomas Huth } 45137058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4514fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4515fcf5ef2aSThomas Huth t0); 4516fcf5ef2aSThomas Huth } 4517fcf5ef2aSThomas Huth 4518fcf5ef2aSThomas Huth /* tdi */ 4519fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4520fcf5ef2aSThomas Huth { 4521fcf5ef2aSThomas Huth TCGv t0; 4522fcf5ef2aSThomas Huth TCGv_i32 t1; 4523fcf5ef2aSThomas Huth 4524fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4525fcf5ef2aSThomas Huth return; 4526fcf5ef2aSThomas Huth } 45277058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45287058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4529fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4530fcf5ef2aSThomas Huth } 4531fcf5ef2aSThomas Huth #endif 4532fcf5ef2aSThomas Huth 4533fcf5ef2aSThomas Huth /*** Processor control ***/ 4534fcf5ef2aSThomas Huth 4535fcf5ef2aSThomas Huth /* mcrxr */ 4536fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4537fcf5ef2aSThomas Huth { 4538fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4539fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4540fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4541fcf5ef2aSThomas Huth 4542fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4543fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4544fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4545fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4546fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4547fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4548fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4549fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4550fcf5ef2aSThomas Huth 4551fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4552fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4553fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4554fcf5ef2aSThomas Huth } 4555fcf5ef2aSThomas Huth 4556b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4557b63d0434SNikunj A Dadhania /* mcrxrx */ 4558b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4559b63d0434SNikunj A Dadhania { 4560b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4561b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4562b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4563b63d0434SNikunj A Dadhania 4564b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4565b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4566b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4567b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4568b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4569b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4570b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4571b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4572b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4573b63d0434SNikunj A Dadhania } 4574b63d0434SNikunj A Dadhania #endif 4575b63d0434SNikunj A Dadhania 4576fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4577fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4578fcf5ef2aSThomas Huth { 4579fcf5ef2aSThomas Huth uint32_t crm, crn; 4580fcf5ef2aSThomas Huth 4581fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4582fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4583fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4584fcf5ef2aSThomas Huth crn = ctz32(crm); 4585fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4586fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4587fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4588fcf5ef2aSThomas Huth } 4589fcf5ef2aSThomas Huth } else { 4590fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4591fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4592fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4593fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4594fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4595fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4596fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4597fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4598fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4599fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4600fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4601fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4602fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4603fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4604fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4605fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4606fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4607fcf5ef2aSThomas Huth } 4608fcf5ef2aSThomas Huth } 4609fcf5ef2aSThomas Huth 4610fcf5ef2aSThomas Huth /* mfmsr */ 4611fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4612fcf5ef2aSThomas Huth { 46139f0cf041SMatheus Ferst CHK_SV(ctx); 4614fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4615fcf5ef2aSThomas Huth } 4616fcf5ef2aSThomas Huth 4617fcf5ef2aSThomas Huth /* mfspr */ 4618fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4619fcf5ef2aSThomas Huth { 4620fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4621fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4622fcf5ef2aSThomas Huth 4623fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4624fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4625fcf5ef2aSThomas Huth #else 4626fcf5ef2aSThomas Huth if (ctx->pr) { 4627fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4628fcf5ef2aSThomas Huth } else if (ctx->hv) { 4629fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4630fcf5ef2aSThomas Huth } else { 4631fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4632fcf5ef2aSThomas Huth } 4633fcf5ef2aSThomas Huth #endif 4634fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4635fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4636fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4637fcf5ef2aSThomas Huth } else { 4638fcf5ef2aSThomas Huth /* Privilege exception */ 4639efe843d8SDavid Gibson /* 4640efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4641fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4642fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4643fcf5ef2aSThomas Huth */ 4644fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 464531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 464631085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 46472c2bcb1bSRichard Henderson ctx->cia); 4648fcf5ef2aSThomas Huth } 4649fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4650fcf5ef2aSThomas Huth } 4651fcf5ef2aSThomas Huth } else { 4652fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4653fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4654fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4655fcf5ef2aSThomas Huth /* This is a nop */ 4656fcf5ef2aSThomas Huth return; 4657fcf5ef2aSThomas Huth } 4658fcf5ef2aSThomas Huth /* Not defined */ 465931085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 466031085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 46612c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4662fcf5ef2aSThomas Huth 4663efe843d8SDavid Gibson /* 4664efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4665efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4666fcf5ef2aSThomas Huth */ 4667fcf5ef2aSThomas Huth if (sprn & 0x10) { 4668fcf5ef2aSThomas Huth if (ctx->pr) { 46691315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4670fcf5ef2aSThomas Huth } 4671fcf5ef2aSThomas Huth } else { 4672fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 46731315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4674fcf5ef2aSThomas Huth } 4675fcf5ef2aSThomas Huth } 4676fcf5ef2aSThomas Huth } 4677fcf5ef2aSThomas Huth } 4678fcf5ef2aSThomas Huth 4679fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4680fcf5ef2aSThomas Huth { 4681fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4682fcf5ef2aSThomas Huth } 4683fcf5ef2aSThomas Huth 4684fcf5ef2aSThomas Huth /* mftb */ 4685fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4686fcf5ef2aSThomas Huth { 4687fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4688fcf5ef2aSThomas Huth } 4689fcf5ef2aSThomas Huth 4690fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4691fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4692fcf5ef2aSThomas Huth { 4693fcf5ef2aSThomas Huth uint32_t crm, crn; 4694fcf5ef2aSThomas Huth 4695fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4696fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4697fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4698fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4699fcf5ef2aSThomas Huth crn = ctz32(crm); 4700fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4701fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4702fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4703fcf5ef2aSThomas Huth } 4704fcf5ef2aSThomas Huth } else { 4705fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4706fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4707fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4708fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4709fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4710fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4711fcf5ef2aSThomas Huth } 4712fcf5ef2aSThomas Huth } 4713fcf5ef2aSThomas Huth } 4714fcf5ef2aSThomas Huth } 4715fcf5ef2aSThomas Huth 4716fcf5ef2aSThomas Huth /* mtmsr */ 4717fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4718fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4719fcf5ef2aSThomas Huth { 4720caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4721caf590ddSNicholas Piggin gen_invalid(ctx); 4722caf590ddSNicholas Piggin return; 4723caf590ddSNicholas Piggin } 4724caf590ddSNicholas Piggin 47259f0cf041SMatheus Ferst CHK_SV(ctx); 4726fcf5ef2aSThomas Huth 4727fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 47286fa5726bSMatheus Ferst TCGv t0, t1; 47296fa5726bSMatheus Ferst target_ulong mask; 47306fa5726bSMatheus Ferst 47316fa5726bSMatheus Ferst t0 = tcg_temp_new(); 47326fa5726bSMatheus Ferst t1 = tcg_temp_new(); 47336fa5726bSMatheus Ferst 4734f5b6daacSRichard Henderson gen_icount_io_start(ctx); 47356fa5726bSMatheus Ferst 4736fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 47375ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 47386fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4739fcf5ef2aSThomas Huth } else { 47406fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 47416fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 47426fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4743efe843d8SDavid Gibson /* 4744efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4745efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4746efe843d8SDavid Gibson * ppc_store_msr 4747fcf5ef2aSThomas Huth */ 4748b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4749fcf5ef2aSThomas Huth } 47506fa5726bSMatheus Ferst 47516fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 47526fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 47536fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 47546fa5726bSMatheus Ferst 47556fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 47566fa5726bSMatheus Ferst 47575ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4758d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4759fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4760fcf5ef2aSThomas Huth } 4761fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4762fcf5ef2aSThomas Huth 4763fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4764fcf5ef2aSThomas Huth { 47659f0cf041SMatheus Ferst CHK_SV(ctx); 4766fcf5ef2aSThomas Huth 4767fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 47686fa5726bSMatheus Ferst TCGv t0, t1; 47696fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 47706fa5726bSMatheus Ferst 47716fa5726bSMatheus Ferst t0 = tcg_temp_new(); 47726fa5726bSMatheus Ferst t1 = tcg_temp_new(); 47736fa5726bSMatheus Ferst 4774f5b6daacSRichard Henderson gen_icount_io_start(ctx); 4775fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 47765ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 47776fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4778fcf5ef2aSThomas Huth } else { 47796fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 47806fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4781fcf5ef2aSThomas Huth 4782efe843d8SDavid Gibson /* 4783efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4784efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4785efe843d8SDavid Gibson * ppc_store_msr 4786fcf5ef2aSThomas Huth */ 4787b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4788fcf5ef2aSThomas Huth } 47896fa5726bSMatheus Ferst 47906fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 47916fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 47926fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 47936fa5726bSMatheus Ferst 47946fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 47956fa5726bSMatheus Ferst 47965ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4797d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4798fcf5ef2aSThomas Huth #endif 4799fcf5ef2aSThomas Huth } 4800fcf5ef2aSThomas Huth 4801fcf5ef2aSThomas Huth /* mtspr */ 4802fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4803fcf5ef2aSThomas Huth { 4804fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4805fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4806fcf5ef2aSThomas Huth 4807fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4808fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4809fcf5ef2aSThomas Huth #else 4810fcf5ef2aSThomas Huth if (ctx->pr) { 4811fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4812fcf5ef2aSThomas Huth } else if (ctx->hv) { 4813fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4814fcf5ef2aSThomas Huth } else { 4815fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4816fcf5ef2aSThomas Huth } 4817fcf5ef2aSThomas Huth #endif 4818fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4819fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4820fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4821fcf5ef2aSThomas Huth } else { 4822fcf5ef2aSThomas Huth /* Privilege exception */ 482331085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 482431085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48252c2bcb1bSRichard Henderson ctx->cia); 4826fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4827fcf5ef2aSThomas Huth } 4828fcf5ef2aSThomas Huth } else { 4829fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4830fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4831fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4832fcf5ef2aSThomas Huth /* This is a nop */ 4833fcf5ef2aSThomas Huth return; 4834fcf5ef2aSThomas Huth } 4835fcf5ef2aSThomas Huth 4836fcf5ef2aSThomas Huth /* Not defined */ 483731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 483831085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 48392c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4840fcf5ef2aSThomas Huth 4841fcf5ef2aSThomas Huth 4842efe843d8SDavid Gibson /* 4843efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4844efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4845fcf5ef2aSThomas Huth */ 4846fcf5ef2aSThomas Huth if (sprn & 0x10) { 4847fcf5ef2aSThomas Huth if (ctx->pr) { 48481315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4849fcf5ef2aSThomas Huth } 4850fcf5ef2aSThomas Huth } else { 4851fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 48521315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4853fcf5ef2aSThomas Huth } 4854fcf5ef2aSThomas Huth } 4855fcf5ef2aSThomas Huth } 4856fcf5ef2aSThomas Huth } 4857fcf5ef2aSThomas Huth 4858fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4859fcf5ef2aSThomas Huth /* setb */ 4860fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4861fcf5ef2aSThomas Huth { 4862fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 48636f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 48646f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 4865fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4866fcf5ef2aSThomas Huth 4867fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4868fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4869fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4870fcf5ef2aSThomas Huth } 4871fcf5ef2aSThomas Huth #endif 4872fcf5ef2aSThomas Huth 4873fcf5ef2aSThomas Huth /*** Cache management ***/ 4874fcf5ef2aSThomas Huth 4875fcf5ef2aSThomas Huth /* dcbf */ 4876fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4877fcf5ef2aSThomas Huth { 4878fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4879fcf5ef2aSThomas Huth TCGv t0; 4880fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4881fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4882fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4883fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4884fcf5ef2aSThomas Huth } 4885fcf5ef2aSThomas Huth 488650728199SRoman Kapl /* dcbfep (external PID dcbf) */ 488750728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 488850728199SRoman Kapl { 488950728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 489050728199SRoman Kapl TCGv t0; 48919f0cf041SMatheus Ferst CHK_SV(ctx); 489250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 489350728199SRoman Kapl t0 = tcg_temp_new(); 489450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 489550728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 489650728199SRoman Kapl } 489750728199SRoman Kapl 4898fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4899fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4900fcf5ef2aSThomas Huth { 4901fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 49029f0cf041SMatheus Ferst GEN_PRIV(ctx); 4903fcf5ef2aSThomas Huth #else 4904fcf5ef2aSThomas Huth TCGv EA, val; 4905fcf5ef2aSThomas Huth 49069f0cf041SMatheus Ferst CHK_SV(ctx); 4907fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4908fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4909fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4910fcf5ef2aSThomas Huth val = tcg_temp_new(); 4911fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4912fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4913fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4914fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4915fcf5ef2aSThomas Huth } 4916fcf5ef2aSThomas Huth 4917fcf5ef2aSThomas Huth /* dcdst */ 4918fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4919fcf5ef2aSThomas Huth { 4920fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4921fcf5ef2aSThomas Huth TCGv t0; 4922fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4923fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4924fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4925fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4926fcf5ef2aSThomas Huth } 4927fcf5ef2aSThomas Huth 492850728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 492950728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 493050728199SRoman Kapl { 493150728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 493250728199SRoman Kapl TCGv t0; 493350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 493450728199SRoman Kapl t0 = tcg_temp_new(); 493550728199SRoman Kapl gen_addr_reg_index(ctx, t0); 493650728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 493750728199SRoman Kapl } 493850728199SRoman Kapl 4939fcf5ef2aSThomas Huth /* dcbt */ 4940fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4941fcf5ef2aSThomas Huth { 4942efe843d8SDavid Gibson /* 4943efe843d8SDavid Gibson * interpreted as no-op 4944efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4945efe843d8SDavid Gibson * does not generate any exception 4946fcf5ef2aSThomas Huth */ 4947fcf5ef2aSThomas Huth } 4948fcf5ef2aSThomas Huth 494950728199SRoman Kapl /* dcbtep */ 495050728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 495150728199SRoman Kapl { 4952efe843d8SDavid Gibson /* 4953efe843d8SDavid Gibson * interpreted as no-op 4954efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4955efe843d8SDavid Gibson * does not generate any exception 495650728199SRoman Kapl */ 495750728199SRoman Kapl } 495850728199SRoman Kapl 4959fcf5ef2aSThomas Huth /* dcbtst */ 4960fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4961fcf5ef2aSThomas Huth { 4962efe843d8SDavid Gibson /* 4963efe843d8SDavid Gibson * interpreted as no-op 4964efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4965efe843d8SDavid Gibson * does not generate any exception 4966fcf5ef2aSThomas Huth */ 4967fcf5ef2aSThomas Huth } 4968fcf5ef2aSThomas Huth 496950728199SRoman Kapl /* dcbtstep */ 497050728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 497150728199SRoman Kapl { 4972efe843d8SDavid Gibson /* 4973efe843d8SDavid Gibson * interpreted as no-op 4974efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4975efe843d8SDavid Gibson * does not generate any exception 497650728199SRoman Kapl */ 497750728199SRoman Kapl } 497850728199SRoman Kapl 4979fcf5ef2aSThomas Huth /* dcbtls */ 4980fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4981fcf5ef2aSThomas Huth { 4982fcf5ef2aSThomas Huth /* Always fails locking the cache */ 4983fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4984fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 4985fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4986fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 4987fcf5ef2aSThomas Huth } 4988fcf5ef2aSThomas Huth 4989e64645baSBernhard Beschow /* dcblc */ 4990e64645baSBernhard Beschow static void gen_dcblc(DisasContext *ctx) 4991e64645baSBernhard Beschow { 4992e64645baSBernhard Beschow /* 4993e64645baSBernhard Beschow * interpreted as no-op 4994e64645baSBernhard Beschow */ 4995e64645baSBernhard Beschow } 4996e64645baSBernhard Beschow 4997fcf5ef2aSThomas Huth /* dcbz */ 4998fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 4999fcf5ef2aSThomas Huth { 5000fcf5ef2aSThomas Huth TCGv tcgv_addr; 5001fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5002fcf5ef2aSThomas Huth 5003fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5004fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 50057058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5006fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5007fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5008fcf5ef2aSThomas Huth } 5009fcf5ef2aSThomas Huth 501050728199SRoman Kapl /* dcbzep */ 501150728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 501250728199SRoman Kapl { 501350728199SRoman Kapl TCGv tcgv_addr; 501450728199SRoman Kapl TCGv_i32 tcgv_op; 501550728199SRoman Kapl 501650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 501750728199SRoman Kapl tcgv_addr = tcg_temp_new(); 50187058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 501950728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 502050728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 502150728199SRoman Kapl } 502250728199SRoman Kapl 5023fcf5ef2aSThomas Huth /* dst / dstt */ 5024fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5025fcf5ef2aSThomas Huth { 5026fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5027fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5028fcf5ef2aSThomas Huth } else { 5029fcf5ef2aSThomas Huth /* interpreted as no-op */ 5030fcf5ef2aSThomas Huth } 5031fcf5ef2aSThomas Huth } 5032fcf5ef2aSThomas Huth 5033fcf5ef2aSThomas Huth /* dstst /dststt */ 5034fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5035fcf5ef2aSThomas Huth { 5036fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5037fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5038fcf5ef2aSThomas Huth } else { 5039fcf5ef2aSThomas Huth /* interpreted as no-op */ 5040fcf5ef2aSThomas Huth } 5041fcf5ef2aSThomas Huth 5042fcf5ef2aSThomas Huth } 5043fcf5ef2aSThomas Huth 5044fcf5ef2aSThomas Huth /* dss / dssall */ 5045fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5046fcf5ef2aSThomas Huth { 5047fcf5ef2aSThomas Huth /* interpreted as no-op */ 5048fcf5ef2aSThomas Huth } 5049fcf5ef2aSThomas Huth 5050fcf5ef2aSThomas Huth /* icbi */ 5051fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5052fcf5ef2aSThomas Huth { 5053fcf5ef2aSThomas Huth TCGv t0; 5054fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5055fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5056fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5057fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5058fcf5ef2aSThomas Huth } 5059fcf5ef2aSThomas Huth 506050728199SRoman Kapl /* icbiep */ 506150728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 506250728199SRoman Kapl { 506350728199SRoman Kapl TCGv t0; 506450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 506550728199SRoman Kapl t0 = tcg_temp_new(); 506650728199SRoman Kapl gen_addr_reg_index(ctx, t0); 506750728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 506850728199SRoman Kapl } 506950728199SRoman Kapl 5070fcf5ef2aSThomas Huth /* Optional: */ 5071fcf5ef2aSThomas Huth /* dcba */ 5072fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5073fcf5ef2aSThomas Huth { 5074efe843d8SDavid Gibson /* 5075efe843d8SDavid Gibson * interpreted as no-op 5076efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5077fcf5ef2aSThomas Huth * but does not generate any exception 5078fcf5ef2aSThomas Huth */ 5079fcf5ef2aSThomas Huth } 5080fcf5ef2aSThomas Huth 5081fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5082fcf5ef2aSThomas Huth /* Supervisor only: */ 5083fcf5ef2aSThomas Huth 5084fcf5ef2aSThomas Huth /* mfsr */ 5085fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5086fcf5ef2aSThomas Huth { 5087fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 50889f0cf041SMatheus Ferst GEN_PRIV(ctx); 5089fcf5ef2aSThomas Huth #else 5090fcf5ef2aSThomas Huth TCGv t0; 5091fcf5ef2aSThomas Huth 50929f0cf041SMatheus Ferst CHK_SV(ctx); 50937058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5094fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5095fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5096fcf5ef2aSThomas Huth } 5097fcf5ef2aSThomas Huth 5098fcf5ef2aSThomas Huth /* mfsrin */ 5099fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5100fcf5ef2aSThomas Huth { 5101fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51029f0cf041SMatheus Ferst GEN_PRIV(ctx); 5103fcf5ef2aSThomas Huth #else 5104fcf5ef2aSThomas Huth TCGv t0; 5105fcf5ef2aSThomas Huth 51069f0cf041SMatheus Ferst CHK_SV(ctx); 5107fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5108e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5109fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5110fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5111fcf5ef2aSThomas Huth } 5112fcf5ef2aSThomas Huth 5113fcf5ef2aSThomas Huth /* mtsr */ 5114fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5115fcf5ef2aSThomas Huth { 5116fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51179f0cf041SMatheus Ferst GEN_PRIV(ctx); 5118fcf5ef2aSThomas Huth #else 5119fcf5ef2aSThomas Huth TCGv t0; 5120fcf5ef2aSThomas Huth 51219f0cf041SMatheus Ferst CHK_SV(ctx); 51227058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5123fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5124fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5125fcf5ef2aSThomas Huth } 5126fcf5ef2aSThomas Huth 5127fcf5ef2aSThomas Huth /* mtsrin */ 5128fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5129fcf5ef2aSThomas Huth { 5130fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51319f0cf041SMatheus Ferst GEN_PRIV(ctx); 5132fcf5ef2aSThomas Huth #else 5133fcf5ef2aSThomas Huth TCGv t0; 51349f0cf041SMatheus Ferst CHK_SV(ctx); 5135fcf5ef2aSThomas Huth 5136fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5137e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5138fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5139fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5140fcf5ef2aSThomas Huth } 5141fcf5ef2aSThomas Huth 5142fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5143fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5144fcf5ef2aSThomas Huth 5145fcf5ef2aSThomas Huth /* mfsr */ 5146fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5147fcf5ef2aSThomas Huth { 5148fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51499f0cf041SMatheus Ferst GEN_PRIV(ctx); 5150fcf5ef2aSThomas Huth #else 5151fcf5ef2aSThomas Huth TCGv t0; 5152fcf5ef2aSThomas Huth 51539f0cf041SMatheus Ferst CHK_SV(ctx); 51547058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5155fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5156fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5157fcf5ef2aSThomas Huth } 5158fcf5ef2aSThomas Huth 5159fcf5ef2aSThomas Huth /* mfsrin */ 5160fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5161fcf5ef2aSThomas Huth { 5162fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51639f0cf041SMatheus Ferst GEN_PRIV(ctx); 5164fcf5ef2aSThomas Huth #else 5165fcf5ef2aSThomas Huth TCGv t0; 5166fcf5ef2aSThomas Huth 51679f0cf041SMatheus Ferst CHK_SV(ctx); 5168fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5169e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5170fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5171fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5172fcf5ef2aSThomas Huth } 5173fcf5ef2aSThomas Huth 5174fcf5ef2aSThomas Huth /* mtsr */ 5175fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5176fcf5ef2aSThomas Huth { 5177fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51789f0cf041SMatheus Ferst GEN_PRIV(ctx); 5179fcf5ef2aSThomas Huth #else 5180fcf5ef2aSThomas Huth TCGv t0; 5181fcf5ef2aSThomas Huth 51829f0cf041SMatheus Ferst CHK_SV(ctx); 51837058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5184fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5185fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5186fcf5ef2aSThomas Huth } 5187fcf5ef2aSThomas Huth 5188fcf5ef2aSThomas Huth /* mtsrin */ 5189fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5190fcf5ef2aSThomas Huth { 5191fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51929f0cf041SMatheus Ferst GEN_PRIV(ctx); 5193fcf5ef2aSThomas Huth #else 5194fcf5ef2aSThomas Huth TCGv t0; 5195fcf5ef2aSThomas Huth 51969f0cf041SMatheus Ferst CHK_SV(ctx); 5197fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5198e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5199fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5200fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5201fcf5ef2aSThomas Huth } 5202fcf5ef2aSThomas Huth 5203fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5204fcf5ef2aSThomas Huth 5205fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5206fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5207fcf5ef2aSThomas Huth 5208fcf5ef2aSThomas Huth /* tlbia */ 5209fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5210fcf5ef2aSThomas Huth { 5211fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52129f0cf041SMatheus Ferst GEN_PRIV(ctx); 5213fcf5ef2aSThomas Huth #else 52149f0cf041SMatheus Ferst CHK_HV(ctx); 5215fcf5ef2aSThomas Huth 5216fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5217fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5218fcf5ef2aSThomas Huth } 5219fcf5ef2aSThomas Huth 5220fcf5ef2aSThomas Huth /* tlbsync */ 5221fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5222fcf5ef2aSThomas Huth { 5223fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52249f0cf041SMatheus Ferst GEN_PRIV(ctx); 5225fcf5ef2aSThomas Huth #else 522691c60f12SCédric Le Goater 522791c60f12SCédric Le Goater if (ctx->gtse) { 52289f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 522991c60f12SCédric Le Goater } else { 52309f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 523191c60f12SCédric Le Goater } 5232fcf5ef2aSThomas Huth 5233fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5234fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5235fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5236fcf5ef2aSThomas Huth } 5237fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5238fcf5ef2aSThomas Huth } 5239fcf5ef2aSThomas Huth 5240fcf5ef2aSThomas Huth /*** External control ***/ 5241fcf5ef2aSThomas Huth /* Optional: */ 5242fcf5ef2aSThomas Huth 5243fcf5ef2aSThomas Huth /* eciwx */ 5244fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5245fcf5ef2aSThomas Huth { 5246fcf5ef2aSThomas Huth TCGv t0; 5247fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5248fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5249fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5250fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5251c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5252c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5253fcf5ef2aSThomas Huth } 5254fcf5ef2aSThomas Huth 5255fcf5ef2aSThomas Huth /* ecowx */ 5256fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5257fcf5ef2aSThomas Huth { 5258fcf5ef2aSThomas Huth TCGv t0; 5259fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5260fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5261fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5262fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5263c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5264c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5265fcf5ef2aSThomas Huth } 5266fcf5ef2aSThomas Huth 5267fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5268fcf5ef2aSThomas Huth 5269fcf5ef2aSThomas Huth /* tlbld */ 5270fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5271fcf5ef2aSThomas Huth { 5272fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52739f0cf041SMatheus Ferst GEN_PRIV(ctx); 5274fcf5ef2aSThomas Huth #else 52759f0cf041SMatheus Ferst CHK_SV(ctx); 5276fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5277fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5278fcf5ef2aSThomas Huth } 5279fcf5ef2aSThomas Huth 5280fcf5ef2aSThomas Huth /* tlbli */ 5281fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5282fcf5ef2aSThomas Huth { 5283fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52849f0cf041SMatheus Ferst GEN_PRIV(ctx); 5285fcf5ef2aSThomas Huth #else 52869f0cf041SMatheus Ferst CHK_SV(ctx); 5287fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5288fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5289fcf5ef2aSThomas Huth } 5290fcf5ef2aSThomas Huth 5291fcf5ef2aSThomas Huth /* BookE specific instructions */ 5292fcf5ef2aSThomas Huth 5293fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5294fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5295fcf5ef2aSThomas Huth { 5296fcf5ef2aSThomas Huth /* XXX: TODO */ 5297fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5298fcf5ef2aSThomas Huth } 5299fcf5ef2aSThomas Huth 5300fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5301fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5302fcf5ef2aSThomas Huth { 5303fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53049f0cf041SMatheus Ferst GEN_PRIV(ctx); 5305fcf5ef2aSThomas Huth #else 5306fcf5ef2aSThomas Huth TCGv t0; 5307fcf5ef2aSThomas Huth 53089f0cf041SMatheus Ferst CHK_SV(ctx); 5309fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5310fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5311fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5312fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5313fcf5ef2aSThomas Huth } 5314fcf5ef2aSThomas Huth 5315fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5316fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5317fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5318fcf5ef2aSThomas Huth { 5319fcf5ef2aSThomas Huth TCGv t0, t1; 5320fcf5ef2aSThomas Huth 53219723281fSRichard Henderson t0 = tcg_temp_new(); 53229723281fSRichard Henderson t1 = tcg_temp_new(); 5323fcf5ef2aSThomas Huth 5324fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5325fcf5ef2aSThomas Huth case 0x05: 5326fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5327fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5328fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5329fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5330fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5331fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5332fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5333fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5334fcf5ef2aSThomas Huth break; 5335fcf5ef2aSThomas Huth case 0x04: 5336fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5337fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5338fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5339fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5340fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5341fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5342fcf5ef2aSThomas Huth break; 5343fcf5ef2aSThomas Huth case 0x01: 5344fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5345fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5346fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5347fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5348fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5349fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5350fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5351fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5352fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5353fcf5ef2aSThomas Huth break; 5354fcf5ef2aSThomas Huth case 0x00: 5355fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5356fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5357fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5358fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5359fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5360fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5361fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5362fcf5ef2aSThomas Huth break; 5363fcf5ef2aSThomas Huth case 0x0D: 5364fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5365fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5366fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5367fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5368fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5369fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5370fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5371fcf5ef2aSThomas Huth break; 5372fcf5ef2aSThomas Huth case 0x0C: 5373fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5374fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5375fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5376fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5377fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5378fcf5ef2aSThomas Huth break; 5379fcf5ef2aSThomas Huth } 5380fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5381fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5382fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5383fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5384fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5385fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5386fcf5ef2aSThomas Huth } else { 5387fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5388fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5389fcf5ef2aSThomas Huth } 5390fcf5ef2aSThomas Huth 5391fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5392fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5393fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5394fcf5ef2aSThomas Huth 5395fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5396fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5397fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5398fcf5ef2aSThomas Huth } 5399fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5400fcf5ef2aSThomas Huth /* Signed */ 5401fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5402fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5403fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5404fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5405fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5406fcf5ef2aSThomas Huth /* Saturate */ 5407fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5408fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5409fcf5ef2aSThomas Huth } 5410fcf5ef2aSThomas Huth } else { 5411fcf5ef2aSThomas Huth /* Unsigned */ 5412fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5413fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5414fcf5ef2aSThomas Huth /* Saturate */ 5415fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5416fcf5ef2aSThomas Huth } 5417fcf5ef2aSThomas Huth } 5418fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5419fcf5ef2aSThomas Huth /* Check overflow */ 5420fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5421fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5422fcf5ef2aSThomas Huth } 5423fcf5ef2aSThomas Huth gen_set_label(l1); 5424fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5425fcf5ef2aSThomas Huth } 5426fcf5ef2aSThomas Huth } else { 5427fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5428fcf5ef2aSThomas Huth } 5429fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5430fcf5ef2aSThomas Huth /* Update Rc0 */ 5431fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5432fcf5ef2aSThomas Huth } 5433fcf5ef2aSThomas Huth } 5434fcf5ef2aSThomas Huth 5435fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5436fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5437fcf5ef2aSThomas Huth { \ 5438fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5439fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5440fcf5ef2aSThomas Huth } 5441fcf5ef2aSThomas Huth 5442fcf5ef2aSThomas Huth /* macchw - macchw. */ 5443fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5444fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5445fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5446fcf5ef2aSThomas Huth /* macchws - macchws. */ 5447fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5448fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5449fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5450fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5451fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5452fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5453fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5454fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5455fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5456fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5457fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5458fcf5ef2aSThomas Huth /* machhw - machhw. */ 5459fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5460fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5461fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5462fcf5ef2aSThomas Huth /* machhws - machhws. */ 5463fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5464fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5465fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5466fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5467fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5468fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5469fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5470fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5471fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5472fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5473fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5474fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5475fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5476fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5477fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5478fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5479fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5480fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5481fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5482fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5483fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5484fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5485fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5486fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5487fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5488fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5489fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5490fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5491fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5492fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5493fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5494fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5495fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5496fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5497fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5498fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5499fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5500fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5501fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5502fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5503fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5504fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5505fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5506fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5507fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5508fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5509fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5510fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5511fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5512fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5513fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5514fcf5ef2aSThomas Huth 5515fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5516fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5517fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5518fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5519fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5520fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5521fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5522fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5523fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5524fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5525fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5526fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5527fcf5ef2aSThomas Huth 5528fcf5ef2aSThomas Huth /* mfdcr */ 5529fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5530fcf5ef2aSThomas Huth { 5531fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55329f0cf041SMatheus Ferst GEN_PRIV(ctx); 5533fcf5ef2aSThomas Huth #else 5534fcf5ef2aSThomas Huth TCGv dcrn; 5535fcf5ef2aSThomas Huth 55369f0cf041SMatheus Ferst CHK_SV(ctx); 55377058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5538fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5539fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5540fcf5ef2aSThomas Huth } 5541fcf5ef2aSThomas Huth 5542fcf5ef2aSThomas Huth /* mtdcr */ 5543fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5544fcf5ef2aSThomas Huth { 5545fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55469f0cf041SMatheus Ferst GEN_PRIV(ctx); 5547fcf5ef2aSThomas Huth #else 5548fcf5ef2aSThomas Huth TCGv dcrn; 5549fcf5ef2aSThomas Huth 55509f0cf041SMatheus Ferst CHK_SV(ctx); 55517058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5552fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5553fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5554fcf5ef2aSThomas Huth } 5555fcf5ef2aSThomas Huth 5556fcf5ef2aSThomas Huth /* mfdcrx */ 5557fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5558fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5559fcf5ef2aSThomas Huth { 5560fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55619f0cf041SMatheus Ferst GEN_PRIV(ctx); 5562fcf5ef2aSThomas Huth #else 55639f0cf041SMatheus Ferst CHK_SV(ctx); 5564fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5565fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5566fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5567fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5568fcf5ef2aSThomas Huth } 5569fcf5ef2aSThomas Huth 5570fcf5ef2aSThomas Huth /* mtdcrx */ 5571fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5572fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5573fcf5ef2aSThomas Huth { 5574fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55759f0cf041SMatheus Ferst GEN_PRIV(ctx); 5576fcf5ef2aSThomas Huth #else 55779f0cf041SMatheus Ferst CHK_SV(ctx); 5578fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5579fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5580fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5581fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5582fcf5ef2aSThomas Huth } 5583fcf5ef2aSThomas Huth 5584fcf5ef2aSThomas Huth /* dccci */ 5585fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5586fcf5ef2aSThomas Huth { 55879f0cf041SMatheus Ferst CHK_SV(ctx); 5588fcf5ef2aSThomas Huth /* interpreted as no-op */ 5589fcf5ef2aSThomas Huth } 5590fcf5ef2aSThomas Huth 5591fcf5ef2aSThomas Huth /* dcread */ 5592fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5593fcf5ef2aSThomas Huth { 5594fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55959f0cf041SMatheus Ferst GEN_PRIV(ctx); 5596fcf5ef2aSThomas Huth #else 5597fcf5ef2aSThomas Huth TCGv EA, val; 5598fcf5ef2aSThomas Huth 55999f0cf041SMatheus Ferst CHK_SV(ctx); 5600fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5601fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5602fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5603fcf5ef2aSThomas Huth val = tcg_temp_new(); 5604fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5605fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5606fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5607fcf5ef2aSThomas Huth } 5608fcf5ef2aSThomas Huth 5609fcf5ef2aSThomas Huth /* icbt */ 5610fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5611fcf5ef2aSThomas Huth { 5612efe843d8SDavid Gibson /* 5613efe843d8SDavid Gibson * interpreted as no-op 5614efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5615efe843d8SDavid Gibson * does not generate any exception 5616fcf5ef2aSThomas Huth */ 5617fcf5ef2aSThomas Huth } 5618fcf5ef2aSThomas Huth 5619fcf5ef2aSThomas Huth /* iccci */ 5620fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5621fcf5ef2aSThomas Huth { 56229f0cf041SMatheus Ferst CHK_SV(ctx); 5623fcf5ef2aSThomas Huth /* interpreted as no-op */ 5624fcf5ef2aSThomas Huth } 5625fcf5ef2aSThomas Huth 5626fcf5ef2aSThomas Huth /* icread */ 5627fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5628fcf5ef2aSThomas Huth { 56299f0cf041SMatheus Ferst CHK_SV(ctx); 5630fcf5ef2aSThomas Huth /* interpreted as no-op */ 5631fcf5ef2aSThomas Huth } 5632fcf5ef2aSThomas Huth 5633fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5634fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5635fcf5ef2aSThomas Huth { 5636fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56379f0cf041SMatheus Ferst GEN_PRIV(ctx); 5638fcf5ef2aSThomas Huth #else 56399f0cf041SMatheus Ferst CHK_SV(ctx); 5640fcf5ef2aSThomas Huth /* Restore CPU state */ 5641fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 564259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5643fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5644fcf5ef2aSThomas Huth } 5645fcf5ef2aSThomas Huth 5646fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5647fcf5ef2aSThomas Huth { 5648fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56499f0cf041SMatheus Ferst GEN_PRIV(ctx); 5650fcf5ef2aSThomas Huth #else 56519f0cf041SMatheus Ferst CHK_SV(ctx); 5652fcf5ef2aSThomas Huth /* Restore CPU state */ 5653fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 565459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5655fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5656fcf5ef2aSThomas Huth } 5657fcf5ef2aSThomas Huth 5658fcf5ef2aSThomas Huth /* BookE specific */ 5659fcf5ef2aSThomas Huth 5660fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5661fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5662fcf5ef2aSThomas Huth { 5663fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56649f0cf041SMatheus Ferst GEN_PRIV(ctx); 5665fcf5ef2aSThomas Huth #else 56669f0cf041SMatheus Ferst CHK_SV(ctx); 5667fcf5ef2aSThomas Huth /* Restore CPU state */ 5668fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 566959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5670fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5671fcf5ef2aSThomas Huth } 5672fcf5ef2aSThomas Huth 5673fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5674fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5675fcf5ef2aSThomas Huth { 5676fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56779f0cf041SMatheus Ferst GEN_PRIV(ctx); 5678fcf5ef2aSThomas Huth #else 56799f0cf041SMatheus Ferst CHK_SV(ctx); 5680fcf5ef2aSThomas Huth /* Restore CPU state */ 5681fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 568259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5683fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5684fcf5ef2aSThomas Huth } 5685fcf5ef2aSThomas Huth 5686fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5687fcf5ef2aSThomas Huth 5688fcf5ef2aSThomas Huth /* tlbre */ 5689fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5690fcf5ef2aSThomas Huth { 5691fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56929f0cf041SMatheus Ferst GEN_PRIV(ctx); 5693fcf5ef2aSThomas Huth #else 56949f0cf041SMatheus Ferst CHK_SV(ctx); 5695fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5696fcf5ef2aSThomas Huth case 0: 5697fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5698fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5699fcf5ef2aSThomas Huth break; 5700fcf5ef2aSThomas Huth case 1: 5701fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5702fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5703fcf5ef2aSThomas Huth break; 5704fcf5ef2aSThomas Huth default: 5705fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5706fcf5ef2aSThomas Huth break; 5707fcf5ef2aSThomas Huth } 5708fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5709fcf5ef2aSThomas Huth } 5710fcf5ef2aSThomas Huth 5711fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5712fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5713fcf5ef2aSThomas Huth { 5714fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57159f0cf041SMatheus Ferst GEN_PRIV(ctx); 5716fcf5ef2aSThomas Huth #else 5717fcf5ef2aSThomas Huth TCGv t0; 5718fcf5ef2aSThomas Huth 57199f0cf041SMatheus Ferst CHK_SV(ctx); 5720fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5721fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5722fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5723fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5724fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5725fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5726fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5727fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5728fcf5ef2aSThomas Huth gen_set_label(l1); 5729fcf5ef2aSThomas Huth } 5730fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5731fcf5ef2aSThomas Huth } 5732fcf5ef2aSThomas Huth 5733fcf5ef2aSThomas Huth /* tlbwe */ 5734fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5735fcf5ef2aSThomas Huth { 5736fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57379f0cf041SMatheus Ferst GEN_PRIV(ctx); 5738fcf5ef2aSThomas Huth #else 57399f0cf041SMatheus Ferst CHK_SV(ctx); 5740fcf5ef2aSThomas Huth 5741fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5742fcf5ef2aSThomas Huth case 0: 5743fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5744fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5745fcf5ef2aSThomas Huth break; 5746fcf5ef2aSThomas Huth case 1: 5747fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5748fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5749fcf5ef2aSThomas Huth break; 5750fcf5ef2aSThomas Huth default: 5751fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5752fcf5ef2aSThomas Huth break; 5753fcf5ef2aSThomas Huth } 5754fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5755fcf5ef2aSThomas Huth } 5756fcf5ef2aSThomas Huth 5757fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5758fcf5ef2aSThomas Huth 5759fcf5ef2aSThomas Huth /* tlbre */ 5760fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5761fcf5ef2aSThomas Huth { 5762fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57639f0cf041SMatheus Ferst GEN_PRIV(ctx); 5764fcf5ef2aSThomas Huth #else 57659f0cf041SMatheus Ferst CHK_SV(ctx); 5766fcf5ef2aSThomas Huth 5767fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5768fcf5ef2aSThomas Huth case 0: 5769fcf5ef2aSThomas Huth case 1: 5770fcf5ef2aSThomas Huth case 2: 5771fcf5ef2aSThomas Huth { 57727058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5773fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5774fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5775fcf5ef2aSThomas Huth } 5776fcf5ef2aSThomas Huth break; 5777fcf5ef2aSThomas Huth default: 5778fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5779fcf5ef2aSThomas Huth break; 5780fcf5ef2aSThomas Huth } 5781fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5782fcf5ef2aSThomas Huth } 5783fcf5ef2aSThomas Huth 5784fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5785fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5786fcf5ef2aSThomas Huth { 5787fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57889f0cf041SMatheus Ferst GEN_PRIV(ctx); 5789fcf5ef2aSThomas Huth #else 5790fcf5ef2aSThomas Huth TCGv t0; 5791fcf5ef2aSThomas Huth 57929f0cf041SMatheus Ferst CHK_SV(ctx); 5793fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5794fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5795fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5796fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5797fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5798fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5799fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5800fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5801fcf5ef2aSThomas Huth gen_set_label(l1); 5802fcf5ef2aSThomas Huth } 5803fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5804fcf5ef2aSThomas Huth } 5805fcf5ef2aSThomas Huth 5806fcf5ef2aSThomas Huth /* tlbwe */ 5807fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 5808fcf5ef2aSThomas Huth { 5809fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58109f0cf041SMatheus Ferst GEN_PRIV(ctx); 5811fcf5ef2aSThomas Huth #else 58129f0cf041SMatheus Ferst CHK_SV(ctx); 5813fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5814fcf5ef2aSThomas Huth case 0: 5815fcf5ef2aSThomas Huth case 1: 5816fcf5ef2aSThomas Huth case 2: 5817fcf5ef2aSThomas Huth { 58187058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5819fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5820fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5821fcf5ef2aSThomas Huth } 5822fcf5ef2aSThomas Huth break; 5823fcf5ef2aSThomas Huth default: 5824fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5825fcf5ef2aSThomas Huth break; 5826fcf5ef2aSThomas Huth } 5827fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5828fcf5ef2aSThomas Huth } 5829fcf5ef2aSThomas Huth 5830fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 5831fcf5ef2aSThomas Huth 5832fcf5ef2aSThomas Huth /* tlbre */ 5833fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 5834fcf5ef2aSThomas Huth { 5835fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58369f0cf041SMatheus Ferst GEN_PRIV(ctx); 5837fcf5ef2aSThomas Huth #else 58389f0cf041SMatheus Ferst CHK_SV(ctx); 5839fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 5840fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5841fcf5ef2aSThomas Huth } 5842fcf5ef2aSThomas Huth 5843fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5844fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 5845fcf5ef2aSThomas Huth { 5846fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58479f0cf041SMatheus Ferst GEN_PRIV(ctx); 5848fcf5ef2aSThomas Huth #else 5849fcf5ef2aSThomas Huth TCGv t0; 5850fcf5ef2aSThomas Huth 58519f0cf041SMatheus Ferst CHK_SV(ctx); 5852fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 5853fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 58549d15d8e1SRichard Henderson tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5855fcf5ef2aSThomas Huth } else { 58569d15d8e1SRichard Henderson t0 = cpu_gpr[rB(ctx->opcode)]; 5857fcf5ef2aSThomas Huth } 5858fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 5859fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5860fcf5ef2aSThomas Huth } 5861fcf5ef2aSThomas Huth 5862fcf5ef2aSThomas Huth /* tlbwe */ 5863fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 5864fcf5ef2aSThomas Huth { 5865fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58669f0cf041SMatheus Ferst GEN_PRIV(ctx); 5867fcf5ef2aSThomas Huth #else 58689f0cf041SMatheus Ferst CHK_SV(ctx); 5869fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 5870fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5871fcf5ef2aSThomas Huth } 5872fcf5ef2aSThomas Huth 5873fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 5874fcf5ef2aSThomas Huth { 5875fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58769f0cf041SMatheus Ferst GEN_PRIV(ctx); 5877fcf5ef2aSThomas Huth #else 5878fcf5ef2aSThomas Huth TCGv t0; 5879fcf5ef2aSThomas Huth 58809f0cf041SMatheus Ferst CHK_SV(ctx); 5881fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5882fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5883fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 5884fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5885fcf5ef2aSThomas Huth } 5886fcf5ef2aSThomas Huth 5887fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 5888fcf5ef2aSThomas Huth { 5889fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58909f0cf041SMatheus Ferst GEN_PRIV(ctx); 5891fcf5ef2aSThomas Huth #else 5892fcf5ef2aSThomas Huth TCGv t0; 5893fcf5ef2aSThomas Huth 58949f0cf041SMatheus Ferst CHK_SV(ctx); 5895fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5896fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5897fcf5ef2aSThomas Huth 5898fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 5899fcf5ef2aSThomas Huth case 0: 5900fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 5901fcf5ef2aSThomas Huth break; 5902fcf5ef2aSThomas Huth case 1: 5903fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 5904fcf5ef2aSThomas Huth break; 5905fcf5ef2aSThomas Huth case 3: 5906fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 5907fcf5ef2aSThomas Huth break; 5908fcf5ef2aSThomas Huth default: 5909fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5910fcf5ef2aSThomas Huth break; 5911fcf5ef2aSThomas Huth } 5912fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5913fcf5ef2aSThomas Huth } 5914fcf5ef2aSThomas Huth 5915fcf5ef2aSThomas Huth /* wrtee */ 5916fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 5917fcf5ef2aSThomas Huth { 5918fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59199f0cf041SMatheus Ferst GEN_PRIV(ctx); 5920fcf5ef2aSThomas Huth #else 5921fcf5ef2aSThomas Huth TCGv t0; 5922fcf5ef2aSThomas Huth 59239f0cf041SMatheus Ferst CHK_SV(ctx); 5924fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5925fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5926fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5927fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 59282fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 5929efe843d8SDavid Gibson /* 5930efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 5931efe843d8SDavid Gibson * just set msr_ee to 1 5932fcf5ef2aSThomas Huth */ 5933d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5934fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5935fcf5ef2aSThomas Huth } 5936fcf5ef2aSThomas Huth 5937fcf5ef2aSThomas Huth /* wrteei */ 5938fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 5939fcf5ef2aSThomas Huth { 5940fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59419f0cf041SMatheus Ferst GEN_PRIV(ctx); 5942fcf5ef2aSThomas Huth #else 59439f0cf041SMatheus Ferst CHK_SV(ctx); 5944fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 5945fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 59462fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 5947fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 5948d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5949fcf5ef2aSThomas Huth } else { 5950fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5951fcf5ef2aSThomas Huth } 5952fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5953fcf5ef2aSThomas Huth } 5954fcf5ef2aSThomas Huth 5955fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 5956fcf5ef2aSThomas Huth 5957fcf5ef2aSThomas Huth /* dlmzb */ 5958fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 5959fcf5ef2aSThomas Huth { 59607058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 5961fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 5962fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 5963fcf5ef2aSThomas Huth } 5964fcf5ef2aSThomas Huth 5965fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 5966fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 5967fcf5ef2aSThomas Huth { 5968fcf5ef2aSThomas Huth /* interpreted as no-op */ 5969fcf5ef2aSThomas Huth } 5970fcf5ef2aSThomas Huth 5971fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 5972fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 5973fcf5ef2aSThomas Huth { 597427a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 597527a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 597627a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 597727a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 597827a3ea7eSBALATON Zoltan } 597927a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 5980fcf5ef2aSThomas Huth } 5981fcf5ef2aSThomas Huth 5982fcf5ef2aSThomas Huth /* icbt */ 5983fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 5984fcf5ef2aSThomas Huth { 5985efe843d8SDavid Gibson /* 5986efe843d8SDavid Gibson * interpreted as no-op 5987efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5988efe843d8SDavid Gibson * does not generate any exception 5989fcf5ef2aSThomas Huth */ 5990fcf5ef2aSThomas Huth } 5991fcf5ef2aSThomas Huth 5992fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5993fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 5994fcf5ef2aSThomas Huth { 5995fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5996fcf5ef2aSThomas Huth 5997fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5998fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 5999fcf5ef2aSThomas Huth } 6000fcf5ef2aSThomas Huth 6001fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6002fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6003fcf5ef2aSThomas Huth { 6004fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6005fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6006fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6007fcf5ef2aSThomas Huth 6008fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6009fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6010fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6011fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6012fcf5ef2aSThomas Huth } else { 6013fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6014fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6015fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6016fcf5ef2aSThomas Huth } 6017fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6018fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6019fcf5ef2aSThomas Huth } 6020fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6021fcf5ef2aSThomas Huth 6022fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6023fcf5ef2aSThomas Huth { 6024fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6025fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6026fcf5ef2aSThomas Huth return; 6027fcf5ef2aSThomas Huth } 6028fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6029fcf5ef2aSThomas Huth } 6030fcf5ef2aSThomas Huth 6031fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6032fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6033fcf5ef2aSThomas Huth { \ 6034fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6035fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6036fcf5ef2aSThomas Huth return; \ 6037fcf5ef2aSThomas Huth } \ 6038efe843d8SDavid Gibson /* \ 6039efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6040fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6041fcf5ef2aSThomas Huth * \ 6042fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6043fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6044fcf5ef2aSThomas Huth */ \ 6045fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6046fcf5ef2aSThomas Huth } 6047fcf5ef2aSThomas Huth 6048fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6049fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6050fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6051fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6052fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6053fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6054fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6055efe843d8SDavid Gibson 6056b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6057b8b4576eSSuraj Jitindar Singh { 6058efe843d8SDavid Gibson /* Do Nothing */ 6059b8b4576eSSuraj Jitindar Singh } 6060fcf5ef2aSThomas Huth 606180b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 606280b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 606380b8c1eeSNikunj A Dadhania { \ 6064efe843d8SDavid Gibson /* \ 6065efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6066efe843d8SDavid Gibson * implementation of the copy paste facility \ 606780b8c1eeSNikunj A Dadhania */ \ 606880b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 606980b8c1eeSNikunj A Dadhania } 607080b8c1eeSNikunj A Dadhania 607180b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 607280b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 607380b8c1eeSNikunj A Dadhania 6074fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6075fcf5ef2aSThomas Huth { 6076fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6077fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6078fcf5ef2aSThomas Huth return; 6079fcf5ef2aSThomas Huth } 6080efe843d8SDavid Gibson /* 6081efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6082efe843d8SDavid Gibson * simple: 6083fcf5ef2aSThomas Huth * 6084fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6085fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6086fcf5ef2aSThomas Huth */ 6087fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6088fcf5ef2aSThomas Huth } 6089fcf5ef2aSThomas Huth 6090fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6091fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6092fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6093fcf5ef2aSThomas Huth { \ 60949f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6095fcf5ef2aSThomas Huth } 6096fcf5ef2aSThomas Huth 6097fcf5ef2aSThomas Huth #else 6098fcf5ef2aSThomas Huth 6099fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6100fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6101fcf5ef2aSThomas Huth { \ 61029f0cf041SMatheus Ferst CHK_SV(ctx); \ 6103fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6104fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6105fcf5ef2aSThomas Huth return; \ 6106fcf5ef2aSThomas Huth } \ 6107efe843d8SDavid Gibson /* \ 6108efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6109fcf5ef2aSThomas Huth * simple: \ 6110fcf5ef2aSThomas Huth * \ 6111fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6112fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6113fcf5ef2aSThomas Huth */ \ 6114fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6115fcf5ef2aSThomas Huth } 6116fcf5ef2aSThomas Huth 6117fcf5ef2aSThomas Huth #endif 6118fcf5ef2aSThomas Huth 6119fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6120fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6121fcf5ef2aSThomas Huth 61221a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 61231a404c91SMark Cave-Ayland { 6124e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 61251a404c91SMark Cave-Ayland } 61261a404c91SMark Cave-Ayland 61271a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 61281a404c91SMark Cave-Ayland { 6129e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 61304b65b6e7SVíctor Colombo /* 61314b65b6e7SVíctor Colombo * Before PowerISA v3.1 the result of doubleword 1 of the VSR 61324b65b6e7SVíctor Colombo * corresponding to the target FPR was undefined. However, 61334b65b6e7SVíctor Colombo * most (if not all) real hardware were setting the result to 0. 61344b65b6e7SVíctor Colombo * Starting at ISA v3.1, the result for doubleword 1 is now defined 61354b65b6e7SVíctor Colombo * to be 0. 61364b65b6e7SVíctor Colombo */ 61374b65b6e7SVíctor Colombo tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 61381a404c91SMark Cave-Ayland } 61391a404c91SMark Cave-Ayland 6140c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6141c4a18dbfSMark Cave-Ayland { 614237da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6143c4a18dbfSMark Cave-Ayland } 6144c4a18dbfSMark Cave-Ayland 6145c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6146c4a18dbfSMark Cave-Ayland { 614737da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6148c4a18dbfSMark Cave-Ayland } 6149c4a18dbfSMark Cave-Ayland 6150c9826ae9SRichard Henderson /* 6151f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6152f2aabda8SRichard Henderson */ 6153d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6154d39b2cc7SLuis Pires { 6155d39b2cc7SLuis Pires return x * 2; 6156d39b2cc7SLuis Pires } 6157d39b2cc7SLuis Pires 6158f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6159f2aabda8SRichard Henderson { 6160f2aabda8SRichard Henderson return x * 4; 6161f2aabda8SRichard Henderson } 6162f2aabda8SRichard Henderson 6163e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6164e10271e1SMatheus Ferst { 6165e10271e1SMatheus Ferst return x * 16; 6166e10271e1SMatheus Ferst } 6167e10271e1SMatheus Ferst 6168670f1da3SVíctor Colombo static int64_t dw_compose_ea(DisasContext *ctx, int x) 6169670f1da3SVíctor Colombo { 6170670f1da3SVíctor Colombo return deposit64(0xfffffffffffffe00, 3, 6, x); 6171670f1da3SVíctor Colombo } 6172670f1da3SVíctor Colombo 6173f2aabda8SRichard Henderson /* 6174c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6175c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6176c9826ae9SRichard Henderson * proper variable. 6177c9826ae9SRichard Henderson */ 6178c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6179c9826ae9SRichard Henderson do { \ 6180c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6181c9826ae9SRichard Henderson return false; \ 6182c9826ae9SRichard Henderson } \ 6183c9826ae9SRichard Henderson } while (0) 6184c9826ae9SRichard Henderson 6185c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6186c9826ae9SRichard Henderson do { \ 6187c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6188c9826ae9SRichard Henderson return false; \ 6189c9826ae9SRichard Henderson } \ 6190c9826ae9SRichard Henderson } while (0) 6191c9826ae9SRichard Henderson 6192c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6193c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6194c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6195c9826ae9SRichard Henderson #else 6196c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6197c9826ae9SRichard Henderson #endif 6198c9826ae9SRichard Henderson 6199e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6200e2205a46SBruno Larsen do { \ 6201e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6202e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6203e2205a46SBruno Larsen return true; \ 6204e2205a46SBruno Larsen } \ 6205e2205a46SBruno Larsen } while (0) 6206e2205a46SBruno Larsen 62078226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 62088226cb2dSBruno Larsen (billionai) do { \ 62098226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 62108226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 62118226cb2dSBruno Larsen (billionai) return true; \ 62128226cb2dSBruno Larsen (billionai) } \ 62138226cb2dSBruno Larsen (billionai) } while (0) 62148226cb2dSBruno Larsen (billionai) 621586057426SFernando Valle #define REQUIRE_FPU(ctx) \ 621686057426SFernando Valle do { \ 621786057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 621886057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 621986057426SFernando Valle return true; \ 622086057426SFernando Valle } \ 622186057426SFernando Valle } while (0) 622286057426SFernando Valle 6223fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6224fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6225fc34e81aSMatheus Ferst do { \ 6226fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6227fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6228fc34e81aSMatheus Ferst return true; \ 6229fc34e81aSMatheus Ferst } \ 6230fc34e81aSMatheus Ferst } while (0) 6231fc34e81aSMatheus Ferst 6232fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6233fc34e81aSMatheus Ferst do { \ 6234e8db3cc7SMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6235fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6236fc34e81aSMatheus Ferst return true; \ 6237fc34e81aSMatheus Ferst } \ 6238fc34e81aSMatheus Ferst } while (0) 6239fc34e81aSMatheus Ferst #else 6240fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6241fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6242fc34e81aSMatheus Ferst #endif 6243fc34e81aSMatheus Ferst 6244f2aabda8SRichard Henderson /* 6245f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6246f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6247f2aabda8SRichard Henderson */ 6248f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6249f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6250f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 625119f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 625219f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 625319f0862dSLuis Pires { \ 625419f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 625519f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 625619f0862dSLuis Pires } 625719f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 625819f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 625919f0862dSLuis Pires { \ 626019f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 626119f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 626219f0862dSLuis Pires } 6263f2aabda8SRichard Henderson 6264f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6265f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6266f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 626719f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 626819f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 626919f0862dSLuis Pires { \ 627019f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 627119f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 627219f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 627319f0862dSLuis Pires } 6274f2aabda8SRichard Henderson 6275f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6276f2aabda8SRichard Henderson 6277f2aabda8SRichard Henderson 627899082815SRichard Henderson #include "decode-insn32.c.inc" 627999082815SRichard Henderson #include "decode-insn64.c.inc" 6280565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6281565cb109SGustavo Romero 6282725b2d4dSFernando Eckhardt Valle /* 6283725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6284725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6285725b2d4dSFernando Eckhardt Valle */ 6286725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6287725b2d4dSFernando Eckhardt Valle { 6288725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6289725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6290725b2d4dSFernando Eckhardt Valle d->si = a->si; 6291725b2d4dSFernando Eckhardt Valle if (a->r) { 6292725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6293725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6294725b2d4dSFernando Eckhardt Valle return false; 6295725b2d4dSFernando Eckhardt Valle } 6296725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6297725b2d4dSFernando Eckhardt Valle } 6298725b2d4dSFernando Eckhardt Valle return true; 6299725b2d4dSFernando Eckhardt Valle } 6300725b2d4dSFernando Eckhardt Valle 630199082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 630299082815SRichard Henderson 6303139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6304fcf5ef2aSThomas Huth 6305139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6306fcf5ef2aSThomas Huth 6307139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6308fcf5ef2aSThomas Huth 6309139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6310fcf5ef2aSThomas Huth 6311139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6312fcf5ef2aSThomas Huth 63131f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 63141f26c751SDaniel Henrique Barboza 631598f43417SMatheus Ferst #include "translate/processor-ctrl-impl.c.inc" 631698f43417SMatheus Ferst 6317016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6318016b6e1dSLeandro Lupori 631920e2d04eSLeandro Lupori /* Handles lfdp */ 63205cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 63215cb091a4SNikunj A Dadhania { 632220e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 63235cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 63245cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 63255cb091a4SNikunj A Dadhania } 63265cb091a4SNikunj A Dadhania } 63275cb091a4SNikunj A Dadhania return gen_invalid(ctx); 63285cb091a4SNikunj A Dadhania } 63295cb091a4SNikunj A Dadhania 633020e2d04eSLeandro Lupori /* Handles stfdp */ 6331e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6332e3001664SNikunj A Dadhania { 633320e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 633420e2d04eSLeandro Lupori /* stfdp */ 6335e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6336e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6337e3001664SNikunj A Dadhania } 6338e3001664SNikunj A Dadhania } 6339e3001664SNikunj A Dadhania return gen_invalid(ctx); 6340e3001664SNikunj A Dadhania } 6341e3001664SNikunj A Dadhania 63429d69cfa2SLijun Pan #if defined(TARGET_PPC64) 63439d69cfa2SLijun Pan /* brd */ 63449d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 63459d69cfa2SLijun Pan { 63469d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 63479d69cfa2SLijun Pan } 63489d69cfa2SLijun Pan 63499d69cfa2SLijun Pan /* brw */ 63509d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 63519d69cfa2SLijun Pan { 63529d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 63539d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 63549d69cfa2SLijun Pan 63559d69cfa2SLijun Pan } 63569d69cfa2SLijun Pan 63579d69cfa2SLijun Pan /* brh */ 63589d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 63599d69cfa2SLijun Pan { 6360491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 63619d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 63629d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 63639d69cfa2SLijun Pan 63649d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6365491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6366491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 63679d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 63689d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 63699d69cfa2SLijun Pan } 63709d69cfa2SLijun Pan #endif 63719d69cfa2SLijun Pan 6372fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 63739d69cfa2SLijun Pan #if defined(TARGET_PPC64) 63749d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 63759d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 63769d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 63779d69cfa2SLijun Pan #endif 6378fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6379fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6380fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6381fcf5ef2aSThomas Huth #endif 6382fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6383fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6384fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6385fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6386fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6387fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6388fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6389fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6390fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6391fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6392fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6393fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6394fcf5ef2aSThomas Huth #endif 6395fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6396fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6397fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6398fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6399fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6400fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6401fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 640280b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6403b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 640480b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6405fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6406fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6407fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6408fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6409fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6410fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6411fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6412fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6413fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6414fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6415fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6416fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6417fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6418fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6419fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6420fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6421fcf5ef2aSThomas Huth #endif 6422fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6423fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6424fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6425fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6426fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6427fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6428fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6429fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6430fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6431fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6432fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6433fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6434fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6435fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6436fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6437fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6438fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6439fcf5ef2aSThomas Huth #endif 64405cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 64415cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 644272b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6443e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6444fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6445fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6446fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6447fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6448fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6449fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6450c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6451fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6452fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6453fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6454fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6455a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6456a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6457fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6458fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6459fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6460fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6461a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6462a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6463fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6464fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6465fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6466fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6467fcf5ef2aSThomas Huth #endif 6468fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 64690c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 64700c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 64710c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6472fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6473fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6474fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6475fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6476fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6477fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6478fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6479fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6480fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 64813c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 64823c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 64833c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 64843c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 64853c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 64863c89b8d6SNicholas Piggin #endif 6487cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6488fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6489fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6490fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6491fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6492fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6493fcf5ef2aSThomas Huth #endif 64943c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 64953c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 64963c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6497fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6498fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6499fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6500fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6501fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6502fcf5ef2aSThomas Huth #endif 6503fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6504fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6505fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6506fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6507fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6508fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6509fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6510fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6511fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6512b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6513fcf5ef2aSThomas Huth #endif 6514fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6515fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6516fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 651750728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6518fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6519fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 652050728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6521fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 652250728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6523fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 652450728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6525fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6526e64645baSBernhard Beschow GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6527fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 652850728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6529fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 653099d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6531fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6532fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 653350728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6534fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6535fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6536fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6537fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6538fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6539fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6540fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6541fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6542fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6543fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6544fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6545fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6546fcf5ef2aSThomas Huth #endif 6547fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6548efe843d8SDavid Gibson /* 6549efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6550efe843d8SDavid Gibson * different ISA versions 6551efe843d8SDavid Gibson */ 6552fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6553fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6554fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6555fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6556fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6557fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6558fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6559fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6560fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6561fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6562fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6563fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6564fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6565fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6566fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6567fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6568fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6569fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6570fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6571fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6572fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6573fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6574fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6575fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6576fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6577fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6578fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6579fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6580fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6581fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6582fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6583fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6584fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6585fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6586fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6587fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6588fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6589fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6590fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6591fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6592fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 659327a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6594fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6595fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 65960c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 65970c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6598fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6599fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6600fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6601fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6602fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6603fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6604fcf5ef2aSThomas Huth PPC2_ISA300), 6605fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6606fcf5ef2aSThomas Huth #endif 6607fcf5ef2aSThomas Huth 6608fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6609fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6610fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6611fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6612fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6613fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6614fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6615fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6616fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6617fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6618fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6619fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6620fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6621fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6622fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 66234c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6624fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6625fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6626fcf5ef2aSThomas Huth 6627fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6628fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6629fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6630fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6631fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6632fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6633fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6634fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6635fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6636fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6637fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6638fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6639fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6640fcf5ef2aSThomas Huth 6641fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6642fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6643fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6644fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6645fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6646fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6647fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6648fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6649fcf5ef2aSThomas Huth 6650fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6651fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6652fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6653fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6654fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6655fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6656fcf5ef2aSThomas Huth 6657fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6658fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6659fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6660fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6661fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6662fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6663fcf5ef2aSThomas Huth #endif 6664fcf5ef2aSThomas Huth 6665fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6666fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6667fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6668fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6669fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6670fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6671fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6672fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6673fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6674fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6675fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6676fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6677fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6678fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6679fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6680fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6681fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6682fcf5ef2aSThomas Huth 6683fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6684fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6685fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6686fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6687fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6688fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6689fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6690fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6691fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6692fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6693fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6694fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6695fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6696fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6697fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6698fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6699fcf5ef2aSThomas Huth #endif 6700fcf5ef2aSThomas Huth 6701fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6702fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6703fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6704fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6705fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6706fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6707fcf5ef2aSThomas Huth PPC_64B) 6708fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6709fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6710fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6711fcf5ef2aSThomas Huth PPC_64B), \ 6712fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6713fcf5ef2aSThomas Huth PPC_64B), \ 6714fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6715fcf5ef2aSThomas Huth PPC_64B) 6716fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6717fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6718fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6719fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6720fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6721fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6722fcf5ef2aSThomas Huth #endif 6723fcf5ef2aSThomas Huth 6724fcf5ef2aSThomas Huth #undef GEN_LDX_E 6725fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6726fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6727fcf5ef2aSThomas Huth 6728fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6729fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6730fcf5ef2aSThomas Huth 6731fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6732fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6733fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6734fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6735fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6736fcf5ef2aSThomas Huth #endif 6737fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6738fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6739fcf5ef2aSThomas Huth 674050728199SRoman Kapl /* External PID based load */ 674150728199SRoman Kapl #undef GEN_LDEPX 674250728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 674350728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 674450728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 674550728199SRoman Kapl 674650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 674750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 674850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 674950728199SRoman Kapl #if defined(TARGET_PPC64) 6750fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 675150728199SRoman Kapl #endif 675250728199SRoman Kapl 6753fcf5ef2aSThomas Huth #undef GEN_STX_E 6754fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 67550123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6756fcf5ef2aSThomas Huth 6757fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6758fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6759fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6760fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6761fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6762fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6763fcf5ef2aSThomas Huth #endif 6764fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6765fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6766fcf5ef2aSThomas Huth 676750728199SRoman Kapl #undef GEN_STEPX 676850728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 676950728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 677050728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 677150728199SRoman Kapl 677250728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 677350728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 677450728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 677550728199SRoman Kapl #if defined(TARGET_PPC64) 6776fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 677750728199SRoman Kapl #endif 677850728199SRoman Kapl 6779fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6780fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6781fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6782fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6783fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6784fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6785fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6786fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6787fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6788fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6789fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6790fcf5ef2aSThomas Huth 6791fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6792fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6793fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6794fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6795fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6796fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6797fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6798fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6799fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6800fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6801fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6802fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6803fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6804fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6805fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6806fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6807fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6808fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6809fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6810fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6811fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6812fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6813fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6814fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6815fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6816fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6817fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6818fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6819fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6820fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6821fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6822fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6823fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6824fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6825fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6826fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6827fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6828fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6829fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6830fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6831fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6832fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6833fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6834fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6835fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6836fcf5ef2aSThomas Huth 6837fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6838fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6839fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6840fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6841fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6842fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6843fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6844fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6845fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6846fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6847fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6848fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6849fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6850fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6851fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6852fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6853fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6854fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6855fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6856fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6857fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6858fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6859fcf5ef2aSThomas Huth 6860139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 6861fcf5ef2aSThomas Huth 6862139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 6863fcf5ef2aSThomas Huth 6864139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 6865fcf5ef2aSThomas Huth 6866139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 6867fcf5ef2aSThomas Huth }; 6868fcf5ef2aSThomas Huth 68697468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 68707468e2c8SBruno Larsen (billionai) /* Opcode types */ 68717468e2c8SBruno Larsen (billionai) enum { 68727468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 68737468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 68747468e2c8SBruno Larsen (billionai) }; 68757468e2c8SBruno Larsen (billionai) 68767468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 68777468e2c8SBruno Larsen (billionai) 68787468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 68797468e2c8SBruno Larsen (billionai) { 68807468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 68817468e2c8SBruno Larsen (billionai) } 68827468e2c8SBruno Larsen (billionai) 68837468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 68847468e2c8SBruno Larsen (billionai) { 68857468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 68867468e2c8SBruno Larsen (billionai) } 68877468e2c8SBruno Larsen (billionai) 68887468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 68897468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 68907468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 68917468e2c8SBruno Larsen (billionai) { 68927468e2c8SBruno Larsen (billionai) int i; 68937468e2c8SBruno Larsen (billionai) 68947468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 68957468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 68967468e2c8SBruno Larsen (billionai) } 68977468e2c8SBruno Larsen (billionai) } 68987468e2c8SBruno Larsen (billionai) 68997468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 69007468e2c8SBruno Larsen (billionai) { 69017468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 69027468e2c8SBruno Larsen (billionai) 69037468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 69047468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 69057468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 69067468e2c8SBruno Larsen (billionai) 69077468e2c8SBruno Larsen (billionai) return 0; 69087468e2c8SBruno Larsen (billionai) } 69097468e2c8SBruno Larsen (billionai) 69107468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 69117468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69127468e2c8SBruno Larsen (billionai) { 69137468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 69147468e2c8SBruno Larsen (billionai) return -1; 69157468e2c8SBruno Larsen (billionai) } 69167468e2c8SBruno Larsen (billionai) table[idx] = handler; 69177468e2c8SBruno Larsen (billionai) 69187468e2c8SBruno Larsen (billionai) return 0; 69197468e2c8SBruno Larsen (billionai) } 69207468e2c8SBruno Larsen (billionai) 69217468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 69227468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 69237468e2c8SBruno Larsen (billionai) { 69247468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 69257468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 69267468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 69277468e2c8SBruno Larsen (billionai) return -1; 69287468e2c8SBruno Larsen (billionai) } 69297468e2c8SBruno Larsen (billionai) 69307468e2c8SBruno Larsen (billionai) return 0; 69317468e2c8SBruno Larsen (billionai) } 69327468e2c8SBruno Larsen (billionai) 69337468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 69347468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 69357468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69367468e2c8SBruno Larsen (billionai) { 69377468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 69387468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 69397468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 69407468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 69417468e2c8SBruno Larsen (billionai) return -1; 69427468e2c8SBruno Larsen (billionai) } 69437468e2c8SBruno Larsen (billionai) } else { 69447468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 69457468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 69467468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 69477468e2c8SBruno Larsen (billionai) return -1; 69487468e2c8SBruno Larsen (billionai) } 69497468e2c8SBruno Larsen (billionai) } 69507468e2c8SBruno Larsen (billionai) if (handler != NULL && 69517468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 69527468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 69537468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 69547468e2c8SBruno Larsen (billionai) return -1; 69557468e2c8SBruno Larsen (billionai) } 69567468e2c8SBruno Larsen (billionai) 69577468e2c8SBruno Larsen (billionai) return 0; 69587468e2c8SBruno Larsen (billionai) } 69597468e2c8SBruno Larsen (billionai) 69607468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 69617468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 69627468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69637468e2c8SBruno Larsen (billionai) { 69647468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 69657468e2c8SBruno Larsen (billionai) } 69667468e2c8SBruno Larsen (billionai) 69677468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 69687468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 69697468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 69707468e2c8SBruno Larsen (billionai) { 69717468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 69727468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 69737468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 69747468e2c8SBruno Larsen (billionai) return -1; 69757468e2c8SBruno Larsen (billionai) } 69767468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 69777468e2c8SBruno Larsen (billionai) handler) < 0) { 69787468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 69797468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 69807468e2c8SBruno Larsen (billionai) return -1; 69817468e2c8SBruno Larsen (billionai) } 69827468e2c8SBruno Larsen (billionai) 69837468e2c8SBruno Larsen (billionai) return 0; 69847468e2c8SBruno Larsen (billionai) } 69857468e2c8SBruno Larsen (billionai) 69867468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 69877468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 69887468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 69897468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69907468e2c8SBruno Larsen (billionai) { 69917468e2c8SBruno Larsen (billionai) opc_handler_t **table; 69927468e2c8SBruno Larsen (billionai) 69937468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 69947468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 69957468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 69967468e2c8SBruno Larsen (billionai) return -1; 69977468e2c8SBruno Larsen (billionai) } 69987468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 69997468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 70007468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 70017468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70027468e2c8SBruno Larsen (billionai) return -1; 70037468e2c8SBruno Larsen (billionai) } 70047468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 70057468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 70067468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70077468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 70087468e2c8SBruno Larsen (billionai) return -1; 70097468e2c8SBruno Larsen (billionai) } 70107468e2c8SBruno Larsen (billionai) return 0; 70117468e2c8SBruno Larsen (billionai) } 70127468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 70137468e2c8SBruno Larsen (billionai) { 70147468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 70157468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 70167468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 70177468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 70187468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 70197468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 70207468e2c8SBruno Larsen (billionai) return -1; 70217468e2c8SBruno Larsen (billionai) } 70227468e2c8SBruno Larsen (billionai) } else { 70237468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 70247468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 70257468e2c8SBruno Larsen (billionai) return -1; 70267468e2c8SBruno Larsen (billionai) } 70277468e2c8SBruno Larsen (billionai) } 70287468e2c8SBruno Larsen (billionai) } else { 70297468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 70307468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 70317468e2c8SBruno Larsen (billionai) return -1; 70327468e2c8SBruno Larsen (billionai) } 70337468e2c8SBruno Larsen (billionai) } 70347468e2c8SBruno Larsen (billionai) } else { 70357468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 70367468e2c8SBruno Larsen (billionai) return -1; 70377468e2c8SBruno Larsen (billionai) } 70387468e2c8SBruno Larsen (billionai) } 70397468e2c8SBruno Larsen (billionai) 70407468e2c8SBruno Larsen (billionai) return 0; 70417468e2c8SBruno Larsen (billionai) } 70427468e2c8SBruno Larsen (billionai) 70437468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 70447468e2c8SBruno Larsen (billionai) { 70457468e2c8SBruno Larsen (billionai) int i, count, tmp; 70467468e2c8SBruno Larsen (billionai) 70477468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 70487468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 70497468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 70507468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 70517468e2c8SBruno Larsen (billionai) } 70527468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 70537468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 70547468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 70557468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 70567468e2c8SBruno Larsen (billionai) if (tmp == 0) { 70577468e2c8SBruno Larsen (billionai) free(table[i]); 70587468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 70597468e2c8SBruno Larsen (billionai) } else { 70607468e2c8SBruno Larsen (billionai) count++; 70617468e2c8SBruno Larsen (billionai) } 70627468e2c8SBruno Larsen (billionai) } else { 70637468e2c8SBruno Larsen (billionai) count++; 70647468e2c8SBruno Larsen (billionai) } 70657468e2c8SBruno Larsen (billionai) } 70667468e2c8SBruno Larsen (billionai) } 70677468e2c8SBruno Larsen (billionai) 70687468e2c8SBruno Larsen (billionai) return count; 70697468e2c8SBruno Larsen (billionai) } 70707468e2c8SBruno Larsen (billionai) 70717468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 70727468e2c8SBruno Larsen (billionai) { 70737468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 70747468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 70757468e2c8SBruno Larsen (billionai) } 70767468e2c8SBruno Larsen (billionai) } 70777468e2c8SBruno Larsen (billionai) 70787468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 70797468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 70807468e2c8SBruno Larsen (billionai) { 70817468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 70827468e2c8SBruno Larsen (billionai) opcode_t *opc; 70837468e2c8SBruno Larsen (billionai) 70847468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 70857468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 70867468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 70877468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 70887468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 70897468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 70907468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 70917468e2c8SBruno Larsen (billionai) opc->opc3); 70927468e2c8SBruno Larsen (billionai) return; 70937468e2c8SBruno Larsen (billionai) } 70947468e2c8SBruno Larsen (billionai) } 70957468e2c8SBruno Larsen (billionai) } 70967468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 70977468e2c8SBruno Larsen (billionai) fflush(stdout); 70987468e2c8SBruno Larsen (billionai) fflush(stderr); 70997468e2c8SBruno Larsen (billionai) } 71007468e2c8SBruno Larsen (billionai) 71017468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 71027468e2c8SBruno Larsen (billionai) { 71037468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 71047468e2c8SBruno Larsen (billionai) int i, j, k; 71057468e2c8SBruno Larsen (billionai) 71067468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 71077468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 71087468e2c8SBruno Larsen (billionai) continue; 71097468e2c8SBruno Larsen (billionai) } 71107468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 71117468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 71127468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 71137468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 71147468e2c8SBruno Larsen (billionai) continue; 71157468e2c8SBruno Larsen (billionai) } 71167468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 71177468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 71187468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 71197468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 71207468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 71217468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 71227468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71237468e2c8SBruno Larsen (billionai) } 71247468e2c8SBruno Larsen (billionai) } 71257468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 71267468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71277468e2c8SBruno Larsen (billionai) } 71287468e2c8SBruno Larsen (billionai) } 71297468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 71307468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71317468e2c8SBruno Larsen (billionai) } 71327468e2c8SBruno Larsen (billionai) } 71337468e2c8SBruno Larsen (billionai) } 71347468e2c8SBruno Larsen (billionai) 71357468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 71367468e2c8SBruno Larsen (billionai) { 71377468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 71387468e2c8SBruno Larsen (billionai) 71397468e2c8SBruno Larsen (billionai) /* 71407468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 71417468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 71427468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 71437468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 71447468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 71457468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 71467468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 71477468e2c8SBruno Larsen (billionai) */ 71487468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 71497468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 71507468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 71517468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 71527468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 71537468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 71547468e2c8SBruno Larsen (billionai) } 71557468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 71567468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 71577468e2c8SBruno Larsen (billionai) return 0; 71587468e2c8SBruno Larsen (billionai) } 71597468e2c8SBruno Larsen (billionai) 7160624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7161624cb07fSRichard Henderson { 7162624cb07fSRichard Henderson opc_handler_t **table, *handler; 7163624cb07fSRichard Henderson uint32_t inval; 7164624cb07fSRichard Henderson 7165624cb07fSRichard Henderson ctx->opcode = insn; 7166624cb07fSRichard Henderson 7167624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7168624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7169624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7170624cb07fSRichard Henderson 7171624cb07fSRichard Henderson table = cpu->opcodes; 7172624cb07fSRichard Henderson handler = table[opc1(insn)]; 7173624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7174624cb07fSRichard Henderson table = ind_table(handler); 7175624cb07fSRichard Henderson handler = table[opc2(insn)]; 7176624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7177624cb07fSRichard Henderson table = ind_table(handler); 7178624cb07fSRichard Henderson handler = table[opc3(insn)]; 7179624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7180624cb07fSRichard Henderson table = ind_table(handler); 7181624cb07fSRichard Henderson handler = table[opc4(insn)]; 7182624cb07fSRichard Henderson } 7183624cb07fSRichard Henderson } 7184624cb07fSRichard Henderson } 7185624cb07fSRichard Henderson 7186624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7187624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7188624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7189624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7190624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7191624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7192624cb07fSRichard Henderson insn, ctx->cia); 7193624cb07fSRichard Henderson return false; 7194624cb07fSRichard Henderson } 7195624cb07fSRichard Henderson 7196624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7197624cb07fSRichard Henderson && Rc(insn))) { 7198624cb07fSRichard Henderson inval = handler->inval2; 7199624cb07fSRichard Henderson } else { 7200624cb07fSRichard Henderson inval = handler->inval1; 7201624cb07fSRichard Henderson } 7202624cb07fSRichard Henderson 7203624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7204624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7205624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7206624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7207624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7208624cb07fSRichard Henderson insn, ctx->cia); 7209624cb07fSRichard Henderson return false; 7210624cb07fSRichard Henderson } 7211624cb07fSRichard Henderson 7212624cb07fSRichard Henderson handler->handler(ctx); 7213624cb07fSRichard Henderson return true; 7214624cb07fSRichard Henderson } 7215624cb07fSRichard Henderson 7216b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7217fcf5ef2aSThomas Huth { 7218b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 72199c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 72202df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7221fcf5ef2aSThomas Huth 7222b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 72232df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7224d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 72252df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 72262df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7227b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7228b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7229b0c2d521SEmilio G. Cota ctx->access_type = -1; 7230d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 72312df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7232b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 72330e3bf489SRoman Kapl ctx->flags = env->flags; 7234fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72352df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7236b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7237fcf5ef2aSThomas Huth #endif 7238e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7239d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7240fcf5ef2aSThomas Huth 72412df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 72422df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 72432df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 72442df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 72452df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7246f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 72471db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7248f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7249f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 72508b3d1c49SLeandro Lupori ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 72518b3d1c49SLeandro Lupori ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 725246d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 72532df4fe7aSRichard Henderson 7254b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 72552df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 72562df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 72579498d103SRichard Henderson ctx->base.max_insns = 1; 7258efe843d8SDavid Gibson } 72592df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7260b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7261efe843d8SDavid Gibson } 726213b45575SRichard Henderson } 7263fcf5ef2aSThomas Huth 7264b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7265b0c2d521SEmilio G. Cota { 7266b0c2d521SEmilio G. Cota } 7267fcf5ef2aSThomas Huth 7268b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7269b0c2d521SEmilio G. Cota { 7270b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7271b0c2d521SEmilio G. Cota } 7272b0c2d521SEmilio G. Cota 727399082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 727499082815SRichard Henderson { 727599082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 727699082815SRichard Henderson return opc1(insn) == 1; 727799082815SRichard Henderson } 727899082815SRichard Henderson 7279b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7280b0c2d521SEmilio G. Cota { 7281b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 728228876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7283b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 728499082815SRichard Henderson target_ulong pc; 7285624cb07fSRichard Henderson uint32_t insn; 7286624cb07fSRichard Henderson bool ok; 7287b0c2d521SEmilio G. Cota 7288fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7289fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7290b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7291b0c2d521SEmilio G. Cota 729299082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 72934e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 729499082815SRichard Henderson ctx->base.pc_next = pc += 4; 7295fcf5ef2aSThomas Huth 729699082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 729799082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 729899082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 729999082815SRichard Henderson } else if ((pc & 63) == 0) { 730099082815SRichard Henderson /* 730199082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 730299082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 730399082815SRichard Henderson * 64-byte address boundary (system alignment error). 730499082815SRichard Henderson */ 730599082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 730699082815SRichard Henderson ok = true; 730799082815SRichard Henderson } else { 73084e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 73094e116893SIlya Leoshkevich need_byteswap(ctx)); 731099082815SRichard Henderson ctx->base.pc_next = pc += 4; 731199082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 731299082815SRichard Henderson } 7313624cb07fSRichard Henderson if (!ok) { 7314624cb07fSRichard Henderson gen_invalid(ctx); 7315fcf5ef2aSThomas Huth } 7316624cb07fSRichard Henderson 731764a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 731899082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 731964a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 732064a0f644SRichard Henderson } 7321fcf5ef2aSThomas Huth } 7322b0c2d521SEmilio G. Cota 7323b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7324b0c2d521SEmilio G. Cota { 7325b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7326a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7327a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7328b0c2d521SEmilio G. Cota 7329a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7330a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 73313d8a5b69SRichard Henderson return; 73323d8a5b69SRichard Henderson } 73333d8a5b69SRichard Henderson 7334a9b5b3d0SRichard Henderson /* Honor single stepping. */ 73359498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 73369498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 7337a9b5b3d0SRichard Henderson switch (is_jmp) { 7338a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7339a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7340a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7341a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7342a9b5b3d0SRichard Henderson break; 7343a9b5b3d0SRichard Henderson case DISAS_EXIT: 7344a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7345a9b5b3d0SRichard Henderson break; 7346a9b5b3d0SRichard Henderson default: 7347a9b5b3d0SRichard Henderson g_assert_not_reached(); 7348fcf5ef2aSThomas Huth } 734913b45575SRichard Henderson 7350a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 7351a9b5b3d0SRichard Henderson return; 7352a9b5b3d0SRichard Henderson } 7353a9b5b3d0SRichard Henderson 7354a9b5b3d0SRichard Henderson switch (is_jmp) { 7355a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7356a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 735746d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7358a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7359a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7360a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7361a9b5b3d0SRichard Henderson break; 7362a9b5b3d0SRichard Henderson } 7363a9b5b3d0SRichard Henderson /* fall through */ 7364a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7365a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7366a9b5b3d0SRichard Henderson /* fall through */ 7367a9b5b3d0SRichard Henderson case DISAS_CHAIN: 736846d396bdSDaniel Henrique Barboza /* 736946d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 737046d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 737146d396bdSDaniel Henrique Barboza */ 737246d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 737346d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 737446d396bdSDaniel Henrique Barboza } 737546d396bdSDaniel Henrique Barboza 7376a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7377a9b5b3d0SRichard Henderson break; 7378a9b5b3d0SRichard Henderson 7379a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7380a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7381a9b5b3d0SRichard Henderson /* fall through */ 7382a9b5b3d0SRichard Henderson case DISAS_EXIT: 738346d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 738407ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7385a9b5b3d0SRichard Henderson break; 7386a9b5b3d0SRichard Henderson 7387a9b5b3d0SRichard Henderson default: 7388a9b5b3d0SRichard Henderson g_assert_not_reached(); 7389fcf5ef2aSThomas Huth } 7390fcf5ef2aSThomas Huth } 7391b0c2d521SEmilio G. Cota 73928eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 73938eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7394b0c2d521SEmilio G. Cota { 73958eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 73968eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7397b0c2d521SEmilio G. Cota } 7398b0c2d521SEmilio G. Cota 7399b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7400b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7401b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7402b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7403b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7404b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7405b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7406b0c2d521SEmilio G. Cota }; 7407b0c2d521SEmilio G. Cota 7408597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7409306c8721SRichard Henderson target_ulong pc, void *host_pc) 7410b0c2d521SEmilio G. Cota { 7411b0c2d521SEmilio G. Cota DisasContext ctx; 7412b0c2d521SEmilio G. Cota 7413306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7414fcf5ef2aSThomas Huth } 7415