1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 49efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 50fcf5ef2aSThomas Huth 51fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 53fcf5ef2aSThomas Huth #else 54fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 55fcf5ef2aSThomas Huth #endif 56fcf5ef2aSThomas Huth /*****************************************************************************/ 57fcf5ef2aSThomas Huth /* Code translation helpers */ 58fcf5ef2aSThomas Huth 59fcf5ef2aSThomas Huth /* global register indexes */ 60fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 61fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 62fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 63fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 64fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 65fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 66fcf5ef2aSThomas Huth static TCGv cpu_nip; 67fcf5ef2aSThomas Huth static TCGv cpu_msr; 68fcf5ef2aSThomas Huth static TCGv cpu_ctr; 69fcf5ef2aSThomas Huth static TCGv cpu_lr; 70fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 71fcf5ef2aSThomas Huth static TCGv cpu_cfar; 72fcf5ef2aSThomas Huth #endif 73dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 74fcf5ef2aSThomas Huth static TCGv cpu_reserve; 75253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 76fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 77fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth void ppc_translate_init(void) 82fcf5ef2aSThomas Huth { 83fcf5ef2aSThomas Huth int i; 84fcf5ef2aSThomas Huth char *p; 85fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 86fcf5ef2aSThomas Huth 87fcf5ef2aSThomas Huth p = cpu_reg_names; 88fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 91fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 92fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 93fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 94fcf5ef2aSThomas Huth p += 5; 95fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 96fcf5ef2aSThomas Huth } 97fcf5ef2aSThomas Huth 98fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 99fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 100fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 101fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 102fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 103fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 105fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 106fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 107fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 108fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth } 110fcf5ef2aSThomas Huth 111fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 112fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 115fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 118fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 124fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 125fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 126fcf5ef2aSThomas Huth #endif 127fcf5ef2aSThomas Huth 128fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 130fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 132fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 134fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 135fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 136dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 138dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 139dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 140fcf5ef2aSThomas Huth 141fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 142fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 143fcf5ef2aSThomas Huth "reserve_addr"); 144253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 145253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 146253ce7b2SNikunj A Dadhania "reserve_val"); 147fcf5ef2aSThomas Huth 148fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 149fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 150fcf5ef2aSThomas Huth 151fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 152efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 153efe843d8SDavid Gibson "access_type"); 154fcf5ef2aSThomas Huth } 155fcf5ef2aSThomas Huth 156fcf5ef2aSThomas Huth /* internal defines */ 157fcf5ef2aSThomas Huth struct DisasContext { 158b6bac4bcSEmilio G. Cota DisasContextBase base; 1592c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 160fcf5ef2aSThomas Huth uint32_t opcode; 161fcf5ef2aSThomas Huth /* Routine used to access memory */ 162fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 163fcf5ef2aSThomas Huth bool lazy_tlb_flush; 164fcf5ef2aSThomas Huth bool need_access_type; 165fcf5ef2aSThomas Huth int mem_idx; 166fcf5ef2aSThomas Huth int access_type; 167fcf5ef2aSThomas Huth /* Translation flags */ 16814776ab5STony Nguyen MemOp default_tcg_memop_mask; 169fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 170fcf5ef2aSThomas Huth bool sf_mode; 171fcf5ef2aSThomas Huth bool has_cfar; 172fcf5ef2aSThomas Huth #endif 173fcf5ef2aSThomas Huth bool fpu_enabled; 174fcf5ef2aSThomas Huth bool altivec_enabled; 175fcf5ef2aSThomas Huth bool vsx_enabled; 176fcf5ef2aSThomas Huth bool spe_enabled; 177fcf5ef2aSThomas Huth bool tm_enabled; 178c6fd28fdSSuraj Jitindar Singh bool gtse; 179fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 180fcf5ef2aSThomas Huth int singlestep_enabled; 1810e3bf489SRoman Kapl uint32_t flags; 182fcf5ef2aSThomas Huth uint64_t insns_flags; 183fcf5ef2aSThomas Huth uint64_t insns_flags2; 184fcf5ef2aSThomas Huth }; 185fcf5ef2aSThomas Huth 186a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 187a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 188a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 189a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 190a9b5b3d0SRichard Henderson 191fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 192fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 193fcf5ef2aSThomas Huth { 194fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 195fcf5ef2aSThomas Huth return ctx->le_mode; 196fcf5ef2aSThomas Huth #else 197fcf5ef2aSThomas Huth return !ctx->le_mode; 198fcf5ef2aSThomas Huth #endif 199fcf5ef2aSThomas Huth } 200fcf5ef2aSThomas Huth 201fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 202fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 203fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 204fcf5ef2aSThomas Huth #else 205fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 206fcf5ef2aSThomas Huth #endif 207fcf5ef2aSThomas Huth 208fcf5ef2aSThomas Huth struct opc_handler_t { 209fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 210fcf5ef2aSThomas Huth uint32_t inval1; 211fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 212fcf5ef2aSThomas Huth uint32_t inval2; 213fcf5ef2aSThomas Huth /* instruction type */ 214fcf5ef2aSThomas Huth uint64_t type; 215fcf5ef2aSThomas Huth /* extended instruction type */ 216fcf5ef2aSThomas Huth uint64_t type2; 217fcf5ef2aSThomas Huth /* handler */ 218fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 219fcf5ef2aSThomas Huth }; 220fcf5ef2aSThomas Huth 2210e3bf489SRoman Kapl /* SPR load/store helpers */ 2220e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2230e3bf489SRoman Kapl { 2240e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2250e3bf489SRoman Kapl } 2260e3bf489SRoman Kapl 2270e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2280e3bf489SRoman Kapl { 2290e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2300e3bf489SRoman Kapl } 2310e3bf489SRoman Kapl 232fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 233fcf5ef2aSThomas Huth { 234fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 235fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 236fcf5ef2aSThomas Huth ctx->access_type = access_type; 237fcf5ef2aSThomas Huth } 238fcf5ef2aSThomas Huth } 239fcf5ef2aSThomas Huth 240fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 241fcf5ef2aSThomas Huth { 242fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 243fcf5ef2aSThomas Huth nip = (uint32_t)nip; 244fcf5ef2aSThomas Huth } 245fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth 248fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 249fcf5ef2aSThomas Huth { 250fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 251fcf5ef2aSThomas Huth 252efe843d8SDavid Gibson /* 253efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 254efe843d8SDavid Gibson * faulting instruction 255fcf5ef2aSThomas Huth */ 2562c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 257fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 258fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 259fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 260fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 261fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2623d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 263fcf5ef2aSThomas Huth } 264fcf5ef2aSThomas Huth 265fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 266fcf5ef2aSThomas Huth { 267fcf5ef2aSThomas Huth TCGv_i32 t0; 268fcf5ef2aSThomas Huth 269efe843d8SDavid Gibson /* 270efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 271efe843d8SDavid Gibson * faulting instruction 272fcf5ef2aSThomas Huth */ 2732c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 274fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 275fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 276fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2773d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 278fcf5ef2aSThomas Huth } 279fcf5ef2aSThomas Huth 280fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 281fcf5ef2aSThomas Huth target_ulong nip) 282fcf5ef2aSThomas Huth { 283fcf5ef2aSThomas Huth TCGv_i32 t0; 284fcf5ef2aSThomas Huth 285fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 286fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 287fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 288fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2893d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 290fcf5ef2aSThomas Huth } 291fcf5ef2aSThomas Huth 292f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 293f5b6daacSRichard Henderson { 294f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 295f5b6daacSRichard Henderson gen_io_start(); 296f5b6daacSRichard Henderson /* 297f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 298f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 299f5b6daacSRichard Henderson * decide if we need to return to the main loop. 300f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 301f5b6daacSRichard Henderson */ 302f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 303f5b6daacSRichard Henderson } 304f5b6daacSRichard Henderson } 305f5b6daacSRichard Henderson 306e150ac89SRoman Kapl /* 307e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 308e150ac89SRoman Kapl * SPR registers for this exception. 309e150ac89SRoman Kapl * 310e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 311e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3120e3bf489SRoman Kapl */ 313e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3140e3bf489SRoman Kapl { 3150e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3160e3bf489SRoman Kapl target_ulong dbsr = 0; 317e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3180e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 319e150ac89SRoman Kapl } else { 320e150ac89SRoman Kapl /* Must have been branch */ 3210e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3220e3bf489SRoman Kapl } 3230e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3240e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3250e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3260e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3270e3bf489SRoman Kapl tcg_temp_free(t0); 3280e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3290e3bf489SRoman Kapl } else { 330e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3310e3bf489SRoman Kapl } 3320e3bf489SRoman Kapl } 3330e3bf489SRoman Kapl 334fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 335fcf5ef2aSThomas Huth { 3362736fc61SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); 3373d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 338fcf5ef2aSThomas Huth } 339fcf5ef2aSThomas Huth 340fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 341fcf5ef2aSThomas Huth { 342fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 343fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 344fcf5ef2aSThomas Huth } 345fcf5ef2aSThomas Huth 346fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 347fcf5ef2aSThomas Huth { 348fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 349fcf5ef2aSThomas Huth } 350fcf5ef2aSThomas Huth 351fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 352fcf5ef2aSThomas Huth { 353fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 354fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 355fcf5ef2aSThomas Huth } 356fcf5ef2aSThomas Huth 35737f219c8SBruno Larsen (billionai) /*****************************************************************************/ 35837f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 35937f219c8SBruno Larsen (billionai) 360a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 36137f219c8SBruno Larsen (billionai) { 36237f219c8SBruno Larsen (billionai) #if 0 36337f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 36437f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 36537f219c8SBruno Larsen (billionai) #endif 36637f219c8SBruno Larsen (billionai) } 36737f219c8SBruno Larsen (billionai) 36837f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 36937f219c8SBruno Larsen (billionai) 37037f219c8SBruno Larsen (billionai) /* 37137f219c8SBruno Larsen (billionai) * Generic callbacks: 37237f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 37337f219c8SBruno Larsen (billionai) */ 37437f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 37537f219c8SBruno Larsen (billionai) { 37637f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 37737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 37837f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 37937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 38037f219c8SBruno Larsen (billionai) #endif 38137f219c8SBruno Larsen (billionai) } 38237f219c8SBruno Larsen (billionai) 383a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 38437f219c8SBruno Larsen (billionai) { 38537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 38637f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 38737f219c8SBruno Larsen (billionai) } 38837f219c8SBruno Larsen (billionai) 38937f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 39037f219c8SBruno Larsen (billionai) { 39137f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39337f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 39437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39537f219c8SBruno Larsen (billionai) #endif 39637f219c8SBruno Larsen (billionai) } 39737f219c8SBruno Larsen (billionai) 398a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 39937f219c8SBruno Larsen (billionai) { 40037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 40137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 40237f219c8SBruno Larsen (billionai) } 40337f219c8SBruno Larsen (billionai) 40437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 405a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 40637f219c8SBruno Larsen (billionai) { 40737f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 40837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 40937f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 41037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 41137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 41237f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41337f219c8SBruno Larsen (billionai) #else 41437f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 41537f219c8SBruno Larsen (billionai) #endif 41637f219c8SBruno Larsen (billionai) } 41737f219c8SBruno Larsen (billionai) 418a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 41937f219c8SBruno Larsen (billionai) { 42037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 42237f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 42337f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 42437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 42537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42737f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 42837f219c8SBruno Larsen (billionai) } 42937f219c8SBruno Larsen (billionai) 430a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 43137f219c8SBruno Larsen (billionai) { 43237f219c8SBruno Larsen (billionai) } 43337f219c8SBruno Larsen (billionai) 43437f219c8SBruno Larsen (billionai) #endif 43537f219c8SBruno Larsen (billionai) 43637f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 43737f219c8SBruno Larsen (billionai) /* XER */ 438a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 43937f219c8SBruno Larsen (billionai) { 44037f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 44137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 44337f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 44437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 44537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 44637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 44737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 44837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 44937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 45037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45137f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 45237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 45337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 45537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 45637f219c8SBruno Larsen (billionai) } 45737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 45837f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 45937f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 46037f219c8SBruno Larsen (billionai) } 46137f219c8SBruno Larsen (billionai) 462a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 46337f219c8SBruno Larsen (billionai) { 46437f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 46537f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 46637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 46737f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 46837f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 46937f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 47037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 47137f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 47237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 47337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 47437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 47537f219c8SBruno Larsen (billionai) } 47637f219c8SBruno Larsen (billionai) 47737f219c8SBruno Larsen (billionai) /* LR */ 478a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 47937f219c8SBruno Larsen (billionai) { 48037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 48137f219c8SBruno Larsen (billionai) } 48237f219c8SBruno Larsen (billionai) 483a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 48437f219c8SBruno Larsen (billionai) { 48537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 48637f219c8SBruno Larsen (billionai) } 48737f219c8SBruno Larsen (billionai) 48837f219c8SBruno Larsen (billionai) /* CFAR */ 48937f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 490a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 49137f219c8SBruno Larsen (billionai) { 49237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 49337f219c8SBruno Larsen (billionai) } 49437f219c8SBruno Larsen (billionai) 495a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 49637f219c8SBruno Larsen (billionai) { 49737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 49837f219c8SBruno Larsen (billionai) } 49937f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 50037f219c8SBruno Larsen (billionai) 50137f219c8SBruno Larsen (billionai) /* CTR */ 502a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 50337f219c8SBruno Larsen (billionai) { 50437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 50537f219c8SBruno Larsen (billionai) } 50637f219c8SBruno Larsen (billionai) 507a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 50837f219c8SBruno Larsen (billionai) { 50937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 51037f219c8SBruno Larsen (billionai) } 51137f219c8SBruno Larsen (billionai) 51237f219c8SBruno Larsen (billionai) /* User read access to SPR */ 51337f219c8SBruno Larsen (billionai) /* USPRx */ 51437f219c8SBruno Larsen (billionai) /* UMMCRx */ 51537f219c8SBruno Larsen (billionai) /* UPMCx */ 51637f219c8SBruno Larsen (billionai) /* USIA */ 51737f219c8SBruno Larsen (billionai) /* UDECR */ 518a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 51937f219c8SBruno Larsen (billionai) { 52037f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 52137f219c8SBruno Larsen (billionai) } 52237f219c8SBruno Larsen (billionai) 52337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 524a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 52537f219c8SBruno Larsen (billionai) { 52637f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 52737f219c8SBruno Larsen (billionai) } 52837f219c8SBruno Larsen (billionai) #endif 52937f219c8SBruno Larsen (billionai) 53037f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 53137f219c8SBruno Larsen (billionai) /* DECR */ 53237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 533a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 53437f219c8SBruno Larsen (billionai) { 535f5b6daacSRichard Henderson gen_icount_io_start(ctx); 53637f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 53737f219c8SBruno Larsen (billionai) } 53837f219c8SBruno Larsen (billionai) 539a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 54037f219c8SBruno Larsen (billionai) { 541f5b6daacSRichard Henderson gen_icount_io_start(ctx); 54237f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 54337f219c8SBruno Larsen (billionai) } 54437f219c8SBruno Larsen (billionai) #endif 54537f219c8SBruno Larsen (billionai) 54637f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 54737f219c8SBruno Larsen (billionai) /* Time base */ 548a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 54937f219c8SBruno Larsen (billionai) { 550f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55137f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 55237f219c8SBruno Larsen (billionai) } 55337f219c8SBruno Larsen (billionai) 554a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 55537f219c8SBruno Larsen (billionai) { 556f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55737f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 55837f219c8SBruno Larsen (billionai) } 55937f219c8SBruno Larsen (billionai) 560a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 56137f219c8SBruno Larsen (billionai) { 56237f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 56337f219c8SBruno Larsen (billionai) } 56437f219c8SBruno Larsen (billionai) 565a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 56637f219c8SBruno Larsen (billionai) { 56737f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 56837f219c8SBruno Larsen (billionai) } 56937f219c8SBruno Larsen (billionai) 57037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 571a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 57237f219c8SBruno Larsen (billionai) { 573f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57437f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 57537f219c8SBruno Larsen (billionai) } 57637f219c8SBruno Larsen (billionai) 577a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 57837f219c8SBruno Larsen (billionai) { 579f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58037f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 58137f219c8SBruno Larsen (billionai) } 58237f219c8SBruno Larsen (billionai) 583a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 58437f219c8SBruno Larsen (billionai) { 58537f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 58637f219c8SBruno Larsen (billionai) } 58737f219c8SBruno Larsen (billionai) 588a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 58937f219c8SBruno Larsen (billionai) { 59037f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 59137f219c8SBruno Larsen (billionai) } 59237f219c8SBruno Larsen (billionai) 59337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 594a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 59537f219c8SBruno Larsen (billionai) { 596f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59737f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 59837f219c8SBruno Larsen (billionai) } 59937f219c8SBruno Larsen (billionai) 600a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 60137f219c8SBruno Larsen (billionai) { 602f5b6daacSRichard Henderson gen_icount_io_start(ctx); 60337f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 60437f219c8SBruno Larsen (billionai) } 60537f219c8SBruno Larsen (billionai) 60637f219c8SBruno Larsen (billionai) /* HDECR */ 607a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 60837f219c8SBruno Larsen (billionai) { 609f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61037f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 61137f219c8SBruno Larsen (billionai) } 61237f219c8SBruno Larsen (billionai) 613a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 61437f219c8SBruno Larsen (billionai) { 615f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61637f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 61737f219c8SBruno Larsen (billionai) } 61837f219c8SBruno Larsen (billionai) 619a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 62037f219c8SBruno Larsen (billionai) { 621f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62237f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 62337f219c8SBruno Larsen (billionai) } 62437f219c8SBruno Larsen (billionai) 625a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 62637f219c8SBruno Larsen (billionai) { 627f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62837f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 62937f219c8SBruno Larsen (billionai) } 63037f219c8SBruno Larsen (billionai) 631a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 63237f219c8SBruno Larsen (billionai) { 633f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63437f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 63537f219c8SBruno Larsen (billionai) } 63637f219c8SBruno Larsen (billionai) 63737f219c8SBruno Larsen (billionai) #endif 63837f219c8SBruno Larsen (billionai) #endif 63937f219c8SBruno Larsen (billionai) 64037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 64137f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 64237f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 643a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 64437f219c8SBruno Larsen (billionai) { 64537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 64637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 64737f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 64837f219c8SBruno Larsen (billionai) } 64937f219c8SBruno Larsen (billionai) 650a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 65137f219c8SBruno Larsen (billionai) { 65237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 65337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 65437f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 65537f219c8SBruno Larsen (billionai) } 65637f219c8SBruno Larsen (billionai) 657a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 65837f219c8SBruno Larsen (billionai) { 65937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 66037f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 66237f219c8SBruno Larsen (billionai) } 66337f219c8SBruno Larsen (billionai) 664a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 66537f219c8SBruno Larsen (billionai) { 66637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 66737f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 66837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 66937f219c8SBruno Larsen (billionai) } 67037f219c8SBruno Larsen (billionai) 671a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 67237f219c8SBruno Larsen (billionai) { 67337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 67437f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 67537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67637f219c8SBruno Larsen (billionai) } 67737f219c8SBruno Larsen (billionai) 678a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 67937f219c8SBruno Larsen (billionai) { 68037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 68137f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) 68537f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 68637f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 687a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 68837f219c8SBruno Larsen (billionai) { 68937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69137f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 69237f219c8SBruno Larsen (billionai) } 69337f219c8SBruno Larsen (billionai) 694a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 69537f219c8SBruno Larsen (billionai) { 69637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 69737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 69837f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 69937f219c8SBruno Larsen (billionai) } 70037f219c8SBruno Larsen (billionai) 701a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 70237f219c8SBruno Larsen (billionai) { 70337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 70437f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 70537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 70637f219c8SBruno Larsen (billionai) } 70737f219c8SBruno Larsen (billionai) 708a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 70937f219c8SBruno Larsen (billionai) { 71037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 71137f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 71337f219c8SBruno Larsen (billionai) } 71437f219c8SBruno Larsen (billionai) 715a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 71637f219c8SBruno Larsen (billionai) { 71737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 71837f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 71937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72037f219c8SBruno Larsen (billionai) } 72137f219c8SBruno Larsen (billionai) 722a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 72337f219c8SBruno Larsen (billionai) { 72437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 72537f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 72637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72737f219c8SBruno Larsen (billionai) } 72837f219c8SBruno Larsen (billionai) 72937f219c8SBruno Larsen (billionai) /* SDR1 */ 730a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 73137f219c8SBruno Larsen (billionai) { 73237f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 73337f219c8SBruno Larsen (billionai) } 73437f219c8SBruno Larsen (billionai) 73537f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 73637f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 73737f219c8SBruno Larsen (billionai) /* PIDR */ 738a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 73937f219c8SBruno Larsen (billionai) { 74037f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 74137f219c8SBruno Larsen (billionai) } 74237f219c8SBruno Larsen (billionai) 743a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 74437f219c8SBruno Larsen (billionai) { 74537f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 74637f219c8SBruno Larsen (billionai) } 74737f219c8SBruno Larsen (billionai) 748a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 74937f219c8SBruno Larsen (billionai) { 75037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 75137f219c8SBruno Larsen (billionai) } 75237f219c8SBruno Larsen (billionai) 753a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 75437f219c8SBruno Larsen (billionai) { 75537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 75637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 75737f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 75837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 75937f219c8SBruno Larsen (billionai) } 760a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 76137f219c8SBruno Larsen (billionai) { 76237f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 76337f219c8SBruno Larsen (billionai) } 76437f219c8SBruno Larsen (billionai) 765a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 76637f219c8SBruno Larsen (billionai) { 76737f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 76837f219c8SBruno Larsen (billionai) } 76937f219c8SBruno Larsen (billionai) 77037f219c8SBruno Larsen (billionai) /* DPDES */ 771a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 77237f219c8SBruno Larsen (billionai) { 77337f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 77437f219c8SBruno Larsen (billionai) } 77537f219c8SBruno Larsen (billionai) 776a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 77737f219c8SBruno Larsen (billionai) { 77837f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 77937f219c8SBruno Larsen (billionai) } 78037f219c8SBruno Larsen (billionai) #endif 78137f219c8SBruno Larsen (billionai) #endif 78237f219c8SBruno Larsen (billionai) 78337f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 78437f219c8SBruno Larsen (billionai) /* RTC */ 785a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 78637f219c8SBruno Larsen (billionai) { 78737f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 78837f219c8SBruno Larsen (billionai) } 78937f219c8SBruno Larsen (billionai) 790a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 79137f219c8SBruno Larsen (billionai) { 79237f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 79337f219c8SBruno Larsen (billionai) } 79437f219c8SBruno Larsen (billionai) 79537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 796a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 79737f219c8SBruno Larsen (billionai) { 79837f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 79937f219c8SBruno Larsen (billionai) } 80037f219c8SBruno Larsen (billionai) 801a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 80237f219c8SBruno Larsen (billionai) { 80337f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 80437f219c8SBruno Larsen (billionai) } 80537f219c8SBruno Larsen (billionai) 806a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 80737f219c8SBruno Larsen (billionai) { 80837f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 80937f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 810d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 81137f219c8SBruno Larsen (billionai) } 81237f219c8SBruno Larsen (billionai) #endif 81337f219c8SBruno Larsen (billionai) 81437f219c8SBruno Larsen (billionai) /* Unified bats */ 81537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 816a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 81737f219c8SBruno Larsen (billionai) { 81837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 81937f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 82037f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 82137f219c8SBruno Larsen (billionai) } 82237f219c8SBruno Larsen (billionai) 823a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 82437f219c8SBruno Larsen (billionai) { 82537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 82637f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 82737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 82837f219c8SBruno Larsen (billionai) } 82937f219c8SBruno Larsen (billionai) 830a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 83137f219c8SBruno Larsen (billionai) { 83237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 83337f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 83437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 83537f219c8SBruno Larsen (billionai) } 83637f219c8SBruno Larsen (billionai) #endif 83737f219c8SBruno Larsen (billionai) 83837f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 83937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 840a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 84137f219c8SBruno Larsen (billionai) { 842f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84337f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 84437f219c8SBruno Larsen (billionai) } 84537f219c8SBruno Larsen (billionai) 846a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 84737f219c8SBruno Larsen (billionai) { 848f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84937f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 85037f219c8SBruno Larsen (billionai) } 85137f219c8SBruno Larsen (billionai) 852a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 85337f219c8SBruno Larsen (billionai) { 854f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 85637f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 85737f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 858d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 85937f219c8SBruno Larsen (billionai) } 86037f219c8SBruno Larsen (billionai) 861a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 86237f219c8SBruno Larsen (billionai) { 863f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86437f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 86537f219c8SBruno Larsen (billionai) } 86637f219c8SBruno Larsen (billionai) 867a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 86837f219c8SBruno Larsen (billionai) { 869f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87037f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 87137f219c8SBruno Larsen (billionai) } 87237f219c8SBruno Larsen (billionai) 873a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 87437f219c8SBruno Larsen (billionai) { 875f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87637f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 87737f219c8SBruno Larsen (billionai) } 87837f219c8SBruno Larsen (billionai) #endif 87937f219c8SBruno Larsen (billionai) 88037f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 88137f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 88237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 883a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 88437f219c8SBruno Larsen (billionai) { 88537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 88637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 88737f219c8SBruno Larsen (billionai) } 88837f219c8SBruno Larsen (billionai) 889a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 89037f219c8SBruno Larsen (billionai) { 89137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 89237f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 89337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 89437f219c8SBruno Larsen (billionai) } 89537f219c8SBruno Larsen (billionai) 896a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 89737f219c8SBruno Larsen (billionai) { 89837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 89937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 90037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 90137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 90237f219c8SBruno Larsen (billionai) } 90337f219c8SBruno Larsen (billionai) #endif 90437f219c8SBruno Larsen (billionai) 90537f219c8SBruno Larsen (billionai) /* SPE specific registers */ 906a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 90737f219c8SBruno Larsen (billionai) { 90837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 90937f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91037f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 91137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91237f219c8SBruno Larsen (billionai) } 91337f219c8SBruno Larsen (billionai) 914a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 91537f219c8SBruno Larsen (billionai) { 91637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91737f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 91837f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92037f219c8SBruno Larsen (billionai) } 92137f219c8SBruno Larsen (billionai) 92237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 92337f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 924a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 92537f219c8SBruno Larsen (billionai) { 92637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 92837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 92937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 93037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 93237f219c8SBruno Larsen (billionai) } 93337f219c8SBruno Larsen (billionai) 934a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 93537f219c8SBruno Larsen (billionai) { 93637f219c8SBruno Larsen (billionai) int sprn_offs; 93737f219c8SBruno Larsen (billionai) 93837f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 93937f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 94037f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 94137f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 94237f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 94337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 94437f219c8SBruno Larsen (billionai) } else { 94537f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 94637f219c8SBruno Larsen (billionai) sprn, sprn); 94737f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 94837f219c8SBruno Larsen (billionai) return; 94937f219c8SBruno Larsen (billionai) } 95037f219c8SBruno Larsen (billionai) 95137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 95237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 95337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 95437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 95537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 95637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 95737f219c8SBruno Larsen (billionai) } 95837f219c8SBruno Larsen (billionai) #endif 95937f219c8SBruno Larsen (billionai) 96037f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 96137f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 962a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 96337f219c8SBruno Larsen (billionai) { 96437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 96637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 96737f219c8SBruno Larsen (billionai) 96837f219c8SBruno Larsen (billionai) /* 96937f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 97037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 97137f219c8SBruno Larsen (billionai) */ 97237f219c8SBruno Larsen (billionai) 97337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 97437f219c8SBruno Larsen (billionai) if (ctx->pr) { 97537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 97637f219c8SBruno Larsen (billionai) } else { 97737f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 97837f219c8SBruno Larsen (billionai) } 97937f219c8SBruno Larsen (billionai) 98037f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98137f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98237f219c8SBruno Larsen (billionai) 98337f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 98437f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 98537f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 98637f219c8SBruno Larsen (billionai) 98737f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 98837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 98937f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 99037f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 99137f219c8SBruno Larsen (billionai) 99237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 99337f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 99437f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 99537f219c8SBruno Larsen (billionai) } 99637f219c8SBruno Larsen (billionai) 997a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 99837f219c8SBruno Larsen (billionai) { 99937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 100037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 100137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 100237f219c8SBruno Larsen (billionai) 100337f219c8SBruno Larsen (billionai) /* 100437f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 100537f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100637f219c8SBruno Larsen (billionai) */ 100737f219c8SBruno Larsen (billionai) 100837f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 100937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 101037f219c8SBruno Larsen (billionai) 101137f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 101237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 101337f219c8SBruno Larsen (billionai) 101437f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 101537f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 101637f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101737f219c8SBruno Larsen (billionai) 101837f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 101937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 102037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 102137f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 102237f219c8SBruno Larsen (billionai) 102337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 102437f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 102537f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 102637f219c8SBruno Larsen (billionai) } 102737f219c8SBruno Larsen (billionai) 1028a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 102937f219c8SBruno Larsen (billionai) { 103037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 103237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 103337f219c8SBruno Larsen (billionai) 103437f219c8SBruno Larsen (billionai) /* 103537f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 103637f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 103737f219c8SBruno Larsen (billionai) */ 103837f219c8SBruno Larsen (billionai) 103937f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 104037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 104137f219c8SBruno Larsen (billionai) 104237f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 104337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 104437f219c8SBruno Larsen (billionai) 104537f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 104637f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 104737f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 104837f219c8SBruno Larsen (billionai) 104937f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 105037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 105137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 105237f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 105337f219c8SBruno Larsen (billionai) 105437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105537f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 105637f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 105737f219c8SBruno Larsen (billionai) } 105837f219c8SBruno Larsen (billionai) #endif 105937f219c8SBruno Larsen (billionai) #endif 106037f219c8SBruno Larsen (billionai) 106137f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1062a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 106337f219c8SBruno Larsen (billionai) { 106437f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 106537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 106637f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 106737f219c8SBruno Larsen (billionai) } 106837f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 106937f219c8SBruno Larsen (billionai) 107037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1071a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 107237f219c8SBruno Larsen (billionai) { 107337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107437f219c8SBruno Larsen (billionai) 107537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 107637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 107837f219c8SBruno Larsen (billionai) } 107937f219c8SBruno Larsen (billionai) 1080a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 108137f219c8SBruno Larsen (billionai) { 108237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108337f219c8SBruno Larsen (billionai) 108437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 108537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 108737f219c8SBruno Larsen (billionai) } 108837f219c8SBruno Larsen (billionai) 1089a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 109037f219c8SBruno Larsen (billionai) { 109137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109237f219c8SBruno Larsen (billionai) 109337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 109437f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 109537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 109637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 109737f219c8SBruno Larsen (billionai) } 109837f219c8SBruno Larsen (billionai) 1099a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 110037f219c8SBruno Larsen (billionai) { 110137f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 110237f219c8SBruno Larsen (billionai) } 110337f219c8SBruno Larsen (billionai) 1104a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 110537f219c8SBruno Larsen (billionai) { 110637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 110737f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 110837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 110937f219c8SBruno Larsen (billionai) } 1110a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 111137f219c8SBruno Larsen (billionai) { 111237f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 111337f219c8SBruno Larsen (billionai) } 1114a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 111537f219c8SBruno Larsen (billionai) { 111637f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 111737f219c8SBruno Larsen (billionai) } 111837f219c8SBruno Larsen (billionai) 111937f219c8SBruno Larsen (billionai) #endif 112037f219c8SBruno Larsen (billionai) 112137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1122a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 112337f219c8SBruno Larsen (billionai) { 112437f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 112537f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 112637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 112737f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 112837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 112937f219c8SBruno Larsen (billionai) tcg_temp_free(val); 113037f219c8SBruno Larsen (billionai) } 113137f219c8SBruno Larsen (billionai) 1132a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 113337f219c8SBruno Larsen (billionai) { 113437f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 113537f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 113637f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 113737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 113837f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 113937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 114037f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 114137f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 114237f219c8SBruno Larsen (billionai) } 114337f219c8SBruno Larsen (billionai) 114437f219c8SBruno Larsen (billionai) #endif 114537f219c8SBruno Larsen (billionai) 114637f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 114737f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 114837f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 114937f219c8SBruno Larsen (billionai) { 115037f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 115137f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 115237f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 115337f219c8SBruno Larsen (billionai) 115437f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 115537f219c8SBruno Larsen (billionai) 115637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 115737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 115837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 115937f219c8SBruno Larsen (billionai) } 116037f219c8SBruno Larsen (billionai) 116137f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 116237f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 116337f219c8SBruno Larsen (billionai) { 116437f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 116537f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 116637f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 116737f219c8SBruno Larsen (billionai) 116837f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 116937f219c8SBruno Larsen (billionai) 117037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 117137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 117237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 117337f219c8SBruno Larsen (billionai) } 117437f219c8SBruno Larsen (billionai) 1175a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 117637f219c8SBruno Larsen (billionai) { 117737f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 117837f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 117937f219c8SBruno Larsen (billionai) 118037f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 118137f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 118237f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 118337f219c8SBruno Larsen (billionai) 118437f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 118537f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 118637f219c8SBruno Larsen (billionai) } 118737f219c8SBruno Larsen (billionai) 1188a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 118937f219c8SBruno Larsen (billionai) { 119037f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 119137f219c8SBruno Larsen (billionai) 119237f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 119337f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 119437f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 119537f219c8SBruno Larsen (billionai) 119637f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 119737f219c8SBruno Larsen (billionai) } 119837f219c8SBruno Larsen (billionai) 119937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1200a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 120137f219c8SBruno Larsen (billionai) { 120237f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 120337f219c8SBruno Larsen (billionai) 120437f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 120537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 120637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 120737f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 120837f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 120937f219c8SBruno Larsen (billionai) } 121037f219c8SBruno Larsen (billionai) 1211a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 121237f219c8SBruno Larsen (billionai) { 121337f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 121437f219c8SBruno Larsen (billionai) } 121537f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 121637f219c8SBruno Larsen (billionai) 1217a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 121837f219c8SBruno Larsen (billionai) { 121937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122037f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 122137f219c8SBruno Larsen (billionai) } 122237f219c8SBruno Larsen (billionai) 1223a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 122437f219c8SBruno Larsen (billionai) { 122537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122637f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 122737f219c8SBruno Larsen (billionai) } 122837f219c8SBruno Larsen (billionai) 1229a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 123037f219c8SBruno Larsen (billionai) { 123137f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123237f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123337f219c8SBruno Larsen (billionai) } 123437f219c8SBruno Larsen (billionai) 1235a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 123637f219c8SBruno Larsen (billionai) { 123737f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 123937f219c8SBruno Larsen (billionai) } 124037f219c8SBruno Larsen (billionai) 1241a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 124237f219c8SBruno Larsen (billionai) { 124337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124437f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124537f219c8SBruno Larsen (billionai) } 124637f219c8SBruno Larsen (billionai) 1247a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 124837f219c8SBruno Larsen (billionai) { 124937f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125037f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125137f219c8SBruno Larsen (billionai) } 125237f219c8SBruno Larsen (billionai) 1253a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 125437f219c8SBruno Larsen (billionai) { 125537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 125637f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 125737f219c8SBruno Larsen (billionai) } 125837f219c8SBruno Larsen (billionai) 1259a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 126037f219c8SBruno Larsen (billionai) { 126137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 126337f219c8SBruno Larsen (billionai) } 126437f219c8SBruno Larsen (billionai) 1265a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 126637f219c8SBruno Larsen (billionai) { 126737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126837f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 126937f219c8SBruno Larsen (billionai) } 127037f219c8SBruno Larsen (billionai) 1271a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 127237f219c8SBruno Larsen (billionai) { 127337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127437f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 127537f219c8SBruno Larsen (billionai) } 127637f219c8SBruno Larsen (billionai) #endif 127737f219c8SBruno Larsen (billionai) 1278fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1279fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1280fcf5ef2aSThomas Huth 1281fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1282fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1283fcf5ef2aSThomas Huth 1284fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1285fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1286fcf5ef2aSThomas Huth 1287fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1288fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1289fcf5ef2aSThomas Huth 1290fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1291fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1292fcf5ef2aSThomas Huth 1293fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1294fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1295fcf5ef2aSThomas Huth 1296fcf5ef2aSThomas Huth typedef struct opcode_t { 1297fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1298fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1299fcf5ef2aSThomas Huth unsigned char pad[4]; 1300fcf5ef2aSThomas Huth #endif 1301fcf5ef2aSThomas Huth opc_handler_t handler; 1302fcf5ef2aSThomas Huth const char *oname; 1303fcf5ef2aSThomas Huth } opcode_t; 1304fcf5ef2aSThomas Huth 1305fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1306fcf5ef2aSThomas Huth #define GEN_PRIV \ 1307fcf5ef2aSThomas Huth do { \ 1308fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1309fcf5ef2aSThomas Huth } while (0) 1310fcf5ef2aSThomas Huth 1311fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1312fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1313fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1314fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1315fcf5ef2aSThomas Huth #else 1316fcf5ef2aSThomas Huth #define CHK_HV \ 1317fcf5ef2aSThomas Huth do { \ 1318fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1319fcf5ef2aSThomas Huth GEN_PRIV; \ 1320fcf5ef2aSThomas Huth } \ 1321fcf5ef2aSThomas Huth } while (0) 1322fcf5ef2aSThomas Huth #define CHK_SV \ 1323fcf5ef2aSThomas Huth do { \ 1324fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1325fcf5ef2aSThomas Huth GEN_PRIV; \ 1326fcf5ef2aSThomas Huth } \ 1327fcf5ef2aSThomas Huth } while (0) 1328fcf5ef2aSThomas Huth #define CHK_HVRM \ 1329fcf5ef2aSThomas Huth do { \ 1330fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1331fcf5ef2aSThomas Huth GEN_PRIV; \ 1332fcf5ef2aSThomas Huth } \ 1333fcf5ef2aSThomas Huth } while (0) 1334fcf5ef2aSThomas Huth #endif 1335fcf5ef2aSThomas Huth 1336fcf5ef2aSThomas Huth #define CHK_NONE 1337fcf5ef2aSThomas Huth 1338fcf5ef2aSThomas Huth /*****************************************************************************/ 1339fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1340fcf5ef2aSThomas Huth 1341fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1342fcf5ef2aSThomas Huth { \ 1343fcf5ef2aSThomas Huth .opc1 = op1, \ 1344fcf5ef2aSThomas Huth .opc2 = op2, \ 1345fcf5ef2aSThomas Huth .opc3 = op3, \ 1346fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1347fcf5ef2aSThomas Huth .handler = { \ 1348fcf5ef2aSThomas Huth .inval1 = invl, \ 1349fcf5ef2aSThomas Huth .type = _typ, \ 1350fcf5ef2aSThomas Huth .type2 = _typ2, \ 1351fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1352fcf5ef2aSThomas Huth }, \ 1353fcf5ef2aSThomas Huth .oname = stringify(name), \ 1354fcf5ef2aSThomas Huth } 1355fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1356fcf5ef2aSThomas Huth { \ 1357fcf5ef2aSThomas Huth .opc1 = op1, \ 1358fcf5ef2aSThomas Huth .opc2 = op2, \ 1359fcf5ef2aSThomas Huth .opc3 = op3, \ 1360fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1361fcf5ef2aSThomas Huth .handler = { \ 1362fcf5ef2aSThomas Huth .inval1 = invl1, \ 1363fcf5ef2aSThomas Huth .inval2 = invl2, \ 1364fcf5ef2aSThomas Huth .type = _typ, \ 1365fcf5ef2aSThomas Huth .type2 = _typ2, \ 1366fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1367fcf5ef2aSThomas Huth }, \ 1368fcf5ef2aSThomas Huth .oname = stringify(name), \ 1369fcf5ef2aSThomas Huth } 1370fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1371fcf5ef2aSThomas Huth { \ 1372fcf5ef2aSThomas Huth .opc1 = op1, \ 1373fcf5ef2aSThomas Huth .opc2 = op2, \ 1374fcf5ef2aSThomas Huth .opc3 = op3, \ 1375fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1376fcf5ef2aSThomas Huth .handler = { \ 1377fcf5ef2aSThomas Huth .inval1 = invl, \ 1378fcf5ef2aSThomas Huth .type = _typ, \ 1379fcf5ef2aSThomas Huth .type2 = _typ2, \ 1380fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1381fcf5ef2aSThomas Huth }, \ 1382fcf5ef2aSThomas Huth .oname = onam, \ 1383fcf5ef2aSThomas Huth } 1384fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1385fcf5ef2aSThomas Huth { \ 1386fcf5ef2aSThomas Huth .opc1 = op1, \ 1387fcf5ef2aSThomas Huth .opc2 = op2, \ 1388fcf5ef2aSThomas Huth .opc3 = op3, \ 1389fcf5ef2aSThomas Huth .opc4 = op4, \ 1390fcf5ef2aSThomas Huth .handler = { \ 1391fcf5ef2aSThomas Huth .inval1 = invl, \ 1392fcf5ef2aSThomas Huth .type = _typ, \ 1393fcf5ef2aSThomas Huth .type2 = _typ2, \ 1394fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1395fcf5ef2aSThomas Huth }, \ 1396fcf5ef2aSThomas Huth .oname = stringify(name), \ 1397fcf5ef2aSThomas Huth } 1398fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1399fcf5ef2aSThomas Huth { \ 1400fcf5ef2aSThomas Huth .opc1 = op1, \ 1401fcf5ef2aSThomas Huth .opc2 = op2, \ 1402fcf5ef2aSThomas Huth .opc3 = op3, \ 1403fcf5ef2aSThomas Huth .opc4 = op4, \ 1404fcf5ef2aSThomas Huth .handler = { \ 1405fcf5ef2aSThomas Huth .inval1 = invl, \ 1406fcf5ef2aSThomas Huth .type = _typ, \ 1407fcf5ef2aSThomas Huth .type2 = _typ2, \ 1408fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1409fcf5ef2aSThomas Huth }, \ 1410fcf5ef2aSThomas Huth .oname = onam, \ 1411fcf5ef2aSThomas Huth } 1412fcf5ef2aSThomas Huth 1413fcf5ef2aSThomas Huth /* Invalid instruction */ 1414fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1415fcf5ef2aSThomas Huth { 1416fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1417fcf5ef2aSThomas Huth } 1418fcf5ef2aSThomas Huth 1419fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1420fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1421fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1422fcf5ef2aSThomas Huth .type = PPC_NONE, 1423fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1424fcf5ef2aSThomas Huth .handler = gen_invalid, 1425fcf5ef2aSThomas Huth }; 1426fcf5ef2aSThomas Huth 1427fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1428fcf5ef2aSThomas Huth 1429fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1430fcf5ef2aSThomas Huth { 1431fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1432b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1433b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1434fcf5ef2aSThomas Huth 1435b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1436b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1437efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1438efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1439b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1440efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1441efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1442b62b3686Spbonzini@redhat.com 1443b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1444fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1445b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1446fcf5ef2aSThomas Huth 1447fcf5ef2aSThomas Huth tcg_temp_free(t0); 1448b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1449b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1450fcf5ef2aSThomas Huth } 1451fcf5ef2aSThomas Huth 1452fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1453fcf5ef2aSThomas Huth { 1454fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1455fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1456fcf5ef2aSThomas Huth tcg_temp_free(t0); 1457fcf5ef2aSThomas Huth } 1458fcf5ef2aSThomas Huth 1459fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1460fcf5ef2aSThomas Huth { 1461fcf5ef2aSThomas Huth TCGv t0, t1; 1462fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1463fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1464fcf5ef2aSThomas Huth if (s) { 1465fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1466fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1467fcf5ef2aSThomas Huth } else { 1468fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1469fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1470fcf5ef2aSThomas Huth } 1471fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1472fcf5ef2aSThomas Huth tcg_temp_free(t1); 1473fcf5ef2aSThomas Huth tcg_temp_free(t0); 1474fcf5ef2aSThomas Huth } 1475fcf5ef2aSThomas Huth 1476fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1477fcf5ef2aSThomas Huth { 1478fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1479fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1480fcf5ef2aSThomas Huth tcg_temp_free(t0); 1481fcf5ef2aSThomas Huth } 1482fcf5ef2aSThomas Huth 1483fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1484fcf5ef2aSThomas Huth { 1485fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1486fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1487fcf5ef2aSThomas Huth } else { 1488fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1489fcf5ef2aSThomas Huth } 1490fcf5ef2aSThomas Huth } 1491fcf5ef2aSThomas Huth 1492fcf5ef2aSThomas Huth /* cmp */ 1493fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 1494fcf5ef2aSThomas Huth { 1495fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1496fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1497fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1498fcf5ef2aSThomas Huth } else { 1499fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1500fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1501fcf5ef2aSThomas Huth } 1502fcf5ef2aSThomas Huth } 1503fcf5ef2aSThomas Huth 1504fcf5ef2aSThomas Huth /* cmpi */ 1505fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 1506fcf5ef2aSThomas Huth { 1507fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1508fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1509fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1510fcf5ef2aSThomas Huth } else { 1511fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1512fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1513fcf5ef2aSThomas Huth } 1514fcf5ef2aSThomas Huth } 1515fcf5ef2aSThomas Huth 1516fcf5ef2aSThomas Huth /* cmpl */ 1517fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 1518fcf5ef2aSThomas Huth { 1519fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1520fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1521fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1522fcf5ef2aSThomas Huth } else { 1523fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1524fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1525fcf5ef2aSThomas Huth } 1526fcf5ef2aSThomas Huth } 1527fcf5ef2aSThomas Huth 1528fcf5ef2aSThomas Huth /* cmpli */ 1529fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 1530fcf5ef2aSThomas Huth { 1531fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1532fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1533fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1534fcf5ef2aSThomas Huth } else { 1535fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1536fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1537fcf5ef2aSThomas Huth } 1538fcf5ef2aSThomas Huth } 1539fcf5ef2aSThomas Huth 1540fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1541fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1542fcf5ef2aSThomas Huth { 1543fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1544fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1545fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1546fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1547fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1548fcf5ef2aSThomas Huth 1549fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1550fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1551fcf5ef2aSThomas Huth 1552fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1553fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1554fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1555fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1556fcf5ef2aSThomas Huth 1557fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1558fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1559fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1560fcf5ef2aSThomas Huth 1561fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1562fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1563fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1564fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1565fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1566fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1567fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1568fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1569fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1570fcf5ef2aSThomas Huth } 1571efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1572fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1573fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1574fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1575fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1576fcf5ef2aSThomas Huth } 1577fcf5ef2aSThomas Huth 1578fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1579fcf5ef2aSThomas Huth /* cmpeqb */ 1580fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1581fcf5ef2aSThomas Huth { 1582fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1583fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1584fcf5ef2aSThomas Huth } 1585fcf5ef2aSThomas Huth #endif 1586fcf5ef2aSThomas Huth 1587fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1588fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1589fcf5ef2aSThomas Huth { 1590fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1591fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1592fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1593fcf5ef2aSThomas Huth TCGv zr; 1594fcf5ef2aSThomas Huth 1595fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1596fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1597fcf5ef2aSThomas Huth 1598fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1599fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1600fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1601fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1602fcf5ef2aSThomas Huth tcg_temp_free(zr); 1603fcf5ef2aSThomas Huth tcg_temp_free(t0); 1604fcf5ef2aSThomas Huth } 1605fcf5ef2aSThomas Huth 1606fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1607fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1608fcf5ef2aSThomas Huth { 1609fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1610fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1611fcf5ef2aSThomas Huth } 1612fcf5ef2aSThomas Huth 1613fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1614fcf5ef2aSThomas Huth 1615fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1616fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1617fcf5ef2aSThomas Huth { 1618fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1619fcf5ef2aSThomas Huth 1620fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1621fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1622fcf5ef2aSThomas Huth if (sub) { 1623fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1624fcf5ef2aSThomas Huth } else { 1625fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1626fcf5ef2aSThomas Huth } 1627fcf5ef2aSThomas Huth tcg_temp_free(t0); 1628fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1629dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1630dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1631dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1632fcf5ef2aSThomas Huth } 1633dc0ad844SNikunj A Dadhania } else { 1634dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1635dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1636dc0ad844SNikunj A Dadhania } 163738a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1638dc0ad844SNikunj A Dadhania } 1639fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1640fcf5ef2aSThomas Huth } 1641fcf5ef2aSThomas Huth 16426b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 16436b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 16444c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 16456b10d008SNikunj A Dadhania { 16466b10d008SNikunj A Dadhania TCGv t0; 16476b10d008SNikunj A Dadhania 16486b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16496b10d008SNikunj A Dadhania return; 16506b10d008SNikunj A Dadhania } 16516b10d008SNikunj A Dadhania 16526b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 165333903d0aSNikunj A Dadhania if (sub) { 165433903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 165533903d0aSNikunj A Dadhania } else { 16566b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 165733903d0aSNikunj A Dadhania } 16586b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16594c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16606b10d008SNikunj A Dadhania tcg_temp_free(t0); 16616b10d008SNikunj A Dadhania } 16626b10d008SNikunj A Dadhania 1663fcf5ef2aSThomas Huth /* Common add function */ 1664fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16654c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16664c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1667fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1668fcf5ef2aSThomas Huth { 1669fcf5ef2aSThomas Huth TCGv t0 = ret; 1670fcf5ef2aSThomas Huth 1671fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1672fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1673fcf5ef2aSThomas Huth } 1674fcf5ef2aSThomas Huth 1675fcf5ef2aSThomas Huth if (compute_ca) { 1676fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1677efe843d8SDavid Gibson /* 1678efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1679efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1680efe843d8SDavid Gibson * produce the carry into bit 32. 1681efe843d8SDavid Gibson */ 1682fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1683fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1684fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1685fcf5ef2aSThomas Huth if (add_ca) { 16864c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1687fcf5ef2aSThomas Huth } 16884c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1689fcf5ef2aSThomas Huth tcg_temp_free(t1); 16904c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16916b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16924c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16936b10d008SNikunj A Dadhania } 1694fcf5ef2aSThomas Huth } else { 1695fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1696fcf5ef2aSThomas Huth if (add_ca) { 16974c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16984c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1699fcf5ef2aSThomas Huth } else { 17004c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1701fcf5ef2aSThomas Huth } 17024c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1703fcf5ef2aSThomas Huth tcg_temp_free(zero); 1704fcf5ef2aSThomas Huth } 1705fcf5ef2aSThomas Huth } else { 1706fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1707fcf5ef2aSThomas Huth if (add_ca) { 17084c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1709fcf5ef2aSThomas Huth } 1710fcf5ef2aSThomas Huth } 1711fcf5ef2aSThomas Huth 1712fcf5ef2aSThomas Huth if (compute_ov) { 1713fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1714fcf5ef2aSThomas Huth } 1715fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1716fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1717fcf5ef2aSThomas Huth } 1718fcf5ef2aSThomas Huth 171911f4e8f8SRichard Henderson if (t0 != ret) { 1720fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1721fcf5ef2aSThomas Huth tcg_temp_free(t0); 1722fcf5ef2aSThomas Huth } 1723fcf5ef2aSThomas Huth } 1724fcf5ef2aSThomas Huth /* Add functions with two operands */ 17254c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1726fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1727fcf5ef2aSThomas Huth { \ 1728fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1729fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 17304c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1731fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1732fcf5ef2aSThomas Huth } 1733fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 17344c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1735fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1736fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1737fcf5ef2aSThomas Huth { \ 1738fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1739fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1740fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 17414c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1742fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1743fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1744fcf5ef2aSThomas Huth } 1745fcf5ef2aSThomas Huth 1746fcf5ef2aSThomas Huth /* add add. addo addo. */ 17474c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 17484c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1749fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 17504c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 17514c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1752fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17534c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17544c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1755fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17564c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17574c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17584c5920afSSuraj Jitindar Singh /* addex */ 17594c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1760fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17614c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17624c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1763fcf5ef2aSThomas Huth /* addic addic.*/ 1764fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1765fcf5ef2aSThomas Huth { 1766fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1767fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17684c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1769fcf5ef2aSThomas Huth tcg_temp_free(c); 1770fcf5ef2aSThomas Huth } 1771fcf5ef2aSThomas Huth 1772fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1773fcf5ef2aSThomas Huth { 1774fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1775fcf5ef2aSThomas Huth } 1776fcf5ef2aSThomas Huth 1777fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1778fcf5ef2aSThomas Huth { 1779fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1780fcf5ef2aSThomas Huth } 1781fcf5ef2aSThomas Huth 1782fcf5ef2aSThomas Huth /* addpcis */ 1783fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 1784fcf5ef2aSThomas Huth { 1785fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 1786fcf5ef2aSThomas Huth 1787b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 1788fcf5ef2aSThomas Huth } 1789fcf5ef2aSThomas Huth 1790fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1791fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1792fcf5ef2aSThomas Huth { 1793fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1794fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1795fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1796fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1797fcf5ef2aSThomas Huth 1798fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1799fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1800fcf5ef2aSThomas Huth if (sign) { 1801fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1802fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1803fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1804fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1805fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1806fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1807fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1808fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1809fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1810fcf5ef2aSThomas Huth } else { 1811fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1812fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1813fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1814fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1815fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1816fcf5ef2aSThomas Huth } 1817fcf5ef2aSThomas Huth if (compute_ov) { 1818fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1819c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1820c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1821c44027ffSNikunj A Dadhania } 1822fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1823fcf5ef2aSThomas Huth } 1824fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1825fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1826fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1827fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1828fcf5ef2aSThomas Huth 1829efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1830fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1831fcf5ef2aSThomas Huth } 1832efe843d8SDavid Gibson } 1833fcf5ef2aSThomas Huth /* Div functions */ 1834fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1835fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1836fcf5ef2aSThomas Huth { \ 1837fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1838fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1839fcf5ef2aSThomas Huth sign, compute_ov); \ 1840fcf5ef2aSThomas Huth } 1841fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1842fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1843fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1844fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1845fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1846fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1847fcf5ef2aSThomas Huth 1848fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1849fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1850fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1851fcf5ef2aSThomas Huth { \ 1852fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1853fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1854fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1855fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1856fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1857fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1858fcf5ef2aSThomas Huth } \ 1859fcf5ef2aSThomas Huth } 1860fcf5ef2aSThomas Huth 1861fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1862fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1863fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1864fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1865fcf5ef2aSThomas Huth 1866fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1867fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1868fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1869fcf5ef2aSThomas Huth { 1870fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1871fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1872fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1873fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1874fcf5ef2aSThomas Huth 1875fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1876fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1877fcf5ef2aSThomas Huth if (sign) { 1878fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1879fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1880fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1881fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1882fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1883fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1884fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1885fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1886fcf5ef2aSThomas Huth } else { 1887fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1888fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1889fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1890fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1891fcf5ef2aSThomas Huth } 1892fcf5ef2aSThomas Huth if (compute_ov) { 1893fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1894c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1895c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1896c44027ffSNikunj A Dadhania } 1897fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1898fcf5ef2aSThomas Huth } 1899fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1900fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1901fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1902fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1903fcf5ef2aSThomas Huth 1904efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1905fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1906fcf5ef2aSThomas Huth } 1907efe843d8SDavid Gibson } 1908fcf5ef2aSThomas Huth 1909fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1910fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1911fcf5ef2aSThomas Huth { \ 1912fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1913fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1914fcf5ef2aSThomas Huth sign, compute_ov); \ 1915fcf5ef2aSThomas Huth } 1916c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1917fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1918fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1919c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1920fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1921fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1922fcf5ef2aSThomas Huth 1923fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1924fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1925fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1926fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1927fcf5ef2aSThomas Huth #endif 1928fcf5ef2aSThomas Huth 1929fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1930fcf5ef2aSThomas Huth TCGv arg2, int sign) 1931fcf5ef2aSThomas Huth { 1932fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1933fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1934fcf5ef2aSThomas Huth 1935fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1936fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1937fcf5ef2aSThomas Huth if (sign) { 1938fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1939fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1940fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1941fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1942fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1943fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1944fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1945fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1946fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1947fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1948fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1949fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1950fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1951fcf5ef2aSThomas Huth } else { 1952fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1953fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1954fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1955fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1956fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1957fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1958fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1959fcf5ef2aSThomas Huth } 1960fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1961fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1962fcf5ef2aSThomas Huth } 1963fcf5ef2aSThomas Huth 1964fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1965fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1966fcf5ef2aSThomas Huth { \ 1967fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1968fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1969fcf5ef2aSThomas Huth sign); \ 1970fcf5ef2aSThomas Huth } 1971fcf5ef2aSThomas Huth 1972fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1973fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1974fcf5ef2aSThomas Huth 1975fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1976fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1977fcf5ef2aSThomas Huth TCGv arg2, int sign) 1978fcf5ef2aSThomas Huth { 1979fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1980fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1981fcf5ef2aSThomas Huth 1982fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1983fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1984fcf5ef2aSThomas Huth if (sign) { 1985fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1986fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1987fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1988fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1989fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1990fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1991fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1992fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1993fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1994fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1995fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1996fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1997fcf5ef2aSThomas Huth } else { 1998fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1999fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 2000fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 2001fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 2002fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2003fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2004fcf5ef2aSThomas Huth } 2005fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2006fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2007fcf5ef2aSThomas Huth } 2008fcf5ef2aSThomas Huth 2009fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 2010fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2011fcf5ef2aSThomas Huth { \ 2012fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2013fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2014fcf5ef2aSThomas Huth sign); \ 2015fcf5ef2aSThomas Huth } 2016fcf5ef2aSThomas Huth 2017fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 2018fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 2019fcf5ef2aSThomas Huth #endif 2020fcf5ef2aSThomas Huth 2021fcf5ef2aSThomas Huth /* mulhw mulhw. */ 2022fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 2023fcf5ef2aSThomas Huth { 2024fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2025fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2026fcf5ef2aSThomas Huth 2027fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2028fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2029fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2030fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2031fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2032fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2033efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2034fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2035fcf5ef2aSThomas Huth } 2036efe843d8SDavid Gibson } 2037fcf5ef2aSThomas Huth 2038fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 2039fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 2040fcf5ef2aSThomas Huth { 2041fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2042fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2043fcf5ef2aSThomas Huth 2044fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2045fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2046fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 2047fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2048fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2049fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2050efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2051fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2052fcf5ef2aSThomas Huth } 2053efe843d8SDavid Gibson } 2054fcf5ef2aSThomas Huth 2055fcf5ef2aSThomas Huth /* mullw mullw. */ 2056fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2057fcf5ef2aSThomas Huth { 2058fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2059fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2060fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2061fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2062fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2063fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2064fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2065fcf5ef2aSThomas Huth tcg_temp_free(t0); 2066fcf5ef2aSThomas Huth tcg_temp_free(t1); 2067fcf5ef2aSThomas Huth #else 2068fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2069fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2070fcf5ef2aSThomas Huth #endif 2071efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2072fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2073fcf5ef2aSThomas Huth } 2074efe843d8SDavid Gibson } 2075fcf5ef2aSThomas Huth 2076fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2077fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2078fcf5ef2aSThomas Huth { 2079fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2080fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2081fcf5ef2aSThomas Huth 2082fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2083fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2084fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2085fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2086fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2087fcf5ef2aSThomas Huth #else 2088fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2089fcf5ef2aSThomas Huth #endif 2090fcf5ef2aSThomas Huth 2091fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2092fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2093fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 209461aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 209561aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 209661aa9a69SNikunj A Dadhania } 2097fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2098fcf5ef2aSThomas Huth 2099fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2100fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2101efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2102fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2103fcf5ef2aSThomas Huth } 2104efe843d8SDavid Gibson } 2105fcf5ef2aSThomas Huth 2106fcf5ef2aSThomas Huth /* mulli */ 2107fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2108fcf5ef2aSThomas Huth { 2109fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2110fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2111fcf5ef2aSThomas Huth } 2112fcf5ef2aSThomas Huth 2113fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2114fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2115fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2116fcf5ef2aSThomas Huth { 2117fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2118fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2119fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2120fcf5ef2aSThomas Huth tcg_temp_free(lo); 2121fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2122fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2123fcf5ef2aSThomas Huth } 2124fcf5ef2aSThomas Huth } 2125fcf5ef2aSThomas Huth 2126fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2127fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2128fcf5ef2aSThomas Huth { 2129fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2130fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2131fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2132fcf5ef2aSThomas Huth tcg_temp_free(lo); 2133fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2134fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2135fcf5ef2aSThomas Huth } 2136fcf5ef2aSThomas Huth } 2137fcf5ef2aSThomas Huth 2138fcf5ef2aSThomas Huth /* mulld mulld. */ 2139fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2140fcf5ef2aSThomas Huth { 2141fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2142fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2143efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2144fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2145fcf5ef2aSThomas Huth } 2146efe843d8SDavid Gibson } 2147fcf5ef2aSThomas Huth 2148fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2149fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2150fcf5ef2aSThomas Huth { 2151fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2152fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2153fcf5ef2aSThomas Huth 2154fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2155fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2156fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2157fcf5ef2aSThomas Huth 2158fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2159fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 216061aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 216161aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 216261aa9a69SNikunj A Dadhania } 2163fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2164fcf5ef2aSThomas Huth 2165fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2166fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2167fcf5ef2aSThomas Huth 2168fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2169fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2170fcf5ef2aSThomas Huth } 2171fcf5ef2aSThomas Huth } 2172fcf5ef2aSThomas Huth #endif 2173fcf5ef2aSThomas Huth 2174fcf5ef2aSThomas Huth /* Common subf function */ 2175fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2176fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2177fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2178fcf5ef2aSThomas Huth { 2179fcf5ef2aSThomas Huth TCGv t0 = ret; 2180fcf5ef2aSThomas Huth 2181fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2182fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2183fcf5ef2aSThomas Huth } 2184fcf5ef2aSThomas Huth 2185fcf5ef2aSThomas Huth if (compute_ca) { 2186fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2187fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2188efe843d8SDavid Gibson /* 2189efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2190efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2191efe843d8SDavid Gibson * produce the carry into bit 32. 2192efe843d8SDavid Gibson */ 2193fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2194fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2195fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2196fcf5ef2aSThomas Huth if (add_ca) { 2197fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2198fcf5ef2aSThomas Huth } else { 2199fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2200fcf5ef2aSThomas Huth } 2201fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2202fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2203fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2204fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2205fcf5ef2aSThomas Huth tcg_temp_free(t1); 2206e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 220733903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 220833903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 220933903d0aSNikunj A Dadhania } 2210fcf5ef2aSThomas Huth } else if (add_ca) { 2211fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2212fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2213fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2214fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2215fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 22164c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2217fcf5ef2aSThomas Huth tcg_temp_free(zero); 2218fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2219fcf5ef2aSThomas Huth } else { 2220fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2221fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 22224c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2223fcf5ef2aSThomas Huth } 2224fcf5ef2aSThomas Huth } else if (add_ca) { 2225efe843d8SDavid Gibson /* 2226efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2227efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2228efe843d8SDavid Gibson */ 2229fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2230fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2231fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2232fcf5ef2aSThomas Huth } else { 2233fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2234fcf5ef2aSThomas Huth } 2235fcf5ef2aSThomas Huth 2236fcf5ef2aSThomas Huth if (compute_ov) { 2237fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2238fcf5ef2aSThomas Huth } 2239fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2240fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2241fcf5ef2aSThomas Huth } 2242fcf5ef2aSThomas Huth 224311f4e8f8SRichard Henderson if (t0 != ret) { 2244fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2245fcf5ef2aSThomas Huth tcg_temp_free(t0); 2246fcf5ef2aSThomas Huth } 2247fcf5ef2aSThomas Huth } 2248fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2249fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2250fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2251fcf5ef2aSThomas Huth { \ 2252fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2253fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2254fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2255fcf5ef2aSThomas Huth } 2256fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2257fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2258fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2259fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2260fcf5ef2aSThomas Huth { \ 2261fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2262fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2263fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2264fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2265fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2266fcf5ef2aSThomas Huth } 2267fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2268fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2269fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2270fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2271fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2272fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2273fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2274fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2275fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2276fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2277fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2278fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2279fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2280fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2281fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2282fcf5ef2aSThomas Huth 2283fcf5ef2aSThomas Huth /* subfic */ 2284fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2285fcf5ef2aSThomas Huth { 2286fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2287fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2288fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2289fcf5ef2aSThomas Huth tcg_temp_free(c); 2290fcf5ef2aSThomas Huth } 2291fcf5ef2aSThomas Huth 2292fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2293fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2294fcf5ef2aSThomas Huth { 2295fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2296fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2297fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2298fcf5ef2aSThomas Huth tcg_temp_free(zero); 2299fcf5ef2aSThomas Huth } 2300fcf5ef2aSThomas Huth 2301fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2302fcf5ef2aSThomas Huth { 23031480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 23041480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 23051480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 23061480d71cSNikunj A Dadhania } 2307fcf5ef2aSThomas Huth } 2308fcf5ef2aSThomas Huth 2309fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2310fcf5ef2aSThomas Huth { 2311fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2312fcf5ef2aSThomas Huth } 2313fcf5ef2aSThomas Huth 2314fcf5ef2aSThomas Huth /*** Integer logical ***/ 2315fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2316fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2317fcf5ef2aSThomas Huth { \ 2318fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2319fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2320fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2321fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2322fcf5ef2aSThomas Huth } 2323fcf5ef2aSThomas Huth 2324fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2325fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2326fcf5ef2aSThomas Huth { \ 2327fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2328fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2329fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2330fcf5ef2aSThomas Huth } 2331fcf5ef2aSThomas Huth 2332fcf5ef2aSThomas Huth /* and & and. */ 2333fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2334fcf5ef2aSThomas Huth /* andc & andc. */ 2335fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2336fcf5ef2aSThomas Huth 2337fcf5ef2aSThomas Huth /* andi. */ 2338fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2339fcf5ef2aSThomas Huth { 2340efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2341efe843d8SDavid Gibson UIMM(ctx->opcode)); 2342fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2343fcf5ef2aSThomas Huth } 2344fcf5ef2aSThomas Huth 2345fcf5ef2aSThomas Huth /* andis. */ 2346fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2347fcf5ef2aSThomas Huth { 2348efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2349efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2350fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2351fcf5ef2aSThomas Huth } 2352fcf5ef2aSThomas Huth 2353fcf5ef2aSThomas Huth /* cntlzw */ 2354fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2355fcf5ef2aSThomas Huth { 23569b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23579b8514e5SRichard Henderson 23589b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23599b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 23609b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23619b8514e5SRichard Henderson tcg_temp_free_i32(t); 23629b8514e5SRichard Henderson 2363efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2364fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2365fcf5ef2aSThomas Huth } 2366efe843d8SDavid Gibson } 2367fcf5ef2aSThomas Huth 2368fcf5ef2aSThomas Huth /* cnttzw */ 2369fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2370fcf5ef2aSThomas Huth { 23719b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23729b8514e5SRichard Henderson 23739b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23749b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 23759b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23769b8514e5SRichard Henderson tcg_temp_free_i32(t); 23779b8514e5SRichard Henderson 2378fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2379fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2380fcf5ef2aSThomas Huth } 2381fcf5ef2aSThomas Huth } 2382fcf5ef2aSThomas Huth 2383fcf5ef2aSThomas Huth /* eqv & eqv. */ 2384fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2385fcf5ef2aSThomas Huth /* extsb & extsb. */ 2386fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2387fcf5ef2aSThomas Huth /* extsh & extsh. */ 2388fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2389fcf5ef2aSThomas Huth /* nand & nand. */ 2390fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2391fcf5ef2aSThomas Huth /* nor & nor. */ 2392fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2393fcf5ef2aSThomas Huth 2394fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2395fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2396fcf5ef2aSThomas Huth { 2397fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2398fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2399fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2400fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2401fcf5ef2aSThomas Huth 2402fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2403b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2404fcf5ef2aSThomas Huth } 2405fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2406fcf5ef2aSThomas Huth 2407fcf5ef2aSThomas Huth /* or & or. */ 2408fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2409fcf5ef2aSThomas Huth { 2410fcf5ef2aSThomas Huth int rs, ra, rb; 2411fcf5ef2aSThomas Huth 2412fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2413fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2414fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2415fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2416fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2417efe843d8SDavid Gibson if (rs != rb) { 2418fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2419efe843d8SDavid Gibson } else { 2420fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2421efe843d8SDavid Gibson } 2422efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2423fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2424efe843d8SDavid Gibson } 2425fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2426fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2427fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2428fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2429fcf5ef2aSThomas Huth int prio = 0; 2430fcf5ef2aSThomas Huth 2431fcf5ef2aSThomas Huth switch (rs) { 2432fcf5ef2aSThomas Huth case 1: 2433fcf5ef2aSThomas Huth /* Set process priority to low */ 2434fcf5ef2aSThomas Huth prio = 2; 2435fcf5ef2aSThomas Huth break; 2436fcf5ef2aSThomas Huth case 6: 2437fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2438fcf5ef2aSThomas Huth prio = 3; 2439fcf5ef2aSThomas Huth break; 2440fcf5ef2aSThomas Huth case 2: 2441fcf5ef2aSThomas Huth /* Set process priority to normal */ 2442fcf5ef2aSThomas Huth prio = 4; 2443fcf5ef2aSThomas Huth break; 2444fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2445fcf5ef2aSThomas Huth case 31: 2446fcf5ef2aSThomas Huth if (!ctx->pr) { 2447fcf5ef2aSThomas Huth /* Set process priority to very low */ 2448fcf5ef2aSThomas Huth prio = 1; 2449fcf5ef2aSThomas Huth } 2450fcf5ef2aSThomas Huth break; 2451fcf5ef2aSThomas Huth case 5: 2452fcf5ef2aSThomas Huth if (!ctx->pr) { 2453fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2454fcf5ef2aSThomas Huth prio = 5; 2455fcf5ef2aSThomas Huth } 2456fcf5ef2aSThomas Huth break; 2457fcf5ef2aSThomas Huth case 3: 2458fcf5ef2aSThomas Huth if (!ctx->pr) { 2459fcf5ef2aSThomas Huth /* Set process priority to high */ 2460fcf5ef2aSThomas Huth prio = 6; 2461fcf5ef2aSThomas Huth } 2462fcf5ef2aSThomas Huth break; 2463fcf5ef2aSThomas Huth case 7: 2464fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2465fcf5ef2aSThomas Huth /* Set process priority to very high */ 2466fcf5ef2aSThomas Huth prio = 7; 2467fcf5ef2aSThomas Huth } 2468fcf5ef2aSThomas Huth break; 2469fcf5ef2aSThomas Huth #endif 2470fcf5ef2aSThomas Huth default: 2471fcf5ef2aSThomas Huth break; 2472fcf5ef2aSThomas Huth } 2473fcf5ef2aSThomas Huth if (prio) { 2474fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2475fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2476fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2477fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2478fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2479fcf5ef2aSThomas Huth tcg_temp_free(t0); 2480fcf5ef2aSThomas Huth } 2481fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2482efe843d8SDavid Gibson /* 2483efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2484efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2485efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2486efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2487fcf5ef2aSThomas Huth */ 2488fcf5ef2aSThomas Huth gen_pause(ctx); 2489fcf5ef2aSThomas Huth #endif 2490fcf5ef2aSThomas Huth #endif 2491fcf5ef2aSThomas Huth } 2492fcf5ef2aSThomas Huth } 2493fcf5ef2aSThomas Huth /* orc & orc. */ 2494fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2495fcf5ef2aSThomas Huth 2496fcf5ef2aSThomas Huth /* xor & xor. */ 2497fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2498fcf5ef2aSThomas Huth { 2499fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2500efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2501efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2502efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2503efe843d8SDavid Gibson } else { 2504fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2505efe843d8SDavid Gibson } 2506efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2507fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2508fcf5ef2aSThomas Huth } 2509efe843d8SDavid Gibson } 2510fcf5ef2aSThomas Huth 2511fcf5ef2aSThomas Huth /* ori */ 2512fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2513fcf5ef2aSThomas Huth { 2514fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2515fcf5ef2aSThomas Huth 2516fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2517fcf5ef2aSThomas Huth return; 2518fcf5ef2aSThomas Huth } 2519fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2520fcf5ef2aSThomas Huth } 2521fcf5ef2aSThomas Huth 2522fcf5ef2aSThomas Huth /* oris */ 2523fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2524fcf5ef2aSThomas Huth { 2525fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2526fcf5ef2aSThomas Huth 2527fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2528fcf5ef2aSThomas Huth /* NOP */ 2529fcf5ef2aSThomas Huth return; 2530fcf5ef2aSThomas Huth } 2531efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2532efe843d8SDavid Gibson uimm << 16); 2533fcf5ef2aSThomas Huth } 2534fcf5ef2aSThomas Huth 2535fcf5ef2aSThomas Huth /* xori */ 2536fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2537fcf5ef2aSThomas Huth { 2538fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2539fcf5ef2aSThomas Huth 2540fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2541fcf5ef2aSThomas Huth /* NOP */ 2542fcf5ef2aSThomas Huth return; 2543fcf5ef2aSThomas Huth } 2544fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2545fcf5ef2aSThomas Huth } 2546fcf5ef2aSThomas Huth 2547fcf5ef2aSThomas Huth /* xoris */ 2548fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2549fcf5ef2aSThomas Huth { 2550fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2551fcf5ef2aSThomas Huth 2552fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2553fcf5ef2aSThomas Huth /* NOP */ 2554fcf5ef2aSThomas Huth return; 2555fcf5ef2aSThomas Huth } 2556efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2557efe843d8SDavid Gibson uimm << 16); 2558fcf5ef2aSThomas Huth } 2559fcf5ef2aSThomas Huth 2560fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2561fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2562fcf5ef2aSThomas Huth { 2563fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2564fcf5ef2aSThomas Huth } 2565fcf5ef2aSThomas Huth 2566fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2567fcf5ef2aSThomas Huth { 256879770002SRichard Henderson #if defined(TARGET_PPC64) 2569fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 257079770002SRichard Henderson #else 257179770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 257279770002SRichard Henderson #endif 2573fcf5ef2aSThomas Huth } 2574fcf5ef2aSThomas Huth 2575fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2576fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2577fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2578fcf5ef2aSThomas Huth { 257979770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2580fcf5ef2aSThomas Huth } 2581fcf5ef2aSThomas Huth #endif 2582fcf5ef2aSThomas Huth 2583fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2584fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2585fcf5ef2aSThomas Huth { 2586fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2587fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2588fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2589fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2590fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2591fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2592fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2593fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2594fcf5ef2aSThomas Huth tcg_temp_free(t0); 2595fcf5ef2aSThomas Huth } 2596fcf5ef2aSThomas Huth 2597fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2598fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2599fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2600fcf5ef2aSThomas Huth { 2601fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2602fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2603fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2604fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2605fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2606fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2607fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2608fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2609fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2610fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2611fcf5ef2aSThomas Huth tcg_temp_free(t0); 2612fcf5ef2aSThomas Huth } 2613fcf5ef2aSThomas Huth #endif 2614fcf5ef2aSThomas Huth 2615fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2616fcf5ef2aSThomas Huth /* bpermd */ 2617fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2618fcf5ef2aSThomas Huth { 2619fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2620fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2621fcf5ef2aSThomas Huth } 2622fcf5ef2aSThomas Huth #endif 2623fcf5ef2aSThomas Huth 2624fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2625fcf5ef2aSThomas Huth /* extsw & extsw. */ 2626fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2627fcf5ef2aSThomas Huth 2628fcf5ef2aSThomas Huth /* cntlzd */ 2629fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2630fcf5ef2aSThomas Huth { 26319b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2632efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2633fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2634fcf5ef2aSThomas Huth } 2635efe843d8SDavid Gibson } 2636fcf5ef2aSThomas Huth 2637fcf5ef2aSThomas Huth /* cnttzd */ 2638fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2639fcf5ef2aSThomas Huth { 26409b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2641fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2642fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2643fcf5ef2aSThomas Huth } 2644fcf5ef2aSThomas Huth } 2645fcf5ef2aSThomas Huth 2646fcf5ef2aSThomas Huth /* darn */ 2647fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2648fcf5ef2aSThomas Huth { 2649fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2650fcf5ef2aSThomas Huth 26517e4357f6SRichard Henderson if (l > 2) { 26527e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 26537e4357f6SRichard Henderson } else { 2654f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2655fcf5ef2aSThomas Huth if (l == 0) { 2656fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 26577e4357f6SRichard Henderson } else { 2658fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2659fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 26607e4357f6SRichard Henderson } 2661fcf5ef2aSThomas Huth } 2662fcf5ef2aSThomas Huth } 2663fcf5ef2aSThomas Huth #endif 2664fcf5ef2aSThomas Huth 2665fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2666fcf5ef2aSThomas Huth 2667fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2668fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2669fcf5ef2aSThomas Huth { 2670fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2671fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2672fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2673fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2674fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2675fcf5ef2aSThomas Huth 2676fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2677fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2678fcf5ef2aSThomas Huth } else { 2679fcf5ef2aSThomas Huth target_ulong mask; 2680c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2681fcf5ef2aSThomas Huth TCGv t1; 2682fcf5ef2aSThomas Huth 2683fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2684fcf5ef2aSThomas Huth mb += 32; 2685fcf5ef2aSThomas Huth me += 32; 2686fcf5ef2aSThomas Huth #endif 2687fcf5ef2aSThomas Huth mask = MASK(mb, me); 2688fcf5ef2aSThomas Huth 2689c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2690c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2691c4f6a4a3SDaniele Buono mask_in_32b = false; 2692c4f6a4a3SDaniele Buono } 2693c4f6a4a3SDaniele Buono #endif 2694fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2695c4f6a4a3SDaniele Buono if (mask_in_32b) { 2696fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2697fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2698fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2699fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2700fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2701fcf5ef2aSThomas Huth } else { 2702fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2703fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2704fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2705fcf5ef2aSThomas Huth #else 2706fcf5ef2aSThomas Huth g_assert_not_reached(); 2707fcf5ef2aSThomas Huth #endif 2708fcf5ef2aSThomas Huth } 2709fcf5ef2aSThomas Huth 2710fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2711fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2712fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2713fcf5ef2aSThomas Huth tcg_temp_free(t1); 2714fcf5ef2aSThomas Huth } 2715fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2716fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2717fcf5ef2aSThomas Huth } 2718fcf5ef2aSThomas Huth } 2719fcf5ef2aSThomas Huth 2720fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2721fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2722fcf5ef2aSThomas Huth { 2723fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2724fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27257b4d326fSRichard Henderson int sh = SH(ctx->opcode); 27267b4d326fSRichard Henderson int mb = MB(ctx->opcode); 27277b4d326fSRichard Henderson int me = ME(ctx->opcode); 27287b4d326fSRichard Henderson int len = me - mb + 1; 27297b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2730fcf5ef2aSThomas Huth 27317b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 27327b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27337b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 27347b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2735fcf5ef2aSThomas Huth } else { 2736fcf5ef2aSThomas Huth target_ulong mask; 2737c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2738fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2739fcf5ef2aSThomas Huth mb += 32; 2740fcf5ef2aSThomas Huth me += 32; 2741fcf5ef2aSThomas Huth #endif 2742fcf5ef2aSThomas Huth mask = MASK(mb, me); 2743c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2744c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2745c4f6a4a3SDaniele Buono mask_in_32b = false; 2746c4f6a4a3SDaniele Buono } 2747c4f6a4a3SDaniele Buono #endif 2748c4f6a4a3SDaniele Buono if (mask_in_32b) { 27497b4d326fSRichard Henderson if (sh == 0) { 27507b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 275194f040aaSVitaly Chikunov } else { 2752fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2753fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2754fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2755fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2756fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2757fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 275894f040aaSVitaly Chikunov } 2759fcf5ef2aSThomas Huth } else { 2760fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2761fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2762fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2763fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2764fcf5ef2aSThomas Huth #else 2765fcf5ef2aSThomas Huth g_assert_not_reached(); 2766fcf5ef2aSThomas Huth #endif 2767fcf5ef2aSThomas Huth } 2768fcf5ef2aSThomas Huth } 2769fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2770fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2771fcf5ef2aSThomas Huth } 2772fcf5ef2aSThomas Huth } 2773fcf5ef2aSThomas Huth 2774fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2775fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2776fcf5ef2aSThomas Huth { 2777fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2778fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2779fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2780fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2781fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2782fcf5ef2aSThomas Huth target_ulong mask; 2783c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2784fcf5ef2aSThomas Huth 2785fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2786fcf5ef2aSThomas Huth mb += 32; 2787fcf5ef2aSThomas Huth me += 32; 2788fcf5ef2aSThomas Huth #endif 2789fcf5ef2aSThomas Huth mask = MASK(mb, me); 2790fcf5ef2aSThomas Huth 2791c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2792c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2793c4f6a4a3SDaniele Buono mask_in_32b = false; 2794c4f6a4a3SDaniele Buono } 2795c4f6a4a3SDaniele Buono #endif 2796c4f6a4a3SDaniele Buono if (mask_in_32b) { 2797fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2798fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2799fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2800fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2801fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2802fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2803fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2804fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2805fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2806fcf5ef2aSThomas Huth } else { 2807fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2808fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2809fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2810fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2811fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2812fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2813fcf5ef2aSThomas Huth #else 2814fcf5ef2aSThomas Huth g_assert_not_reached(); 2815fcf5ef2aSThomas Huth #endif 2816fcf5ef2aSThomas Huth } 2817fcf5ef2aSThomas Huth 2818fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2819fcf5ef2aSThomas Huth 2820fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2821fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2822fcf5ef2aSThomas Huth } 2823fcf5ef2aSThomas Huth } 2824fcf5ef2aSThomas Huth 2825fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2826fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2827fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2828fcf5ef2aSThomas Huth { \ 2829fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2830fcf5ef2aSThomas Huth } \ 2831fcf5ef2aSThomas Huth \ 2832fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2833fcf5ef2aSThomas Huth { \ 2834fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2835fcf5ef2aSThomas Huth } 2836fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2837fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2838fcf5ef2aSThomas Huth { \ 2839fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2840fcf5ef2aSThomas Huth } \ 2841fcf5ef2aSThomas Huth \ 2842fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2843fcf5ef2aSThomas Huth { \ 2844fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2845fcf5ef2aSThomas Huth } \ 2846fcf5ef2aSThomas Huth \ 2847fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2848fcf5ef2aSThomas Huth { \ 2849fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2850fcf5ef2aSThomas Huth } \ 2851fcf5ef2aSThomas Huth \ 2852fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2853fcf5ef2aSThomas Huth { \ 2854fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2855fcf5ef2aSThomas Huth } 2856fcf5ef2aSThomas Huth 2857fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2858fcf5ef2aSThomas Huth { 2859fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2860fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 28617b4d326fSRichard Henderson int len = me - mb + 1; 28627b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2863fcf5ef2aSThomas Huth 28647b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 28657b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 28667b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 28677b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2868fcf5ef2aSThomas Huth } else { 2869fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2870fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2871fcf5ef2aSThomas Huth } 2872fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2873fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2874fcf5ef2aSThomas Huth } 2875fcf5ef2aSThomas Huth } 2876fcf5ef2aSThomas Huth 2877fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2878fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2879fcf5ef2aSThomas Huth { 2880fcf5ef2aSThomas Huth uint32_t sh, mb; 2881fcf5ef2aSThomas Huth 2882fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2883fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2884fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2885fcf5ef2aSThomas Huth } 2886fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2887fcf5ef2aSThomas Huth 2888fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2889fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2890fcf5ef2aSThomas Huth { 2891fcf5ef2aSThomas Huth uint32_t sh, me; 2892fcf5ef2aSThomas Huth 2893fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2894fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2895fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2896fcf5ef2aSThomas Huth } 2897fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2898fcf5ef2aSThomas Huth 2899fcf5ef2aSThomas Huth /* rldic - rldic. */ 2900fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2901fcf5ef2aSThomas Huth { 2902fcf5ef2aSThomas Huth uint32_t sh, mb; 2903fcf5ef2aSThomas Huth 2904fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2905fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2906fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2907fcf5ef2aSThomas Huth } 2908fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2909fcf5ef2aSThomas Huth 2910fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2911fcf5ef2aSThomas Huth { 2912fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2913fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2914fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2915fcf5ef2aSThomas Huth TCGv t0; 2916fcf5ef2aSThomas Huth 2917fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2918fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2919fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2920fcf5ef2aSThomas Huth tcg_temp_free(t0); 2921fcf5ef2aSThomas Huth 2922fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2923fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2924fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2925fcf5ef2aSThomas Huth } 2926fcf5ef2aSThomas Huth } 2927fcf5ef2aSThomas Huth 2928fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2929fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2930fcf5ef2aSThomas Huth { 2931fcf5ef2aSThomas Huth uint32_t mb; 2932fcf5ef2aSThomas Huth 2933fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2934fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2935fcf5ef2aSThomas Huth } 2936fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2937fcf5ef2aSThomas Huth 2938fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2939fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2940fcf5ef2aSThomas Huth { 2941fcf5ef2aSThomas Huth uint32_t me; 2942fcf5ef2aSThomas Huth 2943fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2944fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2945fcf5ef2aSThomas Huth } 2946fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2947fcf5ef2aSThomas Huth 2948fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2949fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2950fcf5ef2aSThomas Huth { 2951fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2952fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2953fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2954fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2955fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2956fcf5ef2aSThomas Huth 2957fcf5ef2aSThomas Huth if (mb <= me) { 2958fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2959fcf5ef2aSThomas Huth } else { 2960fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2961fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2962fcf5ef2aSThomas Huth 2963fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2964fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2965fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2966fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2967fcf5ef2aSThomas Huth tcg_temp_free(t1); 2968fcf5ef2aSThomas Huth } 2969fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2970fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2971fcf5ef2aSThomas Huth } 2972fcf5ef2aSThomas Huth } 2973fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2974fcf5ef2aSThomas Huth #endif 2975fcf5ef2aSThomas Huth 2976fcf5ef2aSThomas Huth /*** Integer shift ***/ 2977fcf5ef2aSThomas Huth 2978fcf5ef2aSThomas Huth /* slw & slw. */ 2979fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2980fcf5ef2aSThomas Huth { 2981fcf5ef2aSThomas Huth TCGv t0, t1; 2982fcf5ef2aSThomas Huth 2983fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2984fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2985fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2986fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2987fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2988fcf5ef2aSThomas Huth #else 2989fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2990fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2991fcf5ef2aSThomas Huth #endif 2992fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2993fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2994fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2995fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2996fcf5ef2aSThomas Huth tcg_temp_free(t1); 2997fcf5ef2aSThomas Huth tcg_temp_free(t0); 2998fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2999efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3000fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3001fcf5ef2aSThomas Huth } 3002efe843d8SDavid Gibson } 3003fcf5ef2aSThomas Huth 3004fcf5ef2aSThomas Huth /* sraw & sraw. */ 3005fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 3006fcf5ef2aSThomas Huth { 3007fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 3008fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3009efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3010fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3011fcf5ef2aSThomas Huth } 3012efe843d8SDavid Gibson } 3013fcf5ef2aSThomas Huth 3014fcf5ef2aSThomas Huth /* srawi & srawi. */ 3015fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 3016fcf5ef2aSThomas Huth { 3017fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 3018fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3019fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3020fcf5ef2aSThomas Huth if (sh == 0) { 3021fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3022fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3023af1c259fSSandipan Das if (is_isa300(ctx)) { 3024af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3025af1c259fSSandipan Das } 3026fcf5ef2aSThomas Huth } else { 3027fcf5ef2aSThomas Huth TCGv t0; 3028fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3029fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 3030fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3031fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 3032fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3033fcf5ef2aSThomas Huth tcg_temp_free(t0); 3034fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3035af1c259fSSandipan Das if (is_isa300(ctx)) { 3036af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3037af1c259fSSandipan Das } 3038fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 3039fcf5ef2aSThomas Huth } 3040fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3041fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3042fcf5ef2aSThomas Huth } 3043fcf5ef2aSThomas Huth } 3044fcf5ef2aSThomas Huth 3045fcf5ef2aSThomas Huth /* srw & srw. */ 3046fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 3047fcf5ef2aSThomas Huth { 3048fcf5ef2aSThomas Huth TCGv t0, t1; 3049fcf5ef2aSThomas Huth 3050fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3051fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3052fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3053fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3054fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3055fcf5ef2aSThomas Huth #else 3056fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3057fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3058fcf5ef2aSThomas Huth #endif 3059fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3060fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3061fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3062fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3063fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3064fcf5ef2aSThomas Huth tcg_temp_free(t1); 3065fcf5ef2aSThomas Huth tcg_temp_free(t0); 3066efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3067fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3068fcf5ef2aSThomas Huth } 3069efe843d8SDavid Gibson } 3070fcf5ef2aSThomas Huth 3071fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3072fcf5ef2aSThomas Huth /* sld & sld. */ 3073fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3074fcf5ef2aSThomas Huth { 3075fcf5ef2aSThomas Huth TCGv t0, t1; 3076fcf5ef2aSThomas Huth 3077fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3078fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3079fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3080fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3081fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3082fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3083fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3084fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3085fcf5ef2aSThomas Huth tcg_temp_free(t1); 3086fcf5ef2aSThomas Huth tcg_temp_free(t0); 3087efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3088fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3089fcf5ef2aSThomas Huth } 3090efe843d8SDavid Gibson } 3091fcf5ef2aSThomas Huth 3092fcf5ef2aSThomas Huth /* srad & srad. */ 3093fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3094fcf5ef2aSThomas Huth { 3095fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3096fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3097efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3098fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3099fcf5ef2aSThomas Huth } 3100efe843d8SDavid Gibson } 3101fcf5ef2aSThomas Huth /* sradi & sradi. */ 3102fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3103fcf5ef2aSThomas Huth { 3104fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3105fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3106fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3107fcf5ef2aSThomas Huth if (sh == 0) { 3108fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3109fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3110af1c259fSSandipan Das if (is_isa300(ctx)) { 3111af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3112af1c259fSSandipan Das } 3113fcf5ef2aSThomas Huth } else { 3114fcf5ef2aSThomas Huth TCGv t0; 3115fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3116fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3117fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3118fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3119fcf5ef2aSThomas Huth tcg_temp_free(t0); 3120fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3121af1c259fSSandipan Das if (is_isa300(ctx)) { 3122af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3123af1c259fSSandipan Das } 3124fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3125fcf5ef2aSThomas Huth } 3126fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3127fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3128fcf5ef2aSThomas Huth } 3129fcf5ef2aSThomas Huth } 3130fcf5ef2aSThomas Huth 3131fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3132fcf5ef2aSThomas Huth { 3133fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3134fcf5ef2aSThomas Huth } 3135fcf5ef2aSThomas Huth 3136fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3137fcf5ef2aSThomas Huth { 3138fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3139fcf5ef2aSThomas Huth } 3140fcf5ef2aSThomas Huth 3141fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3142fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3143fcf5ef2aSThomas Huth { 3144fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3145fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3146fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3147fcf5ef2aSThomas Huth 3148fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3149fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3150fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3151fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3152fcf5ef2aSThomas Huth } 3153fcf5ef2aSThomas Huth } 3154fcf5ef2aSThomas Huth 3155fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3156fcf5ef2aSThomas Huth { 3157fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3158fcf5ef2aSThomas Huth } 3159fcf5ef2aSThomas Huth 3160fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3161fcf5ef2aSThomas Huth { 3162fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3163fcf5ef2aSThomas Huth } 3164fcf5ef2aSThomas Huth 3165fcf5ef2aSThomas Huth /* srd & srd. */ 3166fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3167fcf5ef2aSThomas Huth { 3168fcf5ef2aSThomas Huth TCGv t0, t1; 3169fcf5ef2aSThomas Huth 3170fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3171fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3172fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3173fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3174fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3175fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3176fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3177fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3178fcf5ef2aSThomas Huth tcg_temp_free(t1); 3179fcf5ef2aSThomas Huth tcg_temp_free(t0); 3180efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3181fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3182fcf5ef2aSThomas Huth } 3183efe843d8SDavid Gibson } 3184fcf5ef2aSThomas Huth #endif 3185fcf5ef2aSThomas Huth 3186fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3187fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3188fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3189fcf5ef2aSThomas Huth target_long maskl) 3190fcf5ef2aSThomas Huth { 3191fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3192fcf5ef2aSThomas Huth 3193fcf5ef2aSThomas Huth simm &= ~maskl; 3194fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3195fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3196fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3197fcf5ef2aSThomas Huth } 3198fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3199fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3200fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3201fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3202fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3203fcf5ef2aSThomas Huth } 3204fcf5ef2aSThomas Huth } else { 3205fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3206fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3207fcf5ef2aSThomas Huth } else { 3208fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3209fcf5ef2aSThomas Huth } 3210fcf5ef2aSThomas Huth } 3211fcf5ef2aSThomas Huth } 3212fcf5ef2aSThomas Huth 3213fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3214fcf5ef2aSThomas Huth { 3215fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3216fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3217fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3218fcf5ef2aSThomas Huth } else { 3219fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3220fcf5ef2aSThomas Huth } 3221fcf5ef2aSThomas Huth } else { 3222fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3223fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3224fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3225fcf5ef2aSThomas Huth } 3226fcf5ef2aSThomas Huth } 3227fcf5ef2aSThomas Huth } 3228fcf5ef2aSThomas Huth 3229fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3230fcf5ef2aSThomas Huth { 3231fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3232fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3233fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3234fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3235fcf5ef2aSThomas Huth } else { 3236fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3237fcf5ef2aSThomas Huth } 3238fcf5ef2aSThomas Huth } 3239fcf5ef2aSThomas Huth 3240fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3241fcf5ef2aSThomas Huth target_long val) 3242fcf5ef2aSThomas Huth { 3243fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3244fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3245fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3246fcf5ef2aSThomas Huth } 3247fcf5ef2aSThomas Huth } 3248fcf5ef2aSThomas Huth 3249fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3250fcf5ef2aSThomas Huth { 3251fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3252fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3253fcf5ef2aSThomas Huth } 3254fcf5ef2aSThomas Huth 3255fcf5ef2aSThomas Huth /*** Integer load ***/ 3256fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3257fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3258fcf5ef2aSThomas Huth 3259fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3260fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3261fcf5ef2aSThomas Huth TCGv val, \ 3262fcf5ef2aSThomas Huth TCGv addr) \ 3263fcf5ef2aSThomas Huth { \ 3264fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3265fcf5ef2aSThomas Huth } 3266fcf5ef2aSThomas Huth 3267fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3268fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3269fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3270fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3271fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3272fcf5ef2aSThomas Huth 3273fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3274fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3275fcf5ef2aSThomas Huth 3276fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3277fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3278fcf5ef2aSThomas Huth TCGv_i64 val, \ 3279fcf5ef2aSThomas Huth TCGv addr) \ 3280fcf5ef2aSThomas Huth { \ 3281fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3282fcf5ef2aSThomas Huth } 3283fcf5ef2aSThomas Huth 3284fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3285fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3286fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3287fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3288fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3289fcf5ef2aSThomas Huth 3290fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3291fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3292fcf5ef2aSThomas Huth #endif 3293fcf5ef2aSThomas Huth 3294fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3295fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3296fcf5ef2aSThomas Huth TCGv val, \ 3297fcf5ef2aSThomas Huth TCGv addr) \ 3298fcf5ef2aSThomas Huth { \ 3299fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3300fcf5ef2aSThomas Huth } 3301fcf5ef2aSThomas Huth 3302fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3303fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3304fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3305fcf5ef2aSThomas Huth 3306fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3307fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3308fcf5ef2aSThomas Huth 3309fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3310fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3311fcf5ef2aSThomas Huth TCGv_i64 val, \ 3312fcf5ef2aSThomas Huth TCGv addr) \ 3313fcf5ef2aSThomas Huth { \ 3314fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3315fcf5ef2aSThomas Huth } 3316fcf5ef2aSThomas Huth 3317fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3318fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3319fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3320fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3321fcf5ef2aSThomas Huth 3322fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3323fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3324fcf5ef2aSThomas Huth #endif 3325fcf5ef2aSThomas Huth 3326fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3327fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3328fcf5ef2aSThomas Huth { \ 3329fcf5ef2aSThomas Huth TCGv EA; \ 3330fcf5ef2aSThomas Huth chk; \ 3331fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3332fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3333fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3334fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3335fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3336fcf5ef2aSThomas Huth } 3337fcf5ef2aSThomas Huth 3338fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3339fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3340fcf5ef2aSThomas Huth 3341fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3342fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3343fcf5ef2aSThomas Huth 334450728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 334550728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 334650728199SRoman Kapl { \ 334750728199SRoman Kapl TCGv EA; \ 334850728199SRoman Kapl CHK_SV; \ 334950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 335050728199SRoman Kapl EA = tcg_temp_new(); \ 335150728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 335250728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 335350728199SRoman Kapl tcg_temp_free(EA); \ 335450728199SRoman Kapl } 335550728199SRoman Kapl 335650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 335750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 335850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 335950728199SRoman Kapl #if defined(TARGET_PPC64) 336050728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 336150728199SRoman Kapl #endif 336250728199SRoman Kapl 3363fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3364fcf5ef2aSThomas Huth /* CI load/store variants */ 3365fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3366fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3367fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3368fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3369fcf5ef2aSThomas Huth 3370fcf5ef2aSThomas Huth /* lq */ 3371fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3372fcf5ef2aSThomas Huth { 3373fcf5ef2aSThomas Huth int ra, rd; 337494bf2658SRichard Henderson TCGv EA, hi, lo; 3375fcf5ef2aSThomas Huth 3376fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3377fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3378fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3379fcf5ef2aSThomas Huth 3380fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3381fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3382fcf5ef2aSThomas Huth return; 3383fcf5ef2aSThomas Huth } 3384fcf5ef2aSThomas Huth 3385fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3386fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3387fcf5ef2aSThomas Huth return; 3388fcf5ef2aSThomas Huth } 3389fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3390fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3391fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3392fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3393fcf5ef2aSThomas Huth return; 3394fcf5ef2aSThomas Huth } 3395fcf5ef2aSThomas Huth 3396fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3397fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3398fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3399fcf5ef2aSThomas Huth 340094bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 340194bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 340294bf2658SRichard Henderson hi = cpu_gpr[rd]; 340394bf2658SRichard Henderson 340494bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3405f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 340694bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 340794bf2658SRichard Henderson if (ctx->le_mode) { 340894bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 340994bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3410fcf5ef2aSThomas Huth } else { 341194bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 341294bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 341394bf2658SRichard Henderson } 341494bf2658SRichard Henderson tcg_temp_free_i32(oi); 341594bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3416f34ec0f6SRichard Henderson } else { 341794bf2658SRichard Henderson /* Restart with exclusive lock. */ 341894bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 341994bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3420f34ec0f6SRichard Henderson } 342194bf2658SRichard Henderson } else if (ctx->le_mode) { 342294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3423fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 342494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 342594bf2658SRichard Henderson } else { 342694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 342794bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 342894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3429fcf5ef2aSThomas Huth } 3430fcf5ef2aSThomas Huth tcg_temp_free(EA); 3431fcf5ef2aSThomas Huth } 3432fcf5ef2aSThomas Huth #endif 3433fcf5ef2aSThomas Huth 3434fcf5ef2aSThomas Huth /*** Integer store ***/ 3435fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 3436fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3437fcf5ef2aSThomas Huth { \ 3438fcf5ef2aSThomas Huth TCGv EA; \ 3439fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3440fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3441fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3442fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3443fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3444fcf5ef2aSThomas Huth } 3445fcf5ef2aSThomas Huth 3446fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 3447fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 3448fcf5ef2aSThomas Huth { \ 3449fcf5ef2aSThomas Huth TCGv EA; \ 3450fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3451fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3452fcf5ef2aSThomas Huth return; \ 3453fcf5ef2aSThomas Huth } \ 3454fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3455fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3456fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3457fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3458fcf5ef2aSThomas Huth else \ 3459fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3460fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3461fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3462fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3463fcf5ef2aSThomas Huth } 3464fcf5ef2aSThomas Huth 3465fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 3466fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3467fcf5ef2aSThomas Huth { \ 3468fcf5ef2aSThomas Huth TCGv EA; \ 3469fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3470fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3471fcf5ef2aSThomas Huth return; \ 3472fcf5ef2aSThomas Huth } \ 3473fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3474fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3475fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3476fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3477fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3478fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3479fcf5ef2aSThomas Huth } 3480fcf5ef2aSThomas Huth 3481fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3482fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3483fcf5ef2aSThomas Huth { \ 3484fcf5ef2aSThomas Huth TCGv EA; \ 3485fcf5ef2aSThomas Huth chk; \ 3486fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3487fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3488fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3489fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3490fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3491fcf5ef2aSThomas Huth } 3492fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3493fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3494fcf5ef2aSThomas Huth 3495fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3496fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3497fcf5ef2aSThomas Huth 3498fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 3499fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 3500fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 3501fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 3502fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 3503fcf5ef2aSThomas Huth 3504fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 3505fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 3506fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 3507fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 3508fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 3509fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 351050728199SRoman Kapl 351150728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 351250728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 351350728199SRoman Kapl { \ 351450728199SRoman Kapl TCGv EA; \ 351550728199SRoman Kapl CHK_SV; \ 351650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 351750728199SRoman Kapl EA = tcg_temp_new(); \ 351850728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 351950728199SRoman Kapl tcg_gen_qemu_st_tl( \ 352050728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 352150728199SRoman Kapl tcg_temp_free(EA); \ 352250728199SRoman Kapl } 352350728199SRoman Kapl 352450728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 352550728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 352650728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 352750728199SRoman Kapl #if defined(TARGET_PPC64) 352850728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 352950728199SRoman Kapl #endif 353050728199SRoman Kapl 3531fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3532fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 3533fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 3534fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3535fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3536fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3537fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3538fcf5ef2aSThomas Huth 3539fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3540fcf5ef2aSThomas Huth { 3541fcf5ef2aSThomas Huth int rs; 3542fcf5ef2aSThomas Huth TCGv EA; 3543fcf5ef2aSThomas Huth 3544fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3545fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3546fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3547fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3548f89ced5fSRichard Henderson TCGv hi, lo; 3549fcf5ef2aSThomas Huth 3550fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3551fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3552fcf5ef2aSThomas Huth } 3553fcf5ef2aSThomas Huth 3554fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3555fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3556fcf5ef2aSThomas Huth return; 3557fcf5ef2aSThomas Huth } 3558fcf5ef2aSThomas Huth 3559fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3560fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3561fcf5ef2aSThomas Huth return; 3562fcf5ef2aSThomas Huth } 3563fcf5ef2aSThomas Huth 3564fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3565fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3566fcf5ef2aSThomas Huth return; 3567fcf5ef2aSThomas Huth } 3568fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3569fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3570fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3571fcf5ef2aSThomas Huth 3572f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3573f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3574f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3575f89ced5fSRichard Henderson 3576f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3577f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3578f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3579f89ced5fSRichard Henderson if (ctx->le_mode) { 3580f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 3581f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3582fcf5ef2aSThomas Huth } else { 3583f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 3584f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3585f89ced5fSRichard Henderson } 3586f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3587f34ec0f6SRichard Henderson } else { 3588f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3589f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3590f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3591f34ec0f6SRichard Henderson } 3592f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3593f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3594fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3595f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3596f89ced5fSRichard Henderson } else { 3597f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3598f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3599f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3600fcf5ef2aSThomas Huth } 3601fcf5ef2aSThomas Huth tcg_temp_free(EA); 3602fcf5ef2aSThomas Huth } else { 3603fcf5ef2aSThomas Huth /* std / stdu */ 3604fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3605fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3606fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3607fcf5ef2aSThomas Huth return; 3608fcf5ef2aSThomas Huth } 3609fcf5ef2aSThomas Huth } 3610fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3611fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3612fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3613fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3614efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3615fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3616efe843d8SDavid Gibson } 3617fcf5ef2aSThomas Huth tcg_temp_free(EA); 3618fcf5ef2aSThomas Huth } 3619fcf5ef2aSThomas Huth } 3620fcf5ef2aSThomas Huth #endif 3621fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3622fcf5ef2aSThomas Huth 3623fcf5ef2aSThomas Huth /* lhbrx */ 3624fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3625fcf5ef2aSThomas Huth 3626fcf5ef2aSThomas Huth /* lwbrx */ 3627fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3628fcf5ef2aSThomas Huth 3629fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3630fcf5ef2aSThomas Huth /* ldbrx */ 3631fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3632fcf5ef2aSThomas Huth /* stdbrx */ 3633fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3634fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3635fcf5ef2aSThomas Huth 3636fcf5ef2aSThomas Huth /* sthbrx */ 3637fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3638fcf5ef2aSThomas Huth /* stwbrx */ 3639fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3640fcf5ef2aSThomas Huth 3641fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3642fcf5ef2aSThomas Huth 3643fcf5ef2aSThomas Huth /* lmw */ 3644fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3645fcf5ef2aSThomas Huth { 3646fcf5ef2aSThomas Huth TCGv t0; 3647fcf5ef2aSThomas Huth TCGv_i32 t1; 3648fcf5ef2aSThomas Huth 3649fcf5ef2aSThomas Huth if (ctx->le_mode) { 3650fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3651fcf5ef2aSThomas Huth return; 3652fcf5ef2aSThomas Huth } 3653fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3654fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3655fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3656fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3657fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3658fcf5ef2aSThomas Huth tcg_temp_free(t0); 3659fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3660fcf5ef2aSThomas Huth } 3661fcf5ef2aSThomas Huth 3662fcf5ef2aSThomas Huth /* stmw */ 3663fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3664fcf5ef2aSThomas Huth { 3665fcf5ef2aSThomas Huth TCGv t0; 3666fcf5ef2aSThomas Huth TCGv_i32 t1; 3667fcf5ef2aSThomas Huth 3668fcf5ef2aSThomas Huth if (ctx->le_mode) { 3669fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3670fcf5ef2aSThomas Huth return; 3671fcf5ef2aSThomas Huth } 3672fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3673fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3674fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3675fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3676fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3677fcf5ef2aSThomas Huth tcg_temp_free(t0); 3678fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3679fcf5ef2aSThomas Huth } 3680fcf5ef2aSThomas Huth 3681fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3682fcf5ef2aSThomas Huth 3683fcf5ef2aSThomas Huth /* lswi */ 3684efe843d8SDavid Gibson /* 3685efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3686efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3687efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3688efe843d8SDavid Gibson * spec... 3689fcf5ef2aSThomas Huth */ 3690fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3691fcf5ef2aSThomas Huth { 3692fcf5ef2aSThomas Huth TCGv t0; 3693fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3694fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3695fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3696fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3697fcf5ef2aSThomas Huth int nr; 3698fcf5ef2aSThomas Huth 3699fcf5ef2aSThomas Huth if (ctx->le_mode) { 3700fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3701fcf5ef2aSThomas Huth return; 3702fcf5ef2aSThomas Huth } 3703efe843d8SDavid Gibson if (nb == 0) { 3704fcf5ef2aSThomas Huth nb = 32; 3705efe843d8SDavid Gibson } 3706f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3707fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3708fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3709fcf5ef2aSThomas Huth return; 3710fcf5ef2aSThomas Huth } 3711fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3712fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3713fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3714fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3715fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3716fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3717fcf5ef2aSThomas Huth tcg_temp_free(t0); 3718fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3719fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3720fcf5ef2aSThomas Huth } 3721fcf5ef2aSThomas Huth 3722fcf5ef2aSThomas Huth /* lswx */ 3723fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3724fcf5ef2aSThomas Huth { 3725fcf5ef2aSThomas Huth TCGv t0; 3726fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3727fcf5ef2aSThomas Huth 3728fcf5ef2aSThomas Huth if (ctx->le_mode) { 3729fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3730fcf5ef2aSThomas Huth return; 3731fcf5ef2aSThomas Huth } 3732fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3733fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3734fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3735fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3736fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3737fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3738fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3739fcf5ef2aSThomas Huth tcg_temp_free(t0); 3740fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3741fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3742fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3743fcf5ef2aSThomas Huth } 3744fcf5ef2aSThomas Huth 3745fcf5ef2aSThomas Huth /* stswi */ 3746fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3747fcf5ef2aSThomas Huth { 3748fcf5ef2aSThomas Huth TCGv t0; 3749fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3750fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3751fcf5ef2aSThomas Huth 3752fcf5ef2aSThomas Huth if (ctx->le_mode) { 3753fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3754fcf5ef2aSThomas Huth return; 3755fcf5ef2aSThomas Huth } 3756fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3757fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3758fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3759efe843d8SDavid Gibson if (nb == 0) { 3760fcf5ef2aSThomas Huth nb = 32; 3761efe843d8SDavid Gibson } 3762fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3763fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3764fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3765fcf5ef2aSThomas Huth tcg_temp_free(t0); 3766fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3767fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3768fcf5ef2aSThomas Huth } 3769fcf5ef2aSThomas Huth 3770fcf5ef2aSThomas Huth /* stswx */ 3771fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3772fcf5ef2aSThomas Huth { 3773fcf5ef2aSThomas Huth TCGv t0; 3774fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3775fcf5ef2aSThomas Huth 3776fcf5ef2aSThomas Huth if (ctx->le_mode) { 3777fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3778fcf5ef2aSThomas Huth return; 3779fcf5ef2aSThomas Huth } 3780fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3781fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3782fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3783fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3784fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3785fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3786fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3787fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3788fcf5ef2aSThomas Huth tcg_temp_free(t0); 3789fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3790fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3791fcf5ef2aSThomas Huth } 3792fcf5ef2aSThomas Huth 3793fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3794fcf5ef2aSThomas Huth /* eieio */ 3795fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3796fcf5ef2aSThomas Huth { 3797c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3798c8fd8373SCédric Le Goater 3799c8fd8373SCédric Le Goater /* 3800c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3801c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3802c8fd8373SCédric Le Goater */ 3803c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3804c8fd8373SCédric Le Goater /* 3805c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3806c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3807c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3808c8fd8373SCédric Le Goater * complain to the user. 3809c8fd8373SCédric Le Goater */ 3810c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3811c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 38122c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3813c8fd8373SCédric Le Goater } else { 3814c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3815c8fd8373SCédric Le Goater } 3816c8fd8373SCédric Le Goater } 3817c8fd8373SCédric Le Goater 3818c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3819fcf5ef2aSThomas Huth } 3820fcf5ef2aSThomas Huth 3821fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3822fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3823fcf5ef2aSThomas Huth { 3824fcf5ef2aSThomas Huth TCGv_i32 t; 3825fcf5ef2aSThomas Huth TCGLabel *l; 3826fcf5ef2aSThomas Huth 3827fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3828fcf5ef2aSThomas Huth return; 3829fcf5ef2aSThomas Huth } 3830fcf5ef2aSThomas Huth l = gen_new_label(); 3831fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3832fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3833fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3834fcf5ef2aSThomas Huth if (global) { 3835fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3836fcf5ef2aSThomas Huth } else { 3837fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3838fcf5ef2aSThomas Huth } 3839fcf5ef2aSThomas Huth gen_set_label(l); 3840fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3841fcf5ef2aSThomas Huth } 3842fcf5ef2aSThomas Huth #else 3843fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3844fcf5ef2aSThomas Huth #endif 3845fcf5ef2aSThomas Huth 3846fcf5ef2aSThomas Huth /* isync */ 3847fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3848fcf5ef2aSThomas Huth { 3849fcf5ef2aSThomas Huth /* 3850fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3851fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3852fcf5ef2aSThomas Huth */ 3853fcf5ef2aSThomas Huth if (!ctx->pr) { 3854fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3855fcf5ef2aSThomas Huth } 38564771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3857d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3858fcf5ef2aSThomas Huth } 3859fcf5ef2aSThomas Huth 3860fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3861fcf5ef2aSThomas Huth 386214776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 38632a4e6c1bSRichard Henderson { 38642a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 38652a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 38662a4e6c1bSRichard Henderson 38672a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 38682a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 38692a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 38702a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 38712a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 38722a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 38732a4e6c1bSRichard Henderson tcg_temp_free(t0); 38742a4e6c1bSRichard Henderson } 38752a4e6c1bSRichard Henderson 3876fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3877fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3878fcf5ef2aSThomas Huth { \ 38792a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3880fcf5ef2aSThomas Huth } 3881fcf5ef2aSThomas Huth 3882fcf5ef2aSThomas Huth /* lwarx */ 3883fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3884fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3885fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3886fcf5ef2aSThomas Huth 388714776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 388820923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 388920923c1dSRichard Henderson { 389020923c1dSRichard Henderson TCGv t = tcg_temp_new(); 389120923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 389220923c1dSRichard Henderson TCGv u = tcg_temp_new(); 389320923c1dSRichard Henderson 389420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 389520923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 389620923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 389720923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 389820923c1dSRichard Henderson 389920923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 390020923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 390120923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 390220923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 390320923c1dSRichard Henderson 390420923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 390520923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 390620923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 390720923c1dSRichard Henderson 390820923c1dSRichard Henderson tcg_temp_free(t); 390920923c1dSRichard Henderson tcg_temp_free(t2); 391020923c1dSRichard Henderson tcg_temp_free(u); 391120923c1dSRichard Henderson } 391220923c1dSRichard Henderson 391314776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 391420ba8504SRichard Henderson { 391520ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 391620ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 391720923c1dSRichard Henderson int rt = rD(ctx->opcode); 391820923c1dSRichard Henderson bool need_serial; 391920ba8504SRichard Henderson TCGv src, dst; 392020ba8504SRichard Henderson 392120ba8504SRichard Henderson gen_addr_register(ctx, EA); 392220923c1dSRichard Henderson dst = cpu_gpr[rt]; 392320923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 392420ba8504SRichard Henderson 392520923c1dSRichard Henderson need_serial = false; 392620ba8504SRichard Henderson memop |= MO_ALIGN; 392720ba8504SRichard Henderson switch (gpr_FC) { 392820ba8504SRichard Henderson case 0: /* Fetch and add */ 392920ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 393020ba8504SRichard Henderson break; 393120ba8504SRichard Henderson case 1: /* Fetch and xor */ 393220ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 393320ba8504SRichard Henderson break; 393420ba8504SRichard Henderson case 2: /* Fetch and or */ 393520ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 393620ba8504SRichard Henderson break; 393720ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 393820ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 393920ba8504SRichard Henderson break; 3940b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3941b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3942b8ce0f86SRichard Henderson break; 3943b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3944b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3945b8ce0f86SRichard Henderson break; 3946b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3947b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3948b8ce0f86SRichard Henderson break; 3949b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3950b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3951b8ce0f86SRichard Henderson break; 395220ba8504SRichard Henderson case 8: /* Swap */ 395320ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 395420ba8504SRichard Henderson break; 395520923c1dSRichard Henderson 395620923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 395720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 395820923c1dSRichard Henderson need_serial = true; 395920923c1dSRichard Henderson } else { 396020923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 396120923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 396220923c1dSRichard Henderson 396320923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 396420923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 396520923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 396620923c1dSRichard Henderson } else { 396720923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 396820923c1dSRichard Henderson } 396920923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 397020923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 397120923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 397220923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 397320923c1dSRichard Henderson 397420923c1dSRichard Henderson tcg_temp_free(t0); 397520923c1dSRichard Henderson tcg_temp_free(t1); 397620923c1dSRichard Henderson } 397720ba8504SRichard Henderson break; 397820923c1dSRichard Henderson 397920923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 398020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 398120923c1dSRichard Henderson need_serial = true; 398220923c1dSRichard Henderson } else { 398320923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 398420923c1dSRichard Henderson } 398520923c1dSRichard Henderson break; 398620923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 398720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 398820923c1dSRichard Henderson need_serial = true; 398920923c1dSRichard Henderson } else { 399020923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 399120923c1dSRichard Henderson } 399220923c1dSRichard Henderson break; 399320923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 399420923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 399520923c1dSRichard Henderson need_serial = true; 399620923c1dSRichard Henderson } else { 399720923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 399820923c1dSRichard Henderson } 399920923c1dSRichard Henderson break; 400020923c1dSRichard Henderson 400120ba8504SRichard Henderson default: 400220ba8504SRichard Henderson /* invoke data storage error handler */ 400320ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 400420ba8504SRichard Henderson } 400520ba8504SRichard Henderson tcg_temp_free(EA); 400620923c1dSRichard Henderson 400720923c1dSRichard Henderson if (need_serial) { 400820923c1dSRichard Henderson /* Restart with exclusive lock. */ 400920923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 401020923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 401120923c1dSRichard Henderson } 4012a68a6146SBalamuruhan S } 4013a68a6146SBalamuruhan S 401420ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 401520ba8504SRichard Henderson { 401620ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 401720ba8504SRichard Henderson } 401820ba8504SRichard Henderson 401920ba8504SRichard Henderson #ifdef TARGET_PPC64 402020ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 402120ba8504SRichard Henderson { 402220ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 402320ba8504SRichard Henderson } 4024a68a6146SBalamuruhan S #endif 4025a68a6146SBalamuruhan S 402614776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 40279deb041cSRichard Henderson { 40289deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 40299deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 40309deb041cSRichard Henderson TCGv src, discard; 40319deb041cSRichard Henderson 40329deb041cSRichard Henderson gen_addr_register(ctx, EA); 40339deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 40349deb041cSRichard Henderson discard = tcg_temp_new(); 40359deb041cSRichard Henderson 40369deb041cSRichard Henderson memop |= MO_ALIGN; 40379deb041cSRichard Henderson switch (gpr_FC) { 40389deb041cSRichard Henderson case 0: /* add and Store */ 40399deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 40409deb041cSRichard Henderson break; 40419deb041cSRichard Henderson case 1: /* xor and Store */ 40429deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 40439deb041cSRichard Henderson break; 40449deb041cSRichard Henderson case 2: /* Or and Store */ 40459deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 40469deb041cSRichard Henderson break; 40479deb041cSRichard Henderson case 3: /* 'and' and Store */ 40489deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 40499deb041cSRichard Henderson break; 40509deb041cSRichard Henderson case 4: /* Store max unsigned */ 4051b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4052b8ce0f86SRichard Henderson break; 40539deb041cSRichard Henderson case 5: /* Store max signed */ 4054b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4055b8ce0f86SRichard Henderson break; 40569deb041cSRichard Henderson case 6: /* Store min unsigned */ 4057b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4058b8ce0f86SRichard Henderson break; 40599deb041cSRichard Henderson case 7: /* Store min signed */ 4060b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4061b8ce0f86SRichard Henderson break; 40629deb041cSRichard Henderson case 24: /* Store twin */ 40637fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 40647fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 40657fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 40667fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 40677fbc2b20SRichard Henderson } else { 40687fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 40697fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 40707fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 40717fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 40727fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 40737fbc2b20SRichard Henderson 40747fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 40757fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 40767fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 40777fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 40787fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 40797fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 40807fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 40817fbc2b20SRichard Henderson 40827fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 40837fbc2b20SRichard Henderson tcg_temp_free(s2); 40847fbc2b20SRichard Henderson tcg_temp_free(s); 40857fbc2b20SRichard Henderson tcg_temp_free(t2); 40867fbc2b20SRichard Henderson tcg_temp_free(t); 40877fbc2b20SRichard Henderson } 40889deb041cSRichard Henderson break; 40899deb041cSRichard Henderson default: 40909deb041cSRichard Henderson /* invoke data storage error handler */ 40919deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 40929deb041cSRichard Henderson } 40939deb041cSRichard Henderson tcg_temp_free(discard); 40949deb041cSRichard Henderson tcg_temp_free(EA); 4095a3401188SBalamuruhan S } 4096a3401188SBalamuruhan S 40979deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 40989deb041cSRichard Henderson { 40999deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 41009deb041cSRichard Henderson } 41019deb041cSRichard Henderson 41029deb041cSRichard Henderson #ifdef TARGET_PPC64 41039deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 41049deb041cSRichard Henderson { 41059deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 41069deb041cSRichard Henderson } 4107a3401188SBalamuruhan S #endif 4108a3401188SBalamuruhan S 410914776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 4110fcf5ef2aSThomas Huth { 4111253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 4112253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 4113d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 4114d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4115fcf5ef2aSThomas Huth 4116d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4117d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4118d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4119d8b86898SRichard Henderson tcg_temp_free(t0); 4120253ce7b2SNikunj A Dadhania 4121253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4122253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4123253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4124253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4125253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4126253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4127253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4128253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4129253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4130253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4131253ce7b2SNikunj A Dadhania 4132fcf5ef2aSThomas Huth gen_set_label(l1); 41334771df23SNikunj A Dadhania 4134efe843d8SDavid Gibson /* 4135efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4136efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4137efe843d8SDavid Gibson */ 41384771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4139253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4140253ce7b2SNikunj A Dadhania 4141253ce7b2SNikunj A Dadhania gen_set_label(l2); 4142fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4143fcf5ef2aSThomas Huth } 4144fcf5ef2aSThomas Huth 4145fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4146fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4147fcf5ef2aSThomas Huth { \ 4148d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4149fcf5ef2aSThomas Huth } 4150fcf5ef2aSThomas Huth 4151fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4152fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4153fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4154fcf5ef2aSThomas Huth 4155fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4156fcf5ef2aSThomas Huth /* ldarx */ 4157fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4158fcf5ef2aSThomas Huth /* stdcx. */ 4159fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4160fcf5ef2aSThomas Huth 4161fcf5ef2aSThomas Huth /* lqarx */ 4162fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4163fcf5ef2aSThomas Huth { 4164fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 416594bf2658SRichard Henderson TCGv EA, hi, lo; 4166fcf5ef2aSThomas Huth 4167fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4168fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4169fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4170fcf5ef2aSThomas Huth return; 4171fcf5ef2aSThomas Huth } 4172fcf5ef2aSThomas Huth 4173fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 417494bf2658SRichard Henderson EA = tcg_temp_new(); 4175fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 417694bf2658SRichard Henderson 417794bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 417894bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 417994bf2658SRichard Henderson hi = cpu_gpr[rd]; 418094bf2658SRichard Henderson 418194bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4182f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 418394bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 418494bf2658SRichard Henderson if (ctx->le_mode) { 418594bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 418694bf2658SRichard Henderson ctx->mem_idx)); 418794bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4188fcf5ef2aSThomas Huth } else { 418994bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 419094bf2658SRichard Henderson ctx->mem_idx)); 419194bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4192fcf5ef2aSThomas Huth } 419394bf2658SRichard Henderson tcg_temp_free_i32(oi); 419494bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4195f34ec0f6SRichard Henderson } else { 419694bf2658SRichard Henderson /* Restart with exclusive lock. */ 419794bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 419894bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 419994bf2658SRichard Henderson tcg_temp_free(EA); 420094bf2658SRichard Henderson return; 4201f34ec0f6SRichard Henderson } 420294bf2658SRichard Henderson } else if (ctx->le_mode) { 420394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4204fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4205fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 420694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 420794bf2658SRichard Henderson } else { 420894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 420994bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 421094bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 421194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 421294bf2658SRichard Henderson } 4213fcf5ef2aSThomas Huth tcg_temp_free(EA); 421494bf2658SRichard Henderson 421594bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 421694bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4217fcf5ef2aSThomas Huth } 4218fcf5ef2aSThomas Huth 4219fcf5ef2aSThomas Huth /* stqcx. */ 4220fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4221fcf5ef2aSThomas Huth { 42224a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 42234a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4224fcf5ef2aSThomas Huth 42254a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4226fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4227fcf5ef2aSThomas Huth return; 4228fcf5ef2aSThomas Huth } 42294a9b3c5dSRichard Henderson 4230fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 42314a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4232fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4233fcf5ef2aSThomas Huth 42344a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 42354a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 42364a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4237fcf5ef2aSThomas Huth 42384a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4239f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 42404a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 42414a9b3c5dSRichard Henderson if (ctx->le_mode) { 4242f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4243f34ec0f6SRichard Henderson EA, lo, hi, oi); 4244fcf5ef2aSThomas Huth } else { 4245f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4246f34ec0f6SRichard Henderson EA, lo, hi, oi); 4247fcf5ef2aSThomas Huth } 4248f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4249f34ec0f6SRichard Henderson } else { 42504a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 42514a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 42524a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4253f34ec0f6SRichard Henderson } 4254fcf5ef2aSThomas Huth tcg_temp_free(EA); 42554a9b3c5dSRichard Henderson } else { 42564a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 42574a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 42584a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 42594a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4260fcf5ef2aSThomas Huth 42614a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 42624a9b3c5dSRichard Henderson tcg_temp_free(EA); 42634a9b3c5dSRichard Henderson 42644a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 42654a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 42664a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 42674a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 42684a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 42694a9b3c5dSRichard Henderson 42704a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 42714a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 42724a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 42734a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 42744a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 42754a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 42764a9b3c5dSRichard Henderson 42774a9b3c5dSRichard Henderson /* Success */ 42784a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 42794a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 42804a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 42814a9b3c5dSRichard Henderson 42824a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 42834a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 42844a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 42854a9b3c5dSRichard Henderson 42864a9b3c5dSRichard Henderson gen_set_label(lab_fail); 42874a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 42884a9b3c5dSRichard Henderson 42894a9b3c5dSRichard Henderson gen_set_label(lab_over); 42904a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 42914a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 42924a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 42934a9b3c5dSRichard Henderson } 42944a9b3c5dSRichard Henderson } 4295fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4296fcf5ef2aSThomas Huth 4297fcf5ef2aSThomas Huth /* sync */ 4298fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4299fcf5ef2aSThomas Huth { 4300fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4301fcf5ef2aSThomas Huth 4302fcf5ef2aSThomas Huth /* 4303fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4304fcf5ef2aSThomas Huth * 4305fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4306fcf5ef2aSThomas Huth * 4307fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4308fcf5ef2aSThomas Huth * check MSR_PR as well. 4309fcf5ef2aSThomas Huth */ 4310fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4311fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4312fcf5ef2aSThomas Huth } 43134771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4314fcf5ef2aSThomas Huth } 4315fcf5ef2aSThomas Huth 4316fcf5ef2aSThomas Huth /* wait */ 4317fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4318fcf5ef2aSThomas Huth { 4319fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4320fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4321fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4322fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4323fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4324b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4325fcf5ef2aSThomas Huth } 4326fcf5ef2aSThomas Huth 4327fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4328fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4329fcf5ef2aSThomas Huth { 4330fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4331fcf5ef2aSThomas Huth GEN_PRIV; 4332fcf5ef2aSThomas Huth #else 4333fcf5ef2aSThomas Huth TCGv_i32 t; 4334fcf5ef2aSThomas Huth 4335fcf5ef2aSThomas Huth CHK_HV; 4336fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4337fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4338fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4339154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4340154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4341fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4342fcf5ef2aSThomas Huth } 4343fcf5ef2aSThomas Huth 4344fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4345fcf5ef2aSThomas Huth { 4346fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4347fcf5ef2aSThomas Huth GEN_PRIV; 4348fcf5ef2aSThomas Huth #else 4349fcf5ef2aSThomas Huth TCGv_i32 t; 4350fcf5ef2aSThomas Huth 4351fcf5ef2aSThomas Huth CHK_HV; 4352fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4353fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4354fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4355154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4356154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4357fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4358fcf5ef2aSThomas Huth } 4359fcf5ef2aSThomas Huth 4360cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4361cdee0e72SNikunj A Dadhania { 436221c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 436321c0d66aSBenjamin Herrenschmidt GEN_PRIV; 436421c0d66aSBenjamin Herrenschmidt #else 436521c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 436621c0d66aSBenjamin Herrenschmidt 436721c0d66aSBenjamin Herrenschmidt CHK_HV; 436821c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 436921c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 437021c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 437121c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 437221c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 437321c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4374cdee0e72SNikunj A Dadhania } 4375cdee0e72SNikunj A Dadhania 4376fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4377fcf5ef2aSThomas Huth { 4378fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4379fcf5ef2aSThomas Huth GEN_PRIV; 4380fcf5ef2aSThomas Huth #else 4381fcf5ef2aSThomas Huth TCGv_i32 t; 4382fcf5ef2aSThomas Huth 4383fcf5ef2aSThomas Huth CHK_HV; 4384fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4385fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4386fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4387154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4388154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4389fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4390fcf5ef2aSThomas Huth } 4391fcf5ef2aSThomas Huth 4392fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4393fcf5ef2aSThomas Huth { 4394fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4395fcf5ef2aSThomas Huth GEN_PRIV; 4396fcf5ef2aSThomas Huth #else 4397fcf5ef2aSThomas Huth TCGv_i32 t; 4398fcf5ef2aSThomas Huth 4399fcf5ef2aSThomas Huth CHK_HV; 4400fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4401fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4402fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4403154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4404154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4405fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4406fcf5ef2aSThomas Huth } 4407fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4408fcf5ef2aSThomas Huth 4409fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4410fcf5ef2aSThomas Huth { 4411fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4412efe843d8SDavid Gibson if (ctx->has_cfar) { 4413fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4414efe843d8SDavid Gibson } 4415fcf5ef2aSThomas Huth #endif 4416fcf5ef2aSThomas Huth } 4417fcf5ef2aSThomas Huth 4418fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4419fcf5ef2aSThomas Huth { 4420fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 4421fcf5ef2aSThomas Huth return false; 4422fcf5ef2aSThomas Huth } 4423fcf5ef2aSThomas Huth 4424fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 4425b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 4426fcf5ef2aSThomas Huth #else 4427fcf5ef2aSThomas Huth return true; 4428fcf5ef2aSThomas Huth #endif 4429fcf5ef2aSThomas Huth } 4430fcf5ef2aSThomas Huth 44310e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 44320e3bf489SRoman Kapl { 44330e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 44340e3bf489SRoman Kapl if (unlikely(sse)) { 44350e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 44360e3bf489SRoman Kapl gen_debug_exception(ctx); 44370e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 4438e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 44390e3bf489SRoman Kapl gen_exception(ctx, excp); 44400032dbdbSRichard Henderson } else { 44410e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 44420032dbdbSRichard Henderson } 44430e3bf489SRoman Kapl } else { 44440e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 44450e3bf489SRoman Kapl } 44460e3bf489SRoman Kapl } 44470e3bf489SRoman Kapl 4448fcf5ef2aSThomas Huth /*** Branch ***/ 4449c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4450fcf5ef2aSThomas Huth { 4451fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4452fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4453fcf5ef2aSThomas Huth } 4454fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4455fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4456fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 445707ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4458fcf5ef2aSThomas Huth } else { 4459fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 44600e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4461fcf5ef2aSThomas Huth } 4462fcf5ef2aSThomas Huth } 4463fcf5ef2aSThomas Huth 4464fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4465fcf5ef2aSThomas Huth { 4466fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4467fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4468fcf5ef2aSThomas Huth } 4469fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4470fcf5ef2aSThomas Huth } 4471fcf5ef2aSThomas Huth 4472fcf5ef2aSThomas Huth /* b ba bl bla */ 4473fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4474fcf5ef2aSThomas Huth { 4475fcf5ef2aSThomas Huth target_ulong li, target; 4476fcf5ef2aSThomas Huth 4477fcf5ef2aSThomas Huth /* sign extend LI */ 4478fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4479fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4480fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 44812c2bcb1bSRichard Henderson target = ctx->cia + li; 4482fcf5ef2aSThomas Huth } else { 4483fcf5ef2aSThomas Huth target = li; 4484fcf5ef2aSThomas Huth } 4485fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4486b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4487fcf5ef2aSThomas Huth } 44882c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4489fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 44906086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4491fcf5ef2aSThomas Huth } 4492fcf5ef2aSThomas Huth 4493fcf5ef2aSThomas Huth #define BCOND_IM 0 4494fcf5ef2aSThomas Huth #define BCOND_LR 1 4495fcf5ef2aSThomas Huth #define BCOND_CTR 2 4496fcf5ef2aSThomas Huth #define BCOND_TAR 3 4497fcf5ef2aSThomas Huth 4498c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4499fcf5ef2aSThomas Huth { 4500fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4501fcf5ef2aSThomas Huth TCGLabel *l1; 4502fcf5ef2aSThomas Huth TCGv target; 45030e3bf489SRoman Kapl 4504fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4505fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4506efe843d8SDavid Gibson if (type == BCOND_CTR) { 4507fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4508efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4509fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4510efe843d8SDavid Gibson } else { 4511fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4512efe843d8SDavid Gibson } 4513fcf5ef2aSThomas Huth } else { 4514f764718dSRichard Henderson target = NULL; 4515fcf5ef2aSThomas Huth } 4516efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4517b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4518efe843d8SDavid Gibson } 4519fcf5ef2aSThomas Huth l1 = gen_new_label(); 4520fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4521fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4522fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4523fa200c95SGreg Kurz 4524fa200c95SGreg Kurz if (type == BCOND_CTR) { 4525fa200c95SGreg Kurz /* 4526fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4527fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4528fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 452915d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 453015d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 453115d68c5eSGreg Kurz * it basically useless and thus never used in real code. 453215d68c5eSGreg Kurz * 453315d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 453415d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 453515d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 453615d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 453715d68c5eSGreg Kurz * doing anything else harmful. 4538fa200c95SGreg Kurz */ 4539d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4540fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 45419acc95cdSGreg Kurz tcg_temp_free(temp); 45429acc95cdSGreg Kurz tcg_temp_free(target); 4543fcf5ef2aSThomas Huth return; 4544fcf5ef2aSThomas Huth } 4545fa200c95SGreg Kurz 4546fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4547fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4548fa200c95SGreg Kurz } else { 4549fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4550fa200c95SGreg Kurz } 4551fa200c95SGreg Kurz if (bo & 0x2) { 4552fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4553fa200c95SGreg Kurz } else { 4554fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4555fa200c95SGreg Kurz } 4556fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4557fa200c95SGreg Kurz } else { 4558fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4559fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4560fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4561fcf5ef2aSThomas Huth } else { 4562fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4563fcf5ef2aSThomas Huth } 4564fcf5ef2aSThomas Huth if (bo & 0x2) { 4565fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4566fcf5ef2aSThomas Huth } else { 4567fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4568fcf5ef2aSThomas Huth } 4569fa200c95SGreg Kurz } 4570fcf5ef2aSThomas Huth tcg_temp_free(temp); 4571fcf5ef2aSThomas Huth } 4572fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4573fcf5ef2aSThomas Huth /* Test CR */ 4574fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4575fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4576fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4577fcf5ef2aSThomas Huth 4578fcf5ef2aSThomas Huth if (bo & 0x8) { 4579fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4580fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4581fcf5ef2aSThomas Huth } else { 4582fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4583fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4584fcf5ef2aSThomas Huth } 4585fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4586fcf5ef2aSThomas Huth } 45872c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4588fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4589fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4590fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 45912c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4592fcf5ef2aSThomas Huth } else { 4593fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4594fcf5ef2aSThomas Huth } 4595fcf5ef2aSThomas Huth } else { 4596fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4597fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4598fcf5ef2aSThomas Huth } else { 4599fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4600fcf5ef2aSThomas Huth } 46010e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4602c4a2e3a9SRichard Henderson tcg_temp_free(target); 4603c4a2e3a9SRichard Henderson } 4604fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 46050e3bf489SRoman Kapl /* fallthrough case */ 4606fcf5ef2aSThomas Huth gen_set_label(l1); 4607b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4608fcf5ef2aSThomas Huth } 46096086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4610fcf5ef2aSThomas Huth } 4611fcf5ef2aSThomas Huth 4612fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4613fcf5ef2aSThomas Huth { 4614fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4615fcf5ef2aSThomas Huth } 4616fcf5ef2aSThomas Huth 4617fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4618fcf5ef2aSThomas Huth { 4619fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4620fcf5ef2aSThomas Huth } 4621fcf5ef2aSThomas Huth 4622fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4623fcf5ef2aSThomas Huth { 4624fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4625fcf5ef2aSThomas Huth } 4626fcf5ef2aSThomas Huth 4627fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4628fcf5ef2aSThomas Huth { 4629fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4630fcf5ef2aSThomas Huth } 4631fcf5ef2aSThomas Huth 4632fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4633fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4634fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4635fcf5ef2aSThomas Huth { \ 4636fcf5ef2aSThomas Huth uint8_t bitmask; \ 4637fcf5ef2aSThomas Huth int sh; \ 4638fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4639fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4640fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4641fcf5ef2aSThomas Huth if (sh > 0) \ 4642fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4643fcf5ef2aSThomas Huth else if (sh < 0) \ 4644fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4645fcf5ef2aSThomas Huth else \ 4646fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4647fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4648fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4649fcf5ef2aSThomas Huth if (sh > 0) \ 4650fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4651fcf5ef2aSThomas Huth else if (sh < 0) \ 4652fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4653fcf5ef2aSThomas Huth else \ 4654fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4655fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4656fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4657fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4658fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4659fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4660fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4661fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4662fcf5ef2aSThomas Huth } 4663fcf5ef2aSThomas Huth 4664fcf5ef2aSThomas Huth /* crand */ 4665fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4666fcf5ef2aSThomas Huth /* crandc */ 4667fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4668fcf5ef2aSThomas Huth /* creqv */ 4669fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4670fcf5ef2aSThomas Huth /* crnand */ 4671fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4672fcf5ef2aSThomas Huth /* crnor */ 4673fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4674fcf5ef2aSThomas Huth /* cror */ 4675fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4676fcf5ef2aSThomas Huth /* crorc */ 4677fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4678fcf5ef2aSThomas Huth /* crxor */ 4679fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4680fcf5ef2aSThomas Huth 4681fcf5ef2aSThomas Huth /* mcrf */ 4682fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4683fcf5ef2aSThomas Huth { 4684fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4685fcf5ef2aSThomas Huth } 4686fcf5ef2aSThomas Huth 4687fcf5ef2aSThomas Huth /*** System linkage ***/ 4688fcf5ef2aSThomas Huth 4689fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4690fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4691fcf5ef2aSThomas Huth { 4692fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4693fcf5ef2aSThomas Huth GEN_PRIV; 4694fcf5ef2aSThomas Huth #else 4695efe843d8SDavid Gibson /* 4696efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4697fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4698fcf5ef2aSThomas Huth */ 4699d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4700fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4701fcf5ef2aSThomas Huth return; 4702fcf5ef2aSThomas Huth } 4703fcf5ef2aSThomas Huth /* Restore CPU state */ 4704fcf5ef2aSThomas Huth CHK_SV; 4705f5b6daacSRichard Henderson gen_icount_io_start(ctx); 47062c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4707fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 470859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4709fcf5ef2aSThomas Huth #endif 4710fcf5ef2aSThomas Huth } 4711fcf5ef2aSThomas Huth 4712fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4713fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4714fcf5ef2aSThomas Huth { 4715fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4716fcf5ef2aSThomas Huth GEN_PRIV; 4717fcf5ef2aSThomas Huth #else 4718fcf5ef2aSThomas Huth /* Restore CPU state */ 4719fcf5ef2aSThomas Huth CHK_SV; 4720f5b6daacSRichard Henderson gen_icount_io_start(ctx); 47212c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4722fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 472359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4724fcf5ef2aSThomas Huth #endif 4725fcf5ef2aSThomas Huth } 4726fcf5ef2aSThomas Huth 47273c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 47283c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 47293c89b8d6SNicholas Piggin { 47303c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 47313c89b8d6SNicholas Piggin GEN_PRIV; 47323c89b8d6SNicholas Piggin #else 47333c89b8d6SNicholas Piggin /* Restore CPU state */ 47343c89b8d6SNicholas Piggin CHK_SV; 4735f5b6daacSRichard Henderson gen_icount_io_start(ctx); 47362c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 47373c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 473859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 47393c89b8d6SNicholas Piggin #endif 47403c89b8d6SNicholas Piggin } 47413c89b8d6SNicholas Piggin #endif 47423c89b8d6SNicholas Piggin 4743fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4744fcf5ef2aSThomas Huth { 4745fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4746fcf5ef2aSThomas Huth GEN_PRIV; 4747fcf5ef2aSThomas Huth #else 4748fcf5ef2aSThomas Huth /* Restore CPU state */ 4749fcf5ef2aSThomas Huth CHK_HV; 4750fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 475159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4752fcf5ef2aSThomas Huth #endif 4753fcf5ef2aSThomas Huth } 4754fcf5ef2aSThomas Huth #endif 4755fcf5ef2aSThomas Huth 4756fcf5ef2aSThomas Huth /* sc */ 4757fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4758fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4759fcf5ef2aSThomas Huth #else 4760fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 47613c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4762fcf5ef2aSThomas Huth #endif 4763fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4764fcf5ef2aSThomas Huth { 4765fcf5ef2aSThomas Huth uint32_t lev; 4766fcf5ef2aSThomas Huth 4767fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4768fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4769fcf5ef2aSThomas Huth } 4770fcf5ef2aSThomas Huth 47713c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 47723c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 47733c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 47743c89b8d6SNicholas Piggin { 4775f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 47763c89b8d6SNicholas Piggin 4777f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 47782c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4779f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 47803c89b8d6SNicholas Piggin 47817a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 47823c89b8d6SNicholas Piggin } 47833c89b8d6SNicholas Piggin #endif 47843c89b8d6SNicholas Piggin #endif 47853c89b8d6SNicholas Piggin 4786fcf5ef2aSThomas Huth /*** Trap ***/ 4787fcf5ef2aSThomas Huth 4788fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4789fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4790fcf5ef2aSThomas Huth { 4791fcf5ef2aSThomas Huth /* Trap never */ 4792fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4793fcf5ef2aSThomas Huth return true; 4794fcf5ef2aSThomas Huth } 4795fcf5ef2aSThomas Huth /* Trap always */ 4796fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4797fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4798fcf5ef2aSThomas Huth return true; 4799fcf5ef2aSThomas Huth } 4800fcf5ef2aSThomas Huth return false; 4801fcf5ef2aSThomas Huth } 4802fcf5ef2aSThomas Huth 4803fcf5ef2aSThomas Huth /* tw */ 4804fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4805fcf5ef2aSThomas Huth { 4806fcf5ef2aSThomas Huth TCGv_i32 t0; 4807fcf5ef2aSThomas Huth 4808fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4809fcf5ef2aSThomas Huth return; 4810fcf5ef2aSThomas Huth } 4811fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4812fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4813fcf5ef2aSThomas Huth t0); 4814fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4815fcf5ef2aSThomas Huth } 4816fcf5ef2aSThomas Huth 4817fcf5ef2aSThomas Huth /* twi */ 4818fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4819fcf5ef2aSThomas Huth { 4820fcf5ef2aSThomas Huth TCGv t0; 4821fcf5ef2aSThomas Huth TCGv_i32 t1; 4822fcf5ef2aSThomas Huth 4823fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4824fcf5ef2aSThomas Huth return; 4825fcf5ef2aSThomas Huth } 4826fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4827fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4828fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4829fcf5ef2aSThomas Huth tcg_temp_free(t0); 4830fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4831fcf5ef2aSThomas Huth } 4832fcf5ef2aSThomas Huth 4833fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4834fcf5ef2aSThomas Huth /* td */ 4835fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4836fcf5ef2aSThomas Huth { 4837fcf5ef2aSThomas Huth TCGv_i32 t0; 4838fcf5ef2aSThomas Huth 4839fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4840fcf5ef2aSThomas Huth return; 4841fcf5ef2aSThomas Huth } 4842fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4843fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4844fcf5ef2aSThomas Huth t0); 4845fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4846fcf5ef2aSThomas Huth } 4847fcf5ef2aSThomas Huth 4848fcf5ef2aSThomas Huth /* tdi */ 4849fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4850fcf5ef2aSThomas Huth { 4851fcf5ef2aSThomas Huth TCGv t0; 4852fcf5ef2aSThomas Huth TCGv_i32 t1; 4853fcf5ef2aSThomas Huth 4854fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4855fcf5ef2aSThomas Huth return; 4856fcf5ef2aSThomas Huth } 4857fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4858fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4859fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4860fcf5ef2aSThomas Huth tcg_temp_free(t0); 4861fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4862fcf5ef2aSThomas Huth } 4863fcf5ef2aSThomas Huth #endif 4864fcf5ef2aSThomas Huth 4865fcf5ef2aSThomas Huth /*** Processor control ***/ 4866fcf5ef2aSThomas Huth 4867fcf5ef2aSThomas Huth /* mcrxr */ 4868fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4869fcf5ef2aSThomas Huth { 4870fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4871fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4872fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4873fcf5ef2aSThomas Huth 4874fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4875fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4876fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4877fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4878fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4879fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4880fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4881fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4882fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4883fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4884fcf5ef2aSThomas Huth 4885fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4886fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4887fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4888fcf5ef2aSThomas Huth } 4889fcf5ef2aSThomas Huth 4890b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4891b63d0434SNikunj A Dadhania /* mcrxrx */ 4892b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4893b63d0434SNikunj A Dadhania { 4894b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4895b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4896b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4897b63d0434SNikunj A Dadhania 4898b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4899b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4900b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4901b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4902b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4903b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4904b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4905b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4906b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4907b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4908b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4909b63d0434SNikunj A Dadhania } 4910b63d0434SNikunj A Dadhania #endif 4911b63d0434SNikunj A Dadhania 4912fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4913fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4914fcf5ef2aSThomas Huth { 4915fcf5ef2aSThomas Huth uint32_t crm, crn; 4916fcf5ef2aSThomas Huth 4917fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4918fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4919fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4920fcf5ef2aSThomas Huth crn = ctz32(crm); 4921fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4922fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4923fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4924fcf5ef2aSThomas Huth } 4925fcf5ef2aSThomas Huth } else { 4926fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4927fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4928fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4929fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4930fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4931fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4932fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4933fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4934fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4935fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4936fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4937fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4938fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4939fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4940fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4941fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4942fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4943fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4944fcf5ef2aSThomas Huth } 4945fcf5ef2aSThomas Huth } 4946fcf5ef2aSThomas Huth 4947fcf5ef2aSThomas Huth /* mfmsr */ 4948fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4949fcf5ef2aSThomas Huth { 4950fcf5ef2aSThomas Huth CHK_SV; 4951fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4952fcf5ef2aSThomas Huth } 4953fcf5ef2aSThomas Huth 4954fcf5ef2aSThomas Huth /* mfspr */ 4955fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4956fcf5ef2aSThomas Huth { 4957fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4958fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4959fcf5ef2aSThomas Huth 4960fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4961fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4962fcf5ef2aSThomas Huth #else 4963fcf5ef2aSThomas Huth if (ctx->pr) { 4964fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4965fcf5ef2aSThomas Huth } else if (ctx->hv) { 4966fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4967fcf5ef2aSThomas Huth } else { 4968fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4969fcf5ef2aSThomas Huth } 4970fcf5ef2aSThomas Huth #endif 4971fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4972fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4973fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4974fcf5ef2aSThomas Huth } else { 4975fcf5ef2aSThomas Huth /* Privilege exception */ 4976efe843d8SDavid Gibson /* 4977efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4978fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4979fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4980fcf5ef2aSThomas Huth */ 4981fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 498231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 498331085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 49842c2bcb1bSRichard Henderson ctx->cia); 4985fcf5ef2aSThomas Huth } 4986fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4987fcf5ef2aSThomas Huth } 4988fcf5ef2aSThomas Huth } else { 4989fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4990fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4991fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4992fcf5ef2aSThomas Huth /* This is a nop */ 4993fcf5ef2aSThomas Huth return; 4994fcf5ef2aSThomas Huth } 4995fcf5ef2aSThomas Huth /* Not defined */ 499631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 499731085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 49982c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4999fcf5ef2aSThomas Huth 5000efe843d8SDavid Gibson /* 5001efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5002efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5003fcf5ef2aSThomas Huth */ 5004fcf5ef2aSThomas Huth if (sprn & 0x10) { 5005fcf5ef2aSThomas Huth if (ctx->pr) { 5006fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5007fcf5ef2aSThomas Huth } 5008fcf5ef2aSThomas Huth } else { 5009fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 5010fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5011fcf5ef2aSThomas Huth } 5012fcf5ef2aSThomas Huth } 5013fcf5ef2aSThomas Huth } 5014fcf5ef2aSThomas Huth } 5015fcf5ef2aSThomas Huth 5016fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 5017fcf5ef2aSThomas Huth { 5018fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5019fcf5ef2aSThomas Huth } 5020fcf5ef2aSThomas Huth 5021fcf5ef2aSThomas Huth /* mftb */ 5022fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 5023fcf5ef2aSThomas Huth { 5024fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5025fcf5ef2aSThomas Huth } 5026fcf5ef2aSThomas Huth 5027fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 5028fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 5029fcf5ef2aSThomas Huth { 5030fcf5ef2aSThomas Huth uint32_t crm, crn; 5031fcf5ef2aSThomas Huth 5032fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5033fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 5034fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 5035fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5036fcf5ef2aSThomas Huth crn = ctz32(crm); 5037fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5038fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 5039fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 5040fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5041fcf5ef2aSThomas Huth } 5042fcf5ef2aSThomas Huth } else { 5043fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5044fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5045fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 5046fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 5047fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 5048fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 5049fcf5ef2aSThomas Huth } 5050fcf5ef2aSThomas Huth } 5051fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5052fcf5ef2aSThomas Huth } 5053fcf5ef2aSThomas Huth } 5054fcf5ef2aSThomas Huth 5055fcf5ef2aSThomas Huth /* mtmsr */ 5056fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5057fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 5058fcf5ef2aSThomas Huth { 5059fcf5ef2aSThomas Huth CHK_SV; 5060fcf5ef2aSThomas Huth 5061fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 5062f5b6daacSRichard Henderson gen_icount_io_start(ctx); 5063fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 50645ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5065fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 50665ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5067efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5068efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 50695ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5070efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 50715ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 50725ed19506SNicholas Piggin 50735ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5074fcf5ef2aSThomas Huth tcg_temp_free(t0); 50755ed19506SNicholas Piggin tcg_temp_free(t1); 50765ed19506SNicholas Piggin 5077fcf5ef2aSThomas Huth } else { 5078efe843d8SDavid Gibson /* 5079efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5080efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5081efe843d8SDavid Gibson * ppc_store_msr 5082fcf5ef2aSThomas Huth */ 5083b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5084fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 5085fcf5ef2aSThomas Huth } 50865ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5087d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5088fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 5089fcf5ef2aSThomas Huth } 5090fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5091fcf5ef2aSThomas Huth 5092fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 5093fcf5ef2aSThomas Huth { 5094fcf5ef2aSThomas Huth CHK_SV; 5095fcf5ef2aSThomas Huth 5096fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 5097f5b6daacSRichard Henderson gen_icount_io_start(ctx); 5098fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 50995ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5100fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 51015ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5102efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5103efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 51045ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5105efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 51065ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 51075ed19506SNicholas Piggin 51085ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5109fcf5ef2aSThomas Huth tcg_temp_free(t0); 51105ed19506SNicholas Piggin tcg_temp_free(t1); 51115ed19506SNicholas Piggin 5112fcf5ef2aSThomas Huth } else { 5113fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 5114fcf5ef2aSThomas Huth 5115efe843d8SDavid Gibson /* 5116efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5117efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5118efe843d8SDavid Gibson * ppc_store_msr 5119fcf5ef2aSThomas Huth */ 5120b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5121fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5122fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 5123fcf5ef2aSThomas Huth #else 5124fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 5125fcf5ef2aSThomas Huth #endif 5126fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 5127fcf5ef2aSThomas Huth tcg_temp_free(msr); 5128fcf5ef2aSThomas Huth } 51295ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5130d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5131fcf5ef2aSThomas Huth #endif 5132fcf5ef2aSThomas Huth } 5133fcf5ef2aSThomas Huth 5134fcf5ef2aSThomas Huth /* mtspr */ 5135fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5136fcf5ef2aSThomas Huth { 5137fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5138fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5139fcf5ef2aSThomas Huth 5140fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5141fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5142fcf5ef2aSThomas Huth #else 5143fcf5ef2aSThomas Huth if (ctx->pr) { 5144fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5145fcf5ef2aSThomas Huth } else if (ctx->hv) { 5146fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5147fcf5ef2aSThomas Huth } else { 5148fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5149fcf5ef2aSThomas Huth } 5150fcf5ef2aSThomas Huth #endif 5151fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5152fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5153fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5154fcf5ef2aSThomas Huth } else { 5155fcf5ef2aSThomas Huth /* Privilege exception */ 515631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 515731085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 51582c2bcb1bSRichard Henderson ctx->cia); 5159fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5160fcf5ef2aSThomas Huth } 5161fcf5ef2aSThomas Huth } else { 5162fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5163fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5164fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5165fcf5ef2aSThomas Huth /* This is a nop */ 5166fcf5ef2aSThomas Huth return; 5167fcf5ef2aSThomas Huth } 5168fcf5ef2aSThomas Huth 5169fcf5ef2aSThomas Huth /* Not defined */ 517031085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 517131085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 51722c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5173fcf5ef2aSThomas Huth 5174fcf5ef2aSThomas Huth 5175efe843d8SDavid Gibson /* 5176efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5177efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5178fcf5ef2aSThomas Huth */ 5179fcf5ef2aSThomas Huth if (sprn & 0x10) { 5180fcf5ef2aSThomas Huth if (ctx->pr) { 5181fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5182fcf5ef2aSThomas Huth } 5183fcf5ef2aSThomas Huth } else { 5184fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5185fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5186fcf5ef2aSThomas Huth } 5187fcf5ef2aSThomas Huth } 5188fcf5ef2aSThomas Huth } 5189fcf5ef2aSThomas Huth } 5190fcf5ef2aSThomas Huth 5191fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5192fcf5ef2aSThomas Huth /* setb */ 5193fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5194fcf5ef2aSThomas Huth { 5195fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5196fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 5197fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 5198fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5199fcf5ef2aSThomas Huth 5200fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5201fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 5202fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 5203fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5204fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5205fcf5ef2aSThomas Huth 5206fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5207fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 5208fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 5209fcf5ef2aSThomas Huth } 5210fcf5ef2aSThomas Huth #endif 5211fcf5ef2aSThomas Huth 5212fcf5ef2aSThomas Huth /*** Cache management ***/ 5213fcf5ef2aSThomas Huth 5214fcf5ef2aSThomas Huth /* dcbf */ 5215fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5216fcf5ef2aSThomas Huth { 5217fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5218fcf5ef2aSThomas Huth TCGv t0; 5219fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5220fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5221fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5222fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5223fcf5ef2aSThomas Huth tcg_temp_free(t0); 5224fcf5ef2aSThomas Huth } 5225fcf5ef2aSThomas Huth 522650728199SRoman Kapl /* dcbfep (external PID dcbf) */ 522750728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 522850728199SRoman Kapl { 522950728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 523050728199SRoman Kapl TCGv t0; 523150728199SRoman Kapl CHK_SV; 523250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 523350728199SRoman Kapl t0 = tcg_temp_new(); 523450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 523550728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 523650728199SRoman Kapl tcg_temp_free(t0); 523750728199SRoman Kapl } 523850728199SRoman Kapl 5239fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5240fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5241fcf5ef2aSThomas Huth { 5242fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5243fcf5ef2aSThomas Huth GEN_PRIV; 5244fcf5ef2aSThomas Huth #else 5245fcf5ef2aSThomas Huth TCGv EA, val; 5246fcf5ef2aSThomas Huth 5247fcf5ef2aSThomas Huth CHK_SV; 5248fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5249fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5250fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5251fcf5ef2aSThomas Huth val = tcg_temp_new(); 5252fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5253fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5254fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5255fcf5ef2aSThomas Huth tcg_temp_free(val); 5256fcf5ef2aSThomas Huth tcg_temp_free(EA); 5257fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5258fcf5ef2aSThomas Huth } 5259fcf5ef2aSThomas Huth 5260fcf5ef2aSThomas Huth /* dcdst */ 5261fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5262fcf5ef2aSThomas Huth { 5263fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5264fcf5ef2aSThomas Huth TCGv t0; 5265fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5266fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5267fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5268fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5269fcf5ef2aSThomas Huth tcg_temp_free(t0); 5270fcf5ef2aSThomas Huth } 5271fcf5ef2aSThomas Huth 527250728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 527350728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 527450728199SRoman Kapl { 527550728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 527650728199SRoman Kapl TCGv t0; 527750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 527850728199SRoman Kapl t0 = tcg_temp_new(); 527950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 528050728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 528150728199SRoman Kapl tcg_temp_free(t0); 528250728199SRoman Kapl } 528350728199SRoman Kapl 5284fcf5ef2aSThomas Huth /* dcbt */ 5285fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5286fcf5ef2aSThomas Huth { 5287efe843d8SDavid Gibson /* 5288efe843d8SDavid Gibson * interpreted as no-op 5289efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5290efe843d8SDavid Gibson * does not generate any exception 5291fcf5ef2aSThomas Huth */ 5292fcf5ef2aSThomas Huth } 5293fcf5ef2aSThomas Huth 529450728199SRoman Kapl /* dcbtep */ 529550728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 529650728199SRoman Kapl { 5297efe843d8SDavid Gibson /* 5298efe843d8SDavid Gibson * interpreted as no-op 5299efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5300efe843d8SDavid Gibson * does not generate any exception 530150728199SRoman Kapl */ 530250728199SRoman Kapl } 530350728199SRoman Kapl 5304fcf5ef2aSThomas Huth /* dcbtst */ 5305fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5306fcf5ef2aSThomas Huth { 5307efe843d8SDavid Gibson /* 5308efe843d8SDavid Gibson * interpreted as no-op 5309efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5310efe843d8SDavid Gibson * does not generate any exception 5311fcf5ef2aSThomas Huth */ 5312fcf5ef2aSThomas Huth } 5313fcf5ef2aSThomas Huth 531450728199SRoman Kapl /* dcbtstep */ 531550728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 531650728199SRoman Kapl { 5317efe843d8SDavid Gibson /* 5318efe843d8SDavid Gibson * interpreted as no-op 5319efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5320efe843d8SDavid Gibson * does not generate any exception 532150728199SRoman Kapl */ 532250728199SRoman Kapl } 532350728199SRoman Kapl 5324fcf5ef2aSThomas Huth /* dcbtls */ 5325fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5326fcf5ef2aSThomas Huth { 5327fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5328fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5329fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5330fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5331fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5332fcf5ef2aSThomas Huth tcg_temp_free(t0); 5333fcf5ef2aSThomas Huth } 5334fcf5ef2aSThomas Huth 5335fcf5ef2aSThomas Huth /* dcbz */ 5336fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5337fcf5ef2aSThomas Huth { 5338fcf5ef2aSThomas Huth TCGv tcgv_addr; 5339fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5340fcf5ef2aSThomas Huth 5341fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5342fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5343fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5344fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5345fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5346fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5347fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5348fcf5ef2aSThomas Huth } 5349fcf5ef2aSThomas Huth 535050728199SRoman Kapl /* dcbzep */ 535150728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 535250728199SRoman Kapl { 535350728199SRoman Kapl TCGv tcgv_addr; 535450728199SRoman Kapl TCGv_i32 tcgv_op; 535550728199SRoman Kapl 535650728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 535750728199SRoman Kapl tcgv_addr = tcg_temp_new(); 535850728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 535950728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 536050728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 536150728199SRoman Kapl tcg_temp_free(tcgv_addr); 536250728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 536350728199SRoman Kapl } 536450728199SRoman Kapl 5365fcf5ef2aSThomas Huth /* dst / dstt */ 5366fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5367fcf5ef2aSThomas Huth { 5368fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5369fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5370fcf5ef2aSThomas Huth } else { 5371fcf5ef2aSThomas Huth /* interpreted as no-op */ 5372fcf5ef2aSThomas Huth } 5373fcf5ef2aSThomas Huth } 5374fcf5ef2aSThomas Huth 5375fcf5ef2aSThomas Huth /* dstst /dststt */ 5376fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5377fcf5ef2aSThomas Huth { 5378fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5379fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5380fcf5ef2aSThomas Huth } else { 5381fcf5ef2aSThomas Huth /* interpreted as no-op */ 5382fcf5ef2aSThomas Huth } 5383fcf5ef2aSThomas Huth 5384fcf5ef2aSThomas Huth } 5385fcf5ef2aSThomas Huth 5386fcf5ef2aSThomas Huth /* dss / dssall */ 5387fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5388fcf5ef2aSThomas Huth { 5389fcf5ef2aSThomas Huth /* interpreted as no-op */ 5390fcf5ef2aSThomas Huth } 5391fcf5ef2aSThomas Huth 5392fcf5ef2aSThomas Huth /* icbi */ 5393fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5394fcf5ef2aSThomas Huth { 5395fcf5ef2aSThomas Huth TCGv t0; 5396fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5397fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5398fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5399fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5400fcf5ef2aSThomas Huth tcg_temp_free(t0); 5401fcf5ef2aSThomas Huth } 5402fcf5ef2aSThomas Huth 540350728199SRoman Kapl /* icbiep */ 540450728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 540550728199SRoman Kapl { 540650728199SRoman Kapl TCGv t0; 540750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 540850728199SRoman Kapl t0 = tcg_temp_new(); 540950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 541050728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 541150728199SRoman Kapl tcg_temp_free(t0); 541250728199SRoman Kapl } 541350728199SRoman Kapl 5414fcf5ef2aSThomas Huth /* Optional: */ 5415fcf5ef2aSThomas Huth /* dcba */ 5416fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5417fcf5ef2aSThomas Huth { 5418efe843d8SDavid Gibson /* 5419efe843d8SDavid Gibson * interpreted as no-op 5420efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5421fcf5ef2aSThomas Huth * but does not generate any exception 5422fcf5ef2aSThomas Huth */ 5423fcf5ef2aSThomas Huth } 5424fcf5ef2aSThomas Huth 5425fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5426fcf5ef2aSThomas Huth /* Supervisor only: */ 5427fcf5ef2aSThomas Huth 5428fcf5ef2aSThomas Huth /* mfsr */ 5429fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5430fcf5ef2aSThomas Huth { 5431fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5432fcf5ef2aSThomas Huth GEN_PRIV; 5433fcf5ef2aSThomas Huth #else 5434fcf5ef2aSThomas Huth TCGv t0; 5435fcf5ef2aSThomas Huth 5436fcf5ef2aSThomas Huth CHK_SV; 5437fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5438fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5439fcf5ef2aSThomas Huth tcg_temp_free(t0); 5440fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5441fcf5ef2aSThomas Huth } 5442fcf5ef2aSThomas Huth 5443fcf5ef2aSThomas Huth /* mfsrin */ 5444fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5445fcf5ef2aSThomas Huth { 5446fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5447fcf5ef2aSThomas Huth GEN_PRIV; 5448fcf5ef2aSThomas Huth #else 5449fcf5ef2aSThomas Huth TCGv t0; 5450fcf5ef2aSThomas Huth 5451fcf5ef2aSThomas Huth CHK_SV; 5452fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5453e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5454fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5455fcf5ef2aSThomas Huth tcg_temp_free(t0); 5456fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5457fcf5ef2aSThomas Huth } 5458fcf5ef2aSThomas Huth 5459fcf5ef2aSThomas Huth /* mtsr */ 5460fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5461fcf5ef2aSThomas Huth { 5462fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5463fcf5ef2aSThomas Huth GEN_PRIV; 5464fcf5ef2aSThomas Huth #else 5465fcf5ef2aSThomas Huth TCGv t0; 5466fcf5ef2aSThomas Huth 5467fcf5ef2aSThomas Huth CHK_SV; 5468fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5469fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5470fcf5ef2aSThomas Huth tcg_temp_free(t0); 5471fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5472fcf5ef2aSThomas Huth } 5473fcf5ef2aSThomas Huth 5474fcf5ef2aSThomas Huth /* mtsrin */ 5475fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5476fcf5ef2aSThomas Huth { 5477fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5478fcf5ef2aSThomas Huth GEN_PRIV; 5479fcf5ef2aSThomas Huth #else 5480fcf5ef2aSThomas Huth TCGv t0; 5481fcf5ef2aSThomas Huth CHK_SV; 5482fcf5ef2aSThomas Huth 5483fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5484e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5485fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5486fcf5ef2aSThomas Huth tcg_temp_free(t0); 5487fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5488fcf5ef2aSThomas Huth } 5489fcf5ef2aSThomas Huth 5490fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5491fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5492fcf5ef2aSThomas Huth 5493fcf5ef2aSThomas Huth /* mfsr */ 5494fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5495fcf5ef2aSThomas Huth { 5496fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5497fcf5ef2aSThomas Huth GEN_PRIV; 5498fcf5ef2aSThomas Huth #else 5499fcf5ef2aSThomas Huth TCGv t0; 5500fcf5ef2aSThomas Huth 5501fcf5ef2aSThomas Huth CHK_SV; 5502fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5503fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5504fcf5ef2aSThomas Huth tcg_temp_free(t0); 5505fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5506fcf5ef2aSThomas Huth } 5507fcf5ef2aSThomas Huth 5508fcf5ef2aSThomas Huth /* mfsrin */ 5509fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5510fcf5ef2aSThomas Huth { 5511fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5512fcf5ef2aSThomas Huth GEN_PRIV; 5513fcf5ef2aSThomas Huth #else 5514fcf5ef2aSThomas Huth TCGv t0; 5515fcf5ef2aSThomas Huth 5516fcf5ef2aSThomas Huth CHK_SV; 5517fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5518e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5519fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5520fcf5ef2aSThomas Huth tcg_temp_free(t0); 5521fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5522fcf5ef2aSThomas Huth } 5523fcf5ef2aSThomas Huth 5524fcf5ef2aSThomas Huth /* mtsr */ 5525fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5526fcf5ef2aSThomas Huth { 5527fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5528fcf5ef2aSThomas Huth GEN_PRIV; 5529fcf5ef2aSThomas Huth #else 5530fcf5ef2aSThomas Huth TCGv t0; 5531fcf5ef2aSThomas Huth 5532fcf5ef2aSThomas Huth CHK_SV; 5533fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5534fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5535fcf5ef2aSThomas Huth tcg_temp_free(t0); 5536fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5537fcf5ef2aSThomas Huth } 5538fcf5ef2aSThomas Huth 5539fcf5ef2aSThomas Huth /* mtsrin */ 5540fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5541fcf5ef2aSThomas Huth { 5542fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5543fcf5ef2aSThomas Huth GEN_PRIV; 5544fcf5ef2aSThomas Huth #else 5545fcf5ef2aSThomas Huth TCGv t0; 5546fcf5ef2aSThomas Huth 5547fcf5ef2aSThomas Huth CHK_SV; 5548fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5549e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5550fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5551fcf5ef2aSThomas Huth tcg_temp_free(t0); 5552fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5553fcf5ef2aSThomas Huth } 5554fcf5ef2aSThomas Huth 5555fcf5ef2aSThomas Huth /* slbmte */ 5556fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5557fcf5ef2aSThomas Huth { 5558fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5559fcf5ef2aSThomas Huth GEN_PRIV; 5560fcf5ef2aSThomas Huth #else 5561fcf5ef2aSThomas Huth CHK_SV; 5562fcf5ef2aSThomas Huth 5563fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5564fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5565fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5566fcf5ef2aSThomas Huth } 5567fcf5ef2aSThomas Huth 5568fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5569fcf5ef2aSThomas Huth { 5570fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5571fcf5ef2aSThomas Huth GEN_PRIV; 5572fcf5ef2aSThomas Huth #else 5573fcf5ef2aSThomas Huth CHK_SV; 5574fcf5ef2aSThomas Huth 5575fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5576fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5577fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5578fcf5ef2aSThomas Huth } 5579fcf5ef2aSThomas Huth 5580fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5581fcf5ef2aSThomas Huth { 5582fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5583fcf5ef2aSThomas Huth GEN_PRIV; 5584fcf5ef2aSThomas Huth #else 5585fcf5ef2aSThomas Huth CHK_SV; 5586fcf5ef2aSThomas Huth 5587fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5588fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5589fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5590fcf5ef2aSThomas Huth } 5591fcf5ef2aSThomas Huth 5592fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5593fcf5ef2aSThomas Huth { 5594fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5595fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5596fcf5ef2aSThomas Huth #else 5597fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5598fcf5ef2aSThomas Huth 5599fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5600fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5601fcf5ef2aSThomas Huth return; 5602fcf5ef2aSThomas Huth } 5603fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5604fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5605fcf5ef2aSThomas Huth l1 = gen_new_label(); 5606fcf5ef2aSThomas Huth l2 = gen_new_label(); 5607fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5608fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5609efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5610fcf5ef2aSThomas Huth tcg_gen_br(l2); 5611fcf5ef2aSThomas Huth gen_set_label(l1); 5612fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5613fcf5ef2aSThomas Huth gen_set_label(l2); 5614fcf5ef2aSThomas Huth #endif 5615fcf5ef2aSThomas Huth } 5616fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5617fcf5ef2aSThomas Huth 5618fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5619fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5620fcf5ef2aSThomas Huth 5621fcf5ef2aSThomas Huth /* tlbia */ 5622fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5623fcf5ef2aSThomas Huth { 5624fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5625fcf5ef2aSThomas Huth GEN_PRIV; 5626fcf5ef2aSThomas Huth #else 5627fcf5ef2aSThomas Huth CHK_HV; 5628fcf5ef2aSThomas Huth 5629fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5630fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5631fcf5ef2aSThomas Huth } 5632fcf5ef2aSThomas Huth 5633fcf5ef2aSThomas Huth /* tlbiel */ 5634fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5635fcf5ef2aSThomas Huth { 5636fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5637fcf5ef2aSThomas Huth GEN_PRIV; 5638fcf5ef2aSThomas Huth #else 5639fcf5ef2aSThomas Huth CHK_SV; 5640fcf5ef2aSThomas Huth 5641fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5642fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5643fcf5ef2aSThomas Huth } 5644fcf5ef2aSThomas Huth 5645fcf5ef2aSThomas Huth /* tlbie */ 5646fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5647fcf5ef2aSThomas Huth { 5648fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5649fcf5ef2aSThomas Huth GEN_PRIV; 5650fcf5ef2aSThomas Huth #else 5651fcf5ef2aSThomas Huth TCGv_i32 t1; 5652c6fd28fdSSuraj Jitindar Singh 5653c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 565491c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 5655c6fd28fdSSuraj Jitindar Singh } else { 5656c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 5657c6fd28fdSSuraj Jitindar Singh } 5658fcf5ef2aSThomas Huth 5659fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5660fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5661fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5662fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5663fcf5ef2aSThomas Huth tcg_temp_free(t0); 5664fcf5ef2aSThomas Huth } else { 5665fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5666fcf5ef2aSThomas Huth } 5667fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 5668fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5669fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5670fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5671fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5672fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5673fcf5ef2aSThomas Huth } 5674fcf5ef2aSThomas Huth 5675fcf5ef2aSThomas Huth /* tlbsync */ 5676fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5677fcf5ef2aSThomas Huth { 5678fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5679fcf5ef2aSThomas Huth GEN_PRIV; 5680fcf5ef2aSThomas Huth #else 568191c60f12SCédric Le Goater 568291c60f12SCédric Le Goater if (ctx->gtse) { 568391c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 568491c60f12SCédric Le Goater } else { 568591c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 568691c60f12SCédric Le Goater } 5687fcf5ef2aSThomas Huth 5688fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5689fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5690fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5691fcf5ef2aSThomas Huth } 5692fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5693fcf5ef2aSThomas Huth } 5694fcf5ef2aSThomas Huth 5695fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5696fcf5ef2aSThomas Huth /* slbia */ 5697fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5698fcf5ef2aSThomas Huth { 5699fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5700fcf5ef2aSThomas Huth GEN_PRIV; 5701fcf5ef2aSThomas Huth #else 57020418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 57030418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 57040418bf78SNicholas Piggin 5705fcf5ef2aSThomas Huth CHK_SV; 5706fcf5ef2aSThomas Huth 57070418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 57083119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 5709fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5710fcf5ef2aSThomas Huth } 5711fcf5ef2aSThomas Huth 5712fcf5ef2aSThomas Huth /* slbie */ 5713fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5714fcf5ef2aSThomas Huth { 5715fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5716fcf5ef2aSThomas Huth GEN_PRIV; 5717fcf5ef2aSThomas Huth #else 5718fcf5ef2aSThomas Huth CHK_SV; 5719fcf5ef2aSThomas Huth 5720fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5721fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5722fcf5ef2aSThomas Huth } 5723a63f1dfcSNikunj A Dadhania 5724a63f1dfcSNikunj A Dadhania /* slbieg */ 5725a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5726a63f1dfcSNikunj A Dadhania { 5727a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5728a63f1dfcSNikunj A Dadhania GEN_PRIV; 5729a63f1dfcSNikunj A Dadhania #else 5730a63f1dfcSNikunj A Dadhania CHK_SV; 5731a63f1dfcSNikunj A Dadhania 5732a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5733a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5734a63f1dfcSNikunj A Dadhania } 5735a63f1dfcSNikunj A Dadhania 573662d897caSNikunj A Dadhania /* slbsync */ 573762d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 573862d897caSNikunj A Dadhania { 573962d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 574062d897caSNikunj A Dadhania GEN_PRIV; 574162d897caSNikunj A Dadhania #else 574262d897caSNikunj A Dadhania CHK_SV; 574362d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 574462d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 574562d897caSNikunj A Dadhania } 574662d897caSNikunj A Dadhania 5747fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5748fcf5ef2aSThomas Huth 5749fcf5ef2aSThomas Huth /*** External control ***/ 5750fcf5ef2aSThomas Huth /* Optional: */ 5751fcf5ef2aSThomas Huth 5752fcf5ef2aSThomas Huth /* eciwx */ 5753fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5754fcf5ef2aSThomas Huth { 5755fcf5ef2aSThomas Huth TCGv t0; 5756fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5757fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5758fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5759fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5760c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5761c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5762fcf5ef2aSThomas Huth tcg_temp_free(t0); 5763fcf5ef2aSThomas Huth } 5764fcf5ef2aSThomas Huth 5765fcf5ef2aSThomas Huth /* ecowx */ 5766fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5767fcf5ef2aSThomas Huth { 5768fcf5ef2aSThomas Huth TCGv t0; 5769fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5770fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5771fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5772fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5773c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5774c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5775fcf5ef2aSThomas Huth tcg_temp_free(t0); 5776fcf5ef2aSThomas Huth } 5777fcf5ef2aSThomas Huth 5778fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5779fcf5ef2aSThomas Huth 5780fcf5ef2aSThomas Huth /* abs - abs. */ 5781fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5782fcf5ef2aSThomas Huth { 5783fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5784fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5785fe21b785SRichard Henderson 5786fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5787efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5788fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5789fcf5ef2aSThomas Huth } 5790efe843d8SDavid Gibson } 5791fcf5ef2aSThomas Huth 5792fcf5ef2aSThomas Huth /* abso - abso. */ 5793fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5794fcf5ef2aSThomas Huth { 5795fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5796fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5797fe21b785SRichard Henderson 5798fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5799fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5800fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5801efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5802fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5803fcf5ef2aSThomas Huth } 5804efe843d8SDavid Gibson } 5805fcf5ef2aSThomas Huth 5806fcf5ef2aSThomas Huth /* clcs */ 5807fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5808fcf5ef2aSThomas Huth { 5809fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5810fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5811fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5812fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5813fcf5ef2aSThomas Huth } 5814fcf5ef2aSThomas Huth 5815fcf5ef2aSThomas Huth /* div - div. */ 5816fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5817fcf5ef2aSThomas Huth { 5818fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5819fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5820efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5821fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5822fcf5ef2aSThomas Huth } 5823efe843d8SDavid Gibson } 5824fcf5ef2aSThomas Huth 5825fcf5ef2aSThomas Huth /* divo - divo. */ 5826fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5827fcf5ef2aSThomas Huth { 5828fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5829fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5830efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5831fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5832fcf5ef2aSThomas Huth } 5833efe843d8SDavid Gibson } 5834fcf5ef2aSThomas Huth 5835fcf5ef2aSThomas Huth /* divs - divs. */ 5836fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5837fcf5ef2aSThomas Huth { 5838fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5839fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5840efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5841fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5842fcf5ef2aSThomas Huth } 5843efe843d8SDavid Gibson } 5844fcf5ef2aSThomas Huth 5845fcf5ef2aSThomas Huth /* divso - divso. */ 5846fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5847fcf5ef2aSThomas Huth { 5848fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5849fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5850efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5851fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5852fcf5ef2aSThomas Huth } 5853efe843d8SDavid Gibson } 5854fcf5ef2aSThomas Huth 5855fcf5ef2aSThomas Huth /* doz - doz. */ 5856fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5857fcf5ef2aSThomas Huth { 5858fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5859fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5860efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5861efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5862efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5863efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 5864fcf5ef2aSThomas Huth tcg_gen_br(l2); 5865fcf5ef2aSThomas Huth gen_set_label(l1); 5866fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5867fcf5ef2aSThomas Huth gen_set_label(l2); 5868efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5869fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5870fcf5ef2aSThomas Huth } 5871efe843d8SDavid Gibson } 5872fcf5ef2aSThomas Huth 5873fcf5ef2aSThomas Huth /* dozo - dozo. */ 5874fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5875fcf5ef2aSThomas Huth { 5876fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5877fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5878fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5879fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5880fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5881fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5882fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5883efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5884efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5885fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5886fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5887fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5888fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5889fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5890fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5891fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5892fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5893fcf5ef2aSThomas Huth tcg_gen_br(l2); 5894fcf5ef2aSThomas Huth gen_set_label(l1); 5895fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5896fcf5ef2aSThomas Huth gen_set_label(l2); 5897fcf5ef2aSThomas Huth tcg_temp_free(t0); 5898fcf5ef2aSThomas Huth tcg_temp_free(t1); 5899fcf5ef2aSThomas Huth tcg_temp_free(t2); 5900efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5901fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5902fcf5ef2aSThomas Huth } 5903efe843d8SDavid Gibson } 5904fcf5ef2aSThomas Huth 5905fcf5ef2aSThomas Huth /* dozi */ 5906fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5907fcf5ef2aSThomas Huth { 5908fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5909fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5910fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5911fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5912fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5913fcf5ef2aSThomas Huth tcg_gen_br(l2); 5914fcf5ef2aSThomas Huth gen_set_label(l1); 5915fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5916fcf5ef2aSThomas Huth gen_set_label(l2); 5917efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5918fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5919fcf5ef2aSThomas Huth } 5920efe843d8SDavid Gibson } 5921fcf5ef2aSThomas Huth 5922fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5923fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5924fcf5ef2aSThomas Huth { 5925fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5926fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5927fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5928fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5929fcf5ef2aSThomas Huth 5930fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5931fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5932fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5933fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5934fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5935fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5936fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5937efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5938fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5939efe843d8SDavid Gibson } 5940fcf5ef2aSThomas Huth tcg_temp_free(t0); 5941fcf5ef2aSThomas Huth } 5942fcf5ef2aSThomas Huth 5943fcf5ef2aSThomas Huth /* maskg - maskg. */ 5944fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5945fcf5ef2aSThomas Huth { 5946fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5947fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5948fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5949fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5950fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5951fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5952fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5953fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5954fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5955fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5956fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5957fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5958fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5959fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5960fcf5ef2aSThomas Huth gen_set_label(l1); 5961fcf5ef2aSThomas Huth tcg_temp_free(t0); 5962fcf5ef2aSThomas Huth tcg_temp_free(t1); 5963fcf5ef2aSThomas Huth tcg_temp_free(t2); 5964fcf5ef2aSThomas Huth tcg_temp_free(t3); 5965efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5966fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5967fcf5ef2aSThomas Huth } 5968efe843d8SDavid Gibson } 5969fcf5ef2aSThomas Huth 5970fcf5ef2aSThomas Huth /* maskir - maskir. */ 5971fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5972fcf5ef2aSThomas Huth { 5973fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5974fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5975fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5976fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5977fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5978fcf5ef2aSThomas Huth tcg_temp_free(t0); 5979fcf5ef2aSThomas Huth tcg_temp_free(t1); 5980efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5981fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5982fcf5ef2aSThomas Huth } 5983efe843d8SDavid Gibson } 5984fcf5ef2aSThomas Huth 5985fcf5ef2aSThomas Huth /* mul - mul. */ 5986fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5987fcf5ef2aSThomas Huth { 5988fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5989fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5990fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5991fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5992fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5993fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5994fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5995fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5996fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5997fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5998fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5999fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6000fcf5ef2aSThomas Huth tcg_temp_free(t2); 6001efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6002fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6003fcf5ef2aSThomas Huth } 6004efe843d8SDavid Gibson } 6005fcf5ef2aSThomas Huth 6006fcf5ef2aSThomas Huth /* mulo - mulo. */ 6007fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 6008fcf5ef2aSThomas Huth { 6009fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6010fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6011fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6012fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6013fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6014fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6015fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6016fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6017fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6018fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6019fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6020fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6021fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6022fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 6023fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 6024fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6025fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6026fcf5ef2aSThomas Huth gen_set_label(l1); 6027fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6028fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6029fcf5ef2aSThomas Huth tcg_temp_free(t2); 6030efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6031fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6032fcf5ef2aSThomas Huth } 6033efe843d8SDavid Gibson } 6034fcf5ef2aSThomas Huth 6035fcf5ef2aSThomas Huth /* nabs - nabs. */ 6036fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 6037fcf5ef2aSThomas Huth { 6038fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6039fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6040fe21b785SRichard Henderson 6041fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6042fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6043efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6044fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6045fcf5ef2aSThomas Huth } 6046efe843d8SDavid Gibson } 6047fcf5ef2aSThomas Huth 6048fcf5ef2aSThomas Huth /* nabso - nabso. */ 6049fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 6050fcf5ef2aSThomas Huth { 6051fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6052fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6053fe21b785SRichard Henderson 6054fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6055fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6056fcf5ef2aSThomas Huth /* nabs never overflows */ 6057fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6058efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6059fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6060fcf5ef2aSThomas Huth } 6061efe843d8SDavid Gibson } 6062fcf5ef2aSThomas Huth 6063fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 6064fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 6065fcf5ef2aSThomas Huth { 6066fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 6067fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 6068fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6069fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6070fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6071fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 6072efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 6073efe843d8SDavid Gibson ~MASK(mb, me)); 6074fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 6075fcf5ef2aSThomas Huth tcg_temp_free(t0); 6076efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6077fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6078fcf5ef2aSThomas Huth } 6079efe843d8SDavid Gibson } 6080fcf5ef2aSThomas Huth 6081fcf5ef2aSThomas Huth /* rrib - rrib. */ 6082fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 6083fcf5ef2aSThomas Huth { 6084fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6085fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6086fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6087fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 6088fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6089fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6090fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6091fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 6092fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6093fcf5ef2aSThomas Huth tcg_temp_free(t0); 6094fcf5ef2aSThomas Huth tcg_temp_free(t1); 6095efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6096fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6097fcf5ef2aSThomas Huth } 6098efe843d8SDavid Gibson } 6099fcf5ef2aSThomas Huth 6100fcf5ef2aSThomas Huth /* sle - sle. */ 6101fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 6102fcf5ef2aSThomas Huth { 6103fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6104fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6105fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6106fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6107fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6108fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6109fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6110fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6111fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6112fcf5ef2aSThomas Huth tcg_temp_free(t0); 6113fcf5ef2aSThomas Huth tcg_temp_free(t1); 6114efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6115fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6116fcf5ef2aSThomas Huth } 6117efe843d8SDavid Gibson } 6118fcf5ef2aSThomas Huth 6119fcf5ef2aSThomas Huth /* sleq - sleq. */ 6120fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6121fcf5ef2aSThomas Huth { 6122fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6123fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6124fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6125fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6126fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6127fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6128fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6129fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6130fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6131fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6132fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6133fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6134fcf5ef2aSThomas Huth tcg_temp_free(t0); 6135fcf5ef2aSThomas Huth tcg_temp_free(t1); 6136fcf5ef2aSThomas Huth tcg_temp_free(t2); 6137efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6138fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6139fcf5ef2aSThomas Huth } 6140efe843d8SDavid Gibson } 6141fcf5ef2aSThomas Huth 6142fcf5ef2aSThomas Huth /* sliq - sliq. */ 6143fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6144fcf5ef2aSThomas Huth { 6145fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6146fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6147fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6148fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6149fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6150fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6151fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6152fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6153fcf5ef2aSThomas Huth tcg_temp_free(t0); 6154fcf5ef2aSThomas Huth tcg_temp_free(t1); 6155efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6156fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6157fcf5ef2aSThomas Huth } 6158efe843d8SDavid Gibson } 6159fcf5ef2aSThomas Huth 6160fcf5ef2aSThomas Huth /* slliq - slliq. */ 6161fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6162fcf5ef2aSThomas Huth { 6163fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6164fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6165fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6166fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6167fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6168fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6169fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6170fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6171fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6172fcf5ef2aSThomas Huth tcg_temp_free(t0); 6173fcf5ef2aSThomas Huth tcg_temp_free(t1); 6174efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6175fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6176fcf5ef2aSThomas Huth } 6177efe843d8SDavid Gibson } 6178fcf5ef2aSThomas Huth 6179fcf5ef2aSThomas Huth /* sllq - sllq. */ 6180fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6181fcf5ef2aSThomas Huth { 6182fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6183fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6184fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6185fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6186fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6187fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6188fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6189fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6190fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6191fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6192fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6193fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6194fcf5ef2aSThomas Huth tcg_gen_br(l2); 6195fcf5ef2aSThomas Huth gen_set_label(l1); 6196fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6197fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6198fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6199fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6200fcf5ef2aSThomas Huth gen_set_label(l2); 6201fcf5ef2aSThomas Huth tcg_temp_free(t0); 6202fcf5ef2aSThomas Huth tcg_temp_free(t1); 6203fcf5ef2aSThomas Huth tcg_temp_free(t2); 6204efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6205fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6206fcf5ef2aSThomas Huth } 6207efe843d8SDavid Gibson } 6208fcf5ef2aSThomas Huth 6209fcf5ef2aSThomas Huth /* slq - slq. */ 6210fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6211fcf5ef2aSThomas Huth { 6212fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6213fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6214fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6215fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6216fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6217fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6218fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6219fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6220fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6221fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6222fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6223fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6224fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6225fcf5ef2aSThomas Huth gen_set_label(l1); 6226fcf5ef2aSThomas Huth tcg_temp_free(t0); 6227fcf5ef2aSThomas Huth tcg_temp_free(t1); 6228efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6229fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6230fcf5ef2aSThomas Huth } 6231efe843d8SDavid Gibson } 6232fcf5ef2aSThomas Huth 6233fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6234fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6235fcf5ef2aSThomas Huth { 6236fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6237fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6238fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6239fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6240fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6241fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6242fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6243fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6244fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6245fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6246fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6247fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6248fcf5ef2aSThomas Huth gen_set_label(l1); 6249fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6250fcf5ef2aSThomas Huth tcg_temp_free(t0); 6251fcf5ef2aSThomas Huth tcg_temp_free(t1); 6252efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6253fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6254fcf5ef2aSThomas Huth } 6255efe843d8SDavid Gibson } 6256fcf5ef2aSThomas Huth 6257fcf5ef2aSThomas Huth /* sraq - sraq. */ 6258fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6259fcf5ef2aSThomas Huth { 6260fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6261fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6262fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6263fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6264fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6265fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6266fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6267fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6268fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6269fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6270fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6271fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6272fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6273fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6274fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6275fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6276fcf5ef2aSThomas Huth gen_set_label(l1); 6277fcf5ef2aSThomas Huth tcg_temp_free(t0); 6278fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6279fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6280fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6281fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6282fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6283fcf5ef2aSThomas Huth gen_set_label(l2); 6284fcf5ef2aSThomas Huth tcg_temp_free(t1); 6285fcf5ef2aSThomas Huth tcg_temp_free(t2); 6286efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6287fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6288fcf5ef2aSThomas Huth } 6289efe843d8SDavid Gibson } 6290fcf5ef2aSThomas Huth 6291fcf5ef2aSThomas Huth /* sre - sre. */ 6292fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6293fcf5ef2aSThomas Huth { 6294fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6295fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6296fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6297fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6298fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6299fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6300fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6301fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6302fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6303fcf5ef2aSThomas Huth tcg_temp_free(t0); 6304fcf5ef2aSThomas Huth tcg_temp_free(t1); 6305efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6306fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6307fcf5ef2aSThomas Huth } 6308efe843d8SDavid Gibson } 6309fcf5ef2aSThomas Huth 6310fcf5ef2aSThomas Huth /* srea - srea. */ 6311fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6312fcf5ef2aSThomas Huth { 6313fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6314fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6315fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6316fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6317fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6318fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6319fcf5ef2aSThomas Huth tcg_temp_free(t0); 6320fcf5ef2aSThomas Huth tcg_temp_free(t1); 6321efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6322fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6323fcf5ef2aSThomas Huth } 6324efe843d8SDavid Gibson } 6325fcf5ef2aSThomas Huth 6326fcf5ef2aSThomas Huth /* sreq */ 6327fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6328fcf5ef2aSThomas Huth { 6329fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6330fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6331fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6332fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6333fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6334fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6335fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6336fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6337fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6338fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6339fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6340fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6341fcf5ef2aSThomas Huth tcg_temp_free(t0); 6342fcf5ef2aSThomas Huth tcg_temp_free(t1); 6343fcf5ef2aSThomas Huth tcg_temp_free(t2); 6344efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6345fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6346fcf5ef2aSThomas Huth } 6347efe843d8SDavid Gibson } 6348fcf5ef2aSThomas Huth 6349fcf5ef2aSThomas Huth /* sriq */ 6350fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6351fcf5ef2aSThomas Huth { 6352fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6353fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6354fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6355fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6356fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6357fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6358fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6359fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6360fcf5ef2aSThomas Huth tcg_temp_free(t0); 6361fcf5ef2aSThomas Huth tcg_temp_free(t1); 6362efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6363fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6364fcf5ef2aSThomas Huth } 6365efe843d8SDavid Gibson } 6366fcf5ef2aSThomas Huth 6367fcf5ef2aSThomas Huth /* srliq */ 6368fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6369fcf5ef2aSThomas Huth { 6370fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6371fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6372fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6373fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6374fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6375fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6376fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6377fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6378fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6379fcf5ef2aSThomas Huth tcg_temp_free(t0); 6380fcf5ef2aSThomas Huth tcg_temp_free(t1); 6381efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6382fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6383fcf5ef2aSThomas Huth } 6384efe843d8SDavid Gibson } 6385fcf5ef2aSThomas Huth 6386fcf5ef2aSThomas Huth /* srlq */ 6387fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6388fcf5ef2aSThomas Huth { 6389fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6390fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6391fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6392fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6393fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6394fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6395fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6396fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6397fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6398fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6399fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6400fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6401fcf5ef2aSThomas Huth tcg_gen_br(l2); 6402fcf5ef2aSThomas Huth gen_set_label(l1); 6403fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6404fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6405fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6406fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6407fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6408fcf5ef2aSThomas Huth gen_set_label(l2); 6409fcf5ef2aSThomas Huth tcg_temp_free(t0); 6410fcf5ef2aSThomas Huth tcg_temp_free(t1); 6411fcf5ef2aSThomas Huth tcg_temp_free(t2); 6412efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6413fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6414fcf5ef2aSThomas Huth } 6415efe843d8SDavid Gibson } 6416fcf5ef2aSThomas Huth 6417fcf5ef2aSThomas Huth /* srq */ 6418fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6419fcf5ef2aSThomas Huth { 6420fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6421fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6422fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6423fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6424fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6425fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6426fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6427fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6428fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6429fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6430fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6431fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6432fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6433fcf5ef2aSThomas Huth gen_set_label(l1); 6434fcf5ef2aSThomas Huth tcg_temp_free(t0); 6435fcf5ef2aSThomas Huth tcg_temp_free(t1); 6436efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6437fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6438fcf5ef2aSThomas Huth } 6439efe843d8SDavid Gibson } 6440fcf5ef2aSThomas Huth 6441fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6442fcf5ef2aSThomas Huth 6443fcf5ef2aSThomas Huth /* dsa */ 6444fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6445fcf5ef2aSThomas Huth { 6446fcf5ef2aSThomas Huth /* XXX: TODO */ 6447fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6448fcf5ef2aSThomas Huth } 6449fcf5ef2aSThomas Huth 6450fcf5ef2aSThomas Huth /* esa */ 6451fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6452fcf5ef2aSThomas Huth { 6453fcf5ef2aSThomas Huth /* XXX: TODO */ 6454fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6455fcf5ef2aSThomas Huth } 6456fcf5ef2aSThomas Huth 6457fcf5ef2aSThomas Huth /* mfrom */ 6458fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6459fcf5ef2aSThomas Huth { 6460fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6461fcf5ef2aSThomas Huth GEN_PRIV; 6462fcf5ef2aSThomas Huth #else 6463fcf5ef2aSThomas Huth CHK_SV; 6464fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6465fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6466fcf5ef2aSThomas Huth } 6467fcf5ef2aSThomas Huth 6468fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6469fcf5ef2aSThomas Huth 6470fcf5ef2aSThomas Huth /* tlbld */ 6471fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6472fcf5ef2aSThomas Huth { 6473fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6474fcf5ef2aSThomas Huth GEN_PRIV; 6475fcf5ef2aSThomas Huth #else 6476fcf5ef2aSThomas Huth CHK_SV; 6477fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6478fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6479fcf5ef2aSThomas Huth } 6480fcf5ef2aSThomas Huth 6481fcf5ef2aSThomas Huth /* tlbli */ 6482fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6483fcf5ef2aSThomas Huth { 6484fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6485fcf5ef2aSThomas Huth GEN_PRIV; 6486fcf5ef2aSThomas Huth #else 6487fcf5ef2aSThomas Huth CHK_SV; 6488fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6489fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6490fcf5ef2aSThomas Huth } 6491fcf5ef2aSThomas Huth 6492fcf5ef2aSThomas Huth /* 74xx TLB management */ 6493fcf5ef2aSThomas Huth 6494fcf5ef2aSThomas Huth /* tlbld */ 6495fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6496fcf5ef2aSThomas Huth { 6497fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6498fcf5ef2aSThomas Huth GEN_PRIV; 6499fcf5ef2aSThomas Huth #else 6500fcf5ef2aSThomas Huth CHK_SV; 6501fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6502fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6503fcf5ef2aSThomas Huth } 6504fcf5ef2aSThomas Huth 6505fcf5ef2aSThomas Huth /* tlbli */ 6506fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6507fcf5ef2aSThomas Huth { 6508fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6509fcf5ef2aSThomas Huth GEN_PRIV; 6510fcf5ef2aSThomas Huth #else 6511fcf5ef2aSThomas Huth CHK_SV; 6512fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6513fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6514fcf5ef2aSThomas Huth } 6515fcf5ef2aSThomas Huth 6516fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6517fcf5ef2aSThomas Huth 6518fcf5ef2aSThomas Huth /* clf */ 6519fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6520fcf5ef2aSThomas Huth { 6521fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6522fcf5ef2aSThomas Huth } 6523fcf5ef2aSThomas Huth 6524fcf5ef2aSThomas Huth /* cli */ 6525fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6526fcf5ef2aSThomas Huth { 6527fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6528fcf5ef2aSThomas Huth GEN_PRIV; 6529fcf5ef2aSThomas Huth #else 6530fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6531fcf5ef2aSThomas Huth CHK_SV; 6532fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6533fcf5ef2aSThomas Huth } 6534fcf5ef2aSThomas Huth 6535fcf5ef2aSThomas Huth /* dclst */ 6536fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6537fcf5ef2aSThomas Huth { 6538fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6539fcf5ef2aSThomas Huth } 6540fcf5ef2aSThomas Huth 6541fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6542fcf5ef2aSThomas Huth { 6543fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6544fcf5ef2aSThomas Huth GEN_PRIV; 6545fcf5ef2aSThomas Huth #else 6546fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6547fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6548fcf5ef2aSThomas Huth TCGv t0; 6549fcf5ef2aSThomas Huth 6550fcf5ef2aSThomas Huth CHK_SV; 6551fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6552fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6553e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6554fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6555fcf5ef2aSThomas Huth tcg_temp_free(t0); 6556efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6557fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6558efe843d8SDavid Gibson } 6559fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6560fcf5ef2aSThomas Huth } 6561fcf5ef2aSThomas Huth 6562fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6563fcf5ef2aSThomas Huth { 6564fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6565fcf5ef2aSThomas Huth GEN_PRIV; 6566fcf5ef2aSThomas Huth #else 6567fcf5ef2aSThomas Huth TCGv t0; 6568fcf5ef2aSThomas Huth 6569fcf5ef2aSThomas Huth CHK_SV; 6570fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6571fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6572fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6573fcf5ef2aSThomas Huth tcg_temp_free(t0); 6574fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6575fcf5ef2aSThomas Huth } 6576fcf5ef2aSThomas Huth 6577fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6578fcf5ef2aSThomas Huth { 6579fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6580fcf5ef2aSThomas Huth GEN_PRIV; 6581fcf5ef2aSThomas Huth #else 6582fcf5ef2aSThomas Huth CHK_SV; 6583fcf5ef2aSThomas Huth 6584fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 658559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6586fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6587fcf5ef2aSThomas Huth } 6588fcf5ef2aSThomas Huth 6589fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6590fcf5ef2aSThomas Huth 6591fcf5ef2aSThomas Huth /* BookE specific instructions */ 6592fcf5ef2aSThomas Huth 6593fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6594fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6595fcf5ef2aSThomas Huth { 6596fcf5ef2aSThomas Huth /* XXX: TODO */ 6597fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6598fcf5ef2aSThomas Huth } 6599fcf5ef2aSThomas Huth 6600fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6601fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6602fcf5ef2aSThomas Huth { 6603fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6604fcf5ef2aSThomas Huth GEN_PRIV; 6605fcf5ef2aSThomas Huth #else 6606fcf5ef2aSThomas Huth TCGv t0; 6607fcf5ef2aSThomas Huth 6608fcf5ef2aSThomas Huth CHK_SV; 6609fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6610fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6611fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6612fcf5ef2aSThomas Huth tcg_temp_free(t0); 6613fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6614fcf5ef2aSThomas Huth } 6615fcf5ef2aSThomas Huth 6616fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6617fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6618fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6619fcf5ef2aSThomas Huth { 6620fcf5ef2aSThomas Huth TCGv t0, t1; 6621fcf5ef2aSThomas Huth 6622fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6623fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6624fcf5ef2aSThomas Huth 6625fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6626fcf5ef2aSThomas Huth case 0x05: 6627fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6628fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6629fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6630fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6631fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6632fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6633fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6634fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6635fcf5ef2aSThomas Huth break; 6636fcf5ef2aSThomas Huth case 0x04: 6637fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6638fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6639fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6640fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6641fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6642fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6643fcf5ef2aSThomas Huth break; 6644fcf5ef2aSThomas Huth case 0x01: 6645fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6646fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6647fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6648fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6649fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6650fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6651fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6652fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6653fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6654fcf5ef2aSThomas Huth break; 6655fcf5ef2aSThomas Huth case 0x00: 6656fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6657fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6658fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6659fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6660fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6661fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6662fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6663fcf5ef2aSThomas Huth break; 6664fcf5ef2aSThomas Huth case 0x0D: 6665fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6666fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 6667fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6668fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6669fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6670fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6671fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6672fcf5ef2aSThomas Huth break; 6673fcf5ef2aSThomas Huth case 0x0C: 6674fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6675fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6676fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6677fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6678fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6679fcf5ef2aSThomas Huth break; 6680fcf5ef2aSThomas Huth } 6681fcf5ef2aSThomas Huth if (opc2 & 0x04) { 6682fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6683fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 6684fcf5ef2aSThomas Huth if (opc2 & 0x02) { 6685fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 6686fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6687fcf5ef2aSThomas Huth } else { 6688fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 6689fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6690fcf5ef2aSThomas Huth } 6691fcf5ef2aSThomas Huth 6692fcf5ef2aSThomas Huth if (opc3 & 0x12) { 6693fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 6694fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6695fcf5ef2aSThomas Huth 6696fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6697fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6698fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6699fcf5ef2aSThomas Huth } 6700fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6701fcf5ef2aSThomas Huth /* Signed */ 6702fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6703fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6704fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6705fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6706fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6707fcf5ef2aSThomas Huth /* Saturate */ 6708fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6709fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6710fcf5ef2aSThomas Huth } 6711fcf5ef2aSThomas Huth } else { 6712fcf5ef2aSThomas Huth /* Unsigned */ 6713fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6714fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6715fcf5ef2aSThomas Huth /* Saturate */ 6716fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6717fcf5ef2aSThomas Huth } 6718fcf5ef2aSThomas Huth } 6719fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6720fcf5ef2aSThomas Huth /* Check overflow */ 6721fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6722fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6723fcf5ef2aSThomas Huth } 6724fcf5ef2aSThomas Huth gen_set_label(l1); 6725fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6726fcf5ef2aSThomas Huth } 6727fcf5ef2aSThomas Huth } else { 6728fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6729fcf5ef2aSThomas Huth } 6730fcf5ef2aSThomas Huth tcg_temp_free(t0); 6731fcf5ef2aSThomas Huth tcg_temp_free(t1); 6732fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6733fcf5ef2aSThomas Huth /* Update Rc0 */ 6734fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6735fcf5ef2aSThomas Huth } 6736fcf5ef2aSThomas Huth } 6737fcf5ef2aSThomas Huth 6738fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6739fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6740fcf5ef2aSThomas Huth { \ 6741fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6742fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6743fcf5ef2aSThomas Huth } 6744fcf5ef2aSThomas Huth 6745fcf5ef2aSThomas Huth /* macchw - macchw. */ 6746fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6747fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6748fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6749fcf5ef2aSThomas Huth /* macchws - macchws. */ 6750fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6751fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6752fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6753fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6754fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6755fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6756fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6757fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6758fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6759fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6760fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6761fcf5ef2aSThomas Huth /* machhw - machhw. */ 6762fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6763fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6764fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6765fcf5ef2aSThomas Huth /* machhws - machhws. */ 6766fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6767fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6768fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6769fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6770fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6771fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6772fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6773fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6774fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6775fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6776fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6777fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6778fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6779fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6780fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6781fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6782fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6783fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6784fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6785fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6786fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6787fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6788fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6789fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6790fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6791fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6792fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6793fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6794fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6795fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6796fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6797fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6798fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6799fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6800fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6801fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6802fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6803fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6804fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6805fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6806fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6807fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6808fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6809fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6810fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6811fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6812fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6813fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6814fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6815fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6816fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6817fcf5ef2aSThomas Huth 6818fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6819fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6820fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6821fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6822fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6823fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6824fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6825fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6826fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6827fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6828fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6829fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6830fcf5ef2aSThomas Huth 6831fcf5ef2aSThomas Huth /* mfdcr */ 6832fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6833fcf5ef2aSThomas Huth { 6834fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6835fcf5ef2aSThomas Huth GEN_PRIV; 6836fcf5ef2aSThomas Huth #else 6837fcf5ef2aSThomas Huth TCGv dcrn; 6838fcf5ef2aSThomas Huth 6839fcf5ef2aSThomas Huth CHK_SV; 6840fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6841fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6842fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6843fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6844fcf5ef2aSThomas Huth } 6845fcf5ef2aSThomas Huth 6846fcf5ef2aSThomas Huth /* mtdcr */ 6847fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6848fcf5ef2aSThomas Huth { 6849fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6850fcf5ef2aSThomas Huth GEN_PRIV; 6851fcf5ef2aSThomas Huth #else 6852fcf5ef2aSThomas Huth TCGv dcrn; 6853fcf5ef2aSThomas Huth 6854fcf5ef2aSThomas Huth CHK_SV; 6855fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6856fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6857fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6858fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6859fcf5ef2aSThomas Huth } 6860fcf5ef2aSThomas Huth 6861fcf5ef2aSThomas Huth /* mfdcrx */ 6862fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6863fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6864fcf5ef2aSThomas Huth { 6865fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6866fcf5ef2aSThomas Huth GEN_PRIV; 6867fcf5ef2aSThomas Huth #else 6868fcf5ef2aSThomas Huth CHK_SV; 6869fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6870fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6871fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6872fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6873fcf5ef2aSThomas Huth } 6874fcf5ef2aSThomas Huth 6875fcf5ef2aSThomas Huth /* mtdcrx */ 6876fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6877fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6878fcf5ef2aSThomas Huth { 6879fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6880fcf5ef2aSThomas Huth GEN_PRIV; 6881fcf5ef2aSThomas Huth #else 6882fcf5ef2aSThomas Huth CHK_SV; 6883fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6884fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6885fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6886fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6887fcf5ef2aSThomas Huth } 6888fcf5ef2aSThomas Huth 6889fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6890fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6891fcf5ef2aSThomas Huth { 6892fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6893fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6894fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6895fcf5ef2aSThomas Huth } 6896fcf5ef2aSThomas Huth 6897fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6898fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6899fcf5ef2aSThomas Huth { 6900fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6901fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6902fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6903fcf5ef2aSThomas Huth } 6904fcf5ef2aSThomas Huth 6905fcf5ef2aSThomas Huth /* dccci */ 6906fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6907fcf5ef2aSThomas Huth { 6908fcf5ef2aSThomas Huth CHK_SV; 6909fcf5ef2aSThomas Huth /* interpreted as no-op */ 6910fcf5ef2aSThomas Huth } 6911fcf5ef2aSThomas Huth 6912fcf5ef2aSThomas Huth /* dcread */ 6913fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6914fcf5ef2aSThomas Huth { 6915fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6916fcf5ef2aSThomas Huth GEN_PRIV; 6917fcf5ef2aSThomas Huth #else 6918fcf5ef2aSThomas Huth TCGv EA, val; 6919fcf5ef2aSThomas Huth 6920fcf5ef2aSThomas Huth CHK_SV; 6921fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6922fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6923fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6924fcf5ef2aSThomas Huth val = tcg_temp_new(); 6925fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6926fcf5ef2aSThomas Huth tcg_temp_free(val); 6927fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6928fcf5ef2aSThomas Huth tcg_temp_free(EA); 6929fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6930fcf5ef2aSThomas Huth } 6931fcf5ef2aSThomas Huth 6932fcf5ef2aSThomas Huth /* icbt */ 6933fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6934fcf5ef2aSThomas Huth { 6935efe843d8SDavid Gibson /* 6936efe843d8SDavid Gibson * interpreted as no-op 6937efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6938efe843d8SDavid Gibson * does not generate any exception 6939fcf5ef2aSThomas Huth */ 6940fcf5ef2aSThomas Huth } 6941fcf5ef2aSThomas Huth 6942fcf5ef2aSThomas Huth /* iccci */ 6943fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6944fcf5ef2aSThomas Huth { 6945fcf5ef2aSThomas Huth CHK_SV; 6946fcf5ef2aSThomas Huth /* interpreted as no-op */ 6947fcf5ef2aSThomas Huth } 6948fcf5ef2aSThomas Huth 6949fcf5ef2aSThomas Huth /* icread */ 6950fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6951fcf5ef2aSThomas Huth { 6952fcf5ef2aSThomas Huth CHK_SV; 6953fcf5ef2aSThomas Huth /* interpreted as no-op */ 6954fcf5ef2aSThomas Huth } 6955fcf5ef2aSThomas Huth 6956fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6957fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6958fcf5ef2aSThomas Huth { 6959fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6960fcf5ef2aSThomas Huth GEN_PRIV; 6961fcf5ef2aSThomas Huth #else 6962fcf5ef2aSThomas Huth CHK_SV; 6963fcf5ef2aSThomas Huth /* Restore CPU state */ 6964fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 696559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6966fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6967fcf5ef2aSThomas Huth } 6968fcf5ef2aSThomas Huth 6969fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6970fcf5ef2aSThomas Huth { 6971fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6972fcf5ef2aSThomas Huth GEN_PRIV; 6973fcf5ef2aSThomas Huth #else 6974fcf5ef2aSThomas Huth CHK_SV; 6975fcf5ef2aSThomas Huth /* Restore CPU state */ 6976fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 697759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6978fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6979fcf5ef2aSThomas Huth } 6980fcf5ef2aSThomas Huth 6981fcf5ef2aSThomas Huth /* BookE specific */ 6982fcf5ef2aSThomas Huth 6983fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6984fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6985fcf5ef2aSThomas Huth { 6986fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6987fcf5ef2aSThomas Huth GEN_PRIV; 6988fcf5ef2aSThomas Huth #else 6989fcf5ef2aSThomas Huth CHK_SV; 6990fcf5ef2aSThomas Huth /* Restore CPU state */ 6991fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 699259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6993fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6994fcf5ef2aSThomas Huth } 6995fcf5ef2aSThomas Huth 6996fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6997fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6998fcf5ef2aSThomas Huth { 6999fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7000fcf5ef2aSThomas Huth GEN_PRIV; 7001fcf5ef2aSThomas Huth #else 7002fcf5ef2aSThomas Huth CHK_SV; 7003fcf5ef2aSThomas Huth /* Restore CPU state */ 7004fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 700559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 7006fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7007fcf5ef2aSThomas Huth } 7008fcf5ef2aSThomas Huth 7009fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 7010fcf5ef2aSThomas Huth 7011fcf5ef2aSThomas Huth /* tlbre */ 7012fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 7013fcf5ef2aSThomas Huth { 7014fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7015fcf5ef2aSThomas Huth GEN_PRIV; 7016fcf5ef2aSThomas Huth #else 7017fcf5ef2aSThomas Huth CHK_SV; 7018fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7019fcf5ef2aSThomas Huth case 0: 7020fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 7021fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7022fcf5ef2aSThomas Huth break; 7023fcf5ef2aSThomas Huth case 1: 7024fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 7025fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7026fcf5ef2aSThomas Huth break; 7027fcf5ef2aSThomas Huth default: 7028fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7029fcf5ef2aSThomas Huth break; 7030fcf5ef2aSThomas Huth } 7031fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7032fcf5ef2aSThomas Huth } 7033fcf5ef2aSThomas Huth 7034fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7035fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 7036fcf5ef2aSThomas Huth { 7037fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7038fcf5ef2aSThomas Huth GEN_PRIV; 7039fcf5ef2aSThomas Huth #else 7040fcf5ef2aSThomas Huth TCGv t0; 7041fcf5ef2aSThomas Huth 7042fcf5ef2aSThomas Huth CHK_SV; 7043fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7044fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7045fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7046fcf5ef2aSThomas Huth tcg_temp_free(t0); 7047fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7048fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7049fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7050fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7051fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7052fcf5ef2aSThomas Huth gen_set_label(l1); 7053fcf5ef2aSThomas Huth } 7054fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7055fcf5ef2aSThomas Huth } 7056fcf5ef2aSThomas Huth 7057fcf5ef2aSThomas Huth /* tlbwe */ 7058fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 7059fcf5ef2aSThomas Huth { 7060fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7061fcf5ef2aSThomas Huth GEN_PRIV; 7062fcf5ef2aSThomas Huth #else 7063fcf5ef2aSThomas Huth CHK_SV; 7064fcf5ef2aSThomas Huth 7065fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7066fcf5ef2aSThomas Huth case 0: 7067fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 7068fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7069fcf5ef2aSThomas Huth break; 7070fcf5ef2aSThomas Huth case 1: 7071fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 7072fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7073fcf5ef2aSThomas Huth break; 7074fcf5ef2aSThomas Huth default: 7075fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7076fcf5ef2aSThomas Huth break; 7077fcf5ef2aSThomas Huth } 7078fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7079fcf5ef2aSThomas Huth } 7080fcf5ef2aSThomas Huth 7081fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 7082fcf5ef2aSThomas Huth 7083fcf5ef2aSThomas Huth /* tlbre */ 7084fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 7085fcf5ef2aSThomas Huth { 7086fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7087fcf5ef2aSThomas Huth GEN_PRIV; 7088fcf5ef2aSThomas Huth #else 7089fcf5ef2aSThomas Huth CHK_SV; 7090fcf5ef2aSThomas Huth 7091fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7092fcf5ef2aSThomas Huth case 0: 7093fcf5ef2aSThomas Huth case 1: 7094fcf5ef2aSThomas Huth case 2: 7095fcf5ef2aSThomas Huth { 7096fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7097fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 7098fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 7099fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7100fcf5ef2aSThomas Huth } 7101fcf5ef2aSThomas Huth break; 7102fcf5ef2aSThomas Huth default: 7103fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7104fcf5ef2aSThomas Huth break; 7105fcf5ef2aSThomas Huth } 7106fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7107fcf5ef2aSThomas Huth } 7108fcf5ef2aSThomas Huth 7109fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7110fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7111fcf5ef2aSThomas Huth { 7112fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7113fcf5ef2aSThomas Huth GEN_PRIV; 7114fcf5ef2aSThomas Huth #else 7115fcf5ef2aSThomas Huth TCGv t0; 7116fcf5ef2aSThomas Huth 7117fcf5ef2aSThomas Huth CHK_SV; 7118fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7119fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7120fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7121fcf5ef2aSThomas Huth tcg_temp_free(t0); 7122fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7123fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7124fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7125fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7126fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7127fcf5ef2aSThomas Huth gen_set_label(l1); 7128fcf5ef2aSThomas Huth } 7129fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7130fcf5ef2aSThomas Huth } 7131fcf5ef2aSThomas Huth 7132fcf5ef2aSThomas Huth /* tlbwe */ 7133fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7134fcf5ef2aSThomas Huth { 7135fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7136fcf5ef2aSThomas Huth GEN_PRIV; 7137fcf5ef2aSThomas Huth #else 7138fcf5ef2aSThomas Huth CHK_SV; 7139fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7140fcf5ef2aSThomas Huth case 0: 7141fcf5ef2aSThomas Huth case 1: 7142fcf5ef2aSThomas Huth case 2: 7143fcf5ef2aSThomas Huth { 7144fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7145fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7146fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7147fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7148fcf5ef2aSThomas Huth } 7149fcf5ef2aSThomas Huth break; 7150fcf5ef2aSThomas Huth default: 7151fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7152fcf5ef2aSThomas Huth break; 7153fcf5ef2aSThomas Huth } 7154fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7155fcf5ef2aSThomas Huth } 7156fcf5ef2aSThomas Huth 7157fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7158fcf5ef2aSThomas Huth 7159fcf5ef2aSThomas Huth /* tlbre */ 7160fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7161fcf5ef2aSThomas Huth { 7162fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7163fcf5ef2aSThomas Huth GEN_PRIV; 7164fcf5ef2aSThomas Huth #else 7165fcf5ef2aSThomas Huth CHK_SV; 7166fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7167fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7168fcf5ef2aSThomas Huth } 7169fcf5ef2aSThomas Huth 7170fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7171fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7172fcf5ef2aSThomas Huth { 7173fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7174fcf5ef2aSThomas Huth GEN_PRIV; 7175fcf5ef2aSThomas Huth #else 7176fcf5ef2aSThomas Huth TCGv t0; 7177fcf5ef2aSThomas Huth 7178fcf5ef2aSThomas Huth CHK_SV; 7179fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7180fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7181fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7182fcf5ef2aSThomas Huth } else { 7183fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7184fcf5ef2aSThomas Huth } 7185fcf5ef2aSThomas Huth 7186fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7187fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7188fcf5ef2aSThomas Huth tcg_temp_free(t0); 7189fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7190fcf5ef2aSThomas Huth } 7191fcf5ef2aSThomas Huth 7192fcf5ef2aSThomas Huth /* tlbwe */ 7193fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7194fcf5ef2aSThomas Huth { 7195fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7196fcf5ef2aSThomas Huth GEN_PRIV; 7197fcf5ef2aSThomas Huth #else 7198fcf5ef2aSThomas Huth CHK_SV; 7199fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7200fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7201fcf5ef2aSThomas Huth } 7202fcf5ef2aSThomas Huth 7203fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7204fcf5ef2aSThomas Huth { 7205fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7206fcf5ef2aSThomas Huth GEN_PRIV; 7207fcf5ef2aSThomas Huth #else 7208fcf5ef2aSThomas Huth TCGv t0; 7209fcf5ef2aSThomas Huth 7210fcf5ef2aSThomas Huth CHK_SV; 7211fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7212fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7213fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7214fcf5ef2aSThomas Huth tcg_temp_free(t0); 7215fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7216fcf5ef2aSThomas Huth } 7217fcf5ef2aSThomas Huth 7218fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7219fcf5ef2aSThomas Huth { 7220fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7221fcf5ef2aSThomas Huth GEN_PRIV; 7222fcf5ef2aSThomas Huth #else 7223fcf5ef2aSThomas Huth TCGv t0; 7224fcf5ef2aSThomas Huth 7225fcf5ef2aSThomas Huth CHK_SV; 7226fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7227fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7228fcf5ef2aSThomas Huth 7229fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7230fcf5ef2aSThomas Huth case 0: 7231fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7232fcf5ef2aSThomas Huth break; 7233fcf5ef2aSThomas Huth case 1: 7234fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7235fcf5ef2aSThomas Huth break; 7236fcf5ef2aSThomas Huth case 3: 7237fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7238fcf5ef2aSThomas Huth break; 7239fcf5ef2aSThomas Huth default: 7240fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7241fcf5ef2aSThomas Huth break; 7242fcf5ef2aSThomas Huth } 7243fcf5ef2aSThomas Huth 7244fcf5ef2aSThomas Huth tcg_temp_free(t0); 7245fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7246fcf5ef2aSThomas Huth } 7247fcf5ef2aSThomas Huth 7248fcf5ef2aSThomas Huth 7249fcf5ef2aSThomas Huth /* wrtee */ 7250fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7251fcf5ef2aSThomas Huth { 7252fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7253fcf5ef2aSThomas Huth GEN_PRIV; 7254fcf5ef2aSThomas Huth #else 7255fcf5ef2aSThomas Huth TCGv t0; 7256fcf5ef2aSThomas Huth 7257fcf5ef2aSThomas Huth CHK_SV; 7258fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7259fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7260fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7261fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7262fcf5ef2aSThomas Huth tcg_temp_free(t0); 7263efe843d8SDavid Gibson /* 7264efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7265efe843d8SDavid Gibson * just set msr_ee to 1 7266fcf5ef2aSThomas Huth */ 7267d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7268fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7269fcf5ef2aSThomas Huth } 7270fcf5ef2aSThomas Huth 7271fcf5ef2aSThomas Huth /* wrteei */ 7272fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7273fcf5ef2aSThomas Huth { 7274fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7275fcf5ef2aSThomas Huth GEN_PRIV; 7276fcf5ef2aSThomas Huth #else 7277fcf5ef2aSThomas Huth CHK_SV; 7278fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7279fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7280fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7281d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7282fcf5ef2aSThomas Huth } else { 7283fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7284fcf5ef2aSThomas Huth } 7285fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7286fcf5ef2aSThomas Huth } 7287fcf5ef2aSThomas Huth 7288fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7289fcf5ef2aSThomas Huth 7290fcf5ef2aSThomas Huth /* dlmzb */ 7291fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7292fcf5ef2aSThomas Huth { 7293fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7294fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7295fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7296fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7297fcf5ef2aSThomas Huth } 7298fcf5ef2aSThomas Huth 7299fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7300fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7301fcf5ef2aSThomas Huth { 7302fcf5ef2aSThomas Huth /* interpreted as no-op */ 7303fcf5ef2aSThomas Huth } 7304fcf5ef2aSThomas Huth 7305fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7306fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7307fcf5ef2aSThomas Huth { 730827a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 730927a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 731027a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 731127a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 731227a3ea7eSBALATON Zoltan } 731327a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7314fcf5ef2aSThomas Huth } 7315fcf5ef2aSThomas Huth 7316fcf5ef2aSThomas Huth /* icbt */ 7317fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7318fcf5ef2aSThomas Huth { 7319efe843d8SDavid Gibson /* 7320efe843d8SDavid Gibson * interpreted as no-op 7321efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7322efe843d8SDavid Gibson * does not generate any exception 7323fcf5ef2aSThomas Huth */ 7324fcf5ef2aSThomas Huth } 7325fcf5ef2aSThomas Huth 7326fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7327fcf5ef2aSThomas Huth 7328fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7329fcf5ef2aSThomas Huth { 7330fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7331fcf5ef2aSThomas Huth GEN_PRIV; 7332fcf5ef2aSThomas Huth #else 7333ebca5e6dSCédric Le Goater CHK_HV; 7334d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 73357af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 73367af1e7b0SCédric Le Goater } else { 7337fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 73387af1e7b0SCédric Le Goater } 7339fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7340fcf5ef2aSThomas Huth } 7341fcf5ef2aSThomas Huth 7342fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7343fcf5ef2aSThomas Huth { 7344fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7345fcf5ef2aSThomas Huth GEN_PRIV; 7346fcf5ef2aSThomas Huth #else 7347ebca5e6dSCédric Le Goater CHK_HV; 7348d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 73497af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 73507af1e7b0SCédric Le Goater } else { 7351fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 73527af1e7b0SCédric Le Goater } 7353fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7354fcf5ef2aSThomas Huth } 7355fcf5ef2aSThomas Huth 73565ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 73575ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 73585ba7ba1dSCédric Le Goater { 73595ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 73605ba7ba1dSCédric Le Goater GEN_PRIV; 73615ba7ba1dSCédric Le Goater #else 73625ba7ba1dSCédric Le Goater CHK_SV; 73635ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 73645ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 73655ba7ba1dSCédric Le Goater } 73665ba7ba1dSCédric Le Goater 73675ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 73685ba7ba1dSCédric Le Goater { 73695ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 73705ba7ba1dSCédric Le Goater GEN_PRIV; 73715ba7ba1dSCédric Le Goater #else 73725ba7ba1dSCédric Le Goater CHK_SV; 73735ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 73745ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 73755ba7ba1dSCédric Le Goater } 73765ba7ba1dSCédric Le Goater #endif 73775ba7ba1dSCédric Le Goater 73787af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 73797af1e7b0SCédric Le Goater { 73807af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 73817af1e7b0SCédric Le Goater GEN_PRIV; 73827af1e7b0SCédric Le Goater #else 73837af1e7b0SCédric Le Goater CHK_HV; 73847af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 73857af1e7b0SCédric Le Goater /* interpreted as no-op */ 73867af1e7b0SCédric Le Goater } 7387fcf5ef2aSThomas Huth 7388fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7389fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7390fcf5ef2aSThomas Huth { 7391fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7392fcf5ef2aSThomas Huth 7393fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7394fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7395fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7396fcf5ef2aSThomas Huth } 7397fcf5ef2aSThomas Huth 7398fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7399fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7400fcf5ef2aSThomas Huth { 7401fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7402fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7403fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7404fcf5ef2aSThomas Huth 7405fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7406fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7407fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7408fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7409fcf5ef2aSThomas Huth } else { 7410fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7411fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7412fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7413fcf5ef2aSThomas Huth } 7414fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7415fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7416fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7417fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7418fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7419fcf5ef2aSThomas Huth } 7420fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7421fcf5ef2aSThomas Huth 7422fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7423fcf5ef2aSThomas Huth { 7424fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7425fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7426fcf5ef2aSThomas Huth return; 7427fcf5ef2aSThomas Huth } 7428fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7429fcf5ef2aSThomas Huth } 7430fcf5ef2aSThomas Huth 7431fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7432fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7433fcf5ef2aSThomas Huth { \ 7434fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7435fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7436fcf5ef2aSThomas Huth return; \ 7437fcf5ef2aSThomas Huth } \ 7438efe843d8SDavid Gibson /* \ 7439efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7440fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7441fcf5ef2aSThomas Huth * \ 7442fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7443fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7444fcf5ef2aSThomas Huth */ \ 7445fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7446fcf5ef2aSThomas Huth } 7447fcf5ef2aSThomas Huth 7448fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7449fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7450fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7451fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7452fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7453fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7454fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7455efe843d8SDavid Gibson 7456b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7457b8b4576eSSuraj Jitindar Singh { 7458efe843d8SDavid Gibson /* Do Nothing */ 7459b8b4576eSSuraj Jitindar Singh } 7460fcf5ef2aSThomas Huth 746180b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 746280b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 746380b8c1eeSNikunj A Dadhania { \ 7464efe843d8SDavid Gibson /* \ 7465efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7466efe843d8SDavid Gibson * implementation of the copy paste facility \ 746780b8c1eeSNikunj A Dadhania */ \ 746880b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 746980b8c1eeSNikunj A Dadhania } 747080b8c1eeSNikunj A Dadhania 747180b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 747280b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 747380b8c1eeSNikunj A Dadhania 7474fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7475fcf5ef2aSThomas Huth { 7476fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7477fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7478fcf5ef2aSThomas Huth return; 7479fcf5ef2aSThomas Huth } 7480efe843d8SDavid Gibson /* 7481efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7482efe843d8SDavid Gibson * simple: 7483fcf5ef2aSThomas Huth * 7484fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7485fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7486fcf5ef2aSThomas Huth */ 7487fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7488fcf5ef2aSThomas Huth } 7489fcf5ef2aSThomas Huth 7490fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7491fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7492fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7493fcf5ef2aSThomas Huth { \ 7494fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7495fcf5ef2aSThomas Huth } 7496fcf5ef2aSThomas Huth 7497fcf5ef2aSThomas Huth #else 7498fcf5ef2aSThomas Huth 7499fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7500fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7501fcf5ef2aSThomas Huth { \ 7502fcf5ef2aSThomas Huth CHK_SV; \ 7503fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7504fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7505fcf5ef2aSThomas Huth return; \ 7506fcf5ef2aSThomas Huth } \ 7507efe843d8SDavid Gibson /* \ 7508efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7509fcf5ef2aSThomas Huth * simple: \ 7510fcf5ef2aSThomas Huth * \ 7511fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7512fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7513fcf5ef2aSThomas Huth */ \ 7514fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7515fcf5ef2aSThomas Huth } 7516fcf5ef2aSThomas Huth 7517fcf5ef2aSThomas Huth #endif 7518fcf5ef2aSThomas Huth 7519fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7520fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7521fcf5ef2aSThomas Huth 75221a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 75231a404c91SMark Cave-Ayland { 7524e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 75251a404c91SMark Cave-Ayland } 75261a404c91SMark Cave-Ayland 75271a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 75281a404c91SMark Cave-Ayland { 7529e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 75301a404c91SMark Cave-Ayland } 75311a404c91SMark Cave-Ayland 7532c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7533c4a18dbfSMark Cave-Ayland { 753437da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7535c4a18dbfSMark Cave-Ayland } 7536c4a18dbfSMark Cave-Ayland 7537c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7538c4a18dbfSMark Cave-Ayland { 753937da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7540c4a18dbfSMark Cave-Ayland } 7541c4a18dbfSMark Cave-Ayland 7542c9826ae9SRichard Henderson /* 7543*f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 7544*f2aabda8SRichard Henderson */ 7545*f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 7546*f2aabda8SRichard Henderson { 7547*f2aabda8SRichard Henderson return x * 4; 7548*f2aabda8SRichard Henderson } 7549*f2aabda8SRichard Henderson 7550*f2aabda8SRichard Henderson /* 7551c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 7552c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 7553c9826ae9SRichard Henderson * proper variable. 7554c9826ae9SRichard Henderson */ 7555c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 7556c9826ae9SRichard Henderson do { \ 7557c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 7558c9826ae9SRichard Henderson return false; \ 7559c9826ae9SRichard Henderson } \ 7560c9826ae9SRichard Henderson } while (0) 7561c9826ae9SRichard Henderson 7562c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 7563c9826ae9SRichard Henderson do { \ 7564c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 7565c9826ae9SRichard Henderson return false; \ 7566c9826ae9SRichard Henderson } \ 7567c9826ae9SRichard Henderson } while (0) 7568c9826ae9SRichard Henderson 7569c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 7570c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 7571c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 7572c9826ae9SRichard Henderson #else 7573c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 7574c9826ae9SRichard Henderson #endif 7575c9826ae9SRichard Henderson 7576*f2aabda8SRichard Henderson /* 7577*f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 7578*f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 7579*f2aabda8SRichard Henderson */ 7580*f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 7581*f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7582*f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 7583*f2aabda8SRichard Henderson 7584*f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 7585*f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7586*f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 7587*f2aabda8SRichard Henderson 7588*f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 7589*f2aabda8SRichard Henderson 7590*f2aabda8SRichard Henderson 759199082815SRichard Henderson #include "decode-insn32.c.inc" 759299082815SRichard Henderson #include "decode-insn64.c.inc" 759399082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 759499082815SRichard Henderson 7595139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7596fcf5ef2aSThomas Huth 7597139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7598fcf5ef2aSThomas Huth 7599139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7600fcf5ef2aSThomas Huth 7601139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7602fcf5ef2aSThomas Huth 7603139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7604fcf5ef2aSThomas Huth 76055cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 76065cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 76075cb091a4SNikunj A Dadhania { 76085cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 76095cb091a4SNikunj A Dadhania case 0: /* lfdp */ 76105cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 76115cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 76125cb091a4SNikunj A Dadhania } 76135cb091a4SNikunj A Dadhania break; 76145cb091a4SNikunj A Dadhania case 2: /* lxsd */ 76155cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 76165cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 76175cb091a4SNikunj A Dadhania } 76185cb091a4SNikunj A Dadhania break; 76195cb091a4SNikunj A Dadhania case 3: /* lxssp */ 76205cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 76215cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 76225cb091a4SNikunj A Dadhania } 76235cb091a4SNikunj A Dadhania break; 76245cb091a4SNikunj A Dadhania } 76255cb091a4SNikunj A Dadhania return gen_invalid(ctx); 76265cb091a4SNikunj A Dadhania } 76275cb091a4SNikunj A Dadhania 7628d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7629e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7630e3001664SNikunj A Dadhania { 7631e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7632e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7633e3001664SNikunj A Dadhania case 1: /* lxv */ 7634d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7635d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7636d59ba583SNikunj A Dadhania } 7637e3001664SNikunj A Dadhania break; 7638e3001664SNikunj A Dadhania case 5: /* stxv */ 7639d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7640d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7641d59ba583SNikunj A Dadhania } 7642e3001664SNikunj A Dadhania break; 7643e3001664SNikunj A Dadhania } 7644e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7645e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7646e3001664SNikunj A Dadhania case 0: /* stfdp */ 7647e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7648e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7649e3001664SNikunj A Dadhania } 7650e3001664SNikunj A Dadhania break; 7651e3001664SNikunj A Dadhania case 2: /* stxsd */ 7652e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7653e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7654e3001664SNikunj A Dadhania } 7655e3001664SNikunj A Dadhania break; 7656e3001664SNikunj A Dadhania case 3: /* stxssp */ 7657e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7658e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7659e3001664SNikunj A Dadhania } 7660e3001664SNikunj A Dadhania break; 7661e3001664SNikunj A Dadhania } 7662e3001664SNikunj A Dadhania } 7663e3001664SNikunj A Dadhania return gen_invalid(ctx); 7664e3001664SNikunj A Dadhania } 7665e3001664SNikunj A Dadhania 76669d69cfa2SLijun Pan #if defined(TARGET_PPC64) 76679d69cfa2SLijun Pan /* brd */ 76689d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 76699d69cfa2SLijun Pan { 76709d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 76719d69cfa2SLijun Pan } 76729d69cfa2SLijun Pan 76739d69cfa2SLijun Pan /* brw */ 76749d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 76759d69cfa2SLijun Pan { 76769d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 76779d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 76789d69cfa2SLijun Pan 76799d69cfa2SLijun Pan } 76809d69cfa2SLijun Pan 76819d69cfa2SLijun Pan /* brh */ 76829d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 76839d69cfa2SLijun Pan { 76849d69cfa2SLijun Pan TCGv_i64 t0 = tcg_temp_new_i64(); 76859d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 76869d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 76879d69cfa2SLijun Pan 76889d69cfa2SLijun Pan tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 76899d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 76909d69cfa2SLijun Pan tcg_gen_and_i64(t2, t1, t0); 76919d69cfa2SLijun Pan tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 76929d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 76939d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 76949d69cfa2SLijun Pan 76959d69cfa2SLijun Pan tcg_temp_free_i64(t0); 76969d69cfa2SLijun Pan tcg_temp_free_i64(t1); 76979d69cfa2SLijun Pan tcg_temp_free_i64(t2); 76989d69cfa2SLijun Pan } 76999d69cfa2SLijun Pan #endif 77009d69cfa2SLijun Pan 7701fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 77029d69cfa2SLijun Pan #if defined(TARGET_PPC64) 77039d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 77049d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 77059d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 77069d69cfa2SLijun Pan #endif 7707fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7708fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 7709fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7710fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 7711fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7712fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7713fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7714fcf5ef2aSThomas Huth #endif 7715fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7716fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7717fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7718fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7719fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7720fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7721fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7722fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7723fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7724fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7725fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7726fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7727fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7728fcf5ef2aSThomas Huth #endif 7729fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7730fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7731fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7732fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7733fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7734fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7735fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 773680b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7737b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 773880b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7739fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7740fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7741fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7742fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7743fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7744fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7745fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7746fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7747fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7748fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7749fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7750fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7751fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7752fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7753fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7754fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7755fcf5ef2aSThomas Huth #endif 7756fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7757fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7758fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7759fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7760fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7761fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7762fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7763fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7764fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7765fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7766fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7767fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7768fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7769fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7770fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7771fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7772fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7773fcf5ef2aSThomas Huth #endif 7774fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7775fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 7776fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 7777fcf5ef2aSThomas Huth #endif 77785cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 77795cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7780d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 7781e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7782fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7783fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7784fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7785fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7786fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7787fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7788c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7789fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7790fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7791fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7792fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7793a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7794a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7795fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7796fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7797fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7798fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7799a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7800a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7801fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7802fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7803fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7804fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7805fcf5ef2aSThomas Huth #endif 7806fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7807fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7808c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7809fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7810fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7811fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7812fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7813fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7814fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7815fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7816fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7817fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 78183c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 78193c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 78203c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 78213c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 78223c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 78233c89b8d6SNicholas Piggin #endif 7824cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7825fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7826fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7827fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7828fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7829fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7830fcf5ef2aSThomas Huth #endif 78313c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 78323c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 78333c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7834fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7835fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7836fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7837fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7838fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7839fcf5ef2aSThomas Huth #endif 7840fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7841fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7842fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7843fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7844fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7845fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7846fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7847fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7848fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7849b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7850fcf5ef2aSThomas Huth #endif 7851fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7852fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7853fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 785450728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7855fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7856fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 785750728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7858fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 785950728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7860fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 786150728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7862fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7863fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 786450728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7865fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 786699d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7867fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7868fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 786950728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7870fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7871fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7872fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7873fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7874fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7875fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7876fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7877fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7878fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7879fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7880fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7881fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7882fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7883fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7884fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7885fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7886fcf5ef2aSThomas Huth #endif 7887fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7888efe843d8SDavid Gibson /* 7889efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 7890efe843d8SDavid Gibson * different ISA versions 7891efe843d8SDavid Gibson */ 7892fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7893fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7894c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7895c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7896fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7897fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7898fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7899fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7900a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 790162d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7902fcf5ef2aSThomas Huth #endif 7903fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7904fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7905fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7906fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7907fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7908fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7909fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7910fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7911fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7912fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7913fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7914fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7915fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7916fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7917fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7918fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7919fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7920fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7921fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7922fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7923fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7924fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7925fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7926fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7927fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7928fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7929fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7930fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7931fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7932fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7933fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7934fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7935fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7936fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7937fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7938fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7939fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7940fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7941fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7942fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7943fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7944fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7945fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7946fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7947fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7948fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7949fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7950fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7951fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7952fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7953fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7954fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7955fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7956fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7957fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7958fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7959fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7960fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7961fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7962fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7963fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7964fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7965fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7966fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7967fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7968fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7969fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7970fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7971fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7972fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7973fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7974fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7975fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7976fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7977fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7978fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7979fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7980fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7981fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7982fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7983fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7984fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7985fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7986fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7987fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7988fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7989fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7990fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7991fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7992fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7993fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7994fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7995fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7996fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 79977af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 79987af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7999fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 8000fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 8001fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 8002fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 8003fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 800427a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 8005fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 8006fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 80070c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 80080c8d8c8bSBALATON Zoltan PPC_440_SPEC), 8009fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 8010fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 8011fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 8012fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 8013fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 8014fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8015fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 8016fcf5ef2aSThomas Huth PPC2_ISA300), 8017fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 80185ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 80195ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 80205ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 80215ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 8022fcf5ef2aSThomas Huth #endif 8023fcf5ef2aSThomas Huth 8024fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 8025fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 8026fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 8027fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 8028fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 8029fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8030fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 8031fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 8032fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 8033fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 8034fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 8035fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 8036fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 8037fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 8038fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 80394c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 8040fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 8041fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 8042fcf5ef2aSThomas Huth 8043fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 8044fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 8045fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 8046fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 8047fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 8048fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 8049fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 8050fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8051fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8052fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8053fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8054fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8055fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8056fcf5ef2aSThomas Huth 8057fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8058fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 8059fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 8060fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8061fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 8062fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 8063fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 8064fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 8065fcf5ef2aSThomas Huth 8066fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8067fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8068fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8069fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8070fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8071fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8072fcf5ef2aSThomas Huth 8073fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 8074fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 8075fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8076fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 8077fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 8078fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 8079fcf5ef2aSThomas Huth #endif 8080fcf5ef2aSThomas Huth 8081fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 8082fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 8083fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 8084fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 8085fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 8086fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8087fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 8088fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 8089fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 8090fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 8091fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 8092fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 8093fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 8094fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 8095fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 8096fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 8097fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 8098fcf5ef2aSThomas Huth 8099fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 8100fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 8101fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 8102fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 8103fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 8104fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 8105fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 8106fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 8107fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 8108fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 8109fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 8110fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 8111fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8112fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8113fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8114fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8115fcf5ef2aSThomas Huth #endif 8116fcf5ef2aSThomas Huth 8117fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8118fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8119fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8120fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8121fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8122fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8123fcf5ef2aSThomas Huth PPC_64B) 8124fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8125fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8126fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8127fcf5ef2aSThomas Huth PPC_64B), \ 8128fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8129fcf5ef2aSThomas Huth PPC_64B), \ 8130fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8131fcf5ef2aSThomas Huth PPC_64B) 8132fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8133fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8134fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8135fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8136fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8137fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8138fcf5ef2aSThomas Huth #endif 8139fcf5ef2aSThomas Huth 8140fcf5ef2aSThomas Huth #undef GEN_LDX_E 8141fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8142fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8143fcf5ef2aSThomas Huth 8144fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8145fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8146fcf5ef2aSThomas Huth 8147fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8148fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8149fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8150fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8151fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8152fcf5ef2aSThomas Huth #endif 8153fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8154fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8155fcf5ef2aSThomas Huth 815650728199SRoman Kapl /* External PID based load */ 815750728199SRoman Kapl #undef GEN_LDEPX 815850728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 815950728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 816050728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 816150728199SRoman Kapl 816250728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 816350728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 816450728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 816550728199SRoman Kapl #if defined(TARGET_PPC64) 816650728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 816750728199SRoman Kapl #endif 816850728199SRoman Kapl 8169fcf5ef2aSThomas Huth #undef GEN_ST 8170fcf5ef2aSThomas Huth #undef GEN_STU 8171fcf5ef2aSThomas Huth #undef GEN_STUX 8172fcf5ef2aSThomas Huth #undef GEN_STX_E 8173fcf5ef2aSThomas Huth #undef GEN_STS 8174fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 8175fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8176fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 8177fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 8178fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 8179fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8180fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 81810123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8182fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 8183fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 8184fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 8185fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 8186fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 8187fcf5ef2aSThomas Huth 8188fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 8189fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 8190fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 8191fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8192fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 8193fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 8194fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8195fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8196fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8197fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8198fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8199fcf5ef2aSThomas Huth #endif 8200fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8201fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8202fcf5ef2aSThomas Huth 820350728199SRoman Kapl #undef GEN_STEPX 820450728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 820550728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 820650728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 820750728199SRoman Kapl 820850728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 820950728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 821050728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 821150728199SRoman Kapl #if defined(TARGET_PPC64) 821250728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 821350728199SRoman Kapl #endif 821450728199SRoman Kapl 8215fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8216fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8217fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8218fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8219fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8220fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8221fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8222fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8223fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8224fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8225fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8226fcf5ef2aSThomas Huth 8227fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8228fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8229fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8230fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8231fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8232fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8233fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8234fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8235fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8236fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8237fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8238fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8239fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8240fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8241fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8242fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8243fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8244fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8245fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8246fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8247fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8248fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8249fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8250fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8251fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8252fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8253fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8254fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8255fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8256fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8257fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8258fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8259fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8260fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8261fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8262fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8263fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8264fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8265fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8266fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8267fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8268fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8269fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8270fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8271fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8272fcf5ef2aSThomas Huth 8273fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8274fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8275fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8276fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8277fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8278fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8279fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8280fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8281fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8282fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8283fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8284fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8285fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8286fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8287fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8288fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8289fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8290fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8291fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8292fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8293fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8294fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8295fcf5ef2aSThomas Huth 8296139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8297fcf5ef2aSThomas Huth 8298139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8299fcf5ef2aSThomas Huth 8300139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8301fcf5ef2aSThomas Huth 8302139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8303fcf5ef2aSThomas Huth 8304139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8305fcf5ef2aSThomas Huth }; 8306fcf5ef2aSThomas Huth 83077468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 83087468e2c8SBruno Larsen (billionai) /* Opcode types */ 83097468e2c8SBruno Larsen (billionai) enum { 83107468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 83117468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 83127468e2c8SBruno Larsen (billionai) }; 83137468e2c8SBruno Larsen (billionai) 83147468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 83157468e2c8SBruno Larsen (billionai) 83167468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 83177468e2c8SBruno Larsen (billionai) { 83187468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 83197468e2c8SBruno Larsen (billionai) } 83207468e2c8SBruno Larsen (billionai) 83217468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 83227468e2c8SBruno Larsen (billionai) { 83237468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 83247468e2c8SBruno Larsen (billionai) } 83257468e2c8SBruno Larsen (billionai) 83267468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 83277468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 83287468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 83297468e2c8SBruno Larsen (billionai) { 83307468e2c8SBruno Larsen (billionai) int i; 83317468e2c8SBruno Larsen (billionai) 83327468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 83337468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 83347468e2c8SBruno Larsen (billionai) } 83357468e2c8SBruno Larsen (billionai) } 83367468e2c8SBruno Larsen (billionai) 83377468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 83387468e2c8SBruno Larsen (billionai) { 83397468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 83407468e2c8SBruno Larsen (billionai) 83417468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 83427468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 83437468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 83447468e2c8SBruno Larsen (billionai) 83457468e2c8SBruno Larsen (billionai) return 0; 83467468e2c8SBruno Larsen (billionai) } 83477468e2c8SBruno Larsen (billionai) 83487468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 83497468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 83507468e2c8SBruno Larsen (billionai) { 83517468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 83527468e2c8SBruno Larsen (billionai) return -1; 83537468e2c8SBruno Larsen (billionai) } 83547468e2c8SBruno Larsen (billionai) table[idx] = handler; 83557468e2c8SBruno Larsen (billionai) 83567468e2c8SBruno Larsen (billionai) return 0; 83577468e2c8SBruno Larsen (billionai) } 83587468e2c8SBruno Larsen (billionai) 83597468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 83607468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 83617468e2c8SBruno Larsen (billionai) { 83627468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 83637468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 83647468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 83657468e2c8SBruno Larsen (billionai) return -1; 83667468e2c8SBruno Larsen (billionai) } 83677468e2c8SBruno Larsen (billionai) 83687468e2c8SBruno Larsen (billionai) return 0; 83697468e2c8SBruno Larsen (billionai) } 83707468e2c8SBruno Larsen (billionai) 83717468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 83727468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 83737468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 83747468e2c8SBruno Larsen (billionai) { 83757468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 83767468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 83777468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 83787468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 83797468e2c8SBruno Larsen (billionai) return -1; 83807468e2c8SBruno Larsen (billionai) } 83817468e2c8SBruno Larsen (billionai) } else { 83827468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 83837468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 83847468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 83857468e2c8SBruno Larsen (billionai) return -1; 83867468e2c8SBruno Larsen (billionai) } 83877468e2c8SBruno Larsen (billionai) } 83887468e2c8SBruno Larsen (billionai) if (handler != NULL && 83897468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 83907468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 83917468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 83927468e2c8SBruno Larsen (billionai) return -1; 83937468e2c8SBruno Larsen (billionai) } 83947468e2c8SBruno Larsen (billionai) 83957468e2c8SBruno Larsen (billionai) return 0; 83967468e2c8SBruno Larsen (billionai) } 83977468e2c8SBruno Larsen (billionai) 83987468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 83997468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 84007468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 84017468e2c8SBruno Larsen (billionai) { 84027468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 84037468e2c8SBruno Larsen (billionai) } 84047468e2c8SBruno Larsen (billionai) 84057468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 84067468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 84077468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 84087468e2c8SBruno Larsen (billionai) { 84097468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 84107468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 84117468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 84127468e2c8SBruno Larsen (billionai) return -1; 84137468e2c8SBruno Larsen (billionai) } 84147468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 84157468e2c8SBruno Larsen (billionai) handler) < 0) { 84167468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 84177468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 84187468e2c8SBruno Larsen (billionai) return -1; 84197468e2c8SBruno Larsen (billionai) } 84207468e2c8SBruno Larsen (billionai) 84217468e2c8SBruno Larsen (billionai) return 0; 84227468e2c8SBruno Larsen (billionai) } 84237468e2c8SBruno Larsen (billionai) 84247468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 84257468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 84267468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 84277468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 84287468e2c8SBruno Larsen (billionai) { 84297468e2c8SBruno Larsen (billionai) opc_handler_t **table; 84307468e2c8SBruno Larsen (billionai) 84317468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 84327468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 84337468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 84347468e2c8SBruno Larsen (billionai) return -1; 84357468e2c8SBruno Larsen (billionai) } 84367468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 84377468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 84387468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 84397468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 84407468e2c8SBruno Larsen (billionai) return -1; 84417468e2c8SBruno Larsen (billionai) } 84427468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 84437468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 84447468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 84457468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 84467468e2c8SBruno Larsen (billionai) return -1; 84477468e2c8SBruno Larsen (billionai) } 84487468e2c8SBruno Larsen (billionai) return 0; 84497468e2c8SBruno Larsen (billionai) } 84507468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 84517468e2c8SBruno Larsen (billionai) { 84527468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 84537468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 84547468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 84557468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 84567468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 84577468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 84587468e2c8SBruno Larsen (billionai) return -1; 84597468e2c8SBruno Larsen (billionai) } 84607468e2c8SBruno Larsen (billionai) } else { 84617468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 84627468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 84637468e2c8SBruno Larsen (billionai) return -1; 84647468e2c8SBruno Larsen (billionai) } 84657468e2c8SBruno Larsen (billionai) } 84667468e2c8SBruno Larsen (billionai) } else { 84677468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 84687468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 84697468e2c8SBruno Larsen (billionai) return -1; 84707468e2c8SBruno Larsen (billionai) } 84717468e2c8SBruno Larsen (billionai) } 84727468e2c8SBruno Larsen (billionai) } else { 84737468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 84747468e2c8SBruno Larsen (billionai) return -1; 84757468e2c8SBruno Larsen (billionai) } 84767468e2c8SBruno Larsen (billionai) } 84777468e2c8SBruno Larsen (billionai) 84787468e2c8SBruno Larsen (billionai) return 0; 84797468e2c8SBruno Larsen (billionai) } 84807468e2c8SBruno Larsen (billionai) 84817468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 84827468e2c8SBruno Larsen (billionai) { 84837468e2c8SBruno Larsen (billionai) int i, count, tmp; 84847468e2c8SBruno Larsen (billionai) 84857468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 84867468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 84877468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 84887468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 84897468e2c8SBruno Larsen (billionai) } 84907468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 84917468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 84927468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 84937468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 84947468e2c8SBruno Larsen (billionai) if (tmp == 0) { 84957468e2c8SBruno Larsen (billionai) free(table[i]); 84967468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 84977468e2c8SBruno Larsen (billionai) } else { 84987468e2c8SBruno Larsen (billionai) count++; 84997468e2c8SBruno Larsen (billionai) } 85007468e2c8SBruno Larsen (billionai) } else { 85017468e2c8SBruno Larsen (billionai) count++; 85027468e2c8SBruno Larsen (billionai) } 85037468e2c8SBruno Larsen (billionai) } 85047468e2c8SBruno Larsen (billionai) } 85057468e2c8SBruno Larsen (billionai) 85067468e2c8SBruno Larsen (billionai) return count; 85077468e2c8SBruno Larsen (billionai) } 85087468e2c8SBruno Larsen (billionai) 85097468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 85107468e2c8SBruno Larsen (billionai) { 85117468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 85127468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 85137468e2c8SBruno Larsen (billionai) } 85147468e2c8SBruno Larsen (billionai) } 85157468e2c8SBruno Larsen (billionai) 85167468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 85177468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 85187468e2c8SBruno Larsen (billionai) { 85197468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 85207468e2c8SBruno Larsen (billionai) opcode_t *opc; 85217468e2c8SBruno Larsen (billionai) 85227468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 85237468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 85247468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 85257468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 85267468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 85277468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 85287468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 85297468e2c8SBruno Larsen (billionai) opc->opc3); 85307468e2c8SBruno Larsen (billionai) return; 85317468e2c8SBruno Larsen (billionai) } 85327468e2c8SBruno Larsen (billionai) } 85337468e2c8SBruno Larsen (billionai) } 85347468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 85357468e2c8SBruno Larsen (billionai) fflush(stdout); 85367468e2c8SBruno Larsen (billionai) fflush(stderr); 85377468e2c8SBruno Larsen (billionai) } 85387468e2c8SBruno Larsen (billionai) 85397468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 85407468e2c8SBruno Larsen (billionai) { 85417468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 85427468e2c8SBruno Larsen (billionai) int i, j, k; 85437468e2c8SBruno Larsen (billionai) 85447468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 85457468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 85467468e2c8SBruno Larsen (billionai) continue; 85477468e2c8SBruno Larsen (billionai) } 85487468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 85497468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 85507468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 85517468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 85527468e2c8SBruno Larsen (billionai) continue; 85537468e2c8SBruno Larsen (billionai) } 85547468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 85557468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 85567468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 85577468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 85587468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 85597468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 85607468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 85617468e2c8SBruno Larsen (billionai) } 85627468e2c8SBruno Larsen (billionai) } 85637468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 85647468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 85657468e2c8SBruno Larsen (billionai) } 85667468e2c8SBruno Larsen (billionai) } 85677468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 85687468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 85697468e2c8SBruno Larsen (billionai) } 85707468e2c8SBruno Larsen (billionai) } 85717468e2c8SBruno Larsen (billionai) } 85727468e2c8SBruno Larsen (billionai) 85737468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 85747468e2c8SBruno Larsen (billionai) { 85757468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 85767468e2c8SBruno Larsen (billionai) 85777468e2c8SBruno Larsen (billionai) /* 85787468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 85797468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 85807468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 85817468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 85827468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 85837468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 85847468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 85857468e2c8SBruno Larsen (billionai) */ 85867468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 85877468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 85887468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 85897468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 85907468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 85917468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 85927468e2c8SBruno Larsen (billionai) } 85937468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 85947468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 85957468e2c8SBruno Larsen (billionai) return 0; 85967468e2c8SBruno Larsen (billionai) } 85977468e2c8SBruno Larsen (billionai) 8598624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 8599624cb07fSRichard Henderson { 8600624cb07fSRichard Henderson opc_handler_t **table, *handler; 8601624cb07fSRichard Henderson uint32_t inval; 8602624cb07fSRichard Henderson 8603624cb07fSRichard Henderson ctx->opcode = insn; 8604624cb07fSRichard Henderson 8605624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8606624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8607624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 8608624cb07fSRichard Henderson 8609624cb07fSRichard Henderson table = cpu->opcodes; 8610624cb07fSRichard Henderson handler = table[opc1(insn)]; 8611624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8612624cb07fSRichard Henderson table = ind_table(handler); 8613624cb07fSRichard Henderson handler = table[opc2(insn)]; 8614624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8615624cb07fSRichard Henderson table = ind_table(handler); 8616624cb07fSRichard Henderson handler = table[opc3(insn)]; 8617624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8618624cb07fSRichard Henderson table = ind_table(handler); 8619624cb07fSRichard Henderson handler = table[opc4(insn)]; 8620624cb07fSRichard Henderson } 8621624cb07fSRichard Henderson } 8622624cb07fSRichard Henderson } 8623624cb07fSRichard Henderson 8624624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 8625624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 8626624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8627624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8628624cb07fSRichard Henderson TARGET_FMT_lx "\n", 8629624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8630624cb07fSRichard Henderson insn, ctx->cia); 8631624cb07fSRichard Henderson return false; 8632624cb07fSRichard Henderson } 8633624cb07fSRichard Henderson 8634624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8635624cb07fSRichard Henderson && Rc(insn))) { 8636624cb07fSRichard Henderson inval = handler->inval2; 8637624cb07fSRichard Henderson } else { 8638624cb07fSRichard Henderson inval = handler->inval1; 8639624cb07fSRichard Henderson } 8640624cb07fSRichard Henderson 8641624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 8642624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8643624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8644624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 8645624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8646624cb07fSRichard Henderson insn, ctx->cia); 8647624cb07fSRichard Henderson return false; 8648624cb07fSRichard Henderson } 8649624cb07fSRichard Henderson 8650624cb07fSRichard Henderson handler->handler(ctx); 8651624cb07fSRichard Henderson return true; 8652624cb07fSRichard Henderson } 8653624cb07fSRichard Henderson 8654b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 8655fcf5ef2aSThomas Huth { 8656b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 86579c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 86582df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 8659fcf5ef2aSThomas Huth 8660b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 86612df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 8662d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 86632df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 86642df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 8665b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 8666b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 8667b0c2d521SEmilio G. Cota ctx->access_type = -1; 8668d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 86692df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 8670b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 86710e3bf489SRoman Kapl ctx->flags = env->flags; 8672fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 86732df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 8674b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 8675fcf5ef2aSThomas Huth #endif 8676e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 8677e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 8678d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 8679fcf5ef2aSThomas Huth 86802df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 86812df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 86822df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 86832df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 86842df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 8685f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 86862df4fe7aSRichard Henderson 8687b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 86882df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 86892df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 8690efe843d8SDavid Gibson } 86912df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 8692b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 8693efe843d8SDavid Gibson } 8694b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 8695b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 8696fcf5ef2aSThomas Huth } 8697b0c2d521SEmilio G. Cota 869813b45575SRichard Henderson if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) { 869913b45575SRichard Henderson ctx->base.max_insns = 1; 8700fcf5ef2aSThomas Huth } 870113b45575SRichard Henderson } 8702fcf5ef2aSThomas Huth 8703b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 8704b0c2d521SEmilio G. Cota { 8705b0c2d521SEmilio G. Cota } 8706fcf5ef2aSThomas Huth 8707b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 8708b0c2d521SEmilio G. Cota { 8709b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 8710b0c2d521SEmilio G. Cota } 8711b0c2d521SEmilio G. Cota 8712b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 8713b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 8714b0c2d521SEmilio G. Cota { 8715b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8716b0c2d521SEmilio G. Cota 87172736fc61SRichard Henderson gen_update_nip(ctx, ctx->base.pc_next); 8718b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 8719efe843d8SDavid Gibson /* 8720efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 8721efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 8722efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 8723efe843d8SDavid Gibson * setting tb->size below does the right thing. 8724efe843d8SDavid Gibson */ 8725b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 8726b0c2d521SEmilio G. Cota return true; 8727fcf5ef2aSThomas Huth } 8728fcf5ef2aSThomas Huth 872999082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 873099082815SRichard Henderson { 873199082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 873299082815SRichard Henderson return opc1(insn) == 1; 873399082815SRichard Henderson } 873499082815SRichard Henderson 8735b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 8736b0c2d521SEmilio G. Cota { 8737b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 873828876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 8739b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 874099082815SRichard Henderson target_ulong pc; 8741624cb07fSRichard Henderson uint32_t insn; 8742624cb07fSRichard Henderson bool ok; 8743b0c2d521SEmilio G. Cota 8744fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 8745fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 8746b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 8747b0c2d521SEmilio G. Cota 874899082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 874999082815SRichard Henderson insn = translator_ldl_swap(env, pc, need_byteswap(ctx)); 875099082815SRichard Henderson ctx->base.pc_next = pc += 4; 8751fcf5ef2aSThomas Huth 875299082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 875399082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 875499082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 875599082815SRichard Henderson } else if ((pc & 63) == 0) { 875699082815SRichard Henderson /* 875799082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 875899082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 875999082815SRichard Henderson * 64-byte address boundary (system alignment error). 876099082815SRichard Henderson */ 876199082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 876299082815SRichard Henderson ok = true; 876399082815SRichard Henderson } else { 876499082815SRichard Henderson uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx)); 876599082815SRichard Henderson ctx->base.pc_next = pc += 4; 876699082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 876799082815SRichard Henderson } 8768624cb07fSRichard Henderson if (!ok) { 8769624cb07fSRichard Henderson gen_invalid(ctx); 8770fcf5ef2aSThomas Huth } 8771624cb07fSRichard Henderson 877264a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 877399082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 877464a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 877564a0f644SRichard Henderson } 877664a0f644SRichard Henderson 877751eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 8778fcf5ef2aSThomas Huth } 8779b0c2d521SEmilio G. Cota 8780b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 8781b0c2d521SEmilio G. Cota { 8782b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8783a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 8784a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 878513b45575SRichard Henderson int sse; 8786b0c2d521SEmilio G. Cota 8787a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 8788a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 87893d8a5b69SRichard Henderson return; 87903d8a5b69SRichard Henderson } 87913d8a5b69SRichard Henderson 8792a9b5b3d0SRichard Henderson /* Honor single stepping. */ 879313b45575SRichard Henderson sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP); 879413b45575SRichard Henderson if (unlikely(sse)) { 8795a9b5b3d0SRichard Henderson switch (is_jmp) { 8796a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8797a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8798a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8799a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8800a9b5b3d0SRichard Henderson break; 8801a9b5b3d0SRichard Henderson case DISAS_EXIT: 8802a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8803a9b5b3d0SRichard Henderson break; 8804a9b5b3d0SRichard Henderson default: 8805a9b5b3d0SRichard Henderson g_assert_not_reached(); 8806fcf5ef2aSThomas Huth } 880713b45575SRichard Henderson 880813b45575SRichard Henderson if (sse & GDBSTUB_SINGLE_STEP) { 8809a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 8810a9b5b3d0SRichard Henderson return; 8811a9b5b3d0SRichard Henderson } 881213b45575SRichard Henderson /* else CPU_SINGLE_STEP... */ 881313b45575SRichard Henderson if (nip <= 0x100 || nip > 0xf00) { 881413b45575SRichard Henderson gen_exception(ctx, gen_prep_dbgex(ctx)); 881513b45575SRichard Henderson return; 881613b45575SRichard Henderson } 881713b45575SRichard Henderson } 8818a9b5b3d0SRichard Henderson 8819a9b5b3d0SRichard Henderson switch (is_jmp) { 8820a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8821a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 8822a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 8823a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8824a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 8825a9b5b3d0SRichard Henderson break; 8826a9b5b3d0SRichard Henderson } 8827a9b5b3d0SRichard Henderson /* fall through */ 8828a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8829a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8830a9b5b3d0SRichard Henderson /* fall through */ 8831a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8832a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 8833a9b5b3d0SRichard Henderson break; 8834a9b5b3d0SRichard Henderson 8835a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8836a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8837a9b5b3d0SRichard Henderson /* fall through */ 8838a9b5b3d0SRichard Henderson case DISAS_EXIT: 883907ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 8840a9b5b3d0SRichard Henderson break; 8841a9b5b3d0SRichard Henderson 8842a9b5b3d0SRichard Henderson default: 8843a9b5b3d0SRichard Henderson g_assert_not_reached(); 8844fcf5ef2aSThomas Huth } 8845fcf5ef2aSThomas Huth } 8846b0c2d521SEmilio G. Cota 8847b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8848b0c2d521SEmilio G. Cota { 8849b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8850b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8851b0c2d521SEmilio G. Cota } 8852b0c2d521SEmilio G. Cota 8853b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 8854b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 8855b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 8856b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 8857b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 8858b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 8859b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 8860b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 8861b0c2d521SEmilio G. Cota }; 8862b0c2d521SEmilio G. Cota 88638b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8864b0c2d521SEmilio G. Cota { 8865b0c2d521SEmilio G. Cota DisasContext ctx; 8866b0c2d521SEmilio G. Cota 88678b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8868fcf5ef2aSThomas Huth } 8869fcf5ef2aSThomas Huth 8870fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8871fcf5ef2aSThomas Huth target_ulong *data) 8872fcf5ef2aSThomas Huth { 8873fcf5ef2aSThomas Huth env->nip = data[0]; 8874fcf5ef2aSThomas Huth } 8875